SCHOOL OF ELECTRONICS ENGINEERING

ECE 2002 - ANALOG ELECTRONIC CIRCUITS – Lab Manual

FS 2017-18

Faculty Name: Dr. B. Bindu

List of Experiments:
Design of the Amplifiers for the given frequency Specifications -
BJT Single Stage Amplifier
MOS Single Stage Amplifier
Design of Feedback Amplifiers for the given Specifications -
Shunt Series Feedback Amplifier
Design of Oscillators for the given Specifications - RC Phase shift
Oscillators
BJT Class B Power Amplifiers
Single tuned voltage amplifier
Design of the Amplifiers for the given frequency Specifications -
BJT Single Stage Amplifier
MOS Multi-Stage Amplifiers – Cascade Amplifier
Series Shunt Feedback Amplifier
Design of Oscillators for the given Specifications - Wien bridge
Design of Power Amplifiers for the given Specifications
MOSFET Class A
Cascode amplifier
HARDWARE EXPERIMENTS
 HARDWARE EXPERIMENT 1

Experiment:

Single Stage BJT Amplifier

Aim :

To design a single stage CE amplifier using BJT and to analyze its frequency response.

Theory:

CE amplifier is widely used in audio frequency applications and in radio and TV receivers.

Base current controls the collector current. Smaller base current results in a larger collector
current. The emitter base junction is forward biased and the collector base is reverse biased.
Rb1,Rb2 provides voltage divider biasing which provides independence against the variations
in β. The Coupling capacitors Cc couples the ac signal to the input of the amplifier and blocks
dc. It also isolates the input signal source and the voltage divider circuit.Xc1 < Rin /10. Where
Rin=R1||R2|| hfere and re = 25mV / I E is the internal emitter resistance of the transistor and
25 mV is the temperature equivalent voltage. The bypass capacitor bypasses the signal
currents to the ground. XCE < RE /10. BC107 is selected with hFE of 100 to 500 depending on
the requirement of Av. For distortion-less output the operating point should be in the middle
of the load line so VcEQ= 50% VCC. . IC for BC 107 is 2 mA. RE provides current series
feedback.

It stabilizes the operating point against temperature variations. 10% of Vcc is fixed across RE.
40% OF Vcc flows across Rc

DESIGN:

DC BIASING CONDITIONS

Consider Vcc = 12V , I c= 2mA (BC 107)

VRC= 40% of VCC = 4.8 V

VRE= 10% of VCC = 1.2 V

VCE= 50% of VCC = 6 V

Design of RE

RE= VRE/ IE = VRE/ IC = 1.2/ 2m = 0.6K=600 ohm

Design of Rc

RC= VRC/ IC = 2.4K ohm

Design of Voltage Divider R1 and R2

hfe (min) = 100

IB=IC/ hfe (min) = 0.02m = 20µ A

Assume that 10 IB flows through R1 and 9IB flows through R2.

VR2= VBE+V RE = 0.7+ 1.2=1.9V

R2= VR2/ 9 IB= 1.9/(9* 20 µ A) = 10K

VCC-VR2 = V R1

12- 1.9 = VR1

10.1= VR1

R1= VR1/ 10 IB= 10.1/(10* 20u) = 10.1/200 µ A = 50K

XCE ≤ RE/ 10

CE ≥ 1 2 *  *100 * 68 = 23 µF ≈ 22 µF

Circuit Diagram:

Procedure:

1. Check the dc bias conditions by removing the input signal and the capacitors.
2. Connect the capacitors and apply a 100mV peak to peak sinusoidal signal from the
function generator to the input circuit. Observe the input and output waveforms on the CRO.
3. Keeping the input voltage constant vary the frequency of the input signal from 0 to 1
MHz. Measure the output voltage.
4. Using the input voltage and the output voltage calculate the gain in dB plot the frequency
response characteristics with gain in dB on the y-axis and log f on the x-axis. Mark log fL and
fH corresponding to 1/√2 of the maximum gain.
5. Calculate the bandwidth BW= fH- fL
6. Repeat the same procedure by removing CE.

Table:

Vin=100mV

Sl. No Frequency (in Hz) Output voltage Av=20

(Vout in volt) log10(Vout/Vin)
1 590 2 26.02
2 952 2.2 26.848
3 1560 2.4 27.604
4 2567 2.4 27.604
5 3091 2.4 27.604
6 4522 2.5 27.958
7 5435 2.5 27.958
8 6028 2.5 27.958
9 10730 2.5 27.958
10 334600 2.5 27.958
11 436500 2.5 27.958
12 495400 2.4 27.604
13 620900 2 24.02
Graph:

Frequency Response
Gain(dB)

Frequency (Hz)

Inference:

Bandwidth increases and gain decreases in the absence of CE.

 HARDWARE EXPERIMENT 2

Title: Single Stage MOSFET Amplifier

AIM:

To obtain the gain of MOSFET amplifier and analyze its frequency response
characteristics.

APPARATUS REQUIRED:

1. MOSFET-IFT150
2. Capacitors-0.1 µf,10 µF,100 µF
3. Resistors-470Kohms,1.5Kohms,220Kohms,100ohms,1Kohm
4. Power supply
5. Breadboard
6. Function Generator

THEORY:

The Metal oxide semiconductor field effect transistor is a type of transistor used for
amplifying or switching electronic Signals. MOSFET is a combination of the metal,
dielectric and a conductor. It operates in the Enhancement Mode and Depletion Mode.
The width of the channel depends on the gate voltage applied. If the drain current is
enhanced with respect to the gate it is referred to as Enhancement mode MOSFET
and if the drain current decreases with respect to the gate potential it operates in the
Depletion Mode. The conductive region or path is called “the channel”. We can make
this conductive channel wider or smaller by applying a suitable gate potential. The
main advantage of a MOSFET over a regular transistor is that it requires very little
amount of current to turn on, while delivering a much higher current to load. An
electric field induced around the gate terminal by the application of this gate voltage
affects the electrical characteristics of the channel, thus the name field-effect
transistor.
 CIRCUIT DIAGRAM:

PROCEDURE:

1. Check the dc bias conditions by removing the input signal and the capacitors.

2. Connect the capacitors and apply a 100mV peak to peak sinusoidal signal from the
function generator to the input circuit. Observe the input and output waveforms on the CRO.

3. Keeping the input voltage constant vary the frequency of the input signal from 10 to
2000Hz. Measure the output voltage.

4. Using the input voltage and the output voltage calculate the gain in dB plot the frequency
response characteristics with gain in dB on the y-axis and log f on the x-axis. Mark log fL and
fH corresponding to 1/√2 of the maximum gain.

5. Calculate the bandwidth BW= fH- fL

Table: Vin=100mV

Sl. No Frequency (in Hz) Output voltage (Vout in Gain Gain in dB

volt) VO/VIN Av=20 log10(Vout/Vin)
1 100 2.7 27 28.62
2 250 2.8 28 28.94
3 400 2.85 28.5 29.09
4 650 3 30 29.54
5 900 3 30 29.54
6 1500 3 30 29.54
7 1800 2.9 29 29.24
8 2000 2.5 25 29.05

Graph:

Frequency Response
Gain (dB)

Frequency ( Hz)

Inference:

Bandwidth increases and gain decreases in the absence of CE.

 HARDWARE EXPERIMENT 3

Title: Voltage Shunt feedback amplifier

Circuit Diagram:

Theory :

In voltage shunt feedback amplifier used CE amplifier with negative feedback. The use of
negative feedback is a part of the output voltage fed back to input. The advantage of voltage
shunt feedback is increases the bandwidth and reduces the gain.

Table:

Vin=100mV

Sl. No Frequency (in Hz) Output voltage Av=20

(Vout in mv) log10(Vout/Vin)
1 47.2 50 -6.02
2 500 75 -2.498
3 1K 75 -2.498
4 10K 75 -2.498
5 100K 75 -2.498
6 500K 60 -4.436
7 1000K 40 -7.958
8 5000K 5 -26.02
Frequency Response Graph:

f(in Hz)
Gain (in DB)

Inference: The readings are noted down as per the table and graph is drawn. It is shown that
the bandwidth is more than that without feedback.
 HARDWARE EXPERIMENT 4

Title: RC Phase shift oscillator to generate 1K Hz sine wave signal

Circuit Diagram:

Theory :

RC phase shift oscillator involves three network such as CE amplifier, RC network

(frequency selective network) and feedback network. CE amplifier circuit amplify the week
signal to strong signal , the amplified output is in out of phase, RC network (frequency
selective network )produces the 180 degree in-phase signal and feedback network feed a part
of output signal into the base. Here the feedback is positive.

Design

Vcc = 12V , I c= 2mA (BC 107)

VRC= 40% of VCC = 4.8 V

VRE= 10% of VCC = 1.2 V

VCE= 50% of VCC = 6 V

RE= VRE/ IE = VRE/ IC = 1.2/ 2m = 0.6K=600 ohm

RC= VRC/ IC = 2.4K ohm

hfe (min) = 100

IB=IC/ hfe (min)

= 0.02m = 20u A

VR2= VBE+V RE

= 0.7+ 1.2

1.9V

VCC-VR2 = V R1

12- 1.9 = VR1

10.1= VR1

R1= VR1/ 10 IB= 10.1/(10* 20u) = 10.1/200u = 50K

R2= VR2/ 9 IB= 1.9/(9* 20u) = 10K

XCE ≤ RE/ 10

CE ≥ 1 2 *  *100 * 68 = 23u ≈ 22u

Frequency selective network for 1K Hz = f

For f=1K Hz

R 
f  1 / 2RC 6  4 C 
 R 

Put

R= 4.7K ohm

C= 0.01 u F
tan 1 RC = 60 

tan 1 (2 * 3.14 *1k * 4.7k * 0.01u ) = 60 

Inference: Generate the 1K Hz sine wave with an amplitude of 10VP-P and its phase is
in.
 HARDWARE EXPERIMENT 5

Experiment : Class B Complementary Symmetry -Power amplifier

Aim:

To study cross over distortion in Class B power amplifier.

Theory:

In Class B the Q point is located at the cut off so collector current flows for 1800 of the input
cycle. Complementary symmetry uses NPN and PNP transistor with identical characteristics.
The transistors are connected as emitter followers with emitters connected. During the
positive cycle base of emitter is positive and SL 100 conducts whereas SK100 remains
OFF. During the negative cycle SL 100 is OFF and SK100 conducts. Output current
flows in the opposite direction. But voltage flows in the same direction as the input voltage.
In this the transistor conducts after 0.6 V so output voltage distorts near zero crossing . This
is called cross over distortion. This can be overcome by applying slight base bias. Phase
splitting is obtained without using a transformer.

Circuit Diagram:
Procedure:

The frequency of the input signal is kept at 1 KHz. An input signal of 3 V is given from the
function generator. The output waveform is observed on the CRO with cross over distortion.

Output waveform:

Input Voltage:

Amplitude : 3VP-P

Frequency : 1K Hz

Output Voltage:

Amplitude : 1.8VP-P

Frequency : 1K Hz

Inference:

Phase splitting is obtained without transformer. Cross over distortion can be

eliminated using base bias (diodes).
 HARDWARE EXPERIMENT 6

SINGLE TUNED VOLTAGE AMPLIFIER

AIM: To obtain the frequency response of a tuned voltage amplifier and to obtain the band width.
APPARATUS REQUIRED:
1. Transistor SL100 1
2. Resistors 1K, 22 K, 1.8K, 470 Each 1
3. Capacitors 10F, 33F Each 1
CIRCUIT DIAGRAM:

MODEL GRAPH:

PROCEDURE:
1. Connect the circuit as shown in the figure.
2. Apply a 4 mV sinusoidal signal at a frequency of 1 KHz and note down the O/P.
3. Now vary the frequency of the input signal upto 1MHz in suitable steps by keeping
the input voltage constant.
4. Note down the O/P voltage V0.
5. Tabulate the readings.
6. Draw gain Vs frequency graph on semi log sheet and determine the band width.

TABULAR FORM:
Vi = 5mV

RESULT:

The frequency response of the amplifier is plotted and the bandwidth is measured.
SOFTWARE EXPERIMENTS
 Software Experiment 1
Single Stage BJT amplifier
Aim:

To plot the frequency response curve of a single stage BJT amplifier with and without
feedback

Software Required:

LTSpice

Circuit Diagram:
Model Graph:

Procedure:

1. Construct the circuit as per the circuit diagram of the amplifier using LTSpice

2. Using transient analysis measure the input and output waveform

3. Perform AC analysis to find the frequency response characteristics of the amplifier

4. Repeat the same procedure for the amplifier with feedback

5. Find the gain and bandwidth of the amplifier with and without feedback

Result:

Gain of the amplifier with feedback =

Bandwidth of the amplifier with feedback =

Gain of the amplifier without feedback =

Bandwidth of the amplifier without feedback =

 Software Experiment 2

MOSFET Cascade Amplifier

--------------------------------------------------------------------------------------------------

Aim:

To simulate the amplification of the signal in two stages with two stage RC coupled amplifier
using LTspice.

Components Required:

 PC
 LT Spice Software
Circuit Diagram for MOSFET Cascade Amplifier:

Output for Cascade Amplifier

Frequency Response

Procedure:

1. Run the LT Spice and create a new schematic

2. Click on ‘Component’ and place the required components
3. Change the values of the components according to the requirement
4. Place the ‘Ground’ button
5. Connect all the components by wires
6. Save the schematic and run it
7. Change the range of the axes

Result:

Thus the signal is amplified in two stages using two stage RC coupled amplifier.
 Software Experiment 3
Design and simulation verification of series shunt amplifier circuit using BJT.

Circuit:

Simulation circuit and result for transient analysis:

Calculation:

Assume, β1=β2=100 and Vbe=0.7v.

Simulation circuit for frequency response:

Inferences:
 Software Experiment 4

Design and simulation verification of wien bridge oscillator using

BJT.

It is one of the most popular types of oscillator used in audio and sub-audio frequency ranges (20
Hz – 20 kHz). This type of oscillator is simple in design, compact in size, and remarkably stable
in its frequency output. Furthermore, its output is relatively free from distortion and its frequency
can be varied easily. However, the maximum frequency output of a typical Wien bridge oscillator
is only about 1 MHz. This is also, in fact, a phase-shift oscillator. It employs two transistors, each
producing a phase shift of 180°, and thus producing a total phase-shift of 360° or 0°.

The circuit diagram of Wien bridge oscillator is shown in the figure below.

It is essentially a two-stage amplifier with an R-C bridge circuit. R-C bridge circuit (Wien Bridge)
is a lead-lag network. The phase’-shift across the network lags with increasing frequency and
leads with decreasing frequency. By adding Wien-bridge feedback network, the oscillator
becomes sensitive to a signal of only one particular frequency. This particular frequency is that at
which Wien bridge is balanced and for which the phase shift is 0°.If the Wien-bridge feedback
network is not employed and output of transistor Q2 is feedback to transistor Q1 for providing
regeneration required for producing oscillations, the transistor Q1 will amplify signals over a wide
range of frequencies and thus direct coupling would result in poor frequency stability. Thus by
employing Wien-bridge feedback network frequency stability is increased.
In the bridge circuit R1 in series with C1, R3, R4 and R2 in parallel with C2 form the four arms.
This bridge circuit can be used as feedback network for an oscillator, provided that the phase
shift through the amplifier is zero. This requisite condition is achieved by using a two stage
amplifier, as illustrated in the figure. In this arrangement the output of the second stage is
supplied back to the feedback network and the voltage across the parallel combination C2 R2 is
fed to the input of the first stage. Transistor Q1 serves as an oscillator and amplifier whereas the
transistor Q2 as an inverter to cause a phase shift of 180°. The circuit uses positive and negative
feedbacks. The positive feedback is through R1 C1 R2, C2 to transistor Q1 and negative feedback
is through the voltage divider to the input of transistor Q1. Resistors R3 and R4 are used to
stabilize the amplitude of the output.
The two transistors Q1 and Q2 thus cause a total phase shift of 360° and ensure proper positive
feedback. The negative feedback is provided in the circuit to ensure constant output over a range
of frequencies. This is achieved by taking resistor R4 in the form of a temperature sensitive lamp,
whose resistance increases with the increase in current. In case the amplitude of the output
tends to increase, more current would provide more negative feedback. Thus the output would
regain its original value. A reverse action would take place in case the output tends to fall.
The amplifier voltage gain, A R3 + R4 / R4 = R3 / R4 + 1 = 3
Since R3 = 2 R4
The above corresponds with the feedback network attenuation of 1/3. Thus, in this case, voltage
gain A, must be equal to or greater than 3, to sustain oscillations.

To have a voltage gain of 3 is not difficult. On the other hand to have a gain as low as 3 may be
difficult. For this reason also negative feedback is essential.

Operation:

The circuit is set in oscillation by any random change in base current of transistor Q 1 that may be
due to noise inherent in the transistor or variation in voltage of dc supply. This variation in base
current is amplified in collector circuit of transistor Q1 but with a phase-shift of 180°. the output of
transistor Q1 is fed to the base of second transistor Q2 through capacitor C4. Now a still further
amplified and twice phase-reversed signal appears at the collector of the transistor Q2. Having
been inverted twice, the output signal will be in phase with the signal input to the base of
transistor Q1 A part of the output signal at transistor Q2 is feedback to the input points of the
bridge circuit (point A-C). A part of this feedback signal is applied to emitter resistor R4 where it
produces degenerative effect (or negative feedback). Similarly, a part of the feedback signal is
applied across the base-bias resistor R2 where it produces regenerative effect (or positive
feedback). At the rated frequency, effect of regeneration is made slightly more than that of
degeneration so as to obtain sustained oscillations.
The continuous frequency variation in this oscillator can be had by varying the two capacitors
C1and C2 simultaneously. These capacitors are variable air-gang capacitors. We can change the
frequency range of the oscillator by switching into the circuit different values of resistors R 1 and
R2.
Simulated circuit in LT_Spice:

OUTPUT Result:
 Software Experiment 5

MOSFET Class-A power Amplifier

--------------------------------------------------------------------------------------------------

Aim:

To simulate the MOSFET power amplifier in class-A mode of operation using LTspice.

Components Required:

 PC
 LT Spice Software

Circuit Diagram for MOSFET Class-A power Amplifier:

Output for Class-A power Amplifier

Frequency Response

Procedure:

1. Run the LT Spice and create a new schematic

2. Click on ‘Component’ and place the required components
3. Change the values of the components according to the requirement
4. Place the ‘Ground’ button
5. Connect all the components by wires
6. Save the schematic and run it
7. Change the range of the axes
Efficiency

The efficiency of an amplifier represents the amount of ac power delivered (transferred)

from the dc source. The efficiency of the amplifier is calculated using

𝑃𝑜(𝑎𝑐)
%ɳ = 𝑃𝑖(𝑑𝑐)
× 100% (1)
Maximum Efficiency

For the class A series-fed amplifier, the maximum efficiency can be determined using the
maximum voltage and current swings. For the voltage swing it is

Maximum VCE(p − p)=VCC (2)

For the current swing it is

Vcc
Maximum Ic (p − p) = Rc
(3)

The ac power delivered to the load may be expressed using

𝑉𝐶𝐸 (𝑝−𝑝)𝐼𝐶 (𝑝−𝑝)

𝑃𝑜 (𝑎𝑐) = 2
(4)

Substituting (2) and (3) in (4), we get

2
𝑉𝐶𝐶
Maximum 𝑃𝑜 (𝑎𝑐) = (5)
8𝑅𝐶

The maximum power input can be calculated using the dc bias current set to one-half the maximum
value
2
𝑉𝐶𝐶 ⁄𝑅𝐶 𝑉𝐶𝐶
Maximum Pi(dc) = VCC(maximum IC) =𝑉𝐶𝐶 = (6)
2 2𝑅𝐶

Substituting (5) and (6) in (1), we get

𝑃𝑜(𝑎𝑐)
Maximum %ɳ = 𝑃𝑖(𝑑𝑐)
× 100%

𝑉 2 ⁄8𝑅
𝐶
= 𝑉𝐶𝐶
2 ⁄2𝑅 × 100%
𝐶𝐶 𝐶

=25%

The maximum efficiency of a class A series-fed amplifier is seen to be 25%. Since this maximum
efficiency will occur only for ideal conditions of both voltage and current swing, most series-fed
circuits will provide efficiencies of much less than 25%

Result:

Thus the MOSFET power amplifier in class-A mode of operation is simulated using LTspice
Software Experiment 6