A B C D E

1 1

Compal confidential 2

Schematics Document
Mobile Merom uFCPGA with Satna Rosa Platform

3 3

2007-01-08
REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 1 of 40
A B C D E
 A B C D E

Compal confidential
File Name : LA-3732P
ZZZ1
Spartan 1.0 (Merom +Crestline+ICH8)
PCB
1 1
Fan Control Mobile Yonah/Merom
page 4
uFCPGA-478 CPU Thermal Sensor Clock Generator
Socket P ADM1032AR ICS9LPRS355
page 4,5,6 page 4 page 15

FSB
H_A#(3..31) 533/667/800MHz H_D#(0..63)

CRT/TV-OUT DDR2-SO-DIMM X2
page 16 DDR2 -400/533/667 BANK 0, 1, 2, 3
NB Crestline page 13,14

LVDS Conn Dual Channel

page 17 page 7,8,9,10,11,12

2 2

DMI
USB2.0
USB Conn
page 27

PCI BUS
MODEM AMOM
AC-LINK/Azalia
Audio Conexant CX20548
PCI-E BUS SB ICH8 CX20549-12
page 25

page 24
Realtac
RTL8100CL AMP & Audio Jack
LED page 18,19,20,21 SATA TPA6017A2 page 26
page 23
page 28 SATA HDD Connector
3 3
page 22
Mini-Card
RTC CKT. RJ45/11 CONN WLAN PATA Master
IDE ODD Connector
page 23 page 22
page 19 page 22

LPC BUS

SPI SPI ROM

Power On/Off CKT. ENE KB926 25LF080A
page 30 page 29
page 28

Touch Pad CONN. Int.KBD

4 DC/DC Interface CKT. page 28 page 30 4

page 31

Power Circuit DC/DC

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

Page 32,33,34,35,36,37,38 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 2 of 40
A B C D E
 5 4 3 2 1

Voltage Rails
+5VS
+3VS
power
plane +1.5VS
+5VALW
+B +1.8V +1.25VS
+3VALW
D
+0.9V D
State
+VCCP
+CPU_CORE Symbol Note :

S0
: means Digital Ground
O O O O
S1
O O O O : means Analog Ground
S3
O O O X @ : means just reserve , no build
DEBUG@ : means just reserve for debug.
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X
S5 S4/AC & Battery
don't exist X X X X
C C

External PCI Devices

DEVICE IDSEL # REQ/GNT # PIRQ

L AN AD22 0 A

B
SMBUS Control Table B

THERMAL
I2C / SMBUS ADDRESSING SERIAL SENSOR
SOURCE INVERTER BATT EEPROM (CPU) SODIMM CLK CHIP MINI CARD LCD
ADM1032
DEVICE HEX ADDRESS SMB_EC_CK1
SMB_EC_DA1
KB925 X V V X X X X X
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100 SMB_EC_CK2
SMB_EC_DA2
KB925 X X X V X X X X
CLOCK GENERATOR (EXT.) D2 11010010
SMB_CK_CLK1
SMB_CK_DAT1 ICH8 X X X X V V V X
LCD_CLK
LCD_DAT Crestline
X X X X X X X V

A BOM: 43XXXXXX A

Jump-Short: PJP?
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 3 of 40
5 4 3 2 1
 5 4 3 2 1

XDP Connector layout note: Change R7 to 649 ohm if using XTP to ITP adapter +3VS

R1
XDP_DBRESET#_R 1 2 @ 1K_0402_5%
+VCCP

JP1 XDP_TDI R2 1 2 54.9_0402_1%

1 GND0 GND1 2
XDP_BPM#5 3 4 XDP_TMS R3 1 2 54.9_0402_1%
XDP_BPM#4 OBSFN_A0 OBSFN_C0
5 OBSFN_A1 OBSFN_C1 6
7 8 XDP_TDO R4 1 2 54.9_0402_1%
D XDP_BPM#3 GND2 GND3 D
9 OBSDATA_A0 OBSDATA_C0 10
XDP_BPM#2 11 12 XDP_BPM#5 R5 1 2 54.9_0402_1%
OBSDATA_A1 OBSDATA_C1
13 GND4 GND5 14
XDP_BPM#1 15 16 XDP_HOOK1 R6 1 2 @ 54.9_0402_1%
XDP_BPM#0 OBSDATA_A2 OBSDATA_C2
17 OBSDATA_A3 OBSDATA_C3 18
19 GND6 GND7 20
21 22 XDP_TRST# R7 1 2 51_0402_1%
OBSFN_B0 OBSFN_D0
<7> H_A#[3..16] 23 OBSFN_B1 OBSFN_D1 24
JP2A 25 26 XDP_TCK R8 1 2 54.9_0402_1%
H_A#3 H_ADS# GND8 GND9
J4 A[3]# ADS# H1 H_ADS# <7> 27 OBSDATA_B0 OBSDATA_D0 28

ADDR GROUP 0
H_A#4 L5 E2 H_BNR# 29 30
A[4]# BNR# H_BNR# <7> OBSDATA_B1 OBSDATA_D1
H_A#5 L4 G5 H_BPRI# 31 32
A[5]# BPRI# H_BPRI# <7> GND10 GND11
H_A#6 K5 33 34
H_A#7 A[6]# H_DEFER# OBSDATA_B2 OBSDATA_D2
M3 A[7]# DEFER# H5 H_DEFER# <7> 35 OBSDATA_B3 OBSDATA_D3 36
H_A#8 N2 F21 H_DRD Y# 37 38
A[8]# DRDY# H_DRDY# <7> GND12 GND13
H_A#9 J1 E1 H_DBSY# <5> H_PWRGOOD_R H_PWRGOOD_R 39 40 CLK_CPU_XDP CLK_CPU_XDP <15>
A[9]# DBSY# H_DBSY# <7> PWRGOOD/HOOK0 ITPCLK/HOOK4
H_A#10 N3 XDP_HOOK1 41 42 CLK_CPU_XDP# CLK_CPU_XDP# <15>
H_A#11 A[10]# H_BR0# R10 HOOK1 ITPCLK#/HOOK5 1K_0402_1%
P5 A[11]# BR0# F1 H_BR0# <7> +VCCP 43 VCC_OBS_AB VCC_OBS_CD 44 +VCCP
H_A#12 P2 56_0402_5% 45 46 H_RESET#_R 1 R9 2 H_RESET#
A[12]# HOOK2 RESET#/HOOK6

CONTROL
H_A#13 L2 D20 H_IERR# 2 1 1 47 48 XDP_DBRESET#_R 2 1 XDP_DBRESET#
H_A#14 A[13]# IERR# H_INIT# +VCCP HOOK3 DBR#/HOOK7 200_0402_1%
P4 A[14]# INIT# B3 H_INIT# <19> 49 GND14 GND15 50
H_A#15 P1 C1 51 52 XDP_TDO R11
H_A#16 A[15]# H_LOCK# C2 0.1U_0402_16V4Z SDA TD0 XDP_TRST#
R1 A[16]# LOCK# H4 H_LOCK# <7> 53 SCL TRST# 54
H_ADSTB#0 2 XDP_TDI
<7> H_ADSTB#0 M1 ADSTB[0]# 1 2 55 TCK1 TDI 56
C1 H_RESET# XDP_TCK 57 58 XDP_TMS
RESET# H_RESET# <7> TCK0 TMS
H_REQ#0 K3 F3 H_RS#0 59 60 XDP_PRE 1 R12 2 0_0402_5%
<7> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <7> GND16 GND17
H_REQ#1 H2 F4 H_RS#1 0.1U_0402_16V4Z
<7> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <7>
H_REQ#2 K2 G3 H_RS#2 @ SAMTE_BSH-030-01-L-D-A
<7> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <7>
H_REQ#3 J3 G2 H_TRDY# Place R9 within 200ps (~1") to CPU
<7> H_REQ#3 REQ[3]# TRDY# H_TRDY# <7>
H_REQ#4 L1
<7> H_REQ#4 REQ[4]#
G6 H_HIT#
<7> H_A#[17..35] HIT# H_HIT# <7>
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# <7> C
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4
ADDR GROUP 1

H_A#20 W6 AD3 XDP_BPM#1

H_A#21 U4
A[20]# BPM[1]#
AD1 XDP_BPM#2 Thermal Sensor ADM1032ARMZ
XDP/ITP SIGNALS

H_A#22 A[21]# BPM[2]# XDP_BPM#3

Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 XDP_BPM#4 +3VS
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI
T3 A[26]# TDI AA6 2
H_A#27 W2 AB3 XDP_TDO C3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST# 0.1U_0402_16V4Z
H_A#30 A[29]# TRST# XDP_DBRESET# 1
U2 A[30]# DBR# C20 XDP_DBRESET# <20>
H_A#31 V4 U1
A[31]# H_PROCHOT# <37>
H_A#32 W3 R13 1 8 SMB_EC_CK2
H_A#33 A[32]# H_PROCHOT# VDD SCLK
AA4 A[33]# THERMAL 2 1 +VCCP
H_A#34 AB2 68_0402_5% H_THERMDA 2 7 SMB_EC_DA2
H_A#35 A[34]# C4 D+ SDATA
AA3 A[35]# PROCHOT# D21
H_ADSTB#1 V1 A24 H_THERMDA_R1 R14 2 0_0402_5% H_THERMDA 1 2 H_THERMDC 3 6
<7> H_ADSTB#1 ADSTB[1]# THERMDA D- ALERT#
B25 H_THERMDC_R1 R15 2 0_0402_5% H_THERMDC
H_A20M# THERMDC 2200P_0402_50V7K THERM#
<19> H_A20M# A6 A20M# 4 THERM# GND 5
ICH

H_FERR# A5 C7 H_THERMTRIP#
<19> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <7,19>
H_IGNNE# C4 R16
<19> H_IGNNE# IGNNE#
+3VS 1 2 ADM1032ARMZ-2REEL_MSOP8
H_STPCLK# D5
<19> H_STPCLK# STPCLK#
H_INTR C6 H CLK 10K_0402_5% Address:100_1100
<19> H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
<19> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <15>
H_SMI# A3 A21 CLK_CPU_BCLK#
<19> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <15>
M4 <30> SMB_EC_DA2 SMB_EC_DA2
RSVD[01] SMB_EC_CK2
N5 RSVD[02] H_THERMDA, H_THERMDC routing together, <30> SMB_EC_CK2
T2 RSVD[03]
B
V3 Trace width / Spacing = 10 / 10 mil B
RSVD[04]
B2
RESERVED

RSVD[05]
C3 RSVD[06]
D2 RSVD[07] For Merom, R14 and R15 are 0ohm
D22
D3
RSVD[08] For Penryn, R14 and R15 are 100ohm.
RSVD[09]
F6 RSVD[10]
PWM Fan Control circuit +5VS SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P
Merom Ball-out Rev 1a
CONN@
JP3

1
SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU 0306_Reserve. 1 1 1
+VCCP SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3 D1 C5 C6 1
2 2
0.1U_0402_16V4Z 3
@ R405 0_0402_5% RB751V_SOD323 4.7U_0805_10V4Z G1
4 G2
2 2
1 2

2
1

ACES_85204-02001
R17 CONN@
+3VS FAN
@ 56_0402_5%
2 2

1
2
5
6

1
5
B

U2 D Q1 @ D26
1 G

P
<30> FAN_PWM INB
E

H_PROCHOT# 3 1 OCP# 4 3 RLZ5.1B_LL34

OCP# <20> O
C

@ Q2 THERM# 2 S SI3456BDV-T1-E3_TSOP6

2
INA

G
MMBT3904_SOT23

4
TC7SH00FU_SSOP5

3
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+/XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 4 of 40
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
<7> H_D#[0..15] H_D#[32..47] <7>
JP2B JP2C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9

DATA GRP 0
D H_D#4 H_D#36 D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18

DATA GRP 2
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 D[13]# D[45]# AA23 B14 VCC[014] VCC[081] AD14
H_D#14 K22 AA24 H_D#46 B15 AD15
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
H23 D[15]# D[47]# AB25 B17 VCC[016] VCC[083] AD17
H_DSTBN#0 J26 Y26 H_DSTBN#2 B18 AD18
<7> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <7> VCC[017] VCC[084]
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
<7> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <7> VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
<7> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <7> VCC[019] VCC[086]
<7> H_D#[16..31] H_D#[48..63] <7> C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18

DATA GRP 3
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R18 0_0402_5%
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 D[29]# D[61]# AD23 E10 VCC[035] VCCP[01] G21 2 1
H_D#30 T25 AF22 H_D#62 E12 V6 2 1
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R19 0_0402_5% C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
<7> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <7> VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
<7> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <7> VCC[039] VCCP[05] +
H_DINV#1 N24 AC20 H_DINV#3 E18 J21 C7
<7> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <7> VCC[040] VCCP[06]
E20 VCC[041] VCCP[07] K21
V_CPU_GTLREF AD26 R26 COMP0 F7 M21 330U_4V_M
R20 GTLREF COMP[0] VCC[042] VCCP[08] 2
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
R21 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T1 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
C8 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
T2 AF1 TEST5 DPRSTP# E5 H_DPRSTP# <7,19,37> F15 VCC[047] VCCP[13] T21

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T3 TEST6 DPSLP# H_DPSLP# <19> VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# <7> VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PW RGOOD F20 W21
<15> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD <19> VCC[050] VCCP[16]

R22

R23

R24

R25
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
<15> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <7> VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
<15> CPU_BSEL2 BSEL[2] PSI# H_PSI# <37> VCC[052] VCCA[01] +1.5VS

0.01U_0402_16V7K
AA10 C26

2
VCC[053] VCCA[02]

10U_0805_6.3V6M
Merom Ball-out Rev 1a R26 AA12 VCC[054]
CONN@ 2 1H_PWRGOOD_R H_PWRGOOD_R <4> AA13 VCC[055] VID[0] AD6 CPU_VID0 <37>
1K_0402_5% AA15 AF5 1 1
VCC[056] VID[1] CPU_VID1 <37>
AA17 VCC[057] VID[2] AE5 CPU_VID2 <37>

C10
C9
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within AA18 VCC[058] VID[3] AF4 CPU_VID3 <37>
AA20 AE3 CPU_VID4 <37>
0.5" of CPU pin.Trace AB9
VCC[059] VID[4]
AF3
2 2
VCC[060] VID[5] CPU_VID5 <37>
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10 VCC[061] VID[6] AE2 CPU_VID6 <37>
AB10
mils away from any other AB12
VCC[062]
VCC[063]
toggling signal. AB14 VCC[064] VCCSENSE AF7 VCCSENSE VCCSENSE <37>
166 0 1 1 COMP[0,2] trace width is AB15 VCC[065] Near pin B26
AB17 VCC[066]
18 mils. COMP[1,3] trace AB18 VCC[067] VSSSENSE AE7 VSSSENSE VSSSENSE <37>
B width is 4 mils. Merom Ball-out Rev 1a B
200 0 1 0
CONN@ .
Length match within 25 mils.
The trace width/space/other is
20/7/25.
+VCCP
1

R27
1K_0402_1%
+VCC_CORE
2

V_CPU_GTLREF R28
100_0402_1%
1 2 VCCSENSE
1

R30
R29 100_0402_1%
2K_0402_1% 1 2 VSSSENSE
2

Close to CPU pin AD26

within 500mils. Close to CPU pin
within 500mils.
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 5 of 40
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

1 1 1 1 1 1 1 1
C11 C12 C13 C14 C15 C16 C17 C18
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
D 2 2 2 2 2 2 2 2 D

JP2D
A4 VSS[001] VSS[082] P6
+VCC_CORE
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5 1 1 1 1 1 1 1 1
A19 R22 C19 C20 C21 C22 C23 C24 C25 C26
VSS[006] VSS[087] Place these capacitors on L8
A23 VSS[007] VSS[088] R25
AF2 T1 (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[008] VSS[089] 2 2 2 2 2 2 2 2
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23
B11 VSS[011] VSS[092] T26
B13 VSS[012] VSS[093] U3
+VCC_CORE
B16 VSS[013] VSS[094] U6
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2 1 1 1 1 1 1 1 1
C5 V5 C27 C28 C29 C30 C31 C32 C33 C34
VSS[017] VSS[098] Place these capacitors on L8
C8 VSS[018] VSS[099] V22
C11 V25 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[019] VSS[100] 2 2 2 2 2 2 2 2
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4
C19 VSS[022] VSS[103] W23
C2 VSS[023] VSS[104] W26
+VCC_CORE
C22 VSS[024] VSS[105] Y3
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24 1 1 1 1 1 1 1 1
D8 AA2 C35 C36 C37 C38 C39 C40 C41 C42
VSS[028] VSS[109] Place these capacitors on L8
D11 VSS[029] VSS[110] AA5
C (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
D13 VSS[030] VSS[111] AA8
2 2 2 2 2 2 2 2
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14 Mid Frequence Decoupling
D23 VSS[033] VSS[114] AA16
D26 VSS[034] VSS[115] AA19
E3 VSS[035] VSS[116] AA22
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
F16 AC8
F19
F2
VSS[048]
VSS[049]
VSS[129]
VSS[130] AC11
AC14
ESR <= 1.5m ohm
F22
VSS[050]
VSS[051]
VSS[131]
VSS[132] AC16 Near CPU CORE regulator Capacitor > 1980uF
F25 VSS[052] VSS[133] AC19
G4 VSS[053] VSS[134] AC21
G1 VSS[054] VSS[135] AC24
G23 VSS[055] VSS[136] AD2
G26 VSS[056] VSS[137] AD5
+VCC_CORE
H3 VSS[057] VSS[138] AD8
H6 VSS[058] VSS[139] AD11
H21 AD13 330U_D2E_2.5VM_R7 1000U 2.5V M H80 LESR8M
VSS[059] VSS[140]
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25 1 1 1 1 1
J25 VSS[064] VSS[145] AE1
K1 AE4 C45 + C46 + @ C47 + C48 + C49 +
VSS[065] VSS[146] 330U_D2E_2.5VM_R7
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
2 2 2 2 2
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 AE23 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7
VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26 0214_Change type from DIP to SMD.
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6 0301_Remount C46. 0301_Delete C49.
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11 Place these inside
N1 VSS[077] VSS[158] AF13 socket cavity on L8
N4 VSS[078] VSS[159] AF16 (North side
N23 VSS[079] VSS[160] AF19
N26 AF21
Secondary)
VSS[080] VSS[161]
P3 VSS[081] VSS[162] A25
AF25 +VCCP
VSS[163]
Merom Ball-out Rev 1a
CONN@ . 1 1 1 1 1 1
C50 C51 C52 C53 C54 C55

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 6 of 40
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] <4> U3B For Crestline: 20ohm

<5> H_D#[0..63] U3A For Calero: 80.6ohm
J13 H_A#3 P36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0
E2 H_D#_0 H_A#_4 B11 P37 RSVD2 SM_CK_0 AV29 M_CLK_DDR0 <13>
H_D#1 G2 C11 H_A#5 R35 BB23 M_CLK_DDR1 M_CLK_DDR1 <13>
H_D#2 H_D#_1 H_A#_5 H_A#6 RSVD3 SM_CK_1 M_CLK_DDR2
G7 H_D#_2 H_A#_6 M11 N35 RSVD4 SM_CK_3 BA25 M_CLK_DDR2 <14>
H_D#3 M6 C15 H_A#7 AR12 AV23 M_CLK_DDR3 M_CLK_DDR3 <14>
H_D#_3 H_A#_7 RSVD5 SM_CK_4

0.01U_0402_16V7K
+1.8V

2.2U_0805_16V4Z
H_D#4 H7 F16 H_A#8 AR13
H_D#5 H_D#_4 H_A#_8 H_A#9 RSVD6 M_CLK_DDR#0
H3 H_D#_5 H_A#_9 L13 AM12 RSVD7 SM_CK#_0 AW30 M_CLK_DDR#0 <13>
H_D#6 G4 G17 H_A#10 2 2 AN13 BA23 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SM_CK#_1 M_CLK_DDR#1 <13>

1
H_D#7 F3 C14 H_A#11 J12 AW25 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SM_CK#_3 M_CLK_DDR#2 <14>

C56

RSVD
H_D#8 N8 K16 H_A#12 R31 AR37 AW23 M_CLK_DDR#3
H_D#_8 H_A#_12 RSVD10 SM_CK#_4 M_CLK_DDR#3 <14>

C57
H_D#9 H2 B13 H_A#13 AM36
H_D#10 H_D#_9 H_A#_13 H_A#14 1 1 1K_0402_1% RSVD11 DDR_CKE0_DIMMA
M10 H_D#_10 H_A#_14 L16 AL36 RSVD12 SM_CKE_0 BE29 DDR_CKE0_DIMMA <13>
H_D#11 N12 J17 H_A#15 AM37 AY32 DDR_CKE1_DIMMA
DDR_CKE1_DIMMA <13>

2
D H_D#12 H_D#_11 H_A#_15 H_A#16 SMRCOMP_VOH RSVD13 SM_CKE_1 DDR_CKE2_DIMMB D
N9 H_D#_12 H_A#_16 B14 D20 RSVD14 SM_CKE_3 BD39 DDR_CKE2_DIMMB <14>
H_D#13 H5 K19 H_A#17 BG37 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SM_CKE_4 DDR_CKE3_DIMMB <14>

1
H_D#14 P13 P15 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19 R32 DDR_CS0_DIMMA#
K9 H_D#_15 H_A#_19 R17 SM_CS#_0 BG20 DDR_CS0_DIMMA# <13>
H_D#16 M2 B16 H_A#20 3.01K_0402_1% BK16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 SM_CS#_1 DDR_CS1_DIMMA# <13>
H_D#17 W10 H20 H_A#21 NA lead free BG16 DDR_CS2_DIMMB#
H_D#_17 H_A#_21 SM_CS#_2 DDR_CS2_DIMMB# <14>
H_D#18 Y8 L19 H_A#22 H10 BE13 DDR_CS3_DIMMB#
DDR_CS3_DIMMB# <14>

2
H_D#_18 H_A#_22 RSVD20 SM_CS#_3

MUXING
H_D#19 V4 D17 H_A#23 SMRCOMP_VOL B51
H_D#20 H_D#_19 H_A#_23 H_A#24 RSVD21 M_ODT0
M3 H_D#_20 H_A#_24 M17 BJ20 RSVD22 SM_ODT_0 BH18 M_ODT0 <13>

1
0.01U_0402_16V7K
2.2U_0805_16V4Z
H_D#21 J1 N16 H_A#25 BK22 BJ15 M_ODT1 M_ODT1 <13>
H_D#22 H_D#_21 H_A#_25 H_A#26 R33 RSVD23 SM_ODT_1 M_ODT2 +1.8V
N5 H_D#_22 H_A#_26 J19 1 1 BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 <14>
H_D#23 N3 B18 H_A#27 BH20 BE16 M_ODT3 M_ODT3 <14>
H_D#_23 H_A#_27 RSVD25 SM_ODT_3

C58
H_D#24 W6 E19 H_A#28 1K_0402_1% BK18 20_0402_1%
H_D#_24 H_A#_28 RSVD26

C59
H_D#25 W9 B17 H_A#29 BJ18 BL15 SMRCOMP R34 2 1

2
H_D#26 H_D#_25 H_A#_29 H_A#30 2 2 RSVD27 SM_RCOMP SMRCOMP#
N2 H_D#_26 H_A#_30 B15 BF23 RSVD28 SM_RCOMP# BK14 2 1
H_D#27 Y7 E17 H_A#31 BG23 R35 20_0402_1%
H_D#28 H_D#_27 H_A#_31 H_A#32 RSVD29 SMRCOMP_VOH
Y9 H_D#_28 H_A#_32 C18 BC23 RSVD30 SM_RCOMP_VOH BK31
H_D#29 P4 A19 H_A#33 BD24 BL31 SMRCOMP_VOL

DDR
H_D#30 H_D#_29 H_A#_33 H_A#34 RSVD31 SM_RCOMP_VOL
W3 H_D#_30 H_A#_34 B19 <13> DDR_A_MA14 BJ29 RSVD32
H_D#31 N1 N19 H_A#35 BE24 AR49
H_D#_31 H_A#_35 <14> DDR_B_MA14 RSVD33 SM_VREF_0
H_D#32 AD12 BH39 AW4 V_DDR_MCH_REF
H_D#33 H_D#_32 H_ADS# RSVD34 SM_VREF_1
AE3 H_D#_33 H_ADS# G12 H_ADS# <4> AW20 RSVD35
H_D#34 AD9
HOST H17 H_ADSTB#0 +3VS BK20
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4> RSVD36
H_D#35 AC9 G20 H_ADSTB#1 R36 C48
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <4> RSVD37
H_D#36 AC7 C8 H_BNR# PM_EXTTS#0 2 1 D47 B42 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# <4> RSVD38 DPLL_REF_CLK CLK_MCH_DREFCLK <15>
H_D#37 AC14 E8 H_BPRI# B44 C42 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# <4> RSVD39 DPLL_REF_CLK# CLK_MCH_DREFCLK# <15>
H_D#38 AD11 F12 H_BR0# 10K_0402_5% C44 H48 MCH_SSCDREFCLK
H_D#_38 H_BREQ# H_BR0# <4> RSVD40 DPLL_REF_SSCLK MCH_SSCDREFCLK <15>
H_D#39 AC11 D6 H_DEFER# A35 H47 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# <4> RSVD41 DPLL_REF_SSCLK# MCH_SSCDREFCLK# <15>
H_D#40 AB2 C10 H_DBSY# R37 B37
H_D#_40 H_DBSY# H_DBSY# <4> RSVD42
H_D#41 AD7 AM5 CLK_MCH_BCLK PM_EXTTS#1 2 1 B36 K44 CLK_MCH_3GPLL
CLK_MCH_BCLK <15> CLK_MCH_3GPLL <15>

CLK
H_D#42 H_D#_41 HPLL_CLK CLK_MCH_BCLK# RSVD43 PEG_CLK CLK_MCH_3GPLL#
AB1 H_D#_42 HPLL_CLK# AM7 CLK_MCH_BCLK# <15> B34 RSVD44 PEG_CLK# K45 CLK_MCH_3GPLL# <15>
H_D#43 Y3 H8 H_DPWR# 10K_0402_5% C34
C H_D#_43 H_DPWR# H_DPWR# <5> RSVD45 C
H_D#44 AC6 K7 H_DRD Y#
H_D#_44 H_DRDY# H_DRDY# <4>
H_D#45 AE2 E4 H_HIT# R38
H_D#_45 H_HIT# H_HIT# <4>
H_D#46 AC5 C6 H_HITM# CLKREQ#_B 2 <> 1 AN47 DMI_TXN0
H_D#_46 H_HITM# H_HITM# <4> DMI_RXN_0 DMI_TXN0 <20>
H_D#47 AG3 G10 H_LOCK# AJ38 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# <4> DMI_RXN_1 DMI_TXN1 <20>
H_D#48 AJ9 B7 H_TRDY# 10K_0402_5% AN42 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# <4> DMI_RXN_2 DMI_TXN2 <20>
H_D#49 AH8 AN46 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 <20>
H_D#50 AJ14
H_D#51 H_D#_50 DMI_TXP0
AE9 H_D#_51 DMI_RXP_0 AM47 DMI_TXP0 <20>
H_D#52 AE11 MCH_CLKSEL0 P27 AJ39 DMI_TXP1
+VCCP H_D#_52 <15> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 <20>
H_D#53 AH12 K5 H_DINV#0 MCH_CLKSEL1 N27 AN41 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 <5> <15> MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 <20>
H_D#54 AJ5 L2 H_DINV#1 MCH_CLKSEL2 N24 AN45 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 <5> <15> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 <20>
H_D#55 AH5 AD13 H_DINV#2 C21
H_D#_55 H_DINV#_2 H_DINV#2 <5> CFG_3
H_D#56 AJ6 AE13 H_DINV#3 C23 AJ46 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 <5> CFG_4 DMI_TXN_0 DMI_RXN0 <20>
54.9_0402_1%

54.9_0402_1%

H_D#57 AE7 T4 CFG5 F23 AJ41 DMI_RXN1

H_D#_57 CFG_5 DMI_TXN_1 DMI_RXN1 <20>
1

H_D#58 AJ7 M7 H_DSTBN#0 T5 CFG6 N23 AM40 DMI_RXN2

H_D#_58 H_DSTBN#_0 H_DSTBN#0 <5> CFG_6 DMI_TXN_2 DMI_RXN2 <20>
H_D#59 AJ2 K3 H_DSTBN#1 T6 CFG7 G23 AM44 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <5> CFG_7 DMI_TXN_3 DMI_RXN3 <20>
R39

R40

H_D#60 AE5 AD2 H_DSTBN#2 T7 CFG8 J20

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <5> CFG_8

CFG
H_D#61 AJ3 AH11 H_DSTBN#3 T8 CFG9 C20 AJ47 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5> CFG_9 DMI_TXP_0 DMI_RXP0 <20>
H_D#62 AH2 T9 CFG10 R24 AJ42 DMI_RXP1
DMI_RXP1 <20>
2

H_D#63 H_D#_62 H_DSTBP#0 T10 CFG11 CFG_10 DMI_TXP_1 DMI_RXP2

AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 <5> L23 CFG_11 DMI_TXP_2 AM39 DMI_RXP2 <20>
K2 H_DSTBP#1 T11 CFG12 J23 AM43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 <5> CFG_12 DMI_TXP_3 DMI_RXP3 <20>
AC2 H_DSTBP#2 T12 CFG13 E23
H_DSTBP#_2 H_DSTBP#2 <5> CFG_13
H_SWNG B3 AJ10 H_DSTBP#3 E20
H_SWING H_DSTBP#_3 H_DSTBP#3 <5> CFG_14
H_RCOMP C2 K23
H_RCOMP H_REQ#0 T13 CFG16 CFG_15
H_REQ#_0 M14 H_REQ#0 <4> M20 CFG_16
H_SCOMP H_REQ#1

GRAPHICS VID
W1 H_SCOMP H_REQ#_1 E13 H_REQ#1 <4> M24 CFG_17
H_SCOMP# W2 A11 H_REQ#2 T44 CFG18 L32
H_SCOMP# H_REQ#_2 H_REQ#2 <4> CFG_18
H13 H_REQ#3 T14 CFG19 N33
H_REQ#_3 H_REQ#3 <4> CFG_19
<4> H_RESET# H_RESET# B6 B12 H_REQ#4 T15 CFG20 L35
H_CPURST# H_REQ#_4 H_REQ#4 <4> CFG_20
<5> H_CPUSLP# H_CPUSLP# E5 H_CPUSLP# H_RS#0
H_RS#_0 E12 H_RS#0 <4>
D7 H_RS#1 H_RS#1 <4> E35 T16
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_0 T17 B
H_RS#_2 D8 H_RS#2 <4> <20> PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39
B9 H_DPRSTP# L39 C38 T18
H_AVREF <5,19,37> H_DPRSTP# PM_DPRSTP# GFX_VID_2
H_VREF A9 PM_EXTTS#0 L36 B39 T19
H_DVREF <13> PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3

PM
PM_EXTTS#1 J36 E36 T20
<14> PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN
CRESTLINE_1p0 PM_PWROK AW49
<20,30> PM_PWROK PWROK +1.25VM_AXD
PLT_RST# AV20
<18,22> PLT_RST# RSTIN#
layout note: <4,19> H_THERMTRIP# H_THERMTRIP# N20
DPRSLPVR THERMTRIP#
<20,37> DPRSLPVR G36 DPRSLPVR

1
Route H_SCOMP and H_SCOMP# with trace width, spacing and
AM49 CL_CLK0 R41
impedance (55 ohm) same as FSB data traces CL_CLK CL_CLK0 <20>
AK50 CL_DATA0
CL_DATA CL_DATA0 <20>
BJ51 AT43 M_PWROK 1K_0402_1%
NC_1 CL_PWROK M_PWROK <20,30>
CL_RST#

ME
BK51 AN49 CL_RST# <20>

2
NC_2 CL_RST# CL_VREF CL_VREF
BK50 NC_3 CL_VREF AM50
BL50 NC_4

1
Layout Note: BL49 0.1U_0402_16V4Z 1
NC_5 R42
H_RCOMP / H_VREF / H_SWNG Layout Note: BL3 NC_6
BL2 C60 392_0402_1%
V_DDR_MCH_REF +1.8V NC_7

NC
trace width and spacing is 10/20 trace width and
BK1 NC_8 2
BJ1 H35

2
NC_9 SDVO_CTRL_CLK

MISC
spacing is 20/20. E1 NC_10 SDVO_CTRL_DATA K36
1

A5 G39 CLKREQ#_B CLKREQ#_B <15>

@ R43 NC_11 CLK_REQ# MCH_ICH_SYNC#
C51 NC_12 ICH_SYNC# G40 MCH_ICH_SYNC# <20>
+VCCP 1K_0402_1% B50
+VCCP NC_13
A50 NC_14
A49 A37
2

NC_15 TEST_1
221_0603_1%
1K_0402_1%

V_DDR_MCH_REF BK2 R32

<13,14,35> V_DDR_MCH_REF NC_16 TEST_2
1

0.1U_0402_16V4Z

1
R45

CRESTLINE_1p0
R44

1 @ R46 R47 R48

1K_0402_1%
C61

0.1U_0402_16V4Z 20K_0402_5% 0_0402_5%

2

A H_VREF H_RCOMP H_SWNG A

2

2
2
24.9_0402_1%

0.1U_0402_16V4Z
1

1
100_0402_1%
2K_0402_1%

1 1
R49

C62

R50

R51

C63

2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(1/6)-AGTL+/DMI/DDR2
within 100 mils from NB Near B3 pin AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 7 of 40
5 4 3 2 1
 5 4 3 2 1

D D

<13> DDR_A_D[0..63] <14> DDR_B_D[0..63]

U3D U3E
DDR_A_D0 AR43 BB19 DDR_A_BS0 DDR_B_D0 AP49 AY17 DDR_B_BS0
SA_DQ_0 SA_BS_0 DDR_A_BS0 <13> SB_DQ_0 SB_BS_0 DDR_B_BS0 <14>
DDR_A_D1 AW44 BK19 DDR_A_BS1 DDR_B_D1 AR51 BG18 DDR_B_BS1
SA_DQ_1 SA_BS_1 DDR_A_BS1 <13> SB_DQ_1 SB_BS_1 DDR_B_BS1 <14>
DDR_A_D2 BA45 BF29 DDR_A_BS2 DDR_B_D2 AW50 BG36 DDR_B_BS2
SA_DQ_2 SA_BS_2 DDR_A_BS2 <13> SB_DQ_2 SB_BS_2 DDR_B_BS2 <14>
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
AR41 SA_DQ_4 SA_CAS# BL17 DDR_A_CAS# <13> AN51 SB_DQ_4 SB_CAS# BE17 DDR_B_CAS# <14>
DDR_A_D5 AR45 DDR_B_D5 AN50
SA_DQ_5 DDR_A_DM[0..7] <13> SB_DQ_5 DDR_B_DM[0..7] <14>
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
DDR_A_D12 BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
DDR_A_D13 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14 BH49 DDR_A_DQS[0..7] <13> DDR_B_D14 BF50
SA_DQ_14 SB_DQ_14 DDR_B_DQS[0..7] <14>
DDR_A_D15 BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0

A
DDR_A_D16 SA_DQ_15 SA_DQS_0 DDR_A_DQS1 DDR_B_D16 SB_DQ_15 SB_DQS_0 DDR_B_DQS1
AW43 BE48 BJ50 BD50

B
DDR_A_D17 SA_DQ_16 SA_DQS_1 DDR_A_DQS2 DDR_B_D17 SB_DQ_16 SB_DQS_1 DDR_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
DDR_A_D18 BG42 BC37 DDR_A_DQS3 DDR_B_D18 BJ43 BK39 DDR_B_DQS3
DDR_A_D19 SA_DQ_18 SA_DQS_3 DDR_A_DQS4 DDR_B_D19 SB_DQ_18 SB_DQS_3 DDR_B_DQS4
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
DDR_A_D20 DDR_A_DQS5 DDR_B_D20 DDR_B_DQS5

MEMORY
BF44 SA_DQ_20 SA_DQS_5 BH6 BK47 SB_DQ_20 SB_DQS_5 BL7
DDR_A_D21 DDR_A_DQS6 DDR_B_D21 DDR_B_DQS6

MEMORY
BH45 SA_DQ_21 SA_DQS_6 BB2 BK49 SB_DQ_21 SB_DQS_6 BE2
DDR_A_D22 BG40 AP3 DDR_A_DQS7 DDR_B_D22 BK43 AV2 DDR_B_DQS7
SA_DQ_22 SA_DQS_7 DDR_A_DQS#[0..7] <13> SB_DQ_22 SB_DQS_7 DDR_B_DQS#[0..7] <14>
DDR_A_D23 BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR_A_D24 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
DDR_A_D25 AW40 BC41 DDR_A_DQS#2 DDR_B_D25 BL41 BL45 DDR_B_DQS#2
DDR_A_D26 SA_DQ_25 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D26 SB_DQ_25 SB_DQS#_2 DDR_B_DQS#3
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
DDR_A_D27 AW36 BA16 DDR_A_DQS#4 DDR_B_D27 BJ36 BK12 DDR_B_DQS#4
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
C DDR_A_D29 DDR_A_DQS#6 DDR_B_D29 DDR_B_DQS#6 C
AY41 SA_DQ_29 SA_DQS#_6 BC1 BJ40 SB_DQ_29 SB_DQS#_6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
SA_DQ_30 SA_DQS#_7 DDR_A_MA[0..13] <13> SB_DQ_30 SB_DQS#_7
DDR_A_D31 AT38 DDR_B_D31 BK37 DDR_B_MA[0..13] <14>
DDR_A_D32 SA_DQ_31 DDR_A_MA0 DDR_B_D32 SB_DQ_31 DDR_B_MA0
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18
SYSTEM

DDR_A_D33 AT13 BD20 DDR_A_MA1 DDR_B_D33 BE11 BG28 DDR_B_MA1

SA_DQ_33 SA_MA_1 SB_DQ_33 SB_MA_1

SYSTEM
DDR_A_D34 AW11 BK27 DDR_A_MA2 DDR_B_D34 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
DDR_A_D44 BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
DDR_A_D45 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR

DDR_A_D46 BD7 DDR_B_D46 BJ8

SA_DQ_46 SB_DQ_46

DDR
DDR_A_D47 BB9 DDR_B_D47 BJ6 AV16 DDR_B_RAS#
SA_DQ_47 SB_DQ_47 SB_RAS# DDR_B_RAS# <14>
DDR_A_D48 BB5 BE18 DDR_A_RAS# DDR_B_D48 BF4 AY18 SB_RCVEN#
SA_DQ_48 SA_RAS# DDR_A_RAS# <13> SB_DQ_48 SB_RCVEN#
DDR_A_D49 AY7 AY20 SA_RCVEN# DDR_B_D49 BH5 T21
DDR_A_D50 SA_DQ_49 SA_RCVEN# T22 DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 SA_DQ_50 BG1 SB_DQ_50 SB_WE# BC17 DDR_B_WE# <14>
DDR_A_D51 AT7 BA19 DDR_A_WE# DDR_A_WE# <13> DDR_B_D51 BC2
DDR_A_D52 SA_DQ_51 SA_WE# DDR_B_D52 SB_DQ_51
AY6 SA_DQ_52 BK3 SB_DQ_52
DDR_A_D53 BB7 DDR_B_D53 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 SA_DQ_54 BD3 SB_DQ_54
DDR_A_D55 AR8 DDR_B_D55 BJ2
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AR9 SA_DQ_56 BA3 SB_DQ_56
DDR_A_D57 AN3 DDR_B_D57 BB3
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AM8 SA_DQ_58 AR1 SB_DQ_58
DDR_A_D59 AN10 DDR_B_D59 AT3
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AT9 SA_DQ_60 AY2 SB_DQ_60
B DDR_A_D61 DDR_B_D61 B
AN9 SA_DQ_61 AY3 SB_DQ_61
DDR_A_D62 AM9 DDR_B_D62 AU2
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AN11 SA_DQ_63 AT2 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 8 of 40
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

010 = FSB 800MHz
CFG[2:0] FSB Freq select 011 = FSB 667MHz
Others = Reserved

D
0 = DMI x 2 D
0312_Add test point. CFG5 (DMI select)
U3C 1 = DMI x 4
BKLT_CTRL J40
R52
24.9_0402_1% +VCCP *
ENABLT L_BKLT_CTRL PEGCOMP
<17> ENABLT H39 L_BKLT_EN PEG_COMPI N43 1 2 CFG6 Reserved
+3VS R53 1 2 10K_0402_5% E39 M43
R54 1 L_CTRL_CLK PEG_COMPO
2 10K_0402_5% E40 L_CTRL_DATA PEGCOMP trace width
LCD_CLK C37 CFG7 (CPU Strap) 0 = Reserved
<17> LCD_CLK L_DDC_CLK and spacing is 20/25 mils.
LCD_DATA D35 J51
<17> LCD_DATA L_DDC_DATA PEG_RX#_0
For Crestline:2.4kohm ENAVDD K40 L51 1 = Mobile CPU
For Calero: 1.5Kohm
<17> ENAVDD
2 1 L41
L_VDD_EN PEG_RX#_1
PEG_RX#_2 N47
T45
*
R55 2.4K_0402_1% LVDS_IBG PEG_RX#_3
L43 LVDS_VBG PEG_RX#_4 T50 0 = Normal mode
N41 LVDS_VREFH PEG_RX#_5 U40 CFG8 (Low power PCIE)
N40 Y44 1 = Low Power mode
<17> LVDSAC-
LVDSAC-
LVDSAC+
D46
C45
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_6
PEG_RX#_7 Y40
AB51
*
<17> LVDSAC+ LVDSA_CLK PEG_RX#_8
LVDSBC- D44 W49 CFG9 0 = Reverse Lane
<17> LVDSBC- LVDSB_CLK# PEG_RX#_9
LVDSBC+ E42 AD44
<17> LVDSBC+ LVDSB_CLK PEG_RX#_10

LVDS
AD40 (PCIE Graphics Lane Reversal) 1 = Normal Operation
<17> LVDSA0-
LVDSA0-
LVDSA1-
G51
E51
LVDSA_DATA#_0
PEG_RX#_11
PEG_RX#_12 AG46
AH49
*
<17> LVDSA1- LVDSA2- LVDSA_DATA#_1 PEG_RX#_13
<17> LVDSA2- F49 LVDSA_DATA#_2 PEG_RX#_14 AG45
PEG_RX#_15 AG41 CFG[11:10] Reserved

GRAPHICS
LVDSA0+ G50 J50
<17> LVDSA0+ LVDSA1+ E50
LVDSA_DATA_0 PEG_RX_0
L50
00 = Reserved
<17> LVDSA1+ LVDSA_DATA_1 PEG_RX_1
LVDSA2+ F48 M47 CFG[13:12] (XOR/ALLZ) 01 = XOR Mode Enabled
<17> LVDSA2+ LVDSA_DATA_2 PEG_RX_2
PEG_RX_3 U44 10 = All Z Mode Enabled
T49 11 = Normal Operation (Default)
<17> LVDSB0-
LVDSB0-
LVDSB1-
G44
B47
LVDSB_DATA#_0
PEG_RX_4
PEG_RX_5 T41
W45
*
C <17> LVDSB1- LVDSB_DATA#_1 PEG_RX_6 C
LVDSB2- B45 W41 CFG[15:14] Reserved
<17> LVDSB2- LVDSB_DATA#_2 PEG_RX_7
PEG_RX_8 AB50
PEG_RX_9 Y48
LVDSB0+ E44 AC45 CFG16 (FSB Dynamic ODT) 0 = Disabled
<17> LVDSB0+ LVDSB_DATA_0 PEG_RX_10
LVDSB1+ A47 AC41
<17> LVDSB1+ LVDSB_DATA_1 PEG_RX_11
LVDSB2+ A45 AH47 1 = Enabled
<17> LVDSB2+ LVDSB_DATA_2 PEG_RX_12
AG49 *

PCI-EXPRESS
PEG_RX_13
PEG_RX_14 AH45
PEG_RX_15 AG42 CFG[18:17] Reserved
<16> TV_COMPS TV_COMPS E27 N45
TV_LUMA TVA_DAC PEG_TX#_0
G27 U39 0 = No SDVO Device Present
<16>
<16>
TV_LUMA
TV_CRMA TV_CRMA K27
TVB_DAC
TVC_DAC
PEG_TX#_1
PEG_TX#_2 U47 SDVO_CTRLDATA *

TV
PEG_TX#_3 N51 1 = SDVO Device Present
F27 TVA_RTN PEG_TX#_4 R50
J27 TVB_RTN PEG_TX#_5 T42
L27 Y43 0 = Normal Operation
2.2K_0402_5% M35
TVC_RTN PEG_TX#_6
PEG_TX#_7 W46
W38
CFG19 (DMI Lane Reversal) (Lane number in Order) *
R56 TV_DCONSEL_0 PEG_TX#_8
+3VS 1 2 P33 TV_DCONSEL_1 PEG_TX#_9 AD39 1 = Reverse Lane
PEG_TX#_10 AC46
PEG_TX#_11 AC49
AC42 0 = Only PCIE or SDVO is operational.
PEG_TX#_12
PEG_TX#_13 AH39
AE49
CFG20 (PCIE/SDVO concurrent)
1 = PCIE/SDVO are operating simu.
*
PEG_TX#_14
PEG_TX#_15 AH44

CRT_B H32 M45

<16> CRT_B CRT_BLUE PEG_TX_0
G32 CRT_BLUE# PEG_TX_1 T38
CRT_G K29 T46 CFG[17:3] have internal pull up
<16> CRT_G CRT_GREEN PEG_TX_2
J29 CRT_GREEN# PEG_TX_3 N50
CRT_R F29 R51 CFG[19:18] have internal pull down
<16> CRT_R CRT_RED PEG_TX_4
VGA
B B
E29 CRT_RED# PEG_TX_5 U43
PEG_TX_6 W42
PEG_TX_7 Y47
3VDDCCL K33 Y39
<16> 3VDDCCL CRT_DDC_CLK PEG_TX_8
3VDDCDA G35 AC38
<16> 3VDDCDA CRT_DDC_DATA PEG_TX_9
<16> CRT_HSYNC CRT_HSYNC F33 AD47
CRT_HSYNC PEG_TX_10
C32 CRT_TVO_IREF PEG_TX_11 AC50
<16> CRT_VSYNC CRT_VSYNC E33 AD43
CRT_VSYNC PEG_TX_12
PEG_TX_13 AG39
1

PEG_TX_14 AE50
1.3K_0402_1%

PEG_TX_15 AH43
R57

CRESTLINE_1p0
2

For Crestline:1.3kohm
For Calero: 255ohm

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 9 of 40
5 4 3 2 1
 5 4 3 2 1

+3VS VCCSYNC
+3VS_DAC_BG
10mA
+3VS R58
BLM18PG181SN1D_0603 2 1
2 1 0_0603_5%
0.022U_0402_16V7K

0.1U_0402_16V4Z
R59 1
+1.25VS_DPLLB +1.25VS

0.1U_0402_16V4Z
+V1.25VS_AXF
+VCCP R60
1 1 C64
2
850mA 1 2 +1.25VS 1 2
C65

C66

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
U3H
330U_4V_M 10U_FLC-453232-100K_0.25A_10% R61
2 2 0_0603_5%
J32 VCCSYNC VTT_1 U13 1 1 1 1

4.7U_0805_10V4Z

C67

C68

C69

C70
VTT_2 U12
80mA A33 VCCA_CRT_DAC_1 VTT_3 U11 1 1
+3VS_DAC_CRT B33 VCCA_CRT_DAC_2 VTT_4 U9
2 2 2 2

C72
U8 C71 +
VTT_5

CRT
5mA VTT_6 U7
D A30 U5 2 D
+3VS_DAC_CRT +3VS +3VS_DAC_BG VCCA_DAC_BG VTT_7 2
VTT_8 U3
BLM18PG181SN1D_0603 B32 U2
VSSA_DAC_BG VTT_9
2 1 VTT_10 U1
0.022U_0402_16V7K

R62 80mA T13

VTT_11 +1.25VS_DMI +1.8V_SM_CK
0.1U_0402_16V4Z

VTT
+1.25VS_DPLLA B49 T11 +1.25VS +1.8V
VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
1 1 80mA T10 R64
VTT_13

10U_0805_10V4Z

10U_0805_10V4Z
+1.25VS_DPLLB H49 VCCA_DPLLB VTT_14 T9 1 1 1 1 2 1 2

0.1U_0402_16V4Z
C73

C74

50mA T7 0_0805_5%
VTT_15

C75

C76

C77
PLL

0.1U_0402_16V4Z
+1.25VM_HPLL AL2 T6 R63 1 1
2 2 VCCA_HPLL VTT_16

C78

C79
150mA T5 0_0603_5% 1
VTT_17 2 2 2

C80
+1.25VM_MPLL AM2 VCCA_MPLL VTT_18 T3 1

C81
VTT_19 T2
10mA 2 2
VTT_20 R3
2

A LVDS
+1.8V_TXLVDS 1000P_0402_50V7K A41 R2
VCCA_LVDS VTT_21 2
1 VTT_22 R1
C82 +1.25VM_AXD
B41 VSSA_LVDS
200mA R65
+3VS_PEG_BG
VCC_AXD_1 AT23 1 2 +1.25VS
R66 5mA 2 0_0805_5%
VCC_AXD_2 AU28

1U_0603_10V4Z

10U_0805_10V4Z
+3VS 2 1 K50 VCCA_PEG_BG VCC_AXD_3 AU24 1 1
+1.25VS_PEGPLL

C83

C84
AXD
0_0603_5% AT29 +1.25VS
VCC_AXD_4 L1 +1.5VS_TVDAC +1.5VS
1 K49 VSSA_PEG_BG VCC_AXD_5 AT25

A PEG
0.1U_0402_16V4Z AT30 BLM18PG121SN1D_0603 R67
VCC_AXD_6 2 2
2 1 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
C85
2 +1.25VS_PEGPLL 20 mils U51 VCCA_PEG_PLL VCC_AXD_NCTF AR29 0_0805_5%

0.1U_0402_16V4Z

10U_0805_10V4Z
350mA 1 1 1 1

C86

C87
AW18 VCCA_SM_1 VCC_AXF_1 B23 +V1.25VS_AXF

C88

C89
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2

AXF
AU19 VCCA_SM_3 VCC_AXF_3 A21
100mA 2 2 2 2
+1.25VM_A_SM AU18 VCCA_SM_4
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25VS_DMI
R68 950mA

A SM
C +1.25VS 1 2 AT22 VCCA_SM_7
120mA C
1 0_0805_5% AT21 BK24 +1.8V_SM_CK
VCCA_SM_8 VCC_SM_CK_1

SM CK
1 1 1 AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
C90 + C91 C92 C93 AT18 BJ24
VCCA_SM_10 VCC_SM_CK_3
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
220U_6.3V_M 10U_0805_10V4Z 4.7U_0805_10V4Z AR17 +1.25VM_HPLL
2 2 2 2 VCCA_SM_NCTF_1 +1.25VS_DPLLA R70 +1.25VS
AR16 VCCA_SM_NCTF_2 R69
1U_0603_10V4Z 100mA
R71 +1.25VM_A_SM_CK 100mA VCC_TX_LVDS A43 +1.8V_TXLVDS 1 2 +1.25VS 2 1

A CK

10U_0805_10V4Z
2 1 BC29 MBK2012121YZF_0805
VCCA_SM_CK_1 +3VS_HV
1U_0603_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

220U_6.3V_M
0_0603_5% BB29 @ 1 10U_FLC-453232-100K_0.25A_10%
VCCA_SM_CK_2
40mA VCC_HV_1 C40 100mA 1 1 1 1

C94

C95

C96
C25 B40 + C97 C98
1 1 1 1 +3VS_TVDACA VCCA_TVA_DAC_1 VCC_HV_2
C99

C100

C101

C102

HV
40mA B25 VCCA_TVA_DAC_2

0.1U_0402_16V4Z
+3VS_TVDACB C27 1450mA 0.1U_0402_16V4Z 10U_0805_10V4Z
VCCA_TVB_DAC_1 2 2 2 2 2
40mA B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51 1200mA +VCC_PEG 1
2 2 2 2
TV

C103
+3VS_TVDACC B28 VCCA_TVC_DAC_1 VCC_PEG_2 W50

PEG
A28 VCCA_TVC_DAC_2 VCC_PEG_3 W51
V49 0.1U_0402_16V4Z
VCC_PEG_4 2
VCC_PEG_5 V50
D TV/CRT

0215_Change package from 0402 to 0603. 75mA 50mAM32 VCCD_CRT

+1.5VS_TVDAC 25mAL29 VCCD_TVDAC
5mA VCC_RXR_DMI_1 AH50 250mA +VCCP +1.25VM_MPLL
DMI

+1.5VS_QDAC N28 VCCD_QDAC VCC_RXR_DMI_2 AH51

250mA 20mils +VCC_PEG R73 +1.25VS
+1.25VM_HPLL AN2 R72
VCCD_HPLL
100mA VTTLF1 A7 2 1 2 1
VTTLF

+1.25VS_PEGPLL U48 F2 0_0805_5% MBK2012121YZF_0805

VCCD_PEG_PLL VTTLF2

220U_6.3V_M

10U_0805_10V4Z
VTTLF3 AH1 1
150mA J41 VCCD_LVDS_1 1 1 1
LVDS

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

C104

C105
H42 + C106 C107
+1.8V_LVDS VCCD_LVDS_2
1 1 1
C108

C109

C110
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 2
+3VS_TVDACC +3VS CRESTLINE_1p0
B BLM18PG181SN1D_0603 2 2 2 B
2 1
0.022U_0402_16V7K

R74
0.1U_0402_16V4Z

1 1
C111

C112

+VCCP_D
2 2

D2 R75 R76
+VCCP 2 1 2 1 2 1 +3VS_HV
10_0402_5% 0_0402_5%
CH751H-40PT_SOD323-2
+3VS
+1.5VS_QDAC +1.5VS
+3VS_TVDACA +3VS R77
BLM18PG181SN1D_0603 2 1
0.022U_0402_16V7K

2 1 100_0603_1%
0.022U_0402_16V7K

0.1U_0402_16V4Z

R78
+1.8V_TXLVDS
0.1U_0402_16V4Z

1 1
1 1 R79
C113

C114
C115

C116

2 1 +1.8V
2 2 0_0603_5%
2 2
1 1
C118
1000P_0402_50V7K C117
10U_0805_10V4Z
2 2
0208_Change C117 value from 220uF to 10uF.
+1.8V_LVDS
A +3VS_TVDACB +3VS A
BLM18PG181SN1D_0603 R81
2 1 2 1 +1.8V
0.022U_0402_16V7K

10U_0805_10V4Z

R80 0_0603_5%
0.1U_0402_16V4Z

1U_0603_10V4Z

1 1
C119

C120

1 1
C121

C122

2 2
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(4/6)-PWR
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 10 of 40
5 4 3 2 1
 5 4 3 2 1

+VCCP
U3G +VCCP VCC_AXG=7700mA
VCC=1260mA
AT35 VCC_1
AT34 VCC_2 VCC_AXG_NCTF_1 T17
AH28 VCC_3 VCC_AXG_NCTF_2 T18
AC32 T19 0.1U_0402_16V4Z
VCC_5 VCC_AXG_NCTF_3
AC31 VCC_4 VCC_AXG_NCTF_4 T21
AK32 VCC_6 VCC_AXG_NCTF_5 T22 1 C123 1 C124 1
AJ31 T23 C125
+VCCP VCC_7 VCC_AXG_NCTF_6
AJ28 VCC_8 VCC_AXG_NCTF_7 T25
D U3F D
AH32 VCC_9 VCC_AXG_NCTF_8 U15
2 2 2

VCC CORE
VCC=1260mA AH31 VCC_10 VCC_AXG_NCTF_9 U16
AB33 VCC_NCTF_1 AH29 VCC_11 VCC_AXG_NCTF_10 U17
AB36 AF32 U19 0.22U_0603_10V7K 4.7U_0805_10V4Z
VCC_NCTF_2 VCC_12 VCC_AXG_NCTF_11
AB37 VCC_NCTF_3 VCC_AXG_NCTF_12 U20
AC33 VCC_NCTF_4 VSS_NCTF_1 T27 VCC_AXG_NCTF_13 U21
AC35 T37 R82 U23
VCC_NCTF_5 VSS_NCTF_2 VCC_AXG_NCTF_14
AC36 VCC_NCTF_6 VSS_NCTF_3 U24 1 2 R30 VCC_13 VCC_AXG_NCTF_15 U26
AD35 U28 0_0603_5% V16
VCC_NCTF_7 VSS_NCTF_4 VCC_AXG_NCTF_16
AD36 VCC_NCTF_8 VSS_NCTF_5 V31 VCC_AXG_NCTF_17 V17
AF33 VCC_NCTF_9 VSS_NCTF_6 V35 VCC_AXG_NCTF_18 V19
AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 VCC_AXG_NCTF_19 V20
0.22U_0402_10V4Z

0.22U_0603_10V7K

0.1U_0402_16V4Z

AH33 VCC_NCTF_11 VSS_NCTF_8 AB17 VCC_AXG_NCTF_20 V21

220U_6.3V_M

10U_0805_10V4Z

VSS NCTF
1 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35 VCC_AXG_NCTF_21 V23
1 1 1 1 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19 VCC_AXG_NCTF_22 V24
C126

C127

C128

C129

C130

+ AH37 AD37 Y15

2 2 2 2 2
AJ33
AJ35
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
AF17
AF35
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
Y16
Y17
AK33 VCC_NCTF_17 VSS_NCTF_14 AK17 AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19
AK35 VCC_NCTF_18 VSS_NCTF_15 AM17 3720mA AU33 VCC_SM_2 VCC_AXG_NCTF_27 Y20
AK36 VCC_NCTF_19 VSS_NCTF_16 AM24 +1.8V AU35 VCC_SM_3 VCC_AXG_NCTF_28 Y21
AK37 VCC_NCTF_20 VSS_NCTF_17 AP26 AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23

0.01U_0402_16V7K
AD33 VCC_NCTF_21 VSS_NCTF_18 AP28 AW33 VCC_SM_5 VCC_AXG_NCTF_30 Y24

10U_0805_10V4Z

10U_0805_10V4Z
AJ36 VCC_NCTF_22 VSS_NCTF_19 AR15 1 AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26

VCC NCTF
AM35 VCC_NCTF_23 VSS_NCTF_20 AR19 1 1 2 AY35 VCC_SM_7 VCC_AXG_NCTF_32 Y28

C132

C133

C134
AL33 AR28 C131 + BA32 Y29
VCC_NCTF_24 VSS_NCTF_21 330U_4V_M VCC_SM_8 VCC_AXG_NCTF_33
AL35 VCC_NCTF_25 BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16
AA33 VCC_NCTF_26 BA35 VCC_SM_10 VCC_AXG_NCTF_35 AA17
2 2 2 1
AA35 VCC_NCTF_27 BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16
AA36 VCC_NCTF_28 BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19
AP35 VCC_NCTF_29 BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16
AP36 VCC_NCTF_30 BC35 VCC_SM_14 VCC_AXG_NCTF_39 AC17

VCC SM
C C
AR35 VCC_NCTF_31 BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19
AR36 VCC_NCTF_32 BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15
Y32 VCC_NCTF_33 BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16
Y33 BE33 AD17
VCC_NCTF_34
POWER VCC_SM_18 VCC_AXG_NCTF_43

VCC GFX NCTF

Y35 VCC_NCTF_35 BE35 VCC_SM_19 VCC_AXG_NCTF_44 AF16
Y36 VCC_NCTF_36 BF33 VCC_SM_20 VCC_AXG_NCTF_45 AF19
Y37 VCC_NCTF_37 VSS_SCB1 A3 BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15
T30 VCC_NCTF_38 VSS_SCB2 B2 BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16
VSS SCB
T34 VCC_NCTF_39 VSS_SCB3 C1 BG33 VCC_SM_23 VCC_AXG_NCTF_48 AH17
T35 VCC_NCTF_40 VSS_SCB4 BL1 BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19
U29 VCC_NCTF_41 VSS_SCB5 BL51 BH32 VCC_SM_25 VCC_AXG_NCTF_50 AJ16
U31 VCC_NCTF_42 VSS_SCB6 A51 BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17
U32 VCC_NCTF_43 BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19
U33 VCC_NCTF_44 BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16
U35 VCC_NCTF_45 BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19
U36 VCC_NCTF_46 BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16
V32 VCC_NCTF_47 BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17
V33 VCC_NCTF_48 BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19
V36 VCC_NCTF_49 BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20
V37 VCC_NCTF_50 BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21
+VCCP
VCC_AXM=970mA BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23
VCC_AXM_1 AT33 +VCCP AU30 VCC_SM_36 VCC_AXG_NCTF_61 AM15
VCC_AXM=970mA VCC_AXM_2 AT31 VCC_AXG_NCTF_62 AM16
VCC AXM

VCC_AXM_3 AK29 VCC_AXG_NCTF_63 AM19

VCC_AXM_4 AK24 VCC_AXG_NCTF_64 AM20
10U_0805_10V4Z

10U_0805_10V4Z

VCC_AXM_5 AK23 VCC_AXG_NCTF_65 AM21

1 1 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26 R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23
C135

C136

AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23 VCC_AXG=7700mA T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15

AL28 VCC_AXM_NCTF_3 W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16
AM26 +VCCP W14 AP17
2 2 VCC_AXM_NCTF_4 VCC_AXG_4 VCC_AXG_NCTF_69
VCC AXM NCTF

AM28 VCC_AXM_NCTF_5 Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19

AM29 10U_0805_10V4Z 0.1U_0402_16V4Z AA20 AP20
B VCC_AXM_NCTF_6 VCC_AXG_6 VCC_AXG_NCTF_71 B
AM31 VCC_AXM_NCTF_7 AA23 VCC_AXG_7 VCC_AXG_NCTF_72 AP21
AM32 VCC_AXM_NCTF_8 1 AA26 VCC_AXG_8 VCC_AXG_NCTF_73 AP23
AM33 VCC_AXM_NCTF_9 1 1 1 1 AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24
AP29 C138 C137 + C139 AB21 AR20
VCC_AXM_NCTF_10 C140 C141 VCC_AXG_10 VCC_AXG_NCTF_75
AP31 VCC_AXM_NCTF_11 AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21
AP32 1U_0603_10V4Z AB29 AR23
VCC_AXM_NCTF_12 2 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_77
AP33 VCC_AXM_NCTF_13 AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24

VCC GFX
AL29 VCC_AXM_NCTF_14 AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26
AL31 10U_0805_10V4Z AC23 V26
VCC_AXM_NCTF_15 330U_4V_M VCC_AXG_15 VCC_AXG_NCTF_80
AL32 VCC_AXM_NCTF_16 AC24 VCC_AXG_16 VCC_AXG_NCTF_81 V28
AR31 VCC_AXM_NCTF_17 AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AR32 VCC_AXM_NCTF_18 AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AR33 VCC_AXM_NCTF_19 AC29 VCC_AXG_19

1 1 1 1 1 AD20 VCC_AXG_20
C142

C143

C144

C145

C146

AD23 VCC_AXG_21
AD24 VCC_AXG_22 VCC_SM_LF1 AW45 VCCSM_LF1
AD28 VCC_AXG_23 VCC_SM_LF2 BC39 VCCSM_LF2
2 2 2 2 2

VCC SM LF
CRESTLINE_1p0 AF21 BE39 VCCSM_LF3
VCC_AXG_24 VCC_SM_LF3
AF26 VCC_AXG_25 VCC_SM_LF4 BD17 VCCSM_LF4
AA31 VCC_AXG_26 VCC_SM_LF5 BD4 VCCSM_LF5
AH20 VCC_AXG_27 VCC_SM_LF6 AW8 VCCSM_LF6
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 VCCSM_LF7

C147 0.1U_0402_16V4Z

C148 0.1U_0402_16V4Z

C149 0.22U_0603_10V7K

C150 0.22U_0603_10V7K

C151 0.47U_0603_10V7K

C152 1U_0603_10V4Z

C153 1U_0603_10V4Z
AH23 VCC_AXG_29 1 1 1 1 1 1 1
AH24 VCC_AXG_30
AH26 VCC_AXG_31
AD31 VCC_AXG_32 2 2 2 2 2 2 2
AJ20 VCC_AXG_33
AN14 VCC_AXG_34

A A

CRESTLINE_1p0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 11 of 40
5 4 3 2 1
 5 4 3 2 1

U3I

A13 VSS_1 VSS_100 AW24

A15 VSS_2 VSS_101 AW29
A17 VSS_3 VSS_102 AW32
A24 VSS_4 VSS_103 AW5
AA21 VSS_5 VSS_104 AW7
AA24 VSS_6 VSS_105 AY10
AA29 VSS_7 VSS_106 AY24
AB20 AY37 U3J
D VSS_8 VSS_107 D
AB23 VSS_9 VSS_108 AY42 C46 VSS_199 VSS_287 W11
AB26 VSS_10 VSS_109 AY43 C50 VSS_200 VSS_288 W39
AB28 VSS_11 VSS_110 AY45 C7 VSS_201 VSS_289 W43
AB31 VSS_12 VSS_111 AY47 D13 VSS_202 VSS_290 W47
AC10 VSS_13 VSS_112 AY50 D24 VSS_203 VSS_291 W5
AC13 VSS_14 VSS_113 B10 D3 VSS_204 VSS_292 W7
AC3 VSS_15 VSS_114 B20 D32 VSS_205 VSS_293 Y13
AC39 VSS_16 VSS_115 B24 D39 VSS_206 VSS_294 Y2
AC43 VSS_17 VSS_116 B29 D45 VSS_207 VSS_295 Y41
AC47 VSS_18 VSS_117 B30 D49 VSS_208 VSS_296 Y45
AD1 VSS_19 VSS_118 B35 E10 VSS_209 VSS_297 Y49
AD21 VSS_20 VSS_119 B38 E16 VSS_210 VSS_298 Y5
AD26 VSS_21 VSS_120 B43 E24 VSS_211 VSS_299 Y50
AD29 VSS_22 VSS_121 B46 E28 VSS_212 VSS_300 Y11
AD3 VSS_23 VSS_122 B5 E32 VSS_213 VSS_301 P29
AD41 VSS_24 VSS_123 B8 E47 VSS_214 VSS_302 T29
AD45 VSS_25 VSS_124 BA1 F19 VSS_215 VSS_303 T31
AD49 VSS_26 VSS_125 BA17 F36 VSS_216 VSS_304 T33
AD5 VSS_27 VSS_126 BA18 F4 VSS_217 VSS_305 R28
AD50 VSS_28 VSS_127 BA2 F40 VSS_218
AD8 VSS_29 VSS_128 BA24 F50 VSS_219
AE10 VSS_30 VSS_129 BB12 G1 VSS_220
AE14 VSS_31 VSS_130 BB25 G13 VSS_221 VSS_306 AA32
AE6 VSS_32 VSS_131 BB40 G16 VSS_222 VSS_307 AB32
AF20 BB44 G19 AD32
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G24
G28
VSS_223
VSS_224
VSS_225
VSS_308
VSS_309
VSS_310
AF28
AF29
AF31 VSS_36 VSS_135 BC16 G29 VSS_226 VSS_311 AT27
AG2 VSS_37 VSS_136 BC24 G33 VSS_227 VSS_312 AV25
AG38 VSS_38 VSS_137 BC25 G42 VSS_228 VSS_313 H50
AG43 VSS_39 VSS_138 BC36 G45 VSS_229
AG47 VSS_40 VSS_139 BC40 G48 VSS_230
C C
AG50 VSS_41 VSS_140 BC51 G8 VSS_231
AH3 VSS_42 VSS_141 BD13 H24 VSS_232
AH40 VSS_43 VSS_142 BD2 H28 VSS_233
AH41 VSS_44 VSS_143 BD28 H4 VSS_234
AH7 VSS_45 VSS_144 BD45 H45 VSS_235
AH9 VSS_46 VSS_145 BD48 J11 VSS_236
AJ11 VSS_47 VSS_146 BD5 J16 VSS_237
AJ13 VSS_48 VSS_147 BE1 J2 VSS_238
AJ21 VSS_49 VSS_148 BE19 J24 VSS_239
AJ24 VSS_50 VSS_149 BE23 J28 VSS_240
AJ29 BE30 J33
AJ32
AJ43
VSS_51
VSS_52
VSS_53
VSS_150
VSS_151
VSS_152
BE42
BE51
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ45 VSS_54 VSS_153 BE8
AJ49 VSS_55 VSS_154 BF12 K12 VSS_245
AK20 VSS_56 VSS_155 BF16 K47 VSS_246
AK21 VSS_57 VSS_156 BF36 K8 VSS_247
AK26 VSS_58 VSS_157 BG19 L1 VSS_248
AK28 VSS_59 VSS_158 BG2 L17 VSS_249
AK31 VSS_60 VSS_159 BG24 L20 VSS_250
AK51 VSS_61 VSS_160 BG29 L24 VSS_251
AL1 VSS_62 VSS_161 BG39 L28 VSS_252
AM11 VSS_63 VSS_162 BG48 L3 VSS_253
AM13 VSS_64 VSS_163 BG5 L33 VSS_254
AM3 VSS_65 VSS_164 BG51 L49 VSS_255
AM4 VSS_66 VSS_165 BH17 M28 VSS_256
AM41 VSS_67 VSS_166 BH30 M42 VSS_257
AM45 VSS_68 VSS_167 BH44 M46 VSS_258
AN1 VSS_69 VSS_168 BH46 M49 VSS_259
AN38 VSS_70 VSS_169 BH8 M5 VSS_260
AN39 VSS_71 VSS_170 BJ11 M50 VSS_261
AN43 VSS_72 VSS_171 BJ13 M9 VSS_262
B B
AN5 VSS_73 VSS_172 BJ38 N11 VSS_263
AN7 VSS_74 VSS_173 BJ4 N14 VSS_264
AP4 VSS_75 VSS_174 BJ42 N17 VSS_265
AP48 VSS_76 VSS_175 BJ46 N29 VSS_266
AP50 VSS_77 VSS_176 BK15 N32 VSS_267
AR11 VSS_78 VSS_177 BK17 N36 VSS_268
AR2 VSS_79 VSS_178 BK25 N39 VSS_269
AR39 VSS_80 VSS_179 BK29 N44 VSS_270
AR44 VSS_81 VSS_180 BK36 N49 VSS_271
AR47 VSS_82 VSS_181 BK40 N7 VSS_272
AR7 VSS_83 VSS_182 BK44 P19 VSS_273
AT10 VSS_84 VSS_183 BK6 P2 VSS_274
AT14 VSS_85 VSS_184 BK8 P23 VSS_275
AT41 VSS_86 VSS_185 BL11 P3 VSS_276
AT49 VSS_87 VSS_186 BL13 P50 VSS_277
AU1 VSS_88 VSS_187 BL19 R49 VSS_278
AU23 VSS_89 VSS_188 BL22 T39 VSS_279
AU29 VSS_90 VSS_189 BL37 T43 VSS_280
AU3 VSS_91 VSS_190 BL47 T47 VSS_281
AU36 VSS_92 VSS_191 C12 U41 VSS_282
AU49 VSS_93 VSS_192 C16 U45 VSS_283
AU51 VSS_94 VSS_193 C19 U50 VSS_284
AV39 VSS_95 VSS_194 C28 V2 VSS_285
AV48 VSS_96 VSS_195 C29 V3 VSS_286
AW1 VSS_97 VSS_196 C33
AW12 VSS_98 VSS_197 C36
AW16 C41 CRESTLINE_1p0
VSS_99 VSS_198

CRESTLINE_1p0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 12 of 40
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7] V_DDR_MCH_REF <7,14,35>

<8> DDR_A_D[0..63] JP4

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
<8> DDR_A_DM[0..7] VSS DQ4

C154

C155
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<7,8> DDR_A_MA[0..14] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 DQ3 DQ12 20
21 22 DDR_A_D12
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
Place near JP34 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40
+1.8V
41 VSS VSS 42
DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 47 VSS VSS 48
1 1 1 1 1 1 1 1 1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7>
C157

C158

C159

C160

C161

C162

C163

C164

C165
+ C156 DDR_A_DQS2 51 52 DDR_A_DM2
330U_4V_M DQS2 DM2
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
2 2 2 2 2 2 2 2 2 2 DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS2 85 86 DDR_A_MA14
<8> DDR_A_BS2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <8>
DDR_A_BS0 107 108 DDR_A_RAS#
<8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9V <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7> M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D39
DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C166

C167

C168

C169

C170

C171

C172

C173

C174

C175

C176

C177

C178

133 134 DDR_A_D34

DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
DDR_A_D48 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
+0.9V NC,TEST CK1 M_CLK_DDR1 <7>
Layout Note: 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_DQS#6 167 168
RP1 RP2 56_0404_4P2R_5%
Pla ce these resistor DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
DDR_A_MA3 1 4 4 1 DDR_CKE0_DIMMA closely JP34,all 171 172
DDR_A_MA10 VSS VSS
2 3 3 2 DDR_A_BS2 trace length Max=1.5" DDR_A_D54 173 DQ50 DQ54 174 DDR_A_D51
DDR_A_D50 175 176 DDR_A_D55
RP3 56_0404_4P2R_5% RP4 56_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
DDR_A_MA8 1 4 4 1 DDR_A_MA7 DDR_A_D61 179 180 DDR_A_D57
DDR_A_MA5 DQ56 DQ60
2 3 3 2 DDR_A_MA6 DDR_A_D60 181 DQ57 DQ61 182 DDR_A_D56
183 VSS VSS 184
RP5 56_0404_4P2R_5% RP6 56_0404_4P2R_5% DDR_A_DM7 185 186 DDR_A_DQS#7
DDR_A_RAS# DM7 DQS7#
1 4 4 1 DDR_A_MA12 187 VSS DQS7 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 3 3 2 DDR_A_MA9 DDR_A_D59 189 190
DDR_A_D58 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
RP7 56_0404_4P2R_5% RP8 56_0404_4P2R_5% 193 194 DDR_A_D63
DDR_A_MA1 VSS DQ63
1 4 4 1 DDR_A_MA4 <14,15> CLK_SMBDATA
CLK_SMBDATA 195 SDA VSS 196
DDR_A_BS0 2 3 3 2 DDR_A_MA2 CLK_SMBCLK 197 198
<14,15> CLK_SMBCLK SCL SAO
+3VS 199 VDDSPD SA1 200
RP9 56_0404_4P2R_5% RP10 56_0404_4P2R_5% 203 204
GND GND

1
10K_0402_5%

10K_0402_5%
2.2U_0805_16V4Z

DDR_A_WE# 1 4 4 1 DDR_A_MA0 1 1
0.1U_0402_16V4Z

DDR_A_CAS# 2 3 3 2 DDR_A_BS1 C180

R83

R84
A C179 FOX_ASOA426-M4R-TR A
RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5% CONN@
DDR_CS1_DIMMA# 2 2 2
3 4 1 M_ODT0
SO-DIMM A

2
M_ODT1 1 4 3 2 DDR_A_MA13
SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4
56_0404_4P2R_5% RP13 56_0404_4P2R_5% FOX_AS0A426-M4R-TR_200P
4 1 DDR_CKE1_DIMMA
DDR_A_MA11 1 2 3 2 DDR_A_MA14

R85 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 13 of 40
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF <7,13,35>
<8> DDR_B_DM[0..7] JP5

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
<7,8> DDR_B_MA[0..14] 5 DQ0 DQ5 6

C181

C182
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP10 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C183

C184

C185

C186

C187

C188

C189

C190

C191
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS#1 <7>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS2
83 NC NC/A15 84
DDR_B_MA14
<8> DDR_B_BS2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1
+0.9V A10/AP BA1 DDR_B_BS1 <8>
DDR_B_BS0 107 108 DDR_B_RAS#
<8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C192

C193

C194

C195

C196

C197

C198

C199

C200

C201

C202

C203

C204

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9V 163 164 M_CLK_DDR2
closely JP10,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP14 RP15 56_0404_4P2R_5% trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_MA1 1 4 4 1 DDR_B_MA9 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_MA3 DDR_B_MA12 DQS6 DM6
2 3 3 2 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5% DDR_B_D50 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
DDR_B_BS0 1 4 4 1 DDR_B_MA14 177 178
DDR_B_MA10 DDR_B_MA11 DDR_B_D56 VSS VSS DDR_B_D60
2 3 3 2 179 DQ56 DQ60 180
DDR_B_D61 181 182 DDR_B_D57
RP18 56_0404_4P2R_5% RP19 56_0404_4P2R_5% DQ57 DQ61
183 VSS VSS 184
DDR_B_MA0 1 4 4 1 DDR_B_MA5 DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_BS1 DDR_B_MA8 DM7 DQS7# DDR_B_DQS7
2 3 3 2 187 VSS DQS7 188
DDR_B_D59 189 190
RP20 56_0404_4P2R_5% RP21 56_0404_4P2R_5% DDR_B_D58 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
DDR_B_RAS# 1 4 4 1 DDR_B_MA7 193 194 DDR_B_D63
DDR_CS2_DIMMB# 2 DDR_B_MA6 CLK_SMBDATA VSS DQ63
3 3 2 <13,15> CLK_SMBDATA 195 SDA VSS 196
CLK_SMBCLK 197 198 R86
<13,15> CLK_SMBCLK SCL SA0
RP22 56_0404_4P2R_5% RP23 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_CAS# 1 4 4 1 DDR_B_MA4 201 202
GND GND

1
10K_0402_5%
2.2U_0805_16V4Z

0.1U_0402_16V4Z

DDR_B_WE# 2 3 3 2 DDR_B_MA2 1 1 10K_0402_5%

R87
A RP24 C206 A
56_0404_4P2R_5% RP25 56_0404_4P2R_5% C205 FOX_AS0A426-N8RN-7F
DDR_CS3_DIMMB# 2 3 4 1 M_ODT2 CONN@
M_ODT3 1 4 3 2 DDR_B_MA13 2 2 SO-DIMM B

2
SP07000BZ00 S SOCKET FOXCON AS0A426-N8RN-7F H8 DDR2R
56_0404_4P2R_5% RP26 FOX_AS0A426-N8RN-7F_200P
4 1 DDR_B_BS2
DDR_CKE3_DIMMB 1 2 3 2 DDR_CKE2_DIMMB
R88
56_0402_5% 56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 14 of 40
5 4 3 2 1
 5 4 3 2 1

FSLC FSLB FSLA CPU SRC PCI +3VS_CK505

R89
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz +3VS
+3VS 1 2
1 1 1 1 1 1 1
0 0 1 133 100 33.3 FBMA-L11-201209-221LMA30T_0805 C207 C208 C210 C212 C213
C209 C211 R90 R91
10U_0805_10V4Z 0.1U_0402_16V4Z 680P_0402_50V7K 0.1U_0402_16V4Z 680P_0402_50V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2.2K_0402_5% 2.2K_0402_5%
0 1 0 200 100 33.3

0 1 1 166 100 33.3 Q3

+1.25VS
Place close to U4 3 2N7002_SOT23-3 CLK_SMBDATA

S
<20,22> ICH_SMBDATA 1
D FSB Frequency Selet: +1.25VS_CK505 D
R92

G
2
CPU Driven Stuff R1107 R1135 R1083 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805
1 1 1
C216
1
C217
1 1
C219
SB, MINI PCI +3VS

R1074 R1086 R1098 R1113 R1128 R1139 C215 C218

*(Default) No Stuff

2
C214

G
2 2 2 2 2 2 Q4
Stuff R1086 R1139 R1135 R1074 R1139 R1135 10U_0805_10V4Z 680P_0402_50V7K 680P_0402_50V7K <20,22> ICH_SMBCLK 1 3 2N7002_SOT23-3 CLK_SMBCLK

S
667MHz
No Stuff R1083 R1107 R1128 0308_Change R89 and R92 form 0 ohm to bead, C209, C211, C216, C218 from 0.1uF to 680pF.
R1113 R1098
+3VS_CK505 U4
Stuff
R1135 R1139
2 VDD_PCI NC 48
800MHz 9 VDD48
No Stuff R1083 R1086 R1098 R1128 16 VDDPLL3
61 VDDREF
R1074 R1107 R1113 64 CLK_SMBCLK
SCLK CLK_SMBDATA CLK_SMBCLK <13,14>
39 VDDSRC SDATA 63
55 CLK_SMBDATA <13,14>
VDDCPU
PCI_STOP# 38
37 H_STP_PCI# <20>
CPU_STOP# H_STP_CPU# <20>
+1.25VS_CK505 12 VDD96_IO
R93 20 VDDPLL3_IO
26 R94 C220 2 1 CLK_48M_ICH
VDDSRC_IO R_CPU_BCLK 0_0402_5% @ 5P_0402_50V8C
1 2 +VCCP CPU0 54 1 2 CLK_CPU_BCLK <4>
36 53 R_CPU_BCLK# 1 2 0_0402_5% C221 2 1 CLK_14M_ICH
VDDSRC_IO CPU0# CLK_CPU_BCLK# <4>
1

56_0402_5% CLRP4,CLRP5 for 667/800 FSB select 49 R95 @ 4.7P_0402_50V8C

C VDDCPU_IO C
CLRP1 C222 2 1 CLK_PCI_ICH
R97 NO SHORT PADS
SHORT CLRP5, NO SHORT CLRP4 -- CPU option R96 @ 4.7P_0402_50V8C
2

2.2K_0402_5% SHORT CLRP4, NO SHORT CLRP5 -- FSB 667 51 R_MCH_BCLK 1 2 0_0402_5% C225 2 1 CLK_PCI_EC
CPU1_F CLK_MCH_BCLK <7>
FSA 2 1 1 2 50 R_MCH_BCLK# 1 2 0_0402_5% @ 4.7P_0402_50V8C
MCH_CLKSEL0 <7> CPU1#_F CLK_MCH_BCLK# <7>
R99 C227 2 1 CLK_PCI_LAN
2 1 R98 0301_Change R105 from 22 ohm to 0 ohm. @ 4.7P_0402_50V8C
<5> CPU_BSEL0
1K_0402_5% 47 R_CPU_XDP R100 1 2 0_0402_5% C229 2 1 CLK_DEBUG_PORT
CLRP2 0312_Change R106, 107, 109 from 22 to 33 ohm. SRC8/ITP
46 R_CPU_XDP# 1 2 0_0402_5%
CLK_CPU_XDP <4>
@ 5P_0402_50V8C
SRC8#/ITP# CLK_CPU_XDP# <4>
1

NO SHORT PADS R101

R102 475_0402_1%1 2 R103 1
<20> CLKSATAREQ# PCI0/CR#_A
@ 1K_0402_5% 475_0402_1%1 2 R104 PCI_CLK1 3 35
<7> CLKREQ#_B PCI1/CR#_B SRC10#
34
2

0_0402_5% PCI2_TME SRC10

1 2 R105 4 PCI2/TME
<22,29,30> CLK_DEBUG_PORT
33_0402_5% 1 2 R106 PCI_LANCLK 5
+VCCP <23> CLK_PCI_LAN PCI3
SRC11/CR#_H 33
33_0402_5% 1 2 R107 27_SEL 6 32 For Layout request:
<30> CLK_PCI_EC PCI4/27_Select SRC11#/CR#_G
1. Change MINI_CLKREQ# from pin 32 to pin 43.
2

33_0402_5% 1 2 R109 ITP_EN 7

<18> CLK_PCI_ICH PCIF5/ITP_EN
R111 2. Change CLK_PCIE_MCARD from SRC9 to SRC6.
Y1 30
@ 1K_0402_5% CLK_XTAL_IN SRC9
2 1 SRC9# 31
Routing the trace at 60
1

FSB 14.31818MHZ_16P X1
1 2 MCH_CLKSEL1 <7> least 10mil CLK_XTAL_OUT 59
R114 X2 R108 475_0402_1%
<5> CPU_BSEL1 1 2 2 2 SRC7/CR#_F 44
R115 1K_0402_5% 43 R_CLKREQ#_G 2 1
SRC7#/CR#_E MINI_CLKREQ# <22>
0_0402_5% C230 C231 R110 10K_0402_5%
1

18P_0402_50V8J 18P_0402_50V8J 1 2 +3VS

@ R116 1 1
R112
B 0_0402_5% R_CLK_PCIE_MCard 1 0_0402_5% B
SRC6 41 2 CLK_PCIE_MCARD <22>
33_0402_1% 1 2 R117 FSA 10 40 R_CLK_PCIE_MCard# 1 2 0_0402_5%
CLK_PCIE_MCARD# <22>
2

<20> CLK_48M_ICH USB_48MHZ/FSLA SRC6# R113

FSB 57 R118
+VCCP FSLB/TEST MODE R_MCH_3GPLL 0_0402_5%
SRC4 27 1 2 CLK_MCH_3GPLL <7>
28 R_MCH_3GPLL# 1 2 0_0402_5%
SRC4# CLK_MCH_3GPLL# <7>
33_0402_1% 1 2 R120 FSC 62 R119
REF0/FSLC/TEST_SEL
2

<20> CLK_14M_ICH
R121 33_0402_1% 1 2 @ R400 R122
<30> CLK_14M_DEBUG 24 R_PCIE_ICH 1 2 0_0402_5%
SRC3/CR#_C CLK_PCIE_ICH <20>
R124 @ 1K_0402_5% +1.25VS_CK505 45 25 R_PCIE_ICH# 1 2 0_0402_5%
VDDSRC_IO SRC3#/CR#_D CLK_PCIE_ICH# <20>
10K_0402_5% R123
1

FSC 2 1 1 2 MCH_CLKSEL2 <7>

R127
1 2 R125 21 R_PCIE_SATA 1 2 0_0402_5%
<5> CPU_BSEL2 SRC2/SATA CLK_PCIE_SATA <19>
R126 1K_0402_5% 42 22 R_PCIE_SATA# 1 2 0_0402_5%
GNDSRC SRC2#/SATA# CLK_PCIE_SATA# <19>
0_0402_5% R128
1

8 GNDPCI
@ R129
11 17 SSCDREFCLK
R130 1 2 0_0402_5%
GND48 SRC1/SE1/27MHz_NonSS MCH_SSCDREFCLK <7>
0_0402_5% 18 SSCDREFCLK#
R131 1 2 0_0402_5%
SRC1#/SE2/27MHz_SS MCH_SSCDREFCLK# <7>
15
2

GND
19 R132
GND R_MCH_DREFCLK 0_0402_5%
SRC0/DOT96 13 1 2 CLK_MCH_DREFCLK <7>
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# 52 14 R_MCH_DREFCLK# 1 2 0_0402_5%
+3VS +3VS +3VS GNDCPU SRC0/DOT96# CLK_MCH_DREFCLK# <7>
R133
For 27_SEL, 0 = Enable DOT96 & SRC1, 23 GNDSRC
2

1= Enable SRC0 & 27MHz 29 GNDSRC

R134 R135 R136 56 1 2
A CK_PWRGD/PD# @ R137 0_0402_5% VGATE <20,37> A
10K_0402_5% 10K_0402_5% 10K_0402_5% For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed 58 GNDREF
@
1 = Overclocking of CPU and SRC NOT allowed ICS9LPRS355_TSSOP64 1 2
1

@ R367 0_0402_5% CLK_ENABLE <30>

ITP_EN 27_SEL PCI2_TME * Internal Pull-Up Resistor 1 2
** Internal Pull-Down Resistor R344 0_0402_5% CK_PWRGD <20>
2

R138 R139 R140 Security Classification Compal Secret Data Compal Electronics, Inc.
10K_0402_5% 10K_0402_5% 10K_0402_5% Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
@ @
Clock generator
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 15 of 40
5 4 3 2 1
 A B C D E

1 EMI 1
CRTL_B
CRTL_G
CRTL_R
+R_CRT_VCC , +CRTVDD (40mils) NZQA5V6AXV5T1_SOT533-5

DAN217_SC59

DAN217_SC59

@ DAN217_SC59
+5VS +CRTVDD

D4

D5

D6
EMI

1
+R_CRT_VCC
D7 F1 3 4
Place close to JP6 2 1 1 2

@ @ RB411D_SOT23 1.1A_6VDC_FUSE 1
+CRTVDD
2
CRT CONNECTOR
2

3
C232
0.1U_0402_16V4Z
2
1 5
EMI
CONN@ JP6
L2 6 @ D3
MBK2012800YZF 11
CRT_R 1 2 CRTL_R 1 16
<9> CRT_R
L3 7 17
MBK2012800YZF EMI 12
CLOSE TO JP3
CRT_G 1 2 CRTL_G 2
<9> CRT_G
L4 8
MBK2012800YZF 13
CRT_B 1 2 CRTL_B 3
<9> CRT_B

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
+CRTVDD 9

2
75_0402_5%

75_0402_5%

75_0402_5%
1 1 1 1 1 1 14 DC060001M00 D-CONN 15P D-SUB_F C10510-11505-L
4
+5VS EMI DC060002300 D-CONN 15P VGA_F 070546FR015S235ZR SUYIN

R144 4.7K_0402_5%

R145 4.7K_0402_5%
2 2
10
R141

R142

R143
C239 15
C233 2 2 2 2 2 2

C234

C235

C236

C237

C238
1 2 5
1

1
5

0.1U_0402_16V4Z U5 ALLTO_C10510-115A5-L
R146 @ @ @ Q5 R147
P

OE#

CR THSYNC CRT_HSYNC_R CRT_HSYNCRFL 3 2N7002_SOT23-3 3V_DDCDA

S
<9> CRT_HSYNC 1 2 2 A Y 4 1 2 1 1 2 3VDDCDA <9>
0_0402_5% L5 0_0402_5%
G

74AHCT1G125GW_SOT353-5 FBM-L11-160808-800LMT_0603

G
3

2
C241 10P_0402_50V8J
1 2 CRT_VSYNCRFL Q6 R148

220P_0402_50V8J

220P_0402_50V8J
L6 3 2N7002_SOT23-3
3V_DDCCL

S
1 1 2 3VDDCCL <9>

10P_0402_50V8J
FBM-L11-160808-800LMT_0603 1 1 1 1 0_0402_5%

R149 R150

G
2
5

U6 2 2 2 2

C240
R151 2.2K_0402_5%
P

OE#

1 2 CRTVSYNC 2 4 CRT_VSYNC_R
<9> CRT_VSYNC A Y
0_0402_5%
+3VS
G

C242

C243
74AHCT1G125GW_SOT353-5
2.2K_0402_5%
3

3 3

TV-Out Connector
S-Video
EMI L7
R152 MBC1608121YZF_0603
1 2 TVLUMA 1 2 LUMA_CL
<9> TV_LUMA
0_0402_5%
L8 JP7
R153 MBC1608121YZF_0603 1
TVCRMA CRMA_CL 1
<9> TV_CRMA 1 2 1 2 2 2
0_0402_5% 3 3
4 4
L9 5
R154 MBC1608121YZF_0603 5
6 6 GND 8
1 2 TVCOMPS 1 2 COMPS_CL 7 9
<9> TV_COMPS 0_0402_5% 7 GND
270P_0402_50V7K

270P_0402_50V7K

270P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K

330P_0402_50V7K
SUYIN_030107FR007G317ZR
CONN@
1

1
75_0402_5%

75_0402_5%

75_0402_5%

1 1 1 1 1 1
R155

R156

R157

C244

C245

C246

C247

C248

C249
DC230001300 CONN SUYIN 030107FR007G317ZR 7P S_VIDEO
SUYIN_030107FR007G317ZR_7P

2 2 2 2 2 2
R158
2

4 TVGND 4
1 2

0_0805_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 16 of 40
A B C D E
 5 4 3 2 1

LVDS CONN
D D

+LCDVDD
B+ INVPWR_B+
@
L10 1 2 0_0805_5% 1 1
C250 C251
L11
1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805 2 2

0308_Reserve L10 and install L11.

JP8
INVPWR_B+ 1 1 2 2
3 4 LVDSA2+ LVDSA2+ <9>
3 4 LVDSA2-
5 5 6 6 LVDSA2- <9>
7 7 8 8
9 10 LVDSA1+ LVDSA1+ <9>
+LCDVDD 9 10 LVDSA1-
11 11 12 12 LVDSA1- <9>
+3VS 13 13 14 14
15 16 LVDSA0+ +3VS
15 16 LVDSA0+ <9>
LVDSBC+ 17 18 LVDSA0-
<9> LVDSBC+ 17 18 LVDSA0- <9>
LVDSBC- 19 20
<9> LVDSBC- 19 20
21 22 LVDSAC+
LVDSB0+ 21 22 LVDSAC- LVDSAC+ <9>
<9> LVDSB0+ 23 23 24 24

2
LVDSB0- 25 26 LVDSAC- <9>
<9> LVDSB0- 25 26
27 28 INVTPWM R159 R160
27 28 INV_PWM <30>

C252

C253

C254
LVDSB1+ 29 30 DISPLAYOFF# 2.2K_0402_5% 2.2K_0402_5%
<9> LVDSB1+ 29 30
LVDSB1- 31 32 DAC_BRIG
C <9> LVDSB1- 31 32 DAC_BRIG <30> C
33 34 LCD_CLK
LCD_CLK <9>

1
LVDSB2+ 33 34 LCD_DAT LCD_CLK
<9> LVDSB2+ 35 35 36 36 LCD_DATA <9>
LVDSB2- 37 38 LCD_DATA
<9> LVDSB2- 37 38

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
39 39 40 40
1 41 GND GND 42 1 1
1

1
ACES_88242-4001 C255 C256
CONN@ 680P_0402_50V7K 680P_0402_50V7K
2

2
2 2 2
LVDS connector
SP02000EA00 S W-CONN ACES 88242-4001 40P P1
ACES_88242-4001_40P
0308_Install all cap for EMI request. 0308_Install all cap for EMI request.

+LCDVDD
B +LCDVDD +3VS B
+5VALW Q7 +3VS
SI2301BDS-T1-E3_SOT23-3
1

2
1 S
3
D

R161 R162
2

100_0402_5% R163 4.7K_0402_5%

G
2

47K_0402_5%
2

1
D8
1 2 DISPLAYOFF#
1
1

D <30> BKOFF#
Q8 2 CH751H-40PT_SOD323-2
2N7002_SOT23-3 G
S D9
3

<9> ENABLT 1 2
1 1
1

2
R298 D C258 CH751H-40PT_SOD323-2
1 2 2 C259 C257 R164
<9> ENAVDD
47K_0402_5% G 4.7U_0805_10V4Z 4.7U_0805_10V4Z 100K_0402_5%
S 0.047U_0402_16V7K 2 2
1
3
1

Q9

1
R308 C260 2N7002_SOT23-3
100K_0402_5% 0.1U_0402_16V4Z
2
2

A A
Avoid Panel display garbage after power on.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 17 of 40
5 4 3 2 1
 5 4 3 2 1

PCI_GNT0#

+3VS

1
1 2 PCI_DEVSEL# @ R165
R166 8.2K_0402_5% 1K_0402_5%
1 2 PCI_STOP#

2
R167 8.2K_0402_5% <23> PCI_AD[0..31]
1 2 PCI_TRDY# U7B
R168 8.2K_0402_5% PCI_AD0 D20 A4 PCI_REQ0#
AD0 REQ0# PCI_REQ0# <23>
PCI_FRAME# PCI_AD1 PCI_GNT0#
D
1
R169
2
8.2K_0402_5% PCI_AD2
E19
D19
AD1 PCI GNT0# D7
E18 PCI_REQ1#
PCI_GNT0# <23> D
PCI_PLOCK# PCI_AD3 AD2 REQ1#/GPIO50
1 2 A20 AD3 GNT1#/GPIO51 C18
R170 8.2K_0402_5% PCI_AD4 D17 B19 PCI_REQ2#
PCI _IRDY# PCI_AD5 AD4 REQ2#/GPIO52
1 2 A21 AD5 GNT2#/GPIO53 F18
R171 8.2K_0402_5% PCI_AD6 A19 A11 PCI_REQ3#
PCI_SERR# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3# T23
1 2 C19 AD7 GNT3#/GPIO55 C10
R172 8.2K_0402_5% PCI_AD8 A18
PCI_PERR# PCI_AD9 AD8 PCI_CBE#0
1 2 B16 AD9 C/BE0# C17 PCI_CBE#0 <23>
R173 8.2K_0402_5% PCI_AD10 A12 E15 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 <23>
PCI_AD11 E16 F16 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 <23>
PCI_AD12 A14 E17 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 <23>
PCI_AD13 G16
PCI_AD14 AD13 PCI _IRDY#
A15 AD14 IRDY# C8 PCI_IRDY# <23>
PCI_AD15 B6 D9 PCI_PAR R174
AD15 PAR PCI_PAR <23>
PCI_AD16 C11 G6 PCI_PCIRST# 2 1 PCI_RST#
+3VS AD16 PCIRST# PCI_RST# <23,29,30>
PCI_AD17 A9 D16 PCI_DEVSEL# 0_0402_5%
AD17 DEVSEL# PCI_DEVSEL# <23>
PCI_AD18 D11 A7 PCI_PERR#
AD18 PERR# PCI_PERR# <23>
PCI_AD19 B12 B7 PCI_PLOCK#
PCI_PIRQA# PCI_AD20 AD19 PLOCK# PCI_SERR#
1 2 C12 AD20 SERR# F10 PCI_SERR# <23>
R175 8.2K_0402_5% PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# <23>
1 2 PCI_PIRQB# PCI_AD22 C7 C9 PCI_TRDY#
AD22 TRDY# PCI_TRDY# <23>
R176 8.2K_0402_5% PCI_AD23 F13 A17 PCI_FRAME#
AD23 FRAME# PCI_FRAME# <23>
1 2 PCI_PIRQC# PCI_AD24 E11 R178
R177 8.2K_0402_5% PCI_AD25 AD24 PCI_PLTRST# PLT_RST#
E13 AD25 PLTRST# AG24 2 1 PLT_RST# <7,22>
1 2 PCI_PIRQD# PCI_AD26 E12 B10 CLK_PCI_ICH 0_0402_5%
AD26 PCICLK CLK_PCI_ICH <15>
R179 8.2K_0402_5% PCI_AD27 D8 G7 PCI_PME#
AD27 PME# PCI_PME# <23,30>
1 2 PCI_PIRQE# PCI_AD28 A6
R180 8.2K_0402_5% PCI_AD29 AD28
E8 AD29
1 2 PCI_PIRQF# PCI_AD30 D6
R181 8.2K_0402_5% PCI_AD31 AD30
A3 AD31
1 2 PCI_PIRQG# Place closely pin B10
R182 8.2K_0402_5%
C
2 1 PCI_PIRQH# PCI_PIRQA# F9
Interrupt I/F F8 PCI_PIRQE# Boot BIOS Strap C
<23> PCI_PIRQA# PIRQA# PIRQE#/GPIO2
R183 8.2K_0402_5% PCI_PIRQB# B5 G11 PCI_PIRQF# CLK_PCI_ICH
PCI_REQ0# PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
1 2 C5 PIRQC# PIRQG#/GPIO4 F12

2
R184 8.2K_0402_5% PCI_PIRQD# A10 B3 PCI_PIRQH#
1 2 PCI_REQ1# PIRQD# PIRQH#/GPIO5 R186 PCI_GNT0# SPI_CS#1 Boot BIOS Location
R185 8.2K_0402_5% ICH8M REV 1.0
1 2 PCI_REQ2# @ 10_0402_5%
R187 8.2K_0402_5%
0 1 SPI

1
1 2 PCI_REQ3#
R188 8.2K_0402_5% 1
C261

@ 8.2P_0402_50V 1 0 PCI
2

1 1 LPC *
A16 swap override Strap
*Low= A16 swap override Enble
PCI_GNT3# High= Default

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 18 of 40
5 4 3 2 1
 5 4 3 2 1

+RTCVCC
ICH8M Internal VR Enable Strap
+3VS
R189 330K_0402_1% (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
1 2 LAN100_SLP
R190

2
R191 1M_0402_5% ICH_INTVRMEN Low = Internal VR Disabled GATEA20 2 1
1 2 SM_INTRUDER# @ R192
0_0402_5% High = Internal VR Enabled(Default) 10K_0402_5%
R193 330K_0402_1%
1 2 ICH_INTVRMEN R194

1
2
ICH8M LAN100 SLP Strap KB_RST# 2 1
@ R195
0_0402_5% (Internal VR for VccLAN1.05 and VccCL1.05) 10K_0402_5%
D D

1
ICH_LAN100_SLP Low = Internal VR Disabled
+VCCP
High = Internal VR Enabled(Default) R196
H_FERR# 2 1
LPC_AD[0..3] <22,29,30>
ICH_RTCX1 U7A 56_0402_5%
R197 ICH_RTCX1 AG25 E5 LPC_AD0 @ R198
ICH_RTCX2 ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 H_DPRSTP#
1 2 AF24 RTCX2 FWH1/LAD1 F5 2 1
R199 G8 LPC_AD2
10M_0402_5% ICH_RTCRST# FWH2/LAD2 LPC_AD3 56_0402_5%
+RTCVCC 1 2 AF23 RTCRST# FWH3/LAD3 F6
1 1 @ R200
C262 20K_0402_5% SM_INTRUDER# AD22 C4 LPC_FRAME# H_DPSLP# 2 1
INTRUDER# FWH4/LFRAME# LPC_FRAME# <22,29,30>
15P_0402_50V8J C263 2 CLRP3

RTC
LPC
15P_0402_50V8J C264 SHORT PADS ICH_INTVRMEN AF25 G9 LPC_DRQ0# 56_0402_5%
2 2 INTVRMEN LDRQ0# LPC_DRQ#0 <30>
LAN100_SLP AD21 E6 T25 PAD
1U_0603_10V4Z LAN100_SLP LDRQ1#/GPIO23

1
1 GATEA20
B24 GLAN_CLK A20GATE AF13 GATEA20 <30>
AG26 H_A20M#
A20M# H_A20M# <4>
D22 LAN_RSTSYNC
AF26 H_DPRSTP_R# 2 1 H_DPRSTP#
DPRSTP# H_DPRSTP# <5,7,37>
Y2 C21 AE26 R201 0_0402_5%
LAN_RXD0 DPSLP#
1

B21 H_DPSLP#
LAN_RXD1 H_DPSLP# <5>
0205_Remove R401. C22 AD24 H_FERR#
IN

OUT

LAN_RXD2 FERR# H_FERR# <4>

LAN / GLAN
D21 AG29 H_PW RGOOD
LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD <5>
32.768KHZ_12.5P_1TJS125BJ2A251 E20 LAN_TXD1 H_IGNNE#
NC

NC

C20 LAN_TXD2 IGNNE# AF27 H_IGNNE# <4>

within 2" from R1557
AH21 AE24 H_INIT#
H_INIT# <4>
2

GLAN_DOCK#/GPIO13 INIT# H_INTR +VCCP

INTR AC20 H_INTR <4>

CPU
C KB_RST# C
D25 GLAN_COMPI RCIN# AH14 KB_RST# <30>
0205_Change Crystal type. +1.5VS R202 1 2 24.9_0402_1% GLAN_COMP C25 GLAN_COMPO

1
AD23 H_NMI
NMI H_NMI <4>
<24> ACZ_BITCLK R203 33_0402_5% 1 2 HDA_BITCLK AJ16 AG28 H_SMI# R204
HDA_BIT_CLK SMI# H_SMI# <4>
R205 33_0402_5% 1 2 HDA_SYNC AJ15
<24> ACZ_SYNC HDA_SYNC
AA24 H_STPCLK# 56_0402_5%
STPCLK# H_STPCLK# <4>
R206 33_0402_5% 1 2 HDARST# AE14
<24,30> ACZ_RST#

2
HDA_RST# THRMTRIP_ICH# R207 24_0402_1%
THRMTRIP# AE27 1 2 H_THERMTRIP# <4,7>
ACZ_SDIN0 AJ17
<24> ACZ_SDIN0 HDA_SDIN0
AH17 HDA_SDIN1 TP8 AA23 IDE_HDD[0..15] <22>
AH15 HDA_SDIN2

IHDA
AD13 V1 IDE_HDD0 placed within 2" from ICH8M
HDA_SDIN3 DD0 IDE_HDD1
DD1 U2
R208 33_0402_5% 1 2 HDA_SDOUT AE13 V3 IDE_HDD2
<24> ACZ_SDOUT HDA_SDOUT DD2
T1 IDE_HDD3
DD3 IDE_HDD4
AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
AG14 T5 IDE_HDD5
HDA_DOCK_RST#/GPIO34 DD5 IDE_HDD6
DD6 AB2
SATA_LED# AF10 T6 IDE_HDD7
<28> SATA_LED# SATALED# DD7
T3 IDE_HDD8
SATA_RXN0_C DD8 IDE_HDD9
<22> SATA_RXN0_C AF6 SATA0RXN DD9 R2
SATA_RXP0_C 3900P_0402_50V7K AF5 T4 IDE_HDD10
<22> SATA_RXP0_C SATA0RXP DD10
SATA_TXN0 C265 1 2 SATA_TXN0_C AH5 V6 IDE_HDD11
<22> SATA_TXN0 SATA0TXN DD11
SATA_TXP0 C266 1 2 SATA_TXP0_C AH6 V5 IDE_HDD12
<22> SATA_TXP0 SATA0TXP DD12
U1 IDE_HDD13
3900P_0402_50V7K DD13 IDE_HDD14 +3VS
AG3 SATA1RXN DD14 V2
AG4 U6 IDE_HDD15
SATA1RXP DD15

IDE
AJ4 SATA1TXN
AJ3 AA4 IDE_HDA0
SATA1TXP DA0 IDE_HDA0 <22>
AA1 IDE_HDA1 IDE_ HIORDY R209 1 2 4.7K_0402_5%
DA1 IDE_HDA1 <22>

SATA
AF2 AB3 IDE_HDA2 IDE_HIRQ R210 1 2 8.2K_0402_5%
SATA2RXN DA2 IDE_HDA2 <22>
AF1 SATA2RXP
B IDE_HDCS1# B
AE4 SATA2TXN DCS1# Y6 IDE_HDCS1# <22>
AE3 Y5 IDE_HDCS3#
SATA2TXP DCS3# IDE_HDCS3# <22>
CLK_PCIE_SATA# AB7 W4 IDE_HDIOR#
<15> CLK_PCIE_SATA# SATA_CLKN DIOR# IDE_HDIOR# <22>
CLK_PCIE_SATA AC6 W3 IDE_HDIOW#
<15> CLK_PCIE_SATA SATA_CLKP DIOW# IDE_HDIOW# <22>
Y2 IDE_HDACK#
DDACK# IDE_HDACK# <22>
R211 AG1 Y3 IDE_HIRQ
SATARBIAS# IDEIRQ IDE_HIRQ <22>
1 2 AG2 Y1 IDE_ HIORDY
SATARBIAS IORDY IDE_HIORDY <22>
W5 IDE_HDREQ 0226_Change RTC battery and connector.
DDREQ IDE_HDREQ <22>
24.9_0402_1%
Within 500 mils ICH8M REV 1.0

BATT1

45@ CR2032 RTC BATTERY

+RTCVCC +3VL

BATT1.1
D10
R212 W=20mils 2
1 2 1 R213 JBATT1
W=20mils 3 1 2 W=20mils 1
0_0402_5% W=20mils 1
2 2
2 DAN202U_SC70 1K_0402_5% 3 G1
4 G2
C267
A ACES_85204-02001 A
1U_0603_10V4Z
1
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 19 of 40
5 4 3 2 1
 5 4 3 2 1

+3VALW
Place closely pin G5 Place closely pin AG9
+3VALW 1 2 LINKALERT#
R214 10K_0402_5%
CLK_48M_ICH CLK_14M_ICH

1
2 1 ICH_LOW_BAT#
R215 8.2K_0402_5% R216 R217

1
1 2 ICH_PCIE_WAKE# 2.2K_0402_5% 2.2K_0402_5% R219 R220
R218 1K_0402_5% U7C

2
ICH_SMBCLK AJ26 AJ12 T45 PAD @ 10_0402_5% @ 10_0402_5%
<15,22> ICH_SMBCLK SMBCLK SATA0GP/GPIO21
1 2 I CH_RI# <15,22> ICH_SMBDATA
ICH_SMBDATA AD19 AJ10 T46 PAD

2
R221 10K_0402_5% LINKALERT# SMBDATA SATA1GP/GPIO19
AG21 AF11

GPIO
SATA
LINKALERT# SATA2GP/GPIO36 T47 PAD

SMB
ME_EC_CLK1 AC17 AG11 T48 PAD 1 1
SMLINK0 SATA3GP/GPIO37
1 2 XDP_DBRESET# ME_EC_DATA1 AE19 SMLINK1
C268 C269
R223 1K_0402_5% AG9 CLK_14M_ICH
D CLK14 CLK_14M_ICH <15> D
I CH_RI# AF17 G5 CLK_48M_ICH @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C

Clocks
RI# CLK48 CLK_48M_ICH <15> 2 2
2 1ME_EC_DATA1 +3VS
R224 10K_0402_5% PAD T26 SUS_STAT# F4 D3 ICH_SUSCLK T27 PAD
XDP_DBRESET# AD15 SUS_STAT#/LPCPD# SUSCLK
<4> XDP_DBRESET# SYS_RESET#

2
2 1ME_EC_CLK1 SLP_S3# AG23 SLP_S3#
SLP_S3# <30>
R225 10K_0402_5% @ R226 @ R227 PM_BMBUSY# AG12 AF21 SLP_S4#
<7> PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SLP_S4# <30>
10K_0402_5% 10K_0402_5% AD18 SLP_S5#
SLP_S5# SLP_S5# <30>
<30> EC_LID_OUT# EC_LID_OUT# AG22 SMBALERT#/GPIO11 S4_STATE#
AH27 T28 PAD

1
S4_STATE#/GPIO26

GPIO
+3VS 1 2 GPIO38 H_STP_PCI# AE20
<15> H_STP_PCI# STP_PCI#/GPIO15

SYS
R228 10K_0402_5% 2 1 R_STP_CPU# AG18 AE23 PM_PWROK
<15> H_STP_CPU# STP_CPU#/GPIO25 PWROK PM_PWROK <7,30>
R229 0_0402_5%
1 2 GPIO39 CLKRUN# AH11 AJ14 DPRSLPVR
CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR <7,37>

Power MGT
R230 10K_0402_5% 0205 Change to connect to GND.
ICH_PCIE_WAKE#AE17 AE21 ICH_LOW_BAT# 1 2
<22> ICH_PCIE_WAKE# WAKE# BATLOW#
1 2 GPIO18 SIRQ AF12 @ R398 100K_0402_5%
<30> SIRQ SERIRQ
@ R231 8.2K_0402_5% THERM_SCI# AC13 C2 PWRBTN_OUT#
<30> THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# <30>
2 1
1 2 GPIO22 R395 100K_0402_5% VGATE AJ20 AH20 R233 1 2
<15,37> VGATE VRMPWRGD LAN_RST#
R232 8.2K_0402_5% 0_0402_5%
PAD T29 SST_CTL AJ22 AG27 EC_RMRST# 1 2 R234 EC_RSMRST#
TP7 RSMRST# EC_RSMRST# <30>
1 2 GPIO20 100_0402_5%
@ R235 8.2K_0402_5% OCP# AJ8 E1 CK_PW RGD
<4> OCP# TACH1/GPIO1 CK_PWRGD CK_PWRGD <15>
AJ9 TACH2/GPIO6
1 2 CLKRUN# AH9 E3 M_PWROK
TACH3/GPIO7 CLPWROK M_PWROK <7,30>
R394 8.2K_0402_5% EC_SMI# AE16
<30> EC_SMI# GPIO8
EC_SCI# AC19 AJ25 PM_SLP_M# T30 PAD
<30> EC_SCI# GPIO12 SLP_M#
+3VS 1 2 OCP# AG8
@ R236 10K_0402_5% GPIO18 AH12 TACH0/GPIO17 CL_CLK0 R238 3.24K_0402_1%
GPIO18 CL_CLK0 F23 CL_CLK0 <7>
GPIO20 AE11 AE18 1 2 +3VS
GPIO20 CL_CLK1

GPIO
Controller Link
1 2 MCH_ICH_SYNC# GPIO22 AG10
SCLOCK/GPIO22

1
0.1U_0402_16V4Z
@ R237 10K_0402_5% PAD T31 GPIO27 AH25 F22 CL_DATA0 1
C QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 <7> C
AD16 AF19 C270 R240
SIRQ CLKSATAREQ# AG13 QRT_STATE1/GPIO28 CL_DATA1 453_0402_1%
1 2 <15> CLKSATAREQ# SATACLKREQ#/GPIO35
R239 10K_0402_5% GPIO38 AF9 D24 CL_VREF0_ICH
GPIO39 AJ11 SLOAD/GPIO38 CL_VREF0 CL_VREF1_ICH 2
AH23

2
CLKSATAREQ# IDE_RESET# AD10 SDATAOUT0/GPIO39 CL_VREF1
1 2 <22> IDE_RESET# SDATAOUT1/GPIO48
R241 10K_0402_5% AJ23
CL_RST# CL_RST# <7>
SB_SPKR AD9
<24> SB_SPKR SPKR
1 2 IDE_RESET# AJ27 WL_ON# R243 3.24K_0402_1%
MEM_LED/GPIO24 WL_ON# <22>

MISC
R242 8.2K_0402_5% MCH_ICH_SYNC#AJ13 AJ24 0.1U_0402_16V4Z 1 2 +3VALW
<7> MCH_ICH_SYNC# MCH_SYNC# ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14 AF22 1 2 +3VALW

1
1 2 PM_BMBUSY# 2 1 ICH_RSVD AJ21 AG19 R24510K_0402_5% 1
TP3 WOL_EN/GPIO9

1
R244 8.2K_0402_5% @ R246 1K_0402_5% C271 R247
ICH8M REV 1.0 R396 453_0402_1%

low-->default 100K_0402_5% 2

2
+3VS 1 2 SB_SPKR

2
R248 @ 10K_0402_5% High -->No boot
U7D
PCIE_RXN1 P27 V27 DMI_RXN0 DMI_RXN0 <7>
<22> PCIE_RXN1 PERN1 DMI0RXN
PCIE_RXP1 P26 V26 DMI_RXP0 DMI_RXP0 <7>
<22> PCIE_RXP1 PERP1 DMI0RXP
WLAN <22> PCIE_TXN1 0.1U_0402_16V4Z 2 1 C272 PCIE_C_TXN1 N29 PETN1 DMI0TXN U29 DMI_TXN0 DMI_TXN0 <7>
0.1U_0402_16V4Z 2 1 C273 PCIE_C_TXP1 N28 U28 DMI_TXP0

Direct Media Interface

<22> PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 <7>
DMI_RXN1 <7>
M27 Y27 DMI_RXN1
PERN2 DMI1RXN DMI_RXP1
M26 PERP2 DMI1RXP Y26 DMI_RXP1 <7>
L29 W29 DMI_TXN1 DMI_TXN1 <7>
PETN2 DMI1TXN DMI_TXP1
L28 PETP2 DMI1TXP W28 DMI_TXP1 <7>

PCI-Express
K27 AB26 DMI_RXN2 DMI_RXN2 <7>
PERN3 DMI2RXN DMI_RXP2
K26 PERP3 DMI2RXP AB25 DMI_RXP2 <7>
J29 AA29 DMI_TXN2 DMI_TXN2 <7>
PETN3 DMI2TXN DMI_TXP2
J28 PETP3 DMI2TXP AA28 DMI_TXP2 <7>
B B
H27 AD27 DMI_RXN3 DMI_RXN3 <7>
PERN4 DMI3RXN DMI_RXP3
H26 PERP4 DMI3RXP AD26 DMI_RXP3 <7>
G29 AC29 DMI_TXN3 DMI_TXN3 <7>
PETN4 DMI3TXN DMI_TXP3
G28 PETP4 DMI3TXP AC28 DMI_TXP3 <7>
F27 T26 CLK_PCIE_ICH#
PERN5 DMI_CLKN CLK_PCIE_ICH# <15>
F26 T25 CLK_PCIE_ICH
PERP5 DMI_CLKP CLK_PCIE_ICH <15>
E29 PETN5
E28 Y23 R249 24.9_0402_1% Within 500 mils
PETP5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP Y24 1 2 +1.5VS
D27 PERN6/GLAN_RXN
+3VALW D26 G3 USB20_N0
PERP6/GLAN_RXP USBP0N USB20_N0 <27>
C29 G2 USB20_P0 To USB/B.
PETN6/GLAN_TXN USBP0P USB20_P0 <27>
USB_OC#3 1 2 C28 H5 USB20_N1
+3VALW PETP6/GLAN_TXP USBP1N USB20_N1 <27>
R392 10K_0402_5% H4 USB20_P1 To USB/B.
USBP1P USB20_P1 <27>
2

USB_OC#4 1 2 PAD T40 SPICLK C23 H2 USB20_N2

SPI_CLK USBP2N USB20_N2 <27>
R385 10K_0402_5% @ R250 PAD T41 SPI_CS0# B23 H1 USB20_P2 To MB.
SPI_CS0# USBP2P USB20_P2 <27>
USB_OC#5 1 2 10K_0402_5% PAD T42 SPI_CS1# E22 J3
SPI_CS1# USBP3N
SPI

R386 10K_0402_5% J2
USB_OC#6 SPI_MOSI D23 USBP3P
1 2 PAD T43 K5 USB20_N4 <27>
1

R387 10K_0402_5% SPI_MISO F21 SPI_MOSI USBP4N

SPI_MISO USBP4P K4 USB20_P4 <27> To Card reader/B.
USB_OC#7 1 2 K2
R388 10K_0402_5% USB_OC#0 USBP5N
<27> USB_OC#0 AJ19 OC0# USBP5P K1 0228_Connect USB4 to Card reader/B.
USB_OC#8 1 2 USB_OC#1 AG16 L3
R389 10K_0402_5% USB_OC#2 OC1#/GPIO40 USBP6N
USB_OC#9 1 2
<27> USB_OC#2
USB_OC#3
AG15
AE15
OC2#/GPIO41 USB USBP6P L2
M5
R390 10K_0402_5% USB_OC#4 OC3#/GPIO42 USBP7N
AF15 OC4#/GPIO43 USBP7P M4
USB_OC#2 1 2 USB_OC#5 AG17 M2
R391 10K_0402_5% USB_OC#6 OC5#/GPIO29 USBP8N
AD12 OC6#/GPIO30 USBP8P M1
USB_OC#7 AJ18 N3
USB_OC#8 OC7#/GPIO31 USBP9N
AD14 OC8# USBP9P N2
A USB_OC#9 A
AH18 OC9#
USB_OC#0 1 2 F2 USBRBIAS 1 2
R380 10K_0402_5% USBRBIAS#
USBRBIAS F3
R251 22.6_0402_1%
1 2 USB_OC#1 ICH8M REV 1.0
R381 0_0402_5% Within 500 mils
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(3/4)_PM,USB,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 20 of 40
5 4 3 2 1
 5 4 3 2 1

+RTCVCC U7E
20 mils A23 VSS[001] VSS[099] K7

0.1U_0402_16V4Z

0.1U_0402_16V4Z
A5 VSS[002] VSS[100] L1
1 1 AA2 VSS[003] VSS[101] L13

C274

C275
AA7 VSS[004] VSS[102] L15
+VCCP A25 L26
VSS[005] VSS[103]
2 2
1170mA AB1 VSS[006] VSS[104] L27
AB24 VSS[007] VSS[105] L4
U7F 0.1U_0402_16V4Z AC11 L5
VSS[008] VSS[106]
AD25 VCCRTC VCC1_05[01] A13 AC14 VSS[009] VSS[107] M12
6mA VCC1_05[02] B13 AC25 VSS[010] VSS[108] M13
ICH_V5REF_RUN A16 C13 1 1 AC26 M14
V5REF[1] VCC1_05[03] C276 C277 0.1U_0402_16V4Z VSS[011] VSS[109]
T7 V5REF[2] VCC1_05[04] C14 AC27 VSS[012] VSS[110] M15
3mA VCC1_05[05] D14 AD17 VSS[013] VSS[111] M16
R252 CHB1608U301_0603 ICH_V5REF_SUS G4 E14 AD20 M17
D 10U_0805_10V4ZICH_VCC1_5 770mA V5REF_SUS VCC1_05[06] 2 2 VSS[014] VSS[112] D
+1.5VS 1 2 40 mils VCC1_05[07] F14 AD28 VSS[015] VSS[113] M23
1 AA25 VCC1_5_B[01] VCC1_05[08] G14 AD29 VSS[016] VSS[114] M28
1 1 1 AA26 VCC1_5_B[02] VCC1_05[09] L11 AD3 VSS[017] VSS[115] M29

220U_6.3V_M
C278
+ C279 C280 C281 AA27 L12 AD4 M3
VCC1_5_B[03] VCC1_05[10] VSS[018] VSS[116]
AB27 VCC1_5_B[04] VCC1_05[11] L14 AD6 VSS[019] VSS[117] N1
AB28 VCC1_5_B[05] VCC1_05[12] L16 AE1 VSS[020] VSS[118] N11
2 2 2 2
AB29 VCC1_5_B[06] VCC1_05[13] L17 AE12 VSS[021] VSS[119] N12
+5VS +3VS D28 L18 R253 CHB1608U301_0603 AE2 N13
10U_0805_10V4Z 2.2U_0805_16V4Z VCC1_5_B[07] VCC1_05[14] ICH_VCCDMIPLL VSS[022] VSS[120]
D29 VCC1_5_B[08] VCC1_05[15] M11 1 2 +1.5VS AE22 VSS[023] VSS[121] N14

CORE
E25 VCC1_5_B[09] VCC1_05[16] M18 AD1 VSS[024] VSS[122] N15
1

D11 E26 P11 1 1 AE25 N16

R254 VCC1_5_B[10] VCC1_05[17] C282 C283 VSS[025] VSS[123]
E27 VCC1_5_B[11] VCC1_05[18] P18 AE5 VSS[026] VSS[124] N17
F24 VCC1_5_B[12] VCC1_05[19] T11 AE6 VSS[027] VSS[125] N18
100_0402_5% CH751H-40PT_SOD323-2 F25 T18 AE9 N26
VCC1_5_B[13] VCC1_05[20] 2 2 VSS[028] VSS[126]
20 mils G24 U11 AF14 N27
2

VCC1_5_B[14] VCC1_05[21] VSS[029] VSS[127]

H23 VCC1_5_B[15] VCC1_05[22] U18 AF16 VSS[030] VSS[128] N4
ICH_V5REF_RUN H24 V11 0.01U_0402_16V7K 10U_0805_10V4Z AF18 N5
VCC1_5_B[16] VCC1_05[23] VSS[031] VSS[129]
1 J23 VCC1_5_B[17] VCC1_05[24] V12 AF3 VSS[032] VSS[130] N6
C284 J24 V14 +1.25VS AF4 P12
VCC1_5_B[18] VCC1_05[25] VSS[033] VSS[131]
K24 VCC1_5_B[19] VCC1_05[26] V16 AG5 VSS[034] VSS[132] P13
0.1U_0402_16V4Z K25 V17 AG6 P14
2 VCC1_5_B[20] VCC1_05[27] VSS[035] VSS[133]

10U_0805_10V4Z
L23 VCC1_5_B[21] VCC1_05[28] V18 AH10 VSS[036] VSS[134] P15
L24 VCC1_5_B[22] 26mA 1 AH13 VSS[037] VSS[135] P16

VCCA3GP

C285
L25 VCC1_5_B[23] VCCDMIPLL R29 AH16 VSS[038] VSS[136] P17
M24 VCC1_5_B[24]
40mA AH19 VSS[039] VSS[137] P23
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AH2 VSS[040] VSS[138] P28
2 +VCCP
N23 VCC1_5_B[26] VCC_DMI[2] AE29 AF28 VSS[041] VSS[139] P29
+5VALW +3VALW N24 14mA AH22 R11
VCC1_5_B[27] VSS[042] VSS[140]
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH24 VSS[043] VSS[141] R12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AH26 VSS[044] VSS[142] R13
1

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
D12 P25 VCC3_3=310mA AH3 R14
R255 VCC1_5_B[30] 0.1U_0402_16V4Z +3VS VSS[045] VSS[143]
R24 VCC1_5_B[31] VCC3_3[01] AF29 1 1 1 AH4 VSS[046] VSS[144] R15

C286

C287

C288
C VCC3_3=310mA (DMI) C
R25 VCC1_5_B[32] 1 AH8 VSS[047] VSS[145] R16
10_0402_5% CH751H-40PT_SOD323-2 R26 AD2 0.1U_0402_16V4Z +3VS AJ5 R17
VCC1_5_B[33] VCC3_3[02] (SATA) C289 VSS[048] VSS[146]
R27 VCC3_3=310mA 1 B11 R18
2

ICH_V5REF_SUS VCC1_5_B[34] 2 2 2 VSS[049] VSS[147]

T23 VCC1_5_B[35] VCC3_3[03] AC8 +3VS B14 VSS[050] VSS[148] R28
2

C290
20 mils T24 AD8 B17 R4

VCCP_CORE
VCC1_5_B[36] VCC3_3[04] VSS[051] VSS[149]
1 T27 VCC1_5_B[37] VCC3_3[05] AE8 B2 VSS[052] VSS[150] T12
C291 +3VS 2
T28 VCC1_5_B[38] VCC3_3[06] AF8 B20 VSS[053] VSS[151] T13
T29 VCC1_5_B[39]
VCC3_3=310mA B22 VSS[054] VSS[152] T14
0.1U_0402_16V4Z U24 AA3 0.1U_0402_16V4Z B8 T15
2 VCC1_5_B[40] VCC3_3[07] VSS[055] VSS[153]
U25 VCC1_5_B[41] VCC3_3[08] U7 1 C24 VSS[056] VSS[154] T16
V23 V7 C292 C26 T17
VCC1_5_B[42] VCC3_3[09] VSS[057] VSS[155]
V24 VCC1_5_B[43] VCC3_3[10] W1 C27 VSS[058] VSS[156] T2
V25 W6 C6 U12
IDE
VCC1_5_B[44] VCC3_3[11] 2 +3VS VSS[059] VSS[157]
W25 VCC1_5_B[45] VCC3_3[12] W7 D12 VSS[060] VSS[158] U13
R256 Y25 VCC1_5_B[46] VCC3_3[13] Y7 D15 VSS[061] VSS[159] U14
50mA VCC3_3=310mA D18 VSS[062] VSS[160] U15
+1.5VS 1 2 ICH_VCCSATAPLL AJ6 A8 D2 U16
VCCSATAPLL VCC3_3[14] VSS[063] VSS[161]

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0603_10V4Z

VCC1_5_A=1120mA VCC3_3[15] B15 1 1 1 D4 VSS[064] VSS[162] U17

10U_0805_10V4Z

CHB1608U301_0603 AE7 B18 E21 U23

+1.5VS VCC1_5_A[01] VCC3_3[16] VSS[065] VSS[163]

C293

C294

C295
1 1 AF7 VCC1_5_A[02] VCC3_3[17] B4 E24 VSS[066] VSS[164] U26
ARX
C296

C297

1 AG7 VCC1_5_A[03] VCC3_3[18] B9 E4 VSS[067] VSS[165] U27

C298 2 2 2
AH7 VCC1_5_A[04] VCC3_3[19] C15 E9 VSS[068] VSS[166] U3
AJ7 D13 F15 U5
PCI

2 2 1U_0603_10V4Z VCC1_5_A[05] VCC3_3[20] VSS[069] VSS[167]

VCC3_3[21] D5 E23 VSS[070] VSS[168] V13
2
AC1 VCC1_5_A[06] VCC3_3[22] E10 F28 VSS[071] VSS[169] V15
AC2 VCC1_5_A[07] VCC3_3[23] E7 F29 VSS[072] VSS[170] V28
ATX

AC3 VCC1_5_A[08] VCC3_3[24] F11 F7 VSS[073] VSS[171] V29

AC4 VCC1_5_A[09]
24mA G1 VSS[074] VSS[172] W2
AC5 AC12 0.1U_0402_16V4Z +3VS E2 W26
VCC1_5_A[10] VCCHDA VSS[075] VSS[173]
VCC1_5_A=1120mA 4mA 1 G10 VSS[076] VSS[174] W27
AC10 AD11 0.1U_0402_16V4Z +3VALW G13 Y28
+1.5VS VCC1_5_A[11] VCCSUSHDA C299 VSS[077] VSS[175]
1 AC9 VCC1_5_A[12] 1 G19 VSS[078] VSS[176] Y29
B C300 B
VCCSUS1_05[1] J6 G23 VSS[079] VSS[177] Y4
T32 C301 2
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 G25 VSS[080] VSS[178] AB4
1U_0603_10V4Z T33
AA6 VCC1_5_A[14] G26 VSS[081] VSS[179] AB23
2 2
VCCSUS1_5[1] AC16 VCCSUS1_5_ICH_1 G27 VSS[082] VSS[180] AB5
T34
G12 VCC1_5_A[15] H25 VSS[083] VSS[181] AB6
G17 J7 VCCSUS1_5_ICH_2 +3VALW H28 AD5
VCC1_5_A[16] VCCSUS1_5[2] T35 VSS[084] VSS[182]
H7 VCC1_5_A[17] VCCSUS3_3=141mA H29 VSS[085] VSS[183] U4

0.1U_0402_16V4Z
VCCSUS3_3[01] C3 0.1U_0402_16V4Z H3 VSS[086] VSS[184] W24
AC7 VCC1_5_A[18] 1 1 H6 VSS[087]
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 J1 VSS[088] VSS_NCTF[01] A1
C302

C303
10mA VCCSUS3_3[03] AC21 J25 VSS[089] VSS_NCTF[02] A2
+1.5VS D1 AC22 J26 A28
VCCPSUS

VCCUSBPLL VCCSUS3_3[04] 2 2 VSS[090] VSS_NCTF[03]

+1.5VS VCC1_5_A=1120mA VCCSUS3_3[05] AG20 J27 VSS[091] VSS_NCTF[04] A29
1 1 F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 J4 VSS[092] VSS_NCTF[05] AH1
USB CORE

C304 C305 L6 J5 AH29

VCC1_5_A[21] +3VALW VSS[093] VSS_NCTF[06]
L7 VCC1_5_A[22] VCCSUS3_3[07] P6 K23 VSS[094] VSS_NCTF[07] AJ1
0.1U_0402_16V4Z 0.1U_0402_16V4Z M6 P7 K28 AJ2
2 2 VCC1_5_A[23] VCCSUS3_3[08] VSS[095] VSS_NCTF[08]
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 VCCSUS3_3=141mA K29 VSS[096] VSS_NCTF[09] AJ28
VCC1_5_A=1120mA VCCSUS3_3[10] N7 1 K3 VSS[097] VSS_NCTF[10] AJ29
+1.5VS W23 P1 C306 K6 B1
VCC1_5_A[25] VCCSUS3_3[11] VSS[098] VSS_NCTF[11]
VCCSUS3_3[12] P2 VSS_NCTF[12] B29
T36 VCC_LAN1_05_INT_ICH_1 F17 P3 4.7U_0805_10V4Z
VCCPUSB

+3VS T37 VCC_LAN1_05_INT_ICH_2 G18 VCCLAN1_05[1] VCCSUS3_3[13] 2 ICH8M REV 1.0

VCCLAN1_05[2] VCCSUS3_3[14] P4
12mA VCCSUS3_3[15] P5
F19 VCCLAN3_3[1] VCCSUS3_3[16] R1
1 G20 VCCLAN3_3[2] VCCSUS3_3[17] R3
C307 R257 CHB1608U301_0603 27mA R5
ICH_VCCGLANPLL VCCSUS3_3[18]
1 2 A24 VCCGLANPLL VCCSUS3_3[19] R6
0.1U_0402_16V4Z +1.5VS @ R258 74mA
2
GLAN POWER

1 1 +1.5VS 1 2ICH_VCCGLAN1_5 A26 VCCGLAN1_5[1] VCCCL1_05 G22 VCCCL1_05_ICH

CHB1608U301_0603 T38
1 A27 VCCGLAN1_5[2]
C308 C309 B26 A22 1U_0603_10V4Z 1
A @ C310 VCCGLAN1_5[3] VCCCL1_5 A
2 2
B27 VCCGLAN1_5[4] 12mA
C311
10U_0805_10V4Z

2.2U_0805_16V4Z

4.7U_0805_10V4Z 1mA B28 F20 +3VS

2 VCCGLAN1_5[5] VCCCL3_3[1]
VCCCL3_3[2] G21
2 @
+3VS 1 2ICH_VCCGLAN3_3 B25 VCCGLAN3_3
@ R2590_0402_5%
ICH8M REV 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 21 of 40
5 4 3 2 1
 A B C D E F G H

+5VS

Placea caps. near ODD CONN.

HDD Connector CD-ROM Connector

0.1U_0402_16V4Z

1U_0603_10V4Z

10U_0805_10V4Z
IDE_HDD[0..15] <19> 0213_Change Connector type. 1 1 1 1

C312

C313

C314
JP9 @ R260 0_0402_5% JP10 C315
+5VS 1 2 1 2 10U_0805_10V4Z
<20> IDE_RESET# 1 2 2 2 2 2
1 R261 33_0402_5% 3 4
GND SATA_TXP0 3 4 IDE_HDD8
A+ 2 SATA_TXP0 <19> <7,18> PLT_RST# 1 2 5 5 6 6
10U_0805_10V4Z

0.1U_0402_16V4Z
1 SATA_TXN0 IDE_HDD7 IDE_HDD9 1
A- 3 SATA_TXN0 <19> 7 7 8 8
1 1 1 1 4 0.01U_0402_16V7K IDE_HDD6 9 10 IDE_HDD10
GND 9 10
C317

C320
5 SATA_RXN0 2 1 C316 SATA_RXN0_C IDE_HDD5 11 12 IDE_HDD11
B- SATA_RXN0_C <19> 11 12
C318 C319 6 SATA_RXP0 2 1 C321 SATA_RXP0_C IDE_HDD4 13 14 IDE_HDD12
B+ SATA_RXP0_C <19> 13 14
7 0.01U_0402_16V7K IDE_HDD3 15 16 IDE_HDD13
2 2 2 2 GND IDE_HDD2 15 16 IDE_HDD14
17 18
0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side. IDE_HDD1 19
17
19
18
20 20 IDE_HDD15
8 IDE_HDD0 21 22 IDE_HDREQ
V33 21 22 IDE_HDREQ <19>
9 +3VS_HDD 23 24 IDE_HDIOR#
V33 23 24 IDE_HDIOR# <19>
Pleace near HD CONN (JP23) 10 IDE_HDIOW# 25 26
V33 <19> IDE_HDIOW# 25 26
11 IDE_ HIORDY 27 28 IDE_HDACK#
GND <19> IDE_HIORDY 27 28 IDE_HDACK# <19>
12 IDE_HIRQ 29 30
GND +5VS <19> IDE_HIRQ 29 30
+3VS +3VS_HDD 13 IDE_HDA1 31 32 PDIAG# R262 1 2 100K_0402_5% +5VS
GND <19> IDE_HDA1 31 32
@ R2630_0805_5% 14 IDE_HDA0 33 34 IDE_HDA2
V5 <19> IDE_HDA0 33 34 IDE_HDA2 <19>
330U_V_2.5VK_R9

2 1 15 +5VS IDE_HDCS1# 35 36 IDE_HDCS3#

V5 <19> IDE_HDCS1# 35 36 IDE_HDCS3# <19>
0.1U_0402_16V4Z 1 16 2 1 IDE_ACT# 37 38
V5 R264 10K_0402_5% 37 38
1 1 1 GND 17 39 39 40 40
C322

+ 18 41 42
Reserved +5VS 41 42 +5VS
@ C323 @ C324 @ C325 19 43 44
@ GND 43 44
V12 20 45 45 46 46
2 2 2 2 SEC_CSEL
V12 21 47 47 48 48
1000P_0402_50V7K 1U_0603_10V4Z 22 49 50
V12 49 50

1
Pleace near HD CONN GND 23 53 G G 54
24 R265
GND SUYIN_800194MR050S102ZU
470_0402_5%
CONN@
SUYIN_127043FR022G204ZL_NR CONN@

2
DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA DC030001P00 WAFER OCTEK CDR-50JD1 50P P0.822P SATA
SUYIN_127043FR022G204ZL_22P_NR OCTEK_CDR-50JD1_50P

2 2

Mini-Express Card---WLAN
+3VS_MINI +1.5VS_MINI +3VALW

C326 1 1 1 1 1 1 1
C327 C328 C329 C330 C331 C332

0.01U_0402_16V7K 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z @ 0.1U_0402_16V4Z

2 2 4.7U_0805_10V4Z 2 2 2 2 2

3 3

+1.5VS_MINI +3VS_MINI +3VS

L12 +1.5VS
JP11 FBMA-L11-201209-102LMA10T
<20> ICH_PCIE_WAKE# ICH_PCIE_WAKE# 1 2 1 2
1 2
3 3 4 4 1 2
5 6 L13 FBMA-L11-201209-102LMA10T
5 6
<15> MINI_CLKREQ# 1 2 MINI_CLKREQ#_MC 7 7 8 8 R267 1 2 DEBUG@ 0_0402_5% LPC_FRAME# <19,29,30>
R266 0_0402_5% 9 10 R268 1 2 DEBUG@ 0_0402_5% LPC_AD3
CLK_PCIE_MCARD# 9 10 R269
<15> CLK_PCIE_MCARD# 11 11 12 12 1 2 DEBUG@ 0_0402_5% LPC_AD2
CLK_PCIE_MCARD 13 14 R270 1 2 DEBUG@ 0_0402_5% LPC_AD1
<15> CLK_PCIE_MCARD 13 14
15 16 R271 1 2 DEBUG@ 0_0402_5% LPC_AD0
PLT_RST# 15 16
1 2 17 17 18 18 LPC_AD[0..3] <19,29,30>
R272 DEBUG@ 0_0402_5% 19 20 WL_ON# WL_ON# <20>
<15,29,30> CLK_DEBUG_PORT 19 20
R273 0_0402_5% 21 22 PLT_RST#
PCIE_RXN1 PCIE_C_RXN1 21 22
<20> PCIE_RXN1 1 2 23 23 24 24 +3VALW
PCIE_RXP1 1 2 PCIE_C_RXP1 25 26
<20> PCIE_RXP1 25 26
R274 0_0402_5% 27 28
27 28
29 29 30 30 ICH_SMBCLK <15,20>
PCIE_TXN1 31 32 ICH_SMBDATA <15,20>
<20> PCIE_TXN1 31 32
PCIE_TXP1 33 34
<20> PCIE_TXP1 33 34
35 35 36 36
37 37 38 38
39 39 40 40
41 41 42 42
43 44 WL_LED# WL_LED# <28>
43 44
45 45 46 46
47 47 48 48
49 49 50 50
51 51 52 52
4 4
53 GND1 GND2 54

FOX_AS0B226-S40N-7F~D
Mini Card STANDOFF SP01000P700 S H-CONN ACES 88914-5204 52P P0.8
H19 H20
HOLEA HOLEA Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2007/08/29 Title
HDD/ODD/Mini Card CONN.
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC029000100 MINICARD_STANDOFF_8 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 22 of 40
A B C D E F G H
 5 4 3 2 1

+3VALW
JP12
R275 11
300_0603_5% Yellow LED+
ACTIVITY# 1 2 12 Yellow LED-
8 RX2-
7 RX2+
D D
MDO1- 6 RX1-
5 TX2-
PCI_AD[0..31] R276 4
<18> PCI_AD[0..31] 3.6K_0402_5% TX2+
1 2 +3VA_LAN MDO1+ 3 RX1+
U8 U9 MDO0- 2
PCI_AD0 LAN_EEDO TX1-
104 AD0 EEDO 108 4 DO GND 5 1 SGND1 15
PCI_AD1 103 109 LAN_EEDI 3 6 R277 MDO0+ 1
PCI_AD2 AD1 AUX/EEDI LAN_EECLK DI NC C333 0.1U_0402_16V4Z 300_0603_5% TX1+
102 AD2 EESK 111 2 SK NC 7 SGND2 16
PCI_AD3 98 106 LAN_EECS 1 8 +3VALW LINK_100# 1 2 10
PCI_AD4 AD3 EECS CS VCC 2 Green LED-
97 AD4
PCI_AD5 96 117 ACTIVITY#_R1 2 AT93C46-10SU-2.7_SO8 ACTIVITY# 1 2 For EMI, 9
AD5 LED0 +3VALW Green LED+
PCI_AD6 95 115 R278 0_0603_5% C334 680P_0402_50V7K
PCI_AD7 93
AD6 LED1
114 LINK_100#_R1 2 LINK_100# 1 2 locate close RJ45 / LED
PCI_AD8 AD7 LED2 R279 0_0603_5% C335 680P_0402_50V7K TIP
90 AD8 NC/LED3 113 to LAN chip 13 RJ11_1
PCI_AD9 89
PCI_AD10 AD9 TXD+/MDI0+ RI NG
87 AD10 TXD+/MDI0+ 1 14 RJ11_2
PCI_AD11 86 2 TXD-/MDI0- RJ11
PCI_AD12 AD11 TXD-/MDI0- RXIN+/MDI1+ C336 27P_0402_50V8J CONN@ JM34F2-M5125-7F
85 AD12 RXIN+/MDI1+ 5
PCI_AD13 83 6 RXIN-/MDI1- 1 2
PCI_AD14 AD13 RXIN-/MDI1-
82 AD14 JM34F2*-N5125-7F

2
PCI_AD15 79 14
PCI_AD16 AD15 NC/MDI2+ JM34F2A-M5125-7F
59 AD16 NC/MDI2- 15
PCI_AD17 58 18 Y3
PCI_AD18 AD17 NC/MDI3+ 25MHZ_20P_1BG25000CK1A U10
57 AD18 NC/MDI3- 19
PCI_AD19 55
PCI_AD20 AD19 LAN_X1 C337 27P_0402_50V8J TXD+/MDI0+ MDO0+ R280 C338
53 121 8 9

1
PCI_AD21 AD20 X1 LAN_X2 TXD-/MDI0- TD- TX- MDO0- 75_0402_5%
50 AD21 X2 122 1 2 7 TD+ TX+ 10
C PCI_AD22 MCT0 RJ45_GND 2 C
49 AD22 6 CT CT 11 2 1 1
PCI I/F

PCI_AD23 47 105 R281 1 2 1K_0402_5% C339

PCI_AD24 AD23 LWAKE R282 +3VS
43 AD24 ISOLATE# 23 1 2 15K_0402_5% 0.1U_0402_16V4Z
PCI_AD25 42 127 R283 1 2 5.6K_0603_1% 1 2 3 14 MCT1 2 1 1000P_1206_2KV7K
PCI_AD26 AD25 RTSET RXIN+/MDI1+ CT CT MDO1+ R284
40 AD26 NC/SMBCLK 72 2 RD- RX- 15
PCI_AD27 39 74 RXIN-/MDI1- 1 16 MDO1- 75_0402_5%
PCI_AD28 AD27 NC/SMBDATA RD+ RX+
37 AD28
PCI_AD29 36 88
PCI_AD30 AD29 NC/M66EN NS0013_16P
34 AD30
PCI_AD31 33 10
AD31 NC/AVDDH
NC/HV 120
<18> PCI_CBE#0 PCI_CBE#0 92
PCI_CBE#1 C/BE#0
<18> PCI_CBE#1 77 C/BE#1 NC/HSDAC+ 11
<18> PCI_CBE#2 PCI_CBE#2 60 123
PCI_CBE#3 C/BE#2 NC/HG
<18> PCI_CBE#3 44 C/BE#3 NC/LG2 124
NC/LV2 126
PCI_AD17 1 2 LAN_IDSEL 46
R285 100_0402_5% IDSEL
LAN I/F

PCI_PAR 76
<18> PCI_PAR PAR
PCI_FRAME# 61 9
<18> PCI_FRAME# FRAME# NC/VSS +3VALW
PCI _IRDY# 63 13
<18> PCI_IRDY# IRDY# NC/VSS
PCI_TRDY# 67
<18> PCI_TRDY# TRDY#
PCI_DEVSEL# 68
<18> PCI_DEVSEL# DEVSEL#
PCI_STOP# 69 22 C340 1U_0603_10V4Z
<18> PCI_STOP# STOP# NC/GND
NC/GND 48 1 2 close to chip
PCI_PERR# 70 62
<18> PCI_PERR# PERR# NC/GND
3

PCI_SERR# 75 73 Q10 R286

<18> PCI_SERR# SERR# NC/GND
112 49.9_0402_1% C341
PCI_REQ0# NC/GND CTRL25 TXD+/MDI0+ 0.01U_0402_16V7K
<18> PCI_REQ0# 30 REQ# NC/GND 118 1 2 1
PCI_GNT0# 29 2 1
<18> PCI_GNT0# GNT# TXD-/MDI0- 2 1
<18> PCI_PIRQA# PCI_PIRQA# 25 2SB1188T100R_SC62-3
V2.5_LAN R287
2

B INTA# 49.9_0402_1% B
CTRL25 8
PCI_PME# 31 C342 4.7U_0805_10V4Z +3VA_LAN
<18,30> PCI_PME# PME#
RTT3/CRTL18 125 1 2
PCI_RST# 27 R288
<18,29,30> PCI_RST# RST#
VDD33 26 2 1 +3VALW
CLK_PCI_LAN 28 41 0_0603_5%
<15> CLK_PCI_LAN
1 2 65
CLK
CLKRUN#
VDD33
VDD33 56
1 1 1 1 1
close to magnetic
R289 71 C343 C344 C345 C346 C347
10K_0402_5% VDD33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R290
VDD33 84
2 2 2 2 2 49.9_0402_1% C348
VDD33 94
107 RXIN+/MDI1+ 2 1 0.01U_0402_16V7K
VDD33
4 GND/VSS 2 1
17 RXIN-/MDI1- 2 1
GND/VSS R291
128 GND/VSS
3 49.9_0402_1%
AVDD33/AVDDL
AVDD33/AVDDL 7 1 1 1
21 GND/VSSPST AVDD33/AVDDL 20
38 16 C349 C350 C351
GND/VSSPST NC/AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
51 GND/VSSPST 2 2 2 0310_Dammy by safty request.
66 GND/VSSPST Footprint can not match part number.
CLK_PCI_LAN 81 32 V2.5_LAN
GND/VSSPST VDD25/VDD18
91 GND/VSSPST VDD25/VDD18 54 1 1 1 1
1

101 78 SP020008Y00 S W-CONN ACES 88266-02001 2P P1.25

@ R292 GND/VSSPST VDD25/VDD18 C352 C353 C354 C355 ACES_88266-02001_2P
119 GND/VSSPST VDD25/VDD18 99
10_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 JP13
Power

35 24 RI NG 1
2

GND NC/VDD18 TIP 1

1 52 45 2
@ C356
10P_0402_50V8J
80
100
GND
GND
GND
NC/VDD18
NC/VDD18
NC/VDD18
64
110
2 2
C358
2
RJ11
NC/VDD18 116 3 G1
2 R293 C357 @ 4 G2
A 0_0402_5% 1 1 A
12 V_12P 1 2 V2.5_LAN ACES_88266-02001
AVDD25/HSDAC- 220P_1808_3KV
1 CONN@
RTL8100CL_LQFP128 C359 @ 220P_1808_3KV

0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2007/08/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-8100CL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 23 of 40
5 4 3 2 1
 A B C D E

0308_Change R294 and R295 from 0 ohm to bead, C363 from 10uF to 680pF, C365 and C368 from 0.1uF to 680p
AUDIO CODEC CODEC POWER
0212_Change to +5VALW.
For Layout: (3.33V)
In order for the modem wake on ring feature to function, Place decoupling caps near the +5VALW +VDDA_CODEC
W=40Mil U11
the CODEC must be powered by a rail that is not
removed when the system is in standby.
power pins of SmartAMC
1 2 1 5
250mA
device. C360 0.1U_0402_16V4Z VIN OUT
1
2 GND C361

<30,31,33,35,36> SUSP# 3 4 0.1U_0402_16V4Z

1 R294 +3VDD_CODEC +3VAMP_CODEC SHDN# BP 2 1
1
R295 APE8805A-33Y5P_SOT23-5
+3VS 2 1 2 1 +VDDA_CODEC C362

680P_0402_50V7K

680P_0402_50V7K
0.1U_0402_16V4Z

@ 0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0603_10V4Z
MBV2012301YZF_0805 MBV2012301YZF_0805 0208_Change SLP_S3# to SUSP#. 0.1U_0402_16V4Z
2

680P_0402_50V7K

1U_0603_10V4Z
1 1 1 1 1 1 1 1

C365
2 2 2 2 2 2 2 2
C363

C364

C366

C367

C368

C369

C370
+CODEC_REFF_INR

45

20
31
37
3

8
U12

1
AVDDHP
DVDD
VDDIO

AVDD_20
AVDD_31
DVDDM
R296
2.2K_0402_5%

ACZ_RST# 10 29
<19,30> ACZ_RST#

2
RESET# MIC_BIAS_L
MIC_BIAS_R 30 +CODEC_REFF_INR
5 21 MIC_INL C371 1 2 10U_0805_10V4Z
<19> ACZ_BITCLK BIT_CLK MIC_L
R299 33_0402_5% 9 22 MIC_INR C372 1 2 10U_0805_10V4Z
<19> ACZ_SYNC SYNC MIC_R MIC_IN_R <26>
1

<19> ACZ_SDIN0 1 2 7 SDI

R300 4 35 LINE_OUTL +CODEC_REFF_EXTR +CODEC_REFF_EXTL
<19> ACZ_SDOUT SDO LINEOUT_L LINE_OUTL <26>
47_0402_5% 36 LINE_OUTR
LINEOUT_R LINE_OUTR <26>
R301 0_0402_5% 33
2

PORT-A_BIAS_L

1
1 <25> DIB_P 1 2 DIBP_C 44 DIBP PORT-A_BIAS_R 34
38 HP_OUTL R303 R304
PORT-A_L HP_OUTL <26>
C374 R305 0_0402_5% 39 HP_OUTR 2.2K_0402_5% 2.2K_0402_5%
33P_0402_50V8K PORT-A_R HP_OUTR <26>
<25> DIB_N 1 2 D IBN_C 43 DIBN
2 2 2
14 +CODEC_REFF_EXTL

2
R302 C373 PORT-B_BIAS_L
0216_Change value. PORT-B_BIAS_R 15 +CODEC_REFF_EXTR
0_0402_5% 1U_0603_10V4Z 23 MIC_EXTL C375 1 2 10U_0805_10V4Z
PORT-B_L MIC_EXT_L <26>
SB_SPKR
1 2 MONO_IN1 1 2 MONO_INR 11 24 MIC_EXTR C376 1 2 10U_0805_10V4Z
<20> SB_SPKR PCBEEP PORT-B_R MIC_EXT_R <26>
@ R306
1 5.1K_0402_5%
2 CD_L 17 1 2
18 R307 20K_0402_1% +3VAMP_CODEC
CD_GND
48 SPDIF CD_R 19 1 2 HP_DET# <26>
R309 5.1K_0402_1%
13 SENSE 1 2
T39 EAPD SENSE For Vista R310 5.1K_0402_1%
47 EAPD
1 2 EXTMIC_DET# <26>
R337 10K_0402_1%
1 NC_1
2 26 VREF_HI
+3VDD_CODEC NC_2 VREF_HI VREF_LO
16 NC_16 VREF_LO 27
28 VC_REFA
RCOSC VC_REFA
VSSIO_42
VSSIO_46

2 1 41
AVSS_12
AVSS_25
AVSS_32

RCOSC
AVSSHP

R311 237K_0402_1% 1 1 2
DVSS

C378 C377 1U_0603_10V4Z

1U_0603_10V4Z
CX20549-12Z_LQFP48_9X9 2
42
46

12
25
32
40

DIGITAL ANALOG
3 3
C379
0.1U_0402_16V4Z
1 2

C380
0.1U_0402_16V4Z
1 2

C381
0.1U_0402_16V4Z
1 2

C382
0_0402_5%
1 2

C383
0.1U_0402_16V4Z
1 2
HP_DET# MIC_DET PORT-A
R312
0_1206_5%
LINEOUT <Earphone OUT> MIC EQ
1 2 0(LOW) 0(LOW) OFF ON ON Disable
R313 0(LOW) NC OFF ON OFF Disable
0_1206_5%
1 2 GNDA <26> NC 0(LOW) ON OFF ON Enable
NC NC ON OFF OFF Enable
4
GND GNDA 4

0312_Mount C379~383, R313.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMOM_codec
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 24 of 40
A B C D E
 5 4 3 2 1

RAC1_RING 5335R13-005 RING_1

MU1
CX20548 MMBD3004S MFB2
MBR1
D D
MR3 6.81M
4 RAC1 2
RAC AGND_LSD 1 2 1
12 TEST
4 3

MRV1
ML1 @ MJ2
MR1 6.81M @ Optional
5 TAC1 2
TAC
1
res_0805_681m MBR2
MMBD3004S @ MJ1
TAC1_TIP 5335R13-005 TIP_1
2
DIBN 16 11 EIC MC11 0.1uF MFB1 1
DIBN EIC cap_0402_01uf MC8 MC7 MC9
470 pF @ Omit 470 pF @ MJ3
MC10 0.01uF
AGND_LSD Note: MC8 and MC9 can be optionally
populated here or behind the RJ-11
cap_0603_001uf connector.
PWR+ 15 R810 and C810 must be placed near pin 6 (RXI)
PWR and there should be no vias on the(RXI)net. AGND_LSD
<24> DIB_P GND
<24> DIB_N AVdd
MC5
C C
0.1uF MR2
cap_0402_01uf 2 6 RXI RX1_1 MC1 0.047uF BRIDGE_CC
MC12 AVDD RXI 100.0V
GND MC3 237K
150pF 0.1uF MR9 MR5 MR6 MR10
@ MJ4 MT1
CAP_0402_150PF cap_0402_01uf 280 280 280 280
2 DIBN_HS 2 3 RES_1206_280RES_1206_280
RES_1206_280 RES_1206_280
1 DIBP_HS MC6
47P_0402_50V8J BRIDGE_CC2
CAP_0402_47PF AGND_LSD
1 4
MODEM-SMAR DIBP 14 10 MR13 100_0402_5% MQ1
DIBP EIO MMBTA42
MC13 RES_0402_100
QBASE MQ3 MQ4
150pF 9 EIF MMBTA42 MMBTA42
CAP_0402_150PF EIF
MR8
DVdd 1 8 TXO MQ2 56 MR11 MR12
DVDD TXO MMBTA42 5% 3.01 3.01
GND
@ RES_0603_56 res_0402_301 res_0402_301
MC4 7 TXF
0.1uF TXF
@ MJ5 cap_0402_01uf 13
GPIO MR4
B 1 B
110

VC

EP
2
AGND_LSD 5% MR7
9.1

17
res_1206_91

VC_LSD
GND

AGND_LSD

MC2
Revision History 0.1uF
cap_0402_01uf
REV Description Date
0 Initial Release April 26, 2005 AGND_LSD

No changes to schematic. PCB updated to -003.

1 Updated footprints and corrected via spacing errors. August 18, 2005

A
Changed MC8 and MC9 pads. No schematic changes. A
2 PCB updated to -005. November 3, 2005

3 Added MR11 and MR12. PCB updated to -007. November 18, 2005
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2007/07/26 Title
4 Added MR13. PCB updated to -009. January 3, 2006

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMOM-CX20548
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
4.01 AVL update only. April 20, 2006
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 14, 2007 Sheet 25 of 40
5 4 3 2 1
 A B C D E

+5VAMP R314 +5VS SP02000D000 S W-CONN ACES 85204-04001 4P P1.25 SPEAKER

0.1U_0402_16V4Z 0_1206_5% JP15
1 2 SPKL+ 1
SPKL- 1
2 2
1 1 1 SPKR+ 3
SPKR- 3
4 4
C384 C385 C386
10U_0805_10V4Z E&T_3801-04
2 2 2

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J

47P_0402_50V8J
CONN@
1 1 1 1
0.1U_0402_16V4Z

C387

C388

C389

C390
10 dB
1 +5VS 1
2 2 2 2

1
@ @ @ @

16
15
6
U13 R315 @ R316
100K_0402_5% 100K_0402_5%

PVDD1
PVDD2
VDD

2
C391 1 2 0.47U_0603_10V7K 7 2
RIN+ GAIN0

GAIN1 3

1
C393 1 2 0.47U_0603_10V7K LINE_C_OUTR 17 @ C394 47P_0402_50V8J
<24> LINE_OUTR RIN- SPKR+ @ R318 R319
18 2 1
ROUT+ 100K_0402_5% 100K_0402_5% MIC INT In-R
JP28
14 SPKR- 2 1 MICIN_R 1
<24> MIC_IN_R

2
C395 1 ROUT- 1
2 0.47U_0603_10V7K 9 LIN+
R320 0_0603_5% 2 2
3 G1
4 SPKL+ 4
LOUT+ G2
C396 1 2 0.47U_0603_10V7K LINE_C_OUTL 5 ACES_85204-02001
<24> LINE_OUTL LIN- SPKL-
LOUT- 8 CONN@

12
NC MIC EXT In
2 10 Keep 10 mil width EXTMIC_DET# 2
BYPASS <24> EXTMIC_DET# CONN@
EC_MUTE# 19
<30> EC_MUTE# SHUTDOWN SUYIN_010030FR006G105ZR
2
6

GND5
GND1
GND2
GND3
GND4
C397 @ C398 47P_0402_50V8J 5
0.47U_0603_10V7K 2 1
1
4
R321 0_0603_5%
21
20
13
11
1
MIC_EXT_L 2 1 MICEXT_L 3
P3017THF D0 TSSOP 20P <24> MIC_EXT_L
MIC_EXT_R 2 1 MICEXT_R 2
<24> MIC_EXT_R
R322 0_0603_5% 1

2 1 JP16
0310_Change to ENE AMP. @ C399 47P_0402_50V8J

2
B+
B+

1
R323

1
@ D13

1
330K_0402_5% R324 SM05_SOT23

2
330K_0402_5%

2
1
D
EC_MUTE# 2 Q12
G 2N7002_SOT23-3
S

3
3 3

HeadPhone Out/Line Out

CONN@

1
D HP_DET#
<24> HP_DET# SUYIN_010030FR006G105ZR
2 Q13
cap. high 5.7mm G 2N7002_SOT23-3 6
2

@ C401 47P_0402_50V8J
G

S 5

3
C402 Q14 2 1
HP_OUTR 2 100U_6.3V_M HP_OUT_R 3 2N7002_SOT23-3
HP_OUTR+
+

<24> HP_OUTR 1 1 4
R325 0_0603_5%
D

HP_OUTR+ 2 1 PR 3
Q15 HP_OUTL+ 2 1 PL 2
HP_OUTL 2 100U_6.3V_M HP_OUT_L 3 2N7002_SOT23-3
HP_OUTL+ R326 0_0603_5%
+

<24> HP_OUTL 1 1 1
1

C403 2 1 JP17
1

2
R327 @C404 47P_0402_50V8J
G
2

1K_0402_5% R328
1K_0402_5%
2

@ D14 0302_Change Audio Jack.

1
1

D SM05_SOT23
Q16
2
2N7002_SOT23-3
G
S
3

D
Q17
2
4 4
2N7002_SOT23-3
G
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2007/08/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 26 of 40
A B C D E
 5 4 3 2 1

0228_Add JP29 for USB card reader.

D D

JP29
<20> USB20_P4 1 1 2 2 +3VS
<20> USB20_N4 3 3 4 4
5 6
USB Port +5VALW
7
9
5
7
6
8 8
10
9 10
+5VS 11 11 12 12

GND
GND
GND
GND
GND
GND
+5VALW
+USB_VCCA
U14 ACES_88020-12101

13
14
15
16
17
18
1 GND OUT 8 CONN@
2 IN OUT 7
3 IN OUT 6
SYSON# 4 5 USB_OC#2
EN# FLG USB_OC#2 <20>
G528P1UF_SO8

+USB_VCCA
220U_6.3V_M

1 0308_Change connector type. +5VALW

1 1
C406

+ C407 C408
C C
1000P_0402_50V7K
2 2 2 JP18
JP19 1
0.1U_0402_16V4Z 1
1 1 2 2
<20> USB20_N2 2 2 3 3
<20> USB20_P2 3 3 <20> USB20_N0 4 4
4 4 <20> USB20_P0 5 5
5 GND 6 6

3
6 GND <20> USB20_N1 7 7
@D15 7 <20> USB20_P1 8
GND 8
PSOT24C_SOT23-3 8 GND <20> USB_OC#0 9 9
SYSON# 10
<31,35> SYSON# 10
SUYIN_020133MB004S580ZL-C
CONN@
1
11 GND1
DC233000U00 CONN SUYIN 020173MR004S558ZL 4P USB 12
SUYIN_020173MR004S558ZL_4P GND2
ACES_87213-1000G
CONN@

SP02000DX00 S W-CONN ACES 87213-1000G 10P P1.0

ACES_87213-1000G_10P

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 27 of 40
5 4 3 2 1
 5 4 3 2 1

POWER LED(Left 1)
BLUE +5VALW
M/BtoS/B
D16 R329
0301_Change Voltage from 3V to 5V. ON/OFFBTN_LED# 1 2 1 2

470_0402_5%
+5VALW +5VS LTST-C191TBKT-5A_BLUE_0603~D
JP20

D
1
2
1 Battery Charge LED(Left 2) D
ON/OFFBTN# 2 +5VALW
3
4
3 BLUE
<29,30> NUM_LED# 4
WL_BTN# 5
<30> WL_BTN# 5 D18 R331
ON/OFFBTN_LED# 6
<29,30> ON/OFFBTN_LED# 6
WL_LED# 7 1 2 1 2
Power ON/OFF <30> LID_SW#
LID_SW# 8
9
7
8
<30> BAT_LED#
LTST-C191TBKT-5A_BLUE_0603~D 470_0402_5%
9
10
+3VALW
11
12
10
GND HDD LED(Left 3)
GND +5VS
ACES_85201-1005N
CONN@
BLUE

2
D20 R333
R330
SP01000H400 S H-CONN ACES 85201-1005N 10P P1.0 1 2 1 2
4.7K_0402_5% ACES_85201-1005N_10P <19> SATA_LED#
1 470_0402_5%
D17 LTST-C191TBKT-5A_BLUE_0603~D
2 ON/OFF ON/OFF <30>
ON/OFFBTN# 1 0208_Change Voltage from 3V to 5V.
3 51ON# 51ON# <34>
DAN202U_SC70
Wireless ON/OFF LED(Left 4)
1

Q18
O

DTC124EK_SC59 +5VS
1

0216_Delete D19.
M/B to SB(Caps Lock LED)
G

1
+3VALW 2 C409
I

C 1000P_0402_50V7K R334 R335 C

2

820_0402_5% 200_0402_5%
1

R332

4 2

2 2
4.7K_0402_5% +5VS
AMBER BLUE
+5VS
2

1
EC_ON D21
<30> EC_ON

Orange

Blue
JP21 R336
1 LTST-C195TBKFKT_BLUE/ORG 10K_0402_5%
1
2

1
<29,30> CAPS_LED# 2
3

2
G1
4 G2

1
D
ACES_85204-02001 Q19
2 WL_LED#_LIGHT
CONN@ 2N7002_SOT23-3
G
S

3
SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P
On (WL_ON#=L)-> Blue
Off (WL_ON#=H)-> Amber

1
D
WL_LED# 2 Q20
<22> WL_LED#
G 2N7002_SOT23-3
S

3
0208_Change R329, R331, R333 to 470 ohm, R334 and R339 to 820 ohm, R335 and R338 to 200 ohm.
B
0208_Delete reserve component (D25、SW2) for 14.1". D21, D25, D23 Footprint can not match part number. B

+5VS
TouchPAD ON/OFF LED TP ON/OFF T/P Board TP_DATA
TP_CLK
+5VALW +5V
Q33

2
+5V
1

+5V D24 SI2301BDS-T1-E3_SOT23-3

R338 R339 PSOT24C_SOT23-3

S
200_0402_5% 820_0402_5%

D
@ 3 1
2

R340
2

1
10K_0402_5%

G
2
+5VS R384
BLUE AMBER 1 EMI request
2

SW1 @ C412 10K_0402_5%

1

SMT1-05-A_4P
1

D23 3 1 TP_BTN# TP_BTN# <30> 0.1U_0402_16V4Z

2
R341 JP22 2
Blue

Orange

10K_0402_5% LTST-C195TBKFKT_BLUE/ORG 4 2 1
1

1
D
2 TP_CLK <30>
1

2 SYSON Q34
3 TP_DATA <30> <30,31,35> SYSON 2
2

5
6

Q21 3 G 2N7002_SOT23-3
4 4
1

2N7002_SOT23-3 D
5 S

3
G1
2 G2 6
G On (TP_LED#=L)-> Blue 1 1
S ACES_85201-0405N
Off (TP_LED#=H)-> Amber
3

TP_LED#_LIGHT CONN@ @C413 @C414

100P_0402_50V8J 100P_0402_50V8J
1

D 2 2
Q22
2 TP_LED# TP_LED# <30>
SN100000F00 S TACT SW SMT1-05-A SPST HCH H1.5 4P SP01000H300 S H-CONN ACES 85201-0405N 4P P1.0 0226_Change package from 0603 to 0402.
A 2N7002_SOT23-3
G SW_SMT1-05-A_4P ACES_85201-0405N_4P A
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 28 of 40

5 4 3 2 1
 +3VALW +3VALW

1
1
C415
R342
0.1U_0402_16V4Z 100K_0402_5%
2 U16

2
8 VCC A0 1
7 WP A1 2
<30,38> SMB_EC_CK1 6 SCL A2 3
<30,38> SMB_EC_DA1 5 SDA GND 4

AT24C16AN-10SI-2.7_SO8
LPC Debug Port

1
R343
Change from +3VL to +3VS. 6/9
100K_0402_5% Removed +3VS. 6/13

2
B+

JP23
1 Ground
<15,22,30> CLK_DEBUG_PORT 2 LPC_PCI_CLK
3
SPI ROM <19,22,30> LPC_FRAME# 4
Ground
LPC_FRAME#
5 +V3S
<18,23,30> PCI_RST# 6 LPC_RESET#
7 +V3S
+3VALW 8
<19,22,30> LPC_AD0 LPC_AD0
U17 9
20mils <19,22,30> LPC_AD1 LPC_AD1
8 VCC VSS 4 <19,22,30> LPC_AD2 10 LPC_AD2
1 <19,22,30> LPC_AD3 11 LPC_AD3
C416 3 12
0.1U_0402_16V4Z W ON/OFFBTNLED# VCC_3VA
13 PWR_LED#
7 CAPSLED# 14
2 HOLD NUMLED# CAPS_LED#
15 NUM_LED#
1 2 SPI_FSEL# 1 VCC1PWRGD 16
<30> FSEL# S VCC1_PWRGD
R345 0_0402_5% SPI_CLK_JP52 17
SPI_CLK_R SPI_CS#_JP52 SPI_CLK
<30> SPI_CLK 1 2 6 C 18 SPI_CS#
R346 0_0402_5% SPI_SI_JP52 19
FWR# 1 SPI_FWR# SPI_SO 1 SPI_SI
<30> FWR# 2 5 D Q 2 2FR D# FRD# <30> SPI_SO_JP52 20 SPI_SO
R347 0_0402_5% R348 0_0402_5% SPI_HOLD#_0 21
CONN@ WIESON G6179 8P SPI SPI_HOLD#
22 Reserved
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH 23
WIESO_G6179-100000_8P Reserved
24 Reserved
&U1 Connect pin3 & 23
ACES_87216-2404_24P
together and pin 24 @
to GND in 6/29.
45level

45@ SST25LF080B_SO8-200mil
@ R349 0_0402_5%
SPI_CLK 1 2 SPI_CLK_JP52

@ R350 0_0402_5%
FSEL# 1 2 SPI_CS#_JP52

@ R351 0_0402_5%
FWR# 1 2 SPI_SI_JP52
+3VALW
@ R352 0_0402_5%
HOLD# 1 2 SPI_HOLD#_0

@ R353 0_0402_5%
FR D# 1 2 SPI_SO_JP52

1 2 ON/OFFBTNLED#
<28,30> ON/OFFBTN_LED#
@ R222 0_0402_5%
1 2 CAPSLED#
<28,30> CAPS_LED#
@ R356 0_0402_5%
1 2 NUMLED#
<28,30> NUM_LED#
@ R357 0_0402_5%
1 2 VCC1PWRGD
<30> VCC1_PWRGD
@ R399 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 29 of 40
 +3VALW_EC

+3VALW_EC
Ra

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K @ R354
+3VALW
1 1 1 1 1
+3VALW_EC +EC_AVCC 100K_0402_5%
C417 C418 C419 C420 C421 R382

2
2 1 M/B_ID
2 2 2 2 2 0_0805_5%
Rb

1
0.1U_0402_16V4Z 1000P_0402_50V7K 1
@ C422 R355

111
125
22
33
96

67
0_0402_5%

9
U18 0.1U_0402_16V4Z
2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

2
GATEA20 1 21 INV_PWM
<19> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM <17>
KB_RST# 2 23 FAN_PWM VCC 3.3V+/-5%
<19> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 FAN_PWM <4>
SIRQ 3 26
<20> SIRQ SERIRQ# FANPWM1/GPIO12
LPC_LFRAME# 4 27 ACOFF Ra 100K+/-5%
<19,22,29> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <33>
@ C424 @ R358 <19,22,29> LPC_AD3 LPC_LAD3 5 1 2 ECAGND
LPC_LAD2 LAD3 C423 0.01U_0402_16V7K
1 2 1 2 <19,22,29> LPC_AD2 7 LAD2 PWM Output Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
<19,22,29> LPC_AD1 LPC_LAD1 8 63 BATT_TEMP
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <38>
15P_0402_50V8J 33_0402_5% LPC_LAD0 BATT_OVP
<19,22,29> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_IN
BATT_OVP <33> 0 0 0V 0V 0V
ADP_I/AD2/GPIO3A 65 ADP_I <33>
CLK_PCI_EC 12 AD Input 66 M/B_ID 1 8.2K+/-5% 0.216V 0.250V 0.289V
<15> CLK_PCI_EC PCICLK AD3/GPIO3B
PCI_RST# 13 75
<18,23,29> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VALW 2 R359 1 ECRST# 37 ECRST# SELIO2#/AD5/GPIO43 76 2 18K+/-5% 0.436V 0.503V 0.538V
47K_0402_5% EC_SCI# 20
C425 <20> EC_SCI# SCI#/GPIO0E
38 CLKRUN#/GPIO1D 3 33K+/-5% 0.712V 0.819V 0.875V

1
1 2 J1 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG <17>
EN_DFAN1/DA1/GPIO3D 70 4 56K+/-5% 1.036V 1.185V 1.264V
JOPEN DA Output 71 IR EF
IREF <33>

2
0.1U_0402_16V4Z KSI0 IREF/DA2/GPIO3E
55 KSI0/GPIO30 DA3/GPIO3F 72 5 100K+/-5% 1.453V 1.650V 1.759V
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32 6 200K+/-5% 1.935V 2.200V 2.341V
KSI3 58 83 EC_MUTE#
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A ACZ_RST# EC_MUTE# <26>
59 KSI4/GPIO34 PSDAT1/GPIO4B 84 ACZ_RST# <19,24> 7 NC 2.500V 3.300V 3.300V
KSI5 60 85
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C TP_LED#
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 TP_LED# <28>
KSI7 62 87 TP_CLK TP_CLK <28> +5V
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <28>
+3VALW +3VS KSO1 40
KSO2 KSO1/GPIO21 CLK_ENABLE TP_CLK
41 KSO2/GPIO22 CLK_ENABLE <15> 2 1
KSO3 42 97 2 1 10K_0402_5% R361
KSO4 KSO3/GPIO23 SDICS#/GPXOA00 R360 10K_0402_5% TP_DATA
43 KSO4/GPIO24 SDICLK/GPXOA01 98 2 1
KSO5 10K_0402_5% R362
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
1

KSO6 45 109 WL_BTN#

R403 R404 KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 WL_BTN# <28>
46 KSO7/GPIO27 SPI Device Interface
10K_0402_5% 10K_0402_5% KSO8 47
+3VS +5VALW KSO9 KSO8/GPIO28 FR D#
48 KSO9/GPIO29 SPIDI/RD# 119 FRD# <29>
KSO10 49 120 FWR#
FWR# <29>
2

KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK

50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK <29>
KSO12 51 128 FSEL#
KSO12/GPIO2C SPICS# FSEL# <29>
LID_SW# WL_BTN# KSO13 52 KSO13/GPIO2D
1

KSO14 53
R363 R364 KSO15 KSO14/GPIO2E
54 KSO15/GPIO2F CIR_RX/GPIO40 73
1

4.7K_0402_5% 0214_Add Pull high resistor for LID_SW# and WL_BTN#. 81 74 VCC1_PW RGD
KSO16/GPIO48 CIR_RLC_TX/GPIO41 VCC1_PWRGD <29>
R365 R366 4.7K_0402_5% 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <33>
4.7K_0402_5% 90
2

4.7K_0402_5% BATT_CHGI_LED#/GPIO52 CAPS_LED#

CAPS_LED#/GPIO53 91 CAPS_LED# <28,29>
SMB_EC_DA1 SMB_EC_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BAT_LED#
<29,38> SMB_EC_CK1 BAT_LED# <28>
2

SMB_EC_CK1 SMB_EC_DA1 SCL1/GPIO44 ON/OFFBTN_LED#

<29,38> SMB_EC_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 ON/OFFBTN_LED# <28,29>
SMB_EC_DA2 SMB_EC_CK2 79 SM Bus 95 SYSON
<4> SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <28,31,35>
SMB_EC_CK2 SMB_EC_DA2 80 121 VR_ON
<4> SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <37>
ACIN
AC_IN/GPIO59 127
2
ACIN
1
<33> For EMI
R393 10K_0402_5% CP1
SLP_S3# 6 100 EC_RSMRST# JP25 KSO14 1 8
<20> SLP_S3# SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <20>
<20> SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 R397 1 0_0402_5%
2 EC_LID_OUT# <20>
KSO15 1 1
KSO11 2 7
EC_SMI# 15 102 EC_ON KSO10 2 KSO10 3 6
<20> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <28> 2
SUSP# LID_SW# 16 103 KSO11 3 KSO15 4 5
<28> LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 3
SUSP# 17 104 PM_PWROK KSO14 4
<24,31,33,35,36> SUSP# SUSP#/GPIO0B ICH_PWROK/GPXO06 PM_PWROK <7,20> 4
PWRBTN_OUT# 18 GPO 105 BKOFF# KSO13 5 @ 100P_1206_8P4C_50V8
<20> PWRBTN_OUT# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <17> 5
1

PCI_PME# 19 GPIO 106 M_PWROK KSO12 6 CP2

R402 <18,23> PCI_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 M_PWROK <7,20> KSO3 6 KSO6
25 EC_THERM#/GPIO11 GPXO10 107 7 7 1 8
100K_0402_5% 28 108 KSO6 8 KSO3 2 7
TP_BTN# FAN_SPEED1/FANFB1/GPIO14 GPXO11 KSO8 8 KSO12
<28> TP_BTN# 29 FANFB2/GPIO15 9 9 3 6
UTX 30 KSO7 10 KSO13 4 5
2

URX EC_TX/GPIO16 SLP_S4# KSO4 10

31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SLP_S4# <20> 11 11
ON/OFF 32 112 KSO2 12 @ 100P_1206_8P4C_50V8
<28> ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 12
34 114 KSI0 13
NUM_LED# PWR_LED#/GPIO19 GPXID3 THERM_SCI# KSO1 13
<28,29> NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 THERM_SCI# <20> 14 14
CP3
116 KSO5 15 KSO2 1 8
EC DEBUG port GPXID5
117 KSI3 16
15 KSO4 2 7
GPXID6 KSI2 16 KSO7
0205_Add Pull down R402 for SUSP#. GPXID7 118 17 17 3 6
1 2 C RY2 122 KSO0 18 KSO8 4 5
@ JP26 XCLK1 KSI5 18
123 XCLK0 V18R 124 19 19
1 10P_0402_50V8J KSI4 20 @ 100P_1206_8P4C_50V8
1 +5VALW 20
1

AGND

2 URX C426 KSO9 21 CP4

GND
GND
GND
GND
GND

2 UTX KSI6 21 KSI3

3 3 3 NC OUT 4 22 22 1 8
4 @ 20M_0402_5% KSI7 23 KSO5 2 7
4 R368 KB926QFB0_LQFP128_14X14 KSI1 23 KSO1
2 IN 1 24 3 6
11
24
35
94
113

69

ACES_85205-0400 NC 24 KSI0 4 5
2

Y4 32.768KHZ_12.5P_1TJS125DJ2A073
1 2 C RY1 @ 100P_1206_8P4C_50V8
25
FOR LPC SIO DEBUG PORT 10P_0402_50V8J +3VALW_EC 26
GND1
GND2
CP5
@ JP24 KSI4 1 8
ECAGND

1 +5VS ACES_85201-24051 KSI5 2 7

1
1

2 C427 CONN@ KSO0 3 6

2 +EC_AVCC L14 KSI2
3 3 +3VS 4 5
4 0_0603_5%
4 @ 100P_1206_8P4C_50V8
5 5
6 L15 SP01000FF00 85201-24051 24P P1.0
CLK_14M_DEBUG <15> CP6
2

6 LPC_AD0 ACES_85201-24051_24P
7 7 1 2 1 2
8 LPC_AD1 C428 0_0603_5% KSI1 1 8
8 LPC_AD2 0.1U_0402_16V4Z KSI7
9 9 2 7
10 LPC_AD3 3 6
10 LPC_FRAME#
11 11 4 5
12 LPC_DRQ#0 LPC_DRQ#0 <19>@ R383
12 PCI_RST# 10K_0402_5% @ 100P_1206_8P4C_50V8
13 13
14 14 2 1
15 CLK_DEBUG_PORT
15 CLK_DEBUG_PORT <15,22,29>
16 SIRQ
16
17 17
Security Classification Compal Secret Data Compal Electronics, Inc.
18 18 Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
19
19
20 20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
ACES_85201-2005 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 30 of 40
 A B C D E

1
+5VALW to +5VS Transfer +3VALW to +3VS Transfer 1

+5VALW +5VS +3VALW +3VS

B+
U19 U20
8 1 8 1 10U_0805_10V4Z
D S D S

1
7 D S 2 7 D S 2
1 6 3 R369 1 6 3
C429 D S C430 D S
5 D G 4 1 1 5 D G 4 1 1
C431 C432 330K_0402_5% C433 C434
AO4422_SO8 AO4422_SO8

2
2 10U_0805_10V4Z 10U_0805_10V4Z 2 10U_0805_10V4Z
2 2 2 2
RUNON RUNON

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
R370

470_0402_5%

1
D

2
SUSP 2 Q23 1
G 2N7002_SOT23-3 C435
S

3
0.01U_0402_16V7K
2

2 2

+5VALW +5VALW
C436
1

1
+VCC_CORE 1 2 +VCCP
R371 R372

100K_0402_5% 100K_0402_5% 0.1U_0402_16V4Z

2

2
C437
SYSON# SUSP +VCCP 1 2 +1.5VS
<27,35> SYSON# <35> SUSP

0.1U_0402_16V4Z
1

1
D D
SYSON 2 Q24 SUSP# 2 Q25
<28,30,35> SYSON <24,30,33,35,36> SUSP#
G 2N7002_SOT23-3 G 2N7002_SOT23-3
S S
3

3
3 3

Discharge circuit H1 H2 H3 H5 H6 H7 H8 H9 H10

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
+5VS +3VS +1.8V +1.5VS +1.25VS +VCCP +0.9V

1
1

1
R374 R373 R375 R376 R377 R378 R379

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

2

H24 H25 H26 H11 H12 H15 H16 H17 H18 H21 H23
HOLEA HOLEA HOLEC H27 HOLEA HOLEA HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC
1

D D D D D D D HOLEA
SUSP 2 Q26 SUSP 2 SYSON# 2
Q27 Q28 SUSP 2 Q29 SUSP 2 Q30 SUSP 2 Q31 SUSP 2 Q32
G 2N7002_SOT23-3
G 2N7002_SOT23-3
G 2N7002_SOT23-3
G 2N7002_SOT23-3
G 2N7002_SOT23-3
G 2N7002_SOT23-3
G 2N7002_SOT23-3

1
S S S S S S S
3

1
FM1 FM2 FM4
For Card reader/B stand off. 1 1 1
4 4

CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8

1 1 1 1 1 1 1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 31 of 40
A B C D E
 A B C D

1 1

2 2

VIN

PL1
HCB4532KF-800T90_1812
PCN1
1 ADPIN 1 2
1
2 2

1000P_0402_50V7K
3 3
4 4

1
PC4
100P_0402_50V8J

5 PC1
5
1

1
PC3

ACES_88334-057N

2
100P_0402_50V8J PC2
2

1000P_0402_50V7K

+3VALW
3 3
PQ38
3

TP0610K-T1-E3_SOT23

2 AC_LED <33>
1

PR157
100_0402_5%
1 2

4 4

Security Classification Compal Secret Data

Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
DC CONN Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 32 of 40
A B C D
 A B C D

P2
VIN
PQ1 PQ2
FDS4435BZ_SO8 FDS4435BZ_SO8
8 3 3 8
B+
7 2 2 7 PQ3
FDS4435BZ_SO8
BATT
6 1 1 6
5 5 3 8
PR3 2 7

0.1U_0603_16V7K
47K_0402_5% 1 6

4
P4
2 1 5

1
47P_0402_50V8J
2

1
PC6
PR4 PR5

4
PC5
1 1
200K_0402_5% 1 2 VIN
2 47K_0402_5%

2
1

2
PQ4
PR6 PL2
PR7

2
47K_0402_1% DTA144EUA_SC70-3 SMB3025500YA_2P
1 2 2 1 2 1 2
CHG_B+ PR2

1
10K_0402_5%
1

4.7U_1206_25V6K
PQ5

0.1U_0603_25V7K

2200P_0402_50V7K

4.7U_1206_25V6K
2 DTC115EUA_SC70-3 0.015_2512_1%

1
G PR8
3

1
PC7

PC8

PC9

PC10
S PQ6 150K_0402_5% ACOFF#
3

RHU002N06_SOT323-3 <30> ADP_I 2 1

2
2

1
<32> AC_LED

RHU002N06_SOT323-3
PR9 CHG_B+ PR10 PQ11

1
PC11 10K_0402_5% 100K_0402_5% D

PQ7
0.22U_0603_16V7K +3VLP 2 1 2 DTC115EUA_SC70-3

1
PU1 G

1
D ACOFF <30>

0_0402_5%
MB39A126PFV-ER_SSOP24 S 2
PR11

3
1
2
3

1
D

PR13
P ACIN 1 2 2 PQ8 1 -INC2 +INC2 24
3K_0402_5% G RHU002N06_SOT323-3 PR12 PC12 PR14 P ACIN 2
S 10K_0402_1% 4700P_0402_25V7K 100K_0402_1% G

3
MB39A126 1 2 1 2 2 1 ADP_I_A 2 23 4 PQ10 PQ9 S
PD5

3
OUTC2 GND PC13 RHU002N06_SOT323-3
ACOFF# 1 2 0.22U_0603_16V7K
3 22 CS 1 2 FDS4435BZ_SO8
+INE2 CS PC14
1SS355_SOD323-2

34.8K_0603_1%
0.1U_0603_25V7K

10K_0402_1%
0.01U_0402_25V7K
4 21 1 2

5
6
7
8
-INE2 VCC

1
1

PC15

PR15

PR16
VREF 65W: PR46=34.8K 5 20
2
ACOK OUT PC16 2

90W: PR46=21.0K

2
0.1U_0603_25V7K

2
6 19 1 2 PL3
VREF VH PR17

0.22U_0603_16V7K
16UH_SIL1045R-160_4.1A_30%
1 2 1 2
BATT
PR18

1
PC17
1 2 7 ACIN XACOK 18

EC31QS04
1M_0402_5% PR19 PC18 PR20 0.02_1206_1%
P2

PD1
1K_0402_1% 2200P_0402_50V7K 47K_0402_1%

2
MB39A1261 2 1 2 8 17 1 2
VIN -INE1 RT

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
2
1

1
VIN
IREF <30>

PC19

PC20

PC21
PR160 1 2 9 16
PR25 +INE1 -INE3 PR26 PC23
47_1206_5%

2
133K_0603_1%

100K_0402_1%

1U_0603_6.3V6M
PR21 10K_0402_1% 33K_0402_1% 1500P_0402_50V7K
1

PC22
150K_0402_1% 2 1 10 15 MB39A126 1 21 2
PR146
2

OUTC1 FB123
1

PR24
1
PR23

PR22 1 2 PD2

2
PC24 10K_0402_1% ACIN <30> 11 14 1 2 FSTCHG
SEL CTL

100K_0402_1%
0.1U_0603_25V7K PC25
2

2
1K_0402_5%

1
PR27 10P_0402_50V8J RB751V-40_SOD323-2
2

PR1
2.15K_0402_1% PU2A 12 13 1 2 PD3
-INC1 +INC1
1 2 3 3.2V 1 2
P

+ SUSP# <24,30,31,35,36>
0.047U_0402_16V7K

1 P ACIN
O
1

PACIN <34>
10K_0603_0.1%

2 RB751V-40_SOD323-2

2
-
1

G
PC26

PR28

LM393DG_SO8
4

PR29
2

PD4 10K_0402_5%
2

P2 RLZ4.3B_LL34
2

PC27
PR30 47P_0402_50V8J
3 1 2 1 2 3

BATT
22P_0402_25V8K

51K_0402_1%
1
PC28

499K_0402_1% 340K_0402_1%
1

PU3 +5VALW
1.24VREF +3VALW
PR31
2

4 3 +3VALW
REF CATHODE CV=12.6V (6/12 CELLS LI-ION)
0.01U_0402_25V7K

2 CC=3.08A (6/12 CELLS LI-ION)

2

NC

2
1

PC29

5 1 PR158
ANODE NC
1

2
100K_0402_5%
PR32

PR159
2

LMV431ACM5X_SOT23-5 100K_0402_5%

1
2

1
8

PR35

1
10K_0402_5% D
3
P

+3VALW <30> BATT_OVP 1 2 1

+ PQ37 2 BATT_DET <38>
0 RHU002N06_SOT323-3 G
- 2
G
47K_0402_1%

105K_0402_1%

CS S

3
1

0.01U_0402_25V7K
4

1
PR33

PR34

PU4A
PC30

LM358ADT_SO8
2
2

2
1

D
2 PQ12
G RHU002N06_SOT323-3
1

S +5VALW
3

PQ13
DTC115EUA_SC70-3
4
PU4B 4

2 LM358ADT_SO8
8

<30> FSTCHG
5
P

+
7 0
6
3

-
4 G

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 14, 2007 Sheet 33 of 40
A B C D
 A B C D E

PC31 PC32
PL4 0.1U_0603_50V4Z 0.1U_0603_50V4Z
B++
1 2 BST_5V_B BST_3.3V_B 1 2
FBM-L11-322513-151LMAT_1210

2
B+ 2 1

2200P_0402_50V7K

10U_1206_25V6M
B++
1 PD6 1

8
7
6
5
CHP202UPT_SOT323-3

2200P_0402_50V7K
PQ15 VL

4.7U_1206_25V6K
AO4468_SO8

1
PC33

PC34
PR39

5
6
7
8
0_0402_5%

PC36

PC37
4DH_5V_B 1 2 PQ16

47_0402_5%
B++ AO4468_SO8

2
1
2

PR40
PC35

0.1U_0603_50V4Z
PR41 0.1U_0603_16V7K 4

1
2
3

2
0_0402_5%

2
8
7
6
5
PR42

1
PQ35 0_0402_5%

3
2
1
AO4468_SO8 VL 2VREF_1999 DH_3.3V_B

4.7U_0805_10V4Z

1
1

2
1U_0805_16V7K
1

1
0_0402_5%

PC38

PC39
4 1
PR44

2
PR43

PC40
PL5

2
10U_LF919AS-100M-P3_4.5A_20% 0_0402_5%

5
6
7
8
2

0_0402_5%
1
2
3

2
@499K_0402_1%

@499K_0402_1%
PQ36

18

20

13

17
2

2
PU5 AO4468_SO8

PR47
BST_5V 14

PR45
V+
LD05

TON

VCC
BST5

PR46
ILIM3 5
DH_5V 16 4

1
DH5

1
+5VALWP

1
2 LX_5V 15 2
DL_5V LX5
19 DL5 ILIM5 11
@10.2K_0402_1%

21 PL6

3
2
1
OUT5 BST_3.3V 10U_LF919AS-100M-P3_4.5A_20%
9 FB5 BST3 28
2

1 26 DH_3.3V

2
B++ PR49 N.C. DH3
PR48

2VREF_1999 1 2 24 DL_3.3V
0_0402_5% DL3 LX_3.3V
6 SHDN# LX3 27
PC41 1 PR50 4 22
ON5 OUT3
1
47K_0402_5%

2VREF_1999 1 2 3
1

ON3
220U_6.3VM_R15

+ @0_0402_5% 7
FB3
PR51

1 2 12 SKIP# PGOOD 2 +3VALWP

2

0_0402_5%

PR52
2

PRO#
PR53

@3.57K_0402_1%
LDO3
@10K_0402_5% 8

GND
2

REF

2
2VREF_1999
0.1U_0603_25V7K

PR54
MAX8734AEEI+_QSOP28
1

23

25

10
1

0.22U_0603_10V7K
VL +3VLP 1

4.7U_0805_10V4Z
MAINPWON MAINPWON <38>

1
1
PC42

PC44
+
1
2

2
300K_0402_5%
PC43
PR55

2
PR56

PC45
2 1 PR57 220U_6.3VM_R15

2
0_0402_5% 2
499K_0603_1% 2

PR58
0_0402_5%
1

1
PC46
2

0.047U_0603_16V7K
1
VL
3 3

PR59
PQ17 100K_0402_5%
1

D
2

2 PQ26
G
S RHU002N06_SOT323-3 TP0610K-T1-E3_SOT23
3

1
D D
2 PACIN <33> 2 1 3 +3VLP
G G
S PQ18 S PQ19
3

2
RHU002N06_SOT323-3 RHU002N06_SOT323-3

2
PR156
PR154 100K_0402_5%
100K_0402_5%

1
1
<28> 51ON#

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP / 5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 34 of 40
A B C D E
 5 4 3 2 1

PL7
FBMA-L11-322513-151LMA50T_1210
B+ 2 1 1.8V_B+

+5VALW

2200P_0402_50V7K

10U_1206_25V6M
1
1

1
PC48

5
6
7
8
PC49

10_0402_5%
PC47
2

2
D 680P_0402_50V7K PQ21 D

1
AO4468_SO8

PR61
PR62
1M_0402_5%

2
PD7 4

2
1SS355_SOD323-2

1
PC54

BOOT_1.8V 1

3
2
1
1000P_0402_50V7K

2
<28,30,31> SYSON 1 2
PR65 UG_1.8V

1
PR64 PR66 1 2 BOOT1_1.8V 1 2 PL8

1
0_0402_5% 100K_0402_5% 0_0402_5% 3.3UH_SIL1045R-3R3PF_8.2A_30%
PC55 PC56 1 2 +1.8VP
@2200P_0402_25V7K 0.1U_0402_16V7K

16

15

14

13
2
PU6

220U_6.3VM_R15

0.1U_0402_16V7K

0.1U_0402_16V7K
1

EN/PSV
TON

NC

BST

5
6
7
8

1
PC50

PC51

PC52
1 12 PQ22 +
VOUT DH

1
FDS6690AS_NL_SO8 PR68
PC57 2 11 LX_1.8V @4.7_1206_5%

2
1U_0603_10V6K VCCA LX PR69 2

2
3 10 1 2 4

2
FB ILIM 16.9K_0402_1%
4 PGD VDDP 9

1
PGND
VSSA
PC58

1
@680P_0603_50V7K

NC
TP

DL

3
2
1
PC59

2
C SC411MLTRT_MLPQ16_4X4 C
1U_0603_10V6K

17

2
LG_1.8V +5VALW

1
PC126 +1.5VS
1U_0603_6.3V6M

2
PR70
1 2

6
27K_0603_0.1% PU13

1
5

VCNTL
VIN PC129
1 2 1 2 7 POK
PR147 9 10U_1206_6.3V6M

2
PC60 @ 0_0402_5% VIN
33P_0402_50V8J 3
VOUT

1
PR71
<24,30,31,33,36> SUSP# 1 2 8 EN VOUT 4 +1.25VSP
10K_0603_0.1% PR148

GND
1

1
0_0402_5% 2
2 FB PC130
PC127 22U_1206_6.3V6M

2
1
@ 0.01U_0402_16V7K

1
PR149
33.2K_0402_1% PC128

2
APL5913-KAC-TRL_SO8 47P_0402_50V8J

2
B B

1
PJP1 PJP2

+5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9) +1.25VSP 1 2 +1.25VS(500mA,40mils ,Via NO.= 1)

PR150
PAD-OPEN 3x3m +1.8V 59K_0402_1%
PAD-OPEN 4x4m

2
PJP3
1 2 +3VALW (3A,120mils ,Via NO.= 6) PJP4 PU8
+3VALWP
+3VLP 2 1 +3VL (100mA,20mils ,Via NO.= 1) 1 VIN VCNTL 6 +5VALW
PAD-OPEN 4x4m

10U_0805_10V4Z
PAD-OPEN 2x2m 2 5
GND NC

1
PJP5

PC64

1
1 2 +1.8V (7A,280mils ,Via NO.= 14) PC63 3 7
+1.8VP VREF NC

1
10U_0805_10V4Z

2
PAD-OPEN 4x4m PR72 PC65
4 VOUT NC 8
1K_0402_1% 1U_0603_16V6K

2
PJP6 9

2
1 2 +VCCP (6A,240mils ,Via NO.=12) <7,13,14> V_DDR_MCH_REF @ TP
+1.05V_VCCP
G2992F1U_SO8
PAD-OPEN 4x4m
<27,31> SYSON# 1 2

0.1U_0402_16V7K
PJP7 PR73 +0.9VP

1
+1.5VSP 1 2 +1.5VS (6A,240mils ,Via NO.=12) @0_0402_5%
PQ20
PAD-OPEN 4x4m RHU002N06_SOT323-3 PR67

1
D
PJP8 1K_0402_1%
1 2 2 PC67
<31> SUSP

PC66
1 2 +0.9V (2A,80mils ,Via NO.= 4) PR60 G 10U_1206_6.3V7K
+0.9VP

2
0_0402_5% S

3
1
A PAD-OPEN 3x3m A
PC68

2
@0.1U_0402_16V7K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VP/0.9VSP/2.5VSP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 14, 2007 Sheet 35 of 40
5 4 3 2 1
 5 4 3 2 1

PL9 B+++
FBMA-L11-322513-151LMA50T_1210
B+ 1 2

@2200P_0402_50V7K
1

1
PR76 PR77

PC71
PC72 PR74 PR75 75K_0402_1% 29.4K_0402_1%

@2200P_0402_50V7K
4.7U_1206_25V6K 73.2K_0402_1% 75K_0402_1%

10U_1206_25V6M
1 2 1 2 1 2 1 2
D D

1
PC69

PC70
2

2
2
PR78

5
6
7
8
0_0402_5%
PC131 PQ24
AO4468_SO8
1 2

1
0.1U_0603_16V7K 4
VCCP_POK

1
PU9

VO2

VFB2

TONSEL

VFB1

VO1
GND
25

3
2
1
PR79 P PAD
0_0402_5% PR82
PQ23 PR80 PR81 0_0402_5%
1 2 1 2 7 PGOOD2 PGOOD1 24 2 1
1 8 UG1_1.5V 0_0402_5% 0_0402_5% 1 2UG1_1.05V
D2 G2 PR83 PL10
2 7 PC77 8 23
3
D2 D1/S2/K
6 0_0402_5% EN2 EN1 PR84 2.2UH_PCMC063T-2R2MN_8A_20% +1.05V_VCCP
G1 D1/S2/K PC78
4 5 2 1 1 2 BST_1.5V 9 22 BST_1.05V 0_0402_5% <BOM Structure>
S1/A D1/S2/K VBST2 VBST1
1 2 1 2 1 2
+1.5VSP PL14 SP8K10S FD5 2N SOP8 UG_1.5V 10 21 UG_1.05V
0.1U_0603_25V7K DR VH2 DR VH1

220U_6.3VM_R15
3.3UH_SIQB74B-3R3PF_5.9A_20% 0.1U_0603_25V7K
11 LL2 LL1 20
2 1 LX_1.5V LX_1.05V 1

5
6
7
8
12 DR VL2 DR VL1 19

PC73
LG_1.5V LG_1.05V +
PC74

PGND2

PGND1
V5FILT
TRIP2

TRIP1
4.7U_0805_6.3V6K

V5IN

2
2
1
220U_6.3VM_R15

C 4 C
2
PC75

+ TPS51124RGER_QFN24_4x4 PQ25

13

14

15

16

17

18
PC76 FDS6690AS_NL_SO8
4.7U_0805_6.3V6K
1

3
2
1
1
PR85
PR87 15K_0402_1% PR86
0_0402_5% 1 2 18K_0402_1%
<24,30,31,33,35> SUSP# 2 1

2
1
PC79

1
@1000P_0402_50V7K
2

1
PR88
PC80 3.3_0402_5%
1U_0603_10V6K

2
+5VALWP

1
PC81 1 2 SUSP#
4.7U_1206_25V6K
0_0402_5%

2
PR89

1
PC82

2
@1000P_0402_50V7K

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.2V_VP/1.5VSP/1.05VP
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 14, 2007 Sheet 36 of 40
5 4 3 2 1
 5 4 3 2 1

+5VS CPU_B+ B+
PL11
SMB3025500YA_2P

2 1

2200P_0402_50V7K

1000P_0402_50V7K
0.01U_0402_25V7K

47U 25V M 6.3X6 ESR0.44 CE-LX

1

1
10U_1206_25V6M

10U_1206_25V6M
PC91

PC95
PR94

PC92

PC93

PC94

PC96
+
10_0402_5%

2
PC90

2
D D

2.2U_0603_6.3V6K 2

1
1U_0603_16V6K

200K_0402_5%
1

PR96
PC97
PR95

1
13K_0402_5% BSTM1 CPU

2
2

0.22U_0603_16V7K

5
6
7
8
PU12
@470KB_0402_5%_ERTJ0EV474J

D
D
D
D
2
PC98
PH4 V CC 19 25 PQ27
Vcc VDD SI4684DY-T1-E3_SO8
2 1
6 8

1
THRM TON

G
S
S
S
2 1 31 30 BST1_CPU 2 1

4
3
2
1
<5> CPU_VID0 PR98 0_0402_5% D0 BST1 PR99 0_0402_5% PL12
+VCC_CORE
2 1 32 29 PR101 2.2_0603_5%
<5> CPU_VID1 PR100 0_0402_5% D1 DH1 DH11_CPU 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
2 1 33 28 LX1_CPU
<5> CPU_VID2 PR97 0_0402_5% D2 LX1 +VCC_CORE
1 2
2 1 34 26 DL1_CPU
<5> CPU_VID3 D3 DL1

2
PR102 0_0402_5%

4.7_1206_5%
2 1 35 27 PR105
<5> CPU_VID4 D4 PGND1

D 5
D 6
D 7
D 8

5
6
7
8
FDS6676AS_SO8

FDS6676AS_SO8
PR104 0_0402_5% 2.1K_0603_1%

1
2 1 36 18

D
D
D
D
<5> CPU_VID5 D5 GND

PQ28

PQ29

PR107
PR103 0_0402_5% NTC

DL1_CPU

1
2 1 37 17 CSP1_CPU PH2
<5> CPU_VID6 PR106 0_0402_5% D6 CSP1

4 G

G
3 S
2 S
1 S

S
S
S
C CSN1_CPU C
2 1 7 16 1 2 1 2

2
TIME CSN1

680P_0603_50V7K
PR108 71.5K_0402_1% PR109

4
3
2
1
1 2 9 12 FB1_CPU 3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J
CCV FB

PC101
PC99 470P_0402_50V8J
1 2 11 10 CC1_CPU 1 2
PC100 0.22U_0603_16V7K REF CCI

2
1 2 39 21 DH2_CPU PC102
<7,20> DPRSLPVR PR110 499_0402_1% DPRSLPVR DH2 0.22U_0603_16V7K
1 2 40 20 BST2_CPU
<5,7,19> H_DPRSTP# PR112 0_0402_5% DPRSTP BST2
1 2 3 22 LX2_CPU
<5> H_PSI# PSI LX2

0_0402_5%
PR111 0_0402_5%
2 24 DL2_CPU
PWRGD DL2
+3VS
1 CLKEN PGND2 23

2
1 2 1 2 VCCSENSE
38 14 CSP2_CPU PR115 @3K_0603_1% PC103 @0.022U_0402_16V7K VCCSENSE <5>
SHDN CSP2
5 15 CSN2_CPU 1 2 1 2
VRHOT CSN2
1

PR114
PR118 3.65K_0402_1% PR116 100_0402_5%

1
2

1
PR117 4 13 PC104
PR119 POUT GNDS
2K_0402_1%
1.91K_0402_1% 1 2 1 2 4700P_0402_25V7K

2
TP

BSTM2 CPU
2

NTC PR120 PR121

1

1 2 MAX8770GTL+_TQFN40 @3K_0603_1% @3K_0603_1%

41

<15,20> VGATE PR123 0_0402_5% 1 2 1 2

1000P_0402_50V7K

1 2 CPU_B+
1

CLK_EN#
PC105

PR122 0_0402_5% PR124 PC106

1 2 20K_0402_1% 470P_0402_50V8J
<30> VR_ON
1

PR125
2

0.22U_0603_16V7K
B 0_0402_5% B

2
PR126

2200P_0402_50V7K
@10K_0402_5%
2

1
10U_1206_25V6M

10U_1206_25V6M
2

1
PC109

PC107

PC108
PR127

5
6
7
8

PC110
100_0402_5%

2
D
D
D
D

2
1 2 PQ30
1

<4> H_PROCHOT# PR128 @0_0402_5% SI4684DY-T1-E3_SO8

G
S
S
S
POUT 1 2 VSSSENSE PL13
PR129 10K_0402_5% <5> VSSSENSE

4
3
2
1
2

PR130 2.2_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%

PC111 1 2
0.1U_0402_16V7K 1 2
1

4.7_1206_5%
1
D 5
D 6
D 7
D 8

5
6
7
8

2
FDS6676AS_SO8

FDS6676AS_SO8

PR131
PR132

D
D
D
D
PQ31

PQ32
2.1K_0603_1%

680P_0603_50V7K
DL2_CPU

1
4 G

G
3 S
2 S
1 S

S
S
S
NTC

PC112
PH3

4
3
2
1
1 2 1 2

2
PR133
3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J
A A

1 2
PC113 0.22U_0603_16V7K

Compal Electronics, Inc.

Title
+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, March 14, 2007 Sheet 37 of 40
5 4 3 2 1
 A B C D

VMB PL15 BATT

PCN2
HCB4532KF-800T90_1812
BATT+ 6 1 2

5 EC_SMD
SMD BATT_DET <33>
4 EC_SMC
SMC PR151
RES 3 2 1

1
TS 2 @1K_0402_5%
1 1

2
1 PC122 PC123

2
GND PD8 @SM05_SOT23 1000P_0402_50V7K 0.01U_0402_50V4Z
3
TYCO_C-1746706_6P 1
2

PR152 PD9

1
6.49K_0402_1% @SM24.TC_SOT23-3
1 2 +3VL

1
1

1
PR153
1K_0402_5%
PR138

2
PR139
100_0402_5% 100_0402_5%
BATT_TEMP <30>

2
SMB_EC_DA1 SMB_EC_DA1 <29,30>
SMB_EC_CK1 SMB_EC_CK1 <29,30>

2 2

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

PR140
+5VS 47K_0402_1%
1 2

+5VS

CPU
1

2
3 3

PR141
PH1 10K_0402_5%
2

10K_TH11-3H103FT_0603_1%

1
MAINPWON <34>
PR142

8
15K_0603_1% PU2B

1
D
1 2 5

P
+ PQ33
O 7 2
+5VS 1 2 6 G RHU002N06_SOT323-3
-

G
PR143 S

3
150K_0402_1% LM393DG_SO8

4
1

PR144
1

2.55K_0603_1%
PC124 PC125
0.22U_0603_10V7K PR145 1000P_0402_50V7K
2

150K_0402_1%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date <Issued_Date> Deciphered Date <Deciphered_Date> Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-3732P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 40 of 38
A B C D
 5 4 3 2 1

Version change list (P.I.R. List) Power section Page 1 of 1

D Item Reason for change PG# Modify List Date Phase D

HW request. Modify 1.25VSP enable signal from SLP_S3# to SUSP#.

1 35 2/13
Change PR152 from 210K to 6.49K
2 38 Change PR152 from 210K to 6.49K 2/13
Follow Volga 2.0 design.
3 37 Delete PC118,PC119,PC120,PC121,PR113,PR134. 3/6
For layout concern. Change PC95 location behind PL11.
4 37 3/8
Prevent S3 leakage issue. Change PD3 pin 2 connect from EC_ON to SUSP#
5 33 3/9
Prevent LMV431 will oscillate. Change PR30 from 75K to 51K.
6 33 3/9
Prevent LMV431 will oscillate. Change PC28 from 0.022u to 22P.
7 33 3/9
C EMI request add CPU core snabber and gate driver use 2.2_0603 Change PR101&PR130 from 0_0402 to 2.2_0603 C
8 34 3/12
Modify DC in jack LED design for energy star. Add PQ105.
9 35 3/12

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/28 Deciphered Date 2007/02/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 39 of 40
5 4 3 2 1
 5 4 3 2 1

Version Change List ( P. I. R. List ) for HW Circuit

Item Change item Page Date Phase

D
1 Change C117 from 220uF to 10uF. 10 2/8 DB --> SI D
2 Remove R401. 19 2/5 DB --> SI
3 Change Crystal Y2 type (the same as Abita). 19 2/5 DB --> SI
4 Connect LAN_RST# from EC_RAMRST# to GND. 20 2/5 DB --> SI
5 Change ODD connector type. 22 2/13 DB --> SI
6 Change U11 power from +5VS to +5VALW. 24 2/12 DB --> SI
7 Change U11 enable signal from SLP_S3# to SUSP#. 24 2/8 DB --> SI

8
Reverse JP19 USB Connector and 27 2/12 DB --> SI
need to double check layout symbol.
9
Change Power and Battery charge LED 28 2/8 DB --> SI
power from +3VALW to +5VALW.
10 Change HDD LED power from +3VS to +5VS. 28 2/8 DB --> SI
11 Delete reserve component (D25 BSW2) for 14.1". 28 2/8 DB --> SI
12 Change R329, R333, R470 from 200 ohm to 470 ohm. 28 2/8 DB --> SI
13 Change R334, R339 from 200 ohm to 820 ohm. 28 2/8 DB --> SI
14 Add pull down resistor R402 (100k ohm) for SUSP#. 30 2/5 DB --> SI
C
15 Change C44, C49 type from DIP to SMD. 06 2/14 DB --> SI C
16 Add R402 pull high resistor for LID_SW#. 30 2/14 DB --> SI
17 Add R403 pull high resistor for WL_BTN#. 30 2/14 DB --> SI
18 Delete D19. 28 2/16 DB --> SI

19
Change R300 from 10 ohm to 47 ohm 24 2/16 DB --> SI
and C374 from 10pF to 33pF.
20 Delete JP27, R317, C392. 26 2/16 DB --> SI
21 Delete R297. 24 2/16 DB --> SI
22 Change RTC battery and connector. 19 2/26 DB --> SI
23 Change C413 and 414 package from 0603 to 0402. 28 2/26 DB --> SI
24 Add JP28 for USB card reader. 27 2/28 DB --> SI
25 Change R105 from 22 ohm to 0 ohm. 15 3/1 DB --> SI
26 Delete C49 and remount C46. 06 3/1 DB --> SI
27 Change JP16 and JP17 Audio Jack. 26 3/2 DB --> SI
28 Add R405. 04 3/6 DB --> SI
29 Change USB connector (JP19) type. 27 3/8 DB --> SI
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/28 Deciphered Date 2007/02/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3732P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 14, 2007 Sheet 40 of 40
5 4 3 2 1