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    A300d La-4581p Ktkae Rev1.0

    Uploaded by

    Alexander Bronnikov
    The document is a schematic for the Compal Electronics KTKAE LA-4581P motherboard. It contains confidential information about the board's design and components. The board supports AMD S1G2 CPUs and includes components like the ATI M82/86 GPU with VRAM, DDRII memory controller, HDMI and VGA ports, USB and SATA ports, LAN, and PCIe slots for accessories. It was created by Compal Electronics and contains a security classification marking it as confidential proprietary information.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    A300d La-4581p Ktkae Rev1.0

    Uploaded by

    Alexander Bronnikov
    107 views45 pages
    The document is a schematic for the Compal Electronics KTKAE LA-4581P motherboard. It contains confidential information about the board's design and components. The board supports AMD S1G2 CPUs and includes components like the ATI M82/86 GPU with VRAM, DDRII memory controller, HDMI and VGA ports, USB and SATA ports, LAN, and PCIe slots for accessories. It was created by Compal Electronics and contains a security classification marking it as confidential proprietary information.

    Original Title

    a300d La-4581p Ktkae Rev1.0

    Copyright

    © © All Rights Reserved

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    PDF, TXT or read online from Scribd

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    The document is a schematic for the Compal Electronics KTKAE LA-4581P motherboard. It contains confidential information about the board's design and components. The board supports AMD S1G2 CPUs and includes components like the ATI M82/86 GPU with VRAM, DDRII memory controller, HDMI and VGA ports, USB and SATA ports, LAN, and PCIe slots for accessories. It was created by Compal Electronics and contains a security classification marking it as confidential proprietary information.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    107 views45 pages

    A300d La-4581p Ktkae Rev1.0

    Uploaded by

    Alexander Bronnikov
    The document is a schematic for the Compal Electronics KTKAE LA-4581P motherboard. It contains confidential information about the board's design and components. The board supports AMD S1G2 CPUs and includes components like the ATI M82/86 GPU with VRAM, DDRII memory controller, HDMI and VGA ports, USB and SATA ports, LAN, and PCIe slots for accessories. It was created by Compal Electronics and contains a security classification marking it as confidential proprietary information.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 45

    A B C D E

    1 1

    Compal confidential
    2 2

    Los Angeles 10A+/10AG+


    KTKAE LA-4581P REV1.0 Schematics Document

    Mobile AMD S1G2 /RS780M&RS780MC&RX781/SB700


    3
    2009-8-04 Rev. 1.0 3

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    2008/04/14 2009/04/14 Title
    Issued Date Deciphered Date SCHEMATIC MB A4581
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 1 of 45
    A B C D E
    A B C D E

    Compal Confidential Fan Control AMD S1G2 CPU Thermal Sensor Clock Generator
    page 4
    Model Name : KTKAE ADM1032ARMZ page 6 SLG8SP626 page 15
    uFCPGA-638 Package
    File Name : LA-4581P page 4,5,6,7
    1 1
    Hyper Transport Link 2.6GHz
    Griffin Platform 16X16
    ATI M82/86 VGA Conn
    with VRAM Page 19

    TV-OUT ATI
    page 16

    CRT RS780M
    page 16

    LCD Conn. RS780MC Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2


    page 17 Dual Channel BANK 0, 1, 2, 3 page 8,9
    RX781 1.8V DDRII 667/800MHZ
    EC SMBUS HDMI CEC Controller HDMI Conn.
    page 18
    R5F211A4SP page 18

    2
    page 10,11,12,13,14 2
    PCIeMini Card PCIeMini Card
    WLAN GPS/UWB
    PCIe Port 2 page 27 PCIe Port 5 page 27 A-Link Express II
    4X PCI-E
    PCIe 4x USB Conn Int. Camera Bluetooth Finger Print
    USB Port 4 USBPort 9 USBPort 6 USBPort 7
    1.5V 2.5GHz(250MB/s) page 31 page 29 page 31 page 31

    USB 7x
    RTL8111C/8102E JMB380 5V 480MHz
    LAN 1G/10/100M 5IN1/1394 PCIe 1x
    PCIe port 3 page 26 PCIe port 1 page 28 NEW Card 1.5V 2.5GHz(250MB/s) ATI
    USB port 11 USB Reserve GPS
    PCIe port 0 page 27 USBPort 8 USBPort 10
    5V 480MHz page 27 page 27
    RJ45 1394 5IN1 PCIe 1x
    SB700
    page 26 page 28 page 28 eSATA 1.5V 2.5GHz(250MB/s) SATA SATA HDD0
    USB port 2 USB 5V 1.5GHz(150MB/s) port 0 page 25
    SATA port 2 page 31
    5V 480MHz
    3 3
    SATA SATA HDD1
    5V 1.5GHz(150MB/s) port 1 page 25
    page 20,21,22,23,24
    SATA SATA ODD
    5V 1.5GHz(150MB/s) port 3 page 25

    I2C from SB HD Audio 3.3V 24.576MHz/48Mhz


    RTC CKT. CRT/B
    page 16
    page 36 LPC BUS
    3.3V 33 MHz
    USB/B HDA Codec
    Power On/Off CKT. page 31
    FM tuner Debug Port ENE KB926 C1 MDC 1.5 ALC272
    page 32 page 32 page 33 page 32 page 29
    page 34

    Finger Printer/B
    page 31
    DC/DC Interface CKT. CIR Touch Pad Int.KBD SPI ROM RJ11 AMPLIFIER MIC CONN Int. MIC HP CONN Volume Control
    page 32 page 34 page 32 page 32 page 32 TPA6017 page 30 page 30 page 30 page 30
    page 35
    Power/B page 30
    4
    page 34 4

    Power Circuit DC/DC SPK CONN


    page 36,37,38,39 FUN/B page 30
    40,41,42,43 page 34
    Security Classification Compal Secret Data Compal Electronics, Inc.
    2008/04/14 2009/04/14 Title
    LED/B Issued Date Deciphered Date
    SCHEMATIC MB A4581
    page 34 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 2 of 45
    A B C D E
    A B C D E

    O MEANS ON X MEANS OFF


    Voltage Rails
    Symbol Note : @ : means just reserve , no build
    DEBUG@ : means just reserve for debug.
    : means Digital Ground
    +5VS
    Item CPU NB VGA SB
    L Layout Notes
    1
    +3VS
    GM@ S1G2 RS780M NA SB700 1

    power UMA@ : means for RS780M. PM@+PM1@ S1G2 RX781 M82/M86 SB700
    plane +2.5VS : means Analog Ground
    +1.8VS
    RV@+PM@ S1G2 RS780M M82 SB700
    +1.5VS
    GM@ S1G2 RS780MC NA SB700
    +1.1VS
    +B +5VALW +1.8V
    +VGA_CORE
    +3VL +3VALW +0.9V BTO Option Table
    +1.2V_HT
    +5VL +1.2VALW +0.9V
    State +CPU_CORE_NB
    +RTCVCC +3V_LAN
    +CPU_CORE_0 Function HDMI TV-out
    +CPU_CORE_1
    description (Y) (S)

    explain AMD(UMA) ATI VGA/B COMMON

    BTO IHDMI@ HDMI@ H@ TV@


    S0
    O O O O
    S1 Function 2nd HDD LAN Mini card RJ11/FM tuner 3G SIM slot
    2
    O O O O 2

    description (2H) (E) (C) (D2) (R) (M) (G)


    S3
    O O O X
    explain 10/100M Giga Two Crads RJ11 FM
    S5 S4/AC
    O O X X BTO HDD2@ 8102E@ 8111C@ WLAN@ GPS@ MDC@ FM@ 3G@

    S5 S4/ Battery only


    O X X X
    Function Felica BLUE TOOTH CIR CAMERA & MIC Finger printer
    S5 S4/AC & Battery
    don't exist X X X X description (J) (B) (I) (X) (F)

    explain CAMERA MIC

    BTO FLICA@ BT@ CIR@ CAM@ MIC@ FP@

    I2C / SMBUS ADDRESSING


    SMBUS Control Table
    DEVICE HEX ADDRESS THERMAL
    SENSOR
    SOURCE INVERTER BATT CEC CPU & SODIMM CLK CHIP MINI CARD LCD HDMI G-Sensor
    3
    DDR SO-DIMM 0 A0 10100000 ADM1032 I / II Slot 2 3

    DDR SO-DIMM 1 A4 10100100 SMB_EC_CK1


    CLOCK GENERATOR (EXT.) D2 11010010 SMB_EC_DA1
    KB926 X V V X X X X X X X
    SMB_EC_CK2
    SMB_EC_DA2
    KB926 X X X V X X X X X X
    I2C_CLK
    I2C_DATA
    RS780M
    X X X X X X X V X X
    EC SM Bus1 address EC SM Bus2 address DDC_CLK0

    Device HEX Address Device HEX Address


    DDC_DATA0
    RS780M X X X X X X X X V X
    DDC_CLK1
    Smart Battery
    HDMI-CEC
    16H
    34H
    0001 011X b
    0011 010X b
    ADI1032-1 CPU 98H
    ADI1032-2 VGA 9AH
    1001 100X b
    1001 101X b
    DDC_DATA1
    RS780M X X X X X X X X X X
    SCL0
    EC KB926C1 EC KB926C1
    Ext. VGA/B
    SDA0
    SB700 X X X X V V X X X V
    SCL1
    CS/B
    SDA1
    SB700 X X X X X X V X X X
    SCL2
    4
    SDA2
    SB700 X X X X X X X X X X 4

    SCL3
    SDA3
    SB700 X X X X X X X X X X
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 3 of 45
    A B C D E
    A B C D E

    1 1

    +1.2V_HT
    VLDT CAP.
    250 mil

    1 1 1 1 1 1
    C1 C2 C3 C4 C5 C6
    H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
    <10> H_CADIP[0..15] H_CADOP[0..15] <10>
    H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
    <10> H_CADIN[0..15] H_CADON[0..15] <10>

    Near CPU Socket


    +1.2V_HT
    JCPUA

    2 2
    VLDT=500mA D1 VLDT_A0 HT LINK VLDT_B0 AE2 +VLDT_B 1 2
    D2 AE3 C7 4.7U_0805_10V4Z
    VLDT_A1 VLDT_B1
    D3 VLDT_A2 VLDT_B2 AE4
    D4 VLDT_A3 VLDT_B3 AE5

    H_CADIP0 E3 AD1 H_CADOP0


    H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
    E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
    H_CADIP1 E1 AC2 H_CADOP1
    H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
    F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
    H_CADIP2 G3 AB1 H_CADOP2
    H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
    G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
    H_CADIP3 G1 AA2 H_CADOP3
    H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
    H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
    H_CADIP4 J1 W2 H_CADOP4
    H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
    K1 L0_CADIN_L4 L0_CADOUT_L4 W3
    H_CADIP5 L3 V1 H_CADOP5
    H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
    L2 L0_CADIN_L5 L0_CADOUT_L5 U1
    H_CADIP6 L1 U2 H_CADOP6
    H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
    M1 L0_CADIN_L6 L0_CADOUT_L6 U3
    H_CADIP7 N3 T1 H_CADOP7
    H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
    N2 L0_CADIN_L7 L0_CADOUT_L7 R1
    H_CADIP8 E5 AD4 H_CADOP8
    H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
    F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
    H_CADIP9 F3 AD5 H_CADOP9
    H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
    F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
    H_CADIP10 G5 AB4 H_CADOP10
    H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
    H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
    H_CADIP11 H3 AB5 H_CADOP11
    H_CADIN11 H4
    L0_CADIN_H11
    L0_CADIN_L11
    L0_CADOUT_H11
    L0_CADOUT_L11 AA5 H_CADON11
    +5VS
    FAN Control Circuit
    H_CADIP12 K3 Y5 H_CADOP12
    H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
    K4 L0_CADIN_L12 L0_CADOUT_L12 W5
    H_CADIP13 L5 V4 H_CADOP13 1A
    3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
    M5 L0_CADIN_L13 L0_CADOUT_L13 V3
    H_CADIP14 M3 V5 H_CADOP14
    L0_CADIN_H14 L0_CADOUT_H14

    1
    H_CADIN14 M4 U5 H_CADON14
    H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
    N5 L0_CADIN_H15 L0_CADOUT_H15 T4 1SS355_SOD323-2
    H_CADIN15 P5 T3 H_CADON15 2
    L0_CADIN_L15 L0_CADOUT_L15 D1
    C183 JFAN
    <10> H_CLKIP0 J3 Y1 H_CLKOP0 <10>

    2
    L0_CLKIN_H0 L0_CLKOUT_H0 10U_0805_10V4Z +FAN1
    <10> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <10> 1 1
    1
    <10> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <10> 2 2

    1
    <10> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <10> 2 3 3
    U6
    N1 R2 1 8 D2 C9 4
    <10> H_CTLIP0 L0_CTLIN_H0 L0_CTLOUT_H0 H_CTLOP0 <10> VEN GND GND
    P1 R3 2 7 @ 1000P_0402_25V8J 5
    <10> H_CTLIN0 L0_CTLIN_L0 L0_CTLOUT_L0 H_CTLON0 <10> VIN GND 1 GND
    P3 T5 +FAN1 3 6
    <10> H_CTLIP1 H_CTLOP1 <10>

    2
    L0_CTLIN_H1 L0_CTLOUT_H1 VO GND
    <10> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <10> <33> EAN_DFAN1 4 VSET GND 5 ACES_85204-0300N
    1 BAS16_SOT23-3
    G990P11U_SOP8
    @ 6090022100G_B C192
    10U_0805_10V4Z
    2
    2 1 +3VS
    R12 10K_0402_5%
    FAN_SPEED1 <33>
    2
    @ C8
    0.01U_0402_16V7K
    1

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 4 of 45
    A B C D E
    A B C D E

    Processor DDR2 Memory Interface


    PLACE CLOSE TO PROCESSOR
    WITHIN 1.5 INCH JCPUC
    <8> DDR_B_D[63..0]
    MEM:DATA
    DDR_A_D[63..0] <9>
    DDR_A_CLK0 DDR_B_D0 C11 G12 DDR_A_D0
    1 +1.8V DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1 1
    1 A11 MB_DATA1 MA_DATA1 F12
    DDR_B_D2 A14 H14 DDR_A_D2
    C10 DDR_B_D3 MB_DATA2 MA_DATA2 DDR_A_D3
    B14 MB_DATA3 MA_DATA3 G14
    2

    1.5P_0402_50V9C DDR_B_D4 G11 H11 DDR_A_D4


    R1 DDR_A_CLK#0 2 DDR_B_D5 MB_DATA4 MA_DATA4 DDR_A_D5
    E11 MB_DATA5 MA_DATA5 H12
    1K_0402_1% DDR_B_D6 D12 C13 DDR_A_D6
    DDR_A_CLK1 DDR_B_D7 MB_DATA6 MA_DATA6 DDR_A_D7
    A13 MB_DATA7 MA_DATA7 E13
    1 DDR_B_D8 A15 H15 DDR_A_D8
    1

    +MCH_REF DDR_B_D9 MB_DATA8 MA_DATA8 DDR_A_D9


    A16 MB_DATA9 MA_DATA9 E15
    1000P_0402_25V8J
    0.1U_0402_16V4Z

    C11 DDR_B_D10 A19 E17 DDR_A_D10


    MB_DATA10 MA_DATA10
    2

    1 1 1.5P_0402_50V9C DDR_B_D11 A20 H17 DDR_A_D11


    2 MB_DATA11 MA_DATA11
    C12

    C13

    R2 DDR_A_CLK#1 DDR_B_D12 C14 E14 DDR_A_D12


    1K_0402_1% DDR_B_D13 MB_DATA12 MA_DATA12 DDR_A_D13
    D14 MB_DATA13 MA_DATA13 F14
    DDR_B_D14 C18 C17 DDR_A_D14
    2 2 DDR_B_CLK0 DDR_B_D15 MB_DATA14 MA_DATA14 DDR_A_D15
    D18 G17
    1

    DDR_B_D16 MB_DATA15 MA_DATA15 DDR_A_D16


    1 D20 MB_DATA16 MA_DATA16 G18
    DDR_B_D17 A21 C19 DDR_A_D17
    C14 DDR_B_D18 MB_DATA17 MA_DATA17 DDR_A_D18
    D24 MB_DATA18 MA_DATA18 D22
    1.5P_0402_50V9C DDR_B_D19 C25 E20 DDR_A_D19
    DDR_B_CLK#0 2 DDR_B_D20 MB_DATA19 MA_DATA19 DDR_A_D20
    B20 MB_DATA20 MA_DATA20 E18
    DDR_B_D21 C20 F18 DDR_A_D21
    DDR_B_CLK1 DDR_B_D22 MB_DATA21 MA_DATA21 DDR_A_D22
    B24 MB_DATA22 MA_DATA22 B22
    1 DDR_B_D23 C24 C23 DDR_A_D23
    DDR_B_D24 MB_DATA23 MA_DATA23 DDR_A_D24
    E23 MB_DATA24 MA_DATA24 F20
    C15 DDR_B_D25 E24 F22 DDR_A_D25
    1.5P_0402_50V9C DDR_B_D26 MB_DATA25 MA_DATA25 DDR_A_D26
    G25 MB_DATA26 MA_DATA26 H24
    DDR_B_CLK#1 2 DDR_B_D27 DDR_A_D27
    G26 MB_DATA27 MA_DATA27 J19
    DDR_B_D28 C26 E21 DDR_A_D28
    DDR_B_D29 MB_DATA28 MA_DATA28 DDR_A_D29
    D26 MB_DATA29 MA_DATA29 E22
    DDR_B_D30 G23 H20 DDR_A_D30
    +0.9V +0.9V DDR_B_D31 MB_DATA30 MA_DATA30 DDR_A_D31
    G24 MB_DATA31 MA_DATA31 H22
    JCPUB DDR_B_D32 AA24 Y24 DDR_A_D32
    2 DDR_B_D33 MB_DATA32 MA_DATA32 DDR_A_D33 2
    AA23 MB_DATA33 MA_DATA33 AB24
    D10 W10 DDR_B_D34 AD24 AB22 DDR_A_D34
    VTT1 MEM:CMD/CTRL/CLK VTT5 DDR_B_D35 MB_DATA34 MA_DATA34 DDR_A_D35
    Place them close to CPU within 1" C10 VTT2 VTT6 AC10 AE24 MB_DATA35 MA_DATA35 AA21
    B10 AB10 DDR_B_D36 AA26 W22 DDR_A_D36
    VTT3 VTT7 DDR_B_D37 MB_DATA36 MA_DATA36 DDR_A_D37
    AD10 VTT4 VTT8 AA10 AA25 MB_DATA37 MA_DATA37 W21
    R4 39.2_0402_1% A10 DDR_B_D38 AD26 Y22 DDR_A_D38
    MEM_P VTT9 DDR_B_D39 MB_DATA38 MA_DATA38 DDR_A_D39
    1 2 AF10 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
    +1.8V 1 2 MEM_N AE10 Y10 VTT_SENSE DDR_B_D40 AC22 Y20 DDR_A_D40
    MEMZN VTT_SENSE PAD T1 MB_DATA40 MA_DATA40
    R3 39.2_0402_1% DDR_B_D41 AD22 AA20 DDR_A_D41
    +MCH_REF DDR_B_D42 MB_DATA41 MA_DATA41 DDR_A_D42
    T2 PAD H16 RSVD_M1 MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18
    DDR_B_D43 AF20 AB18 DDR_A_D43
    DDR_A_ODT0 DDR_B_D44 MB_DATA43 MA_DATA43 DDR_A_D44
    <9> DDR_A_ODT0 T19 MA0_ODT0 RSVD_M2 B18 PAD T3 AF24 MB_DATA44 MA_DATA44 AB21
    DDR_A_ODT1 V22 DDR_B_D45 AF23 AD21 DDR_A_D45
    <9> DDR_A_ODT1 MA0_ODT1 MB_DATA45 MA_DATA45
    U21 W26 DDR_B_ODT0 DDR_B_D46 AC20 AD19 DDR_A_D46
    MA1_ODT0 MB0_ODT0 DDR_B_ODT0 <8> MB_DATA46 MA_DATA46
    V19 W23 DDR_B_ODT1 DDR_B_D47 AD20 Y18 DDR_A_D47
    MA1_ODT1 MB0_ODT1 DDR_B_ODT1 <8> MB_DATA47 MA_DATA47
    Y26 DDR_B_D48 AD18 AD17 DDR_A_D48
    DDR_CS0_DIMMA# MB1_ODT0 DDR_B_D49 MB_DATA48 MA_DATA48 DDR_A_D49
    <9> DDR_CS0_DIMMA# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
    DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D50 AC14 W14 DDR_A_D50
    <9> DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# <8> MB_DATA50 MA_DATA50
    U20 W25 DDR_CS1_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
    MA1_CS_L0 MB0_CS_L1 DDR_CS1_DIMMB# <8> MB_DATA51 MA_DATA51
    V20 U22 DDR_B_D52 AF19 Y17 DDR_A_D52
    MA1_CS_L1 MB1_CS_L0 DDR_B_D53 MB_DATA52 MA_DATA52 DDR_A_D53
    AC18 MB_DATA53 MA_DATA53 AB17
    DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB DDR_B_D54 AF16 AB15 DDR_A_D54
    <9> DDR_CKE0_DIMMA MA_CKE0 MB_CKE0 DDR_CKE0_DIMMB <8> MB_DATA54 MA_DATA54
    DDR_CKE1_DIMMA J20 H26 DDR_CKE1_DIMMB DDR_B_D55 AF15 AD15 DDR_A_D55
    <9> DDR_CKE1_DIMMA MA_CKE1 MB_CKE1 DDR_CKE1_DIMMB <8> MB_DATA55 MA_DATA55
    DDR_B_D56 AF13 AB13 DDR_A_D56
    DDR_B_D57 MB_DATA56 MA_DATA56 DDR_A_D57
    N19 MA_CLK_H0 MB_CLK_H0 P22 AC12 MB_DATA57 MA_DATA57 AD13
    N20 R22 DDR_B_D58 AB11 Y12 DDR_A_D58
    DDR_A_CLK0 MA_CLK_L0 MB_CLK_L0 DDR_B_CLK0 DDR_B_D59 MB_DATA58 MA_DATA58 DDR_A_D59
    <9> DDR_A_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDR_B_CLK0 <8> Y11 MB_DATA59 MA_DATA59 W11
    DDR_A_CLK#0 F16 A18 DDR_B_CLK#0 DDR_B_D60 AE14 AB14 DDR_A_D60
    <9> DDR_A_CLK#0 MA_CLK_L1 MB_CLK_L1 DDR_B_CLK#0 <8> MB_DATA60 MA_DATA60
    DDR_A_CLK1 Y16 AF18 DDR_B_CLK1 DDR_B_D61 AF14 AA14 DDR_A_D61
    <9> DDR_A_CLK1 MA_CLK_H2 MB_CLK_H2 DDR_B_CLK1 <8> MB_DATA61 MA_DATA61
    DDR_A_CLK#1 AA16 AF17 DDR_B_CLK#1 DDR_B_D62 AF11 AB12 DDR_A_D62
    <9> DDR_A_CLK#1 MA_CLK_L2 MB_CLK_L2 DDR_B_CLK#1 <8> MB_DATA62 MA_DATA62
    P19 R26 DDR_B_D63 AD11 AA12 DDR_A_D63
    MA_CLK_H3 MB_CLK_H3 MB_DATA63 MA_DATA63
    P20 MA_CLK_L3 MB_CLK_L3 R25 <8> DDR_B_DM[7..0] DDR_A_DM[7..0] <9>
    3 DDR_B_DM0 DDR_A_DM0 3
    <9> DDR_A_MA[15..0] DDR_B_MA[15..0] <8> A12 MB_DM0 MA_DM0 E12
    DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM1 B16 C15 DDR_A_DM1
    DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM2 MB_DM1 MA_DM1 DDR_A_DM2
    M20 MA_ADD1 MB_ADD1 N24 A22 MB_DM2 MA_DM2 E19
    DDR_A_MA2 N22 P26 DDR_B_MA2 DDR_B_DM3 E25 F24 DDR_A_DM3
    DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM4 MB_DM3 MA_DM3 DDR_A_DM4
    M19 MA_ADD3 MB_ADD3 N23 AB26 MB_DM4 MA_DM4 AC24
    DDR_A_MA4 M22 N26 DDR_B_MA4 DDR_B_DM5 AE22 Y19 DDR_A_DM5
    DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM6 MB_DM5 MA_DM5 DDR_A_DM6
    L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
    DDR_A_MA6 M24 N25 DDR_B_MA6 DDR_B_DM7 AD12 Y13 DDR_A_DM7
    DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 MB_DM7 MA_DM7
    L21 MA_ADD7 MB_ADD7 L24
    DDR_A_MA8 L19 M26 DDR_B_MA8 DDR_B_DQS0 C12 G13 DDR_A_DQS0
    MA_ADD8 MB_ADD8 <8> DDR_B_DQS0 MB_DQS_H0 MA_DQS_H0 DDR_A_DQS0 <9>
    DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
    MA_ADD9 MB_ADD9 <8> DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 <9>
    DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS1 D16 G16 DDR_A_DQS1
    MA_ADD10 MB_ADD10 <8> DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 <9>
    DDR_A_MA11 L22 L26 DDR_B_MA11 DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
    MA_ADD11 MB_ADD11 <8> DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 <9>
    DDR_A_MA12 K20 L25 DDR_B_MA12 DDR_B_DQS2 A24 C22 DDR_A_DQS2
    MA_ADD12 MB_ADD12 <8> DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 <9>
    DDR_A_MA13 V24 W24 DDR_B_MA13 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
    MA_ADD13 MB_ADD13 <8> DDR_B_DQS#2 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS#2 <9>
    DDR_A_MA14 K24 J23 DDR_B_MA14 DDR_B_DQS3 F26 G22 DDR_A_DQS3
    MA_ADD14 MB_ADD14 <8> DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 <9>
    DDR_A_MA15 K19 J24 DDR_B_MA15 DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
    MA_ADD15 MB_ADD15 <8> DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 <9>
    DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
    <8> DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 <9>
    DDR_A_BS#0 R20 R24 DDR_B_BS#0 DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
    <9> DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 <8> <8> DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 <9>
    DDR_A_BS#1 R23 U26 DDR_B_BS#1 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
    <9> DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 <8> <8> DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 <9>
    DDR_A_BS#2 J21 J26 DDR_B_BS#2 DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
    <9> DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 <8> <8> DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 <9>
    DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
    <8> DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 <9>
    DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
    <9> DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# <8> <8> DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 <9>
    DDR_A_CAS# T22 U24 DDR_B_CAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
    <9> DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# <8> <8> DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 <9>
    DDR_A_WE# T24 U23 DDR_B_WE# DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
    <9> DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# <8> <8> DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 <9>

    @ @ 6090022100G_B

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 5 of 45
    A B C D E
    A B C D E

    +2.5VDDA
    VDDA=300mA
    L1 +1.8V 1 2 CH751H-40PT_SOD323-2
    +2.5VS 1 2 3300P_0402_50V7K R10 10K_0402_5% D12
    1 FBM_L11_201209_300L_0805 1 2 1 2 ENTRIP2 <37,39>
    1 1 1 R5 300_0402_5%
    C16 +

    2
    B
    @ 100U_D2_10VM 4.7U_0805_10V4Z C17 C18 C19 CH751H-40PT_SOD323-2
    0.22U_0603_16V4Z Q3 D16
    2 2 2 2

    E
    CPU_THERMTRIP#_R 3 1 1 2 H_THERMTRIP# <21,33>

    C
    MMBT3904_NL_SOT23-3
    1 JCPUD 1

    F8 VDDA1 KEY1 M11


    F9 VDDA2 KEY2 W18

    1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC


    <15> CLK_CPU_BCLK CLKIN_H SVC CPU_SVC <43>
    C20 CPU_CLKIN_SC_N A8 A4 CPU_SVD
    CLKIN_L SVD CPU_SVD <43>

    1
    LDT_RST# B7
    R8 H_PWRGD RESET_L
    A7 PWROK +1.8V 1 2
    169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R R9 300_0402_5%
    CPU_LDT_REQ# LDTSTOP_L THERMTRIP_L CPU_PROCHOT#_1.8 R11
    C6 AC7

    2
    LDTREQ_L PROCHOT_L CPU_PROCHOT#_1.8
    <15> CLK_CPU_BCLK# 1 2 MEMHOT_L AA8 2 1 +1.8V 1 2 H_PROCHOT# <20>
    C21 3900P_0402_50V7K AF4 R42 300_0402_5% @ 0_0402_5%
    SIC
    Address:100_1100 AF5 SID
    +1.8VS AE6 W7 THERMDC_CPU
    ALERT_L THERMDC THERMDA_CPU
    Place close to CPU wihtin 1.5" THERMDA W8
    R13 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
    2

    R14 1 2 44.2_0402_1% CPU_HTREF1 P6


    R15
    +1.2V_HT HT_REF1 +1.8V sense no support
    300_0402_5% CPU_VDD0_RUN_FB_H F6 W9 +VDDNB
    <43> CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H PAD T22
    <43> CPU_VDD0_RUN_FB_L CPU_VDD0_RUN_FB_L E6 Y9
    +CPU_CORE_0 VDD0_FB_L VDDIO_FB_L PAD T21
    R484 10_0402_5%
    1

    LDT_RST# R487 10_0402_5% <43> CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_H Y6 H6 CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_H 1 2


    <20> LDT_RST# VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H <43>
    1 2CPU_VDD0_RUN_FB_H <43> CPU_VDD1_RUN_FB_L CPU_VDD1_RUN_FB_L AB6
    VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_RUN_FB_L
    CPU_VDDNB_RUN_FB_L <43>
    CPU_VDDNB_RUN_FB_L 1 2
    1 1 2CPU_VDD0_RUN_FB_L R485 10_0402_5%
    C22 R486 10_0402_5% G10
    T9 PAD DBRDY
    0.01U_0402_25V4Z AA9 E10 CPU_DBREQ# Close to CPU
    T10 PAD TMS DBREQ_L
    @ AC9
    2 T11 PAD TCK
    T12 PAD AD9 TRST_L TDO AE9 PAD T20
    Close to CPU T19 PAD AF9 TDI
    2 CPU_TEST28_H_PLLCHRZ_P 2
    AD7 TEST23 TEST28_H J7 PAD T5 route as differential
    +CPU_CORE_1 H8 CPU_TEST28_L_PLLCHRZ_N as short as possible
    +1.8VS TEST28_L PAD T6
    R489 10_0402_5% H10 testpoint under package
    +1.8V TEST18
    1 2CPU_VDD1_RUN_FB_H G9 TEST19 TEST17 D7 CPU_TEST17_BP3
    PAD T7
    1 2CPU_VDD1_RUN_FB_L @ R493 30.1_0402_1%
    TEST16 E7 CPU_TEST16_BP2
    PAD T8
    2

    1 2CPU_TEST25_H_BYPASSCLK_H E9 F7 +1.8V
    R21 R488 10_0402_5% TEST25_H TEST15
    1 2CPU_TEST25_L_BYPASSCLK_L E8 TEST25_L TEST14 C7 0718 AMD --> 1K ohm
    300_0402_5% @ R492 30.1_0402_1%
    CPU_TEST21_SCANEN AB8 C3 CPU_SVC 1 2
    TEST21 TEST7 CPU_SVD R22 1K_0402_5%
    AF7 K8 1 2
    1

    H_PWRGD CPU_TEST24_SCANCLK1 TEST20 TEST10 R23 1K_0402_5%


    <20,43> H_PWRGD AE7 TEST24
    AE8 TEST22 TEST8 C4
    1 AC8 TEST12
    AF8 TEST27
    C23 C9 CPU_TEST29_H_FBCLKOUT_P
    +1.8VS TEST29_H PAD T13
    @ 0.1U_0402_16V4Z 1 R25 2 0_0402_5% C2 C8 CPU_TEST29_L_FBCLKOUT_N CPU_TEST21_SCANEN R26 1 2 300_0402_5%
    2 TEST9 TEST29_L PAD T14
    AA6 TEST6 CPU_TEST24_SCANCLK1 R28 2 1 300_0402_5%
    2

    A3 RSVD1 RSVD10 H18


    R30 A5 H19
    300_0402_5% RSVD2 RSVD9
    B3 RSVD3 RSVD8 AA7
    +1.8VS B5 D5
    RSVD4 RSVD7
    C1 C5
    1

    CPU_LDT_REQ# RSVD5 RSVD6


    CPU_LDT_REQ# <11,20>
    2

    R36 1 @ 6090022100G_B
    300_0402_5%
    C24
    330P_0402_50V7K
    1

    LDT_STOP# 2
    <11,20> LDT_STOP#
    1
    3 C25 3
    0.01U_0402_25V4Z
    @
    2

    +1.8V

    @ 220_0402_5% R37

    @ 220_0402_5% R38

    @ 220_0402_5% R39

    @ 220_0402_5% R40

    300_0402_5% R41
    HDT Connector

    1
    JP3

    @ 1 2

    2
    R494 0_0402_5% 3 4
    CPU_DBREQ#
    5 6
    1 2 7 8
    T23 PAD 9 10
    11 12
    13 14
    15 16
    +3VS 17 18
    T24 PAD 19 20
    21 22 LDT_RST#
    23 24
    26
    0.1U_0402_16V4Z

    1 NOTE: HDT TERMINATION IS REQUIRED


    C26 FOR REV. Ax SILICON ONLY. CONN@ SAMTEC_ASP-68200-07
    2
    4 U2 4
    1 8 SMB_EC_CK2 SMB_EC_CK2 <19,33>
    VDD SCLK
    THERMDA_CPU 2 7 SMB_EC_DA2
    D+ SDATA SMB_EC_DA2 <19,33>
    C27
    1 2 THERMDC_CPU 3 6
    2200P_0402_50V7K D- ALERT#
    4 5
    THERM# GND Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    ADM1032ARM-1 ZREEL_MSOP8
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 6 of 45
    A B C D E
    A B C D E

    JCPUF

    VDD(+CPU_CORE) decoupling. +CPU_CORE_0 JCPUE +CPU_CORE_1


    AA4
    AA11
    VSS1
    VSS2
    VSS66
    VSS67
    J6
    J8
    AA13 VSS3 VSS68 J10
    G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
    H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
    +CPU_CORE_0 +CPU_CORE_1 J9 R4 AA19 J16
    VDD0_3 VDD1_3 VSS6 VSS71
    J11 VDD0_4 VDD1_4 R7 AB2 VSS7 VSS72 J18
    J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
    J15 VDD0_6 VDD1_6 R11 AB9 VSS9 VSS74 K7
    1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
    K10 VDD0_8 VDD1_8 T6 AB25 VSS11 VSS76 K11
    + C30 + C28 + C31 + C29 K12 T8 AC11 K13
    1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M VDD0_9 VDD1_9 VSS12 VSS77 1
    K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
    L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
    2 2 2 2
    L7 VDD0_12 VDD1_12 T14 AC17 VSS15 VSS80 L6
    L9 VDD0_13 VDD1_13 U7 AC19 VSS16 VSS81 L8
    L11 U9 AC21 L10
    Near CPU Socket L13
    VDD0_14
    VDD0_15
    VDD1_14
    VDD1_15 U11 AD6
    VSS17
    VSS18
    VSS82
    VSS83 L12
    L15 VDD0_16 VDD1_16 U13 AD8 VSS19 VSS84 L14
    M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
    M6 VDD0_18 VDD1_18 V6 AE11 VSS21 VSS86 L18
    M8 VDD0_19 VDD1_19 V8 AE13 VSS22 VSS87 M7
    +CPU_CORE_0 M10 V10 AE15 M9
    +CPU_CORE_1 VDD0_20 VDD1_20 VSS23 VSS88
    N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6
    N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
    +VDDNB N11 W4 AE21 N4
    VDD0_23 VDD1_23 VSS26 VSS91
    1 1 1 1 VDD1_24 Y2 AE23 VSS27 VSS92 N8
    C32 C33 C34 C35 1 1 1 1 K16 AC4 B4 N10
    22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C36 C37 C38 C39 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
    M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
    22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18
    2 2 2 2 VDDNB_3 VSS30 VSS95
    T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
    2 2 2 2 +1.8V V16 VDDNB_5 VDDIO26 V25 B11 VSS32 VSS97 P7
    VDDIO25 V23 B13 VSS33 VSS98 P9
    +CPU_CORE_0 H25 V21 B15 P11
    +CPU_CORE_1 VDDIO1 VDDIO24 VSS34 VSS99
    J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
    K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
    K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10
    1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
    C40 C41 C42 C43 C44 C45 K25 T21 B25 R18
    0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
    L17 VDDIO7 VDDIO18 T18 D6 VSS40 VSS105 T7
    M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
    2 2 2 2 2 2
    M21 VDDIO9 VDDIO16 P25 D9 VSS42 VSS107 T11
    M23 P23 D11 T13
    Under CPU Socket M25
    VDDIO10
    VDDIO11
    VDDIO15
    VDDIO14 P21 D13
    VSS43
    VSS44
    VSS108
    VSS109 T15
    2 2
    N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
    D17 VSS46 VSS111 U4
    D19 VSS47 VSS112 U6
    6090022100G_B D21 U8
    Athlon 64 S1 VSS48 VSS113
    D23 U10
    VDDIO decoupling. Processor Socket
    @
    D25
    E4
    VSS49
    VSS50
    VSS51
    VSS114
    VSS115
    VSS116
    U12
    U14
    F2 U16

    +1.8V
    +CPU_CORE_NB decoupling. F11
    F13
    VSS52
    VSS53
    VSS54
    VSS117
    VSS118
    VSS119
    U18
    V2
    F15 VSS55 VSS120 V7
    F17 VSS56 VSS121 V9
    +VDDNB F19 V11
    VSS57 VSS122
    F21 VSS58 VSS123 V13
    1 1 1 1 1 1 F23 VSS59 VSS124 V15
    C46 C47 C48 C49 C50 C51 1 1 1 F25 V17
    22U_0805_6.3V6M 22U_0805_6.3V6M C52 C53 C54 VSS60 VSS125
    H7 VSS61 VSS126 W6
    0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M @ 22U_0805_6.3V6M H9 Y21
    2 2 2 2 2 2 VSS62 VSS127
    H21 VSS63 VSS128 Y23
    2 2 2
    H23 VSS64 VSS129 N6
    J4 VSS65
    6090022100G_B
    Under CPU Socket Athlon 64 S1
    Processor Socket
    @

    Between CPU Socket and DIMM


    +1.8V +0.9V
    3 3
    Near Power Supply
    1
    C55
    1
    C56
    1
    C57
    1
    C58
    VTT decoupling. 1
    C: Change to NBO CAP
    + C59
    0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 220U_Y_4VM
    2 2 2 2 2

    180PF Qt'y follow the distance between


    +1.8V +1.8V CPU socket and DIMM0. <2.5inch> +0.9V

    1 1 1 1 1 1
    C60 C61 C62 C63 C64 C65 1 1 1 1 1 1 1 1
    0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C66 C67 C68 C69 C70 C71 C72 C73
    4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
    2 2 2 2 2 2
    A: Add C165 and C176 2 2 2 2 2 2 2 2
    to follow AMD Layout
    +1.8V
    review recommand for
    EMI Near CPU Socket Right side.
    +0.9V
    1
    1 1 1 1 C: Change to NBO CAP
    + C78
    C74 C75 C76 C77 220U_Y_4VM 1 1 1 1 1 1 1 1
    4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C79 C80 C81 C82 C83 C84 C85 C86
    2 2 2 2 2 @ 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
    2 2 2 2 2 2 2 2
    4 4

    Near CPU Socket Left side.

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 7 of 45
    A B C D E
    A B C D E

    +1.8V
    JDDRH +1.8V +0.9V +1.8V
    1 2 DDR_B_D[0..63] RP8
    <9> +V_DDR_MCH_REF VREF VSS DDR_B_D[0..63] <5>
    3 4 DDR_B_D4 DDR_B_MA4 1 8 2 1
    DDR_B_D0 VSS DQ4 DDR_B_D5 DDR_B_DM[0..7] DDR_B_MA2 C105 0.1U_0402_16V4Z
    5 DQ0 DQ5 6 DDR_B_DM[0..7] <5> 2 7
    DDR_B_D1 7 8 DDR_B_MA0 3 6 1 2
    DQ1 VSS

    1000P_0402_25V8J
    1 9 10 DDR_B_DM0 DDR_B_DQS[0..7] DDR_B_RAS# 4 5 C106 0.1U_0402_16V4Z
    DDR_B_DQS#0 VSS DM0 DDR_B_DQS[0..7] <5>
    11 DQS0# VSS 12

    C104
    DDR_B_DQS0 13 14 DDR_B_D6 DDR_B_MA[0..15] 47_0804_8P4R_5%
    DQS0 DQ6 DDR_B_MA[0..15] <5>
    15 16 DDR_B_D7
    2 DDR_B_D2 VSS DQ7 DDR_B_DQS#[0..7] RP9
    17 DQ2 VSS 18 DDR_B_DQS#[0..7] <5>
    DDR_B_D3 19 20 DDR_B_D12 DDR_B_MA14 1 8 2 1
    1 DQ3 DQ12 DDR_B_D13 DDR_B_MA11 C108 0.1U_0402_16V4Z 1
    21 VSS DQ13 22 2 7
    DDR_B_D8 23 24 DDR_B_MA7 3 6 1 2
    DDR_B_D9 DQ8 VSS DDR_B_DM1 DDR_B_MA6 C107 0.1U_0402_16V4Z
    25 DQ9 DM1 26 4 5
    27 VSS VSS 28
    DDR_B_DQS#1 29 30 47_0804_8P4R_5%
    DQS1# CK0 DDR_B_CLK0 <5>
    DDR_B_DQS1 31 32
    DQS1 CK0# DDR_B_CLK#0 <5>
    33 34 RP10
    DDR_B_D10 VSS VSS DDR_B_D14 DDR_CKE0_DIMMB
    35 DQ10 DQ14 36 8 1 2 1
    DDR_B_D11 37 38 DDR_B_D15 DDR_B_BS#2 7 2 C109 0.1U_0402_16V4Z
    DQ11 DQ15 DDR_B_MA15
    39 VSS VSS 40 6 3 1 2
    DDR_CKE1_DIMMB 5 4 C110 0.1U_0402_16V4Z

    41 42 47_0804_8P4R_5%
    DDR_B_D16 VSS VSS DDR_B_D20
    43 DQ16 DQ20 44
    DDR_B_D17 45 46 DDR_B_D21 RP11
    DQ17 DQ21 DDR_B_MA3
    47 VSS VSS 48 8 1 2 1
    DDR_B_DQS#2 49 50 DDR_B_MA8 7 2 C111 0.1U_0402_16V4Z
    DDR_B_DQS2 DQS2# NC DDR_B_DM2 DDR_B_MA12
    51 DQS2 DM2 52 6 3 1 2
    53 54 DDR_B_MA9 5 4 C112 0.1U_0402_16V4Z
    DDR_B_D18 VSS VSS DDR_B_D22
    55 DQ18 DQ22 56
    DDR_B_D19 57 58 DDR_B_D23 47_0804_8P4R_5%
    DQ19 DQ23
    59 VSS VSS 60
    DDR_B_D24 61 62 DDR_B_D28 RP12
    DDR_B_D25 DQ24 DQ28 DDR_B_D29 DDR_B_BS#0
    63 DQ25 DQ29 64 8 1 2 1
    65 66 DDR_B_MA10 7 2 C114 0.1U_0402_16V4Z
    DDR_B_DM3 VSS VSS DDR_B_DQS#3 DDR_B_MA1
    67 DM3 DQS3# 68 6 3 1 2
    69 70 DDR_B_DQS3 DDR_B_MA5 5 4 C113 0.1U_0402_16V4Z
    NC DQS3
    71 VSS VSS 72
    DDR_B_D26 73 74 DDR_B_D30 47_0804_8P4R_5%
    DDR_B_D27 DQ26 DQ30 DDR_B_D31
    75 DQ27 DQ31 76
    77 78 RP13
    DDR_CKE0_DIMMB VSS VSS DDR_CKE1_DIMMB DDR_CS1_DIMMB#
    <5> DDR_CKE0_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMB <5> 8 1 2 1
    2 DDR_B_ODT1 C116 0.1U_0402_16V4Z 2
    81 VDD VDD 82 7 2
    83 84 DDR_B_MA15 DDR_B_CAS# 6 3 1 2
    DDR_B_BS#2 NC NC/A15 DDR_B_MA14 DDR_B_WE# C115 0.1U_0402_16V4Z
    <5> DDR_B_BS#2 85 BA2 NC/A14 86 5 4
    87 VDD VDD 88
    DDR_B_MA12 89 90 DDR_B_MA11 47_0804_8P4R_5%
    DDR_B_MA9 A12 A11 DDR_B_MA7
    91 A9 A7 92
    DDR_B_MA8 93 94 DDR_B_MA6 RP14
    A8 A6 DDR_B_BS#1
    95 VDD VDD 96 1 8 2 1
    DDR_B_MA5 97 98 DDR_B_MA4 DDR_CS0_DIMMB# 2 7 C118 0.1U_0402_16V4Z
    DDR_B_MA3 A5 A4 DDR_B_MA2 DDR_B_MA13
    99 A3 A2 100 3 6 1 2
    DDR_B_MA1 101 102 DDR_B_MA0 DDR_B_ODT0 4 5 C117 0.1U_0402_16V4Z
    A1 A0
    103 VDD VDD 104
    DDR_B_MA10 105 106 DDR_B_BS#1 47_0804_8P4R_5%
    A10/AP BA1 DDR_B_BS#1 <5>
    DDR_B_BS#0 107 108 DDR_B_RAS#
    <5> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <5>
    DDR_B_WE# 109 110 DDR_CS0_DIMMB#
    <5> DDR_B_WE# WE# S0# DDR_CS0_DIMMB# <5>
    111 VDD VDD 112
    DDR_B_CAS# 113 114 DDR_B_ODT0
    <5> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <5>
    DDR_CS1_DIMMB# 115 116 DDR_B_MA13
    <5> DDR_CS1_DIMMB# NC/S1# NC/A13
    117 VDD VDD 118
    DDR_B_ODT1 119 120
    <5> DDR_B_ODT1 NC/ODT1 NC
    121 VSS VSS 122
    DDR_B_D32 123 124 DDR_B_D36
    DDR_B_D33 DQ32 DQ36 DDR_B_D37
    125 DQ33 DQ37 126
    127 VSS VSS 128
    DDR_B_DQS#4 129 130 DDR_B_DM4
    DDR_B_DQS4 DQS4# DM4
    131 DQS4 VSS 132
    133 134 DDR_B_D38
    DDR_B_D34 VSS DQ38 DDR_B_D39
    135 DQ34 DQ39 136
    DDR_B_D35 137 138
    DQ35 VSS DDR_B_D44
    139 VSS DQ44 140
    DDR_B_D40 141 142 DDR_B_D45
    DDR_B_D41 DQ40 DQ45
    143 DQ41 VSS 144
    3 DDR_B_DQS#5 3
    145 VSS DQS5# 146
    DDR_B_DM5 147 148 DDR_B_DQS5
    DM5 DQS5
    149 VSS VSS 150
    DDR_B_D42 151 152 DDR_B_D46
    DDR_B_D43 DQ42 DQ46 DDR_B_D47
    153 DQ43 DQ47 154
    155 VSS VSS 156
    DDR_B_D48 157 158 DDR_B_D52
    DDR_B_D49 DQ48 DQ52 DDR_B_D53
    159 DQ49 DQ53 160
    161 VSS VSS 162
    163 NC,TEST CK1 164 DDR_B_CLK1 <5>
    165 VSS CK1# 166 DDR_B_CLK#1 <5>
    DDR_B_DQS#6 167 168
    DDR_B_DQS6 DQS6# VSS DDR_B_DM6
    169 DQS6 DM6 170
    171 VSS VSS 172
    DDR_B_D50 173 174 DDR_B_D54
    DDR_B_D51 DQ50 DQ54 DDR_B_D55
    175 DQ51 DQ55 176
    177 VSS VSS 178
    DDR_B_D56 179 180 DDR_B_D60
    DDR_B_D57 DQ56 DQ60 DDR_B_D61
    181 DQ57 DQ61 182
    183 VSS VSS 184
    DDR_B_DM7 185 186 DDR_B_DQS#7
    DM7 DQS7# DDR_B_DQS7
    187 VSS DQS7 188
    DDR_B_D58 189 190
    DDR_B_D59 DQ58 VSS DDR_B_D62
    191 DQ59 DQ62 192
    193 194 DDR_B_D63
    VSS DQ63
    <9,15,21,27> SMB_CK_DAT0 195 SDA VSS 196
    <9,15,21,27> SMB_CK_CLK0 197 SCL SAO 198 +3VS
    +3VS 199 VDDSPD SA1 200
    1
    C119 P-TWO_A5692B-A0G16-P
    0.1U_0402_16V4Z @
    4 2 4

    DIMM0 STD H:9.2mm (Bot)


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 8 of 45
    A B C D E
    A B C D E

    +V_DDR_MCH_REF

    +1.8V JDDRL +1.8V


    1 VREF VSS 2
    3 4 DDR_A_D4 DDR_A_D[0..63]
    DDR_A_D0 VSS DQ4 DDR_A_D5 DDR_A_D[0..63] <5> +0.9V +1.8V
    5 DQ0 DQ5 6
    DDR_A_D1 7 8 DDR_A_DM[0..7] RP1
    DQ1 VSS DDR_A_DM[0..7] <5>
    9 10 DDR_A_DM0 DDR_A_MA6 1 8 1 2
    DDR_A_DQS#0 VSS DM0 DDR_A_DQS[0..7] DDR_A_MA14 C87 0.1U_0402_16V4Z
    11 DQS0# VSS 12 DDR_A_DQS[0..7] <5> 2 7
    1 DDR_A_DQS0 DDR_A_D6 DDR_A_MA7 1
    13 DQS0 DQ6 14 3 6 1 2
    15 16 DDR_A_D7 DDR_A_MA[0..15] DDR_A_MA11 4 5 C88 0.1U_0402_16V4Z
    VSS DQ7 DDR_A_MA[0..15] <5>
    DDR_A_D2 17 18
    DDR_A_D3 DQ2 VSS DDR_A_D12 DDR_A_DQS#[0..7] 47_0804_8P4R_5%
    19 DQ3 DQ12 20 DDR_A_DQS#[0..7] <5>
    21 22 DDR_A_D13 RP2
    DDR_A_D8 VSS DQ13 DDR_CKE0_DIMMA
    23 DQ8 VSS 24 8 1 1 2
    DDR_A_D9 25 26 DDR_A_DM1 DDR_A_BS#2 7 2 C90 0.1U_0402_16V4Z
    DQ9 DM1 DDR_CKE1_DIMMA
    27 VSS VSS 28 6 3 1 2
    DDR_A_DQS#1 29 30 DDR_A_MA15 5 4 C89 0.1U_0402_16V4Z
    DQS1# CK0 DDR_A_CLK0 <5>
    DDR_A_DQS1 31 32
    DQS1 CK0# DDR_A_CLK#0 <5>
    33 34 47_0804_8P4R_5%
    DDR_A_D10 VSS VSS DDR_A_D14 RP3
    35 DQ10 DQ14 36
    DDR_A_D11 37 38 DDR_A_D15 +1.8V DDR_A_BS#1 1 8 1 2
    DQ11 DQ15 DDR_A_MA2 C91 0.1U_0402_16V4Z
    39 VSS VSS 40 2 7
    DDR_A_MA0 3 6 1 2

    2
    DDR_A_MA4 4 5 C92 0.1U_0402_16V4Z
    41 42 R43
    DDR_A_D16 VSS VSS DDR_A_D20 1K_0402_1% 47_0804_8P4R_5%
    43 DQ16 DQ20 44
    DDR_A_D17 45 46 DDR_A_D21 RP4
    DQ17 DQ21 DDR_A_MA5
    47 48 8 1 1 2

    1
    DDR_A_DQS#2 VSS VSS +V_DDR_MCH_REF DDR_A_MA8 C93 0.1U_0402_16V4Z
    49 DQS2# NC 50 +V_DDR_MCH_REF <8> 7 2

    0.1U_0402_16V4Z
    DDR_A_DQS2 51 52 DDR_A_DM2 DDR_A_MA9 6 3 1 2
    DQS2 DM2

    1000P_0402_25V8J
    53 54 1 1 DDR_A_MA12 5 4 C94 0.1U_0402_16V4Z
    VSS VSS

    2
    C96
    DDR_A_D18 55 56 DDR_A_D22
    DQ18 DQ22

    C95
    DDR_A_D19 57 58 DDR_A_D23 R44 47_0804_8P4R_5%
    DQ19 DQ23 1K_0402_1% RP5
    59 VSS VSS 60
    DDR_A_D24 DDR_A_D28 2 2 DDR_A_BS#0
    61 DQ24 DQ28 62 8 1 1 2
    DDR_A_D25 63 64 DDR_A_D29 DDR_A_MA10 7 2 C98 0.1U_0402_16V4Z

    1
    DQ25 DQ29 DDR_A_MA3
    65 VSS VSS 66 6 3 1 2
    DDR_A_DM3 67 68 DDR_A_DQS#3 DDR_A_MA1 5 4 C97 0.1U_0402_16V4Z
    DM3 DQS3# DDR_A_DQS3
    69 NC DQS3 70
    71 72 47_0804_8P4R_5%
    2 DDR_A_D26 VSS VSS DDR_A_D30 RP6 2
    73 DQ26 DQ30 74
    DDR_A_D27 75 76 DDR_A_D31 DDR_A_ODT1 8 1 1 2
    DQ27 DQ31 DDR_CS1_DIMMA# C100 0.1U_0402_16V4Z
    77 VSS VSS 78 7 2
    DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA DDR_A_CAS# 6 3 1 2
    <5> DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA <5>
    81 82 DDR_A_WE# 5 4 C99 0.1U_0402_16V4Z
    VDD VDD DDR_A_MA15
    83 NC NC/A15 84
    DDR_A_BS#2 85 86 DDR_A_MA14 47_0804_8P4R_5%
    <5> DDR_A_BS#2 BA2 NC/A14
    87 88 RP7
    DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_MA13
    89 A12 A11 90 1 8 1 2
    DDR_A_MA9 91 92 DDR_A_MA7 DDR_A_ODT0 2 7 C102 0.1U_0402_16V4Z
    DDR_A_MA8 A9 A7 DDR_A_MA6 DDR_A_RAS#
    93 A8 A6 94 3 6 1 2
    95 96 DDR_CS0_DIMMA# 4 5 C101 0.1U_0402_16V4Z
    DDR_A_MA5 VDD VDD DDR_A_MA4
    97 A5 A4 98
    DDR_A_MA3 99 100 DDR_A_MA2 47_0804_8P4R_5%
    DDR_A_MA1 A3 A2 DDR_A_MA0
    101 A1 A0 102
    103 VDD VDD 104
    DDR_A_MA10 105 106 DDR_A_BS#1
    A10/AP BA1 DDR_A_BS#1 <5>
    DDR_A_BS#0 107 108 DDR_A_RAS#
    <5> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <5>
    DDR_A_WE# 109 110 DDR_CS0_DIMMA#
    <5> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <5>
    111 VDD VDD 112
    DDR_A_CAS# 113 114 DDR_A_ODT0
    <5> DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 <5>
    DDR_CS1_DIMMA# 115 116 DDR_A_MA13
    <5> DDR_CS1_DIMMA# NC/S1# NC/A13
    117 VDD VDD 118
    DDR_A_ODT1 119 120
    <5> DDR_A_ODT1 NC/ODT1 NC
    121 VSS VSS 122
    DDR_A_D32 123 124 DDR_A_D36
    DDR_A_D33 DQ32 DQ36 DDR_A_D37
    125 DQ33 DQ37 126
    127 VSS VSS 128
    DDR_A_DQS#4 129 130 DDR_A_DM4
    DDR_A_DQS4 DQS4# DM4
    131 DQS4 VSS 132
    133 134 DDR_A_D38
    DDR_A_D34 VSS DQ38 DDR_A_D39
    135 DQ34 DQ39 136
    3 DDR_A_D35 3
    137 DQ35 VSS 138
    139 140 DDR_A_D44
    DDR_A_D40 VSS DQ44 DDR_A_D45
    141 DQ40 DQ45 142
    DDR_A_D41 143 144
    DQ41 VSS DDR_A_DQS#5
    145 VSS DQS5# 146
    DDR_A_DM5 147 148 DDR_A_DQS5
    DM5 DQS5
    149 VSS VSS 150
    DDR_A_D42 151 152 DDR_A_D46
    DDR_A_D43 DQ42 DQ46 DDR_A_D47
    153 DQ43 DQ47 154
    155 VSS VSS 156
    DDR_A_D48 157 158 DDR_A_D52
    DDR_A_D49 DQ48 DQ52 DDR_A_D53
    159 DQ49 DQ53 160
    161 VSS VSS 162
    163 NC,TEST CK1 164 DDR_A_CLK1 <5>
    165 VSS CK1# 166 DDR_A_CLK#1 <5>
    DDR_A_DQS#6 167 168
    DDR_A_DQS6 DQS6# VSS DDR_A_DM6
    169 DQS6 DM6 170
    171 VSS VSS 172
    DDR_A_D50 173 174 DDR_A_D54
    DDR_A_D51 DQ50 DQ54 DDR_A_D55
    175 DQ51 DQ55 176
    177 VSS VSS 178
    DDR_A_D56 179 180 DDR_A_D60
    DDR_A_D57 DQ56 DQ60 DDR_A_D61
    181 DQ57 DQ61 182
    183 VSS VSS 184
    DDR_A_DM7 185 186 DDR_A_DQS#7
    DM7 DQS7# DDR_A_DQS7
    187 VSS DQS7 188
    DDR_A_D58 189 190
    DDR_A_D59 DQ58 VSS DDR_A_D62
    191 DQ59 DQ62 192
    193 194 DDR_A_D63
    VSS DQ63
    <8,15,21,27> SMB_CK_DAT0 195 SDA VSS 196
    <8,15,21,27> SMB_CK_CLK0 197 SCL SAO 198
    +3VS 199 VDDSPD SA1 200
    4 4
    1
    C103 PTI_A5652D-A0G16-P
    0.1U_0402_16V4Z @
    2

    DIMM0 STD H:5.2mm (Bot) Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 9 of 45
    A B C D E
    A B C D E

    PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15]
    <19> PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] <19>
    PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15]
    <19> PCIE_GTX_C_MRX_N[0..15] GM:RS780M,PM:RX781 PCIE_MTX_C_GRX_N[0..15] <19>

    U3B
    PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C120 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
    PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C121 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
    PCIE_GTX_C_MRX_N1
    C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5
    PCIE_MTX_GRX_P1 C122 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
    A3 GFX_RX1P GFX_TX1P A4 2
    PCIE_GTX_C_MRX_P1 B3 B4 PCIE_MTX_GRX_N1 C123 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
    1 PCIE_GTX_C_MRX_P2 GFX_RX1N GFX_TX1N PCIE_MTX_GRX_P2 C124 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 1
    C2 GFX_RX2P GFX_TX2P C3 2
    PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C125 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
    PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3 C126 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
    E5 D1 2
    PCIE_GTX_C_MRX_N3 F5
    GFX_RX3P GFX_TX3P
    D2 PCIE_MTX_GRX_N3 C127 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3 Polarity inversion
    PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4 C128 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
    G5 GFX_RX4P GFX_TX4P E2 2
    PCIE_GTX_C_MRX_N4 G6 E1 PCIE_MTX_GRX_N4 C129 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
    PCIE_GTX_C_MRX_P5 GFX_RX4N GFX_TX4N PCIE_MTX_GRX_P5 C130 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
    H5 GFX_RX5P GFX_TX5P F4 2
    PCIE_GTX_C_MRX_N5 H6 F3 PCIE_MTX_GRX_N5 C131 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
    PCIE_GTX_C_MRX_N6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 C132 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
    J6 GFX_RX6P GFX_TX6P F1 2
    PCIE_GTX_C_MRX_P6 J5 F2 PCIE_MTX_GRX_N6 C133 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
    PCIE_GTX_C_MRX_P7 J7
    GFX_RX6N GFX_TX6N
    H4 PCIE_MTX_GRX_P7 C134 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7 Polarity inversion
    PCIE_GTX_C_MRX_N7 GFX_RX7P GFX_TX7P PCIE_MTX_GRX_N7 C135 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
    J8 GFX_RX7N GFX_TX7N H3
    PCIE_GTX_C_MRX_P8 L5 H1 PCIE_MTX_GRX_P8 C136 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
    PCIE_GTX_C_MRX_N8 GFX_RX8P GFX_TX8P PCIE_MTX_GRX_N8 C137 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
    L6 GFX_RX8N GFX_TX8N H2
    PCIE_GTX_C_MRX_P9 M8 J2 PCIE_MTX_GRX_P9 C138 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
    PCIE_GTX_C_MRX_N9 GFX_RX9P GFX_TX9P PCIE_MTX_GRX_N9 C139 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
    L8 GFX_RX9N GFX_TX9N J1

    PCIE I/F GFX


    PCIE_GTX_C_MRX_P10 P7 K4 PCIE_MTX_GRX_P10 C140 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
    PCIE_GTX_C_MRX_N10 GFX_RX10P GFX_TX10P PCIE_MTX_GRX_N10 C141 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
    M7 GFX_RX10N GFX_TX10N K3
    PCIE_GTX_C_MRX_P11 P5 K1 PCIE_MTX_GRX_P11 C142 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
    PCIE_GTX_C_MRX_N11 GFX_RX11P GFX_TX11P PCIE_MTX_GRX_N11 C143 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
    M5 GFX_RX11N GFX_TX11N K2
    PCIE_GTX_C_MRX_P12 R8 M4 PCIE_MTX_GRX_P12 C144 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
    PCIE_GTX_C_MRX_N12 P8
    GFX_RX12P GFX_TX12P
    M3 PCIE_MTX_GRX_N12 C145 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 Polarity inversion
    PCIE_GTX_C_MRX_P13 GFX_RX12N GFX_TX12N PCIE_MTX_GRX_P13 C146 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
    R6 GFX_RX13P GFX_TX13P M1 2
    PCIE_GTX_C_MRX_N13 R5 M2 PCIE_MTX_GRX_N13 C147 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
    PCIE_GTX_C_MRX_P14 GFX_RX13N GFX_TX13N PCIE_MTX_GRX_P14 C148 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
    P4 GFX_RX14P GFX_TX14P N2 2
    PCIE_GTX_C_MRX_N14 P3 N1 PCIE_MTX_GRX_N14 C149 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
    PCIE_GTX_C_MRX_P15 GFX_RX14N GFX_TX14N PCIE_MTX_GRX_P15 C150 1PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
    T4 GFX_RX15P GFX_TX15P P1 2
    PCIE_GTX_C_MRX_N15 T3 P2 PCIE_MTX_GRX_N15 C151 1PM@ 2 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
    GFX_RX15N GFX_TX15N
    AE3 AC1 PCIE_ITX_PRX_P0 C152 1 2 0.1U_0402_16V7K
    <27> PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_C_PRX_P0 <27>
    AD4 AC2 PCIE_ITX_PRX_N0 C153 1 2 0.1U_0402_16V7K New Card
    <27> PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 <27>
    AE2 AB4 PCIE_ITX_PRX_P1 C154 1 2 0.1U_0402_16V7K
    2 <28> PCIE_PTX_C_IRX_P1 GPP_RX1P GPP_TX1P PCIE_ITX_C_PRX_P1 <28> 2
    AD3 AB3 PCIE_ITX_PRX_N1 C155 1 2 0.1U_0402_16V7K Card Reader
    <28> PCIE_PTX_C_IRX_N1 GPP_RX1N GPP_TX1N PCIE_ITX_C_PRX_N1 <28>
    AD1 AA2 PCIE_ITX_PRX_P2WLAN@ C156 1 2 0.1U_0402_16V7K
    <27> PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 <27>
    AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2WLAN@ C157 1 2 0.1U_0402_16V7K WLAN
    <27> PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 <27>
    V5 Y1 PCIE_ITX_PRX_P3 C158 1 2 0.1U_0402_16V7K
    <26> PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 <26>
    W6 Y2 PCIE_ITX_PRX_N3 C159 1 2 0.1U_0402_16V7K LAN
    <26> PCIE_PTX_C_IRX_N3 GPP_RX3N GPP_TX3N PCIE_ITX_C_PRX_N3 <26>
    U5 GPP_RX4P GPP_TX4P Y4
    U6 Y3 H_CADOP[0..15] H_CADIP[0..15]
    GPP_RX4N GPP_TX4N <4> H_CADOP[0..15] H_CADIP[0..15] <4>
    U8 V1 PCIE_ITX_PRX_P5 C160 1 2 0.1U_0402_16V7K
    <27> PCIE_PTX_C_IRX_P5 GPP_RX5P GPP_TX5P PCIE_ITX_C_PRX_P5 <27> H_CADON[0..15] H_CADIN[0..15]
    U7 V2 PCIE_ITX_PRX_N5 C161 1 2 0.1U_0402_16V7K Reserve
    <27> PCIE_PTX_C_IRX_N5 GPP_RX5N GPP_TX5N PCIE_ITX_C_PRX_N5 <27> <4> H_CADON[0..15] H_CADIN[0..15] <4>

    <20> SB_RX0P AA8 AD7 SB_TX0P_C C162 1 2 0.1U_0402_16V7K


    SB_RX0P SB_TX0P SB_TX0P <20>
    <20> SB_RX0N Y8 AE7 SB_TX0N_C C163 1 2 0.1U_0402_16V7K
    SB_RX0N SB_TX0N SB_TX0N <20>
    <20> SB_RX1P AA7 AE6 SB_TX1P_C C164 1 2 0.1U_0402_16V7K
    SB_RX1P SB_TX1P SB_TX1P <20>
    <20> SB_RX1N Y7 AD6 SB_TX1N_C C165 1 2 0.1U_0402_16V7K U3A
    SB_RX1N SB_TX1N SB_TX1N <20>
    <20> SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C166 1 2 0.1U_0402_16V7K H_CADOP0 Y25 D24 H_CADIP0
    SB_RX2P SB_TX2P SB_TX2P <20> HT_RXCAD0P HT_TXCAD0P
    <20> SB_RX2N AA6 AC6 SB_TX2N_C C168 1 2 0.1U_0402_16V7K H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
    SB_RX2N SB_TX2N SB_TX2N <20> HT_RXCAD0N HT_TXCAD0N
    <20> SB_RX3P W5 AD5 SB_TX3P_C C169 1 2 0.1U_0402_16V7K H_CADOP1 V22 E24 H_CADIP1
    SB_RX3P SB_TX3P SB_TX3P <20> HT_RXCAD1P HT_TXCAD1P
    <20> SB_RX3N Y5 AE5 SB_TX3N_C C167 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H_CADIN1
    SB_RX3N SB_TX3N SB_TX3N <20> HT_RXCAD1N HT_TXCAD1N
    H_CADOP2 V25 F24 H_CADIP2
    R55 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
    PCE_CALRP(PCE_BCALRP) AC8 1 2 V24 HT_RXCAD2N HT_TXCAD2N F25
    AB8 R56 1 2 2K_0402_1% +1.1VS H_CADOP3 U24 F23 H_CADIP3
    PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
    U25 HT_RXCAD3N HT_TXCAD3N F22
    RS780M_FCBGA528 H_CADOP4 T25 H23 H_CADIP4
    H_CADON4 HT_RXCAD4P HT_TXCAD4P H_CADIN4
    T24 HT_RXCAD4N HT_TXCAD4N H22

    HYPER TRANSPORT CPU I/F


    RS780M Display Port Support (muxed on GFX) H_CADOP5 P22 J25 H_CADIP5
    RS780MR3@ H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
    P23 HT_RXCAD5N HT_TXCAD5N J24
    H_CADOP6 P25 K24 H_CADIP6
    GFX_TX0,TX1,TX2 and TX3 H_CADON6 HT_RXCAD6P HT_TXCAD6P H_CADIN6
    P24 HT_RXCAD6N HT_TXCAD6N K25
    DP0 H_CADOP7 N24 K23 H_CADIP7
    AUX0 and HPD0 H_CADON7 HT_RXCAD7P HT_TXCAD7P H_CADIN7
    N25 HT_RXCAD7N HT_TXCAD7N K22

    H_CADOP8 AC24 F21 H_CADIP8


    3 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
    AC25 HT_RXCAD8N HT_TXCAD8N G21
    DP1 H_CADOP9 AB25 G20 H_CADIP9
    AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
    AB24 HT_RXCAD9N HT_TXCAD9N H21
    H_CADOP10 AA24 J20 H_CADIP10
    H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
    AA25 HT_RXCAD10N HT_TXCAD10N J21
    H_CADOP11 Y22 J18 H_CADIP11
    H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
    Y23 HT_RXCAD11N HT_TXCAD11N K17
    H_CADOP12 W21 L19 H_CADIP12
    H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
    W20 HT_RXCAD12N HT_TXCAD12N J19
    H_CADOP13 V21 M19 H_CADIP13
    H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
    V20 HT_RXCAD13N HT_TXCAD13N L18
    H_CADOP14 U20 M21 H_CADIP14
    H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
    U21 HT_RXCAD14N HT_TXCAD14N P21
    H_CADOP15 U19 P18 H_CADIP15
    PCIE_MTX_GRX_P0 R74 1 IHDMI@ 2 0_0402_5% H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
    HDMI_TXD2+ <18,19> U18 HT_RXCAD15N HT_TXCAD15N M18
    PCIE_MTX_GRX_N0 R75 1 IHDMI@ 2 0_0402_5% HDMI_TXD2- <18,19>
    PCIE_MTX_GRX_P1 R76 1 IHDMI@ 2 0_0402_5% HDMI_TXD1+ <18,19> T22 H24
    <4> H_CLKOP0 HT_RXCLK0P HT_TXCLK0P H_CLKIP0 <4>
    PCIE_MTX_GRX_N1 R81 1 IHDMI@ 2 0_0402_5% HDMI_TXD1- <18,19> T23 H25
    <4> H_CLKON0 HT_RXCLK0N HT_TXCLK0N H_CLKIN0 <4>
    <4> H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 <4>
    PCIE_MTX_GRX_P2 R82 1 IHDMI@ 2 0_0402_5% HDMI_TXD0+ <18,19> AA22 L20
    <4> H_CLKON1 HT_RXCLK1N HT_TXCLK1N H_CLKIN1 <4>
    PCIE_MTX_GRX_N2 R83 1 IHDMI@ 2 0_0402_5% HDMI_TXD0- <18,19>
    PCIE_MTX_GRX_P3 R84 1 IHDMI@ 2 0_0402_5% HDMI_CLK0+ <18,19> H_CTLOP0 M22 M24 H_CTLIP0
    <4> H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 <4>
    PCIE_MTX_GRX_N3 R85 1 IHDMI@ 2 0_0402_5% HDMI_CLK0- <18,19> H_CTLON0 M23 M25 H_CTLIN0
    <4> H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 <4>
    H_CTLOP1 R21 P19 H_CTLIP1
    <4> H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 <4>
    H_CTLON1 R20 R18 H_CTLIN1
    <4> H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 <4>
    1 R57 2 301_0402_1% C23 HT_RXCALP HT_TXCALP B24 1 R58 2 301_0402_1%
    A24 HT_RXCALN HT_TXCALN B25

    0718 Place within 1" RS780M_FCBGA528 0718 Place within 1"


    layout 1:2 layout 1:2
    4
    RS780MR3@ 4

    NEED CHECK R57 & R58 WITH AMD


    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 10 of 45
    A B C D E
    A B C D E

    GM@ L3
    L4 RV@ +VDDLTP18 1 2 +1.8VS
    +1.8VS 0_0603_5% BLM18PG121SN1D_0603
    1
    GM@ L4
    +AVDD2 GM@
    0_0603_5% 1 1 C171 PM1@ C171 RV@ C171 L3 RV@
    GM@ GM@ 0_0603_5% 2.2U_0603_6.3V4Z 2 2.2U_0603_6.3V4Z BLM18PG121SN1D_0603
    C172 C198 C198 PM1@ C198 RV@
    C172 RV@ C172 PM1@ 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 0_0402_5% 0.1U_0402_16V4Z
    2.2U_0603_6.3V4Z 0_0603_5% 2 2
    1 1

    1 GM@ 2 UMA_TV_CRMA
    R435 150_0402_1%
    1 GM@ 2 UMA_TV_LUMA L5 RV@
    R436 150_0402_1% BLM18PG121SN1D_0603
    1 GM@ 2 UMA_CRT_R
    L2 RV@ R62 140_0402_1%
    BLM18PG121SN1D_0603 1 GM@ 2 UMA_CRT_G GM@ L5
    R63 150_0402_1% +VDDLT18 1 2 +1.8VS
    +3VS 1 GM@ 2 UMA_CRT_B BLM18PG121SN1D_0603
    1 1
    GM@ L2 R64 150_0402_1%
    1 2 +AVDD1 C173 PM1@ C173 RV@ GM@ GM@
    BLM18PG121SN1D_0603 1 0_0402_5% 0.1U_0402_16V4Z C173 C174 C174 RV@
    0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z
    C170
    2.2U_0603_6.3V4Z C170 PM1@ C170 RV@
    GM@ 2 0_0603_5% 2.2U_0603_6.3V4Z

    L6 RV@ AVDD=100mA U3C


    BLM18PG121SN1D_0603 +AVDD1 F12 A22 UMA_LCD_TXOUT0_A0+ <17>
    +1.8VS AVDD1(NC) TXOUT_L0P(NC)
    E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 UMA_LCD_TXOUT0_A0- <17>
    +AVDD2 F14 A21 UMA_LCD_TXOUT0_A1+ <17>
    GM@ L6 AVDDDI(NC) TXOUT_L1P(NC)
    G15 AVSSDI(NC) TXOUT_L1N(NC) B21 UMA_LCD_TXOUT0_A1- <17>
    1 2 +AVDDQ +AVDDQ H15 B20 UMA_LCD_TXOUT0_A2+ <17>
    2 BLM18PG121SN1D_0603 1 AVDDQ(NC) TXOUT_L2P(NC) 2
    H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 UMA_LCD_TXOUT0_A2- <17>
    GM@ A19
    C175 C175 RV@ C175 PM1@ UMA_TV_CRMA TXOUT_L3P(NC)
    <16> UMA_TV_CRMA E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
    2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z 0_0603_5% UMA_TV_LUMA

    CRT/TVOUT
    <16> UMA_TV_LUMA F17 Y(DFT_GPIO2)
    2
    1 GM@ 2 F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 UMA_LCD_TZOUT0_B0+ <17>
    R97 140_0402_1% A18 UMA_LCD_TZOUT0_B0- <17>
    UMA_CRT_R TXOUT_U0N(NC)
    <16> UMA_CRT_R G18 RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) A17 UMA_LCD_TZOUT0_B1+ <17>
    G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17 UMA_LCD_TZOUT0_B1- <17>
    UMA_CRT_G E18 D20 UMA_LCD_TZOUT0_B2+ <17>
    <16> UMA_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC)
    F18 GREENb(NC) TXOUT_U2N(NC) D21 UMA_LCD_TZOUT0_B2- <17>
    UMA_CRT_B E19 D18
    <16> UMA_CRT_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
    L7 RV@ F19 D19
    BLM18PG121SN1D_0603 BLUEb(NC) TXOUT_U3N(NC)
    UMA_CRT_HSYNC A11 B16 UMA_LCD_TXCLK_ACLK+ <17>
    <14,16> UMA_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
    UMA_CRT_VSYNC B11 A16 UMA_LCD_TXCLK_ACLK- <17>
    +1.8VS +NB_HTPVDD <14,16> UMA_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
    GM@ L7 F8 D16 UMA_LCD_TZCLK_BCLK+ <17>
    <16> UMA_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
    1 2 <16> UMA_CRT_DATA E8 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17 UMA_LCD_TZCLK_BCLK- <17>
    BLM18PG121SN1D_0603 1
    R65 1 GM@ 2 715_0402_1% G14
    C176 GM@ C176 PM1@ C176 RV@ R65 RV@ DAC_RSET(PWM_GPIO1) +VDDLTP18
    VDDLTP18(NC) A13
    2.2U_0603_6.3V4Z 0_0603_5% 2.2U_0603_6.3V4Z 715_0402_1% +NB_PLLVDD +NB_PLLVDD A12 B13
    2 +NB_HTPVDD PLLVDD(NC) VSSLTP18(NC)
    +NB_HTPVDD D14 PLLVDD18(NC)
    B12 A15 +VDDLT18

    LVTM
    PLLVSS(NC) VDDLT18_1(NC)
    B15

    PLL PWR
    VDDLT18_2(NC)
    +VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
    VDDLT33_2(NC) B14
    +VDDA18PCIEPLL D7 VDDA18PCIEPLL1
    E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
    <14,19,20,26,27,28,32,33> PLT_RST# 1 2 VSSLT2(VSS) D15
    R67 0_0402_5% NB_RESET# D8 C16
    +1.8VS NB_PWRGD SYSRESETb VSSLT3(VSS)
    <21> NB_PWRGD A10 POWERGOOD VSSLT4(VSS) C18
    +1.1VS C10 C20
    3 <6,20> LDT_STOP# LDTSTOPb VSSLT5(VSS) 3
    1 2 NB_PWRGD C12 E20

    PM
    <6,20> CPU_LDT_REQ# ALLOW_LDTSTOP VSSLT6(VSS)
    R371 300_0402_5% C22
    VSSLT7(VSS)
    2

    <15> CLK_NBHT C25 HT_REFCLKP


    R71 C24
    <15> CLK_NBHT# HT_REFCLKN
    4.7K_0402_5%
    <15> NB_OSC_14.318M E11 REFCLK_P/OSCIN(OSCIN)

    CLOCKs
    F11 E9 UMA_ENVDD <17>
    1 1

    REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP)
    LVDS_BLON(PCE_RCALRP) F7 1 GM@ 2 ENBKL <19,33>
    T2 G12 R79 0_0402_5%
    <15> NBGFX_CLK GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2)
    <15> NBGFX_CLK# T1 GFX_REFCLKN 2 GM@ 1
    R72 R73 100K_0402_5%
    4.7K_0402_5% U1 GPP_REFCLKP R73 RV@
    U2
    2

    GPP_REFCLKN 100K_0402_5%
    <15> CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)
    L9 RV@ V3 R78 RV@
    <15> CLK_SBLINK_BCLK# GPPSB_REFCLKN(SB_REFCLKN)
    BLM18PG121SN1D_0603 0_0402_5%
    <17> UMA_LCD_DDC_CLK B9 I2C_CLK
    A9 D9 1 GM@ 2
    +1.1VS <17> UMA_LCD_DDC_DAT
    B8
    I2C_DATA MIS. TMDS_HPD(NC)
    D10 R78 0_0402_5%
    HPD <18,19>
    +NB_PLLVDD <18> HDMIDAT_UMA DDC_DATA0/AUX0N(NC) HPD(NC)
    GM@ L9 A8
    <18> HDMICLK_UMA DDC_CLK0/AUX0P(NC)
    1 2 B7 DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) D12 SUS_STAT# <14,21>
    BLM18PG121SN1D_0603 1 A7 Strap pin
    PM1@ DDC_DATA1/AUX1N(NC)
    THERMALDIODE_P AE8
    C178 GM@ C178 PM1@ C178 RV@ +3VS 2 1 B10 AD8
    2.2U_0603_6.3V4Z 0_0603_5% 2.2U_0603_6.3V4Z STRP_DATA THERMALDIODE_N
    2 R88 10K_0402_5% G11 RSVD TESTMODE D13 1 2
    R88 RV@ R80
    10K_0402_5% C8 1.8K_0402_5%
    <14> AUX_CAL AUX_CAL(NC)
    Strap pin RS780M_FCBGA528
    4 4
    RS780MR3@
    +1.8VS +VDDA18HTPLL +1.8VS +VDDA18PCIEPLL
    L10 L11
    1 2 1 2
    BLM18PG121SN1D_0603 1 BLM18PG121SN1D_0603 1
    C179 C180 /
    2.2U_0603_6.3V4Z
    2
    2.2U_0603_6.3V4Z
    2
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 11 of 45
    A B C D E
    2 1

    U3D
    PAR 4 OF 6
    AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
    AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
    V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
    AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
    AA12 MEM_A4(NC) MEM_DQ4(NC) V17
    AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
    AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
    AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
    AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
    AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19

    SBD_MEM/DVO_I/F
    AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
    AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
    AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
    Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
    MEM_DQ14/DVO_D10(NC) AC22
    AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
    AE17 MEM_BA1(NC)
    AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
    MEM_DQS0N/DVO_IDCKN(NC) W18
    W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
    B B
    Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
    AD18 MEM_WEb(NC)
    AB13 MEM_CSb(NC) MEM_DM0(NC) W17
    AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19
    V14 MEM_ODT(NC)
    IOPLLVDD18(NC) AE23 +1.8VS
    V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
    W14 MEM_CKN(NC)
    IOPLLVSS(NC) AD23
    AE12 MEM_COMPP(NC)
    AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18

    RS780M_FCBGA528
    RS780MR3@

    A A

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 12 of 45
    2 1
    A B C D E

    U3F
    A25 VSSAHT1 VSSAPCIE1 A2
    D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
    E22 VSSAHT3 VSSAPCIE3 D3
    G22 VSSAHT4 VSSAPCIE4 D5
    G24 VSSAHT5 VSSAPCIE5 E4
    G25 VSSAHT6 VSSAPCIE6 G1
    1 L16 1
    2A H19 VSSAHT7 VSSAPCIE7 G2
    +1.1VS 2 1 +VDDHT J22 G4
    0_0805_5% VSSAHT8 VSSAPCIE8
    L17 VSSAHT9 VSSAPCIE9 H7
    1 1 1 1 1 L22 VSSAHT10 VSSAPCIE10 J4
    L17 L24 R7
    C209 C206 C207 C208 C210 VSSAHT11 VSSAPCIE11
    1 2 +1.1VS L25 VSSAHT12 VSSAPCIE12 L1
    VDDA_12=2.5A FBMA-L11-201209-221LMA30T_0805 M20 L2
    2 2 2 2 2 U3E VSSAHT13 VSSAPCIE13
    N22 VSSAHT14 VSSAPCIE14 L4
    J17 A6 +VDDA11PCIE P20 L7
    VDDHT_1 VDDPCIE_1 C211 10U_0805_10V4Z VSSAHT15 VSSAPCIE15
    4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 R19 VSSAHT16 VSSAPCIE16 M6
    L16 VDDHT_3 VDDPCIE_3 C6 R22 VSSAHT17 VSSAPCIE17 N4
    L18 2A 0.1U_0402_16V4Z 0.1U_0402_16V4Z M16 D6 C212 10U_0805_10V4Z R24 P6
    +VDDHTRX VDDHT_4 VDDPCIE_4 VSSAHT18 VSSAPCIE18
    2 1 P16 VDDHT_5 VDDPCIE_5 E6 R25 VSSAHT19 VSSAPCIE19 R1
    0_0805_5% R16 F6 C220 1 2 1U_0402_6.3V4Z H20 R2
    VDDHT_6 VDDPCIE_6 C219 1U_0402_6.3V4Z VSSAHT20 VSSAPCIE20
    1 1 1 1 T16 VDDHT_7 VDDPCIE_7 G7 1 2 U22 VSSAHT21 VSSAPCIE21 R4
    H8 C222 1 2 1U_0402_6.3V4Z V19 V7
    C215 C214 C216 C217 C218 VDDPCIE_8 C221 1U_0402_6.3V4Z VSSAHT22 VSSAPCIE22

    GROUND
    H18 VDDHTRX_1 VDDPCIE_9 J9 1 2 W22 VSSAHT23 VSSAPCIE23 U4
    G19 K9 C224 2 1 0.1U_0402_16V4Z W24 V8
    2 2 2 2 VDDHTRX_2 VDDPCIE_10 C223 0.1U_0402_16V4Z VSSAHT24 VSSAPCIE24
    F20 VDDHTRX_3 VDDPCIE_11 M9 2 1 W25 VSSAHT25 VSSAPCIE25 V6
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21 L9 Y21 W1
    VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
    D22 VDDHTRX_5 VDDPCIE_13 P9 AD25 VSSAHT27 VSSAPCIE27 W2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z B23 R9 W4
    VDDHTRX_6 VDDPCIE_14 VSSAPCIE28
    A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
    L19 2A V9 M14 W8
    +VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30
    +1.2V_HT 2 1 AE25 VDDHTTX_1 VDDPCIE_17 U9 N13 VSS13 VSSAPCIE31 Y6
    0_0805_5% AD24 PJP3 P12 AA4
    VDDHTTX_2 VSS14 VSSAPCIE32
    1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 +1.1VS 1 2 +NB_CORE P15 VSS15 VSSAPCIE33 AB5
    AB22 VDDHTTX_4 VDDC_2 J14 R11 VSS16 VSSAPCIE34 AB1
    C225 C226 C227 C228 C229 AA21 U16 PAD-OPEN 4x4m R14 AB7
    VDDHTTX_5 VDDC_3 VSS17 VSSAPCIE35
    Y20 VDDHTTX_6 VDDC_4 J11 T12 VSS18 VSSAPCIE36 AC3
    2 2 2 2 2
    W19 VDDHTTX_7 VDDC_5 K15 U14 VSS19 VSSAPCIE37 AC4

    POWER
    2
    V18 VDDHTTX_8 VDDC_6 M12 VDD_CORE:GM=5A/PM=10A U11 VSS20 VSSAPCIE38 AE1
    2
    U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
    4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T17 L11 V12 AB2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDHTTX_10 VDDC_8 VSS22 VSSAPCIE40
    R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23
    P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
    M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14

    330U_D2E_2.5VM
    C247

    C240

    C241

    C242

    C243

    C230

    C231

    C244

    C232

    C233

    C245
    L22 2A N14 1 AA14 D11
    +VDDA18PCIE VDDC_12 VSS26 VSS2
    +1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 VSS27 VSS3 G8

    C234
    0_0805_5% P10 P13 + AB11 E14
    VDDA18PCIE_2 VDDC_14 VSS28 VSS4
    1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 AB15 VSS29 VSS5 E15

    10U_0805_10V4Z

    10U_0805_10V4Z
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    M10 VDDA18PCIE_4 VDDC_16 R12 AB17 VSS30 VSS6 J15
    C235 C246 C236 C237 C238 C239 2 2 2 2 2 2 2 2 2 2 2 2
    L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
    4.7U_0805_10V4Z W9 T11 AE20 K14
    2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
    H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
    T10 VDDA18PCIE_8 VDDC_20 U12 K11 VSS34 VSS10 L15
    R10 VDDA18PCIE_9 VDDC_21 T14
    4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Y9 J16 RS780M_FCBGA528
    0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDA18PCIE_10 VDDC_22
    AA9 VDDA18PCIE_11
    AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
    AD9 AA11 RS780MR3@
    L89 RV@ VDDA18PCIE_13 VDD_MEM2(NC)
    AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
    0_0603_5% U10 AD10
    VDDA18PCIE_15 VDD_MEM4(NC)
    VDD_MEM5(NC) AB10
    +1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10
    G9 VDD18_2
    +1.8VS 1 2 AE11 VDD18_MEM1(NC) VDD33_1(NC) H11
    GM@ L89 AD11 H12
    0_0603_5% VDD18_MEM2(NC) VDD33_2(NC) C250 RV@
    1 1 RS780M_FCBGA528 0.1U_0402_16V4Z
    C251 GM@ RS780MR3@ +3VS
    1U_0402_6.3V4Z C252
    1U_0402_6.3V4Z 1GM@ 2
    2 2 0.1U_0402_16V4Z C250
    3 3
    1GM@ 2
    C252 PM1@ 0.1U_0402_16V4Z C253
    0_0402_5%

    C252 RV@ C253 RV@


    1U_0402_6.3V4Z 0.1U_0402_16V4Z

    4 4

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 13 of 45
    A B C D E
    A B C D E

    RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb


    SI2: Change to 3K pull high
    <11,16> UMA_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO.
    R101 3K_0402_5%
    1 : Enable (RX780, RS780)
    2 1
    1 R102 @ 3K_0402_5% 0 : Disable (RX780, RS780) 1
    PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

    DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

    These pin straps are used to configure PCI-E GPP mode.


    000 : 00001
    001 : 00010
    RS780 use register to control PCI-E configure 010 : 01011
    011 : 00100
    100 : 01010
    101 : 01100
    111 : 01011

    2 2

    DFT_GPIO1: LOAD_EEPROM_STRAPS

    <11> AUX_CAL 1 2
    @R104
    @ R104 150_0402_1% Selects Loading of STRAPS from EPROM
    D4 @ CH751H-40PT_SOD323-2
    1 : Bypass the loading of EEPROM straps and use Hardware Default Values
    RS780 DFT_GPIO1 <11,21> 2 1 0 : I2C Master can load strap values from EEPROM if connected, or use
    SUS_STAT# PLT_RST# <11,19,20,26,27,28,32,33>
    default values if not connected
    RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

    DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
    3 3

    RX780: Enables the Test Debug Bus using PCIE bus


    1 : Disable ( Can still be enabled using nbcfg register access )
    0 : Enable
    RS780 use HSYNC to enable SIDE PORT (internal pull high)
    RS780: Enables Side port memory ( RS780 use HSYNC#)
    1. Disable (RS780)
    <11,16> UMA_CRT_HSYNC 2 1 +3VS
    R125 3K_0402_5% 0 : Enable (RS780)

    4 4

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 14 of 45
    A B C D E
    A B C D E

    +1.2V_HT +VDDCLK_IO +3VS_CLK


    R167
    +3VS 1 2
    R168 0_0805_5% 1 1 1 1 1 1 1 1
    1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C445 C446 C447 C448 C449 C450 C451
    0_0805_5% 1 1 1 1 1 1 C444
    22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z
    C452 C453 C454 C455 C456 C457 2 2 2 2 2 2 2 2
    22U_0805_6.3V6M
    2 2 2 2 2 2
    +3VS_CLK
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1
    1 C458 C459 C460 C461 1

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


    2 2 2 2

    CLK_XTAL_OUT

    CLK_XTAL_IN

    Y2
    CLK_48M_CRUSB R170 1 2 33_0402_5%
    CLK_48M_USB <21>
    2 1 OSC_14M_NB
    NB_OSC_14.318M_R 1 2
    14.31818MHZ_20P_6X1430004201 R379 158_0402_1% NB_OSC_14.318M <11>
    RS780 1.1V 158R/90.9R

    +3VS_CLK
    1 1 1 2 R380
    C464 C465 90.9_0402_1%

    SEL_SATA
    27M_SEL
    22P_0402_50V8J 22P_0402_50V8J
    2 2
    CLK_NBHT <11>

    +3VS_CLK
    +3VS_CLK
    CLK_NBHT# <11>NB
    1 2 +3VS_CLK

    CLK_XTAL_OUT
    Routing the trace at least 10mil R174 8.2K_0402_5%
    CLK_CPU_BCLK <6>

    CLK_XTAL_IN
    1 2

    2
    2 C629 1U_0402_6.3V4Z 2
    1 2 R186
    R946 0_0402_5% @ 261_0402_1% CPU
    1 2
    R945 0_0402_5%

    1
    CLK_CPU_BCLK# <6>

    73

    72
    71
    70
    69
    68
    67
    66
    65
    64
    63
    62
    61
    60
    59
    58
    57
    56
    55
    U10

    GND

    XTAL_IN

    REF_1/SEL_SATA
    VSS_48
    48MHz_0
    48MHz_1
    VDD_48
    XTAL_OUT

    REF_2/SEL_27

    HTT_0/66M_0
    HTT_0#/66M_1

    PD#
    CPU_K8_0
    VSS_REF
    REF_0/SEL_HTT66

    VDD_REF
    VDD_HTT

    VSS_HTT

    CPU_K8_0#
    CLKREQ_NCARD# 1 2 +3VS_CLK
    R324 8.2K_0402_5%
    CLKREQ_MCARD2# 1 2
    1 54 +3VS_CLK R325 8.2K_0402_5%
    <8,9,21,27> SMB_CK_CLK0 SCL VDD_CPU CLKREQ_MCARD1#
    2 SDA VDD_CPU_I/O 53 +VDDCLK_IO 1 2
    <8,9,21,27> SMB_CK_DAT0 R326 8.2K_0402_5%
    +3VS_CLK 3 VDD_DOT VSS_CPU 52
    R226 1 @ 2 0_0402_5% 4 51 CLKREQ_NCARD# CLKREQ_LAN 1 2
    <19> 27M_CLK R228 SRC_7#/27M CLKREQ_1# CLKREQ_NCARD# <27>
    1 @ 2 0_0402_5% 5 SRC_7/27M_SS CLKREQ_2# 50 CLKREQ_MCARD2# R390 8.2K_0402_5%
    <19> 27M_SSC CLKREQ_MCARD2# <27>
    6 VSS_DOT VDD_A 49 +3VS_CLK
    7 SRC_5# VSS_A 48
    8 SRC_5 VSS_SATA 47
    <11> CLK_SBLINK_BCLK# 9 SRC_4# SRC_6/SATA 46 CLK_SBSRC_BCLK <20>
    SB LINK <11> CLK_SBLINK_BCLK 10 SRC_4 SRC_6#/SATA# 45 SB
    CLK_SBSRC_BCLK# <20> SRC
    11 VSS_SRC VDD_SATA 44 +3VS_CLK
    +VDDCLK_IO 12 43 CLKREQ_MCARD1#
    VDD_SRC_IO CLKREQ_3# CLKREQ_MCARD1# <27>
    <27> CLK_PCIE_MCARD1# 13 SRC_3# CLKREQ_4# 42
    <27> CLK_PCIE_MCARD1 14 SRC_3 SB_SRC_SLOW# 41 1 2 +3VS_CLK
    15 40 R372 10K_0402_5%
    <27> CLK_PCIE_MCARD2# SRC_2# SB_SRC_0
    WLAN <27> CLK_PCIE_MCARD2 16 SRC_2 SB_SRC_0# 39
    +3VS_CLK 17 VDD_SRC VDD_SB_SRC 38 +3VS_CLK
    +VDDCLK_IO 18 VDD_SRC_IO VDD_SB_SRC_IO 37 +VDDCLK_IO

    VDD_ATIG_IO

    VSS_SB_SRC
    3 3

    ATIGCLK_2#

    ATIGCLK_1#

    ATIGCLK_0#
    CLKREQ_0#

    SB_SRC_1#
    ATIGCLK_2

    ATIGCLK_1

    ATIGCLK_0

    SB_SRC_1
    VDD_ATIG
    VSS_ATIG
    VSS_SRC
    SRC_1#

    SRC_0#
    SRC_1

    SRC_0

    +3VS_CLK
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    2

    SLG8SP626VTR_QFN72_10x10
    R179
    @ 8.2K_0402_5%
    1

    SEL_SATA +3VS_CLK
    +3VS_CLK
    +VDDCLK_IO
    2

    R181 NB CLOCK INPUT TABLE


    NBGFX_CLK <11>
    R180
    8.2K_0402_5% NBGFX_CLK# <11> NB GFX
    8.2K_0402_5% NB CLOCKS RX780 RS780
    CLK_PCIE_VGA <19>
    CLK_PCIE_VGA# <19>
    1

    HT_REFCLKP
    1

    27M_SEL 100M DIFF 100M DIFF


    HT_REFCLKN 100M DIFF 100M DIFF
    CLK_PCIE_MCARD0 <28>
    REFCLK_P
    CLK_PCIE_MCARD0# <28>MiniCard_1
    1 configure as SATA output CLKREQ_LAN 14M SE (1.8V) 14M SE (1.1V)
    CLKREQ_LAN <26>
    SEL_SATA 1 * configure as 27M and 27M_SS output REFCLK_N NC vref
    CLK_PCIE_LAN <26>
    0 * configure as normal SRC(SRC_6) output 27M_SEL GLAN
    CLK_PCIE_LAN# <26>
    * default 0 configure as SRC_7 output GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
    * default
    CLK_PCIE_NCARD <27> NC or 100M DIFF OUTPUT
    New Card GPP_REFCLK 100M DIFF
    4 CLK_PCIE_NCARD# <27> 4
    GPPSB_REFCLK 100M DIFF 100M DIFF

    Use voltage divider resistor R379 & R380 to pull low /

    1 configure as single-ended 66MHz output


    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    NB_OSC_14.318M
    0* configure as differential 100MHz output
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    * default AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 15 of 45
    A B C D E
    A B C D E

    CRT CONNECTOR
    +5VS +R_CRT_VCC +CRT_VCC
    D36 F2
    <11> UMA_CRT_R 1 2 2 1 1 2

    1
    R662 GM@ 0_0402_5% D35 D37 D34 1
    1 2 RB491D_SOT23 1A_6VDC_MINISMDC110
    <19> VGA_CRT_R
    R666 PM@ 0_0402_5% C475
    1 0.1U_0402_16V4Z 1
    <11> UMA_CRT_G 1 2
    R664 GM@ 0_0402_5% +3VS 2
    1 2 DAN217_SC59 DAN217_SC59DAN217_SC59
    <19> VGA_CRT_G

    3
    R663 PM@ 0_0402_5% @ @ @
    <11> UMA_CRT_B 1 2
    R665 GM@ 0_0402_5%
    <19> VGA_CRT_B 1 2 JCRTB
    R661 PM@ 0_0402_5% L47
    RED 1 2 RED_L BLUE_L 1
    BLM15BB121SN1D_0402 1
    2 2
    L48 GREEN_L 3
    GREEN GREEN_L 3
    1 2 4 4
    R214 PM@ BLM15BB121SN1D_0402 RED_L 5
    150_0402_1% L49 5
    6 6
    BLUE 1 2 BLUE_L VSYNC 7
    BLM15BB121SN1D_0402 HSYNC 7
    8 8

    6P_0402_50V8K

    6P_0402_50V8K

    6P_0402_50V8K
    9 9

    140_0402_1%

    150_0402_1%

    150_0402_1%

    6P_0402_50V8K

    6P_0402_50V8K

    6P_0402_50V8K
    1 1 1 D_DDCCLK 10 10

    1
    USE RS780 A13 change R pull low GM@ 1 1 1 D_DDCDATA 11 13
    R214 R211 R217 C471 C859 C469 11 GND
    +CRT_VCC 12 14
    from 150 to 140 ohm C858 12 GND
    2 2 2 C476 C472
    2 2 2 ACES_85201-1205N

    2
    @

    +3VS

    +CRT_VCC
    PM:VGA Board have pull high
    R100 PM@ R218 PM@
    2K_0402_1% 2K_0402_1% +CRT_VCC
    1

    2 GM@ GM@ 2
    R237 R238 +3VS GM@ GM@ 1 2
    4.7K_0402_5% 4.7K_0402_5% R100 R218 C473

    5
    1
    6.8K_0402_5% 6.8K_0402_5% 0.1U_0402_16V4Z
    5

    P
    OE#
    2

    1 2 2 4 D_HSYNC 1 2 HSYNC
    <11,14> UMA_CRT_HSYNC A Y
    <11> UMA_CRT_DATA 1 2 CRT_DATA 4 3 D_DDCDATA R673 GM@ 0_0402_5% L84 10_0402_5%

    G
    R672 GM@ 0_0402_5% U14
    1 2 Q10B 1 2
    <19> VGA_CRT_DATA <19> VGA_CRT_HSYNC

    3
    R670 PM@ 0_0402_5% 2N7002DW-7-F_SOT363-6 R674 PM@ 0_0402_5% SN74AHCT1G125GW_SOT353-5 1 2 VSYNC
    1

    @ L83 10_0402_5%

    10P_0402_50V8J

    10P_0402_50V8J
    C177
    33P_0402_50V8K +3VS +CRT_VCC
    1 1
    2

    1 2 C474 C470
    2

    C477 @ @
    FOR EMI

    5
    1
    0.1U_0402_16V4Z 2 2
    1 2 CRT_CLK 1 6 D_DDCCLK

    P
    OE#
    <11> UMA_CRT_CLK
    R669 GM@ 0_0402_5% 1 2 2 4 D_VSYNC
    <11,14> UMA_CRT_VSYNC A Y
    1 2 1 1 R676 GM@ 0_0402_5%
    <19> VGA_CRT_CLK Q10A
    1

    G
    R671 PM@ 0_0402_5% @ U13
    C181 2N7002DW-7-F_SOT363-6 C857 C856 1 2 SN74AHCT1G125GW_SOT353-5
    <19> VGA_CRT_VSYNC

    3
    @ @ R675 PM@ 0_0402_5%
    RS780 DAC_SCL & SDA is 5V tolerance 33P_0402_50V8K
    2

    470P_0402_50V8J 2 2 470P_0402_50V8J

    3 3
    D5 D6
    @ DAN217_SC59 @ DAN217_SC59

    TV-OUT CONNECTOR

    1
    2

    3
    +3VS
    1 2 C750
    1 2 @ 22P_0402_50V8J
    <19> VGA_TV_LUMA
    R289 PM@ 0_0402_5% TV@
    1 2 TV_LUMA 1 2
    <11> UMA_TV_LUMA
    R287 GM@ 0_0402_5% L58 MBK1608121YZF_0603
    TV@
    1 2 TV_CRMA 1 2
    <19> VGA_TV_CRMA
    R295 PM@ 0_0402_5% L57 MBK1608121YZF_0603
    1 2 JTV
    <11> UMA_TV_CRMA
    R291 GM@ 0_0402_5% 1 2 C754 TV_CRMA_L 4 CRMA
    1

    TV@ 1 1 @ 22P_0402_50V8J TV_LUMA_L 3 6


    R433 TV@ TV@ TV@ LUMA GND
    2 5
    150_0402_1% R434
    150_0402_1%
    C753
    100P_0402_25V8K
    C755
    100P_0402_25V8K
    1
    TV@
    C751
    1
    TV@
    C752
    1
    GND
    GND
    GND TV-OUT Conn.
    2 2 ALLTO_C10888-10405-L 1. Y ground
    2

    2 2 @ 2. C ground
    100P_0402_25V8K 100P_0402_25V8K 3. Y (luminance+sync)
    4. C (crominance)
    4 4

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 16 of 45
    A B C D E
    A B C D E

    LCD/PANEL BD. Conn.


    +LCD_VDD +3V_SB

    1
    1 1
    R142 R143 +3VS
    300_0603_5% 1M_0402_5% W=60mils
    <11> UMA_LCD_TXOUT0_A0+ 1 2

    6 2

    2
    R543 GM@ 0_0402_5% LCD_TXOUT0+
    <19> LCD_TXOUT0+
    1 2 LCD_TXOUT0- Q1A
    <11> UMA_LCD_TXOUT0_A0-

    3
    S
    R580 GM@ 0_0402_5% 2N7002DW-T/R7_SOT363-6 100K_0402_5%
    <19> LCD_TXOUT0- G
    2 1 2 2 Q2
    1 2 R140 AO3413_SOT23
    <11> UMA_LCD_TXOUT0_A1+

    3
    R566 GM@ 0_0402_5% LCD_TXOUT1+ 2
    D
    <19> LCD_TXOUT1+

    1
    C262 +LCD_VDD
    1 2 LCD_TXOUT1- 1000P_0402_50V7K W=60mils
    <11> UMA_LCD_TXOUT0_A1-
    R578 GM@ 0_0402_5% 1 2 ENVDD 5 Q1B
    <19> LCD_TXOUT1- <11> UMA_ENVDD 1
    R668 GM@ 0_0402_5% 2N7002DW-T/R7_SOT363-6
    <11> UMA_LCD_TXOUT0_A2+ 1 2 <19> VGA_ENVDD 1 2 1 1

    4
    1
    R573 GM@ 0_0402_5% LCD_TXOUT2+ R667 PM@ 0_0402_5% C263 C264
    <19> LCD_TXOUT2+
    1 2 LCD_TXOUT2- R144 @ 4.7U_0805_10V4Z 0.1U_0402_16V4Z
    <11> UMA_LCD_TXOUT0_A2- 2 2
    R574 GM@ 0_0402_5% 100K_0402_5%
    <19> LCD_TXOUT2-

    2
    <11> UMA_LCD_TXCLK_ACLK+ 1 2
    R540 GM@ 0_0402_5% LCD_TXCLK+
    <19> LCD_TXCLK+
    1 2 LCD_TXCLK-
    <11> UMA_LCD_TXCLK_ACLK-
    R559 GM@ 0_0402_5%
    <19> LCD_TXCLK-

    <11> UMA_LCD_TZOUT0_B0+ 1 2
    R590 GM@ 0_0402_5% LCD_TZOUT0+
    <19> LCD_TZOUT0+
    1 2 LCD_TZOUT0-
    2 <11> UMA_LCD_TZOUT0_B0- 2
    R681 GM@ 0_0402_5%
    <19> LCD_TZOUT0-

    <11> UMA_LCD_TZOUT0_B1+ 1 2
    R631 GM@ 0_0402_5% LCD_TZOUT1+
    <19> LCD_TZOUT1+
    1 2 LCD_TZOUT1-
    <11> UMA_LCD_TZOUT0_B1-
    R680 GM@ 0_0402_5%
    <19> LCD_TZOUT1-
    1 2 JLVDS 1.5A
    <11> UMA_LCD_TZOUT0_B2+
    R660 GM@ 0_0402_5% LCD_TZOUT2+ 2 +LCDVDD_R 2 L8
    <19> LCD_TZOUT2+
    LCD_TXOUT0+ 2 1 1 LCD_TXCLK+ 0_0805_5%
    1 +LCD_VDD
    4 4 3 3
    1 2 LCD_TZOUT2- LCD_TXOUT0- 6 LCD_TXCLK-
    <11> UMA_LCD_TZOUT0_B2-
    R677 GM@ 0_0402_5% 6 5 5 1 1
    <19> LCD_TZOUT2- 8 8 7 7
    LCD_TXOUT1+ 10 C265 C266
    LCD_TZCLK+ LCD_TXOUT1- 10 9 9 DAC_BRIG <33>
    0.1U_0402_16V4Z 4.7U_0805_10V4Z
    <11> UMA_LCD_TZCLK_BCLK+ 1 2 12 12 11 11 INVT_PWM <33>
    R591 GM@ 0_0402_5% 2 2
    <19> LCD_TZCLK+ 14 14 13 13
    LCD_TXOUT2+ 16 LCD_TZCLK+
    LCD_TZCLK- LCD_TXOUT2- 16 15 15 LCD_TZCLK-
    <11> UMA_LCD_TZCLK_BCLK- 1 2 18 18 17 17
    R594 GM@ 0_0402_5% 20
    <19> LCD_TZCLK-
    LCD_TZOUT0+ 20 19 19 LCD_EDID_CLK
    22 22 21 21
    1 2 LCD_TZOUT0- 24 LCD_EDID_DATA
    <11> UMA_LCD_DDC_CLK
    R555 GM@ 0_0402_5% LCD_EDID_CLK 24 23 23 +3VS
    <19> LCD_EDID_CLK 26 26 25 25
    LCD_TZOUT1+ 28 +LCDVDD_R
    LCD_EDID_DATA LCD_TZOUT1- 28 27 27
    <11> UMA_LCD_DDC_DAT 1 2 30 30 29 29
    R586 GM@ 0_0402_5% 32
    <19> LCD_EDID_DATA
    LCD_TZOUT2+ 32 31 31 1
    34 34 33 33 +LCD_INV
    LCD_TZOUT2- 36 C267
    36 35 35 B+ 0.1U_0402_16V4Z
    38 38 37 37
    BKOFF# L12 2
    <33> BKOFF# 40 40 39 39
    42 GND GND 41 2 1
    FBMA-L11-201209-221LMA30T_0805
    ACES_88242-4001 1 1 Rated Current MAX:3000mA
    3 3
    @
    C268 C269
    68P_0402_50V8J 0.1U_0402_25V4Z
    2 2
    +3VS

    1 @ 2 BKOFF#
    R175 4.7K_0402_5%
    1 GM@ 2 UMA_LCD_DDC_CLK
    R68 4.7K_0402_5%
    1 GM@ 2 UMA_LCD_DDC_DAT
    R69 4.7K_0402_5%

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 17 of 45
    A B C D E
    A B C D E

    +5VL +3VL

    2
    HDMI CEC Controller
    U8
    U28 @
    VCC 3
    +5VL R157
    10K_0402_5%
    H@
    D13
    CH751H-40PT_SOD323-2
    H@
    CEC_RST# 2 1

    1 1
    SMB_EC_CK1 RESET# C626
    <33,34,37> SMB_EC_CK1 1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 11 CEC_INT# <33> +5VL
    1 0.1U_0402_16V4Z HDMI_CECIN
    H@ GND @ R583
    +5VL CEC_TEST G691L308T72UF_SOT23-3 2 27K_0402_5%
    2 P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 12 1 2

    1
    1 R169 4.7K_0402_5% H@ D H@ 1
    H@ Q149 2 HDMI_CEC

    2
    2 1CEC_RST# 3 RESET# P1_4/TXD0 13 CEC_FSHUPD 1 2 2N7002_SOT23-3 G
    R182 4.7K_0402_5% R171 4.7K_0402_5% U35 @ S

    3
    H@ CEC_FSHUPD (Pin13) 5 Vcc
    +5VL NC 1
    2 1CEC_XOUT 4 XOUT/P4_7 P1_3/KI3#/AN11/TZOUT 14 Low= Force to update flash. 1 A 2
    HDMI_CEC

    1
    R178 4.7K_0402_5% @ HDMI_CECIN R163 D H@
    1 2 4 Y GND 3
    H@ H@ C543 1U_0402_6.3V4Z C627 HDMI_CECOUT 1 2 2 Q150
    5 15 1 2 1U_0402_6.3V4Z TC7SET14FU_SOT353-5 G 2N7002_SOT23-3
    VSS/AVSS P1_2/KI2#/AN10/CMP0_2 H@ C257 0.1U_0402_16V4Z 2 27K_0402_5% S

    3
    1
    H@
    R177
    1 2CEC_XIN 6 XIN/P4_6 P4_2/VREF 16 +5VL R165
    47K_0402_5% 100K_0402_5%
    H@ H@
    7 17 HDMI_SCLK H@

    2
    VCC/AVCC P1_1/KI1#/AN9/CMP0_1 D17 F3 H@
    +5VL 2 +5VS_HDMI
    1 2 1 +HDMI_5V_OUT
    2 1 8 18 HDMI_SDATA 1.1A_6V_MINISMDC110F-2
    1
    R183 4.7K_0402_5% MODE P1_0/KI0#/AN8/CMP0_0 RB161M-20_SOD123-2 C258
    C256 1 H@ D53 H@
    0.1U_0402_16V4Z HDMI_CECIN 9 19 HDMI_HPD_R +5VS 2 1 0.1U_0402_16V4Z
    H@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 2 8MHZ_20PF_X8A008000IK1H
    RB161M-20_SOD123-2 CEC_XIN 2 1 2 2 CEC_XOUT
    2 HDMI_CECOUT SMB_EC_DA1 H@
    10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 SMB_EC_DA1 <33,34,37>
    C623 Y5 @ C619
    22P_0402_50V8J 22P_0402_50V8J
    R5F211A4SP_LSSOP20 @ 1 1 @
    H@

    2 2

    H@ C189 1 2 0.1U_0402_16V7K HDMI_TX0+


    <10,19> HDMI_TXD0+
    H@ C188 1 2 0.1U_0402_16V7K HDMI_TX0-

    +5VL 2
    R589 H@
    1 2
    R588 H@
    1 +3VS
    <10,19> HDMI_TXD0-
    <10,19> HDMI_TXD1+
    <10,19> HDMI_TXD1-
    H@
    H@
    C190
    C184
    1
    1
    2
    2
    0.1U_0402_16V7K
    0.1U_0402_16V7K
    HDMI_TX1+
    HDMI_TX1- HDMI Connector
    2.2K_0402_5% 2.2K_0402_5% JHDMI
    HDMI_HPD_R 1 2 H@ C187 1 2 0.1U_0402_16V7K HDMI_TX2+ HDMI_HPD 19
    <33> HDMI_HPD_R HPD <11,19> <10,19> HDMI_TXD2+ HP_DET
    D57 H@ C191 1 2 0.1U_0402_16V7K HDMI_TX2- +HDMI_5V_OUT 18
    <10,19> HDMI_TXD2- +5V
    CH751H-40PT_SOD323-2 H@ C185 1 2 0.1U_0402_16V7K HDMI_CLK+ 17
    <10,19> HDMI_CLK0+ DDC/CEC_GND
    SI:Add R6161~R624 for EMI requset H@ H@ C186 1 2 0.1U_0402_16V7K HDMI_CLK- HDMI_SDATA 16
    <10,19> HDMI_CLK0- SDA
    HDMI_SCLK 15
    HDMI_CLK- @ HDMI_R_CK- SCL
    1 2 14 Reserved
    R616 0_0402_5% HDMI_CEC 13
    HDMI_R_CK- CEC
    12 CK- GND 20
    L85 H@ 11 21
    HDMI_R_CK+ CK_shield GND
    1 1 2 2 10 CK+ GND 22
    HDMI_R_D0- 9 23
    D0- GND
    8 D0_shield
    4 3 HDMI_R_D0+ 7
    4 3 R307 HDMI@ HDMI_R_D1- D0+
    6 D1-
    WCM-2012-900T_0805 499_0402_1% H@ 5
    HDMI_CLK+ @ HDMI_R_CK+ HDMI_R_D1+ D1_shield
    1 2 Q136A 4 D1+
    R617 0_0402_5% HDMI_R_D2- 3
    2N7002DW-7-F_SOT363-6 D2-
    2 D2_shield
    HDMI_R_CK+ 1 IHDMI@ 2 6 1 HDMI_R_D2+ 1
    R307 715_0402_1% D2+
    HDMI_TX0- 1 @ 2 HDMI_R_D0- HDMI_R_CK- 1 IHDMI@ 2 +5VL @ TYCO_1939864-1_19P
    3 R618 0_0402_5% R315 715_0402_1% 3
    2

    HDMI_HPD
    L86 H@ +5VS C851 2
    1 2 R315 HDMI@ R304 HDMI@ 0.1U_0402_16V4Z
    1 2

    2
    499_0402_1% 499_0402_1% H@ H@ R628 2 C850

    5
    1
    Q136B 100K_0402_5% 0.1U_0402_16V4Z
    2N7002DW-7-F_SOT363-6 1 H@ H@
    4 3

    P
    OE#
    4 3 HDMI_R_D0- 1 IHDMI@ 2 3 4 2 A Y 4 HDMI_HPD_R
    WCM-2012-900T_0805 R304 715_0402_1% 1

    1
    G
    HDMI_TX0+ 1 @ 2 HDMI_R_D0+ HDMI_R_D0+ 1 IHDMI@ 2 U39
    R619 0_0402_5% R172 715_0402_1% SN74AHCT1G125GW_SOT353-5
    5

    3
    H@
    +5VS
    R297 HDMI@ R172 HDMI@ H@
    HDMI_TX1- 1 @ 2 HDMI_R_D1- 499_0402_1% 499_0402_1% +3VS +HDMI_5V_OUT
    R620 0_0402_5% Q137A
    2N7002DW-7-F_SOT363-6 R210 HDMI@
    L87 H@ HDMI_R_D1- 1 IHDMI@ 2 6 1 2K_0402_1%
    1 2 R297 715_0402_1% R236 HDMI@
    1 2

    2
    HDMI_R_D1+ 1 IHDMI@ 2 +3VS 2K_0402_1%
    R173 715_0402_1% R176 R209 IHDMI@ IHDMI@
    2

    4 3 4.7K_0402_5% 4.7K_0402_5% R210 R236


    4 3 IHDMI@ IHDMI@ H@ 6.8K_0402_5% 6.8K_0402_5%
    +5VS

    2
    G
    WCM-2012-900T_0805 R173 HDMI@ R141 HDMI@ 2 Q139

    1
    HDMI_TX1+ 1 @ 2 HDMI_R_D1+ 499_0402_1% 499_0402_1% H@ 2N7002_SOT23-3
    R621 0_0402_5% Q137B 1 IHDMI@ 2 3 1 HDMI_SDATA
    2N7002DW-7-F_SOT363-6 <11> HDMIDAT_UMA R298 0_0402_5%

    D
    HDMI_R_D2+ 1 IHDMI@ 2 3 4 +3VS
    R141 715_0402_1% 1 HDMI@ 2
    HDMI_TX2- @ HDMI_R_D2- HDMI_R_D2- 1 IHDMI@ 2 <19> HDMIDAT_VGA R299 0_0402_5% H@
    1 2

    2
    G
    R623 0_0402_5% R139 715_0402_1% Q140
    5

    2N7002_SOT23-3
    4 L88 H@ 4
    +5VS <11> HDMICLK_UMA 1 IHDMI@ 2 3 1 HDMI_SCLK
    R301 0_0402_5%

    D
    1 1 2 2

    R139 HDMI@ 1 HDMI@ 2


    499_0402_1% <19> HDMICLK_VGA R302 0_0402_5%
    4 4 3 3

    WCM-2012-900T_0805
    HDMI_TX2+ 1 @ 2 HDMI_R_D2+
    R624 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 18 of 45
    A B C D E
    5 4 3 2 1

    1 1 2 2
    PCIE_MTX_C_GRX_N0 3 4 PCIE_GTX_C_MRX_N0 PCIE_MTX_C_GRX_P[0..15]
    PCIE_MTX_C_GRX_P0 3 4 PCIE_GTX_C_MRX_P0 PCIE_MTX_C_GRX_P[0..15] <10>
    5 5 6 6
    7 8 PCIE_MTX_C_GRX_N[0..15]
    PCIE_MTX_C_GRX_N1 7 8 PCIE_GTX_C_MRX_N1 PCIE_MTX_C_GRX_N[0..15] <10>
    9 9 10 10
    PCIE_MTX_C_GRX_P1 11 12 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P[0..15]
    11 12 PCIE_GTX_C_MRX_P[0..15] <10>
    13 13 14 14
    PCIE_MTX_C_GRX_N2 15 16 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N[0..15]
    15 16 PCIE_GTX_C_MRX_N[0..15] <10>
    PCIE_MTX_C_GRX_P2 17 18 PCIE_GTX_C_MRX_P2
    17 18
    19 19 20 20
    D PCIE_MTX_C_GRX_P3 PCIE_GTX_C_MRX_N3 D
    21 21 22 22
    PCIE_MTX_C_GRX_N3 23 24 PCIE_GTX_C_MRX_P3
    23 24
    25 25 26 26
    PCIE_MTX_C_GRX_P4 27 28 PCIE_GTX_C_MRX_N4
    PCIE_MTX_C_GRX_N4 27 28 PCIE_GTX_C_MRX_P4
    29 29 30 30
    31 31 32 32
    PCIE_MTX_C_GRX_P5 33 34 PCIE_GTX_C_MRX_N5
    PCIE_MTX_C_GRX_N5 33 34 PCIE_GTX_C_MRX_P5
    35 35 36 36
    37 37 38 38
    PCIE_MTX_C_GRX_N6 39 40 PCIE_GTX_C_MRX_N6
    PCIE_MTX_C_GRX_P6 39 40 PCIE_GTX_C_MRX_P6
    41 41 42 42
    43 43 44 44
    PCIE_MTX_C_GRX_N7 45 46 PCIE_GTX_C_MRX_N7
    PCIE_MTX_C_GRX_P7 45 46 PCIE_GTX_C_MRX_P7
    47 47 48 48
    49 49 50 50
    PCIE_MTX_C_GRX_P8 51 52 PCIE_GTX_C_MRX_N8
    PCIE_MTX_C_GRX_N8 51 52 PCIE_GTX_C_MRX_P8
    53 53 54 54
    55 55 56 56
    PCIE_MTX_C_GRX_P9 57 58 PCIE_GTX_C_MRX_N9 VGA_HDMI_TXD2+ R87 1 HDMI@ 2 0_0402_5% HDMI_TXD2+ <10,18>
    PCIE_MTX_C_GRX_N9 57 58 PCIE_GTX_C_MRX_P9 VGA_HDMI_TXD2- R91 1 HDMI@ 0_0402_5%
    59 59 60 60 2 HDMI_TXD2- <10,18>
    61 62 VGA_HDMI_TXD1+ R92 1 HDMI@ 2 0_0402_5% HDMI_TXD1+ <10,18>
    PCIE_MTX_C_GRX_P10 61 62 PCIE_GTX_C_MRX_N10 VGA_HDMI_TXD1- R93 1 HDMI@ 0_0402_5%
    63 63 64 64 2 HDMI_TXD1- <10,18>
    PCIE_MTX_C_GRX_N10 65 66 PCIE_GTX_C_MRX_P10
    65 66 VGA_HDMI_TXD0+ R94 1 HDMI@ 0_0402_5%
    67 67 68 68 2 HDMI_TXD0+ <10,18>
    PCIE_MTX_C_GRX_P11 69 70 PCIE_GTX_C_MRX_N11 VGA_HDMI_TXD0- R86 1 HDMI@ 2 0_0402_5% HDMI_TXD0- <10,18>
    PCIE_MTX_C_GRX_N11 69 70 PCIE_GTX_C_MRX_P11 VGA_HDMI_CLK+ R89 1 HDMI@ 0_0402_5%
    71 71 72 72 2 HDMI_CLK0+ <10,18>
    73 74 VGA_HDMI_CLK- R90 1 HDMI@ 2 0_0402_5% HDMI_CLK0- <10,18>
    PCIE_MTX_C_GRX_P12 73 74 PCIE_GTX_C_MRX_N12
    75 75 76 76
    PCIE_MTX_C_GRX_N12 77 78 PCIE_GTX_C_MRX_P12
    77 78
    79 79 80 80
    PCIE_MTX_C_GRX_P13 81 82 PCIE_GTX_C_MRX_N13
    PCIE_MTX_C_GRX_N13 81 82 PCIE_GTX_C_MRX_P13
    83 83 84 84
    C C
    85 85 86 86
    PCIE_MTX_C_GRX_N14 87 88 PCIE_GTX_C_MRX_N14
    PCIE_MTX_C_GRX_P14 87 88 PCIE_GTX_C_MRX_P14
    89 89 90 90
    91 91 92 92
    PCIE_MTX_C_GRX_P15 93 94 PCIE_GTX_C_MRX_N15
    PCIE_MTX_C_GRX_N15 93 94 PCIE_GTX_C_MRX_P15
    95 95 96 96
    97 97 98 98
    CLK_PCIE_VGA 99 100 LCD_TXOUT0+
    <15> CLK_PCIE_VGA 99 100 LCD_TXOUT0+ <17>
    CLK_PCIE_VGA# 101 102 LCD_TXOUT0-
    <15> CLK_PCIE_VGA# 101 102 LCD_TXOUT0- <17>
    103 103 104 104
    VGA_HDMI_TXD0+ 105 106 LCD_TXOUT1+
    105 106 LCD_TXOUT1+ <17>
    VGA_HDMI_TXD0- 107 108 LCD_TXOUT1-
    107 108 LCD_TXOUT1- <17>
    109 109 110 110
    VGA_HDMI_TXD1+ 111 112 LCD_TXOUT2+
    111 112 LCD_TXOUT2+ <17>
    VGA_HDMI_TXD1- 113 114 LCD_TXOUT2-
    113 114 LCD_TXOUT2- <17>
    115 115 116 116
    VGA_HDMI_TXD2+ 117 118 LCD_TXCLK+
    117 118 LCD_TXCLK+ <17>
    VGA_HDMI_TXD2- 119 120 LCD_TXCLK-
    119 120 LCD_TXCLK- <17>
    121 121 122 122
    VGA_HDMI_CLK+ 123 124 LCD_TZOUT0+
    123 124 LCD_TZOUT0+ <17>
    VGA_HDMI_CLK- 125 126 LCD_TZOUT0-
    125 126 LCD_TZOUT0- <17>
    127 127 128 128
    <18> HDMICLK_VGA HDMICLK_VGA 129 130 LCD_TZOUT1+
    129 130 LCD_TZOUT1+ <17>
    <18> HDMIDAT_VGA HDMIDAT_VGA 131 132 LCD_TZOUT1-
    131 132 LCD_TZOUT1- <17>
    <11,18> HPD HPD 133 134
    LCD_EDID_CLK 133 134 LCD_TZOUT2+
    <17> LCD_EDID_CLK 135 135 136 136 LCD_TZOUT2+ <17>
    <17> LCD_EDID_DATA LCD_EDID_DATA 137 138 LCD_TZOUT2-
    137 138 LCD_TZOUT2- <17>
    VGA_ENVDD 139 140
    <17> VGA_ENVDD 139 140
    VGA_CRT_CLK 141 142 LCD_TZCLK+
    <16> VGA_CRT_CLK 141 142 LCD_TZCLK+ <17>
    VGA_CRT_DATA 143 144 LCD_TZCLK-
    <16> VGA_CRT_DATA 143 144 LCD_TZCLK- <17>
    145 145 146 146
    147 148 27M_CLK 27M_CLK <15>
    B <16> VGA_CRT_R 147 148 B
    149 150 27M_SSC 27M_SSC <15>
    <16> VGA_CRT_G 149 150
    <16> VGA_CRT_B 151 151 152 152
    153 154 VGA_TV_LUMA
    153 154 VGA_TV_LUMA <16>
    155 156 VGA_TV_CRMA
    <16> VGA_CRT_HSYNC 155 156 VGA_TV_CRMA <16>
    <16> VGA_CRT_VSYNC 157 157 158 158
    159 160 PLT_RST# PLT_RST# <11,14,20,26,27,28,32,33>
    SUSP# 159 160 SMB_EC_CK2
    <27,29,33,35,40> SUSP# 161 161 162 162 SMB_EC_CK2 <6,33>
    163 164 SMB_EC_DA2
    163 164 SMB_EC_DA2 <6,33>
    +1.8VS 165 166 ENBKL
    165 166 ENBKL <11,33>
    167 167 168 168 +5VALW
    169 169 170 170
    171 171 172 172 +3VS
    173 173 174 174
    175 175 176 176
    177 177 178 178 +1.8VS
    179 179 180 180
    181 181 182 182
    183 183 184 184
    185 185 186 186
    187 187 188 188
    189 189 190 190 B+
    191 191 192 192
    193 193 194 194
    195 195 196 196
    197 197 198 198
    199 199 200 200
    201 201 202 202
    203 203 204 204
    205 205 206 206

    JAE_WB3F200VD1R1000~D
    JVGA@
    A A

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/4/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 19 of 45
    5 4 3 2 1
    A B C D E

    U15A

    NB_RST#_R N2
    SB700 P4
    A_RST# PCICLK0
    Part 1 of 5 PCICLK1 P3

    PCI CLKS
    C492 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
    1 <10> SB_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 <24> 1
    C493 1 2 0.1U_0402_16V7K SB_RX0N_C V22 P2
    <10> SB_RX0N PCIE_TX0N PCICLK3 PCI_CLK3 <24>
    C494 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4
    <10> SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 <24>
    C495 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
    <10> SB_RX1N PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 <24>
    C496 1 2 0.1U_0402_16V7K SB_RX2P_C U25
    <10> SB_RX2P PCIE_TX2P
    C497 1 2 0.1U_0402_16V7K SB_RX2N_C U24
    <10> SB_RX2N PCIE_TX2N
    C498 1 2 0.1U_0402_16V7K SB_RX3P_C T23
    <10> SB_RX3P PCIE_TX3P
    C499 1 2 0.1U_0402_16V7K SB_RX3N_C T22 N1
    <10> SB_RX3N PCIE_TX3N PCIRST#

    PCI EXPRESS INTERFACE


    <10> SB_TX0P U22 PCIE_RX0P
    <10> SB_TX0N U21 PCIE_RX0N AD0 U2
    <10> SB_TX1P U19 PCIE_RX1P AD1 P7
    <10> SB_TX1N V19 PCIE_RX1N AD2 V4
    <10> SB_TX2P R20 PCIE_RX2P AD3 T1
    <10> SB_TX2N R21 PCIE_RX2N AD4 V3
    <10> SB_TX3P R18 PCIE_RX3P AD5 U1
    <10> SB_TX3N R17 PCIE_RX3N AD6 V1
    AD7 V2
    R305 2 1 562_0402_1% T25 T2
    R306 PCIE_CALRP AD8
    +PCIE_VDDR 2 1 2.05K_0402_1% T24 PCIE_CALRN AD9 W1
    L53 T9
    +SB_PCIEVDD AD10
    +1.2V_HT 1 2 P24 PCIE_PVDD AD11 R6
    BLM18PG121SN1D_0603 1 R7
    C504 AD12
    P25 PCIE_PVSS AD13 R5
    AD14 U8
    +3V_SB 2.2U_0603_6.3V4Z U5
    C506 2 AD15
    AD16 Y7
    2 1 AD17 W8
    AD18 V9
    5

    @ 0.1U_0402_16V4Z U16 Close to SB Y8


    AD19
    2 AA8
    P

    B PLT_RST# AD20
    Y 4 PLT_RST# <11,14,19,26,27,28,32,33> AD21 Y4
    NB_RST#_R 1 Y3
    A AD22
    G

    2 NC7SZ08P5X_NL_SC70-5 PCI_AD23 2
    AD23 Y2 PCI_AD23 <24>
    AA2 PCI_AD24
    PCI_AD24 <24>
    3

    AD24 PCI_AD25
    AD25 AB4 PCI_AD25 <24>
    N25 AA1 PCI_AD26
    <15> CLK_SBSRC_BCLK PCIE_RCLKP/NB_LNK_CLKP AD26 PCI_AD26 <24>
    N24 AB3 PCI_AD27
    <15> CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27 PCI_AD27 <24>
    2 1 AB2 PCI_AD28
    AD28 PCI_AD28 <24>
    R312 @ 33_0402_5% K23 AC1 PAD T17
    NB_DISP_CLKP AD29 PAD T18
    K22 NB_DISP_CLKN AD30 AC2
    AD31 AD1
    M24 W2

    PCI INTERFACE
    NB_HT_CLKP CBE0#
    M25 NB_HT_CLKN CBE1# U7
    CBE2# AA7
    P17 CPU_HT_CLKP CBE3# Y1
    M18 CPU_HT_CLKN FRAME# AA6
    DEVSEL# W5
    M23 SLT_GFX_CLKP IRDY# AA5
    M22 SLT_GFX_CLKN TRDY# Y5
    PAR U6
    J19 GPP_CLK0P STOP# W6
    J18 GPP_CLK0N PERR# W4
    SERR# V7
    L20 GPP_CLK1P REQ0# AC3
    L19 GPP_CLK1N REQ1# AD4
    @ R314 20M_0402_5%
    @R314 AB7
    REQ2#
    1 2 M19 GPP_CLK2P REQ3#/GPIO70 AE6
    M20 AB6 PAD T15
    GPP_CLK2N REQ4#/GPIO71
    C643 GNT0# AD2

    CLOCK GENERATOR
    N22 GPP_CLK3P GNT1# AE4
    1 2 SB_32KHI P22 AD5
    GPP_CLK3N GNT2#
    GNT3#/GPIO72 AC6
    18P_0402_50V8J Y3 L18 AE5 PAD T16
    25M_48M_66M_OSC GNT4#/GPIO73
    1

    4 OUT NC 3 CLKRUN# AD6 CLKRUN# <33>


    3 R389 3
    LOCK# V5
    20M_0603_5% 1 2 J21
    IN NC 25M_X1 CLK_PCI_EC C501 1
    INTE#/GPIO33 AD3 1 2 2@ 100P_0402_25V8K
    32.768KHZ_12.5P_1TJS125BJ4A421P AC4 R303 @ 100_0402_5%
    C652
    2

    INTF#/GPIO34 CLK_PCI_SIO2 C503 1


    INTG#/GPIO35 AE2 1 2 2@ 100P_0402_25V8K
    1 2 SB_32KHO J20 AE3 R369 @ 100_0402_5%
    25M_X2 INTH#/GPIO36
    18P_0402_50V8J
    G22 CLK_PCI_EC1 R308 1 2 22_0402_5% CLK_PCI_EC
    LPCCLK0 CLK_PCI_EC <24,33>
    Close to SB E22 CLK_PCI_SIOC R310 1 2 22_0402_5%
    LPCCLK1 CLK_PCI_SIO2 <24,32>
    SB_32KHI A3 H24
    X1 LAD0 LPC_AD0 <32,33>
    LAD1 H23
    J25
    LPC_AD1 <32,33> EC & TPM &Debug
    LAD2 LPC_AD2 <32,33>
    J24
    RTC XTAL

    LAD3 LPC_AD3 <32,33>


    LPC

    SB_32KHO B3 H25
    X2 LFRAME# LPC_FRAME# <32,33>
    LDRQ0# H22
    LDRQ1#/GNT5#/GPIO68 AB8
    BMREQ#/REQ5#/GPIO65 AD7
    +3VS 2 1 H_PROCHOT# V15
    SERIRQ SIRQ <32,33>
    R319 10K_0402_5%
    CPU_LDT_REQ# F23
    <6,11> CPU_LDT_REQ# ALLOW_LDTSTP
    H_PROCHOT#
    <6> H_PROCHOT#
    H_PWRGD
    F24
    F22
    PROCHOT# RTCCLK C3
    C2
    RTC_CLK <24> STRAP PIN
    <6,43> H_PWRGD LDT_PG INTRUDER_ALERT#
    CPU

    <6,11> LDT_STOP# G25 LDT_STP# VBAT B2 +SB_VBAT


    G24 +SB_VBAT +RTCVCC
    <6> LDT_RST# LDT_RST# +RTCBATT
    RTC

    R316 R317
    D10
    120_0402_5% 120_0402_5%
    1 2 1 2 2 1 3
    218S7EALA11FG_BGA528_SB700 1 1 R184 1K_0402_5%

    0.1U_0402_16V4Z
    W=20mils 1

    2
    C509 C510 1
    4 SB700R3@ J1 C297 4
    2

    2
    2 2 @ JUMP_43X39
    1U_0402_6.3V4Z
    2 BAS40-04_SOT23-3

    1
    0.1U_0402_16V4Z
    +CHGRTC

    1
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 20 of 45
    A B C D E
    A B C D E

    +3V_SB
    +3VS

    2
    1 @ 2 CR_CPPE# R561
    R569 100K_0402_5% 1K_0402_5%

    Reserve for EMI request

    1
    1 @ 2 LAN_DSM#
    R571 100K_0402_5% EC_SWI#
    <27,33> EC_SWI# U15D
    1 2 C617 1 2 100P_0402_25V8K
    Part 4 of 5 R311 100_0402_5%
    1
    E1
    SB700 1
    PCI_PME#/GEVENT4#
    E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB <15>
    demo circuit LID use RI# H7 SLP_S2/GPM9#
    F5 G8 USB_RCOMP 1 2
    <33> SLP_S3# SLP_S3# USB_RCOMP
    G1 11.8K_0402_1% R323
    <33> SLP_S5# SLP_S5#

    USB MISC
    ACPI / WAKE UP EVENTS
    <33> PWRBTN_OUT# H2 PWR_BTN#
    <33,43> SB_PWRGD H1 PWR_GOOD
    +3VS 1 2 SUS_STAT# SUS_STAT# K3
    <11,14> SUS_STAT# SUS_STAT#
    R388 4.7K_0402_5% SB_TEST2 H5 E6
    SB_TEST1 TEST2 USB_FSD13P
    H4 TEST1 USB_FSD13N E7
    SB700 has internal PD SB_TEST0 H3 TEST0

    USB 1.1
    <33> GATEA20 Y15 GA20IN/GEVENT0# USB_FSD12P F7
    +3V_SB 1 2 SB_TEST2 W15 E8
    <33> KB_RST# KBRST#/GEVENT1# USB_FSD12N
    R320 @ 2.2K_0402_5% K4
    <33> EC_SCI# LPC_PME#/GEVENT3#
    1 2 SB_TEST1 K24 H11 USB20_P11
    <33> EC_SMI# LPC_SMI#/EXTEVNT1# USB_HSD11P USB20_P11 <27>
    R321 @ 2.2K_0402_5% F1 J10 USB20_N11 USB-11 New Card
    S3_STATE/GEVENT5# USB_HSD11N USB20_N11 <27>
    1 2 SB_TEST0 J2
    R322 @ 2.2K_0402_5% EC_SWI# SYS_RESET#/GPM7# USB20_P10
    H6 WAKE#/GEVENT8# USB_HSD10P E11 USB20_P10 <27>
    (28) CR_CPPE# CR_CPPE# F2 F11 USB20_N10 USB-10 GPS
    BLINK/GPM6# USB_HSD10N USB20_N10 <27>
    H_THERMTRIP# J6
    <6,33> H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
    W14 A11 USB20_P9
    <11> NB_PWRGD NB_PWRGD USB_HSD9P USB20_P9 <29>
    B11 USB20_N9 USB-9 Int Camera
    USB_HSD9N USB20_N9 <29>
    2 1 EC_RSMRST# <33> EC_RSMRST#
    EC_RSMRST# D3 RSMRST#
    R327 100K_0402_5% C10 USB20_P8
    USB_HSD8P USB20_P8 <27>
    D10 USB20_N8 Reserve
    USB_HSD8N USB20_N8 <27>
    AE18 G11 USB20_P7
    SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 <31>
    (28) CR_WAKE# AD18 H12 USB20_N7 USB-7 Finger Printer
    CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 <31>
    AA19 SMARTVOLT1/SATA_IS2#/GPIO4
    W17 E12 USB20_P6
    CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P USB20_P6 <31>
    V17 E14 USB20_N6 USB-6 Bluetooth
    CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USB20_N6 <31>
    W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
    2 2
    <29> SB_SPKR W21 C12

    USB 2.0
    SMB_CK_CLK0 SPKR/GPIO2 USB_HSD5P
    <8,9,15,27> SMB_CK_CLK0 AA18 SCL0/GPOC0# USB_HSD5N D12
    <8,9,15,27> SMB_CK_DAT0 SMB_CK_DAT0 W18
    +3VS SMB_CK_CLK1 SDA0/GPOC1# USB20_P4
    <27> SMB_CK_CLK1 K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 <31>
    SMB_CK_DAT1 K2 A12 USB20_N4 USB-4 Left side
    <27> SMB_CK_DAT1 SDA1/GPOC3# USB_HSD4N USB20_N4 <31>
    AA20 DDC1_SCL/GPIO9

    GPIO
    R328 1 2 1.2K_0402_5% SMB_CK_CLK0 Y18 G12
    DDC1_SDA/GPIO8 USB_HSD3P
    C1 LLB#/GPIO66 USB_HSD3N G14
    R329 1 2 1.2K_0402_5% SMB_CK_DAT0 +3VS 1 2 Y19
    R400 @ 4.7K_0402_5% SMARTVOLT2/SHUTDOWN#/GPIO5 USB20_P2
    G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USB20_P2 <31>
    +3V_SB USB20_N2
    USB_HSD2N H15 USB20_N2 <31> USB-2 eSATA
    A13 USB20_P1
    USB_HSD1P USB20_P1 <31>
    B13 USB20_N1 USB-1 Right side
    USB_HSD1N USB20_N1 <31>
    R331 1 2 2.2K_0402_5% SMB_CK_CLK1
    B14 USB20_P0
    USB_HSD0P USB20_P0 <31>
    R332 1 2 2.2K_0402_5% SMB_CK_DAT1 B9 A14 USB20_N0 USB-0 Right side
    <33> EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 <31>
    <27> EXP_CPPE# B8 USB_OC5#/IR_TX0/GPM5#
    A8 A18

    USB OC
    <31> USB_OC#2 USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
    <31> USB_OC#0 A9 USB_OC3#/IR_RX1/GPM3# IMC_GPIO9 B18
    E5 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21
    F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21
    R333 33_0402_5% 1 2 HDA_BITCLK_R E4 F19
    <29> HDA_BITCLK_CODEC USB_OC0#/GPM0# SDA2/IMC_GPIO12
    R334 33_0402_5% 1 2 HDA_BITCLK E20
    <32> HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13
    R335 33_0402_5% 1 2 M1 E21
    <32> HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14
    R336 33_0402_5% 1 2 HDA_SDOUT M2 E19
    <29> HDA_SDOUT_CODEC AZ_SDOUT IMC_PWM1/IMC_GPIO15
    HDA_SDIN0 J7 D19 STRAP PIN
    <29> HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 <24>
    HDA_SDIN1
    <32> HDA_SDIN1 J8
    L8
    AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 E18 GPIO17 <24> STRAP PIN

    HD AUDIO
    AZ_SDIN2/GPIO44
    M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
    R337 33_0402_5% 1 2 HDA_SYNC L6 G21
    <32> HDA_SYNC_MDC AZ_SYNC IMC_GPIO19
    R338 33_0402_5% 1 2 M4 D25
    3 <29> HDA_SYNC_CODEC AZ_RST# IMC_GPIO20 3
    L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
    R339 33_0402_5% HDARST#

    INTEGRATED uC
    <29> HDA_RST#_CODEC 1 2 IMC_GPIO22 C25
    R340 33_0402_5% 1 2 C24
    <32> HDA_RST#_MDC IMC_GPIO23
    IMC_GPIO24 B25
    IMC_GPIO25 C23
    STRAP PIN <24> HDARST#
    B24
    LAN_DSM# IMC_GPIO26
    (26) LAN_DSM# IMC_GPIO27 B23
    IMC_GPIO28 A23
    IMC_GPIO29 C22
    IMC_GPIO30 A22
    IMC_GPIO31 B22
    IMC_GPIO32 B21
    IMC_GPIO33 A21
    reserve for EMI request H19 IMC_GPIO0 IMC_GPIO34 D20
    +3VS 1 2 H20 IMC_GPIO1 IMC_GPIO35 C20
    R625 0_0603_5%
    INTEGRATED uC

    H21 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 A20


    +1.5VS 1 2 F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20
    R626 0_0603_5% R629 B19
    @ 10K_0402_5% IMC_GPIO38
    D22 IMC_GPIO4 IMC_GPIO39 A19
    U11 E24 D18
    HDA_BITCLK IMC_GPIO5 IMC_GPIO40
    1 CLKIN VDD 8 1 2 E25 IMC_GPIO6 IMC_GPIO41 C18
    R219 C275 0.1U_0402_16V4Z D23
    10K_0402_5% IMC_GPIO7
    2 PD#/OE SSEXTR 7
    @
    3 FS DLY_CTRL 6
    2 218S7EALA11FG_BGA528_SB700
    4 GND ModOUT 5HDA_BITCLK_R C670 R627
    1.5M_0402_5% SB700R3@
    R220 0.1U_0402_16V4Z
    10K_0402_5% PCS3P73Z11BXG-08-CR_TDFN8_2X2 @ 1

    4 4
    HDA_BITCLK 2 1 HDA_BITCLK_R
    0_0402_5% @ R204

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 21 of 45
    A B C D E
    A B C D E

    1 1

    U15B

    C512 1 2 0.01U_0402_25V7K SATA_STX_DRX_P0 AD9 SB700 AA24


    <25> SATA_TXP0 SATA_TX0P IDE_IORDY
    C513 1 2 0.01U_0402_25V7K SATA_STX_DRX_N0 AE9 Part 2 of 5 AA25
    <25> SATA_TXN0 SATA_TX0N IDE_IRQ
    IDE_A0 Y22
    HDD1 AB10 AB23 @
    <25> SATA_RXN0_C SATA_RX0N IDE_A1
    <25> SATA_RXP0_C AC10 SATA_RX0P IDE_A2 Y23 +3V_SB 2 1
    AB24 D30 RB751V_SOD323
    C514 SATA_STX_DRX_P1 AE10 IDE_DACK#
    <25> SATA_TXP1 1HDD2@
    2 0.01U_0402_25V7K SATA_TX1P IDE_DRQ AD25
    C515 1HDD2@
    2 0.01U_0402_25V7K SATA_STX_DRX_N1 AD10 AC25
    2 <25> SATA_TXN1 SATA_TX1N IDE_IOR# R558 2
    AC24 C667 0.1U_0402_16V4Z
    IDE_IOW#
    HDD2 <25> SATA_RXN1_C AD11 SATA_RX1N IDE_CS1# Y25 +3V_SB 2 1 1 2
    SBROM@
    <25> SATA_RXP1_C AE11 SATA_RX1P IDE_CS3# Y24
    0_0603_5%
    C520 1 2 0.01U_0402_25V7K SATA_STX_DRX_P2 AB12 AD24 SBROM@
    <31> SATA_TXP2 SATA_TX2P IDE_D0/GPIO15
    C521 1 2 0.01U_0402_25V7K SATA_STX_DRX_N2 AC12 AD23 +SB_SPI_VCC
    <31> SATA_TXN2 SATA_TX2N IDE_D1/GPIO16

    ATA 66/100/133
    IDE_D2/GPIO17 AE22
    eSATA <31> SATA_RXN2_C AE12 SATA_RX2N IDE_D3/GPIO18 AC22

    2
    AD12 AD21
    <31> SATA_RXP2_C SATA_RX2P IDE_D4/GPIO19
    IDE_D5/GPIO20 AE20 R551 R552 R553 8Mb SPI ROM
    C518 1 2 0.01U_0402_25V7K SATA_STX_DRX_P3 AD13 AB20 1K_0402_5% 10K_0402_5%
    <25> SATA_TXP3 SATA_TX3P IDE_D6/GPIO21
    C519 1 2 0.01U_0402_25V7K SATA_STX_DRX_N3 AE13 AD19 SBROM@ SBROM@
    <25> SATA_TXN3 SATA_TX3N IDE_D7/GPIO22
    AE19

    SERIAL ATA

    1
    IDE_D8/GPIO23 U23
    ODD <25> SATA_RXN3_C AB14 SATA_RX3N IDE_D9/GPIO24 AC20
    10K_0402_5%
    <25> SATA_RXP3_C AC14 SATA_RX3P IDE_D10/GPIO25 AD20 8 VCC VSS 4
    AE21 If use, Un-pop R547 SBROM@
    IDE_D11/GPIO26
    AE14 SATA_TX4P IDE_D12/GPIO27 AB22 3 W
    AD14 SATA_TX4N IDE_D13/GPIO28 AD22
    AE23 SB_HOLD# 1 @ 2 7
    IDE_D14/GPIO29 R547 0_0402_5% HOLD
    AD15 SATA_RX4N IDE_D15/GPIO30 AC23
    AE15 SB_SPICS# 1
    SATA_RX4P S
    AB16 SB_SPICLK 6
    SATA_TX5P C
    AC16 SATA_TX5N
    G6 SB_SI_SPI_SO SB_SO_SPI_SI 5 2 SB_SI_SPI_SO
    SPI_DI/GPIO12 SB_SO_SPI_SI D Q
    AE16 SATA_RX5N SPI_DO/GPIO11 D2
    AD16 D1 SB_SPICLK SST25VF080B-50-4C-S2AF_SO8
    SATA_RX5P SPI_CLK/GPIO47 SB_HOLD# SBROM@
    F4

    SPI ROM
    SATA_CAL SPI_HOLD#/GPIO31 SB_SPICS#
    2 1 V12 SATA_CAL SPI_CS1#/GPIO32 F3
    R342 1K_0402_1%
    SATA_X1 Y12 U15
    SATA_X1 LAN_RST#/GPIO13
    ROM_RST#/GPIO14 J1
    3 SATA_X2 AA12 +3VS 3
    SATA_X2
    +3VS R343 1 2 10K_0402_5% FANOUT0/GPIO3 M8
    <34> SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5
    +1.2V_HT M7 1 @ 2 LAN_ISOLATE#
    FANOUT2/GPIO49 CAM_PWR <29>
    L54 R570 100K_0402_5%
    2 1 +PLLVDD_SATA AA11 P5 FM_I2CCLK
    PLLVDD_SATA FANIN0/GPIO50 FM_I2CCLK <32>
    BLM18PG121SN1D_0603 P8 FM_I2CDAT
    FANIN1/GPIO51 FM_I2CDAT <32>
    SATA PWR

    2 2 W12 XTLVDD_SATA FANIN2/GPIO52 R8 SB_INT_FLASH_SEL <32>


    C522 C523 C6
    1U_0402_6.3V4Z TEMP_COMM LAN_ISOLATE#
    1U_0402_6.3V4Z TEMPIN0/GPIO61 B6 LAN_ISOLATE# (26)
    1 1
    TEMPIN1/GPIO62 A6
    A5 SPK_SEL
    TEMPIN2/GPIO63 SPK_SEL <29>
    B5
    HW MONITOR

    TEMPIN3/TALERT#/GPIO64 EC_THERM# <33> CH751H-40PT_SOD323-2


    +3VS A4 2 1
    VIN0/GPIO53 ACIN <33,34,36>
    L55 B4 BT_DET#
    VIN1/GPIO54 BT_DET# <31> D41
    2 1 +XTLVDD_SATA C4 CIR_DET
    BLM18PG121SN1D_0603 VIN2/GPIO55
    2 1 VIN3/GPIO56 D4 1 2 +3V_SB
    D5 R562 150K_0402_5%
    C524 C625 VIN4/GPIO57
    VIN5/GPIO58 D6
    1U_0402_6.3V4Z @ 0.1U_0402_16V4Z A7
    1 2 VIN6/GPIO59
    VIN7/GPIO60 B7
    +3V_SB
    L56 +3VS
    F6 +SB_AVDD 2 1
    AVDD BLM18PG121SN1D_0603
    1 1
    10P_0402_50V8J 2 1 C516 SATA_X1 G7 CIR_DET 2 CIR@ 1
    AVSS C526 R554 1K_0402_5%
    1

    2.2U_0603_6.3V4Z 2 1
    Y4 R341 2 2 R557 100K_0402_5%
    218S7EALA11FG_BGA528_SB700
    4 25MHZ_20P SB700R3@ C525 4
    10M_0402_5% 0.1U_0402_16V4Z
    2

    10P_0402_50V8J 2 1 C517 SATA_X2

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 22 of 45
    A B C D E
    A B C D E

    U15C U15E

    SB700 L15 +1.2V_HT_R


    +3VS L9
    M9
    VDDQ_1
    Part 3 of 5
    VDD_1
    M12
    1
    R593
    2
    0_0805_5%
    +1.2V_HT SB700 A2
    VDDQ_2 VDD_2 VSS_1
    2 1 T15 VDDQ_3 VDD_3 M14 1 2 VSS_2 A25
    C528 22U_0805_6.3V6M U9 N13 10U_0805_6.3V6M C529 B1

    CORE S0
    1 C531 1U_0402_6.3V4Z VDDQ_4 VDD_4 1U_0402_6.3V4Z C532 VSS_3 1
    1 2 U16 VDDQ_5 VDD_5 P12 2 1 VSS_4 D7
    C530 1 2 1U_0402_6.3V4Z U17 P14 1U_0402_6.3V4Z 2 1 C534 T10 F20
    VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5

    PCI/GPIO I/O
    C533 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C538 U10 G19
    C536 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C537 AVSS_SATA_2 VSS_6
    1 2 W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
    C535 1 2 1U_0402_6.3V4Z Y6 T16 0.1U_0402_16V4Z 2 1 C527 U12 K9
    C539 0.1U_0402_16V4Z VDDQ_9 VDD_9 0.1U_0402_16V4Z C540 AVSS_SATA_4 VSS_8
    1 2 AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
    C541 1 2 0.1U_0402_16V4Z AB5 V14 K16
    C542 0.1U_0402_16V4Z VDDQ_11 AVSS_SATA_6 VSS_10
    1 2 AB21 VDDQ_12 W9 AVSS_SATA_7 VSS_11 L4
    Y9 AVSS_SATA_8 VSS_12 L7
    Y11 AVSS_SATA_9 VSS_13 L10
    No IDE device unmount CAP Y14 AVSS_SATA_10 VSS_14 L11
    Y17 AVSS_SATA_11 VSS_15 L12
    +3VS Y20 L21 +1.2V_HT +1.2V_HT AA9 L14
    VDD33_18_1 CKVDD_1.2V_1 AVSS_SATA_12 VSS_16
    AA21 VDD33_18_2 CKVDD_1.2V_2 L22 AB9 AVSS_SATA_13 VSS_17 L16
    AA22 L24 AB11 M6

    IDE/FLSH I/O

    CLKGEN I/O
    VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18
    AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB13 AVSS_SATA_15 VSS_19 M10
    AB15 AVSS_SATA_16 VSS_20 M11
    AB17 AVSS_SATA_17 VSS_21 M13
    AC8 AVSS_SATA_18 VSS_22 M15
    AD8 AVSS_SATA_19 VSS_23 N4
    AE8 AVSS_SATA_20 VSS_24 N12
    VSS_25 N14
    +PCIE_VDDR P6
    L61 POWER VSS_26
    VSS_27 P9
    +1.2V_HT 2 1 VSS_28 P10
    0_0805_5% A15 P11
    AVSS_USB_1 VSS_29
    P18 PCIE_VDDR_1 B15 AVSS_USB_2 VSS_30 P13
    2 1 P19 +3V_SB C14 P15
    C552 4.7U_0805_10V6K PCIE_VDDR_2 AVSS_USB_3 VSS_31
    P20 PCIE_VDDR_3 D8 AVSS_USB_4 VSS_32 R1
    C553 1 2@ 1U_0402_6.3V4Z P21 A17 +S5_3V 1 2 D9 R2

    A-LINK I/O
    C555 PCIE_VDDR_4 S5_3.3V_1 AVSS_USB_5 VSS_33
    1 2 1U_0402_6.3V4Z R22 PCIE_VDDR_5 S5_3.3V_2 A24 R564 0_0805_5% D11 AVSS_USB_6 VSS_34 R4
    C554 1 2 1U_0402_6.3V4Z R24 B17 1 2 D13 R9
    PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35

    GROUND
    2 C558 2
    1 2 1U_0402_6.3V4Z R25 PCIE_VDDR_7 S5_3.3V_4 J4 22U_0805_6.3V6M @ C556 D14 AVSS_USB_8 VSS_36 R10

    3.3V_S5 I/O
    C557 1 2 0.1U_0402_16V4Z J5 2.2U_0603_6.3V4Z 2 1 C559 D15 R12
    C560 S5_3.3V_5 AVSS_USB_9 VSS_37
    1 2 0.1U_0402_16V4Z S5_3.3V_6 L1 2.2U_0603_6.3V4Z 2 1 C561 E15 AVSS_USB_10 VSS_38 R14
    L2 1U_0402_6.3V4Z 2 1 C562 F12 T11
    +1.2V_SATA S5_3.3V_7 0.1U_0402_16V4Z 2 C563 AVSS_USB_11 VSS_39
    1 F14 AVSS_USB_12 VSS_40 T12
    L63 0.1U_0402_16V4Z 2 1 C564 G9 T14
    0.1U_0402_16V4Z 2 C565 AVSS_USB_13 VSS_41
    +1.2V_HT 2 1 AA14 AVDD_SATA_1 1 H9 AVSS_USB_14 VSS_42 U4
    0_0805_5% AB18 +1.2VALW H17 U14
    AVDD_SATA_4 AVSS_USB_15 VSS_43
    AA15 AVDD_SATA_2 J9 AVSS_USB_16 VSS_44 V6
    2 1 AA17 G2 +S5_1.2V L64 0_0603_5% J11 Y21

    CORE S5
    AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

    SATA I/O
    C566 22U_0805_6.3V6M AC18 G4 J12 AB1
    C567 1U_0402_6.3V4Z AVDD_SATA_5 S5_1.2V_2 +1.2VALW 1U_0402_6.3V4Z C569 AVSS_USB_18 VSS_46
    1 2 AD17 AVDD_SATA_6 2 1 J14 AVSS_USB_19 VSS_47 AB19
    C568 1 2 1U_0402_6.3V4Z AE17 1U_0402_6.3V4Z 2 1 C570 J15 AB25
    C571 0.1U_0402_16V4Z AVDD_SATA_7 +1.2_USB L65 0_0603_5% AVSS_USB_20 VSS_48
    1 2 K10 AVSS_USB_21 VSS_49 AE1
    C572 1 2 0.1U_0402_16V4Z A10 K12 AE24
    USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
    USB_PHY_1.2V_2 B10 1 2 K14 AVSS_USB_23
    10U_0805_10V4Z @ C573 K15
    1U_0402_6.3V4Z 2 C574 AVSS_USB_24
    1 PCIE_CK_VSS_9 P23
    0.1U_0402_16V4Z 2 1 C575 R16
    PCIE_CK_VSS_10
    PCIE_CK_VSS_11 R19
    +AVDD_USB T17
    L66 PCIE_CK_VSS_12
    PCIE_CK_VSS_13 U18
    +3V_SB 2 1 A16 AE7 +V5_VREF 1K_0402_5% 2 1 R346 +5VS H18 U20
    0_0805_5% AVDDTX_0 V5_VREF D14 PCIE_CK_VSS_1 PCIE_CK_VSS_14
    B16 AVDDTX_1 2 2 J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18
    C16 J16 +AVDDCK_3.3V 1 2 +3VS J22 V20
    C576 10U_0805_10V4Z AVDDTX_2 AVDDCK_3.3V C578 C579 PCIE_CK_VSS_3 PCIE_CK_VSS_16
    1 2 D16 AVDDTX_3 K25 PCIE_CK_VSS_4 PCIE_CK_VSS_17 V21
    C577 1 2 10U_0805_10V4Z D17 K17 +AVDDCK_1.2V 0.1U_0402_16V4Z 1U_0603_10V4Z CH751H-40PT_SOD323-2 M16 W19
    PLL

    C580 1U_0402_6.3V4Z AVDDTX_4 AVDDCK_1.2V 1 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18


    1 2 E17 AVDDTX_5 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
    USB I/O

    C581 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24


    C583 0.1U_0402_16V4Z AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
    1 2 F17 AVDDRX_1 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
    C582 1 2 0.1U_0402_16V4Z F18 L67
    C584 0.1U_0402_16V4Z AVDDRX_2
    1 2 G15 AVDDRX_3 2 1 +3V_SB F9 AVSSC AVSSCK L17
    3 0_0603_5% 3
    G17 AVDDRX_4 Part 5 of 5
    G18 AVDDRX_5 2.2U_0603_6.3V4Z 2 1 C585 218S7EALA11FG_BGA528_SB700

    0.1U_0402_16V4Z 2 1 C586
    218S7EALA11FG_BGA528_SB700 SB700R3@

    SB700R3@

    L68
    +AVDDCK_1.2V 2 1 +1.2V_HT
    0_0603_5%

    2.2U_0603_6.3V4Z 2 1 C587

    0.1U_0402_16V4Z 2 1 C588

    L69
    +AVDDCK_3.3V 2 1 +3VS
    0_0603_5%

    2.2U_0603_6.3V4Z 2 1 C589

    0.1U_0402_16V4Z 2 1 C590

    4 4

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 23 of 45
    A B C D E
    A B C D E

    REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

    PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 LPC_CLK0 LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16

    PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
    HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
    H,H = Reserved
    ENABLED STRAPS
    1 DEFAULT 1
    H,L = SPI ROM
    EXT. RTC
    PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
    LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default)
    DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
    DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

    +3VS +3VS +3VS +3VS +3V_SB +3V_SB +3V_SB +3V_SB +3V_SB +3V_SB

    1
    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    2.2K_0402_5%

    2.2K_0402_5%
    R355

    R356
    R347

    R348

    R349

    R350

    R351

    R352

    R353

    R354
    2

    2
    @

    @
    @ @ @ @ @ @ @
    <20> PCI_CLK2
    <20> PCI_CLK3 SI2: mount 2.2K
    <20> PCI_CLK4
    <20> PCI_CLK5
    <20,33> CLK_PCI_EC
    <20,32> CLK_PCI_SIO2
    <20> RTC_CLK
    <21> HDARST#
    2 <21> GPIO17 2
    <21> GPIO16

    1
    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%

    10K_0402_5%
    2.2K_0402_5%

    2.2K_0402_5%

    2.2K_0402_5%
    R363

    R365

    R366
    R357

    R358

    R359

    R360

    R361

    R362

    R364
    2

    2
    @ @ @ @

    DEBUG STRAPS Need to confirm if SB SPI ROM will mount


    SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

    PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

    USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
    PULL LONG PLL BCLK PLL PCIE STRAPS
    HIGH RESET
    3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3

    PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM


    LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
    RESET BCLK

    <20> PCI_AD28
    <20> PCI_AD27
    <20> PCI_AD26
    <20> PCI_AD25
    <20> PCI_AD24
    <20> PCI_AD23
    1

    1
    2.2K_0402_5%

    2.2K_0402_5%

    2.2K_0402_5%

    2.2K_0402_5%

    2.2K_0402_5%

    2.2K_0402_5%
    R373

    R374

    R375

    R376

    R377

    R378
    2

    2
    @ @ @ @ @ @

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 24 of 45
    A B C D E
    A B C D E

    SATA HDD1 Conn. SATA HDD2 Conn.


    +5VS +5VS
    Place closely JHDD0 SATA CONN. Place closely JHDD1 SATA CONN.
    1.2A 1.2A
    1 1 1 1 1 1 1 1
    C387 C388 C389 C390 C392 C393 C394 C396
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2 2 HDD2@ 2 HDD2@ 2 HDD2@ 2 HDD2@

    1 1
    SSD HDD need 400mA for 3V(PHISON)
    SSD HDD need 400mA for 3V(PHISON) +3VS
    +3VS
    +3VS rail reserve for SSD
    +3VS rail reserve for SSD
    1 1 1 1
    1 1 1 1 C194 C195 C196 C197
    C336 C337 C338 C339
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 SSD@ 2 2 2
    SSD@ SSD@ SSD@
    2 SSD@ 2 2 2
    SSD@ SSD@ SSD@

    D8
    2 D11
    1 2
    JHDD0 3 1
    3
    @ PJDLC05_SOT23-3 JHDD2
    1 @ PJDLC05_SOT23-3
    GND SATA_TXP0
    A+ 2 SATA_TXP0 <22> GND 1
    3 SATA_TXN0 2 SATA_TXP1
    A- SATA_TXN0 <22> A+ SATA_TXP1 <22>
    4 3 SATA_TXN1
    GND A- SATA_TXN1 <22>
    5 SATA_IRX_DTX_N0 C410 1 2 0.01U_0402_25V7K 4 HDD2@
    B- SATA_RXN0_C <22> GND
    6 SATA_IRX_DTX_P0 C412 1 2 0.01U_0402_25V7K 5 SATA_IRX_DTX_N1 C411 1 2 0.01U_0402_25V7K
    B+ SATA_RXP0_C <22> B- SATA_RXN1_C <22>
    7 6 SATA_IRX_DTX_P1 C413 1 2 0.01U_0402_25V7K
    GND B+ SATA_RXP1_C <22>
    D7 7
    2 GND HDD2@ D9 2
    2
    V33 8 +3VS 1 2
    V33 9 3 1
    V33 10 VCC3.3 8 +3VS 3
    11 @ PJDLC05_SOT23-3 9
    GND VCC3.3 @ PJDLC05_SOT23-3
    GND 12 VCC3.3 10
    GND 13 GND 11
    V5 14 +5VS Reserve for EMI request GND 12
    V5 15 GND 13 Reserve for EMI request
    V5 16 VCC5 14 +5VS
    GND 17 VCC5 15
    Reserved 18 VCC5 16
    GND 19 GND 17
    V12 20 RESERVED 18
    24 GND V12 21 GND 19
    23 GND V12 22 VCC12 20
    VCC12 21
    VCC12 22
    OCTEK_SAT-22SO1G_RV
    @
    SUYIN_127043FB022G208ZR_RV
    @

    3 SATA ODD Conn 3

    +5VS
    1.1A

    1 1 1 1 1
    C414 C415 C416
    @ C417 C418
    10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2 2

    Place component's closely ODD CONN.

    JODD

    GND 1
    2 SATA_TXP3
    A+ SATA_TXP3 <22>
    3 SATA_TXN3
    A- SATA_TXN3 <22>
    GND 4
    5 SATA_IRX_DTX_N3 C424 1 2 0.01U_0402_25V7K
    B- SATA_RXN3_C <22>
    6 SATA_IRX_DTX_P3 C425 1 2 0.01U_0402_25V7K
    B+ SATA_RXP3_C <22>
    GND 7
    4 4

    DP 8
    +5V 9 +5VS
    +5V 10
    MD 11
    15 GND GND 12
    14 13 /
    GND GND Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    SANTA_206401-1_RV
    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 25 of 45
    A B C D E
    A B C D E

    1 2 +3V_LAN
    +3V_LAN
    U20 RL1 3.6K_0402_5%
    @ UL2 Close to Pin16,37,46,53
    <10> PCIE_PTX_C_IRX_P3 CL1 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 29 45 LAN_DO 4 5 2
    HSOP EEDO LAN_DI DO GND CL3
    EEDI/AUX 47 3 DI ORG 6
    1 1
    <10> PCIE_PTX_C_IRX_N3 CL2 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 30 HSON EESK 48 LAN_SK 2 SK NC 7 1 2
    44 LAN_CS 1 8 @ +3V_LAN 0.1U_0402_16V4Z CL4
    EECS CS VCC 1
    0.1U_0402_16V4Z
    <10> PCIE_ITX_C_PRX_P3 23 HSIP 1 2
    CAT93C46VI-GT3_SO8 0.1U_0402_16V4Z CL5
    <10> PCIE_ITX_C_PRX_N3 24 HSIN 1 2
    54 0.1U_0402_16V4Z CL6
    LED3
    LED2 55 1 2
    33 56 LAN_LINK# 0.1U_0402_16V4Z CL7
    <15> CLKREQ_LAN CLKREQB LED1
    57 LAN_ACTIVITY# 1 2
    LED0 RL2 0_0603_5%
    <15> CLK_PCIE_LAN 26 REFCLK_P 8102E@ +LAN_AVDD12
    27 3 LAN_MDI0+
    <15> CLK_PCIE_LAN# REFCLK_N MDIP0
    4 LAN_MDI0- LL1
    MDIN0 LAN_MDI1+ +LAN_CTRL18
    <11,14,19,20,27,28,32,33> PLT_RST# 20 PERSTB MDIP1 6 1 2
    7 LAN_MDI1- 4.7UH_1008HC-472EJFS-A_5%_1008
    MDIN1 LAN_MDI2+ 8111C@
    MDIP2 9 1 2
    +LAN_CTRL18 1 10 LAN_MDI2- Layout Note: L18 must be +LAN_DVDD12
    SROUT12 MDIN2 LAN_MDI3+ within 500mil to Pin1 CL8 CL9
    MDIP3 12
    +LAN_DVDD12 5 13 LAN_MDI3- C496,C497 must be within 22U_0805_6.3V6M 0.1U_0402_16V4Z
    FB12 MDIN3 500mil to L18 8111C@ 2 1
    1
    CL11 +3V_LAN RL4 62 ENSR 1 2
    0.01U_0402_25V4Z 0_0402_5% 8111C@ 21 +LAN_DVDD12 0.1U_0402_16V4Z CL10
    @ DVDD12
    1 2 64 32 1 2
    2 RL5 2.49K_0402_1% RSET DVDD12
    38 0.1U_0402_16V4Z CL12
    DVDD12
    DVDD12 43 1 2
    for better EMI performace 49 +LAN_AVDD12 0.1U_0402_16V4Z CL13
    LAN_PCIE_WAKE# DVDD12 +LAN_EVDD12
    <33> LAN_PCIE_WAKE# 19 LANWAKEB DVDD12 52 1 2
    0.1U_0402_16V4Z CL14
    +3V_LAN ISOLATEB 36 1 2 1 2
    ISOLATEB LL2 0_0603_5% 0.1U_0402_16V4Z CL15
    EVDD12 22 +LAN_EVDD12 1 2
    1 2 LAN_PCIE_WAKE# 28 8111C@ 1 2
    RL3 100K_0402_5% LAN_X1 EVDD12 CL17 CL18 0.1U_0402_16V4Z CL16
    60 CKTAL1
    2 1U_0402_6.3V4Z 0.1U_0402_16V4Z 2
    1 2
    LAN_X2 61 16 +3V_LAN 8102E@ 2 1 8111C@ CL17 8111C@ 0.1U_0402_16V4Z CL19
    CKTAL2 VDD33 0.1U_0402_16V4Z
    VDD33 37 1 2
    46 8111C@ 0.1U_0402_16V4Z CL20
    VDD33
    Y1 53 Close to Pin28 1 2
    LAN_X1 2 VDD33
    1LAN_X2 65 EXPOSE_PAD
    8111C@ 0.1U_0402_16V4Z CL21
    1 2
    25MHz_20pF_6X25000017 63 +VDDSR 8111C@ 0.1U_0402_16V4Z CL22
    VDDSR
    1 1 25 EGND 1 2
    CL24 CL25 2 +3V_LAN +LAN_DVDD12 +3V_LAN 8111C@ 0.1U_0402_16V4Z CL23
    AVDD33
    31 EGND AVDD33 59 1 2
    27P_0402_50V8J 27P_0402_50V8J RL8 0_0603_5% +3V_LAN
    2 2 8102E@
    AVDD12 8 +LAN_AVDD12 2 2
    +LAN_DVDD12 15 11 +VDDSR 1 2
    NC AVDD12 LL4 0_0603_5% CL26 CL27
    17 NC AVDD12 14 1 1
    18 58 8111C@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    +3VS NC AVDD12 CL28 CL29 8111C@ 1 1
    34 NC
    35 0.1U_0402_16V4Z 22U_0805_6.3V6M
    NC @ 8111C@ 2 2 8111C@
    39 NC IGPIO 50 Close to Pin2,59
    1

    40 51 DSM# 2 1
    NC OGPIO LAN_DSM# <21>
    RL6 41 R399
    1K_0402_1% NC 0_0402_5%
    42 NC
    RTL8111C-GR_QFN64_9X9
    LAN Conn.
    2

    <22> LAN_ISOLATE# 2 R398 1 ISOLATEB 8111C@


    1K_0402_1%
    +LAN_DVDD12 +LAN_AVDD12
    @
    JLAN
    RL7 1 2 LAN_ACTIVITY# 2 1 RL10 12
    15K_0402_5% RL9 0_0603_5% 300_0402_5% Yellow LED-
    1
    8111C@ 11
    CL30 +3V_LAN Yellow LED+
    3 UL3 68P_0402_50V8J RJ45_MIDI3- 3
    8 PR4-
    2
    1 TCT1 MCT1 24 1 8111C@ 2 RJ45_MIDI3+ 7 PR4+
    LAN_MDI3- 2 23 RL11 75_0402_1% RJ45_MIDI3-
    LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+ RJ45_MIDI1-
    3 TD1- MX1- 22 6 PR2-
    4 21 1 8111C@ 2 RJ45_MIDI2- 5
    LAN_MDI2- TCT2 MCT2 RL12 75_0402_1% RJ45_MIDI2- PR3-
    5 TD2+ MX2+ 20
    LAN_MDI2+ 6 19 RJ45_MIDI2+ RJ45_MIDI2+ 4
    TD2- MX2- PR3+
    7 18 1 2 RJ45_MIDI1+ 3
    LAN_MDI1- TCT3 MCT3 RL13 75_0402_1% RJ45_MIDI1- PR2+
    8 TD3+ MX3+ 17
    LAN_MDI1+ 9 16 RJ45_MIDI1+ RJ45_MIDI0- 2
    TD3- MX3- PR1-
    SHLD2 14
    10 15 1 2 RJ45_MIDI0+ 1
    LAN_MDI0- TCT4 MCT4 RL15 75_0402_1% RJ45_MIDI0- PR1+
    11 TD4+ MX4+ 14 SHLD1 13
    LAN_MDI0+ 12 13 RJ45_MIDI0+ LAN_LINK# 2 1 RL14 10
    TD4- MX4- 300_0402_5% Green LED-
    1
    +3V_LAN 9 Green LED+
    1 1 CL31
    SUPERWORLD_SWG150401 68P_0402_50V8J TYCO_2068888-1_12P-T
    CL32 CL33 2
    1 1 @
    0.01U_0402_16V7K 0.01U_0402_16V7K 8111C@ RJ45_GND
    8111C@ 2 2 8111C@ CL34 CL35
    0.01U_0402_16V7K 0.01U_0402_16V7K
    2 2 RJ45_GND 1 2 1000P_1808_3KV7K LANGND
    Place these components CL36 1 1
    pin assignments table for difference CL37 CL38
    colsed to LAN chip
    Pin 8111C 8102E 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
    1 SROUT12 VCTRL12A 2 2
    5 FB12 NC
    4 8 AVDD12 NC 4
    9 MDIP2 NC
    10 MDIN2 NC
    11 AVDD12 NC
    12 MDIP3 NC
    13 MDIN3 NC
    14 AVDD12 NC
    15 NC DVDD12
    22 EVDD12 NC Security Classification Compal Secret Data Compal Electronics, Inc.
    32 DVDD12 NC Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    52 DVDD12 NC
    58 AVDD12 DVDD12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    59 AVDD33 NC AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    62 ENSR NC DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    63 VDDSR VCTRL12D MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 26 of 45
    A B C D E
    A B C D E

    +3V_WLAN

    0.1U_0402_16V4Z
    1 1 1
    PCIe Mini Card for WLAN CM17
    WLAN@
    CM18
    WLAN@
    CM19
    WLAN@
    PCIe Mini Card GPS/UWB
    2 2 2 +3VS
    0.01U_0402_25V4Z 4.7U_0805_10V4Z
    0.1U_0402_16V4Z
    1 1 1
    +3V_WLAN +1.5VS +1.5VS +3VS
    +3V_WLAN +1.5VS CM1 CM2 CM3
    RM4 0.1U_0402_16V4Z JGPS GPS@ GPS@ GPS@
    1 2 2 2 1
    1 2 100K_0402_5% JWLAN 1 1 1 1 1 2 2
    1 2 3 4 0.01U_0402_25V4Z 4.7U_0805_10V4Z
    <33> WLAN_WAKE# 1 2 3 4
    3 4 CM20 CM21 CM22 5 6
    3 4 WLAN@ WLAN@ WLAN@ 5 6
    5 5 6 6 <15> CLKREQ_MCARD1# 7 7 8 8
    2 2 2
    <15> CLKREQ_MCARD2# 7 7 8 8 9 9 10 10
    9 10 0.01U_0402_25V4Z 4.7U_0805_10V4Z 11 12 +1.5VS
    9 10 <15> CLK_PCIE_MCARD1# 11 12
    <15> CLK_PCIE_MCARD2# 11 11 12 12 <15> CLK_PCIE_MCARD1 13 13 14 14
    13 14 15 16 0.1U_0402_16V4Z
    <15> CLK_PCIE_MCARD2 13 14 15 16
    15 16 17 18 R811 0_0402_5% 1 1 1
    15 16 17 18 UWB_DISABLE#
    17 17 18 18 19 19 20 20 1 2 UWB_OFF# <33>
    19 20 XMIT_OFF# 21 22 PLT_RST# GPS@ CM4 CM5 CM6
    19 20 PLT_RST# 21 22 GPS@ GPS@ GPS@
    21 21 22 22 PLT_RST# <11,14,19,20,26,28,32,33> <10> PCIE_PTX_C_IRX_N5 23 23 24 24
    2 2 2
    <10> PCIE_PTX_C_IRX_N2 23 23 24 24 <10> PCIE_PTX_C_IRX_P5 25 25 26 26
    <10> PCIE_PTX_C_IRX_P2 25 26 27 28 0.01U_0402_25V4Z 4.7U_0805_10V4Z
    25 26 27 28
    27 27 28 28 29 29 30 30
    29 30 SMB_CK_CLK1 31 32
    29 30 SMB_CK_CLK1 <21> <10> PCIE_ITX_C_PRX_N5 31 32
    31 32 SMB_CK_DAT1 33 34 R107 0_0402_5%
    <10> PCIE_ITX_C_PRX_N2 31 32 SMB_CK_DAT1 <21> <10> PCIE_ITX_C_PRX_P5 33 34
    33 34 35 36 USB20_N10C 1 2
    <10> PCIE_ITX_C_PRX_P2 33 34 USB20_N8C 35 36 USB20_P10C
    35 35 36 36 Reserve 37 37 38 38 Reserve for EMI request
    WLAN 37 38 USB20_P8C +3VS 39 40
    37 38 39 40 LED_WIMAX#_R WCM-2012-900T_0805
    +3V_WLAN 39 39 40 40 41 41 42 42
    41 42 LED_WIMAX#_R 43 44 1 2
    41 42 43 44 USB20_N10C 1 2
    43 44 45 46
    Kill SWITCH 45
    43
    45
    44
    46 46 47
    45
    47
    46
    48 48 USB20_P10C
    USB20_N10 <21>
    USB20_P10 <21>
    47 47 48 48 49 49 50 50 4 4 3 3

    +3V_WLAN
    49 49 50 50
    R109 0_0402_5%
    51 51 52 52 GPS/UWB
    51 51 52 52
    1 2 53 54 @ L70
    GND1 GND2
    53 GND1 GND2 54 Reserve for EMI request 1 2
    3

    SW1 DM5 WCM-2012-900T_0805 FOX_AS0B226-S40N-7F R108 0_0402_5%


    5 DAN217_SC59 ACES_88911-5204 1 2 @
    2 G2 @ USB20_N8C 1 2 2
    G1 4 @ USB20_N8 <21>
    RM5 USB20_P8C USB20_P8 <21>
    1 2 +3V_WLAN 4 3
    1

    100K_0402_5% 4 3
    3 3
    2 2 KILL_SW# <33>
    1 @ L71
    1
    1 2
    1BS003-1210L_3P
    WLAN@ R110 0_0402_5%

    XMIT_OFF# +3VS
    +3V_WLAN
    RM2 RM3
    1 2 1 2 +3V_WLAN KS@
    10K_0402_5% 100K_0402_5% CM23 0.1U_0402_16V4Z
    2

    GPS@ GPS@
    G

    1 2
    5

    LED_WIMAX#_R 1 3 LED_WIMAX# <34>


    2
    D

    <33> WLAN_XMIT_OFF# B
    QM1 4 XMIT_OFF#
    2N7002_SOT23-3 KILL_SW# 1 Y
    A
    G

    GPS@
    1 2 UM1
    3

    RM6 @ 0_0402_5% NC7SZ08P5X_NL_SC70-5


    KS@

    +3VALW_CARD +3VS_CARD +1.5VS_CARD


    3 3
    Imax = 0.275A Imax = 1.35A Imax = 0.75A
    1 1 1 1 1 1 JEXP

    CN1 CN2 CN3 CN4 CN5 CN6 1


    10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z GND
    <21> USB20_N11 2 USB_D-
    2 2 2 2 2 2
    <21> USB20_P11 3 USB_D+
    CP_USB# 4 CPUSB#
    U21 5 RSV
    +3V_SB
    60mils 6 RSV
    SMB_CK_CLK0
    1 2 CP_USB#
    +1.5VS 12
    14
    1.5Vin 1.5Vout 11
    13
    +1.5VS_CARD Change SMBus <8,9,15,21> SMB_CK_CLK0
    SMB_CK_DAT0
    7
    8
    SMB_CLK
    1.5Vin 1.5Vout <8,9,15,21> SMB_CK_DAT0 SMB_DATA
    RN1 100K_0402_5% +1.5VS_CARD 9 +1.5V
    share with USB OC PIN 40mils 10 +1.5V
    +3VS 2 3 +3VS_CARD EC_SWI# 11
    3.3Vin 3.3Vout <21,33> EC_SWI# WAKE#
    RN2
    1 2EXP_CPPE#
    100K_0402_5%
    need always pull high 4 3.3Vin 3.3Vout 5 +3VALW_CARD
    PERST#
    12 +3.3VAUX
    40mils 13 PERST#
    +3V_SB 17 AUX_IN AUX_OUT 15 +3VALW_CARD +3VS_CARD 14 +3.3V
    1 2 PLT_RST# 15 +3.3V
    RN3 100K_0402_5% PLT_RST# 6 19 CLKREQ# 16
    SYSRST# OC# EXP_CPPE# CLKREQ#
    <21> EXP_CPPE# 17 CPPE#
    20 8 PERST# 18
    <33,35,41> SYSON SHDN# PERST# <15> CLK_PCIE_NCARD# REFCLK-
    <15> CLK_PCIE_NCARD 19 REFCLK+
    +3VS +3VS 1 16 20
    <19,29,33,35,40> SUSP# STBY# NC GND
    <10> PCIE_PTX_C_IRX_N0 21 PERn0
    +3VS EXP_CPPE# 10 7 22
    CPPE# GND <10> PCIE_PTX_C_IRX_P0 PERp0
    1

    RN4 1 23
    CN7 CP_USB# GND
    9 CPUSB# Thermal_Pad 21 <10> PCIE_ITX_C_PRX_N0 24 PETn0
    1

    10K_0402_5% 0.1U_0402_16V4Z <10> PCIE_ITX_C_PRX_P0 25


    RN5 RCLKEN PETp0
    18 RCLKEN 26 GND GND 29
    5

    UN2 2
    30
    2

    10K_0402_5% CLKREQ# GND


    2 27
    G Vcc

    4 B G577NSR91U_TQFN20_4x4 GND 4
    4 CLKREQ_NCARD# 28
    CLKREQ_NCARD# <15>
    2

    Y GND
    1 A SANTA_130801-5_RT
    NC7SZ32P5X_NL_SC70-5 @
    3
    1

    D
    RCLKEN 2
    G another at page35
    Q21 S /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    3

    2N7002_SOT23-3
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 27 of 45
    A B C D E
    A B C D E

    +1.8VS_OUT
    40mil
    0.1U_0402_16V4Z 1000P_0402_50V7K
    1 1 1 1 D3E mode
    +3VALW
    Power Circuit CC1 CC2 CC3 CC4

    1
    U37 2 2 2 2
    10U_0805_10V4Z 0.1U_0402_16V4Z R129
    CLK_PCIE_MCARD0# 3 5 +3VS 10K_0402_5%
    <15> CLK_PCIE_MCARD0# CLK_PCIE_MCARD0 APCLKN APVDD
    <15> CLK_PCIE_MCARD0 4 APCLKP APV18 10
    1 2 Q54

    2
    <10> PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_N1 9 CC5 0.1U_0402_16V4Z <21> CR_CPPE# CPPE#
    1 PCIE_ITX_C_PRX_P1 APRXN 0_0603_5% 1
    <10> PCIE_ITX_C_PRX_P1 8 APRXP DV33 19 1 2
    20 CC6 0.1U_0402_16V4Z
    CC7 0.1U_0402_16V7K PCIE_PTX_IRX_N1 DV33
    <10> PCIE_PTX_C_IRX_N1 1 2 11 APTXN DV33 44 +1.8VS_OUT
    <10> PCIE_PTX_C_IRX_P1 CC8 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P1 12 18
    APTXP DV18
    DV18 37 1 1
    2 1 7 APREXT
    CC11 22P_0402_50V8J 8.2K_0402_5% RC1 48 XD_SD_MS_D0 CC9 CC10
    7mil XIN MDIO0 XD_SD_MS_D1 0.1U_0402_16V4Z
    2 1 MDIO1 47
    XIN XD_SD_MS_D2 2 2 +VCC_OUT
    38 TXIN MDIO2 46
    XOUT 39 45 XD_SD_MS_D3 @
    TXOUT JMB380 MDIO3
    1

    +3VS 43 SDCMD_MSBS_XDWE# 0.1U_0402_16V4Z RC3 10K_0402_5% 0_0402_5%


    XC1 RC2 MDIO4 SDCLK_MSCLK_XDCE# XDWP#_SDWP# 2 XDCD0#_SDCD#
    MDIO5 42 1 <21> CR_WAKE# 1 2
    1M_0402_5% 1 2 30 41 XDWP#_SDWP# R397
    CC12 0.1U_0402_16V4Z TAV33 MDIO6 XD_CLE XD_RB#
    40 2 1
    2

    24.576MHz_16P_3XG-24576-43E1 MDIO7 XD_SD_D4 RC4 10K_0402_5%


    29 1 2
    2

    XOUT PLT_RST# MDIO8 XD_SD_D5


    2 1 <11,14,19,20,26,27,32,33> PLT_RST# 1 XRSTN MDIO9 28
    7mil 2 27 XD_SD_D6 CH751H-40PT_SOD323-2 D24
    CC13 22P_0402_50V8J XTEST MDIO10 XD_SD_D7
    MDIO11 26
    25 XD_RE#
    +3VS CPPE# MDIO12 XD_RB#
    13 SEEDAT MDIO13 23
    TC2 PAD 14 22 XD_ALE Strapping setting
    4.7K_0402_5% RC5 SEECLK MDIO14
    1 2XDCD0#_SDCD# TPA1P 34 TPA+ Description
    XDCD1#_MSCD# 15 35 TPBIAS +3VS Pin name
    4.7K_0402_5% RC7 XDCD0#_SDCD# CR1_CD1N TPBIAS_1 TREXT
    16 CR1_CD0N TREXT 36 1 2 High low
    1 2 XDCD1#_MSCD# RC6 12K_0402_1%
    6 XD_CLE 1 2
    APGND RC8 10K_0402_5%
    +3VS +VCC_OUT 17 CR1_PCTLN MDIO7 on-board★ add-in card
    24 TCPS 2 1
    TCPS TPB- RC9 10K_0402_5%
    TPB1N 31
    CR_LED 21 32 TPB+ +VCC_OUT +VCC_OUT
    CR1_LEDN TPB1P
    1

    33 TPA- XD_RE# 1 2 MDIO12


    2 RC11 TPA1N RC10 200K_0402_5% high active low active★ 2
    120_0402_5% 49
    GND
    JMB380-QGAZ0A_QFN48_7X7 MDIO14 CR_LED CR_LED
    2 2

    XD_ALE 1 2
    RC12 10K_0402_5% high active★ low active
    DC1
    HT-F196BP5_WHITE P.S VCC_OUT also can out 3V with 250mA for
    5IN1 using.(MDIO12 can't be seted after MP IC)
    1
    6

    SDCLK_MSCLK_XDCE# 1 2 2 1 SDCLK
    22_0402_5% 2 1 RC13 MSCLK
    QC1A RC16 22_0402_5% 2 1 RC14 XDCE#
    2N7002DW-T/R7_SOT363-6 2CR_LED 100_0402_5% 22_0402_5% RC15
    @
    Close to Chip
    2

    1
    1

    RC17 100P_0402_25V8K
    4.7K_0402_5% CC14

    2
    1
    1

    1
    CC16 RC19 RC20 RC21
    56_0402_5% 56_0402_5%
    2 1394 Port
    Card Reader Connector Reserve for EMI request

    2
    +VCC_OUT +VCC_OUT J1394
    20 mils JREAD 220P_0402_50V8K 4.99K_0402_1% TPB- 1 5
    TPB+ TPB- GND
    3 XD-VCC SD-VCC 21 2 TPB+ GND 6
    28 TPA- 3 7
    3 XD_SD_MS_D0 MS-VCC TPA+ TPA- GND 3
    1 1 32 XD-D0 4 TPA+ GND 8
    XD_SD_MS_D1 10 20 SDCLK
    CC17 CC18 XD_SD_MS_D2 XD-D1 SD_CLK XD_SD_MS_D0 P-TWO_CU8047-A0G15
    9 XD-D2 SD-DAT0 14

    1
    10U_0805_10V4Z 0.1U_0402_16V4Z XD_SD_MS_D3 8 7 IN 1 CONN 12 XD_SD_MS_D1 RC22 @
    XD-D3 SD-DAT1

    3
    2 2 XD_SD_D4 XD_SD_MS_D2 TPBIAS 56_0402_5% RC23
    7 XD-D4 SD-DAT2 30
    XD_SD_D5 6 29 XD_SD_MS_D3 56_0402_5%
    XD_SD_D6 XD-D5 SD-DAT3 XD_SD_D4 IOGND
    5 XD-D6 SD-DAT4 27 1
    XD_SD_D7 4 23 XD_SD_D5

    2
    XD-D7 SD-DAT5 XD_SD_D6 CC20
    SD-DAT6 18
    2 1 2 1 XDCE# SDCMD_MSBS_XDWE# 34 16 XD_SD_D7 0.33U_0603_10V7K D21 D23
    RC24 XDWP#_SDWP# XD-WE SD-DAT7 XDCD0#_SDCD# 2 PJDLC05_SOT23-3
    33 XD-WP SD-CD 1 PJDLC05_SOT23-3
    CC19 100_0402_5% XD_ALE 35 2 XDWP#_SDWP#
    100P_0402_25V8K @ XD_CD# XD-ALE SD-WP SDCMD_MSBS_XDWE#
    40 25

    1
    @ XD_RB# XD-CD SD-CMD
    39 XD-R/B
    Reserve for EMI request XD_RE# 38 26 MSCLK
    XDCE# XD-RE MS-SCLK XD_SD_MS_D0
    37 XD-CE MS-DATA0 17
    DC2 XD_CLE 36 15 XD_SD_MS_D1
    XDCD1#_MSCD# XD-CLE MS-DATA1 XD_SD_MS_D2
    2 MS-DATA2 19
    1 XD_CD# 31 24 XD_SD_MS_D3
    XDCD0#_SDCD# 7IN1-GND MS-DATA3 XDCD1#_MSCD#
    3 1 11 7IN1-GND MS-INS 22
    41 13 SDCMD_MSBS_XDWE#
    DAN202U_SC70 CC21 7IN1-GND MS-BS
    42 7IN1-GND
    270P_0402_50V7K
    2
    R281
    TAITW_R015-D10-LM_NR
    @ 2 1

    0_0805_5%

    IOGND
    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 28 of 45
    A B C D E
    A B C D E

    1 1 2 2 +3VS
    @ PJ24
    JUMP_43X79
    +3VS_DVDD RA1
    10U_0805_10V4Z 30mil 2 1 +3VS +VDDA
    1 1 0_0603_1%
    CA1 CA2 +5VALW

    +AVDD
    4.75V
    2 2 UA1
    RA3 40mil 0.1U_0402_16V4Z CA9
    2
    2
    +VDDA 2 1 10U_0805_10V4Z 0.1U_0402_16V4Z 1 5 @
    0_0603_1% 1U_0402_6.3V4Z VIN VOUT CA10
    1 1 1 1 1
    1 CA3 CA4 CA5 CA6 10U_0805_10V4Z 1U_0402_6.3V4Z 1
    2 GND CA11 1
    1 1
    <19,27,33,35,40> SUSP# 3 SHDN# BP 4 2 1
    2 2 2 2 CA7 CA8
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.22U_0402_10V4Z
    2 2
    0.1U_0402_16V4Z APL5151-475BC-TRL_SOT23-5

    25

    38

    9
    UA2

    DVDD
    AVDD1

    AVDD2

    DVDD_IO
    14 LINE2-L LOUT1_L 35 AMP_SPK_L <30>
    EC Beep RA8
    <33> EC_BEEP 1 2
    15 LINE2-R LOUT1_R 36 AMP_SPK_R <30> 47K_0402_5%

    <30> MIC2_L 16 MIC2_L LOUT2_L 39


    Int. Mic 17 41 PCI Beep CA15
    <30> MIC2_R MIC2_R LOUT2_R RA9
    1 2 1 2 MONO_IN
    LA2 1 <21> SB_SPKR
    <32> FM_LINE_L 1 2 23 LINE1_L SPDIFO1 48 2 SPDIF <30> 47K_0402_5%
    CA12 2.2U_0603_6.3V6K MBK1608121YZF_0603 0.1U_0402_16V4Z
    <32> FM_LINE_R 1 2
    CA13 2.2U_0603_6.3V6K
    24 LINE1_R SPDIFO2 45
    @C193
    @
    1
    C193
    2
    33P_0402_50V8K FOR EMI
    <30> MIC1_C_L 21 MIC1_L HPOUT_L 33 1 RA5 2 HP_L <30>
    63.4_0402_1%
    Ext. Mic <30> MIC1_C_R 22 MIC1_R HPOUT_R 32 1 RA6 2 HP_R <30>

    1
    63.4_0402_1% 1

    1 2 MONO_IN 12 37 RA11 CA20


    CA14 100P_0402_25V8K BEEP_IN MONO_OUT 10K_0402_5% 0.1U_0402_16V4Z
    2

    2
    2 2
    <21> HDA_BITCLK_CODEC 6 BITCLK DMIC_CLK1/2 46

    <21> HDA_SDOUT_CODEC 5 SDATA_OUT DMIC_CLK3/4 44

    <21> HDA_SDIN0 2 1 HDA_SDIN0_R 8 SDATA_IN LINE2_VREFO 20


    33_0402_5% RA7
    <21> HDA_RST#_CODEC 11 RESET# LINE1_VREFO 18

    <21> HDA_SYNC_CODEC 10 SYNC MIC1_VREFO 28 10mil +MIC1_VREFO


    19
    10mil
    MIC2_VREFO +MIC2_VREFO
    <22> SPK_SEL 2 GPIO0/DMIC_DATA1/2
    CPVREF 31 1 2
    3 CA16 2.2U_0603_6.3V6K
    GPIO1/DMIC_DATA3/4 AC_VREF CA18 CA19
    VREF 27

    10U_0805_10V4Z

    0.1U_0402_16V4Z
    SENSE_A 13 SENSE A AC_JDREF
    JDREF 40 1 RA10 2 1 1
    SENSE_B 34 20K_0402_1%
    SENSE B
    CBN 30 1 2
    EAPD_CODEC 47 CA17 2.2U_0603_6.3V6K
    <33> EAPD_CODEC EAPD 2 2
    CBP 29
    43 NC
    4 DVSS AVSS1 26
    7 DVSS AVSS2 42

    ALC272-GR_LQFP48 1 2
    need to re-link ALC272 RA12 0_0603_5%
    DGND AGND 1 2
    RA13 0_0603_5%
    1 2
    3 GPIO0-->SPK_SEL HIGH:HARMAN RA14 @ 0_0603_5% 3

    LOW:NO-BRAND 1 2
    RA15 0_0603_5%

    +5VS
    Int. Camera +5VS

    2
    Sense Pin Impedance Codec Signals Function place close to chip R429
    1M_0402_5%
    39.2K PORT-A (PIN 39, 41) <30> NBA_PLUG 1 2 SENSE_B @ C743

    3
    S
    RA16 5.1K_0402_5% R430 R427 @ 0.1U_0402_16V4Z

    1
    G
    RA17 +5VS 1 2 1 2 2 @
    20K PORT-B (PIN 21, 22) 0_0603_5% 100K_0402_5%
    Ext. MIC 1 2

    1
    20K_0402_1% D
    SENSE A CAM@
    D
    2

    1
    MIC@ W=20mils 2 C742 Q8
    <22> CAM_PWR
    10K PORT-C (PIN 23, 24) R428 G 1000P_0402_50V7K AO3413_SOT23-3
    FM tuner 1 2 +CAM_VDD Q9 S @ @
    +5VALW

    3
    0_0603_5% 2N7002_SOT23-3 1
    1 +CAM_VDD
    5.1K PORT-D (PIN 35, 36) C744 R103 0_0402_5% @ @
    SPK out @
    0.1U_0402_16V4Z 1 2
    CAM@ Reserve for EMI request
    2
    39.2K PORT-E (PIN 14, 15) WCM-2012-900T_0805
    <30> MIC_SENSE 1 RA18 2 SENSE_A JCAM
    20K_0402_1% 1 1 2
    1 USB20_N9_R 1 2
    20K PORT-F (PIN 16, 17) Int. MIC 2 2 USB20_N9 <21>
    SENSE B 1 RA19 2 3 3 USB20_P9_R
    USB20_P9 <21>
    10K_0402_1% 4 4 3
    4 FM@ 4 4 3 4
    10K PORT-H (PIN 37) 5 5
    GND1 6
    7 L60 CAM@
    GND2
    5.1K PORT-I (PIN 32, 33) Headphone out ACES_88266-05001
    1 2

    @ R99 0_0402_5% @

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 29 of 45
    A B C D E
    A B C D E

    Ext. Mic
    CH751H-40PT_SOD323-2
    TPA6017 Medium Range Amplifier CA21
    RA21 2 RA20 1
    1K_0402_5% 4.7K_0402_5%
    1
    DA1
    2 +MIC1_VREFO
    4.7U_0805_10V4Z 2 1 2 1 MIC1_L
    <29> MIC1_C_L
    +5VS 4.7U_0805_10V4Z 2 1 2 1 MIC1_R
    1 <29> MIC1_C_R 1
    0.1U_0402_16V4Z 1K_0402_5%
    CA22 RA22 2 RA23 1 1 2 +MIC1_VREFO
    4.7K_0402_5% DA2
    1 1 1 CH751H-40PT_SOD323-2

    CA23
    10U_0805_10V4Z
    CA24 CA25 Int. Mic MIC@
    2 2 2
    2 1 +MIC2_VREFO
    4.7K_0402_5% RA24
    0.1U_0402_16V4Z MIC@ MIC@ RA25
    10 dB CA26 1K_0402_5% JMIC
    1U_0402_6.3V4Z 2 1 2 1 INT_MIC1 3
    +5VS <29> MIC2_L 1 NC1
    1 2 2 2 NC2 4

    1
    1U_0402_6.3V4Z CA27

    16
    15
    <29> MIC2_R 2 1 2 1

    6
    UA3 RA27 @ RA28 1K_0402_5% 220P_0402_50V7K ACES_85204-0200N
    100K_0402_5% 100K_0402_5% CA28 RA26 @

    VDD
    PVDD1
    PVDD2

    3
    MIC@ MIC@

    PSOT24C_SOT23
    2

    2
    @
    CA29 1 2 0.033U_0603_16V7 7 2
    RIN+ GAIN0
    3

    1
    GAIN1 DA3

    1
    <29> AMP_SPK_R CA30 1 2 0.033U_0603_16V7 LINE_C_OUTR 17
    RIN- SPKR+ @ RA29 RA30
    ROUT+ 18
    100K_0402_5% 100K_0402_5%

    14 SPKR- Left Connector DA4 PACDN042Y3R_SOT23-3

    2
    CA31 1 ROUT-
    2 0.033U_0603_16V7 9 LIN+ 2
    1
    4 SPKL+ 3
    LOUT+ LA3 FBMA-L11-160808-800LMT_0603 JSPKL
    2 CA32 1 LINE_C_OUTL SPKL+ SPK_L1 2
    <29> AMP_SPK_L 2 0.033U_0603_16V7 5 LIN- 1 2 1 1 NC1 3
    8 SPKL- SPKL- 1 2 SPK_L2 2 4
    LOUT- 2 NC2
    LA4 FBMA-L11-160808-800LMT_0603 ACES_85204-0200N
    @

    12 Keep 10 mil width


    Right Connector DA5 PACDN042Y3R_SOT23-3
    NC
    3
    10 AMP_BYPASS 1
    BYPASS
    <33> EC_MUTE# 19 SHUTDOWN 2
    2 LA5 FBMA-L11-160808-800LMT_0603 JSPKR
    SPKR+ 1 2 SPK_R1 1 3
    1 NC1
    GND5
    GND1
    GND2
    GND3
    GND4

    CA33 SPKR- 1 2 SPK_R2 2 4


    2 NC2
    0.47U_0603_10V7K
    1 LA6 FBMA-L11-160808-800LMT_0603 ACES_85204-0200N
    TPA6017A2_TSSOP20 @
    21
    20
    13
    11
    1

    GAIN0 GAIN1 Av(db) Rin(ohm)

    0 0 6 90K
    0 1 10 70K HeadPhone/LINE Out JACK JLINE
    1 0 15.6 45K <29> NBA_PLUG 1 1
    L35 1 2 HP_R_L 2
    <29> HP_R 2
    1 1 21.6 25K KC FBM-L11-160808-121LMT 0603
    L36 1 2 HP_L_L 3
    <29> HP_L 3
    KC FBM-L11-160808-121LMT 0603
    4 4
    3 5 5
    1
    3 SPDIF_R 3
    2 8 8
    +3VS

    +3VS
    Volume Control DA6
    PJDLC05_SOT23-3
    +5VS 9 9
    DRIVE
    IC
    1

    10 10 GND 6
    RA32 1 2 SPDIF_R 7
    <29> SPDIF GND
    100K_0402_5% RA31 1
    1

    CA35 0.1U_0402_16V4Z 0_0603_5% AGND SINGA_2SJ-A373-H01


    RA33 RA34 +3VS 1 2 CA34 @
    2
    5

    SW2 10K_0402_5% 10K_0402_5% +3VS 100P_0402_50V8J


    2
    1
    DIP

    1
    2

    CA36
    P

    NC

    2 1 2 2 4 0.1U_0402_16V4Z
    A RA35 10K_0402_5% A Y 2
    G

    74LVC1G14GW_SOT353-5 UA5
    1 UA4 1 14 Ext.MIC/LINE IN JACK
    3

    COM CD1# VCC FOX_JA6333L-B3T0-7F


    2 D1 CD2# 13
    3 12 AGND 5
    CP1 D2
    B 3 1 2 4 SD1# CP2 11
    RA36 10K_0402_5% 5 10 4
    Q1 SD2# <29> MIC_SENSE
    1 1 6 Q1# Q2 09 1
    DIP

    7 08 CA39 MIC1_R LA9 1 2 MIC1_L_R 3


    CA37 CA38 GND Q2# KC FBM-L11-160808-121LMT 0603 6
    SW_XRE094_3P 0.01U_0402_16V7K 0.01U_0402_16V7K 74LCX74MTC_TSSOP14 MIC1_L LA101 2 MIC1_L_L 2
    4

    2 2 2 KC FBM-L11-160808-121LMT 0603 1
    DA7
    JEXMIC
    0.1U_0402_16V4Z 3 1 1
    ENCODER_DIR <33>
    1 @ @
    ENCODER_PULSE <33>
    2 CA40 CA41
    100P_0402_25V8K 100P_0402_25V8K
    4 2 2 4
    PJDLC05_SOT23-3

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 30 of 45
    A B C D E
    A B C D E

    eSATA/USB
    W=60mils
    +5VALW 1.4A +USB_VCCB
    U19
    1 GND OUT 8
    2 IN OUT 7
    3 IN OUT 6
    <33> USB_EN# 4 EN# FLG 5 1 R584 2 USB_OC#2 <21>
    0_0402_5%
    G528_SO8 1
    1 C367 1
    4.7U_0805_10V4Z
    @
    2
    +USB_VCCB
    +USB_VCCB W=60mils
    D20
    W=60mils
    2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    1 1 1 1
    3 D15 1 1 1
    C405 + C406 C407 2 @
    PJDLC05_SOT23-3 1 C350 +
    2 2 C352 C351
    3
    220U_6.3V_M 2 150U_D_6.3VM 2 2
    R70 0_0402_5% @ 1000P_0402_50V7K PJDLC05_SOT23-3 2
    1 2 1000P_0402_50V7K
    Reserve for EMI request
    L52 R95 0_0402_5% @
    JUSB 1 2
    <21> USB20_N4 1 1 2 2
    USB20_N4_R
    1 VCC GND 5 Reserve for EMI request eSATA/USB Conn
    2 D- GND 6
    USB20_P4_R 3 7 L46 JESATA
    D+ GND USB
    <21> USB20_P4 4 4 3 3 4 GND GND 8 <21> USB20_N2 1 1 2 2 1 VBUS
    USB20_N2_R 2
    WCM-2012-900T_0805 P-TWO_CU304G-A0G1G-P USB20_P2_R D-
    3 D+
    @ 4 3 4
    <21> USB20_P2 4 3 GND
    R77 0_0402_5% @
    1 2 WCM-2012-900T_0805 5
    IOGND GND
    <22> SATA_TXP2 6 A+
    1 2 7 ESATA
    <22> SATA_TXN2 A-
    8 GND SHIELD 12
    R96 0_0402_5% @ SATA_RXN2 9 13
    2 SATA_RXP2 B- SHIELD 2
    10 B+ SHIELD 14
    11 GND SHIELD 15
    <22> SATA_RXN2_C 2 1
    C361 2 1 0.01U_0402_25V7K TYCO_1909574-1
    <22> SATA_RXP2_C
    C357 0.01U_0402_25V7K @
    IOGND

    +5VS
    +3VS
    BlueTooth Interface
    USB Board

    2
    C482 BT@
    R432 0.1U_0402_16V4Z
    1M_0402_5%
    3 BT@ 3
    W=60mils

    3
    S
    R441 BT@
    1.4A

    1
    +5VALW +USB_VCCA +USB_VCCA
    G
    1 2 2
    U25 100K_0402_5%
    1 8 W=60mils JUSBB 2
    D Q25 BT@

    1
    GND OUT

    1
    D BT@ C481 AO3413_SOT23 R106 0_0402_5%
    2 IN OUT 7 1 1
    3 6 2 <33> BT_PWR 2 1000P_0402_50V7K 1 2
    USB_EN# IN OUT 2 G
    4 EN# FLG 5 1 2 USB_OC#0 <21> 3 3 1 +BT_VCC Reserve for EMI request
    1 R422 0_0402_5% L50 4 BT@ Q26 S

    3
    G528_SO8 C438 4 2N7002_SOT23 @ L62
    5 5
    @ <21> USB20_N0 1 2 6 4 3
    4.7U_0805_10V4Z 1 2 USB20_N0_R 6 4 3
    7 7 <21> USB20_P6
    2 USB20_P0_R 8 8 <21> USB20_N6
    <21> USB20_P0 4 4 3 3 9 9 1 1 2 2
    USB20_N1_R 10 Bluetooth Connector
    WCM-2012-900T_0805 USB20_P1_R 10 WCM-2012-900T_0805
    11 11
    L51 12 JBT
    12
    13 GND 1 2 1 1
    <21> USB20_N1 1 2 14 USB20_P6_R 2
    1 2 GND R105 0_0402_5% USB20_N6_R 2
    3 3
    E&T_6905-E12N-00R 4
    BT@ 2 4
    <21> USB20_P1 4 4 3 3 @ <22> BT_DET# 1 5 5
    <33> BT_RST# 1 BT@ 2BT_RESET# R437 0_0402_5% 6
    WCM-2012-900T_0805 R440 0_0402_5% 6
    7 7
    8 8
    Reserve for EMI request +3VS 1 2 9 9
    R438 @ 10
    4.7K_0402_5% 10
    +BT_VCC

    2
    C480 (MAX=200mA)
    Finger printer 0.1U_0402_16V4Z
    BT@ C483
    1
    C479 BT@R439
    BT@R439
    11 GND1
    12
    4 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5% GND2 4
    BT@ 2 BT@ ACES_87213-1000G

    1
    @
    +3VS 1 R119 2 +3VS_FP
    0_0603_5% 1
    FP@ C468
    0.1U_0402_16V4Z
    FP@ JFP /
    2
    USB20_N7
    1 1 USB20_N7 2
    D22 Security Classification Compal Secret Data Compal Electronics, Inc.
    <21> USB20_N7 2 2 Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    USB20_P7 3 5 1
    <21> USB20_P7
    1 2 4
    3 GND
    4 GND 6 USB20_P7 3
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    R118 0_0603_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    ACES_85201-04051 PJDLC05_SOT23-3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    FP@ @ MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 31 of 45
    A B C D E
    A B C D E

    SPI Flash (8Mb*1) +3VL FM tuner


    +3VS
    1 20mils
    C786 U46 FM_I2CCLK 1 FM@ 2
    8 4 R423 4.7K_0402_5%
    0.1U_0402_16V4Z VCC VSS FM_I2CDAT 1 FM@ 2
    2 @ JFM R426 4.7K_0402_5%
    3 W
    1 1 +3VS
    7 HOLD 2 2
    3 FM_I2CCLK
    3 FM_I2CCLK <22>
    SPI_CS# 1 2 INT_SPI_CS# 1 4 FM_I2CDAT
    1 S 4 FM_I2CDAT <22> 1
    R751 0_0402_5% 5
    EC_SPICLK 6 5
    <33> SPI_CLK C 6 6 FM_LINE_R <29>
    7 7 FM_LINE_L <29>
    <33> EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO <33> 8 8
    11 GND 9 9
    SST25VF080B-50-4C-S2AF_SO8 12 10
    GND 10
    ACES_88514-1041

    EC_SPICLK 1 2 1 2
    External Flash ROM R518 C606
    @ 10_0402_5% @ 4.7P_0402_50V8C
    JP35
    SPI_CS# 1 2 +3VL
    <33> SPI_CS# 1 2
    EC_SI_SPI_SO 3 4 INT_FLASH_EN#
    <22> SB_INT_FLASH_SEL 5
    7
    3
    5
    4
    6 6
    8
    EC_SPICLK
    EC_SO_SPI_SI
    LPC Debug Port
    7 8
    Please place the PAD under DDR DIMM.
    E&T_2941-G08N-00E~D
    @
    H1
    +3VALW
    CIR
    6 5 1 2 E51_TXD
    E51_TXD <33>
    R758 @ 0_0402_5%

    SIRQ 1 2 7 4 PLT_RST#
    <20,33> SIRQ PLT_RST# <11,14,19,20,26,27,28,33>
    If these TEST@ components are mounded, please delete R387 R622 0_0402_5% U31
    1
    +3VL @ LPC_AD3 8 3 LPC_AD2 C628 1
    2 <20,33> LPC_AD3 LPC_AD2 <20,33> GND 2
    C610 0.1U_0402_16V4Z 4.7U_0805_10V4Z
    2 1 CIR@ 2
    @ LPC_AD1 LPC_AD0 2 GND
    <20,33> LPC_AD1 9 2 LPC_AD0 <20,33>
    5

    U40 R519 100K_0402_5% +5VL 2 CIR@ 1 +5VALW_CIR 3 VCC


    R520 2 INT_FLASH_EN# 1 2 R576 100_0805_5%
    G Vcc

    INT_SPI_CS# B LPC_FRAME# 10 CIR_IN


    1 2 4 Y <20,33> LPC_FRAME# 1 CLK_PCI_SIO2 <20,24> <33> CIR_IN 4 ROUT
    22_0402_5% 1 SPI_CS#
    @ A TSOP6238-TR_4P

    2
    NC7SZ32P5X_NL_SC70-5
    3

    @ @ DEBUG_PAD R634 CIR@


    22_0402_5%

    1
    2
    C639
    22P_0402_50V8J
    1

    For EMI
    Left switch
    KEYBOARD CONN. KSO2 1
    C725
    2
    100P_0402_25V8K
    KSO1 1 2 SW3
    C717 100P_0402_25V8K
    KSI[0..7] KSO0 1 2 1 3
    KSI[0..7] <33>
    C721 100P_0402_25V8K
    KSO[0..15] KSO4 1 2 2 4
    KSO[0..15] <33> <34> TP_SWL
    KSO3
    C609
    1
    100P_0402_25V8K
    2 MDC 1.5 Conn. 1
    SMT1-05-A_4P

    6
    5
    3 C724 100P_0402_25V8K C748 3
    JKB KSO5 1 2 Change type 4/25 180P_0402_50V8J

    2
    C728 100P_0402_25V8K 2
    34 1 2 +3VS
    R502 300_0402_5% KSO14 1 2 D39
    33 C730 100P_0402_25V8K JMDC @
    32 PJDLC05_SOT23-3
    KSO6 1 2 @
    31 C715 100P_0402_25V8K
    30 1 GND1 RES0 2 +3V_SB
    1 2 +3VS KSO7 1 2 <21> HDA_SDOUT_MDC HDA_SDOUT_MDC 3 4
    29 KSO2 R503 300_0402_5% C732 100P_0402_25V8K IAC_SDATA_OUT RES1
    28 5 GND2 3.3V 6 +3V_SB
    KSO1 KSO13 1 2 <21> HDA_SYNC_MDC HDA_SYNC_MDC 7 8
    27 KSO0 C733 100P_0402_25V8K IAC_SYNC GND3
    <21> HDA_SDIN1 1 MDC@ 2R495 HDA_SDIN1_MDC 9 10

    1
    26 KSO4 KSO8 33_0402_5% IAC_SDATA_IN GND4
    25 1 2 <21> HDA_RST#_MDC 11 IAC_RESET# IAC_BITCLK 12 HDA_BITCLK_MDC <21>
    KSO3 C740 100P_0402_25V8K
    24 KSO5 KSO9
    23 1 2 2 1 1 2
    KSO14 C737 100P_0402_25V8K +3V_SB R496 C777

    GND
    GND
    GND
    GND
    GND
    GND
    22 KSO6 KSO10 @ 10_0402_5% @ 10P_0402_25V8K
    21 KSO7
    1
    C729
    2
    100P_0402_25V8K
    Right Switch
    20 KSO13 KSO11 ACES_88018-124G
    1 2

    13
    14
    15
    16
    17
    18
    19
    1000P_0402_50V7K
    C778

    C779

    0.1U_0402_16V4Z

    KSO8 C738 100P_0402_25V8K SW4


    18 KSO9 KSO12
    17 1 2 1 1 1
    KSO10 C718 100P_0402_25V8K MDC@ Connector for MDC Rev1.5 1 3
    16 KSO11 KSO15 C780
    15 1 2
    MDC@

    MDC@

    KSO12 C736 100P_0402_25V8K 4.7U_0805_10V4Z 2 4


    14 2 2 2 <34> TP_SWR
    KSO15 KSI7 1 2
    13 KSI7 C716 100P_0402_25V8K SMT1-05-A_4P
    1

    6
    5
    12 KSI2 KSI2
    11 1 2
    KSI3 C741 100P_0402_25V8K C749
    10

    2
    KSI4 KSI3 1 2 180P_0402_50V8J
    9 KSI0 C726 100P_0402_25V8K 2 D58
    8 KSI5 KSI4
    7 1 2 PJDLC05_SOT23-3
    KSI6 C723 100P_0402_25V8K
    6 KSI1 KSI0 @
    5 1 2
    4 C731 100P_0402_25V8K 4
    4 2 1 +3VS
    CAPS_LED# R509 300_0402_5% KSI5 1 2
    3 CAPS_LED# <33>
    CURS_LED# C739 100P_0402_25V8K
    2 CURS_LED# <33>
    NUM_LED# KSI6 1 2
    NUM_LED# <33>

    1
    1 C735 100P_0402_25V8K
    ACES_88170-3400 KSI1 1 2
    @ C734 100P_0402_25V8K
    CAPS_LED# 1 2 /

    CURS_LED#
    C722 100P_0402_25V8K Security Classification Compal Secret Data Compal Electronics, Inc.
    1 2 Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    C727 100P_0402_25V8K
    NUM_LED# 1 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    C714 100P_0402_25V8K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 32 of 45
    A B C D E
    A B C D E

    +3VL_EC

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K


    1 1 1 1 1
    C805 C806 C807 C808 C809 +3VL +3VL_EC +EC_AVCC

    2 2 2 2 2 L25
    0.1U_0402_16V4Z 1000P_0402_50V7K 2 1
    0_0603_5%

    111
    125
    1 1

    22
    33
    96

    67
    9
    RP15 U33
    SMB_EC_DA2 1 8

    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    AVCC
    +3VS
    SMB_EC_CK2 2 7 BATT_OVP 2 1
    SMB_EC_DA1 3 6 +5VL 100P_0402_50V8J C327
    SMB_EC_CK1 4 5
    GATEA20 1 21 INVT_PWM
    <21> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM <17>
    4.7K_0804_8P4R_5% KB_RST# 2 23
    <21> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP <29>
    Reserve for EMI request SIRQ 3 26 VR_LED
    <20,32> SIRQ SERIRQ# FANPWM1/GPIO12 VR_LED <34>
    LPC_LFRAME# 4 27 ACOFF
    <20,32> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <38>
    C810 R530 <20,32> LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K
    LPC_AD2 LAD3 C812 ECAGND
    1 2 1 2 <20,32> LPC_AD2 7 LAD2 PWM Output 1 2
    @ 33_0402_5% <20,32> LPC_AD1 LPC_AD1 8 63 BATT_TEMP
    LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA <37>
    @ 15P_0402_50V8J LPC_AD0 BATT_OVP
    <20,32> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP <38>
    ADP_I/AD2/GPIO3A 65
    CLK_PCI_EC 12 AD Input 66
    <20,24> CLK_PCI_EC PCICLK AD3/GPIO3B
    PLT_RST# 13 75 KILL_SW#
    <11,14,19,20,26,27,28,32> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 KILL_SW# <27>
    +3VL R533 1 2 ECRST# 37 76
    47K_0402_5% EC_SCI# ECRST# SELIO2#/AD5/GPIO43
    <21> EC_SCI# 20 SCI#/GPIO0E
    <20> CLKRUN# 1 2 38 CLKRUN#/GPIO1D
    R229 0_0402_5% 68
    DAC_BRIG/DA0/GPIO3C DAC_BRIG <17>
    2 1 70 EAN_DFAN1
    EN_DFAN1/DA1/GPIO3D EAN_DFAN1 <4>
    DA Output 71 IREF
    IREF/DA2/GPIO3E IREF <38>
    C811 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ
    KSI0/GPIO30 DA3/GPIO3F CHGVADJ <38>
    KSI1 56
    KSI2 KSI1/GPIO31
    57 KSI2/GPIO32
    KSI3 58 83
    KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <30>
    KSI4 59 84
    KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <31>
    KSI5 60 85 CAP_INT#
    KSI5/GPIO35 PSCLK2/GPIO4C CAP_INT# <34>
    KSI6 61 PS2 Interface 86 ENCODER_PULSE
    KSI6/GPIO36 PSDAT2/GPIO4D ENCODER_PULSE <30> +5VL
    SUSP# SYSON KSI7 62 87 TP_CLK
    KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK <34>
    39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA <34>
    2 KSI[0..7] KSO1 40 CAP_INT# R565 1 @ 2 4.7K_0402_5% 2
    <32> KSI[0..7] KSO1/GPIO21
    1

    KSO2 41
    R536 R539 KSO[0..15] KSO3 KSO2/GPIO22 BT_RST# CIR_IN R567
    <32> KSO[0..15] 42 KSO3/GPIO23 SDICS#/GPXOA00 97 BT_RST# <31> 1 2 4.7K_0402_5%
    10K_0402_5% 100K_0402_5% KSO4 43 98 WOL_EN
    KSO5 KSO4/GPIO24 SDICLK/GPXOA01 SBPWR_EN WOL_EN <35>
    KSO6
    44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 SBPWR_EN <35>
    45 KSO6/GPIO26 Matrix 109 VGATE <43>
    2

    KSO7 SDIDI/GPXID0
    46 KSO7/GPIO27 SPI Device Interface
    KSO8 47
    KSO9 KSO8/GPIO28
    48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO <32>
    KSO10 49 120
    +3VALW KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <32>
    KSO11 50 SPI Flash ROM 126
    KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK <32>
    KSO12 51 128
    KSO12/GPIO2C SPICS# SPI_CS# <32>
    KSO13 52
    KSO14 KSO13/GPIO2D
    0205_Add Pull down 53 KSO14/GPIO2E
    R402 for SUSP#. KSO15 54 73 CIR_IN
    KSO15/GPIO2F CIR_RX/GPIO40 CIR_IN <32>
    1

    WL_AMBER_LED# 81 74 WLAN_WAKE#
    <34> WL_AMBER_LED# KSO16/GPIO48 CIR_RLC_TX/GPIO41 WLAN_WAKE# <27>
    R538 82 89 FSTCHG +5VS
    KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <38>
    100K_0402_5% 90 BATT_FULL_LED#
    BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <34>
    91 TP_CLK 1 2
    CAPS_LED#/GPIO53 CAPS_LED# <32>
    SMB_EC_CK1 77 GPIO 92 BAT_LED# R534 10K_0402_5%
    <18,34,37> SMB_EC_CK1 BAT_LED# <34>
    2

    SMB_EC_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 CURS_LED#


    <18,34,37> SMB_EC_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 CURS_LED# <32>
    SMB_EC_CK2 79 SM Bus 95 SYSON TP_DATA 1 2
    <6,19> SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <27,35,41>
    LID_SW# SMB_EC_DA2 80 121 CPU_VCORE_ENABLE R535 10K_0402_5%
    <6,19> SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 CPU_VCORE_ENABLE <43>
    127 ACIN_D
    AC_IN/GPIO59
    2 1
    R541 10K_0402_5%
    SLP_S3# 6 100 EC_RSMRST#
    <21> SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <21>
    +3VL SLP_S5# 14 101
    <21> SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <21>
    @ EC_SMI# 15 102 1 2 +3VL
    <21> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <34,35>
    CEC_INT# R563 1 2 4.7K_0402_5% LID_SW# 16 103 EC_SWI# R560 150K_0402_5%
    <34> LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# <21,27>
    CEC_INT# 17 104 SB_PWRGD D33
    <18> CEC_INT# SUSP#/GPIO0B ICH_PWROK/GPXO06 SB_PWRGD <21,43>
    18 GPO 105 BKOFF# ACIN_D 2 1
    3 PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <17> ACIN <22,34,36> 3
    BT_PWR 19 GPIO 106 WLAN_XMIT_OFF#
    <31> BT_PWR EC_PME#/GPIO0D WL_OFF#/GPXO09 WLAN_XMIT_OFF# <27>
    25 107 HDMI_HPD_R CH751H-40PT_SOD323-2
    <6,21> H_THERMTRIP# EC_THERM#/GPIO11 GPXO10 HDMI_HPD_R <18>
    FAN_SPEED1 28 108 STB_WLAN
    <4> FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 STB_WLAN <35>
    <35> VLDT_EN 29 FANFB2/GPIO15 2 1
    E51_TXD 30 C326 100P_0402_50V8J
    <32> E51_TXD UWB_OFF# EC_TX/GPIO16 ENCODER_DIR
    <27> UWB_OFF# 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 ENCODER_DIR <30>
    ON/OFFBTN# 32 112 ENBKL <11,19>
    <34> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2
    PWR_SUSP_LED 34 114 EAPD_CODEC <29>
    <34> PWR_SUSP_LED NUM_LED# PWR_LED#/GPIO19 GPXID3
    <32> NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# <22>
    116 SUSP#
    GPXID5 SUSP# <19,27,29,35,40>
    C813 117 PWRBTN_OUT#
    GPXID6 PWRBTN_OUT# <21>
    15P_0402_50V8J 118 LAN_PCIE_WAKE#
    GPXID7 LAN_PCIE_WAKE# <26>
    1 2 CRY2 122 XCLK1
    123 XCLK0 V18R 124 2 1
    C814 4.7U_0805_10V4Z
    1

    AGND

    Y7
    GND
    GND
    GND
    GND
    GND

    2 1 @
    NC OSC R545
    3 4 20M_0402_5% KB926QFC0_LQFP128_14X14
    EC DEBUG port
    11
    24
    35
    94
    113

    69

    NC OSC
    2

    @ 32.768KHZ_12.5PF_9H03200413
    JP34
    1 1 2 CRY1 +3VL_EC
    1 +5VL
    2 2
    3 E51_TXD C815
    ECAGND

    3
    1

    4 15P_0402_50V8J
    4 L80
    ACES_85205-0400 +EC_AVCC 0_0603_5%
    2

    L81
    1 2 2 1
    4 C816 0.1U_0402_16V4Z 0_0603_5% 4

    /
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 33 of 45
    A B C D E
    A B C D E

    Touch/B Connector FUN/B Connector


    Power Button/ PWR/B
    JTOUCH JCS
    JPOWER
    +5VS 2 R111 1 +5VS_TOUCH 1 1 +5VALW R113 2 0_0603_5%
    1 +5VALW_CS 1 1
    1 POWER_ON_LED 0_0603_5% 2 +5VL R114 2 0_0603_5%
    1 +5VL_CS 2
    1 <33> TP_CLK 2 2
    2 SWB_SUSPLED 2 <33> 3 R524 1 0_0402_5%
    2 3
    2 TP_DATA 3 <33> CAP_INT# 3
    +3VL 5 3 ON/OFFBTN# 4 4
    GND 3 C713 <32> TP_SWL 4 4
    6 GND 4 4 <32> TP_SWR 5 5 <18,33,37> SMB_EC_DA1 5 5
    1U_0402_6.3V4Z 6 6
    6 <18,33,37> SMB_EC_CK1 6

    2
    1 ACES_85201-04051 1 1
    7 GND 7 GND

    1
    R512 @ 8 @ @ @ 8
    GND GND

    1
    @ 1 1 1

    C861 10P_0402_50V8J

    C855 10P_0402_50V8J

    C860 10P_0402_50V8J
    SW5 100K_0402_5% R112 ACES_85201-06051 2 ACES_85201-06051
    0_0603_5% @ 1 R115 @
    51_ON# <36>

    1
    1 3 ON/OFFBTN# 3 0_0603_5%
    ON/OFFBTN# <33>

    2
    D59 D60 2 2 2
    TOP side

    2
    2 4 PJDLC05_SOT23-3 PJDLC05_SOT23-3 D83
    PJDLC05_SOT23-3
    SMT1-05-A_4P
    6
    5

    1
    D

    1
    2 2N7002_SOT23-3
    SW6 @ <33,35> EC_ON G

    2
    1 3 Q19 S

    3
    R514
    BTM side 2 4 10K_0402_5%

    SMT1-05-A_4P
    6
    5

    1
    debug phase using
    +3VALW

    U34
    APX9132ATI-TRL_SOT23-3
    ACIN <22,33,36>
    DC-IN LED LED/B Connector 2 3

    GND
    VDD VOUT LID_SW# <33>
    5

    Vf=2.8V(typ),3.15V(max)
    D54 JLED
    +5VALW 1 2 2 1 3 4 +5VS 2 4 1 1

    1
    2 R515 120_0402_5% LEDB_LED# 2 NC2 2
    1 1 NC1 3
    HT-F196BP5_WHITE another at page28 C645 C647
    QC1B ACES_85204-0200N 0.1U_0402_16V4Z 10P_0402_50V8J
    <BOM Structure>
    2N7002DW-T/R7_SOT363-6 @ 2 2

    POWER LED

    1
    D
    D55 VR_LED 2 Q51
    +5VS 1 2 2 1 G 2N7002_SOT23-3
    R516 120_0402_5% S

    3
    HT-F196BP5_WHITE
    1 2 POWER_ON_LED
    R544 120_0402_5%

    WL&BT LED WL_AMBER_LED# <33>


    GPS LED Vf=3.3V(typ),3.9V(max) Screw Hole
    D75
    2

    WLAN@ +5VS 1 2 2 1 LED_WIMAX# <27>


    R568 R778 300_0402_5% H2 H3 H4 H6 H7 H8 H9 H10
    +5VS 2 1 6 1 @ HT-110NB5 1204 BLUE
    @
    10K_0402_5% H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

    1
    WLAN@ Q158A @ @ @ @ @ @ @ @
    5

    2N7002DW-T/R7_SOT363-6
    D50 SUSPEND LED
    +5VS 1 2 2 1 3 4 H12 H13 H14 H15 H11
    R550 300_0402_5% +3VALW
    WLAN@ HT-110UD_1204
    Q158B H_3P0 H_3P0 H_3P0 H_3P0 H_5P0
    WLAN@

    1
    3

    Vf=1.9V(typ),2.4V(max) 2N7002DW-T/R7_SOT363-6 47K @ @ @ @ @


    WLAN@ Q27

    10K 2
    3 PWR_SUSP_LED <33> 3
    H16 H37

    DTA114YKAT146_SOT23-3 H_3P0N H_5P0X3P0N

    1
    D49 @ @
    Logo LED
    1

    D18 1 2 2 1
    HT-SV116BP_WHITE R521 120_0402_5% HT-191UD_AMBER_0603
    1 2
    1 2 SWB_SUSPLED MINI CARD-1 H32 H34 CPU H20 H22 H19 H21
    VR_LED <33>
    R522 120_0402_5%
    2
    G

    @ D71 @ R529 @ H_3P8 H_3P8 H_3P7 H_3P8 H_4P6X3P8 H_4P6X3P8

    1
    +5VS 1 R526 2 1 2 2 1 1 2 LOGO_LED#
    1 3 @ @ @ @ @ @
    0_0402_5% R774 120_0402_5% HT-110TW_WHITE 0_0402_5%
    D

    2N7002_SOT23-3 MINI CARD-2 H28 H31 VGA H25 H26 H30


    D73 @ Q30
    LOGO_LED# 1 R527 2 1 2 2 1 1 R531 2 +5VS
    BATT CHARGE/FULL LED
    0_0402_5% R776 120_0402_5% HT-110TW_WHITE 0_0402_5% D38 H_3P8 H_3P8 H_4P0 H_4P0 H_4P0

    1
    +5VALW 1 2 2 1 @ @ @ @ @
    BAT_LED# <33>
    R549 300_0402_5% HT-191UD_AMBER_0603
    D56
    1 2 1 2 2 1 MINI CARD-3 H24 MDC H27 H33
    BATT_FULL_LED# <33>
    R542 120_0402_5%
    HT-F196BP5_WHITE
    D19 H_11P0X4P0N H_1P2 H_1P2

    1
    HT-SV116BP_WHITE @ @ @
    +5VALW @ C199 1 2 0.22U_0603_16V4Z

    @ C200 1 2 0.22U_0603_16V4Z

    @ C201 1 2 0.22U_0603_16V4Z
    PCB Fedical Mark PAD
    4 EMI reserve 4
    @ C202 1 2 0.22U_0603_16V4Z FD1 FD2 FD3 FD4

    HDD LED SATA_LED# <22>


    @ C203 1 2 0.22U_0603_16V4Z @ @ @ @
    2

    1
    +5VS 2 R546 1 6 1
    10K_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    5

    D46 Q18A 2008/04/14 2009/04/14 Title


    Issued Date Deciphered Date
    1 2 2 1 3 4 2N7002DW-T/R7_SOT363-6
    +5VS
    R548 120_0402_5%
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    HT-F196BP5_WHITE AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Q18B
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    2N7002DW-T/R7_SOT363-6
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 34 of 45
    A B C D E
    A B C D E

    +5VL +5VL

    +3VALW TO +3V_LAN

    1
    R595 R596
    +3V_LAN
    +3VALW TO +3VS 100K_0402_5% 100K_0402_5%
    +5VALW TO +5VS

    2
    +3VALW +3VS SYSON# SUSP
    <42> SYSON# SUSP <42>

    2
    +5VALW +5VS +5VALW
    4.7U_0805_10V4Z
    R635 +3VALW
    1 1

    6
    1 1 Q14 C839 C838 4.7U_0805_10V4Z 470_0805_5%
    1 Q35 C833 C835 STAR@ Vgs=-4.5V,Id=3A,Rds<97mohm Q142B Q142A 1
    8 1

    6 1
    D S R17 2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6
    8 D S 1 7 D S 2
    2 2 100K_0402_5% Q38
    7 D S 2 6 D S 3 <27,33,41> SYSON 5 2 SUSP# <19,27,29,33,40>

    2
    2 2 Q154A STAR@ AO3413_SOT23
    6 3 5 4

    1
    D S D G

    3
    S
    5 4 1U_0402_6.3V4Z STAR@ STAR@ PJ29

    1
    D G 1U_0402_6.3V4Z SI4800BDY_SO8 RUNON WOL_EN#
    G
    2 R152 1 +VSB 2 1 2 2 JUMP_43X79

    0.01U_0402_25V7K
    4.7U_0805_10V4Z
    SI4800BDY_SO8 1 1 750K_0402_1% R19 1K_0402_1% @

    1
    +3V_LAN

    1
    4.7U_0805_10V4Z

    1 2N7002DW-T/R7_SOT363-6 STAR@ 2
    D

    1
    1
    C840 R556 D C182

    1
    C864 RUNON C834 2 SUSP 1000P_0402_50V7K
    2 2 10M_0402_5% G STAR@

    3
    2 S Q17 1
    1 1

    3
    2N7002_SOT23-3 2N7002DW-T/R7_SOT363-6
    Q154B C679 C680 1U_0402_6.3V4Z +5VL +5VL
    5 STAR@ 4.7U_0805_10V4Z STAR@
    <33> WOL_EN
    @ 2 2

    1
    4
    1
    R598
    R18 R597 100K_0402_5%
    100K_0402_5% 100K_0402_5%
    STAR@

    2
    2
    +1.8V TO +1.8VS VLDT_EN# EC_ON#
    +1.2VALW TO +1.2V_HT

    3
    +1.8V +1.8VS +1.2V_HT
    +1.2VALW Q143B
    +3VALW TO +3V_WLAN 2N7002DW-7-F_SOT363-6
    Q11 1 1 VLDT_EN 2 5
    IRF8113PBF_SO8 <33> VLDT_EN EC_ON <33,34>
    Q4 1 2 C846 C862 4.7U_0805_10V4Z Q143A
    IRF8113PBF_SO8 C848 8 1 2N7002DW-7-F_SOT363-6

    4
    2
    8 1 C841 7 2 +3V_WLAN 2
    2 2
    7 2 10U_0805_10V4Z 6 3
    2 1
    6 3 5

    2
    5 1U_0402_6.3V4Z +5VALW
    1U_0402_6.3V4Z

    4
    1

    +3VALW
    4.7U_0805_10V4Z

    4.7U_0805_10V4Z

    1 1 R685
    4

    2
    R367 2 R233 1 +VSB 470_0805_5%

    0.01U_0402_25V7K
    C842 C847 1K_0402_5% 1 330K_0402_5% @ +3VS

    6 1
    1

    C837 R683

    6
    2 1.8VS_ENABLE R138 2 2 R808 100K_0402_5% Q36
    1 +VSB
    2

    2
    0.01U_0402_25V7K

    1 750K_0402_1% 10M_0402_5% Q12A Q155A @ AO3413_SOT23

    1
    1

    3
    2
    S
    @ @ PJ30

    2
    1

    R809 D VLDT_EN# STB_WLAN#


    G
    +3V_WLAN
    2 2 1 2 2 JUMP_43X79
    2

    10M_0402_5% C849 Q13


    2 SUSP R684 1K_0402_1% @
    2

    1
    2N7002_SOT23-3
    G 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 @ 2
    D

    1
    S C683
    2

    1
    3
    1000P_0402_50V7K
    2N7002DW-T/R7_SOT363-6 @
    Q155B 1
    1 1
    5 @ C682
    <33> STB_WLAN
    4.7U_0805_10V4Z C681
    @ 1U_0402_6.3V4Z

    4
    1
    2 2 @
    R686
    @ +3VALW
    100K_0402_5%

    2
    Discharge circuit R24
    100K_0402_5%
    @
    +5VS +1.8VS +1.2V_HT +1.8V +1.2VALW

    1
    3 3
    SBPWR_EN#
    2

    1
    R239 R279 R280 R284 R368 D
    470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% @ 470_0805_5% 2 Q15
    <33> SBPWR_EN
    G 2N7002_SOT23-3
    +3VALW TO +3V_SB S @
    1

    3
    1
    R20
    1

    D D D D +3VALW +3V_SB 100K_0402_5%


    SUSP
    2 SUSP 2 2N7002DW-T/R7_SOT363-6 SYSON# 2 EC_ON# 2 PJ31 @
    G G Q12B G G 2 1

    2
    Q46 Q48 VLDT_EN# 5 Q41 @ Q42 2 1
    S S S S
    3

    2N7002_SOT23-3 2N7002_SOT23-3 2N7002_SOT23-3 2N7002_SOT23-3 Q39 @ JUMP_43X79


    Vgs=10V,Id=6A,Rds=35mohm
    4

    D
    6

    S
    1 5 4 1U_0402_6.3V4Z
    C707 2 1 1

    2
    10U_0805_10V4Z 1 C712
    @ 4.7U_0805_10V4Z C684 R689

    G
    2 @ @ 470_0805_5%

    3
    +3VS +0.9V @ 2 2 @
    +1.5VS +1.1VS 2 1 SI3456BDV-T1-E3_TSOP6
    +VSB

    6 1
    R687 20K_0402_5%
    2

    1
    @ 1
    2

    R288 R292 R688 C685 Q157A


    470_0805_5% 470_0805_5% R293 R294 Q157B 330K_0402_5% 0.1U_0402_25V4Z @
    470_0805_5% 470_0805_5% SBPWR_EN# 5 @ @ @ 2 SBPWR_EN#
    2
    1

    2
    2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
    1

    1
    1

    D D
    1

    4 SUSP SYSON# D D 4
    2 2
    G G SUSP 2 SUSP 2
    Q47 S Q49 S G G
    3

    2N7002_SOT23-3 2N7002_SOT23-3 Q50 S Q52 S


    3

    2N7002_SOT23-3 2N7002_SOT23-3

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 35 of 45
    A B C D E
    A B C D

    VIN
    PL1 PR1
    PF1 SMB3025500YA_2P 1M_0402_1%
    DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2 1 2
    VIN
    PJP1 VS
    1 10A_125V_451010MRL
    +

    1
    1

    1
    2 PR3
    + PC1 PC2 PC3 PC4 84.5K_0402_1%
    3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J PR4

    2
    -

    8
    PU1A 22K_0402_1%
    PR2

    2
    4 3 1 2

    P
    1 1
    - PR5 +
    1 2 1 0
    <22,33,34> ACIN

    20K_0402_1%
    @ SINGA_2DW-0005-B03 2
    -

    1
    0_0402_1% 10K_0402_1%

    PR6
    0.1U_0603_25V7K
    LM358DT_SO8 PC5

    4
    PR7 PD2 1000P_0402_50V7K

    2
    PC6
    10K_0402_1% GLZ4.3B_LL34-2

    2
    2

    2
    VIN

    1 2
    RTCVREF

    2
    PR8
    PD3 10K_0402_1%
    RLS4148_LL34-2

    1
    BATT+ 2 1

    1
    PD4 PR9 PR10
    RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
    TP0610K-T1-E3_SOT23-3 Vin Detector
    PR11

    2
    200_0603_5%
    CHGRTCP 1 2 N1 3 1 VS High 18.384 17.901 17.430
    2
    Low 17.728 17.257 16.976 2
    1

    1
    PC8
    PR12 PC7 0.1U_0603_25V7K
    100K_0402_1% 0.22U_1206_25V7K
    RTC Battery
    2

    2
    2

    2
    <34> 51_ON# 1 2
    PR13
    22K_0402_1%
    - PBJ1 +
    2 1 +RTCBATT +RTCBATT
    RTCVREF
    1

    PR14
    200_0603_5% @ MAXEL_ML1220T10
    PR15 PR16 PU2 G920AT24U_SOT89-3
    560_0603_5% 560_0603_5% 3.3V
    2

    1 2 1 2 3 2 N2
    +CHGRTC OUT IN
    SP093MX0000
    1

    GND
    PC9 PC10
    10U_0805_10V4Z 1
    2

    1U_0805_25V4Z

    3 3

    PJ1 PJ2
    PJ3
    +3VALWP 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V
    VL 2 2 1 1 +5VL
    @ JUMP_43X118 @ JUMP_43X118
    (5A,200mils ,Via NO.= 10) PJ4 @ JUMP_43X39
    2 2 1 1 (100mA,40mils ,Via NO.= 2)
    PJ5
    +5VALWP 2 1 +5VALW @ JUMP_43X118
    2 1
    (12A,480mils ,Via NO.= 24)
    @ JUMP_43X118
    PJ6
    (5A,200mils ,Via NO.= 10)
    PJ7 +3VLP 2 1 +3VL
    +1.2VALWP +1.2VALW 2 1
    PJ8 2 2 1 1
    @ JUMP_43X39
    +VSBP 2 1 +VSB @ JUMP_43X118 (100mA,40mils ,Via NO.= 2)
    2 1
    (5A,200mils ,Via NO.=10)
    @ JUMP_43X39
    PJ9
    (120mA,40mils ,Via NO.= 1) +NB_COREP 2 1 +NB_CORE
    2 1
    @ JUMP_43X118
    PJ10 (7.0A,280mils ,Via NO.=14)
    +VDDNBP 2 1 +VDDNB
    2 1
    PJ11
    4 @ JUMP_43X118 4

    +2.5VSP 2 1 +2.5VS
    2 1
    (3A,120mils ,Via NO.=6)
    @ JUMP_43X39
    (0.5A,20mils ,Via NO.=1)
    PJ12
    2 1
    +0.9VP 2
    @ JUMP_43X79
    1 +0.9V
    +1.5VSP
    PJ13
    +1.5VS
    Security Classification Compal Secret Data Compal Electronics, Inc.
    2 2 1 1 Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    (2A,80mils ,Via NO.= 4)
    @ JUMP_43X79
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    (2.0A,80mils ,Via NO.=4) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 36 of 45
    A B C D
    A B C D

    PH1 under CPU botten side :


    CPU thermal protection at 92 degree C
    Recovery at 56 degree C
    VMB VL
    PF2 PL2 VL ENTRIP1 <39>
    1
    PJP2 15A_65V_451015MRL SMB3025500YA_2P VL 1

    1 BATT_S1 1 2 1 2
    1 BATT+
    2 2

    2
    3 3 1 2 1 2 +3VLP
    4 PR17 PR18 PR19
    4

    1
    1K_0402_1% 47K_0402_1% 47K_0402_1% D
    5 5
    10 6 EC_SMDA PC11 PC12 PH1 PC13 2 PQ2
    GND 6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR20 G SSM3K7002FU_SC70-3
    11 7

    1
    GND 7 47K_0402_1%
    12 8 S

    3
    GND 8

    1
    13 9 1 2

    2
    GND 9 PR21 PR22

    8
    @ OCTEK_BTJ-09HA1G 1K_0402_1% 13.7K_0402_1% PU3A
    1 2 3

    P
    +
    1 2 1

    2
    O
    2

    2
    TM_REF1 2 ENTRIP2 <6,39>
    -

    G
    PR23 PR24 PD5
    100_0402_1% 100_0402_1% LM393DG_SO8 RLS4148_LL34-2

    4
    0.22U_0805_16V7K
    1

    1
    D

    15.4K_0402_1%
    1

    1
    PC14
    PR26 2 PQ3

    1000P_0402_50V7K
    PR25
    6.49K_0402_1% G SSM3K7002FU_SC70-3
    2 1 +3VLP 2 1 VL S

    3
    1

    PC15
    PR27

    2
    100K_0402_1%

    2
    1

    1
    PR28
    1K_0402_1%
    PR29
    100K_0402_1%
    2

    2 2

    2
    BATT_TEMPA <33>

    SMB_EC_DA1 <18,33,34>

    SMB_EC_CK1 <18,33,34>
    PH2 near main Battery CONN :
    BAT. thermal protection at 92 degree C
    Recovery at 56 degree C

    VL VL

    PQ4

    2
    TP0610K-T1-E3_SOT23-3

    1
    PR30
    47K_0402_1%
    B+ 3 1 +VSBP PH2 PR31
    100K_0603_1%_TH11-4H104FT 47K_0402_1%

    1
    100K_0402_1%

    0.22U_1206_25V7K

    0.1U_0603_25V7K
    1 2

    2
    1

    1
    PR32

    PC16

    PC17

    PR33

    8
    3 13.7K_0402_1% PU3B 3

    1 2 5

    P
    2

    +
    7 2 1
    2

    TM_REF1 O
    6 -

    G
    VL PR35 PD6

    1
    22K_0402_1% @ @ LM393DG_SO8 RLS4148_LL34-2

    4
    1 2 PC18 PR34
    2

    0.22U_0805_16V7K 15.4K_0402_1%

    2
    PR36

    2
    100K_0402_1%

    PR37
    1

    0_0402_5% D
    1 2 2 PQ5
    <39,40> POK
    G SSM3K7002FU_SC70-3
    0.1U_0402_16V7K

    S
    3
    1

    PC19
    2

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 37 of 45
    A B C D
    A B C D E

    B+
    VIN
    PQ7 PQ6
    PQ8 PR38
    8 D S 1 1 S D 8 1 4 1 S D 8
    7 D S 2 2 S D 7 2 S D 7

    0.01U_0402_25V7K
    6 D S 3 3 S D 6 2 3 3 S D 6

    0.1U_0402_25V4K
    PR39 5 4 4 5 PL16 4 5
    D G G D G D

    100K_0402_1%
    3.3_1210_5% HCB2012KF-121T50_0805

    1
    0.015_2512_1% 1 2 CHG_B+

    1
    PC141

    PC20

    PR40
    0.01U_0402_25V7K
    FDS4435BZ_SO8 FDS4435BZ_SO8 FDS4435BZ_SO8

    2 1

    100K_0402_1%
    0.01U_0603_50V7K

    4.7U_1206_25V6K

    4.7U_1206_25V6K

    4.7U_1206_25V6K
    PQ9

    1
    1

    2
    2

    2
    PC21

    PR42
    1 PR41 @ 1

    CHGEN#
    1 8

    2
    S D

    PC22

    PC23

    PC24
    3.3_1210_5% 2 7
    S D

    PC25
    PC26 PC27 3 6

    1
    S D

    5
    6
    7
    8
    0.1U_0402_16V7K PU4 0.1U_0805_25V7K /BATDRV 4 5

    1 1

    2
    G D
    1 2 1 CHGEN PVCC 28 1 2
    PC28

    1
    2.2U_0805_25V6K PR43 @ FDS4435BZ_SO8
    PC29 PC30 0_0603_5% PQ10
    2

    0.1U_0603_25V7K @0.1U_0603_25V7K 27 1 2 4 AO4466_SO8

    2
    BTST

    2
    PR44
    340K_0402_1% 2 26
    ACN HIDRV
    3

    3
    2
    1
    ACP PR45

    1
    4 25 PL3 0.02_2512_1%
    ACDET ACDRV PH PD7 10UH_SIL1045RA-100PF_4.5A_30%
    5 ACDET
    2 1 1 2 1 2 1 4

    10U_1206_25V6M

    10U_1206_25V6M
    RLS4148_LL34-2 PC31 BATT+

    REGN
    2 3
    2

    1
    PR47 0.1U_0603_25V7K

    5
    6
    7
    8

    1
    PC32

    PC33
    PR46 100K_0402_1%
    54.9K_0402_1% 1 2 ACSET 6
    VREF

    2
    ACSET PC34
    24

    2
    REGN

    1
    0.1U_0402_16V7K
    1

    1
    PR48 PC36 PQ11 1 2
    PC35 120K_0402_1% 1U_0603_10V6K 4 AO4466_SO8
    @ 0.01U_0402_25V7K

    2
    2

    1
    2
    1 2 7 ACOP PC38 PC39
    PR49 PC37 23 0.1U_0603_25V7K @0.1U_0603_25V7K

    3
    2
    1

    2
    340K_0402_1% 0.47U_0603_16V7K LODRV
    1

    2 2
    PGND 22
    OVPSET 8 OVPSET

    9 AGND LEARN 21 ACOFF <33>


    2

    PR50
    54.9K_0402_1%
    VREF 20 CELLS
    CELLS
    1

    10 VREF
    PQ12
    3

    1
    SI2301BDS-T1-E3_SOT23-3 PC40
    1U_0603_10V6K
    PR51 19

    2
    100K_0402_1% SRP
    RTCVREF
    1 2 2 11 VDAC SRN 18

    BAT 17
    1

    VREF

    1
    PC41 VADJ 12
    VREF 0.1U_0603_25V7K PR52 VADJ PC42
    2

    1
    1

    ACSET 100K_0402_1% 0.1U_0603_25V7K

    2
    PR53 29
    1

    200K_0402_1% ACGOOD# TP
    13 ACGOOD
    1

    D
    PR55
    2

    PR54 2 PQ13 16 2 1 IREF <33>


    100K_0402_1% G SSM3K7002FU_SC70-3 /BATDRV SRSET
    14 BATDRV 49.9K_0402_1%

    1
    S
    2

    3
    1

    1
    D
    PR56
    ACOFF 1 2 2 PQ14 15 1 2 100K_0402_1% PC44
    3 G SSM3K7002FU_SC70-3 IADAPT @0.01U_0402_25V7K 3

    2
    1

    PC43 S BQ24751ARHDR_QFN28_5X5 PR57


    3

    2
    0.1U_0402_16V7K PR58 10_0603_5%
    340K_0402_1% REGN

    1
    PC45
    2

    100P_0402_50V8J

    2
    1

    PR59 IREF Current


    75W,Iadapter=3.947A,PR38=0.015ohm,PR47=100K,PR48=120K,CP=3.63A @ 0_0402_5%
    PR60
    90W,Iadapter=4.736A,PR38=0.015ohm,PR47=54.9K,PR48=100K,CP=4.357A 210K_0402_1% 2.968V 3A
    2

    <33> CHGVADJ 1 2 VADJ CHGVADJ Pre Cell


    120W,Iadapter=6.316A,PR38=0.01ohm,PR47=71.5K,PR48=100K,CP=5.81A
    1

    1.484V 1.5A
    PR61 3.28V 4.35V
    499K_0402_1%
    VMB
    VREF
    0V 4V
    2
    499K_0402_1% 340K_0402_1%
    1

    VS

    2
    PR62

    CHGVADJ要接到EC DA pin
    PR63
    0.01U_0402_25V7K

    100K_0402_1%
    2

    1
    1

    PC46

    CHGEN#
    PR64
    2

    1
    D
    PQ15
    LI-3S :13.5V----BATT-OVP=1.5V <33> FSTCHG 2
    G SSM3K7002FU_SC70-3
    2
    8

    4 PR65 PU1B 4
    BATT-OVP=0.111*BATT+ S

    3
    10K_0402_1% 5
    P

    +
    <33> BATT_OVP 1 2 7 0
    - 6
    G

    105K_0402_1%
    1

    0.01U_0402_25V7K

    LM358DT_SO8
    4

    1
    PR66

    PC47

    Security Classification Compal Secret Data Compal Electronics, Inc.


    2

    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title


    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 38 of 45
    A B C D E
    A B C D

    2VREF_51125

    0.22U_0603_10V7K
    1 1

    1
    PC48

    2
    PR67 PR68
    13K_0402_1% 30K_0402_1%
    1 2 1 2

    PR69 PR70
    B++
    20K_0402_1% 20K_0402_1%
    B++
    1 2 1 2

    PJ15
    B+ 2 2 1 1 +3VLP

    ENTRIP2

    ENTRIP1
    2200P_0402_50V7K

    @ JUMP_43X118 PR71 PR72


    10U_1206_25V6M

    10U_1206_25V6M
    150K_0402_1% 150K_0402_1%
    1

    2200P_0402_50V7K
    PC49

    4.7U_0805_10V6K
    1 2 1 2

    1
    PC50

    PC52
    PC51
    2

    2
    6

    5
    6
    7
    8
    PC53
    PU5

    8
    7
    6
    5

    ENTRIP2

    VFB2

    TONSEL

    VFB1

    ENTRIP1
    VREF
    25 PQ16
    2 PQ17 P PAD AO4466_SO8 2

    2
    AO4466_SO8
    7 VO2 VO1 24 POK <37,40> 4
    4
    8 23 PR74 PC55
    PR73 VREG3 PGOOD 0_0603_1% 0.1U_0402_16V7K
    1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

    3
    2
    1
    0_0603_1% VBST2 VBST1
    1
    2
    3

    PL4 PC54 UG_3V 10 21 UG_5V PL5


    4.7U_LF919AS-4R7M-P3_5.2A_20% 0.1U_0402_16V7K DRVH2 DRVH1 4.7U_LF919AS-4R7M-P3_5.2A_20%
    1 2 LX_3V 11 20 LX_5V 1 2
    +3VALWP LL2 LL1
    1

    8
    7
    6
    5

    5
    6
    7
    8

    1
    4.7_1206_5%

    680P_0603_50V7K 4.7_1206_5%
    LG_3V 12 19 LG_5V +5VALWP
    DRVL2 DRVL1
    @ PR75

    @ PR76
    SKIPSEL

    220U_6.3V_M
    PQ18 PQ19

    VREG5
    0.1U_0402_16V7K

    VCLK
    1 AO4712_SO8 AO4712_SO8 1

    GND
    EN0
    1

    VIN
    220U_D2_4VM
    PC142

    0.1U_0402_16V7K
    2

    1
    + +
    PC56

    PC57

    PC143
    4 4
    PR77 TPS51125RGER_QFN24_4X4
    2

    13

    14

    15

    16

    17

    18
    1

    1
    680P_0603_50V7K

    PC59
    @ 499K_0402_1%

    2
    2 2
    PC58

    1 2 @
    B+
    2

    1
    2
    3

    3
    2
    1

    2
    1
    100K_0402_1%
    @
    @

    PR78
    1 2 VL

    PC60
    4.7U_0805_10V6K
    PR79

    2
    @ 0_0402_5%

    2
    ENTRIP1 <37> ENTRIP2 <6,37>
    B++

    1
    3 3

    0.1U_0603_25V7K
    2
    PC61
    1

    D D
    2VREF_51125
    PQ20 2 2 PQ21
    SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
    S S
    3

    VL 2 1

    PR80
    100K_0402_1%
    1

    VS 1 2 2 PQ22
    G SSM3K7002FU_SC70-3
    49.9K_0402_1%

    0.01U_0402_16V7K

    PR81 S
    3
    1

    100K_0402_1%
    1
    PR82

    @ PC62
    2
    2

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 39 of 45
    A B C D
    5 4 3 2 1

    D D

    PR83 PR84 PR85 PR86


    44.2K_0402_1% 75K_0402_1% 75K_0402_1% 33K_0402_1%

    +1.2VALWP 1 2 1 2 2 1 2 1 +NB_COREP 51124_B+


    PL14
    HCB2012KF-121T50_0805
    1 2 B+

    0.1U_0402_25V4K

    0.1U_0402_25V4K

    0.1U_0402_25V4K
    51124_B+

    2
    PR87

    2200P_0402_50V7K
    4.7U_1206_25V6K

    4.7U_1206_25V6K
    0_0402_5%

    1
    PC137

    PC138

    PC139
    1

    1
    PC63

    PC64

    2
    1
    @ @

    PC65
    2

    4.7U_1206_25V6K

    4.7U_1206_25V6K

    2200P_0402_50V7K
    8
    7
    6
    5

    5
    6
    7
    8

    1
    PC66

    PC67
    PU6 PQ24

    1
    GND
    VO2

    VFB2

    TONSEL

    VFB1

    VO1

    PC68
    PQ23 25 AO4466_SO8

    2
    AO4466_SO8 P PAD

    2
    4 7 PGOOD2 PGOOD1 24 4
    PC70
    C PC69 PR88 PR89 C
    8 EN2 EN1 23 0.1U_0402_16V7K
    0.1U_0402_16V7K 0_0603_1% 0_0603_1%
    2 1 2 1 BST_1.2V 9 22 BST_NB_COREP 2 1 1 2
    1
    2
    3

    3
    2
    1
    VBST2 VBST1
    +1.1V
    PL6 UG_1.2V 10 21 UG_NB_COREP PL7
    1.8U_D104C-919AS-1R8N_9.5A_30% DR VH2 DR VH1 1.8U_D104C-919AS-1R8N_9.5A_30% +NB_COREP
    +1.2VALWP 1 2 LX_1.2V 11 20 LX_NB_COREP 1 2
    +1.2VALWP LL2 LL1
    LG_1.2V 12 19 LG_NB_COREP
    DR VL2 DR VL1
    1

    8
    7
    6
    5
    4.7_1206_5%

    5
    6
    7
    8

    4.7_1206_5%
    @ PR90
    0.1U_0402_16V7K

    PGND2

    PGND1
    1

    V5FILT
    TRIP2

    TRIP1
    220U_6.3V_M

    220U_6.3V_M
    @ PR91

    0.1U_0402_16V7K
    4.7U_0805_6.3V6K

    4.7U_0805_6.3V6K
    PQ25 1

    V5IN
    1

    +
    PC144

    PC71

    PC145
    AO4712_SO8 PQ26

    1
    PC72

    PC73
    AO4712_SO8 +
    2

    PC74
    4 TPS51124RGER_QFN24_4x4
    2

    13

    14

    15

    16

    17

    18

    2
    @ 2 @
    4

    2
    1

    2
    680P_0603_50V7K
    PC75

    680P_0603_50V7K
    2

    1
    2
    3

    PC76
    PR93

    3
    2
    1
    @ 13.7K_0402_1% PR92

    2
    1 2 16.5K_0402_1%
    @

    2
    PR94 PR96
    0_0402_5% 22K_0402_5%
    2 1 1 2 +5VALW 1 2
    <37,39> POK SUSP# <19,27,29,33,35>
    PR95
    3.3_0402_5%
    1

    B PC77 B
    1

    1
    @ 0.1U_0402_16V7K PC78 PC79 PC80
    1U_0603_10V6K 4.7U_0805_10V6K 0.1U_0402_16V7K
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 40 of 45
    5 4 3 2 1
    5 4 3 2 1

    PL15
    HCB2012KF-121T50_0805
    51117_B+ 1 2 B+

    0.1U_0402_25V4K
    4.7U_1206_25V6K

    4.7U_1206_25V6K

    1
    PC140
    D D

    1
    PC81

    PC82

    2
    5
    6
    7
    8

    2
    PQ27
    AO4466_SO8 @

    PR97
    255K_0402_1% 4
    1 2
    PR98 PR99
    0_0402_5% 0_0603_1%
    <27,33,35> SYSON 1 2 1 2

    3
    2
    1
    <BOM Structure>

    1
    PL8

    15

    14
    PC84

    1
    PC83 PU7 1.8U_D104C-919AS-1R8N_9.5A_30%
    @0.1U_0402_16V7K BST_1.8VP 1 2 1 2

    EN_PSV

    TP

    VBST
    +1.8VP

    2
    2 13 DH_1.8VP 0.1U_0603_25V7K
    TON DRVH

    680P_0603_50V7K @ 4.7_1206_5%
    PR101 3 12 LX_1.8VP
    VOUT LL

    5
    6
    7
    8

    PR100
    422_0603_1% 1

    220U_D2_4VM

    0.1U_0402_16V7K
    +5VALW 1 2 4 11 1 2 +5VALW PQ28
    V5FILT TRIP

    1
    +

    PC85

    PC146
    PR102 AO4712_SO8

    2
    5 10 15.4K_0402_1% 1 2 <BOM Structure>
    VFB V5DRV

    2
    1

    1
    PC89 2 @
    6 PGOOD DRVL 9 4

    PGND

    PC87
    PC86 4.7U_0805_10V6K

    GND
    1U_0603_10V6K PC88 DL_1.8VP

    2
    @ 47P_0402_50V8J
    1 2 TPS51117RGYR_QFN14_3.5x3.5

    3
    2
    1
    C C

    PR103 @
    28.7K_0402_1%
    1 2

    1 PR104
    20.5K_0402_1%
    2

    B B

    PU8
    APL5508-25DC-TRL_SOT89-3
    PJ18
    +3VS
    1 1 2 2 2 IN OUT 3 +2.5VSP
    @ JUMP_43X39
    GND
    1

    PC90 1 PC91
    1U_0603_10V6K 4.7U_0805_6.3V6K
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 41 of 45
    5 4 3 2 1
    5 4 3 2 1

    +3VS
    D D

    1
    PJ19

    1
    @ JUMP_43X79

    2
    PU9

    2
    1 VIN VCNTL 6 +5VALW
    2 GND NC 5

    1
    1
    PC92 3 7 PC93
    4.7U_0805_6.3V6K VREF NC 1U_0603_6.3V6M

    2
    PR105 4 8
    1.15K_0402_1% VOUT NC
    9

    2
    TP
    APL5331KAC-TRL_SO8

    +1.5VSP

    1
    PR106

    1
    D 1K_0402_1%

    1
    SUSP 1 2 2
    <35> SUSP
    PR107 G PC94 PC95

    1
    0_0402_5% S PQ29 0.1U_0402_16V7K 10U_0805_6.3V6M

    2
    PC96 SSM3K7002FU_SC70-3
    @ 0.1U_0402_16V7K

    2
    C C

    +1.8V

    1 1 PJ20
    @ JUMP_43X79
    2

    PU10
    2

    1 VIN VCNTL 6 +3VALW


    2 GND NC 5
    1

    1
    B PC97 B
    1
    4.7U_0805_6.3V6K 3 7 PC98
    PR108 VREF NC 1U_0603_6.3V6M
    2

    2
    1K_0402_1% 4 8
    VOUT NC
    9
    2

    TP
    APL5331KAC-TRL_SO8
    1

    PR110 +0.9VP
    1

    0_0402_5% D PR109
    1 2 2 1K_0402_1% PC99
    <35> SYSON# 1
    G 0.1U_0402_16V7K
    2
    1

    S PQ30 PC100
    3

    PC101 SSM3K7002FU_SC70-3 10U_0805_6.3V6M


    2

    @ 0.1U_0402_16V7K
    2

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 42 of 45
    5 4 3 2 1
    A B C D E

    CPU_B+ PL13 PL9


    HCB2012KF-121T50_0805 HCB4532KF-800T90_1812
    PC102 1 2 1 2 B+

    10U_1206_25V6M

    0.1U_0402_25V4K

    0.1U_0402_25V4K

    0.1U_0402_25V4K

    0.1U_0402_25V4K
    33P_0402_50V8K

    220U_25V_M

    @ 220U_25V_M

    0.1U_0402_25V4K
    2 1 1 1

    5
    6
    7
    8

    1
    + +

    PC106

    PC103

    PC104

    PC136

    PC135

    PC132

    PC134
    PC133
    2 1 2 1

    2
    PR111 PC105 2 2 @ @
    44.2K_0402_1% 1000P_0402_50V7K UGATE_NB 4 PQ31
    PR112 AO4466_SO8
    1 2_0603_5% 1

    +5VS 1 2 PC107 PL10


    1000P_0402_50V7K 4.7U_LF919AS-4R7M-P3_5.2A_20%

    3
    2
    1
    2 1 PHASE_NB 1 2 +VDDNBP
    PR113

    5
    6
    7
    8

    1
    PC108 PR115 0_0603_5%
    0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 PR114
    2 1 @ 4.7_1206_5% 1

    2
    PR116 PC109 PJ21
    10_0402_5% 0.22U_0603_10V7K PQ32 + PC110 2 1

    1 2
    220U_D2_4VM 2 1
    1 2+VDDNBP LGATE_NB 4 AO4712_SO8
    CPU_B+ 1 2 PR118 PC111 @ JUMP_43X118
    0_0402_5% @ 680P_0603_50V7K 2
    PR117 2 1 PJ22
    CPU_VDDNB_RUN_FB_H <6>

    2
    2_0603_5% PR119 +CPU_CORE_0 2 1 +CPU_CORE_1

    3
    2
    1
    +5VS +3VS 11.3K_0402_1% 2 1
    2 1 PHASE_NB @ JUMP_43X118

    LGATE_NB PJ23

    1
    PC112 CPU_B+ 2 1
    0.1U_0603_25V7K PHASE_NB 2 1
    1

    1
    @ JUMP_43X118

    2
    PR120 PR121 UGATE_NB

    10U_1206_25V6M

    10U_1206_25V6M
    0_0402_5% @ 105K_0402_1%

    5
    2 1 CPU_VDDNB_RUN_FB_L <6>
    PR122
    2

    2
    1

    1
    PC113

    PC114
    0_0402_5%
    PR124 PQ33
    PR123 @ 10K_0402_1% PR125 SI7686DP-T1-E3_SO8

    2
    105K_0402_1% 10_0402_5% UGATE0 4
    1

    48

    47

    46

    45

    44

    43

    42

    41

    40

    39

    38

    37
    2

    1
    PR126 PU11
    2 @ 105K_0402_1% PHASE0 PL11 2

    FB_NB

    COMP_NB

    FSET_NB

    VSEN_NB

    OCSET_NB

    LGATE_NB

    UGATE_NB
    VIN

    VCC

    RTN_NB

    PGND_NB

    PHASE_NB
    PR127 0.36UH_PCMC104T-R36MN1R17_30A_20%

    3
    2
    1
    0_0603_5%
    2

    <33> VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 4 +CPU_CORE_0


    OFS/VFIXEN BOOT_NB
    1 2
    <6,20> H_PWRGD @ PR129 100K_0402_5% 2 35 BOOT0 PC115 2 3
    PGOOD BOOT0

    5
    6
    7
    8

    5
    6
    7
    8
    1 2 0.22U_0603_10V7K

    1
    <21,33> SB_PWRGD PR158 100K_0402_5% ISL6265_PWROK 3 34 UGATE0
    PWROK UGATE0

    2
    PR130
    <6> CPU_SVD 2 1 4 33 PHASE0 @ 4.7_1206_5% PR128
    <6> CPU_SVC PR131 SVD PHASE0 PQ35 3.65K_0402_1%
    0_0402_5%2 1 5 32 PQ34 4 4 SI4634DY-T1-E3_SO8

    1 2
    <33> CPU_VCORE_ENABLE PR132 SVC PGND0 +5VS SI4634DY-T1-E3_SO8

    1
    PR133 PR134 0_0402_5% 6 31 LGATE0 PC116 PC117
    113K_0402_1% 4.02K_0402_1% ENABLE LGATE0 @ 680P_0603_50V7K 2 1
    2 1 2 1 7 30

    3
    2
    1

    3
    2
    1

    2
    RBIAS ISL6265HRTZ-T_QFN48_6X6 PVCC 0.1U_0603_16V7K
    8 29 LGATE1
    OCSET LGATE1

    1
    PC118 2 1
    9 28 1U_0603_16V6K LGATE0
    VDIFF0 PGND1 PR136

    ISN0
    ISP0
    10 27 PHASE1 47K_0402_1%
    FB0 PHASE1
    11 26 UGATE1
    COMP0 UGATE1 CPU_B+
    12 25 BOOT1
    VW0 BOOT1
    COMP1
    VDIFF1
    VSEN0

    VSEN1
    RTN0

    RTN1
    ISN0

    ISN1
    ISP0

    VW1

    ISP1
    FB1

    10U_1206_25V6M

    10U_1206_25V6M
    TP

    5
    PR137
    +CPU_CORE_0 2 1
    13

    14

    15

    16

    17

    18

    19

    20

    21

    22

    23

    24

    49

    1
    PC119

    PC120
    10_0402_5%
    3 ISP0 PQ36 3
    PR135 ISN0 SI7686DP-T1-E3_SO8

    2
    ISN1
    ISP1

    0_0402_5% UGATE1 4
    2 1 VSEN0
    <6> CPU_VDD0_RUN_FB_H 0_0402_5%
    2 PR138 1 RTN0 PHASE1 PL12
    <6> CPU_VDD0_RUN_FB_L PR139 0.36UH_PCMC104T-R36MN1R17_30A_20%

    3
    2
    1
    2 1RTN1 0_0603_5%
    <6> CPU_VDD1_RUN_FB_L PR140 BOOT1 1 2 1 2 1 4 +CPU_CORE_1
    2
    10_0402_5%

    10_0402_5%

    0_0402_5%
    PR143 2
    PR142

    PC121 2 3

    5
    6
    7
    8

    5
    6
    7
    8
    0.22U_0603_10V7K

    2
    PR144
    1

    @ 4.7_1206_5% PR141
    1

    PQ38 3.65K_0402_1%
    PR145 PQ37 4 4 SI4634DY-T1-E3_SO8

    1 2
    0_0402_5% SI4634DY-T1-E3_SO8

    1
    <6> CPU_VDD1_RUN_FB_H 2 1 VSEN1 PC122 PC123
    @ 680P_0603_50V7K 2 1
    +CPU_CORE_1 2 PR146 1

    3
    2
    1

    3
    2
    1

    2
    10_0402_5% 0.1U_0603_16V7K

    DIFF_0 VW0 DIFF_1 VW1 2 1


    LGATE1
    PR147 PC124 PR148 PC127 PR157

    ISN1
    ISP1
    255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K 47K_0402_1%
    2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1

    PC125 PC126 PC128 PC129


    180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K

    4 PR149 PR151 PR152 PR154 4


    1K_0402_5% PR150 PC130 6.81K_0402_1% 1K_0402_5% PR153 PC131 6.81K_0402_1%
    2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

    54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K


    1

    PR155 PR156
    @ 36.5K_0402_1% @ 36.5K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title
    SCHEMATIC MB A4581
    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 43 of 45
    A B C D E
    A B C D E

    Version Change List ( P. I. R. List ) for Power Circuit


    Item Page# Title Date Request Rev.
    Owner Issue Description Solution Description
    1
    43 Add PR158 remove PR129 2008/06/23 HW Code 88 change EC to CPU control signal,PWROK 1

    41 Change UMA PR102 to 15.4K 2008/06/23 POWER OCP to low Change trip resistor.
    42 Change PU10 SUSP to SYSON# 2008/06/23 HW Change control signal
    39 Add PC142,PC143 2008/07/23 SED GPS Reduce GPS noise
    40 Add PC144,PC145 2008/07/23 SED GPS Reduce GPS noise
    41 Add PC146,Change PC85 2008/07/23 SED,ME GPS Reduce GPS noise

    2 2

    3 3

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Tuesday, August 04, 2009 Sheet 44 of 45
    A B C D E
    5 4 3 2 1

    HW4 Product Improvement Record (P.I.R.)


    Revision Change: 0.1 to 0.2
    U3 PJP1
    NO DATE PAGE MODIFICATION LIST PURPOSE
    -------------------------------------------------------------------------------------------------------
    D 1 6/20 27 Exchange UIM_RESET and UIM_CLK connect to J3GSIM Correct schematic RS780MC DC-IN D

    2 6/20 21 Change FM_I2CCLK and FM_I2CDAT to GPIO50, GPIO51 For NXP request RS780MC R3 PJP1
    RS780MCR3@ 45@
    3 6/20 25 Remove JHDD1 Remove Dip HDD
    U3 ZZZ
    4 6/20 34 Change Q27.3 to pull up with +3VALW and R521, R522 to 120ohm Solve suspend led issue
    5 6/22 27 Change CM15, CM16 to 10P and un-mount RM1 and CM14 For customer request RX781 PCB
    6 6/23 32 Change ROM from 1M to 2M For BIOS request
    RX781 R3 PCB 03X LA-4581P REV1.0 M/B
    7 6/23 30 Change CA30, CA32 from0.47u to 0.033u Set high pass frequency to 68Hz RX781R3@

    8 6/24 16, 29 Reserve C177, C181, C193 For EMI request


    U20

    Revision Change: 0.2 to 0.3 LAN


    8102E
    NO DATE PAGE MODIFICATION LIST PURPOSE 8102E@
    ------------------------------------------------------------------------------------------------------ UL3
    1 7/14 29 Remove Felica function schematic KTKAE don't support
    2 7/14 18 Change U39.5 from +HDMI_5V_OUT to +5VL For customer request and follow Toshiba deisgn guide with CEC
    C 3 7/18 21 Change internal camera USB port from port 5 to port 9 For USB sleep and charge function C
    10/100M transformer
    4 7/21 27 Change New card SMBus from 1 to 0 For Express card logo 8102E@

    5 7/22 32 Change MDC power from +3VS to +3V_SB Support wake on MDC
    6 7/22 28 Add ESD diode near 1394 connector For EMI request
    7 7/23 22 Add SPI ROM schematic on SB For AMD+ENE issue
    8 7/24 34 Co-layout LOGO LED Change logo led to high illumination R1
    9 7/24 32 Change BIOS ROM from 2M to 1M For SW request
    10 7/24 28 Add D3E mode schematic For Energy star U15

    11 7/24 26 Add LAN saving mode schematic For Energy star


    10 8/8 21 Change R328, R329 to 1.2K For new card recognize issue SB700
    11 8/8 22 Add R557 Correct CIR schematic SB700R1
    SB700R1@
    12 8/8 16 Change R433, R435 from 137 to 150ohm For TV out
    13 8/8 21 Correct HDA SSC schematic For EMI request U3

    14 8/8 Add EMI test schematic For EMI request


    B
    RS780MC B
    RS780MC R1
    Revision Change: 0.3 to 1.0 RS780MCR1@
    NO DATE PAGE MODIFICATION LIST PURPOSE U3
    ------------------------------------------------------------------------------------------------------
    1 8/06 6 CPU thermtrip connection For customer request RS780M
    2 8/11 29 Change Camera power from +5VALW to +5VS For Energy star
    RS780M R1
    3 8/12 32 Delete TEST@ For MP RS780MR1@

    4 8/12 35 Change all +3VALW to +3V_WLAN components from STAR@ to @ No need


    U3
    5 8/12 22 Add R557 Correct CIR schematic
    6 8/13 28 Correct JMB380 schematic For Energy star RX781
    7 8/24 26 Delete R398 No need LAN saving mode function
    RX781 R1
    8 8/24 35 Short PJ31, Delete Q15, R24, R20,Q39,Q157, For SB leakage issue RX781R1@
    R687,R688,R689,C707,C685,C684,C712
    9 8/24 18 Add L85,L86,L87,L88, Delete R616~R621,R623,R624 For EMI request
    10 8/28 33 Change R536 from 100k to 10k For LED twinkle when insert AC issue
    A 11 9/10 26 Remove R399 No DSM function A

    12 9/24 6 Add C24 Add ESD solution

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2008/04/14 Deciphered Date 2009/04/14 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    SCHEMATIC MB A4581
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401606 D
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Wednesday, August 05, 2009 Sheet 45 of 45
    5 4 3 2 1

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