A B C D E

1 1

Compal confidential
Schematics Document
2 2

Mobile Penryn uFCPGA with Intel

Cantiga_GM+ICH9-M core logic
2010-04-08
NCL50 REV:1.0
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 1 of 46
A B C D E
 A B C D E

Compal confidential Montevina 14" UMA

CK505 72QFN
Clock Generator
Thermal Sensor Mobile Penryn/Merom
1 SLG8SP553V 1

EMC1402 uFCPGA-478 CPU P17

P06

P6, 7, 8

Fan conn P06 H_A#(3..35)

FSB
H_D#(0..63) 667/800/1066 MHz 1.05V
DDR3 800/1066MHz
LVDS Panel 1.5V DDR3 SO-DIMM X2
BANK 0, 1, 2, 3 P15, 16
Interface P19
Intel Cantiga MCH
Dual Channel
CRT FCBGA 1329
P18

USB conn x3
P9,10, 11, 12, 13, 14 P30

2 2

USB2.0 X12
DMI X4 C-Link BT Conn
P30

USB Camera
P19
PCI-E BUS*2 Azalia

Intel ICH9-M SATA Master-1

SATA Slave
RTL8103EL Mini-Card mBGA-676
(10/100M) CardReader 3 in1 Slot P27
WLAN P20,21,22,23
RTS5159
P25 P26 P26 P27

RJ45/11 CONN LPC BUS Audio CKT AMP & Audio Jack
P25
3 Codec_AL272 TPA6017A2 3
P28 P28

SATA HDD Connector

P24
ENE
KB926 SATA ODD ConnectorP24
SPI
P31

Touch Pad CONN. Int.KBD

P32 P31

USB Board Conn

USB conn x3 SPI ROM
ZZZ3
SST25VF080P30
4 4

RTC CKT. LED

PCB
P21 P32

Security Classification Compal Secret Data Compal Electronics, Inc.

2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
P33 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 2 of 46
A B C D E
 A

Symbol Note :
Voltage Rails O MEANS ON X MEANS OFF USB assignment:
: means Digital Ground USB-0 Right side daughter board
USB-0 Right side daughter board
USB-2 Left side
: means Analog Ground USB-3 X
power USB-4 Camera
plane
USB-5 WLAN
+B +5VALW +1.8V +5VS @ : means just reserve , no build USB-6 Bluetooth
+1.5V +3VS USB-7 Cardreader
+3VALW +1.5VS
45@ : means need be mounted when 45 level assy or rework stage. USB-8 X
+VCCP DEBUG@ : means just reserve for debug. USB-9 X
State +CPU_CORE USB-10 X
+0.75VS
BATT @ : means need be mounted when 45 level assy or rework stage. USB-11 X
CONN@ : means ME part

PCIe assignment:
PCIe-1 X
S0 O O O O PCIe-2 X
PCIe-3 WLAN
S1 O O O O PCIe-4 GLAN (Realtek)
PCIe-5 X
S3 O O O X PCIe-6 X

S5 S4/AC O O X X
I2C / SMBUS ADDRESSING
S5 S4/ Battery only O X X X
S5 S4/AC & Battery DEVICE HEX ADDRESS
don't exist X X X X
1
DDR SO-DIMM 0 A0 10100000 1

DDR SO-DIMM 1 A4 10100100

CLOCK GENERATOR (EXT.) D2 11010010

SMBUS Control Table

SERIAL Thermal
SOURCE INVERTER BATT EEPROM Sensor SODIMM CLK CHIP MINI CARD LCD

SMB_EC_CK1 ： UMA GL PR FF-

43184330L01：
SMB_EC_DA1
KB926 X V X X X X X X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
ICH_SMBCLK
ICH_SMBDATA
ICH9 X X X X V V V X
DDC2_CLK
DDC2_DATA
Cantiga X X X X X X X V

：Main@/DEBUG@/NewC@
43184330L01：
：DA60000GI00 --->M/B
PCB：

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
Notes List

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 3 of 46
A
 5 4 3 2 1

40mA
+3VAUX_BT
D D

20mA
+3VALW_EC

10mA
SPI ROM
177mA
0.35A ICH9 250mA
INVPWR_B+ LVDS CON RTS5159

LAN 278mA
AC VIN ICH9
1.7A 5.89A 3.35A
+3VALW +3VS 1500mA
2A +LCDVDD LVDS CON
B++
250mA
+3VS_CK505
C
1A C

Mini card (WLAN)

0.58A 1.3A +VDDA

+5VALW +5VS ALC272
B+
7A
DDR3 +5VAMP

+1.5V 1.8A
ODD

+0.75VS 700mA
657mA ICH_VCC1_5 SATA
B B

3.7 X 3=11.1V 0.3A 2.2A ICH9

+1.5VS 1.56A
DC BATT ICH9 Web Camera
1.9A 12.11A 3.7A
B+++ +1.8V MCH

1.17A
ICH9

4.7A 1.26A
1.05V_B+ +VCCP MCH

2.3A
CPU

2A 10mA 34A/1.025V
CPU_B+ +VCC_CORE CPU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
Power delevry

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 4 of 46
5 4 3 2 1
 A

1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
Notes List

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 5 of 46
A
 5 4 3 2 1

+3VS

ITP-XDP Connector XDP_DBRESET# 1

@R1
@ R1
2 1K_0402_5%

Change value in 5/02 +VCCP

： follow check list ver:1.5 change to 51 ohm
PV：
04/29 MV1 R2~R8 change to 54.9 Ohm,
XDP_TDI R2 1 2 54.9_0402_1%
follow checklist 2.0
XDP_TMS R3 1 2 54.9_0402_1%
D D
XDP_TDO R4 1 2 54.9_0402_1%

XDP_TRST# R7 1 2 54.9_0402_1%
9 H_A#[3..16]
JCPU1A
H_A#3 J4 H1 H_ADS# XDP_TCK R8 1 2 54.9_0402_1%
A[3]# ADS# H_ADS# 9

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
H_A#5 A[4]# BNR# H_BPRI# H_BNR# 9
L4 G5 H_BPRI# 9
H_A#6 A[5]# BPRI#
K5 A[6]# This shall place near CPU
H_A#7 M3 H5 H_DEFER#
H_A#8 A[7]# DEFER# H_DRDY# H_DEFER# 9
N2 F21 H_DRDY# 9
H_A#9 A[8]# DRDY# H_DBSY#
J1 E1 H_DBSY# 9
H_A#10 A[9]# DBSY#
N3 A[10]#
H_A#11 P5 F1 H_BR0#
A[11]# BR0# H_BR0# 9
H_A#12 P2 A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# T1
H_A#14 A[13]# IERR# H_INIT#
P4 B3 H_INIT# 21
H_A#15 A[14]# INIT#
P1
A[15]# Place TP with a
H_A#16 R1 H4 H_LOCK#
9 H_ADSTB#0 H_ADSTB#0 M1
A[16]# LOCK# H_LOCK# 9 GND 0.1" away
ADSTB[0]# H_RESET#
C1 H_RESET# 9
H_REQ#0 RESET# H_RS#0
9 H_REQ#0 K3 REQ[0]# RS[0]# F3 H_RS#0 9
H_REQ#1 H2 F4 H_RS#1
9 H_REQ#1 H_REQ#2 REQ[1]# RS[1]# H_RS#2 H_RS#1 9
9 H_REQ#2 K2 G3 H_RS#2 9
H_REQ#3 REQ[2]# RS[2]# H_TRDY#
9 H_REQ#3 J3 REQ[3]# TRDY# G2 H_TRDY# 9
H_REQ#4 L1
9 H_REQ#4 REQ[4]# H_HIT#
9 H_A#[17..35] G6 H_HIT# 9
H_A#17 HIT# H_HITM#
C H_A#18
Y2
A[17]# HITM#
E4 H_HITM# 9 ： Delete XDP connector
03/18 PV： C
U5 A[18]#
H_A#19 R3 AD4
A[19]# BPM[0]#
ADDR GROUP_1

H_A#20 W6 AD3
H_A#21 A[20]# BPM[1]#
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4
A[22]# BPM[3]#
XDP/ITP SIGNALS

H_A#23 U1 AC2
H_A#24 A[23]# PRDY#
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK +3VS
H_A#26 A[25]# TCK XDP_TDI
H_A#27
T3 A[26]# TDI AA6
XDP_TDO
： Checklist Ver 1.5 change to 56 ohm
PV：
W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5

0.1U_0402_16V4Z
H_A#29 Y4 AB6 XDP_TRST# 1
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# 22
H_A#31 V4 C2
H_A#32 A[31]# U1
W3
H_A#33 A[32]# 2
AA4
A[33]# THERMAL
H_A#34 AB2 H_PROCHOT# R13 1 2 56_0402_1%
H_A#35 A[34]# +VCCP SMB_EC_CK2
AA3 D21 1 8 SMB_EC_CK2 31
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA_R R14 H_THERMDA VDD SMCLK
9 H_ADSTB#1 V1 A24 1 2 0_0402_5%
ADSTB[1]# THERMDA H_THERMDC_R R15 H_THERMDC H_THERMDA SMB_EC_DA2
THERMDC B25 1 2 0_0402_5% 2 DP SMDATA 7 SMB_EC_DA2 31
H_A20M# A6 C3
21 H_A20M# A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# 1 2 H_THERMDC 3 6 R6 1 2 10K_0402_5%

21 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 9,21 DN ALERT# +3VS
H_IGNNE# C4 2200P_0402_50V7K
21 H_IGNNE# IGNNE# THERM# 4 5
H_STPCLK# THERM# GND
21 H_STPCLK# D5
H_INTR STPCLK# <BOM Structure>
21 H_INTR C6
LINT0 H CLK R16 04/29 MV1 reserve
H_NMI B4 A22 CLK_CPU_BCLK 1 2
21 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 17 +3VS 10K for 2nd source
H_SMI# A3 A21 CLK_CPU_BCLK# 10K_0402_5%
21 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 17 EMC1402-1-ACZL-TR_MSOP8
M4
RSVD[01] Address:100_1100
N5
RSVD[02] H_THERMDA, H_THERMDC routing together,
T2
B
V3
RSVD[03] Trace width / Spacing = 10 / 10 mil B
RSVD[04]
B2
RESERVED

RSVD[05]
D2
RSVD[06]
D22 RSVD[07]
D3
RSVD[08] For Merom, R14 and R15 are 0ohm
F6
RSVD[09] For Penryn, R14 and R15 are 100ohm.
、 R15 to 0
04/29 MV1 change R14、 PWM Fan Control circuit
ohm
Penryn +5VS
Modify as KSWAA, need double check the CONN pin define. 10/24 Prince
1A
+VCCP

1
D34
2 1SS355_SOD323-2
1

@
R17 C62 @ JP2

2
56_0402_5% 10U_0805_10V4Z +FAN1 1
1 1
2 2

1
2 3
2 2

U6 3
B

1 8 D11 C168 4
EN GND @ @ 1000P_0402_25V8J GND
2 7 5
VIN GND 1 GND
E

H_PROCHOT# 3 1 OCP# +FAN1 3 6 CONN@

2
OCP# 22 VOUT GND
C

@ Q1 4 5 ACES_85205-03001
31 EN_DFAN1 VSET GND
MMBT3904_NL_SOT23-3 1 BAS16_SOT23-3
10mil APL5607KI-TRG_SO8 1 R50 2 +3VS

0.01U_0402_16V7K
C63 10K_0402_5%
+VCCP 10U_0805_10V4Z
A 2 FAN_SPEED1 31 A

1
2

R18 C60
56_0402_5% @
2
<BOM Structure>
1

H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/ITP-XDP

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 6 of 46
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE
9 H_D#[0..15] H_D#[32..47] 9
JCPU1B JCPU1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]

DATA GRP 0
H_D#3 G22 V26 H_D#35 A12 AC9

DATA GRP 2
D H_D#4 D[3]# D[35]# H_D#36 VCC[004] VCC[071] D
F23 D[4]# D[36]# V23 A13 VCC[005] VCC[072] AC12
H_D#5 G25 T22 H_D#37 A15 AC13
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
E25 D[6]# D[38]# U25 A17 VCC[007] VCC[074] AC15
H_D#7 E23 U23 H_D#39 A18 AC17
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
G24 D[9]# D[41]# W22 B7 VCC[010] VCC[077] AD7
H_D#10 J24 Y23 H_D#42 B9 AD9
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
J23 D[11]# D[43]# W24 B10 VCC[012] VCC[079] AD10
H_D#12 H22 W25 H_D#44 B12 AD12
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
F26 AA23 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
9 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 9 B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
9 H_DSTBP#0 H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2 H_DSTBP#2 9 VCC[018] VCC[085]
9 H_DINV#0 H25 U22 H_DINV#2 9 C9 AE10
DINV[0]# DINV[2]# VCC[019] VCC[086]
9 H_D#[16..31] H_D#[48..63] 9 C10 AE12
VCC[020] VCC[087]
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 AB22 C18 AE20
H_D#20 D[19]# D[51]# H_D#52 VCC[025] VCC[092]
L23 AB21 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
T24 D[27]# D[59]# AD21 E7 VCC[033] VCC[100] AF20
H_D#28 R24 AC22 H_D#60 E9 R19
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
L25 AD23 E10 G21 +VCCPA 1 2 0_0402_5%
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01] +VCCPB 0_0402_5%
T25 AF22 E12 V6 1 2
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R20 C
N25 D[31]# D[63]# AC23 E13 VCC[037] VCCP[03] J6
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
9 H_DSTBN#1 H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 H_DSTBN#3 9 VCC[038] VCCP[04]
9 H_DSTBP#1 M26 AF24 H_DSTBP#3 9 E17 M6
H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 VCC[039] VCCP[05] + C6
9 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 9 E18 VCC[040] VCCP[06] J21
E20 K21 330U_D2E_2.5VM_R7
+V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 R26 F7 M21
@ R21 TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP[08] 2
1 2 1K_0402_5% C23 TEST1 MISC COMP[1] U26 F9 VCC[043] VCCP[09] N21
@ R22 1 2 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
TEST4 AF26 F14 R6
T3 TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
AF1 E5 H_DPRSTP# 9,21,41 R23 R24 R25 R26 F15 T21
T4 TEST5 DPRSTP# VCC[047] VCCP[13]

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# 21 VCC[048] VCCP[14]

1
TEST7 C3 D24 H_DPWR# F18 V21
T6 CPU_BSEL0 TEST7 DPWR# H_PWRGOOD H_DPWR# 9 VCC[049] VCCP[15]
17 CPU_BSEL0 B22 D6 H_PWRGOOD 21 F20 W21
CPU_BSEL1 BSEL[0] PWRGOOD H_CPUSLP# VCC[050] VCCP[16]
17 CPU_BSEL1 B23 D7 H_CPUSLP# 9 AA7
CPU_BSEL2 BSEL[1] SLP# H_PSI# VCC[051]
17 CPU_BSEL2 C21 AE6 H_PSI# 41 AA9 B26
BSEL[2] PSI# VCC[052] VCCA[01] +1.5VS
AA10 C26

2
VCC[053] VCCA[02]

0.01U_0402_16V7K
Penryn AA12
VCC[054]

10U_0603_6.3V6M
AA13 AD6
VCC[055] VID[0] CPU_VID0 41
* Route the TEST3 and TEST5 signals through AA15 VCC[056] VID[1] AF5
CPU_VID1 41 1 1
AA17 AE5
a ground referenced Zo = 55-ohm trace that VCC[057] VID[2] CPU_VID2 41 C7 C8
AA18 AF4
VCC[058] VID[3] CPU_VID3 41
ends in a via that is near a GND via and is AA20 AE3
VCC[059] VID[4] CPU_VID4 41 2 2
accessible through an oscilloscope Resistor placed within 0.5" AB9
VCC[060] VID[5]
AF3
CPU_VID5 41
AC10 AE2
of CPU pin.Trace should be VCC[061] VID[6] CPU_VID6 41
connection. AB10
VCC[062]
at least 25 mils away from AB12 VCC[063]
AB14 AF7 VCCSENSE
VCC[064] VCCSENSE VCCSENSE 41
any other toggling signal. AB15
VCC[065] Near pin B26
COMP[0,2] trace width is 18 AB17
VCC[066] VSSSENSE
AB18 AE7 VSSSENSE 41
VCC[067] VSSSENSE
mils. COMP[1,3] trace width
B Penryn B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 is 4 mils. .

166 0 1 1

Length match within 25 mils.

200 0 1 0
The trace width/space/other is 20/7/25.
+VCCP
266 0 0 0
1

R27
1K_0402_1%
+VCC_CORE
2

+V_CPU_GTLREF

R28 1 2 100_0402_1% VCCSENSE

1

R29
2K_0402_1% R30 1 2 100_0402_1% VSSSENSE
2

Close to CPU pin within

Close to CPU pin AD26 500mils.
A A
within 500mils.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 7 of 46
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE

1 1 1 1 1 1 1 1
Place these capacitors on C9 C10 C11 C12 C13 C14 C15 C16
L8 (North side,Secondary
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
Layer) 2 2 2 2 2 2 2 2

D D
+VCC_CORE
JCPU1D
A4 P6
VSS[001] VSS[082]
A8
VSS[002] VSS[083]
P21 Place these capacitors on 1 1 1 1 1 1 1 1
A11 P24 L8 (North side,Secondary C17 C18 C19 C20 C21 C22 C23 C24
VSS[003] VSS[084]
A14 R2
VSS[004] VSS[085] Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A16 VSS[005] VSS[086] R5
A19 R22 2 2 2 2 2 2 2 2
VSS[006] VSS[087]
A23 R25
VSS[007] VSS[088]
AF2 VSS[008] VSS[089] T1
B6 T4
VSS[009] VSS[090] +VCC_CORE
B8 VSS[010] VSS[091] T23
B11 T26
VSS[011] VSS[092]
B13 U3
VSS[012] VSS[093]
B16
VSS[013] VSS[094]
U6 Place these capacitors on 1 1 1 1 1 1 1 1
B19 U21 L8 (North side,Secondary C25 C26 C27 C28 C29 C30 C31 C32
VSS[014] VSS[095]
B21 U24
VSS[015] VSS[096] Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B24 VSS[016] VSS[097] V2
C5 V5 2 2 2 2 2 2 2 2
VSS[017] VSS[098]
C8 V22
VSS[018] VSS[099]
C11 V25
VSS[019] VSS[100]
C14 VSS[020] VSS[101] W1
C16 W4 +VCC_CORE
VSS[021] VSS[102]
C19 W23
VSS[022] VSS[103]
C2 VSS[023] VSS[104] W26
C22
VSS[024] VSS[105]
Y3 Place these capacitors on 1 1 1 1 1 1 1 1
C25 Y6 L8 (North side,Secondary C33 C34 C35 C36 C37 C38 C39 C40
VSS[025] VSS[106]
D1 VSS[026] VSS[107] Y21
D4 Y24 Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VSS[027] VSS[108] 2 2 2 2 2 2 2 2
D8 AA2
VSS[028] VSS[109]
D11 AA5
C VSS[029] VSS[110] C
D13 VSS[030] VSS[111] AA8
D16 AA11
VSS[031] VSS[112]
D19 AA14
D23
VSS[032] VSS[113]
AA16
Mid Frequence Decoupling
VSS[033] VSS[114]
D26 VSS[034] VSS[115] AA19
E3 AA22
VSS[035] VSS[116]
E6 VSS[036] VSS[117] AA25
E8 AB1
VSS[037] VSS[118]
E11 VSS[038] VSS[119] AB4
E14 AB8
VSS[039] VSS[120]
E16 VSS[040] VSS[121] AB11
E19 AB13
E21
E24
VSS[041]
VSS[042]
VSS[122]
VSS[123] AB16
AB19
ESR <= 1.5m ohm
VSS[043] VSS[124] Near CPU CORE regulator
F5
F8
VSS[044]
VSS[045]
VSS[125]
VSS[126]
AB23
AB26
Capacitor > 1980uF
F11 AC3
VSS[046] VSS[127]
F13 AC6
VSS[047] VSS[128] +VCC_CORE
F16 AC8
VSS[048] VSS[129]
F19 VSS[049] VSS[130] AC11
F2 AC14
VSS[050] VSS[131]
F22 AC16
VSS[051] VSS[132]
330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M
F25 AC19
VSS[052] VSS[133]
G4 AC21
VSS[053] VSS[134]
G1 AC24 1 1 1 1
VSS[054] VSS[135] @
G23 AD2
VSS[055] VSS[136] C41 + C42 + C43 + C44 +
G26 VSS[056] VSS[137] AD5
H3 AD8
VSS[057] VSS[138]
H6 AD11
VSS[058] VSS[139] 2 2 2 2
H21 AD13
VSS[059] VSS[140]
H24 AD16
VSS[060] VSS[141]
J2 AD19
B VSS[061] VSS[142] B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 AE1
VSS[064] VSS[145]
K1 VSS[065] VSS[146] AE4
K4
VSS[066] VSS[147]
AE8 11/21 Change ESR=7m ohm
K23 AE11
VSS[067] VSS[148]
K26 AE14
VSS[068] VSS[149]
L3 AE16
VSS[069] VSS[150]
L6 AE19
VSS[070] VSS[151]
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 A2
VSS[073] VSS[154]
M5 AF6
M22
VSS[074] VSS[155]
AF8 +VCCP Inside CPU center cavity in 2 rows
VSS[075] VSS[156]
M25 VSS[076] VSS[157] AF11
N1 AF13
VSS[077] VSS[158]
N4 AF16 1 1 1 1 1 1
VSS[078] VSS[159] C45 C46 C47 C48 C49 C50
N23 AF19
VSS[079] VSS[160]
N26 AF21
VSS[080] VSS[161] 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
P3 A25
VSS[081] VSS[162] 2 2 2 2 2 2
AF25
VSS[163]
Penryn
.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 8 of 46
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 6 U2B
7 H_D#[0..63] U2A

DDR CLK/ CONTROL/COMPENSATION

A14 H_A#3 M36
H_A#_3 T7 RESERVED

0.01U_0402_25V7K
H_D#0 H_A#4 M_CLK_DDR0

2.2U_0603_6.3V4Z
F2 H_D#_0 H_A#_4 C15 T8 N36 RESERVED SA_CK_0 AP24 M_CLK_DDR0 15
H_D#1 G8 F16 H_A#5 R33 AT21 M_CLK_DDR1 M_CLK_DDR1 15
H_D#2 H_D#_1 H_A#_5 H_A#6 +1.5V T9 RESERVED SA_CK_1 M_CLK_DDR2
F8 H13 T10 T33 AV24 M_CLK_DDR2 16
H_D#3 H_D#_2 H_A#_6 H_A#7 RESERVED SB_CK_0 M_CLK_DDR3
E6 C18 T11 AH9 AU20 M_CLK_DDR3 16
H_D#4 H_D#_3 H_A#_7 H_A#8 RESERVED SB_CK_1
G2 M16 1 1 T12 AH10
H_D#_4 H_A#_8 RESERVED

1
C51

C52
H_D#5 H6 J13 H_A#9 AH12 AR24 M_CLK_DDR#0
H_D#_5 H_A#_9 T13 RESERVED SA_CK#_0 M_CLK_DDR#0 15
H_D#6 H2 P16 H_A#10 R31 AH13 AR21 M_CLK_DDR#1
H_D#7 H_D#_6 H_A#_10 H_A#11 T14 RESERVED SA_CK#_1 M_CLK_DDR#2 M_CLK_DDR#1 15
F6 R16 1K_0402_1% K12 AU24
H_D#8 H_D#_7 H_A#_11 H_A#12 2 2 T15 RESERVED SB_CK#_0 M_CLK_DDR#3 M_CLK_DDR#2 16
D4 N17 T16 AL34 AV20 M_CLK_DDR#3 16
H_D#9 H_D#_8 H_A#_12 H_A#13 RESERVED SB_CK#_1
H3 M13 AK34

2
H_D#10 H_D#_9 H_A#_13 H_A#14 SMRCOMP_VOH T17 RESERVED DDR_CKE0_DIMMA
M9 H_D#_10 H_A#_14 E17 T18 AN35 RESERVED SA_CKE_0 BC28 DDR_CKE0_DIMMA 15
H_D#11 M11 P17 H_A#15 80% of 1.5V VCC_SM AM35 AY28 DDR_CKE1_DIMMA
H_D#_11 H_A#_15 T19 RESERVED SA_CKE_1 DDR_CKE1_DIMMA 15

1
D H_D#12 H_A#16 DDR_CKE2_DIMMB D
J1 H_D#_12 H_A#_16 F17 T24 RESERVED SB_CKE_0 AY36 DDR_CKE2_DIMMB 16
H_D#13 J2 G20 H_A#17 R32 Delete them for placement. 11/23 BB36 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB 16

RSVD
H_D#14 N12 B19 H_A#18 3.01K_0402_1% B31
H_D#15 H_D#_14 H_A#_18 H_A#19 RESERVED DDR_CS0_DIMMA#
H_D#16
J6
H_D#_15 H_A#_19
J16
H_A#20
20% of 1.5V VCC_SM T22 B2
RESERVED SA_CS#_0
BA17
DDR_CS1_DIMMA# DDR_CS0_DIMMA# 15
P2 E20 M1 AY16

2
H_D#_16 H_A#_20 T23 RESERVED SA_CS#_1 DDR_CS1_DIMMA# 15
H_D#17 L2 H16 H_A#21 SMRCOMP_VOL AV16 DDR_CS2_DIMMB#
H_D#18 H_D#_17 H_A#_21 H_A#22 SB_CS#_0 DDR_CS3_DIMMB# DDR_CS2_DIMMB# 16
R2 J20 AR13 DDR_CS3_DIMMB# 16
H_D#_18 H_A#_22 SB_CS#_1

1
0.01U_0402_25V7K
H_D#19 H_A#23

2.2U_0603_6.3V4Z
N9 H_D#_19 H_A#_23 L17 T24 AY21 RESERVED
H_D#20 L6 A17 H_A#24 1 1 R33 BD17 M_ODT0
H_D#_20 H_A#_24 SA_ODT_0 M_ODT0 15

C53

C54
H_D#21 M5 B17 H_A#25 1K_0402_1% AY17 M_ODT1 M_ODT1 15
H_D#22 H_D#_21 H_A#_25 H_A#26 SA_ODT_1 M_ODT2 +1.5V
J3 H_D#_22 H_A#_26 L16 SB_ODT_0 BF15 M_ODT2 16
H_D#23 N2 C21 H_A#27 BG23 AY13 M_ODT3
M_ODT3 16

2
H_D#24 H_D#_23 H_A#_27 H_A#28 2 2 T25 RESERVED SB_ODT_1
R1 H_D#_24 H_A#_28 J17 T26 BF23 RESERVED
H_D#25 N5 H20 H_A#29 BH18 BG22 SMRCOMP R34 1 2 80.6_0402_1%
H_D#26 H_D#_25 H_A#_29 H_A#30 T27 RESERVED SM_RCOMP SMRCOMP#
N6 B18 BF18 BH21 R35 1 2 80.6_0402_1%
H_D#_26 H_A#_30 T28 RESERVED SM_RCOMP#
H_D#27 P13 K17 H_A#31 Follow Design Guide
H_D#28 H_D#_27 H_A#_31 H_A#32 SMRCOMP_VOH
N8 H_D#_28 H_A#_32 B20 SM_RCOMP_VOH BF28
H_D#29 L7 F21 H_A#33 BH28 SMRCOMP_VOL For Cantiga: 80.6ohm
H_D#30 H_D#_29 H_A#_33 H_A#34 +3VS SM_RCOMP_VOL
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35 AV42 V_DDR_MCH_REF
H_D#32 H_D#_31 H_A#_35 PM_EXTTS#0 R38 SM_VREF SM_PWROK
Y3 1 2 10K_0402_5% AR36 @ R36 1 2 0_0402_5%
H_D#33 H_D#_32 H_ADS# SM_PWROK SM_REXT R37
AD14 H12 H_ADS# 6 BF17 1 2 499_0402_1%
H_D#34 H_D#_33 H_ADS# H_ADSTB#0 SM_REXT TP_SM_DRAMRST#
Y6 H_D#_34 H_ADSTB#_0 B16 H_ADSTB#0 6 SM_DRAMRST# BC36 SM_DRAMRST# 15,16
H_D#35 Y10 G17 H_ADSTB#1 PM_EXTTS#1 R39 1 2 10K_0402_5%
H_D#36 H_D#_35 H_ADSTB#_1 H_BNR# H_ADSTB#1 6 CLK_MCH_DREFCLK
Y12 A9 H_BNR# 6 B38 CLK_MCH_DREFCLK 17
H_D#37 H_D#_36 H_BNR# H_BPRI# DPLL_REF_CLK CLK_MCH_DREFCLK#
Y14 H_D#_37 H_BPRI# F11 H_BPRI# 6 DPLL_REF_CLK# A38 CLK_MCH_DREFCLK# 17
H_D#38 Y7 G12 H_BR0# CLKREQ#_7 R40 1 2 10K_0402_5% E41 MCH_SSCDREFCLK
H_D#39 H_D#_38 H_BREQ# H_DEFER# H_BR0# 6 DPLL_REF_SSCLK MCH_SSCDREFCLK# MCH_SSCDREFCLK 17
W2 E9 F41
HOST

H_D#_39 H_DEFER# H_DEFER# 6 DPLL_REF_SSCLK# MCH_SSCDREFCLK# 17

H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# 6

CLK
H_D#41 Y9 AH7 CLK_MCH_BCLK F43 CLK_MCH_3GPLL
H_D#42 H_D#_41 HPLL_CLK CLK_MCH_BCLK# CLK_MCH_BCLK 17 PEG_CLK CLK_MCH_3GPLL# CLK_MCH_3GPLL 17
AA13 AH6 CLK_MCH_BCLK# 17 E43 CLK_MCH_3GPLL# 17
H_D#43 H_D#_42 HPLL_CLK# H_DPWR# PEG_CLK#
AA9 J11 H_DPWR# 7
C H_D#44 H_D#_43 H_DPWR# H_DRDY# C
AA11 H_D#_44 H_DRDY# F9 H_DRDY# 6
H_D#45 AD11 H9 H_HIT#
H_D#46 H_D#_45 H_HIT# H_HITM# H_HIT# 6 DMI_TXN0
AD10 E12 H_HITM# 6 AE41 DMI_TXN0 22
H_D#47 H_D#_46 H_HITM# H_LOCK# DMI_RXN_0 DMI_TXN1
AD13 H_D#_47 H_LOCK# H11 H_LOCK# 6 DMI_RXN_1 AE37 DMI_TXN1 22
H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
H_D#49 H_D#_48 H_TRDY# H_TRDY# 6 DMI_RXN_2 DMI_TXN3 DMI_TXN2 22
AE9 AH39 DMI_TXN3 22
H_D#50 H_D#_49 DMI_RXN_3
AA2 H_D#_50
H_D#51 AD8 AE40 DMI_TXP0
H_D#52 H_D#_51 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1 DMI_TXP0 22
AA3 H_D#_52 17 MCH_CLKSEL0 T25 CFG_0 DMI_RXP_1 AE38 DMI_TXP1 22
H_D#53 AD3 J8 H_DINV#0 MCH_CLKSEL1
R25 AE48 DMI_TXP2
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 H_DINV#0 7 17 MCH_CLKSEL1 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3 DMI_TXP2 22
AD7 H_D#_54 H_DINV#_1 L3 H_DINV#1 7 17 MCH_CLKSEL2 P25 CFG_2 DMI_RXP_3 AH40 DMI_TXP3 22
H_D#55 AE14 Y13 H_DINV#2 P20
H_D#_55 H_DINV#_2 H_DINV#2 7 CFG_3
H_D#56 AF3 Y1 H_DINV#3 P24 AE35 DMI_RXN0
H_D#57 H_D#_56 H_DINV#_3 H_DINV#3 7 CFG5 CFG_4 DMI_TXN_0 DMI_RXN1 DMI_RXN0 22
AC1 11 CFG5 C25 AE43 DMI_RXN1 22
H_D#58 H_D#_57 H_DSTBN#0 CFG6 CFG_5 DMI_TXN_1 DMI_RXN2
AE3 L10 H_DSTBN#0 7 11 CFG6 N24 AE46 DMI_RXN2 22
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 CFG7 CFG_6 DMI_TXN_2 DMI_RXN3
AC3 M7 H_DSTBN#1 7 11 CFG7 M24 AH42 DMI_RXN3 22
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 CFG8 CFG_7 DMI_TXN_3
AE11 AA5 H_DSTBN#2 7 11 CFG8 E21
H_D#_60 H_DSTBN#_2 CFG_8

CFG
H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_RXP0
H_DSTBN#3 7 11 CFG9 DMI_RXP0 22

DMI
H_D#62 H_D#_61 H_DSTBN#_3 CFG10 CFG_9 DMI_TXP_0 DMI_RXP1
AG2 11 CFG10 C24 AE44 DMI_RXP1 22
H_D#63 H_D#_62 H_DSTBP#0 CFG11 CFG_10 DMI_TXP_1 DMI_RXP2
AD6 H_D#_63 H_DSTBP#_0 L9 H_DSTBP#0 7 11 CFG11 N21 CFG_11 DMI_TXP_2 AF46 DMI_RXP2 22
M8 H_DSTBP#1 CFG12 P21 AH43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 7 11 CFG12 CFG_12 DMI_TXP_3 DMI_RXP3 22
AA6 H_DSTBP#2 CFG13 T21
+H_SWNG H_DSTBP#_2 H_DSTBP#3 H_DSTBP#2 7 11 CFG13 CFG14 CFG_13
C5 AE5 H_DSTBP#3 7 11 CFG14 R20
H_RCOMP H_SWING H_DSTBP#_3 CFG15 CFG_14
E3 11 CFG15 M20
H_RCOMP H_REQ#0 CFG16 CFG_15
B15 H_REQ#0 6 11 CFG16 L21 2 1 +1.5V
H_REQ#_0 H_REQ#1 CFG17 CFG_16 R1120

GRAPHICS VID
K13 H_REQ#1 6 11 CFG17 H21
H_REQ#_1 H_REQ#2 CFG18 CFG_17 10K_0402_5%~D
H_REQ#_2 F13 H_REQ#2 6 11 CFG18 P29 CFG_18
B13 H_REQ#3 CFG19 R28 D25
H_RESET# H_REQ#_3 H_REQ#4 H_REQ#3 6 11 CFG19 CFG20 CFG_19
6 H_RESET# C12 B14 H_REQ#4 6 11 CFG20 T28 B33 2 1 SYSON 31,33,39
H_CPUSLP# H_CPURST# H_REQ#_4 CFG_20 GFX_VID_0
7 H_CPUSLP# E11 B32
H_CPUSLP# H_RS#0 GFX_VID_1 CH751H-40PT_SOD323-2
B6 H_RS#0 6 G33
H_RS#_0 H_RS#1 GFX_VID_2 SM_PWROK
F12 H_RS#1 6 F33 DDR3_SM_PWROK 39
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_3 B
H_RS#_2 C8 H_RS#2 6 22 PM_BMBUSY# R29 PM_SYNC# GFX_VID_4 E33
+H_VREF A11 7,21,41 H_DPRSTP# H_DPRSTP# B7
H_AVREF PM_EXTTS#0 PM_DPRSTP#
B11
H_DVREF 15 PM_EXTTS#0 PM_EXTTS#1
N33
P32
PM_EXT_TS#_0 delete test point for Placement.11/17
16 PM_EXTTS#1 PM_EXT_TS#_1

PM
CANTIGA ES_FCBGA1329 PM_PWROK AT40 C34
22,31 PM_PWROK PWROK GFX_VR_EN +VCCP
20,25,26 PLT_RST# 1 2 AT11
R41 1 THERMTRIP# RSTIN#
2 100_0402_5% T20
Layout note: 6,21 H_THERMTRIP#
R42 0_0402_5% DPRSLPVR R32
THERMTRIP#
22,41 DPRSLPVR DPRSLPVR

1
Route H_SCOMP and H_SCOMP# with trace CL_CLK0
AH37 R43
width, spacing and impedance (55 ohm) same CL_CLK CL_CLK0 22
0.1U_0402_16V4Z

AH36 CL_DATA0 1K_0402_1%

CL_DATA CL_DATA0 22
1 @ M_PWROK
as FSB data traces C55
BG48
NC CL_PWROK
AN36
CL_RST# M_PWROK 22,31
BF48 AJ35

2
NC CL_RST# +CL_VREF CL_RST# 22
BD48 AH34

ME
NC CL_VREF
Layout Note: Layout Note: V_DDR_MCH_REF BC48 NC

1
2 BH47 0621 add CLK and DAT for DVI
NC 1
H_RCOMP / H_VREF / H_SWNG trace width and spacing is 20/20. BG47 C56 R44
NC 0.1U_0402_16V4Z 499_0402_1%
trace width and spacing is 10/20 BE47 N28
NC DDPC_CTRLCLK
BH46
NC DDPC_CTRLDATA
M28 Delete them for placement. 11/23
+1.5V 2
BF46 G36

2
NC SDVO_CTRLCLK T60

NC
+VCCP
+V_DDR_MCH_REF generated by DC-DC BG45
NC SDVO_CTRLDATA
E36
CLKREQ#_7
T61
BH44 NC CLKREQ# K36 CLKREQ#_7 17
1

MISC
+VCCP BH43 H36 MCH_ICH_SYNC#
NC ICH_SYNC# MCH_ICH_SYNC# 22
R45 BH6 NC
1K_0402_1%

221_0603_1%

10K_0402_1% BH5 1 R737 2 56_0402_5% +VCCP *R44*Follow

NC
1

BG4 B12 TSATN#

NC TSATN# TSATN# 31 Intel feedback
R46 R47 BH3
2

V_DDR_MCH_REF NC
BF3 T29
NC
BH2
NC
1
0.1U_0402_16V4Z

BG2 B28
2

+H_VREF H_RCOMP +H_SWNG R48 NC HDA_BCLK T45

1 BE2 B30
C57 10K_0402_1% NC HDA_RST# T51
BG1 NC HDA_SDI B29
24.9_0402_1%

A A
0.1U_0402_16V4Z

BF1 C29
NC HDA_SDO
1

1
100_0402_1%
0.1U_0402_16V4Z

1 1 BD1 A28 T52

2

2 NC HDA_SYNC
2K_0402_1%

HDA
R52 C58 R54 R55 C59 BC1 T53
NC
F1
NC
A47 NC
0830 Add pull-up and pull-down resistor.
2 2
2

CANTIGA ES_FCBGA1329

： follow check list ver:1.5 change to 10K ohm

PV：
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
within 100 mils from NB Near B3 pin Cantiga(1/6)-AGTL/DMI/DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 9 of 46
5 4 3 2 1
 5 4 3 2 1

D D

15 DDR_A_D[0..63] 16 DDR_B_D[0..63]
U2D U2E
DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_A_BS0 15 DDR_B_D0 AK47 BC16 DDR_B_BS0 DDR_B_BS0 16
DDR_A_D1 SA_DQ_0 SA_BS_0 DDR_A_BS1 DDR_A_BS1 15 DDR_B_D1 SB_DQ_0 SB_BS_0 DDR_B_BS1 DDR_B_BS1 16
AJ41 BG18 AH46 BB17
DDR_A_D2 SA_DQ_1 SA_BS_1 DDR_A_BS2 DDR_A_BS2 15 DDR_B_D2 SB_DQ_1 SB_BS_1 DDR_B_BS2 DDR_B_BS2 16
AN38 SA_DQ_2 SA_BS_2 AT25 AP47 SB_DQ_2 SB_BS_2 BB33
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_A_RAS# 15 DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_A_CAS# DDR_A_CAS# 15 DDR_B_D5 AJ48 AU17 DDR_B_RAS# DDR_B_RAS# 16
DDR_A_D6 SA_DQ_5 SA_CAS# DDR_A_WE# DDR_A_WE# 15 DDR_B_D6 SB_DQ_5 SB_RAS# DDR_B_CAS# DDR_B_CAS# 16
AM44 AY20 AM48 BG16
DDR_A_D7 SA_DQ_6 SA_WE# DDR_B_D7 SB_DQ_6 SB_CAS# DDR_B_WE# DDR_B_WE# 16
AM42 SA_DQ_7 AP48 SB_DQ_7 SB_WE# BF14
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_A_DM[0..7] 15 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10 DDR_B_DM[0..7] 16
AT38 AM37 AY48
DDR_A_D12 SA_DQ_11 SA_DM_0 DDR_A_DM1 DDR_B_D12 SB_DQ_11 DDR_B_DM0
AN41 AT41 AT47 AM47
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
DDR_A_D14 AU44 AU39 DDR_A_DM3 DDR_B_D14 BA47 BD40 DDR_B_DM2
DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
DDR_A_D16 AV39 AY6 DDR_A_DM5 DDR_B_D16 BC46 BG11 DDR_B_DM4
DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
AY44 AT7 BC44 BA3
DDR_A_D18 SA_DQ_17 SA_DM_6 DDR_A_DM7 DDR_B_D18 SB_DQ_17 SB_DM_5 DDR_B_DM6
BA40 AJ5 BG43 AP1
SA_DQ_18 SA_DM_7 SB_DQ_18 SB_DM_6

A
DDR_A_D19 DDR_A_DQS[0..7] 15 DDR_B_D19 DDR_B_DM7

B
BD43 SA_DQ_19 BF43 SB_DQ_19 SB_DM_7 AK2
DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45 DDR_B_DQS[0..7] 16
DDR_A_D21 SA_DQ_20 SA_DQS_0 DDR_A_DQS1 DDR_B_D21 SB_DQ_20 DDR_B_DQS0
AY43 AT44 BC41 AL47
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
DDR_A_D23 BC40 BC37 DDR_A_DQS3 DDR_B_D23 BF41 BG41 DDR_B_DQS2
DDR_A_D24 SA_DQ_23 MEMORY SA_DQS_3 DDR_A_DQS4 DDR_B_D24 SB_DQ_23 SB_DQS_2 DDR_B_DQS3

MEMORY
AY37 AW12 BG38 BG37
DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
DDR_A_D26 AV37 AU8 DDR_A_DQS6 DDR_B_D26 BH35 BB2 DDR_B_DQS5
DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_A_DQS#[0..7] 15 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
AT36 AM7 BG35 AU1
DDR_A_D28 SA_DQ_27 SA_DQS_7 DDR_A_DQS#0 DDR_B_D28 SB_DQ_27 SB_DQS_6 DDR_B_DQS7 DDR_B_DQS#[0..7] 16
AY38 AJ43 BH40 AN6
C DDR_A_D29 SA_DQ_28 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D29 SB_DQ_28 SB_DQS_7 DDR_B_DQS#0 C
BB38 SA_DQ_29 SA_DQS#_1 AT43 BG39 SB_DQ_29 SB_DQS#_0 AL46
DDR_A_D30 AV36 BA44 DDR_A_DQS#2 DDR_B_D30 BG34 AV47 DDR_B_DQS#1
DDR_A_D31 SA_DQ_30 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D31 SB_DQ_30 SB_DQS#_1 DDR_B_DQS#2
AW36 BD37 BH34 BH41
DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
DDR_A_D33 AU11 BD8 DDR_A_DQS#5 DDR_B_D33 BG12 BG9 DDR_B_DQS#4
DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
BC11 AU9 BH11 BC2
DDR_A_D35 SA_DQ_34 SA_DQS#_6 DDR_A_DQS#7 DDR_A_MA[0..14] 15 DDR_B_D35 SB_DQ_34 SB_DQS#_5 DDR_B_DQS#6
BA12 SA_DQ_35 SA_DQS#_7 AM8 BG8 SB_DQ_35 SB_DQS#_6 AT2
DDR_A_D36 AU13 DDR_B_D36 BH12 AN5 DDR_B_DQS#7
SYSTEM

SA_DQ_36 SB_DQ_36 SB_DQS#_7 DDR_B_MA[0..14] 16

SYSTEM
DDR_A_D37 AV13 BA21 DDR_A_MA0 DDR_B_D37 BF11
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BD12 BC24 BF8 AV17
DDR_A_D39 SA_DQ_38 SA_MA_1 DDR_A_MA2 DDR_B_D39 SB_DQ_38 SB_MA_0 DDR_B_MA1
BC12 SA_DQ_39 SA_MA_2 BG24 BG7 SB_DQ_39 SB_MA_1 BA25
DDR_A_D40 BB9 BH24 DDR_A_MA3 DDR_B_D40 BC5 BC25 DDR_B_MA2
DDR_A_D41 SA_DQ_40 SA_MA_3 DDR_A_MA4 DDR_B_D41 SB_DQ_40 SB_MA_2 DDR_B_MA3
BA9 SA_DQ_41 SA_MA_4 BG25 BC6 SB_DQ_41 SB_MA_3 AU25
DDR_A_D42 AU10 BA24 DDR_A_MA5 DDR_B_D42 AY3 AW25 DDR_B_MA4
DDR_A_D43 SA_DQ_42 SA_MA_5 DDR_A_MA6 DDR_B_D43 SB_DQ_42 SB_MA_4 DDR_B_MA5
AV9 BD24 AY1 BB28
DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
BA11 BG27 BF6 AU28
DDR_A_D45 SA_DQ_44 SA_MA_7 DDR_A_MA8 DDR_B_D45 SB_DQ_44 SB_MA_6 DDR_B_MA7
BD9 BF25 BF5 AW28
DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
AY8 AW24 BA1 AT33
DDR_A_D47 SA_DQ_46 SA_MA_9 DDR_A_MA10 DDR_B_D47 SB_DQ_46 SB_MA_8 DDR_B_MA9
BA6 BC21 BD3 BD33
DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16
DDR

DDR_A_D49 AV7 BH26 DDR_A_MA12 DDR_B_D49 AU3 AW33 DDR_B_MA11

SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11

DDR
DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 AY25 AN2 BH15
DDR_A_D52 SA_DQ_51 SA_MA_14 DDR_B_D52 SB_DQ_51 SB_MA_13 DDR_B_MA14
AU5 AY2 AU33
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AU6 AV1
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AT5 AP3
DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
DDR_A_D56 AM11 DDR_B_D56 AL1
DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
AM5 AL2
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AJ9 AJ1
DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
AJ8 AH1
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AN12 AM2
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR3 A/B CH

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 10 of 46
5 4 3 2 1
 5 4 3 2 1

U2C

1
R148
2 ENBKL
Strap Pin Table
R57 +VCC_PEG
100K_0402_5% 19 INV_PWM_GL40 L32
L_BKLT_CTRL 000 = FSB 1066MHz
ENBKL G32 T37 1 2 CFG[2:0] FSB Freq
31 ENBKL R58 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 1 2 10K_0402_5% M32 T36 49.9_0402_1%
L_CTRL_CLK PEG_COMPO select
R59 1 2 10K_0402_5%
011 = FSB 667MHz
19 DDC2_CLK DDC2_CLK
M33 L_CTRL_DATA PEGCOMP trace width
K33 L_DDC_CLK PEG_RX#_0 H44 Others = Reserved
Follow Intel DG & 19 DDC2_DATA
DDC2_DATA J33 J46 and spacing is 20/25 mils.
L_DDC_DATA PEG_RX#_1
L44
Checklist PEG_RX#_2
19 ENAVDD PEG_RX#_3 L40 CFG[4:3] Reserved
ENAVDD M29 N41
R60 1 L_VDD_EN PEG_RX#_4
2 2.4K_0402_1% C44 LVDS_IBG PEG_RX#_5 P48 0 = DMI x 2
D D
B43 N44 CFG5 (DMI select) 1 = DMI x 4
E37
E38
LVDS_VBG
LVDS_VREFH
PEG_RX#_6
PEG_RX#_7 T43
U43
*
0 = The iTPM Host Interface is enable
LVDS_VREFL PEG_RX#_8

LVDS
LVDS_ACLK- C41 Y43 CFG6
19 LVDS_ACLK- LVDS_ACLK+ LVDSA_CLK# PEG_RX#_9
C40 Y48 1 = The iTPM Host Interface is disable
19 LVDS_ACLK+ LVDSA_CLK PEG_RX#_10
*

11/02
B37 LVDSB_CLK# PEG_RX#_11 Y36
A37
LVDSB_CLK PEG_RX#_12
AA43 0 =(TLS)chiper suite with no confidentiality
LVDS_A0- PEG_RX#_13 AD37 CFG7 (Intel Management
Engine Crypto strap) 1 =(TLS)chiper suite with confidentiality
H47 AC47
19
19
LVDS_A0-
LVDS_A1-
LVDS_A1-
LVDS_A2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15
AD39 *
19 LVDS_A2- LVDSA_DATA#_2

11/02
A40 H43
LVDSA_DATA#_3 PEG_RX_0
PEG_RX_1 J44 CFG8 Reserved

GRAPHICS
LVDS_A0+ H48 L43
19 LVDS_A0+ LVDS_A1+ LVDSA_DATA_0 PEG_RX_2
19 LVDS_A1+ D45 L41
LVDS_A2+ LVDSA_DATA_1 PEG_RX_3
19 LVDS_A2+ F40
LVDSA_DATA_2 PEG_RX_4
N40 CFG9 (PCIE Graphics 0 = Reverse Lane,15->0, 14->1
B40 LVDSA_DATA_3 PEG_RX_5 P47
N43 Lane Reversal) 1 = Normal Operation,Lane Number in
For make layout clearance, del
A41
H38
LVDSB_DATA#_0
PEG_RX_6
PEG_RX_7 T42
U42
order *
LVDSB_DATA#_1 PEG_RX_8

11/02
TP for channel B. 11/02 G37 Y42
LVDSB_DATA#_2 PEG_RX_9
J37
LVDSB_DATA#_3 PEG_RX_10
W47 CFG10 (PCIE 0 = Enable
PEG_RX_11 Y37
B42 AA42 Lookback 1 = Disable
G38
LVDSB_DATA_0
LVDSB_DATA_1
PEG_RX_12
PEG_RX_13
AD36 enable) *
delete test point F37
K37
LVDSB_DATA_2 PEG_RX_14 AC48
AD40
CFG11 Reserved
TV_COMPS LVDSB_DATA_3 PEG_RX_15
00 = Reserved

PCI-EXPRESS
TV_LUMA J41 CFG[13:12] (XOR/ALLZ) 01 = XOR Mode Enabled
TV_CRMA PEG_TX#_0
PEG_TX#_1 M46 10 = All Z Mode Enabled
F25 M47 11 = Normal Operation (Default)
TVA_DAC PEG_TX#_2
*
1

H25 M40
TVB_DAC PEG_TX#_3
75_0402_1%

75_0402_1%

75_0402_1%

C C
Follow Intel DG & K25 TVC_DAC PEG_TX#_4 M42

TV
R61 R62 R63 R48 CFG[15:14] Reserved
Checklist PEG_TX#_5
H24 N38
TV_RTN PEG_TX#_6
T40
2

PEG_TX#_7
PEG_TX#_8 U37 CFG16 (FSB Dynamic ODT) 0 = Disabled
11/10 Disable TV out U40 1 = Enabled
@ R64 1 2 2.2K_0402_5%
C31
E32
TV_DCONSEL_0
PEG_TX#_9
PEG_TX#_10 Y40
AA46
*
+3VS TV_DCONSEL_1 PEG_TX#_11
R406 1 2 0_0402_5% AA37 CFG[18:17] Reserved
18 M_BLUE M_BLUE PEG_TX#_12
AA40
18 M_GREEN M_GREEN PEG_TX#_13
PEG_TX#_14 AD43
18 M_RED M_RED AC46 CFG19 (DMI Lane Reversal) 0 = Normal Operation
PEG_TX#_15
(Lane number in Order) *
1

1
150_0402_1%

150_0402_1%

150_0402_1%

E28 J42
CRT_BLUE PEG_TX_0
Follow Intel DG & PEG_TX_1
L46 1 = Reverse Lane
R65 R66 R67 G28 M48
Checklist CRT_GREEN PEG_TX_2
M39
PEG_TX_3
J28 M43
2

CRT_RED PEG_TX_4
VGA
R47 CFG20 (PCIE/SDVO 0 = Only PCIE or SDVO is operational.
G29 CRT_IRTN
PEG_TX_5
PEG_TX_6 N37
T39 concurrent) 1 = PCIE/SDVO are operating simu.
*
3VDDCCL PEG_TX_7
18 3VDDCCL H32 U36
3VDDCDA CRT_DDC_CLK PEG_TX_8
18 3VDDCDA J32 U39
CRT_HSYNC R68 1 HSYNC CRT_DDC_DATA PEG_TX_9
2 J29 Y39
18 CRT_HSYNC 30.1_0402_1% CRT_HSYNC PEG_TX_10
E29 Y46
CRT_VSYNC R69 1 VSYNC CRT_TVO_IREF PEG_TX_11 +3VS
2 L29 AA36
18 CRT_VSYNC 30.1_0402_1% CRT_VSYNC PEG_TX_12
PEG_TX_13 AA39
AD42
PEG_TX_14
1

AD46
PEG_TX_15

1
R70 @ R71 +3VS
1.02K_0402_1% 4.02K_0402_1%
CANTIGA ES_FCBGA1329
B B
2

@ R72 1 2

2
CFG5 9 CFG16
4.02K_0402_1%
9 CFG5

1
@ R73 1 2
9 CFG19
@ R74 4.02K_0402_1%
2.21K_0402_1%
@ R75 1 2
9 CFG20
4.02K_0402_1%

2
@ R76 1 2
9 CFG11
2.21K_0402_1%
、
04/29 MV-1 Delete CFG5、
@ R77 1 2
CFG7、、CFG12、 、CFG13、 、CFG16 9 CFG12
2.21K_0402_1%

@ R78 1 2
9 CFG13
2.21K_0402_1%
@ R79 1 2
9 CFG6
2.21K_0402_1% @ R80 1 2
9 CFG14
2.21K_0402_1%
@ R81 1 2
9 CFG7
2.21K_0402_1% @ R82 1 2
9 CFG15
2.21K_0402_1%
@ R83 1 2
9 CFG8
2.21K_0402_1%

@ R84 1 2 @ R85 1 2
9 CFG9 9 CFG17
2.21K_0402_1% 2.21K_0402_1%
A @ R86 @ R87 A
9 CFG10 1 2 9 CFG18 1 2
2.21K_0402_1% 2.21K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 11 of 46
5 4 3 2 1
 5 4 3 2 1

+3VS_DAC_BG +3VS **RED Mark: Means UMA & dis@ Power select**
R88
1 2 ~It check by INTEL Graphics Disable +VCCP
+1.05VS_DPLLA
Change the size H to L.10/29 +VCCP

0.022U_0402_16V7K
BLM18PG181SN1D_0603
Guidelines~ +VCCP

0.1U_0402_16V4Z

10U_0805_10V4Z
+V1.05VS_AXF
1

@ 1 1 1 U2H 1 2 R93
0_0603_5%

C68

C69

C70
R90 1 2
R89

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
852mA U13 1 @ 10U_FLC-453232-100K_0.25A_10% 0_0603_5%
VTT

220U_6.3V

4.7U_0805_10V4Z

220U_6.3V

C73

C74
73mA T13 1 1 1
2 2 2 VTT

C77
B27 U12 +
1 1 1
2

VCCA_CRT_DAC VTT +

C3200

C72

C78

C79
+3VS_DAC_CRT A26 T12
VCCA_CRT_DAC VTT
VTT U11
2.68mA T11 2 2 2
VTT 2 2 2 2
A25 U10

CRT
+3VS_DAC_BG VCCA_DAC_BG VTT
B25 T10
VSSA_DAC_BG VTT
D
+3VS_DAC_CRT U9 D
+3VS VTT
T9
R91 VTT
VTT U8
1 2 +1.05VS_DPLLA F47 64.8mA T8
VCCA_DPLLA VTT
0.022U_0402_16V7K

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
BLM18PG181SN1D_0603 U7

VTT
VTT +1.5V_SM_CK
0.1U_0402_16V4Z

L48 64.8mA T7 1 1 1 +1.5V

PLL
+1.05VS_DPLLB VCCA_DPLLB VTT
1

+1.05VS_DPLLB +VCCP
C75

C76

<BOM Structure>
1 1 U6 R95
VTT
@

0_0603_5%

C80

C81

C82
+1.05VS_HPLL AD1 24mA T6 R94 1 2
VCCA_HPLL VTT

10U_0805_10V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
U5 1 2 0_0805_5%
VTT 2 2 2
R92

0.1U_0402_16V4Z
+1.05VS_MPLL AE1 139.2mA T5 10U_FLC-453232-100K_0.25A_10% 1 @ 1 1
2 2 VCCA_MPLL VTT

C86

C87

10U_0805_10V4Z

C83

C84

C85
V3
2

13.2mA VTT
U3 1 1

A LVDS
VTT
+1.8V_TXLVDS J48 VCCA_LVDS VTT V2
U2 2 2 2
1 VTT
C88 J47 T2
VSSA_LVDS VTT 2 2
V1
@ R96 1000P_0402_50V7K 414uA VTT
U1
2 VTT
+3VS 1 2
0_0603_5% AD48
+1.5VS_PEG_BG VCCA_PEG_BG
R97

A PEG
+1.5VS 1 2 +1.5VS_TVDAC
0_0603_5% 50mA +1.05VS_HPLL +VCCP +1.5VS
1 +1.05VS_PEGPLL AA48 R98 R99
C89 VCCA_PEG_PLL
1 2 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
MBK2012121YZF_0805 0_0805_5%
0.1U_0402_16V4Z AR20
2 VCCA_SM

0.1U_0402_16V4Z

10U_0805_10V4Z
AP20 1 1 1 1
VCCA_SM

C90

C91
AN20 720mA
VCCA_SM
POWER

C92

C93
AR17
VCCA_SM
AP17
+VCCP VCCA_SM 2 2 2 2
+1.05VS_A_SM AN17 VCCA_SM
AT16 VCCA_SM
R100 AR16 VCCA_SM

A SM
1 2 AP16
C VCCA_SM C
10U_0805_10V4Z

1 0_0805_5%
1 1 1
C94

+
C95

C96 C97 +VCCP

+VCC_PEG
220U_6.3V 4.7U_0805_10V4Z
2 2 2 2 321.35mA +1.05VS_MPLL +VCCP R102
1U_0603_10V4Z AP28 R101 1 2
VCCA_SM_CK 0_0805_5%
AN28 B22 +V1.05VS_AXF 1 2
VCCA_SM_CK VCC_AXF

10U_0805_10V4Z
AP25 26mA B21 MBK2012121YZF_0805 1

AXF
+1.05VS_A_SM_CK VCCA_SM_CK VCC_AXF

220U_6.3V
R103 AN25 A21 1
VCCA_SM_CK VCC_AXF +

C101
1 2 AN24 26mA 1 1
VCCA_SM_CK
1U_0603_10V4Z

0.1U_0402_16V4Z

C98
0_0603_5% AM28 124mA C99 C100
VCCA_SM_CK_NCTF
10U_0805_10V4Z

AM26
VCCA_SM_CK_NCTF 2 2
1 1 1 1 AM25
VCCA_SM_CK_NCTF A CK 0.1U_0402_16V4Z
2 2
10U_0805_10V4Z
C103

C104

C105

C102 AL25 BF21

SM CK
VCCA_SM_CK_NCTF VCC_SM_CK +1.5V_SM_CK
AM24 BH20
1U_0603_10V4Z VCCA_SM_CK_NCTF VCC_SM_CK
AL24 BG20
2 2 2 2 VCCA_SM_CK_NCTF VCC_SM_CK
AM23 BF20
VCCA_SM_CK_NCTF VCC_SM_CK
AL23
VCCA_SM_CK_NCTF 118.8mA
TVA 24.15mA +1.05VS_DMI
TVB 39.48mA K47 +1.05VS_PEGPLL +VCCP +VCCP
VCC_TX_LVDS +1.8V_TXLVDS
B24 TVX 24.15mA L1 R104
VCCA_TV_DAC +3VS_HV
A24 C35 1 2 1 2
TV

+3VS_TVDAC VCCA_TV_DAC VCC_HV

105.3mA B35 BLM18PG121SN1D_0603 0_0603_5%
VCC_HV

0.1U_0402_16V4Z

10U_0805_10V4Z

0.1U_0402_16V4Z
A35
HV

R124 VCC_HV
1 1

<BOM

0.1U_0402_16V4Z

C106

C108
1 2 A32 50mA 1
HDA

VCC_HDA

C109
0_0402_5% V48 +VCC_PEG 1
VCC_PEG

C107
<BOM Structure> 1732mA U48
VCC_PEG

Structure>
2 2
V47
PEG

VCC_PEG 2
U47
D TV/CRT

58.67mA VCC_PEG 2
pull low when no HDMI on 09/22 +1.5VS_TVDAC M25 VCCD_TVDAC VCC_PEG U46

B +1.5VS_QDAC L28 48.363mA B

VCCD_QDAC
AH48 +1.05VS_DMI
157.2mA VCC_DMI
+1.05VS_HPLL AF1 AF48
VCCD_HPLL VCC_DMI
AH47
DMI

50mA VCC_DMI
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VCC_DMI AG47
+VCCP_D
456mA
M38
LVDS

VCCD_LVDS D3 R105 R106

L37 A8
VTTLF

+1.8V_LVDS VCCD_LVDS VTTLF

VTTLF L1 +VCCP 2 1 1 2 1 2 +3VS_HV
60.31mA AB2 10_0402_5% 0_0402_5%
VTTLF CH751H-40PT_SOD323-2
0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

+3VS
1 1 1
C110

C111

C112

CANTIGA ES_FCBGA1329

2 2 2

+1.8V_LVDS +1.8V_TXLVDS
40 mils
R107 R108
1 2 +1.8V 1 2 +1.8V

@R109
@

10U_0805_10V4Z

1U_0603_10V4Z

@R110
@

1000P_0402_50V7K
0_0603_5% 0_0603_5%

1
R109

R110
+1.5VS_QDAC 1 1 1 @
+1.5VS

0_0603_5%

C113

C114

0_0603_5%

C116

220U_6.3V
+3VS_TVDAC 1
+3VS +

C115
R111 R112
1 2 1 2 2 2
2

2
2 2
0.022U_0402_16V7K

0.022U_0402_16V7K

BLM18PG181SN1D_0603 100_0603_1%
1

A A
@ R113

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 @
1
0_0603_5%

C117

C118

@R114
@

C119

C120

220U_D2_4VM

1 1 1 1
R114

0_0603_5%

C121

+
2

2 2 2 2 2
2

Security Classification
Classification
2007/08/28
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 12 of 46
5 4 3 2 1
 5 4 3 2 1

U2G +VCCP
0421 Change size to B2 for DFX 3000mA
Extnal Graphic: 1210.34mA request AP33 W28
VCC_SM VCC_AXG_NCTF
AN33 VCC_SM VCC_AXG_NCTF V28
integrated Graphic: 1930.4mA +1.5V BH32 W26 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
U2F VCC_SM VCC_AXG_NCTF
BG32 V26
VCC_SM VCC_AXG_NCTF

330U_B2_2.5VM_R15M

0.01U_0402_16V7K
+VCCP BF32 W25
VCC_SM VCC_AXG_NCTF 1 1 1

10U_0805_10V4Z

10U_0805_10V4Z
1 BD32 V25 C127 C128 C129
VCC_SM VCC_AXG_NCTF
1 1 2 BC32 VCC_SM VCC_AXG_NCTF W24

@
C126

C122

C130

C123
D
AG34 + BB32 V24 D
VCC VCC_SM VCC_AXG_NCTF 2 2 2
AC34 VCC BA32 VCC_SM VCC_AXG_NCTF W23
AB34 VCC AY32 VCC_SM VCC_AXG_NCTF V23
AA34 2 2 2 1 AW32 AM21 0.22U_0402_10V4Z
VCC VCC_SM VCC_AXG_NCTF
Y34 AV32 AL21
VCC VCC_SM VCC_AXG_NCTF
V34 VCC AU32 VCC_SM VCC_AXG_NCTF AK21
U34 AT32 W21
VCC 0317 change value VCC_SM VCC_AXG_NCTF
AM33 VCC AR32 VCC_SM VCC_AXG_NCTF V21
AK33 VCC AP32 VCC_SM VCC_AXG_NCTF U21

POWER
AJ33 AN32 AM20
VCC VCC_SM VCC_AXG_NCTF
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z
AG33 VCC BH31 VCC_SM VCC_AXG_NCTF AK20
220U_6.3V

10U_0805_10V4Z

1 AF33 BG31 W20

VCC CORE
VCC VCC_SM VCC_AXG_NCTF
1 1 1 1 BF31 VCC_SM VCC_AXG_NCTF U20
C131

C124

C132

C133

+ C125
AE33 BG30 AM19
VCC VCC_SM VCC_AXG_NCTF
AC33 BH29 AL19
VCC VCC_SM VCC_AXG_NCTF
AA33 BG29 AK19
2 2 2 2 2 VCC VCC_SM VCC_AXG_NCTF
Y33 VCC BF29 VCC_SM VCC_AXG_NCTF AJ19
W33 BD29 AH19
VCC VCC_SM VCC_AXG_NCTF
V33 BC29 AG19

VCC SM
VCC VCC_SM VCC_AXG_NCTF
U33 BB29 AF19
VCC VCC_SM VCC_AXG_NCTF
AH28 BA29 AE19
VCC VCC_SM VCC_AXG_NCTF
AF28 AY29 AB19
VCC VCC_SM VCC_AXG_NCTF
AC28 VCC AW29 VCC_SM VCC_AXG_NCTF AA19
AA28 VCC AV29 VCC_SM VCC_AXG_NCTF Y19
AJ26 AU29 W19
VCC VCC_SM VCC_AXG_NCTF
AG26 VCC AT29 VCC_SM VCC_AXG_NCTF V19
AE26 AR29 U19
VCC VCC_SM VCC_AXG_NCTF
AC26 AP29 AM17
VCC VCC_SM VCC_AXG_NCTF
AH25 VCC VCC_AXG_NCTF AK17
AG25 VCC BA36 VCC_SM/NC VCC_AXG_NCTF AH17
AF25 BB24 AG17
VCC VCC_SM/NC VCC_AXG_NCTF
AG24 BD16 AF17
C VCC +VCCP VCC_SM/NC VCC_AXG_NCTF C
AJ23 VCC BB21 VCC_SM/NC VCC_AXG_NCTF AE17
AH23 AW16 AC17
VCC VCC_SM/NC VCC_AXG_NCTF
AF23 AW13 AB17
VCC VCC_SM/NC VCC_AXG_NCTF
POWER
VCC_NCTF AM32 AT13 VCC_SM/NC VCC_AXG_NCTF Y17
T32 VCC VCC_NCTF AL32 VCC_AXG_NCTF W17
VCC_NCTF
AK32 6326.84mA VCC_AXG_NCTF
V17

VCC GFX NCTF

VCC_NCTF AJ32 VCC_AXG_NCTF AM16
AH32 Y26 AL16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
VCC_NCTF AG32 AE25 VCC_AXG VCC_AXG_NCTF AK16
AE32 AB25 AJ16
VCC_NCTF +VCCP VCC_AXG VCC_AXG_NCTF
VCC_NCTF AC32 AA25 VCC_AXG VCC_AXG_NCTF AH16
AA32 AE24 AG16
VCC_NCTF 10U_0805_10V4Z 0.1U_0402_16V4Z VCC_AXG VCC_AXG_NCTF
VCC_NCTF Y32 AC24 VCC_AXG VCC_AXG_NCTF AF16
W32 AA24 AE16
VCC_NCTF VCC_AXG VCC_AXG_NCTF

330U_6.3V
U32 Y24 AC16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AM30 1 1 1 1 1 AE23 AB16
VCC_NCTF C134 C136 C137 C138 VCC_AXG VCC_AXG_NCTF
AL30 AC23 AA16
VCC_NCTF + C135 VCC_AXG VCC_AXG_NCTF
AK30 AB23 Y16
VCC_NCTF 1U_0603_10V4Z VCC_AXG VCC_AXG_NCTF
AH30 AA23 W16
VCC_NCTF 2 2 2 2 VCC_AXG VCC_AXG_NCTF
VCC_NCTF AG30 AJ21 VCC_AXG VCC_AXG_NCTF V16
AF30 2 AG21 U16
VCC_NCTF 10U_0805_10V4Z VCC_AXG VCC_AXG_NCTF
AE30 AE21
VCC_NCTF VCC_AXG
AC30 AC21
VCC_NCTF VCC_AXG
AB30 AA21
VCC_NCTF VCC_AXG
AA30 Y21
VCC_NCTF VCC_AXG
Y30 AH20
VCC NCTF

VCC_NCTF VCC_AXG
VCC_NCTF W30 AF20 VCC_AXG
V30 AE20
VCC_NCTF VCC_AXG
U30 AC20
VCC_NCTF VCC_AXG
AL29 AB20
VCC_NCTF VCC_AXG
AK29 AA20
VCC_NCTF VCC_AXG
AJ29 T17
B VCC_NCTF VCC_AXG B
VCC_NCTF AH29 T16 VCC_AXG
VCC_NCTF AG29 AM15 VCC_AXG
AE29 AL15
VCC_NCTF VCC_AXG
VCC_NCTF AC29 AE15 VCC_AXG
AA29 AJ15
VCC_NCTF VCC_AXG
Y29 AH15
VCC_NCTF VCC_AXG
W29 AG15
VCC_NCTF VCC_AXG
V29 AF15
VCC_NCTF VCC_AXG
AL28 AB15
VCC_NCTF VCC_AXG
VCC_NCTF AK28 AA15 VCC_AXG
AL26 Y15

VCC GFX
VCC_NCTF VCC_AXG
AK26 V15
VCC_NCTF VCC_AXG
VCC_NCTF AK25 U15 VCC_AXG
AK24 AN14
VCC_NCTF VCC_AXG
VCC_NCTF AK23 AM14 VCC_AXG
U14 AV44 VCCSM_LF1
VCC_AXG VCC_SM_LF
T14 BA37 VCCSM_LF2

VCC SM LF
VCC_AXG VCC_SM_LF
AM40 VCCSM_LF3
VCC_SM_LF
AV21 VCCSM_LF4
VCC_SM_LF
AY5 VCCSM_LF5
VCC_SM_LF
AM10 VCCSM_LF6
VCC_SM_LF
CANTIGA ES_FCBGA1329
VCC_SM_LF BB13 VCCSM_LF7

C139 0.1U_0402_16V4Z

C140 0.1U_0402_16V4Z

C141

C142

C143

C144

C145
1 1 1 1 1 1 1

PAD T42 AJ14

VCC_AXG_SENSE
PAD T43 AH14
VSS_AXG_SENSE 2 2 2 2 2 2 2

0.22U_0603_10V7K

0.22U_0603_10V7K

0.47U_0402_6.3V6K

1U_0603_10V4Z

1U_0603_10V4Z
A A

CANTIGA ES_FCBGA1329

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 13 of 46
5 4 3 2 1
 5 4 3 2 1

U2J
U2I BG21 AH8
VSS VSS
L12 Y8
VSS VSS
AU48 AM36 AW21 L8
VSS VSS VSS VSS
AR48 VSS VSS AE36 AU21 VSS VSS E8
AL48 VSS VSS P36 AP21 VSS VSS B8
BB47 L36 AN21 AY7
VSS VSS VSS VSS
AW47 J36 AH21 AU7
VSS VSS VSS VSS
AN47 VSS VSS F36 AF21 VSS VSS AN7
AJ47 VSS VSS B36 AB21 VSS VSS AJ7
AF47 VSS VSS AH35 R21 VSS VSS AE7
D D
AD47 VSS VSS AA35 M21 VSS VSS AA7
AB47 VSS VSS Y35 J21 VSS VSS N7
Y47 VSS VSS U35 G21 VSS VSS J7
T47 T35 BC20 BG6
VSS VSS VSS VSS
N47 BF34 BA20 BD6
VSS VSS VSS VSS
L47 VSS VSS AM34 AW20 VSS VSS AV6
G47 AJ34 AT20 AT6
VSS VSS VSS VSS
BD46 VSS VSS AF34 AJ20 VSS VSS AM6
BA46 VSS VSS AE34 AG20 VSS VSS M6
AY46 W34 Y20 C6
VSS VSS VSS VSS
AV46 VSS VSS B34 N20 VSS VSS BA5
AR46 A34 K20 AH5
VSS VSS VSS VSS
AM46 VSS VSS BG33 F20 VSS VSS AD5
V46 BC33 C20 Y5
VSS VSS VSS VSS
R46 BA33 A20 L5
VSS VSS VSS VSS
P46 AV33 BG19 J5
VSS VSS VSS VSS
H46 VSS VSS AR33 A18 VSS VSS H5
F46 AL33 BG17 F5
VSS VSS VSS VSS
BF44 VSS VSS AH33 BC17 VSS VSS BE4
AH44 AB33 AW17
VSS VSS VSS
AD44 P33 AT17 BC3
AA44
Y44
VSS
VSS
VSS
VSS
VSS
VSS
L33
H33
R17
M17
VSS
VSS
VSS
VSS VSS
VSS
VSS
AV3
AL3
U44 VSS VSS N32 H17 VSS VSS R3
T44 K32 C17 P3
M44
F44
VSS
VSS
VSS
VSS VSS
VSS
VSS
F32
C32 BA16
VSS

VSS
VSS
VSS
VSS
F3
BA2
BC43 A31 AW2
VSS VSS VSS
AV43 VSS VSS AN29 AU16 VSS VSS AU2
AU43 VSS VSS T29 AN16 VSS VSS AR2
AM43 N29 N16 AP2
VSS VSS VSS VSS
J43 K29 K16 AJ2
C VSS VSS VSS VSS C
C43 VSS VSS H29 G16 VSS VSS AH2
BG42 F29 E16 AF2
VSS VSS VSS VSS
AY42 A29 BG15 AE2
VSS VSS VSS VSS
AT42 VSS VSS BG28 AC15 VSS VSS AD2
AN42 VSS VSS BD28 W15 VSS VSS AC2
AJ42 BA28 A15 Y2
VSS VSS VSS VSS
AE42 VSS VSS AV28 BG14 VSS VSS M2
N42 AT28 AA14 K2
VSS VSS VSS VSS
L42 VSS VSS AR28 C14 VSS VSS AM1
BD41 AJ28 BG13 AA1
VSS VSS VSS VSS
AU41 VSS VSS AG28 BC13 VSS VSS P1
AM41 AE28 BA13 H1
VSS VSS VSS VSS
AH41 VSS VSS AB28
AD41 Y28 U24
VSS VSS VSS
AA41 P28 AN13 U28
VSS VSS VSS VSS
Y41 K28 AJ13 U25
VSS VSS VSS VSS
U41 H28 AE13 U29
VSS VSS VSS VSS
T41 F28 N13
VSS VSS VSS
M41 C28 L13
VSS VSS VSS
G41 VSS VSS BF26 G13 VSS VSS_NCTF AF32
B41 AH26 E13 AB32
VSS VSS VSS VSS_NCTF
BG40 AF26 BF12 V32
VSS VSS VSS VSS_NCTF
BB40 AB26 AV12 AJ30
VSS VSS VSS VSS_NCTF
AV40 AA26 AT12 AM29
VSS VSS VSS VSS_NCTF
AN40 C26 AM12 AF29
VSS VSS VSS VSS_NCTF
H40 B26 AA12 AB29

VSS NCTF
VSS VSS VSS VSS_NCTF
E40 VSS VSS BH25 J12 VSS VSS_NCTF U26
AT39 BD25 A12 U23
VSS VSS VSS VSS_NCTF
AM39 BB25 BD11 AL20
VSS VSS VSS VSS_NCTF
AJ39 AV25 BB11 V20
VSS VSS VSS VSS_NCTF
AE39 AR25 AY11 AC19
VSS VSS VSS VSS_NCTF
N39 AJ25 AN11 AL17
B VSS VSS VSS VSS_NCTF B
L39 VSS VSS AC25 AH11 VSS VSS_NCTF AJ17
B39 VSS VSS Y25 VSS_NCTF AA17
BH38 N25 Y11 U17
VSS VSS VSS VSS_NCTF
BC38 VSS VSS L25 N11 VSS
BA38 J25 G11
VSS VSS VSS
AU38 G25 C11 BH48

VSS SCB
VSS VSS VSS VSS_SCB
AH38 E25 BG10 BH1
VSS VSS VSS VSS_SCB
AD38 BF24 AV10 A48
VSS VSS VSS VSS_SCB
AA38 AD12 AT10 C1
VSS VSS VSS VSS_SCB
Y38 VSS VSS AY24 AJ10 VSS VSS_SCB A3
U38 VSS VSS AT24 AE10 VSS
T38 AJ24 AA10 E1
VSS VSS VSS NC
J38 VSS VSS AH24 M10 VSS NC D2
F38 AF24 BF9 C3
VSS VSS VSS NC
C38 VSS VSS AB24 BC9 VSS NC B4
BF37 R24 AN9 A5
VSS VSS VSS NC
BB37 L24 AM9 A6
VSS VSS VSS NC
AW37 K24 AD9 A43
VSS VSS VSS NC
AT37 J24 G9 A44
VSS VSS VSS NC
AN37 G24 B9 B45

NC
VSS VSS VSS NC
AJ37 F24 BH8 C46
VSS VSS VSS NC
H37 VSS VSS E24 BB8 VSS NC D47
C37 BH23 AV8 B47
VSS VSS VSS NC
BG36 VSS VSS AG23 AT8 VSS NC A46
BD36 Y23 F48
VSS VSS NC
AK15 B23 E48
VSS VSS NC
AU36 VSS VSS A23 NC C48
AJ6 B48
VSS NC

CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 14 of 46
5 4 3 2 1
 5 4 3 2 1

10 DDR_A_DQS#[0..7] JDIMM1
+V_DDR3_DIMM_REF 1 VREF_DQ VSS1 2
10 DDR_A_D[0..63] 3 4 DDR_A_D4
VSS2 DQ4

0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C166

C167
1 1 DDR_A_D1 7 8
10 DDR_A_DM[0..7] DQ1 VSS3
9 10 DDR_A_DQS#0
DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
10 DDR_A_DQS[0..7] 11 DM0 DQS0 12
13 VSS5 VSS6 14
2 2 DDR_A_D2 DDR_A_D6
10 DDR_A_MA[0..14] 15 16
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18
DQ3 DQ7
Layout Note: DDR_A_D8
19 VSS7 VSS8 20
DDR_A_D12
21 DQ8 DQ12 22
Place these 4 caps near Command DDR_A_D9 23 24 DDR_A_D13
D DQ9 DQ13 D
and Control signals of DIMMA DDR_A_DQS#1
25 VSS9 VSS10 26
DDR_A_DM1
Layout Note: DDR_A_DQS1
27 DQS#1 DM1 28
SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# 9,16
Place near 31 32
DDR_A_D10 VSS11 VSS12 DDR_A_D14
JDIMM1 33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 44
+1.5V DDR_A_DQS#2 VSS15 VSS16 DDR_A_DM2
45 DQS#2 DM2 46
DDR_A_DQS2 47 48
DQS2 VSS17 DDR_A_D22
49 VSS18 DQ22 50

330U_6.3V
DDR_A_D18 51 52 DDR_A_D23
DQ18 DQ23
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
1 1 1 1 1 1 1 1 1 1 55 56
VSS20 DQ28
C152

C147

C153

C154

C155

C158

C156

C148

C149

C157

C150
+ DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 60
DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
2 2 2 2 2 2 2 2 2 2 2 DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
65 66
DDR_A_D26 VSS23 VSS24 DDR_A_D30
67 68
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
9 DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA 9
+1.5V 75 VDD1 VDD2 76 +1.5V
77 78 @ R1107 1 2 0_0402_5%
DDR_A_BS2 NC1 A15 DDR_A_MA14
10 DDR_A_BS2 79 80
BA2 A14
81 82
C DDR_A_MA12 VDD3 VDD4 DDR_A_MA11 C
Layout Note: DDR_A_MA9
83 A12/BC# A11 84
DDR_A_MA7
85 86
Place near JDIMM1.203 & JDIMM1.204 A9 A7
87 88
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 94
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD9 VDD10 100
M_CLK_DDR0 101 102 M_CLK_DDR1
9 M_CLK_DDR0 M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1 M_CLK_DDR1 9
9 M_CLK_DDR#0 103 CK0# CK1# 104 M_CLK_DDR#1 9
+0.75VS
Modify+0.75V to +0.75VS 09/22 DDR_A_MA10
105
VDD11 VDD12
106
DDR_A_BS1
107 A10/AP BA1 108 DDR_A_BS1 10
DDR_A_BS0 109 110 DDR_A_RAS#
10 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 10
111 112
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
113 114 DDR_CS0_DIMMA# 9
10 DDR_A_WE# WE# S0#
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

DDR_A_CAS# 115 116 M_ODT0

10 DDR_A_CAS# CAS# ODT0 M_ODT0 9
117 118
DDR_A_MA13 VDD15 VDD16 M_ODT1
1 1 1 1 1 119 120 M_ODT1 9
A13 ODT1
C159

C160

C161

C162

C163

DDR_CS1_DIMMA# 121 122

9 DDR_CS1_DIMMA# S1# NC2
123 124
VDD17 VDD18 +V_DDR3_DIMM_REF
125 126
2 2 2 2 2 NCTEST VREF_CA
127 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36
129 130
DQ32 DQ36

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37
133 134 1 1
DDR_A_DQS#4 VSS29 VSS30 DDR_A_DM4
135 DQS#4 DM4 136

C146

C151
DDR_A_DQS4 137 138
DQS4 VSS31 DDR_A_D38
139 140
DDR_A_D34 VSS32 DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS33 DDR_A_D44
145 146
B DDR_A_D40 VSS34 DQ44 DDR_A_D45 B
147 DQ40 DQ45 148
+1.5V DDR_A_D41 149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
1

155 156
R1108 DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 158
1K_0402_1% DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
+V_DDR3_DIMM_REF DQ43 DQ47
Modify net name 09/23 DDR_A_D48
161
VSS39 VSS40
162
DDR_A_D52
163 164
2

DDR_A_D49 DQ48 DQ52 DDR_A_D53

165 DQ49 DQ53 166
167 VSS41 VSS42 168
1
2.2U_0805_16V4Z

0.1U_0402_16V4Z

DDR_A_DQS#6 169 170 DDR_A_DM6

DDR_A_DQS6 DQS#6 DM6
1 1 171 DQS6 VSS43 172
C164

C165

R1109 173 174 DDR_A_D54

1K_0402_1% DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
2

2 2 DQ51 VSS45 DDR_A_D60

179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_A_DQS#7
185 186
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
195 196
R116 1 VSS51 VSS52 PM_EXTTS#0
2 10K_0402_5% 197 198 PM_EXTTS#0 9
SA0 EVENT# CLK_SMBDATA
+3VS 199 VDDSPD SDA 200 CLK_SMBDATA 16,17
201 202 CLK_SMBCLK 16,17
SA1 SCL
2.2U_0603_6.3V4Z

0.1U_0402_16V4Z

203 204 +0.75VS

VTT1 VTT2
1 10K_0402_5%

1 1
205 206
G1 G2
C171

C172

R115

A TYCO_C-2013289 A
2 2
2

CONN@
SO-DIMM A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 15 of 46
5 4 3 2 1
 5 4 3 2 1

+V_DDR3_DIMM_REF
10 DDR_B_DQS#[0..7]
JDIMM2
10 DDR_B_D[0..63] 1 2
VREF_DQ VSS1 DDR_B_D4
3 4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
10 DDR_B_DM[0..7] 5 6
DDR_B_D1 DQ0 DQ5
7 8
DQ1 VSS3 DDR_B_DQS#0
10 DDR_B_DQS[0..7] 9 VSS4 DQS#0 10

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
10 DDR_B_MA[0..14] 1 1 13 14
VSS5 VSS6

C173

C182
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
2 2 DDR_B_D8 DDR_B_D12
D
Layout Note: DDR_B_D9
21 DQ8 DQ12 22
DDR_B_D13 D
23 DQ9 DQ13 24
Place these 4 caps near Command 25 26
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
Layout Note: and Control signals of DIMMB DDR_B_DQS1
27 DQS#1 DM1 28
SM_DRAMRST#
29 30 SM_DRAMRST# 9,15
Place near DQS1 RESET#
31 32
DDR_B_D10 VSS11 VSS12 DDR_B_D14
JDIMM2 DDR_B_D11
33 DQ10 DQ14 34
DDR_B_D15
35 36
DQ11 DQ15
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
+1.5V DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 52
DDR_B_D19 DQ18 DQ23
53 54
DQ19 VSS19
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
55 56 DDR_B_D28
DDR_B_D24 VSS20 DQ28 DDR_B_D29
1 1 1 1 1 1 1 1 1 1 57 58
DQ24 DQ29
C174

C175

C176

C183

C177

C184

C178

C179

C180

C181
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 62
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 64
2 2 2 2 2 2 2 2 2 2 DM3 DQS3
65 66
DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 DQ26 DQ30 68
DDR_B_D27 69 70 DDR_B_D31
DQ27 DQ31
71 72
VSS25 VSS26

DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
9 DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB 9
+1.5V 75 VDD1 VDD2 76 +1.5V
77 78 @ R1110 1 2 0_0402_5%
NC1 A15

2.2U_0805_16V4Z

0.1U_0402_16V4Z
DDR_B_BS2 79 80 DDR_B_MA14
C 10 DDR_B_BS2 BA2 A14 C
81 VDD3 VDD4 82 1 1
Layout Note: DDR_B_MA12 83 84 DDR_B_MA11
A12/BC# A11

C190

C191
DDR_B_MA9 85 86 DDR_B_MA7
Place near JDIMM2.203 & JDIMM2.204 A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6 2 2
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
9 M_CLK_DDR2 101 CK0 CK1 102 M_CLK_DDR3 9
M_CLK_DDR#2 103 104 M_CLK_DDR#3
+0.75VS 9 M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 9
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 10
10 DDR_B_BS0 109 110 DDR_B_RAS# 10
BA0 RAS#
111 112
VDD13 VDD14
1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_6.3V6M

DDR_B_WE# 113 114 DDR_CS2_DIMMB#

10 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 9
DDR_B_CAS# 115 116 M_ODT2
10 DDR_B_CAS# CAS# ODT0 M_ODT2 9
1 1 1 1 1 117 118
VDD15 VDD16
C185

C186

C187

C188

C189

DDR_B_MA13 119 120 M_ODT3

DDR_CS3_DIMMB# A13 ODT1 M_ODT3 9
9 DDR_CS3_DIMMB# 121 122
S1# NC2
123 124
2 2 2 2 2 VDD17 VDD18
125 126 +V_DDR3_DIMM_REF
NCTEST VREF_CA
127 128
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 130
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 DDR_B_DM4
DDR_B_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_B_D38
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 142
DDR_B_D35 DQ34 DQ39
143 144
B DQ35 VSS33 DDR_B_D44 B
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152
DDR_B_DM5 153 154 DDR_B_DQS5
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6
169 DQS#6 DM6 170
DDR_B_DQS6 171 172
DQS6 VSS43 DDR_B_D54
173 VSS44 DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_B_DQS#7
185 186
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 DQ58 DQ62 192
DDR_B_D59 193 194 DDR_B_D63
DQ59 DQ63
195 196
R1111 2 VSS51 VSS52 PM_EXTTS#1
1 10K_0402_5% 197 SA0 EVENT# 198 PM_EXTTS#1 9
199 200 CLK_SMBDATA
+3VS VDDSPD SDA CLK_SMBDATA 15,17
R1112 2 1 10K_0402_5% 201 202
+3VS SA1 SCL CLK_SMBCLK 15,17
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

203 204 +0.75VS

VTT1 VTT2
1 1
205 G1 G2 206
C192

C1403

A A
TYCO_C-2013310
2 2 CONN@

SO-DIMM B
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 16 of 46
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB R121
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 1 2
1 1 1 1 1 1 1
0_0805_5% C199 C200 C201 C202 C203 C204 C205
0 0 0 266 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
Routing the trace at least 10mil +VCCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0
CLK_XTAL_OUT
D CLK_XTAL_IN
Place close to U51 D
0 1 1 166 100 33.3 14.318 96.0 48.0 R122
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
Y1 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 1 2 C206 C207 C208 C209 C210 C211 C212
14.318MHZ_16PF_7A14300083
2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
1 1 0 400 100 33.3 14.318 96.0 48.0 C213 C214
18P_0402_50V8J 18P_0402_50V8J
1 1
1 1 1 Reserved
Vendor suggests 22pF
@ R123 +3VS_CK505 +1.05VS_CK505
1 2 +VCCP
56_0402_5% XDP/ITP
R126 1 2 475_0402_1% R_CLKREQ#_7 R_MCH_3GPLL R127 1 2 0_0402_5%
9 CLKREQ#_7 R_MCH_BCLK# R_MCH_3GPLL# CLK_MCH_3GPLL 9
R128 R130 1 2 0_0402_5% R131 1 2 0_0402_5% 3G_PLL
FSA 9 CLK_MCH_BCLK# R_MCH_BCLK R_CLKREQ#_6 CLK_MCH_3GPLL# 9
1 2 1 2 NB R132 1 2 0_0402_5% R133 1 2 475_0402_1%
MCH_CLKSEL0 9 9 CLK_MCH_BCLK R_CPU_BCLK# R_CLK_PCIE_MCARD2 CLKREQ#_6 26
2.2K_0402_5% R129 R134 1 2 0_0402_5% R135 1 2 0_0402_5%
6 CLK_CPU_BCLK# CLK_PCIE_MCARD2 26
R138 1K_0402_5% CPU R136 1 2 0_0402_5% R_CPU_BCLK R_CLK_PCIE_MCARD2# R137 1 2 0_0402_5% MiniCard_2(WLAN)
6 CLK_CPU_BCLK CLK_PCIE_MCARD2# 26
7 CPU_BSEL0 1 2 +3VS_CK505
0_0402_5%
1

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
R139 U3
1K_0402_5% +3VS_CK505 +1.05VS_CK505

VDD_CPU_IO

VDD_SRC_IO
CPU_0
CPU_0#

CPU_1
CPU_1#

CLKREQ_7#

SRC_8#/CPU_ITP#

SRC_7
SRC_7#

CLKREQ_6#
SRC_6
SRC_6#
SRC_8/CPU_ITP
VDD_CPU

VSS_CPU

VSS_SRC

VDD_SRC
C C
2

@ R141 1 2 0_0402_5%
22,41 VGATE
@ R142 1 2 0_0402_5%
+VCCP 41 CLK_ENABLE# R_CKPWRGD H_STP_PCI#
R140 1 2 0_0402_5% 1 54
22 CK_PWRGD FSB CKPWRGD/PD# PCI_STOP# H_STP_CPU# H_STP_PCI# 22
2 53 H_STP_CPU# 22
FS_B/TEST_MODE CPU_STOP#
3 VSS_REF VDD_SRC_IO 52
2

@ No Debug port anymore CLK_XTAL_OUT

R143 CLK_XTAL_IN
4
5
XTAL_OUT
XTAL_IN
SRC_10#
SRC_10
51
50
delete TV on 09/17 need check clkreq#
1K_0402_5% 6 49
R147 FSC VDD_REF CLKREQ_10#
2 33_0402_1%
22 CLK_14M_ICH
1
REF1
7
8
REF_0/FS_C/TEST_ SRC_11 48
47
delete clock for cardreader on 09/18
1

FSB T44 CLK_SMBDATA REF_1 SRC_11#

1 2 MCH_CLKSEL1 9 9 SDA CLKREQ_11# 46
R150 CLK_SMBCLK 10 45 R_CLK_PCIE_LAN# R152 1 2 0_0402_5%
SCL SRC_9# R_CLK_PCIE_LAN CLK_PCIE_LAN# 25
R154 1K_0402_5% 11 44 R153 1 2 0_0402_5% LAN
26 CLK_DEBUG_PORT_1 NC SRC_9 CLKREQ#_9 R190 CLK_PCIE_LAN 25
7 CPU_BSEL1 1 2 12 43 1 2 475_0402_1% LAN_CLKREQ# 25
0_0402_5% R393 1 PCI2_1 VDD_PCI CLKREQ_9#
2 39_0402_1% 13 42
PCI_1 VSS_SRC
1

@ R158 1 2 33_0402_1% 27_SEL

14
15
PCI_2
PCI_3
CLKREQ_4#
SRC_4#
41
40
delete New card on 09/17 need check clkreq#
R157 31 CLK_PCI_EC PCI_CLK3 16 39
PCI_4/SEL_LCDCL SRC_4

USB_1/CLKREQ_A#
0_0402_5% R161 1 2 33_0402_1% ITP_EN 17 38

LCDCLK#/27M_SS
20 CLK_PCI_ICH PCIF_5/ITP_EN VDD_SRC_IO

SRC_0#/DOT_96#
18 37 R_CLKREQ#_C R162 1 2 475_0402_1%
2

VSS_PCI CLKREQ_3# CLKREQ#_C 22

SRC_0/DOT_96

VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A

VDD_PLL3

VSS_PLL3
CLKREQ#_9 1 R191 2 10K_0402_5%

VSS_SRC
+VCCP

VDD_48

SRC_2#

SRC_3#
VDD_IO
VSS_48
@

VSS_IO

SRC_2

SRC_3
Change 33M and 48M damping to 39M by EMI request
1

@
R163 SLG8SP553VTR_QFN72_10x10

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1K_0402_5% R169 1 2 33_0402_1% +3VS_CK505
27 CLK_SD_48M
B R164 R_PCIE_SATA# R166 0_0402_5% B
1 2
2

CLK_PCIE_SATA# 21
FSC 1 2 1 2 R167 1 2 39_0402_1% FSA R_PCIE_SATA R168 1 2 0_0402_5% SATA
MCH_CLKSEL2 9 22 CLK_48M_ICH CLK_PCIE_SATA 21
10K_0402_5% R165
R171 1K_0402_5% R_CLK_48M_CRUSB R_PCIE_ICH# R170 1 2 0_0402_5%
T82 CLK_PCIE_ICH# 22
1 2 +1.05VS_CK505 R_PCIE_ICH R172 1 2 0_0402_5% ICH
7 CPU_BSEL2 CLK_PCIE_ICH 22
0_0402_5% +1.05VS_CK505
1

R173 1 2 0_0402_5% R_MCH_DREFCLK

9 CLK_MCH_DREFCLK R_MCH_DREFCLK# SSCDREFCLK#
@ R175 1 2 0_0402_5% R176 1 2 0_0402_5%
9 CLK_MCH_DREFCLK# SSCDREFCLK MCH_SSCDREFCLK# 9
R174 R177 1 2 0_0402_5% NB_SSC (UMA)
MCH_SSCDREFCLK 9
0_0402_5%
2

NB (UMA)
+3VS
add 48MHZ for cardreader 09/22
+3VS
0 = SRC8/SRC8#
ITP_EN +3VS
02/13 Add 12P on CLK_14M_ICH for WWAN noise
1 = ITP/ITP# R178 R179
0 = Enable DOT96 & SRC1(UMA) 2.2K_0402_5% 2.2K_0402_5%
PCI_CLK3 @ C215 CLK_48M_ICH
1 = Enable SRC0 & 27MHz(DIS) 2 1
2

Q3A 5P_0402_50V8C
C216 2 1 CLK_14M_ICH
22,26 ICH_SMBDATA 6 1 CLK_SMBDATA 12P_0402_50V8J
+3VS +3VS CLK_SMBDATA 15,16
@ C217 2 1 CLK_PCI_ICH
5

SB, MINI PCI Q3B 2N7002DW-7-F_SOT363-6 4.7P_0402_50V8C

@ C218 2 1 CLK_PCI_EC
1

@ 3 4 CLK_SMBCLK 4.7P_0402_50V8C
22,26 ICH_SMBCLK CLK_SMBCLK 15,16
R180 R181
10K_0402_5% 10K_0402_5% 2N7002DW-7-F_SOT363-6
A A
2

ITP_EN PCI_CLK3
1

@
R182 R183
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
Clock Generator CK505
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 17 of 46
5 4 3 2 1
 A B C D E

BLUE
GREEN
RED
Place close to
@ D5 @ D6 @ D7
JCRT1

1
1 +5VS +RCRT_VCC +CRTVDD 1

DAN217T146_SC59-3

DAN217T146_SC59-3

DAN217T146_SC59-3
D4 F1
2 1 1 2 W=40mils
CRT Connector RB491D_SC59-3 1.1A_6VDC_FUSE
1

3
+CRTVDD
0.1U_0402_16V4Z
C220 2
JCRT1
6
11
RED 1
7
12
GREEN 2
8
13
BLUE 3
9
14
4
+5VS +5VS 10
15
C221 C222 5
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2 16 GND
17 GND
+3VS
+CRTVDD +CRTVDD +3VS
5
1

U4 SUYIN_070546FR015S265ZR
SN74AHCT1G125GW_SOT353-5 R184 CONN@
OE#
P

1
1
2 CRT_HSYNC HSYNC_G_A D_HSYNC 2
11 CRT_HSYNC 2 A Y 4 1 2 0_0603_5%
R185 R186 R187 R188
G

5
1

2.2K_0402_5% 2.2K_0402_5%

2
R189 2.2K_0402_5% 2.2K_0402_5%
OE#
P
3

CRT_VSYNC 2 4 VSYNC_G_A 1 2 0_0603_5% D_VSYNC

2
2
11 CRT_VSYNC A Y D_DDCDATA 3VDDCDA
6 1 3VDDCDA 11
G

U5 1 1
SN74AHCT1G125GW_SOT353-5 C223 C224
3

Q5A

5
5P_0402_50V8C 5P_0402_50V8C 2N7002DW-7-F_SOT363-6
2 2 D_DDCCLK 3 4 3VDDCCL
3VDDCCL 11

Q5B
2N7002DW-7-F_SOT363-6

CRT Termination/EMI Filter 11/07 Change CRT lounting NB-->Docking-->CRT connector

3 3

L2
M_RED 1 2 RED
11 M_RED
NBQ100505T-800Y-N_2P
L3
M_GREEN 1 2 GREEN
11 M_GREEN
NBQ100505T-800Y-N_2P
L4
M_BLUE 1 2 BLUE
11 M_BLUE
NBQ100505T-800Y-N_2P
2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
1

1
150_0402_1%

150_0402_1%

150_0402_1%

1 1 1 1 1 1
R195

R196

R197
2

2 2 2 2 2 2

C225 C226 C227 C228 C229 C230

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 18 of 46
A B C D E
 5 4 3 2 1

+3VS +LCDVDD INVPWR_B+

C235 C236 C237

D
LVDS CONN & USB Camera + Dig Mic D
680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
1 02/20 Change to 0805 size
1

1
+LCDVDD +3VS
+LCDVDD +LCDVDD +5VALW Q7
AO3413_SOT23-3
2

2
2

1
JLVDS1 1 3

4.7U_0805_10V4Z
1 1 2 2 1
3 4 LVDS_A2- 1 1 R198 R199
3 4 LVDS_A2+ LVDS_A2- 11
5 6 C231 C232 470_0805_5% 1M_0402_5% C233 1

G
2
5 6 LVDS_A2+ 11
7 8 @ 4.7U_0805_10V4Z

6 2

2
7 8 LVDS_A1- 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C234
9 9 10 10 LVDS_A1- 11
11 12 LVDS_A1+ 2 2
USB20_P4 11 12 LVDS_A1+ 11 2
22 USB20_P4 13 14
USB20_N4 13 14 LVDS_A0- R200
22 USB20_N4 15 16 LVDS_A0- 11
15 16 LVDS_A0+
17 17 18 18 LVDS_A0+ 11 2 2 1
19 20
19 20 LVDS_ACLK- 2N7002DW-7-F_SOT363-6 100K_0402_5%
21 22

1
DMIC_DAT 21 22 LVDS_ACLK+ LVDS_ACLK- 11
23 24 Q8A C238
28 DMIC_DAT 23 24 LVDS_ACLK+ 11
DMIC_CLK 25 26
28 DMIC_CLK 25 26 0.047U_0402_16V7K
27 28 +3VS
INV_PWM_R 27 28
29 29 30 30

3
BKOFF# 31 32 Limited Current < 1A 01/03 Change to 0.047u to meet T1 timing
31 BKOFF# 31 32
33
33 34
34 delete DAC_BRIG
+5VS 35 36 10/26 Q8B
DDC2_CLK 35 36 2N7002DW-7-F_SOT363-6
11 DDC2_CLK 37 38 11 ENAVDD 5
DDC2_DATA 37 38
39 40
39 40

1
11 DDC2_DATA 41 42

4
GND1GND2 R201
ACES_87142-4041-BS 100K_0402_5%
C BKOFF# C

2
1
C71 @

2
C434
delete Pin28 LOG PWR.10/26 R245 1

10K_0402_5%

470P_0402_50V7K~D
680P_0402_50V7K @ 0_0402_5% Avoid Panel display garbage after power on.
2 1 R596 2
INV_PWM_GL40 11
INV_PWM_R 1 2 INV_PWM 31 2
0_0402_5% R594

1
0308_Install all cap for EMI request.

B+ INVPWR_B+
Must close JLVDS1pin @
+3VS L5 1 2 0_0805_5%
、 26
24、
DMIC_CLK
L6 1 2
DMIC_DAT FBMA-L11-201209-221LMA30T_0805
2

R202 R203 1 1 0308_Reserve L10 and install L11.

DDC2_CLK @ C1401 1 2 100P_0402_50V8J 2.2K_0402_5% 2.2K_0402_5% C302 C303
DDC2_DATA @ C1402 1 2 100P_0402_50V8J
220P_0402_25V8J 220P_0402_25V8J
1

DDC2_CLK 2 2
DDC2_DATA
0831 EMI request
11/09 EMI reserver
B B

delete +5VS transfer to +USB_CAM.10/26

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 19 of 46
5 4 3 2 1
 5 4 3 2 1

+3VS

R272 1 2 8.2K_0402_5% PCI_DEVSEL#

R273 1 2 8.2K_0402_5% PCI_STOP#

R274 1 2 8.2K_0402_5% PCI_TRDY#

R275 1 2 8.2K_0402_5% PCI_FRAME# U12B

D11 F1 PCI_REQ0#
R276 1 PCI_PLOCK# AD0 REQ0# PCI_GNT0#
2 8.2K_0402_5% C8 AD1 GNT0# G4
D PCI_REQ1# D
R277 1 2 8.2K_0402_5% PCI_IRDY#
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7
AD3 GNT1#/GPIO51 PCI_REQ2#
E9 AD4 REQ2#/GPIO52 F13
R278 1 2 8.2K_0402_5% PCI_SERR# C9 F12
AD5 GNT2#/GPIO53 PCI_REQ3#
E10 E6
R279 1 PCI_PERR# AD6 REQ3#/GPIO54 PCI_GNT3#
2 8.2K_0402_5% B7 AD7 GNT3#/GPIO55 F6
C7
AD8
C5 AD9 C/BE0# D8
G11 AD10 C/BE1# B4 Place closely pin
F8 D6
AD11 C/BE2# D4
F11 AD12 C/BE3# A5
E7 CLK_PCI_ICH
AD13 PCI_IRDY#
A3 AD14 IRDY# D3

1
+3VS D2 E3 @
AD15 PAR PCI_RST# R280
F10 R1 PCI_RST# 31
AD16 PCIRST# PCI_DEVSEL# 10_0402_5%
D5 C6
R281 1 PCI_PIRQA# AD17 DEVSEL# PCI_PERR#
2 8.2K_0402_5% D10 AD18 PERR# E4
B3 C2 PCI_PLOCK#

2
R282 1 PCI_PIRQB# AD19 PLOCK# PCI_SERR#
2 8.2K_0402_5% F7 AD20 SERR# J4 PCI_SERR# 31
C3 A4 PCI_STOP# 1
R283 1 PCI_PIRQC# AD21 STOP# PCI_TRDY#
2 8.2K_0402_5% F3 F5 @
AD22 TRDY# PCI_FRAME# C425
F4 D7
R284 1 PCI_PIRQD# AD23 FRAME#
2 8.2K_0402_5% C1 AD24
8.2P_0402_50V
PLT_RST# 2
G7 AD25 PLTRST# C14 PLT_RST# 9,25,26
R285 1 2 8.2K_0402_5% PCI_PIRQE# H7 D4 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH 17
D1 R2 PCI_PME#
PCI_PIRQF# AD27 PME# PCI_PME# 31
R286 1 2 8.2K_0402_5% G5
AD28
H6
AD29 3/28 PCI_PME# Remvoe 8.2k pull high +3VALW
R287 1 2 8.2K_0402_5% PCI_PIRQG# G1
H3
AD30 resistance.
R288 2 PCI_PIRQH# AD31
1 8.2K_0402_5%
C C
PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE#
R289 1 PCI_REQ0# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF#
2 8.2K_0402_5% E1 K6
PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
J6 PIRQC# PIRQG#/GPIO4 F2
R290 1 2 8.2K_0402_5% PCI_REQ1# PCI_PIRQD# C4 G2 PCI_PIRQH#
PIRQD# PIRQH#/GPIO5
R292 1 2 8.2K_0402_5% PCI_REQ2# ICH9-M ES_FCBGA676

R293 1 2 8.2K_0402_5% PCI_REQ3# Delete GS function

A16 swap override Strap

B
Boot BIOS Strap B
Low= A16 swap override Enble
PCI_GNT3# High= * PCI_GNT0# SPI_CS#1 Boot BIOS
Default Location
@ R294
@R294 0 1 SPI
PCI_GNT3# 1 2
1K_0402_5%
1 0 PCI

1 1 LPC *

+3VALW

@ R295
SPI_CS1#_R 1 2
22 SPI_CS1#_R
1K_0402_5%
@ R296
PCI_GNT0# 1 2
1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 20 of 46
5 4 3 2 1
 5 4 3 2 1

： follow check list ver:1.5 change to 8.2K ohm

PV：
ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05,
+RTCVCC
VccSus1.5, VccCL1.5) +3VS

SM_INTRUDER#
ICH_INTVRMEN Low = Internal VR Disabled R298
1 2
R297 1M_0402_5% High = Internal VR Enabled(Default) GATEA20 1 2
1 2 LAN100_SLP 8.2K_0402_5%
R299 330K_0402_5%
1 2 ICH_INTVRMEN ICH8M LAN100 SLP Strap R301
R300 330K_0402_5% KB_RST# 1 2
1 2 ICH_SRTCRST# (Internal VR for VccLAN1.05 and VccCL1.05) 10K_0402_5%
R302 180K_0402_5%

1
0_0402_5%

0_0402_5%
D D
1
C426 @ @ ICH_LAN100_SLP Low = Internal VR Disabled +VCCP
R303 R304
0.1U_0402_16V4Z High = Internal VR Enabled(Default) @ R305
2 H_DPRSTP# 1 2

2
56_0402_5%
LPC_AD[0..3] 26,31
U12A @ R306
ICH_RTCX1 C23 K5 LPC_AD0 H_DPSLP# 1 2
ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
C24 K4
R307 RTCX2 FWH1/LAD1 LPC_AD2
FWH2/LAD2 L6
1 2 ICH_RTCRST# A25 K2 LPC_AD3
+RTCVCC RTCRST# FWH3/LAD3
20K_0402_5% ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST# LPC_FRAME#
C22 K3 LPC_FRAME# 26,31
INTRUDER# FWH4/LFRAME# +VCCP

RTC
1

LPC
1
C427 CLRP2 ICH_INTVRMEN B22 J3
SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
A22 LAN100_SLP LDRQ1#/GPIO23 J1
1U_0603_10V4Z T54 PAD

2
2 GATEA20
E25 GLAN_CLK A20GATE N7 GATEA20 31
AJ27 H_A20M# R308
A20M# H_A20M# 6
C13 56_0402_5%
LAN_RSTSYNC H_DPRSTP_R# R309 H_DPRSTP#
AJ25 1 2 H_DPRSTP# 7,9,41
DPRSTP# H_DPSLP# 0_0402_5%
F14 AE23

1
LAN_RXD0 DPSLP# H_DPSLP# 7
G13 LAN_RXD1
12P_0402_50V8J D14 AJ26 R_H_FERR# R310 1 2 H_FERR#
LAN_RXD2 FERR# H_FERR# 6

LAN / GLAN
C331 1 2 HDA_BITCLK 56_0402_5%
D13 AD22 H_PWRGOOD 3/28 add 56ohm
+1.5VS LAN_TXD_0 CPUPWRGD H_PWRGOOD 7
D12
R311 LAN_TXD_1 H_IGNNE#
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# 6
24.9_0402_1% within 2" from R379
1 2 GLAN_COMP B10 AE22 H_INIT#
GPIO56 INIT# H_INTR H_INIT# 6 +VCCP
R312 33_0402_5% 1 2 AG25

CPU
C 28 HDA_BITCLK_CODEC INTR KB_RST# H_INTR 6 C
B28 GLAN_COMPI RCIN# L3 KB_RST# 31
B27
GLAN_COMPO

1
R316 33_0402_5% 1 2 AF23 H_NMI
28 HDA_SYNC_CODEC NMI H_NMI 6
HDA_BITCLK AF6 AF24 H_SMI# R315
HDA_SYNC HDA_BIT_CLK SMI# H_SMI# 6
AH4 56_0402_5%
R317 33_0402_5% HDA_SYNC H_STPCLK#
28 HDA_RST#_CODEC 1 2 AH27 H_STPCLK# 6
HDARST# STPCLK#
AE7

2
HDA_RST# THRMTRIP_ICH# R319
AG26 1 2 54.9_0402_1% H_THERMTRIP# 6,9
HDA_SDIN0 THRMTRIP#
28 HDA_SDIN0 AF4 HDA_SDIN0
AG4
HDA_SDIN1 TP12
AG27 placed within 2"
AH3 HDA_SDIN2 from ICH9M
delete MDC and HDMI on AE5

IHDA
HDA_SDIN3
SATA4RXN AH11 SATA_DTX_C_IRX_N4 24
09/17 28 HDA_SDOUT_CODEC R321 33_0402_5% 1 2 HDA_SDOUT AG5 AJ11 SATA_DTX_C_IRX_P4 24 ODD
HDA_SDOUT SATA4RXP
AG12 SATA_ITX_DRX_N4 C790 1 2 0.01U_0402_16V7K SATA_ITX_RPI_DRX_N4 24
SATA4TXN
R313 PAD T55 AG7 AF12 SATA_ITX_DRX_P4 C816 1 2 0.01U_0402_16V7K SATA_ITX_RPI_DRX_P4 24
HDA_DOCK_EN#/GPIO33 SATA4TXP
+3VS 1 2 PAD T56 AE8
10K_0402_5% HDA_DOCK_RST#/GPIO34
SATA_LED# AG8
32 SATA_LED# SATALED#
add pull high to +3VS 09/22 SATA5RXN AH9
24 SATA_RXN0_C AJ16 AJ9
0.01U_0402_16V7K SATA0RXN SATA5RXP
24 SATA_RXP0_C AH16 AE10
SATA_TXN0 C431 SATA_TXN0_C SATA0RXP SATA5TXN
1 2 AF17 AF10
P- HDD 24 SATA_TXN0
SATA_TXP0 C433 1 2 SATA_TXP0_C AG17
SATA0TXN SATA5TXP
24 SATA_TXP0 SATA0TXP CLK_PCIE_SATA#
AH18 CLK_PCIE_SATA# 17
SATA_CLKN

SATA
0.01U_0402_16V7K AH13 AJ18 CLK_PCIE_SATA
SATA1RXN SATA_CLKP CLK_PCIE_SATA 17
AJ13 SATA1RXP SATARBIAS# AJ7
AG14 AH7 R322 1 2
SATA1TXN SATARBIAS 24.9_0402_1%
AF14
SATA1TXP
Within 500 mils
ICH9-M ES_FCBGA676
B B

Add 12p on HDA_SDOUT and HDA_SDOUT

02/13 Reserve cap on HDA_BITCLK for WWAN
noise issue

HDA_BITCLK_CODEC C67 1 2 33P_0402_50V8K

HDA_SDOUT_CODEC @ C312 1 2 12P_0402_50V8J

Change BATT1 P/N : SP093PA0200 (Panasonic)

RTC Battery SP093MX0000 (MAXELL)
XOR CHAIN ENTRANCE STRAP:RSVD
+3VS
Modify as NBLB2. 11/02
D12
+RTC_BATT
@ R325
1 2 HDA_SDOUT_CODEC
- BATT1 + R250 R249
560_0603_5% 560_0603_5%
2 +CHGRTC
1K_0402_5% 2 1 1 2 1 2 1
@ R326
1 2 ICH_RSVD 3 +RTCVCC
ICH_RSVD 22
1K_0402_5% ICH_RTCX1
ML1220T13RE

1
R328 @ BAS40-04_SOT23
1 2 ICH_RTCX2 C193
0.1U_0402_16V4Z

2
10M_0402_5%
A A
ICH_RSVD HDA_SDOUT_CODEC C436
1 1
C437

15P_0402_50V8J 15P_0402_50V8J
2 2
0 0
0 1 Y2 Security Classification Compal Secret Data Compal Electronics, Inc.
1 4 Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
1 0 2 3 ICH9(2/4)_LAN,HD,IDE,LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
32.768KHZ_12.5P_MC-146 Custom Montevina UMA LA6121P 0.2
1 1 0821 Change C436 and C437 to 15PF
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 21 of 46
5 4 3 2 1
 5 4 3 2 1

04/29 MV-1 add R337 clock REQ pull high

+3VALW R331 1 2 2.2K_0402_5% Place closely Place closely
+3VS R332 1 2 2.2K_0402_5%
U12C pin AF3 pin H1
ICH_SMBCLK G16 AH23 GPIO21 Modify back to GPIO19 on 09/22 CLK_48M_ICH CLK_14M_ICH
SIRQ 17,26 ICH_SMBCLK ICH_SMBDATA SMBCLK SATA0GP/GPIO21 GPIO19
R333
1 2
10K_0402_5%
17,26 ICH_SMBDATA LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19
AF19
AE21 GPIO36

SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

1
1 2 PM_CLKRUN# ME_EC_CLK1 C17 AD20 GPIO37
R334 @ 8.2K_0402_5% ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37 @ R342 @ R343
B18 SMLINK1
1 2 OCP# H1 CLK_14M_ICH
+3VS ICH_RI# CLK14 CLK_48M_ICH CLK_14M_ICH 17
R335 10K_0402_5% 10_0402_5% 10_0402_5%
1 2 THERM_SCI#
F19
RI# clocks CLK48
AF3 CLK_48M_ICH 17

2
@R336
@ R336 8.2K_0402_5% PAD T57 SUS_STAT# R4 P1 ICH_SUSCLK
CLKREQ#_C XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK ICH_SUSCLK 31
1 2 6 XDP_DBRESET# G19 SYS_RESET# 1 1

1
R337 10K_0402_5% C16 SLP_S3# @ C440 @ C441
D SLP_S3# SLP_S3# 31 D
1 2 PM_BMBUSY# @R339
@ R339 @ R340 PM_BMBUSY# M6 E16 SLP_S4#
9 PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S5# SLP_S4# 31,33
@R338
@ R338 8.2K_0402_5% 10K_0402_5% 10K_0402_5% G17 4.7P_0402_50V8C 4.7P_0402_50V8C
SLP_S5# 31

SYS / GPIO
EC_SCI# EC_LID_OUT# SLP_S5# 2 2
1 2 31 EC_LID_OUT# A17 SMBALERT#/GPIO11
R341 8.2K_0402_5% C10 S4_STATE#

2
GPIO6 H_STP_PCI# S4_STATE#/GPIO26
1 2 17 H_STP_PCI# A14
R344 8.2K_0402_5% R345 R_STP_CPU# STP_PCI# PM_PWROK
17 H_STP_CPU# 1 2 0_0402_5% E19 STP_CPU# PWROK G20 PM_PWROK 9,31
R346 10K_0402_5%
1 2 GPIO22 1 2
R356 8.2K_0402_5% 1 R347 2 PM_CLKRUN# L4 M2 R348 1 2 0_0402_5% DPRSLPVR 9,41

Power MGT
GPIO18 10K_0402_5% CLKRUN# DPRSLPVR/GPIO16
1 2
R349 8.2K_0402_5% ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
GPIO19 25,26 ICH_PCIE_WAKE# SIRQ WAKE# BATLOW#
1 2 31 SIRQ M5 SERIRQ
R350 8.2K_0402_5% THERM_SCI# AJ23 R3 PWRBTN_OUT# 11/17 Add +3VALW GD to
GPIO20 31 THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# 31
1 2
R351 8.2K_0402_5%
17,41 VGATE
VGATE D21 D20 R_EC_RSMRST# 37
EC_RSMRST# to fix Battery mode
GPIO21 VRMPWRGD LAN_RST#
1 2 can't boot issue
R352 8.2K_0402_5% R353 1 2 PAD T59 A20 D22 R_EC_RSMRST# R354 1 2 100_0402_5%
GPIO36 TP11 RSMRST# EC_RSMRST# 31
1 2 100K_0402_5% R355 1 2 10K_0402_5%
R357 8.2K_0402_5% OCP# AG19 R5 CK_PWRGD
6 OCP# GPIO1 CK_PWRGD CK_PWRGD 17
1 2 GPIO37 Delete GPIO6 function for cardreader on 09/18 GPIO6 AH21
R358 8.2K_0402_5% R225 EC_SCI#_SB GPIO6 M_PWROK
31 EC_SCI# 1 2 0_0402_5% AG21 R6 M_PWROK 9,31
GPIO39 EC_SMI# GPIO7 CLPWROK
1 2 31 EC_SMI# A21
R359 10K_0402_5% @ R226 EC_SCI#_GPIO12 GPIO8 +3VS
1 2 0_0402_5% C12 B16
GPIO48 GPIO12 SLP_M#
1 2 PAD T62 C21 GPIO13
@R361
@ R361 8.2K_0402_5% 17/14 AE18 F24 CL_CLK0 R360
GPIO57 GPIO18 GPIO17 CL_CLK0 CL_CLK0 9
1 2 K1 B19 1 2

GPIO
GPIO18 CL_CLK1

Controller Link

0.1U_0402_16V4Z
R362 8.2K_0402_5% GPIO20 AF8 GPIO20

1
GPIO22 AJ22 F22 CL_DATA0 3.24K_0402_1%
Delete GPIO6 function for cardreader on 09/18 DIS/UMA SCLOCK/GPIO22 CL_DATA0 CL_DATA0 9
A9 C19 1
GPIO27 CL_DATA1 C442 R363
PAD T47 D19 GPIO28
CLKREQ#_C L1 C25 CL_VREF0_ICH 453_0402_1%
17 CLKREQ#_C GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL_VREF1_ICH
+3VS 1 2 AE19 A19

2
GPIO49 R364 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1 2 NA lead free
1 2 AG22
C @R365
@ R365 10K_0402_5% GPIO48 SDATAOUT0/GPIO39 CL_RST# +3VALW C
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST# 9
delete New card function for GPIO48 on 09/17 GPIO49 AH24 D18
GPIO57 GPIO49 CL_RST1# R367
A8
GPIO57/CLGPIO5 Change XMIT_OFF to EC contral.01/11
+3VS @ R366 1 2 1K_0402_5% MEM_LED/GPIO24 A16 T63 PAD 1 2
SB_SPKR GPIO10

0.1U_0402_16V4Z
28 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18
MCH_ICH_SYNC# AJ24 C11 GPIO14 3.24K_0402_1%

MISC
9 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT

1
+3VALW ICH_RSVD B21 C20 LAN_WOL_EN
21 ICH_RSVD TP3 WOL_EN/GPIO9 1
AH20 C443 R368
TP8 R370 453_0402_1%
AJ20 TP9
1 2 LINKALERT# R366 05/08 MV-1 Delete R739 AJ21 2 1
TP10 +3VALW 2
R369 10K_0402_5% Low

2
1 2 ICH_LOW_BAT# High -->No ICH9-M ES_FCBGA676 100K_0402_5%
R371 8.2K_0402_5% -->default
1 2 ICH_PCIE_WAKE# boot U12D
R372 1K_0402_5% N29 V27 DMI_RXN0
PERN1 DMI0RXN DMI_RXN0 9
ICH_RI# DMI_RXP0
R374
1 2
10K_0402_5% delete TV on 09/17 N28
P27
PERP1
PETN1
DMI0RXP
DMI0TXN
V26
U29 DMI_TXN0
DMI_RXP0
DMI_TXN0 9
9
1 2 XDP_DBRESET# P26 U28 DMI_TXP0 D22

Direct Media Interface

PETP1 DMI0TXP DMI_TXP0 9
R375 10K_0402_5% PM_PWROK 2 1 R_EC_RSMRST#
1 2 S4_STATE# L29 Y27 DMI_RXN1
PERN2 DMI1RXN DMI_RXN1 9
R376 10K_0402_5% L28 Y26 DMI_RXP1 CH751H-40PT_SOD323-2
PERP2 DMI1RXP DMI_RXP1 9
1 2 ME_EC_CLK1 11/17 Swap PCIE LAN and New card M27 W29 DMI_TXN1
PETN2 DMI1TXN DMI_TXN1 9
R377 10K_0402_5% M26 W28 DMI_TXP1 DMI_TXP1 9 #PV PWROK sequence issue
ME_EC_DATA1 PETP2 DMI1TXP
1 2

PCI - Express
R378 10K_0402_5% PCIE_RXN3 J29 AB27 DMI_RXN2
26 PCIE_RXN3 PERN3 DMI2RXN DMI_RXN2 9
1 2 GPIO10 PCIE_RXP3 J28 AB26 DMI_RXP2
26 PCIE_RXP3 PERP3 DMI2RXP DMI_RXP2 9
R379 10K_0402_5% WLAN 26 PCIE_TXN3 C448 1 2 0.1U_0402_16V4Z PCIE_C_TXN3 K27 PETN3 DMI2TXN AA29 DMI_TXN2
DMI_TXN2 9
1 2 EC_LID_OUT# C449 1 2 0.1U_0402_16V4Z PCIE_C_TXP3 K26 AA28 DMI_TXP2
26 PCIE_TXP3 PETP3 DMI2TXP DMI_TXP2 9
R373 10K_0402_5%
1 2 EC_SMI# GLAN_RXN G29 AD27 DMI_RXN3
25 GLAN_RXN PERN4 DMI3RXN DMI_RXN3 9
R380 8.2K_0402_5% GLAN_RXP G28 AD26 DMI_RXP3
25 GLAN_RXP PERP4 DMI3RXP DMI_RXP3 9
1 2 GPIO14 LAN C452 1 2 0.1U_0402_16V4Z GLAN_TXN_C H27 AC29 DMI_TXN3
B 25 GLAN_TXN PETN4 DMI3TXN DMI_TXN3 9 B
R381 8.2K_0402_5% C453 1 2 0.1U_0402_16V4Z GLAN_TXP_C H26 AC28 DMI_TXP3 DMI_TXP3 9
25 GLAN_TXP PETP4 DMI3TXP
E29 T26 CLK_PCIE_ICH#
PERN5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# 17
E28 PERP5 DMI_CLKP T25 CLK_PCIE_ICH 17
+3VS +3VS
Board ID F27
PETN5
F26 AF29 R382 24.9_0402_1% Within 500 mils
PETP5 DMI_ZCOMP DMI_IRCOMP
AF28 1 2 +1.5VS
DMI_IRCOMP
2

C29
PERN6/GLAN_RXN USB20_N0
@ R745
@R745 @ R747 delete New Card on 09/17 C28
D27
PERP6/GLAN_RXP
PETN6/GLAN_TXN
USBP0N
USBP0P
AC5
AC4 USB20_P0
USB20_N0
USB20_P0
29
29 USB-0 Daughter board
10K_0402_5% 10K_0402_5% D26 AD3 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 29
AD2 USB20_P1 USB-1 Daughter board
1

DIS/UMA 17/14 USBP1P USB20_N2 USB20_P1 29

PAD T64 D23 SPI_CLK USBP2N AC1 USB20_N2 29
Delete HDCP ROM.11/09 PAD T72 D24 AC2 USB20_P2
SPI_CS0# USBP2P USB20_P2 29
2

SPI_CS1#_R
20 SPI_CS1#_R F23 SPI_CS1#GPIO58/CLGPIO6 USBP3N
USBP3P
AA5
AA4
USB-2 On Mather board
R746 R748 USB20_N4
10K_0402_5% 10K_0402_5%
PAD T73 D25
SPI_MOSI SPI USBP4N
AB2
USB20_P4 USB20_N4 19
PAD T74 E23
SPI_MISO USBP4P
AB3
USB20_N5 USB20_P4 19 USB-4 Camera
AA1
1

USB_OC#0 USBP5N USB20_P5 USB20_N5 26

29 USB_OC#0
USB_OC#1
N4
OC0#/GPIO59 USBP5P
AA2
USB20_N6
USB20_P5 26 USB-5 WLAN
N5 W5 USB20_N6 29
USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6
RP27
29 USB_OC#2 WXMIT_OFF#
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3 USB20_N7 USB20_P6 29 USB-6 Bluetooth
USB_OC#5 USB_OC#4 OC3#/GPIO42 USBP7N USB20_P7 USB20_N7 27
USB_OC#1
4 5 +3VALW USB_OC#5
M1 OC4#/GPIO43 USBP7P Y2 USB20_P7 USB-6
27 Cardreader
3 6 N2 W1
USB_OC#2 USB_OC#6 OC5#/GPIO29 USBP8N
2 7 M4 W2
USB_OC#4 USB_OC#7 OC6#/GPIO30 USBP8P
1 8
USB_OC#8
M3
N3
OC7#/GPIO31
OC8#/GPIO44
USBP9N
USBP9P
V2
V3
modify cardreader from PCIE to USB on 0918
10K_1206_8P4R_5% USB_OC#9 N1 U5
OC9#/GPIO45 USBP10N
Delete WXMIT_OFF# for WWAN. 1104 USB_OC#10 P5
OC10#/GPIO46 USBP10P
U4
RP28 USB_OC#11 P3 U1
USB_OC#11 OC11#/GPIO47 USBP11N
4 5 USBP11P U2
A USB_OC#8 USBRBIAS A
3 6 AG2
USB_OC#7 USBRBIAS
2 7 AG1 USBRBIAS#
1

USB_OC#9 1 8 Within 500 mils

ICH9-M ES_FCBGA676
10K_1206_8P4R_5% R384
22.6_0402_1%
RP29
2

WXMIT_OFF# 4 5
USB_OC#0
USB_OC#10
3 6
Security Classification Compal Secret Data Compal Electronics, Inc.
2 7 Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
USB_OC#6 1 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(3/4)_DMI,USB,GPIO,PCIE

www.vinafix.vn
10K_1206_8P4R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 22 of 46
5 4 3 2 1
 5 4 3 2 1

+RTCVCC +VCCP U12E

U12F AA26 H5
VSS[001] VSS[107]
20 mils A23 G3: 6uA A15 AA27 J23
VCCRTC VCC1_05[01] VSS[002] VSS[108]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1634mA B15 AA3 J26
ICH_V5REF_RUN VCC1_05[02] VSS[003] VSS[109]
1 1 A6 2mA C15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
V5REF VCC1_05[03] VSS[004] VSS[110]

C462

C454
D15 1 1 AB1 AC22
VCC1_05[04] C457 C455 VSS[005] VSS[111]
E15 AA23 K28
ICH_V5REF_SUS 2mA VCC1_05[05] VSS[006] VSS[112]
AE1 F15 AB28 K29
2 2 V5REF_SUS VCC1_05[06] VSS[007] VSS[113]
VCC1_05[07] L11 AB29 VSS[008] VSS[114] L13
646mA 2 2
AA24 VCC1_5_B[01] VCC1_05[08] L12 AB4 VSS[009] VSS[115] L15
AA25 L14 AB5 L2
VCC1_5_B[02] VCC1_05[09] VSS[010] VSS[116]
AB24 L16 AC17 L26
VCC1_5_B[03] VCC1_05[10] VSS[011] VSS[117]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AC26 VSS[012] VSS[118] L27
R387 AC24 L18 AC27 L5
10U_0805_10V4Z VCC1_5_B[05] VCC1_05[12] R385 VSS[013] VSS[119]
+1.5VS 1 2 40 mils AC25 VCC1_5_B[06] VCC1_05[13] M11 AC3 VSS[014] VSS[120] L7
D CHB1608U301_0603 0.01U_0402_16V7K D
1 AD24 VCC1_5_B[07] VCC1_05[14] M18 1 2 +1.5VS AD1 VSS[015] VSS[121] M12
AD25 P11 CHB1608U301_0603 AD10 M13

CORE
1 1 1 VCC1_5_B[08] VCC1_05[15] VSS[016] VSS[122]
+

220U_6.3V
C459 C460 C456 AE25 P18 1 1 AD12 M14
VCC1_5_B[09] VCC1_05[16] VSS[017] VSS[123]

C458
AE26 T11 C461 C463 AD13 M15
VCC1_5_B[10] VCC1_05[17] VSS[018] VSS[124]
AE27 T18 AD14 M16
2 2 2 2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[019] VSS[125]
AE28 VCC1_5_B[12] VCC1_05[19] U11 AD17 VSS[020] VSS[126] M17
AE29 U18 2 2 AD18 M23
+5VS +3VS 10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[20] VSS[021] VSS[127]
F25 VCC1_5_B[14] VCC1_05[21] V11 AD21 VSS[022] VSS[128] M28
G25 VCC1_5_B[15] VCC1_05[22] V12 AD28 VSS[023] VSS[129] M29
H24 V14 AD29 N11
VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[130]
1

H25 VCC1_5_B[17] VCC1_05[24] V16 AD4 VSS[025] VSS[131] N12

R386 D9 J24 V17 +VCCP AD5 N13
VCC1_5_B[18] VCC1_05[25] VSS[026] VSS[132]

VCCA3GP

22U_0805_6.3VAM
J25 VCC1_5_B[19] VCC1_05[26] V18 AD6 VSS[027] VSS[133] N14
100_0402_5% CH751H-40_SC76 K24 1 AD7 N15
VCC1_5_B[20] C464 VSS[028] VSS[134]
K25 AD9 N16
2

VCC1_5_B[21] VSS[029] VSS[135]

L23 AE12 N17
ICH_V5REF_RUN VCC1_5_B[22] VSS[030] VSS[136]
L24 VCC1_5_B[23] VCCDMIPLL R29 AE13 VSS[031] VSS[137] N18
2
1 20 mils L25
VCC1_5_B[24]
AE14
VSS[032] VSS[138]
N26
C465 M24 W23 AE16 N27
VCC1_5_B[25]
M25 23mA VCC_DMI[1] Y23 +VCCP AE17
VSS[033] VSS[139]
P12
0.1U_0402_10V6K VCC1_5_B[26] VCC_DMI[2] VSS[034] VSS[140]
N23 AE2 P13
2 VCC1_5_B[27] VSS[035] VSS[141]
N24 AB23 AE20 P14
VCC1_5_B[28] 48mA V_CPU_IO[1] VSS[036] VSS[142]
N25 VCC1_5_B[29] V_CPU_IO[2] AC23 AE24 VSS[037] VSS[143] P15

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P24 VCC1_5_B[30] AE3 VSS[038] VSS[144] P16
P25 AG29 +3VS AE4 P17
VCC1_5_B[31] VCC3_3[01] 1 1 1 VSS[039] VSS[145]
+5VALW +3VALW

C466

C467

C468
R24 2mA AJ6 AE6 P2
VCC1_5_B[32] VCC3_3[02] VSS[040] VSS[146]
R25 AC10 AE9 P23
VCC1_5_B[33] VCC3_3[07] VSS[041] VSS[147]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R26 AF13 P28
VCC1_5_B[34] VSS[042] VSS[148]
1

2 2 2
R27 VCC1_5_B[35] VCC3_3[03] AD19 1 1 1 AF16 VSS[043] VSS[149] P29

VCCP_CORE
R388 D10 T24 AF20 AF18 P4
VCC1_5_B[36] VCC3_3[04] VSS[044] VSS[150]

C469

C470

C471
T27 AG24 AF22 P7
10_0402_5% CH751H-40_SC76 VCC1_5_B[37] VCC3_3[05] VSS[045] VSS[151]
T28 AC20 AH26 R11
C VCC1_5_B[38] VCC3_3[06] +3VS 2 2 2 (DMI) VSS[046] VSS[152] C
T29 AF26 R12
2

VCC1_5_B[39] VSS[047] VSS[153]

ICH_V5REF_SUS U24
VCC1_5_B[40]
308mA AF27
VSS[048] VSS[154]
R13
20 mils U25 B9 0.1U_0402_16V4Z AF5 R14
VCC1_5_B[41] VCC3_3[08] +1.5VS VSS[049] VSS[155]
1 V24 VCC1_5_B[42] VCC3_3[09] F9 1 AF7 VSS[050] VSS[156] R15
C472 V25 G3 C473 AF9 R16
VCC1_5_B[43] VCC3_3[10] VSS[051] VSS[157]
U23 G6 AG13 R17
VCC1_5_B[44] VCC3_3[11] VSS[052] VSS[158]

2
PCI
0.1U_0402_10V6K W24 J2 AG16 R18
2 VCC1_5_B[45] VCC3_3[12] 2 R212 @ VSS[053] VSS[159]
W25 J7 AG18 R28
VCC1_5_B[46] VCC3_3[13] VSS[054] VSS[160]
K23 VCC1_5_B[47] VCC3_3[14] K7 0_0402_5% AG20 VSS[055] VSS[161] T12
Y24 AG23 T13
VCC1_5_B[48] VSS[056] VSS[162]
Y25 AG3 T14

1
VCC1_5_B[49] VSS[057] VSS[163]
47mA 11mA AJ4 1 R742 2 0_0603_5% 0.1U_0402_16V4Z +3VS AG6 T15
VCCHDA VSS[058] VSS[164]
1 AG9 VSS[059] VSS[165] T16
R389 11mA AJ3 0.1U_0402_16V4Z 1 R740 2 0_0603_5% +3VALW C474 AH12 T17
VCCSUSHDA VSS[060] VSS[166]
+1.5VS 1 2 AJ19 1 AH14 T23
VCCSATAPLL VSS[061] VSS[167]

1
1U_0603_10V4Z

CHB1608U301_0603 C475 AH17 B26

2 VSS[062] VSS[168]
10U_0805_10V4Z

AC8 R741 AH19 U12

VCCSUS1_05[1] T65 VSS[063] VSS[169]
1 1 +1.5VS AC16 F17 150_0402_1% AH2 U13
VCC1_5_A[01] VCCSUS1_05[2] T66 2 VSS[064] VSS[170]
C476

C477

AD15 @ AH22 U14

0316 change design VCC1_5_A[02] VSS[065] VSS[171]
1 AD16 AH25 U15

2
VCC1_5_A[03] VSS[066] VSS[172]
C478 AE15 AD8 VCCSUS1_5_ICH_1 AH28 U16
2 2 VCC1_5_A[04] VCCSUS1_5[1] T67 VSS[067] VSS[173]
ARX

AF15 AH5 U17

1U_0603_10V4Z VCC1_5_A[05] VCCSUS1_5_ICH_2 VSS[068] VSS[174]
AG15 F18 AH8 AD23
2 VCC1_5_A[06] VCCSUS1_5[2] T68 +3VALW VSS[069] VSS[175]
AH15 AJ12 U26
VCC1_5_A[07] VSS[070] VSS[176]
AJ15 AJ14 U27
VCC1_5_A[08] 0.1U_0402_16V4Z VSS[071] VSS[177]
A18 AJ17 U3
VCCSUS3_3[01] VSS[072] VSS[178]

0.1U_0402_16V4Z
AC11 212mA D16 1 1 AJ8 V1
VCCPSUS

VCC1_5_A[09] VCCSUS3_3[02] VSS[073] VSS[179]

AD11 D17 B11 V13
VCC1_5_A[10] VCCSUS3_3[03] VSS[074] VSS[180]

C479

C480
AE11 E22 B14 V15
+1.5VS VCC1_5_A[11] VCCSUS3_3[04] VSS[075] VSS[181]
AF11 B17 V23
VCC1_5_A[12] 2 2 VSS[076] VSS[182]
ATX

1 AG10 B2 V28
C481 VCC1_5_A[13] VSS[077] VSS[183]
AG11 B20 V29
B VCC1_5_A[14] VSS[078] VSS[184] B
AH10 VCC1_5_A[15] B23 VSS[079] VSS[185] V4
1U_0603_10V4Z AJ10 AF1 B5 V5
2 VCC1_5_A[16] VCCSUS3_3[05] VSS[080] VSS[186]
B8 W26
VSS[081] VSS[187]
AC9 1342mA
VCC1_5_A[17] C26 VSS[082] VSS[188] W27
C27 W3
VSS[083] VSS[189]
AC18 E11 Y1
VCC1_5_A[18] VSS[084] VSS[190]
AC19 E14 Y28
VCC1_5_A[19] VSS[085] VSS[191]
T1 E18 Y29
VCCSUS3_3[06] VSS[086] VSS[192]
AC21 T2 E2 Y4
VCC1_5_A[20] VCCSUS3_3[07] VSS[087] VSS[193]
VCCSUS3_3[08] T3 E21 VSS[088] VSS[194] Y5
G10 T4 +3VALW E24 AG28
+1.5VS VCC1_5_A[21] VCCSUS3_3[09] VSS[089] VSS[195]
G9 T5 E5 AH6
VCC1_5_A[22]
11mA 11mA VCCSUS3_3[10] VSS[090] VSS[196]
1 VCCSUS3_3[11] T6 E8 VSS[091] VSS[197] AF2
C483 AC12 U6 F16 B25
VCCPUSB

+1.5VS VCC1_5_A[23] VCCSUS3_3[12] 1 VSS[092] VSS[198]

1 AC13 U7 C482 F28
0.1U_0402_16V4Z C484 VCC1_5_A[24] VCCSUS3_3[13] VSS[093]
AC14 V6 F29
2 VCC1_5_A[25] VCCSUS3_3[14] 4.7U_0603_6.3V6M VSS[094]
V7 G12
0.1U_0402_16V4Z VCCSUS3_3[15] 2 VSS[095]
AJ5 W6 G14 A1
2 VCCUSBPLL VCCSUS3_3[16] VSS[096] VSS_NCTF[01]
W7 G18 A2
VCCSUS3_3[17] VSS[097] VSS_NCTF[02]
USB CORE

AA7 Y6 G21 A28

VCC1_5_A[26] VCCSUS3_3[18] VSS[098] VSS_NCTF[03]
AB6 Y7 G24 A29
VCC1_5_A[27] VCCSUS3_3[19] VSS[099] VSS_NCTF[04]
AB7 VCC1_5_A[28] VCCSUS3_3[20] T7 G26 VSS[100] VSS_NCTF[05] AH1
AC6 G27 AH29
VCC1_5_A[29] VSS[101] VSS_NCTF[06]
AC7 VCC1_5_A[30] G8 VSS[102] VSS_NCTF[07] AJ1
H2 AJ2
T69 VCC_LAN1_05_INT_ICH_1 VSS[103] VSS_NCTF[08]
A10 H23 AJ28
T70 VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VCCCL1_05_ICH VSS[104] VSS_NCTF[09]
A11 VCCLAN1_05[2] VCCCL1_05 G22 H28 VSS[105] VSS_NCTF[10] AJ29
+3VS G23 T71 H29 B1
VCCCL1_5 VSS[106] VSS_NCTF[11]
A12 B29
VCCLAN3_3[1] VSS_NCTF[12]
B12 19/78/78mA 19/73/73mA
VCCLAN3_3[2]
0.1U_0402_16V4Z

1 23mA A24 +3VS 1 @

C485 R390 CHB1608U301_0603 VCCCL3_3[1] C486 ICH9-M ES_FCBGA676
VCCCL3_3[2] B24
GLAN POWER

A 1U_0603_10V4Z A
1 2 A27
R391 4.7U_0805_10V4Z VCCGLANPLL
80mA
2 +1.5VS 2
10U_0805_10V4Z

2.2U_0603_6.3V4Z

+1.5VS 1 2 D28 VCCGLAN1_5[1]

D29
CHB1608U301_0603 VCCGLAN1_5[2]
1 1 E26 VCCGLAN1_5[3]
C487 C488 1 E27
VCCGLAN1_5[4]
1mA
A26
2 2
0316 change design
C489
2
+3VS VCCGLAN3_3
ICH9-M ES_FCBGA676
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 23 of 46
5 4 3 2 1
 5 4 3 2 1

Pleace near HDD CONN (JP3)

HDD Connector +5VS

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1

C490
JP3 C491 C492 C493
1
GND SATA_TXP0
A+ 2 SATA_TXP0 21
3 SATA_TXN0 2 2 2 2
A- SATA_TXN0 21
4 0.01U_0402_16V7K
D GND SATA_RXN0 D
B- 5 2 1 C494 SATA_RXN0_C SATA_RXN0_C 21
6 SATA_RXP0 2 1 C495 SATA_RXP0_C
B+ SATA_RXP0_C 21
7 0.01U_0402_16V7K
GND
8
Near CONN side.
V33 +3VS_HDD1
V33 9
10
V33
GND 11 Pleace near HDD CONN
GND 12
13 +3VS_HDD1
GND +5VS @ R392
V5 14
15 +3VS 1 2
V5

1000P_0402_50V7K

1U_0603_10V4Z
0.1U_0402_16V4Z
16 0_0805_5%
V5
17 1 1 1
GND @ C496 @ C497 @ C498
18
Reserved
19
GND
V12 20
23 21 2 2 2
NC V12
24 NC V12 22

SANTA_191901-1

CONN@

C
CD-ROM Connector C

+5VS

JP5 Placea caps. near ODD

1 CONN.
GND SATA_ITX_RPI_DRX_P4
A+ 2 SATA_ITX_RPI_DRX_P4 21
3 SATA_ITX_RPI_DRX_N4
A- SATA_ITX_RPI_DRX_N4 21

1U_0603_10V4Z

10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z
GND 4
5 SATA_DTX_IRX_N4 1 2 SATA_DTX_C_IRX_N4 1 1 1 1
B- SATA_DTX_IRX_P4 C788 SATA_DTX_C_IRX_P4 SATA_DTX_C_IRX_N4 21
6 1 20.01U_0402_16V7K SATA_DTX_C_IRX_P4 21
C512 C513 C514 C515
B+ C789 0.01U_0402_16V7K
7
GND
Near CONN side. 2 2 2 2
8
DP
+5V 9
10 +5VS
+5V
11
MD
15 12
GND GND
14 13
GND GND

SANTA_204901-1

CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 24 of 46
5 4 3 2 1
 5 4 3 2 1

+3V_LAN
3/30 Remove CL3 when use AR8132
60mil
+3VALW 1 2
RL1 0_1206_5%
@ 1 1 1 1
CL3 CL4 CL1 CL2
10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2

D
6
10U_0805_10V4Z 1U_0402_6.3V4Z
S
4 5
2
QL1 1
SI3445ADV-T1-E3_TSOP6
G

+3VALW +3VALW +3VALW

Place Close to Pin 2
3

D D

1 210K_0402_5% LAN_POWER_OFF 31 1 1 1
2 RL6
CL8 C1409 C1410 C1411
0.1U_0402_25V4K 0.1U_0402_25V4K 0.1U_0402_25V4K
0.1U_0402_16V4Z 2 2 2
1
U44

22 GLAN_RXP
CL15 1 2 0.1U_0402_16V7K GLAN_RXP_C 22 HSOP LED3/EEDO 31
+3VS 37
LED1/EESK
22 GLAN_RXN
CL14 1 2 0.1U_0402_16V7K GLAN_RXN_C 23 40
HSON LED0
2

GLAN_TXP 17 30 R466 1 2 10K_0402_5%

22 GLAN_TXP GLAN_TXN HSIP EECS/SCL
R314 18 32 R394 1 2 10K_0402_5%
22 GLAN_TXN HSIN EEDI/SDA
1K_0402_5%
+3VS LAN_CLKREQ# 16 1 MDI0+
1

ISOLATE# 17 LAN_CLKREQ# CLKREQB MDIP0 MDI0- MDI0+ 26

2 MDI0- 26
PLT_RST# MDIN0 MDI1+
9,20,26 PLT_RST# 25 PERSTB MDIP1 4 MDI1+ 26
1

5 MDI1-
MDIN1 MDI1- 26
2

R3101 CLK_PCIE_LAN 19 7 MDI2+

17 CLK_PCIE_LAN REFCLK_P NC/MDIP2 MDI2+ 26
15K_0402_5% R467 CLK_PCIE_LAN# 20 8 MDI2-
17 CLK_PCIE_LAN# REFCLK_N NC/MDIN2 MDI3+ MDI2- 26
10K_0402_5% 10 MDI3+ 26
NC/MDIP3 MDI3-
11
2

NC/MDIN3 MDI3- 26
LAN_XTALI 43
1

CKXTAL1
LAN_CLKREQ# LAN_XTALO 44 13
CKXTAL2 DVDD10 +LAN_VDD10
29
C +3V_LAN DVDD10 C
DVDD10 41
1 R561 2 ICH_PCIE_WAKE#_R 28
22,26 ICH_PCIE_WAKE# LANWAKEB
0_0402_5%
2

ISOLATE# 26 27 +3V_LAN
R397 +3V_LAN ISOLATEB DVDD33
DVDD33 39
0_0402_5%
R318 2 1 1K_0402_5% 14 12 +LAN_VDD10 +LAN_EVDD10
R395 2 NC/SMBCLK AVDD33
1 10K_0402_5% 15 42
1

ENSWREG R396 2 NC/SMBDATA AVDD33

+3V_LAN 1 1K_0402_5% 38 GPO/SMBALERT AVDD33 47
48 RL19 1 2 0_0603_5%
AVDD33
2

R398
Add Lan_clkeq# pull high. 1204 ENSWREG
1 1
33
ENSWREG CL22 CL43
0_0402_5% EVDD10 21 +LAN_EVDD10
@ +LAN_VDDREG 34 1U_0402_6.3V4Z 0.1U_0402_16V4Z
VDDREG 2 2
35 3 +LAN_VDD10
1

VDDREG AVDD10
6
AVDD10
9
RL15 1 2.49K_0402_1% AVDD10 +LAN_VDD10
2 46 45
RSET AVDD10 LL1
24 36 +LAN_VDD10_L 1 2
+3V_LAN +LAN_VDDREG GND REGOUT S INDUC_ 4.7UH +-20% SIA4012-4R7M
49 1 1
PGND
C502 C629
RL18 1 2 0_0603_5% RTL8111E-GR_QFN48_6X6 22U_0805_6.3V6M 0.1U_0402_16V4Z
2 2
1
1

60mil
C630 CL10
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
2

B B

LAN_XTALI

+3V_LAN +LAN_VDD10
LAN_XTALO
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
Y3 1 1 1 1 1 1 1 1
1 2
CL29 CL30 CL31 CL21 CL23 CL24 CL25 CL26
1 25MHZ_20P 1 2 2 2 2 2 2 2 2
CL32 CL33
27P_0402_50V8J 27P_0402_50V8J
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN, WWAN, New Card

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 25 of 46
5 4 3 2 1
 A B C D E

Need to confirm EC GPIO PIN 09/22 Mini Card

+3VL +3VS_WLAN +1.5VS_WLAN ---WLAN

DAN217T146_SC59-3
0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z

+3VL +3VALW R431 1 2 0_0805_5%

1 1 1 1 1 +1.5VS +1.5VS_WLAN
C566 C567 C569 C570 C571

3
1

1
10K_0402_5%
R149 @ 2 2 2 2 2 R432 1 0_0805_5%
+3VS 2 +3VS_WLAN

R145
1 4.7U_0805_10V4Z 1
10K_0402_5% 0.1U_0402_16V4Z
D8

1
@ @ 10K_0402_5%
KILL_SW# 31 BT_OFF#
29,31 BT_OFF# 1 R438 2 02/13 Change WLAN and WWAN 0402 resistor to

BTOFF#
29 BT_OFF#_C BT_OFF#_C 1 R439 2 0805, and WLAN change to +3VS power plane
0_0402_5% JP7
1

3 22,25 ICH_PCIE_WAKE#
ICH_PCIE_WAKE# 1 1 2 2 +3VS_WLAN
WLAN_ACTIVE @1 R424 2 0_0402_5% 3 4
1

3
29 WLAN_ACTIVE BT_ACTIVE 3 4
@1 R430 2 0_0402_5% 5 6 +1.5VS_WLAN
29 BT_ACTIVE CLKREQ#_6 5 6
7 8 R699 1 2 0_0402_5%
SW5
KILL 17 CLKREQ#_6
9
7
9
8
10 10 R700 1 2 0_0402_5%
LPC_FRAME#
LPC_AD3
21,31
21,31
CLK_PCIE_MCARD2# 11 12 R701 1 2 0_0402_5%
1BS003-1211L_3P SWITCH 17
17
CLK_PCIE_MCARD2#
CLK_PCIE_MCARD2
CLK_PCIE_MCARD2 13
11
13
12
14
14 R702
R703
1 2 0_0402_5%
0_0402_5%
LPC_AD2
LPC_AD1
21,31
21,31
15 16 1 2 LPC_AD0 21,31
PLT_RST# 15 16
9,20,25 PLT_RST# 17 17 18 18
left OFF right ON(09/05/26) 17 CLK_DEBUG_PORT_1 19
21
19
21
20
22
20
22
XMIT_OFF#
PLT_RST#
22 PCIE_RXN3 R423 1 2 0_0402_5% PCIE_C_RXN3 23 24 R426 1 2 0_0805_5% +3VS_WLAN
R425 1 PCIE_C_RXP3 23 24
22 PCIE_RXP3 2 0_0402_5% 25 26
25 26
27 28 +1.5VS_WLAN
27 28 ICH_SMBCLK
29 29 30 30
PCIE_TXN3 31 32 ICH_SMBDATA ICH_SMBCLK 17,22
22 PCIE_TXN3 PCIE_TXP3 31 32 ICH_SMBDATA 17,22
33 34
22 PCIE_TXP3 33 34
35 35 36 36 USB20_N5 22
37 38 USB20_P5 22
37 38
39 40
39 40
+3VS_WLAN 41 41 42 42
43 43 44 44
45 46
45 46
47 48 +1.5VS_WLAN
2 C1122 T89 EC_TX 47 48 2
31 EC_TX 49 49 50 50
1 2 1 24 MCT3 C1126 1 2 R5 2 1 75_0402_5% EC_RX 51 52 +3VS_WLAN
MDI3- TCT1 MCT1 MDO3- 31 EC_RX 51 52
0.01U_0402_16V7K 2 23 0.01U_0402_16V7K
25 MDI3- TD1+ MX1+
C1123 MDI3+ 3 22 MDO3+ 53 54
25 MDI3+ TD1- MX1- MCT2 GND1 GND2
1 2 4 21 C1127 1 2 R9 2 1 75_0402_5%
0.01U_0402_16V7K MDI2- TCT2 MCT2 MDO2- 0.01U_0402_16V7K
25 MDI2- 5 20
TD2+ MX2+

1
C1124 MDI2+ 6 19 MDO2+ FOX_AS0B226-S40N-7F_52P
25 MDI2+ TD2- MX2-
1 2 7 18 MCT1 C1128 1 2 R10 2 1 75_0402_5%
0.01U_0402_16V7K MDI1- TCT3 MCT3 MDO1- 0.01U_0402_16V7K R1094
25 MDI1- 8 TD3+ MX3+ 17 CONN@
C1125 MDI1+ 9 16 MDO1+ 100K_0402_5%
25 MDI1+ TD3- MX3- MCT0
1 2 10 15 C1129 1 2 R12 2 1 75_0402_5% C665

2
0.01U_0402_16V7K MDI0- TCT4 MCT4 MDO0- 0.01U_0402_16V7K RJ45_GND
25 MDI0- 11 14 1 2
MDI0+ TD4+ MX4+ MDO0+
25 MDI0+ 12 TD4- MX4- 13
1000P_1808_3KV7K
350uH_GSL5009LF
Place close to TCT pin

Change to IAT50 footprint, because of error layout symbol. 1202

04/29 MV-1 add clock REQ pull high

Modify as B3B5. 11/11 R11
1 2 CLKREQ#_6
+3VS
3 +3VALW 3
10K_0402_5%

LAN Conn.

1
JRJ45 @
@ R433 R434
10K_0402_5% 100K_0402_5%

2
XMIT_OFF#
MDO3- 8 PR4- D

1
D23 @
MDO3+ 7 1 2 2 Q10
PR4+ 31 WL_OFF#
G 2N7002_SOT23-3
MDO1- 6 CH751H-40_SC76 S

3
PR2-
MDO2- 5
PR3- R435
MDO2+
01/03 Prevent WLAN leakage
4 1 2
PR3+ 0_0402_5%
MDO1+ 3
PR2+
MDO0- 2
PR1-
GND 10
MDO0+ 1
PR1+
9
GND

TYCO_1734819_8P-T
CONN@ LANGND
4 4
1 1
CL41 CL42
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN, WWAN, New Card

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 26 of 46
A B C D E
 5 4 3 2 1

SD,MMC,MS muti-function pin define

Realtek Recommend MDIO SD Card MMC Card MS Card
PIN Name PIN Name PIN Name PIN Name
MS_CLK SD_CLK SP1
MODE_SEL

1
SP2 SDWP#

1
1 R515 R517
C609 R516 @ @ SP3 SDCD#
@ 10_0402_5% 10_0402_5%
47P_0402_50V8J 0_0402_5% SP4 SDCDAT1 MSWR

2
2

2
D 1 1 SP5 MSBS D
C610 C611
+3VS_CR_VCC @ @ SP6 MSCDAT1
10P_0402_50V8J 10P_0402_50V8J
2 2
SP7 SDCDAT0 MSCDAT0
1 1 1 0.1U_0402_16V4Z
C612 2 2 SP8 SDCDAT7 MSCDAT2
C613 C614
1U_0603_10V4Z 0.1U_0402_16V4Z 1U_0603_10V4Z C615 C616 U36 SP9 MS_INS#
2 2 2
0.1U_0402_16V4Z AV_PLL 1 1
1 SP10 SDCDAT6 MSCDAT3
AV_PLL
3 NC
7 NC SP11 SDCCLK MSCCLK
+VCC_OUT 9 AV_PLL 20mil (+1.8V internal regulator)
CARD_3V3
11 D3V3 SP12 SDCDAT5 MSCDAT6
33 10 AV_PLL
D3V3 VREG
MS_D4 22 SP13 SDCDAT4 MSCDAT7
NC 30
+3VS_CR_VCC 1 R518 2 0_0603_5% +3V3_IN 8 3V3_IN SP14
CARD_RST# 44
@ MODE_SEL RST#
+3VALW 1 2 45 MODE_SEL SP15 SDCDAT3
R520 0_0603_5% 1 C618 CARD_XTLO 47 43
CARD_XTLI XTLO XD_CLE_SP19
48 XTLI XD_CE#_SP18 42 SP16 SDCDAT2
C617 0.1U_0402_16V4Z 41
+3VS_CR_VCC USB20_N7 XD_ALE_SP17 SDDAT2_XDRE#
4.7U_0805_10V4Z
2 22 USB20_N7 4 DM SD_DAT2/XD_RE#_SP16 40 SP17
22 USB20_P7 USB20_P7 5 39 SDDAT3_XDWE#
DP SD_DAT3/XD_WE#_SP15
14 GPIO0 XD_RDY_SP14 38 SP18
1

@ 37
R521 SD_DAT4/XD_WP#/MS_D7_SP13 R522 0_0402_5%
SD_DAT5/XD_D0/MS_D6_SP12 35 SP19
C 100K_0402_5% 34 SDCLK_MSCLK 1 2 SD_CLK C
SD_CLK/XD_D1/MS_CLK_SP11 SDDAT6_MSD3 R523 0_0402_5%
Internal 200K pull up SD_DAT6/XD_D7/MS_D3_SP10 31
29 MS_INS# 1 2 MS_CLK
2

MS_INS#_SP9
1 R524 2 CARD_RST#
SD_DAT7/XD_D2/MS_D2_SP8 28 SDDAT7_MSD2
0_0603_5% 27 SDDAT0_MSD0
SD_DAT0/XD_D6/MS_D0_SP7
1

C619 26 SP6
SD_DAT1/XD_D3/MS_D1_SP6 MS_BS +3VS_CR_VCC
XD_D5_SP5 25
R525 23 XDD4_SDDAT1
1U_0603_10V4Z 499K_0402_1% XD_D4/SD_DAT1_SP4 SD_CD# U24
SD_CD#_SP3 21
@ 20 SD_WP 8 1 CARD_EECS
2

SD_WP_SP2 +3VS_CR_VCC VCC CS CARD_EESK

XD_CD#_SP1 19 1 7 NC SK 2
18 CARD_EEDI 6 3 CARD_EEDO
EEDI C620 NC DI CARD_EEDI
5 GND DO 4
2 13 R526 1 2 0_0402_5% @
RREF XTAL_CTR
1

24 0.1U_0402_16V4Z 2 AT93C46-10SI-2.7_SO8
R527 MS_D5 @
12 DGND
@ 32 15 CARD_EEDO
Y8 6.19K_0402_1% DGND EEDO CARD_EECS
EECS 16
1 R528 2 CARD_XTLI 1 2 CARD_XTLO 6 17 CARD_EESK
2

17 CLK_SD_48M 0_0402_5% AGND1 AGND EESK SD_CMD +VCC_3IN1

12MHZ_18PF_X5H012000FI1H
46 AGND SD_CMD 36
3 in 1 Card Reader
1

R531
@ R530 S IC RTS5159-GR LQFP 48P CARD READER
250mA
270K_0402_5% 0_0402_5%
1 1 JREAD1
C621 C622 2/17 Change Part number of U25 from SA00001NK10 to SA00002YP00 SD_WP 1
2

@ @ XDD4_SDDAT1 SD-WP
2 SD-DAT1
6P_0402_50V8J 6P_0402_50V8J SDDAT0_MSD0 3
B 2 2 SD-DAT0 B
4 SD-GND
5 MS-GND
MS_BS 6
SD_CLK MS-BS
7 SD-CLK
+VCC_3IN1 SP6 8
4/2 Add by Vivian SDDAT0_MSD0 MS-DAT1
100P_0402_50V8J 2
C878
1 @ CLK_SD_48M
40mil 9
10
MS-DAT0
+VCC_OUT SD-VCC
1 R532 2 SDDAT7_MSD2 11 MS-DAT2
0_0603_5% 12
10U_0805_10V4Z

MS_INS# SD-GND
1 1 13 MS-INS
SDDAT6_MSD3 14
C623 C624 C625 SD_CMD MS-DAT3
15 SD-CMD
4.7U_0805_10V4Z @ MS_CLK 16
2 2 EMI SD_CLK MS_CLK 17
MS-SCLK
0.1U_0402_16V4Z

SDDAT3_XDWE# MS-VCC
18 SD-DAT3
19 MS-GND
SDDAT2_XDRE# 20 22
SD_CD# SD-DAT2 GND1

100K_0402_5%

100K_0402_5%
21 SD-CD GND2 23

1
@ @
R529

R534
Add C822 4.7u and reserve C808 10u TAITW_R009-025-LR_NR
for cost down Michael 2008/5/30 CONN@
2

2
+3VS Change to KIUN0 CONN, need double confirm pin define.10/23 prince
W=40mils 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z
@ @
C626

C628
1

A 1 2 2 A
C627 R533
@
1U_0603_10V4Z 0_0805_5%
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

+3VS_CR_VCC Issued Date 2009/02/04 Deciphered Date 2010/02/04 Title
W=40mils RTS5159 Cardreader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Montevina UMA LA6121P
Date: Thursday, April 15, 2010 Sheet 27 of 46
5 4 3 2 1
 5 4 3 2 1

+5VS +VDDA R020

U39 +VDDA 1 2 +5VS
3 4 0_0805_5% BYPASS R436
@ VIN VOUT LINE_OUT# SPKL+
R1422 1 2
+3VS_HD_DVDD

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 2 1 1 1 2 15K_0603_1%
C1775 EN C1777
C1774 @ 10K_0402_5% 2 5 C1776 @ +DVDD_IO 1 2 +1.5VS C506
@ GND NC @ R1290 0_0603_5% R437
0.22U_0603_10V7K
2 2 RT9198-4GPBG_SOT23-5 2 2 1 LINE_OUT 1 2 SPKR+
@ 1 2 15K_0603_1%
R1300 @ 0_0603_5%

+3VS

+3VS_HD_DVDD 20mil R1280 1 2

D D
+VDDA +AVDD_HD 0_0603_5% U40

0.1U_0402_16V7K

0.1U_0402_16V7K
L108
1 2
40mil C1397
1
C1398
1
MUTE# 1
GND2 9
8 SPKL+ +5VAMP R1958 +5VS
C504 BYPASS SD# OUTN
FBM-L11-160808-800LMT_0603 R429 2 7 0.1U_0402_16V4Z 0_1206_5%
BYPASS GND1
10U_0805_10V4Z

0.1U_0402_16V7K
1 1 2 1 2 LINE_OUT# 3 INP VDD 6 1 2
2 2

0.1U_0402_16V7K

0.1U_0402_16V7K
C3199 4.99K_0603_1% SPKR+

+DVDD_IO
1 1 1 4 5
C1440 C1470 0.22U_0603_10V7K INN OUTP
1 1
C1450 APA0715QBI-TRG_TDFN8_3X3
2 C503 R428 C1495 C1496
2 2 2 LINE_OUTR LINE_C_OUTR 1 LINE_OUT
1 2 2
10K_0603_1% 10U_0805_10V4Z 2 2
0.1U_0603_50V4Z

25

38

9
U38
C505 R427

DVDD_IO
AVDD1

AVDD2

DVDD
LINE_OUTL 1 2 LINE_C_OUTL 1 2
C1784 @ 1 2 1000P_0402_50V7K 10K_0603_1%
0.1U_0603_50V4Z
14 35 LINEL 1 2 LINE_OUTL
LINE2_L LOUT1_L R1427 0_0402_5% +3VS
15 36 LINER 1 2 LINE_OUTR
LINE2_R LOUT_R R1428 0_0402_5%

1
16 MIC2_L LOUT2_L 39 1 2 1000P_0402_50V7K R2405

17 41 C1785 @ 100K_0402_5%
MIC2_R LOUT2_R
23 45 D15

2
LINE1_L SPDIFO2 EC_MUTE# 1 MUTE#
31 EC_MUTE# 2
24 LINE1_R DMIC_CLK1/2 46 DMIC_CLK 19
Low-->mute CH751H-40PT_SOD323-2
18 43 @
LINE1_VREFO NC R410

2
@
C R251 C
20 LINE2_VREFO DMIC_CLK3/4 44 1 2 1 2
10_0402_5% C023 10P_0402_50V8J 1K_0402_5%
19 6 HDA_BITCLK_CODEC
MIC2_VREFO BITCLK HDA_BITCLK_CODEC 21
R08 Low-->mute

1
MIC_L 1 2 1 2 C025 MIC_LEFT 21 8 SDIN_CODEC 1 2
MIC1_L SDATA_IN HDA_SDIN0 21
R252 1K_0402_5% 2.2U_0603_10V6K 33_0402_5% EAPD
MIC_R 1 2 C024 MIC_RIGHT C1042 2
R253
2
1K_0402_5%
1
2.2U_0603_10V6K
22 MIC1_R CBN 30 1 need double confirm Pin1 define.
MONO_IN 12 29 2.2U_0603_10V6K 0_0603_5% JP13
PCBEEP_IN CBP SPKR+ R1281 1 2 SPKR_R 1
SPKL+ 1
MONO_OUT 37 1 2 SPKL_R 2 2
11 C1786 @ R1282 0_0603_5%
21 HDA_RST#_CODEC RESET#

47P_0402_50V8J

47P_0402_50V8J
MIC1_VREFO 28 10mil +MIC1_VREFO 1 2 1000P_0402_50V7K 3 GND

3
21 HDA_SYNC_CODEC 10 1 1 4
SYNC HP_RIGHT HP_R GND
32 1 R1360 2 75_0603_1% HP_R 29 D18
HPOUT_R

C1492

C1493
PJDLC05_SOT23-3
5 ACES_88231-02001
21 HDA_SDOUT_CODEC SDATA_OUT HP_LEFT HP_L
33 1 R1361 2 75_0603_1% HP_L 29 @ @ @
HPOUT_L 2 2
2 CONN@
19 DMIC_DAT 20K_0402_1% GPIO0/DMIC_DATA1/2
3 1 2 1000P_0402_50V7K
SENSE_A GPIO1/DMIC_DATA3/4
29 MIC_JD 1 R892 2 13 SENSE A
@ C1787
1 R013 2 SENSE_B 34 27
29 HP_JD SENSE B VREF
5.1K_0402_1%

1
10U_0805_10V6K
EAPD 47 40 1 R893 2 20K_0402_1% 1 2
EAPD JDREF
48 31 C66 C1413
SPDIFO1 CPVEE
1U_0402_6.3V6K
2 1
2.2U_0603_10V6K

4 DVSS1 AVSS1 26 2
7
DVSS2 AVSS2
42 Change to Digital GND from Jeson&Bill's sugestion. 1201
ALC272-GR_LQFP48_7X7 C1414
1
R1441 1 2 0_0603_5%
B B

R1105 1 2 0_0603_5%
Modify as NAT10 +MIC1_VREFO +MIC1_VREFO
R1106 1 2 0_0603_5%

R117 1 2 0_0603_5% @ 1
C304
1

1
+VDDA
R118 1 2 0_0603_5% R1349 220P_0402_25V8J
R1348 4.7K_0402_5% 2
2

4.7K_0402_5%
GND GNDA R1429
MIC_R 2

10K_0402_5%
MIC_L
1

C1788
1 2 MIC_R 29
2

1U_0402_6.3V6K MIC_L 29
EC Beep R1183
R1430
C1412 10K_0402_5%
1 2 1 2
1

31 EC_BEEP
C1789
1U_0402_6.3V6K 560_0402_5% 1 2 MONO_IN
1 R1431 2
1U_0402_6.3V6K
1

47K_0402_5% C 1 2
2 Q21 R1376
A B A
E 2SC2411K_SC59 2.4K_0402_5%
ICH Beep
3

R1188
C1416
22 SB_SPKR 1 2 1 2
2

1U_0402_6.3V6K 560_0402_5%
1 R1432 2 D21 Security Classification Compal Secret Data Compal Electronics, Inc.
R1433 RB751V_SOD323 Issued Date 2009/02/04 2010/02/04 Title
47K_0402_5%
Deciphered Date
10K_0402_5% HD Audio ALC272
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 28 of 46
5 4 3 2 1
 5 4 3 2 1

+5VALW +USB_AS
0.1U_0402_16V
1
U13
80 mils

1
1 8 + C444 C274
GND OUT R156
2 7
IN OUT 150U_B2_6.3VM_R45M 470_0603_5%
3 6
USB_EN# IN OUT 2
1 4 EN# OC# 5
C275

1 2
RT9711PS SO 8P
0.1U_0402_16V D
2 USB_EN# 2 Q20
G SSM3K7002FU_SC70-3

1
S

3
D USB_OC#2 22 D
R159
100K_0402_5%
1 2 @
R125 0_0402_5%

2
1 2
R144 0_0402_5%

JUSB1
USB20_P2 4 3 1
22 USB20_P2 4 3 USB_P2 GND
2 USB_P
USB_N2 3
USB20_N2 USB_N
22 USB20_N2 1 2 +USB_AS 4
1 2 VCC
W=60mils 5
GND
6 GND
@ L7 WCM2012F2S-900T04_0805 7
GND
8 GND
SUYIN_020173MR004S52KZL
CONN@

+5VALW 4
D46

VIN IO1 2 USB_N2 BT Connector

USB_P2 3 1
IO2 GND +3VAUX_BT
@ PRTR5V0U2X_SOT143-4
JP61
9 1
C GND 1 C
2 2
3 USB20_P6_R R1088 2 1 0_0402_5%
3 USB20_N6_R USB20_P6 22
4 R1089 2 1 0_0402_5%
4 USB20_N6 22
5 5 BT_ACTIVE 26
6 6 WLAN_ACTIVE 26
7
7
10 GND 8 8
modify on 09/17 and need to confirm with ME ACES_87213-0800G

CONN@

+5VALW

D47
0612 no install +5VALW 4 2 USB20_P6_R
VIN IO1
1 USB20_N6_R 3 1
IO2 GND
@ C273 +
1
C64 USB/B to M/B Conn. +3VS
R235
@ PRTR5V0U2X_SOT143-4

150U_B2_6.3V-M~D 470P_0402_50V7K~D 1 2
2 2 JP8
MIC_R 0_0603_5% Q105 +3VAUX_BT
28 MIC_R 1
MIC_L 1 AO3413_SOT23-3
28 MIC_L 2
B MIC_JD 2 B
28 MIC_JD 3 3 0.1U_0402_16V4Z

D
4 4 3 1
HP_L 5
28 HP_L HP_R 5
28 HP_R 6 6

1
HP_JD +3VS

G
7 1 1 1 1

2
28 HP_JD 7 +3VS C1387 C1388
8 C1389
8 C1386 @ R1090
9
USB20_N1 9 1U_0603_10V4Z 100K_0402_5%
22 USB20_N1 10
10

2
USB20_P1 11 2 2 2 2

2
22 USB20_P1 11 2
12 R602
USB20_N0 12 R603 10K_0402_5% 0.01U_0402_16V7K 4.7U_0805_10V4Z
22 USB20_N0 13 13
USB20_P0 14 10K_0402_5%
22 USB20_P0 14
15 C1390

1
22 USB_OC#0 USB_OC#0 15 BT_OFF R1092 1
16 2 10K_0402_5% 1 2
1

USB_EN# 16 Q14 0.1U_0402_16V4Z

31 USB_EN# 17 17
18 2N7002_SOT23-3
18 D

1
+5VALW 19
19 BT_OFF#
20 26,31 BT_OFF# 2
20 G +3VS
21
21
22 S
3
22

2
23
GND1 R604
24 GND2 10K_0402_5%
ACES_87213-2200G

1
CONN@
Q15 BT_OFF#_C BT_OFF#_C 26
2N7002_SOT23-3

1
R155 D
BT_OFF 1 2 2
A G A
0_0402_5% S

3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 29 of 46
5 4 3 2 1
 5 4 3 2 1

D
SPI ROM D

+3VL
U27
20mils 8 4
VCC VSS
1
C712 3
0.1U_0402_16V4Z W
7 HOLD
2
1 2 SPI_FSEL# 1
31 FSEL# S
R553 10_0402_5%
1 2 SPI_CLK_R 6
31 SPI_CLK C
R554 10_0402_5%
1 2 SPI_FWR# 5 2 SPI_SO 1 2 FRD#
31 FWR# D Q FRD# 31
R556 10_0402_5% R555 0_0402_5%
W25Q16BVSSIG_SO8

SP07000F500 S SOCKET WIESON G6179-100000 8P

SPIFLASH
R230 C307
SPI_FSEL# 2 1 2 1 WIESO_G6179-100000_8P

33_0402_5% 22P_0402_50V8J

R231 C308
SPI_CLK_R 2 1 2 1

33_0402_5% 22P_0402_50V8J

R232 C309
SPI_FWR# 2 1 2 1
C C
33_0402_5% 22P_0402_50V8J

12/27EMI
request Remove LPC Debug Port
20090618

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 30 of 46
5 4 3 2 1
 +3VL_EC +3VL

0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K

EC_SEL EC_VERSION
1 1 1 1 1 Follow EC's request.01/18

1
C715 C716 C717 C718 C719 +3VL +3VL_EC +EC_AVCC High KB926D3
@ R1091
2 2 2 2 2
0.1U_0402_16V4Z 1000P_0402_50V7K
R572 Low KB926E0 100K_0402_5%
1 2

2
04/22 MV1 Change SMbus1 power to +3VL 0_0805_5%
EC_SEL
For EMI

111
125
+3VL +3VS

22
33
96

67
9

1
U30 KSO15 @C792
@ C792 1 2 100P_0402_50V8J
SMB_EC_DA1 R573 1 2 2.2K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
SMB_EC_CK1 R577 1 2 2.2K_0402_5% R1093 KSO10 @C793
@ C793 1 2 100P_0402_50V8J
SMB_EC_DA2 R574 1 2 2.2K_0402_5% 100K_0402_5%
SMB_EC_CK2 R575 1 2 2.2K_0402_5% KSO11 @C794
@ C794 1 2 100P_0402_50V8J

2
GATEA20 1 21
21 GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F EC_BEEP T90 KSO14
03/28 PV2 Change SM bus power to +3VL 2 23 @C795
@ C795 1 2 100P_0402_50V8J
21 KB_RST# SIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP 28
22 SIRQ 3 26 KILL_SW# 26
LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF KSO13 @C796
@ C796 1
21,26 LPC_FRAME# 4 LFRAME# ACOFF/FANPWM2/GPIO13 27 ACOFF 35,36 2 100P_0402_50V8J
@ C722 @ R576 21,26 LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K
LPC_AD2 LAD3 ECAGND KSO12
1 2 1 2 21,26 LPC_AD2 7
LAD2 PWM Output C720 1 2 @C797
@ C797 1 2 100P_0402_50V8J
33_0402_5% 21,26 LPC_AD1 LPC_AD1 8 63 BATT_TEMP
LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 34 KSO3
15P_0402_50V8J 21,26 LPC_AD0 10
LAD0 LPC & MISC BATT_OVP/AD1/GPIO39
64 T87 PWR delete BATT_OVP. 11/03 @C798
@ C798 1 2 100P_0402_50V8J
65 ADP_I
ADP_I/AD2/GPIO3A ADP_I 36
CLK_PCI_EC 12 AD Input 66 KSO6 @C799
@ C799 1 2 100P_0402_50V8J
17 CLK_PCI_EC PCI_RST# PCICLK AD3/GPIO3B T92
13 75 T93
20 PCI_RST# ECRST# PCIRST#/GPIO05 AD4/GPIO42 NMI_DBG# KSO8 @C800
@ C800 1
+3VL 1 2 37 ECRST# SELIO2#/AD5/GPIO43 76 2 100P_0402_50V8J
R578 47K_0402_5% 20
22 EC_SCI# SCI#/GPIO0E KSO7
+3VS 2 10K_0402_5%
1 38 Change CHGVADJ from Pin68 to 72, follow EC's suggestion.01/20 @C801
@ C801 1 2 100P_0402_50V8J
@ R590 CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68 T91
1

2 1 J1 11/09 Delete 70 EN_DFAN1 KSO4 @C802

@ C802 1 2 100P_0402_50V8J
EN_DFAN1/DA1/GPIO3D IREF EN_DFAN1 6
C721 0.1U_0402_16V4Z DA Output 71
JOPEN CLKRUN# KSI0 IREF/DA2/GPIO3E CHGVADJ IREF 36 KSO2 @C803
@ C803 1
55 72 Follow Danny's suggestion.01/14 2 100P_0402_50V8J
2

KSI0/GPIO30 DA3/GPIO3F CHGVADJ 36

KSI1 56 PWR delete 2nd batt.1204
KSI2 KSI1/GPIO31 +5VS KSI0 @C804
@ C804 1
57 KSI2/GPIO32 2 100P_0402_50V8J
11/09 Add HDA_RST# to EC KSI3 58 83 EC_MUTE#
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A USB_EN# EC_MUTE# 28 KSO1
11/17 Change to 59 84 R579 1 2 4.7K_0402_5% @C805
@ C805 1 2 100P_0402_50V8J
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 29
60 85 1@ R591 2 0_0603_5% TSATN# 9
R580 1 2 4.7K_0402_5%
+3VALW KSI6 KSI5/GPIO35 PSCLK2/GPIO4C WL_BT_LED# KSO5
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86 WL_BT_LED# 32
@C806
@ C806 1 2 100P_0402_50V8J
SYSON SUSP# PCI_RST# KSI7 62 87 TP_CLK TP_CLK 32
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E
Del HDA_RST#_EC to EC 9/29 Prince KSO0 KSO1
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA
TP_DATA 32
KSI3 @C807
@ C807 1 2 100P_0402_50V8J
1 2 40 KSO1/GPIO21
1

+3VL R584 1 247K_0402_5% KSO2 41 DEL AC_LED# 9/29 Prince 02/13 Correct AC_LED control by EC KSI2 @C808
@ C808 1 2 100P_0402_50V8J
R581 R713 R599 47K_0402_5% KSO3 KSO2/GPIO22
2 42 97
8.2K_0402_5% 100K_0402_5% +3VL KSO4 43
KSO3/GPIO23 SDICS#/GPXOA00
98 LAN_POWER_OFF T84 KSO0 @C809
@ C809 1 2 100P_0402_50V8J
KSO5 KSO4/GPIO24 SDICLK/GPXOA01 BT_OFF# LAN_POWER_OFF 25
C1415
KSO5/GPIO25 Int. K/B 11/09 don't stuff when use
44 99 BT_OFF# 26,29
KSO6 SDIDO/GPXOA02 LID_SW# KSI5 @C810
@ C810 1
1U_0402_6.3V6K 45 109 LID_SW# 32 2 100P_0402_50V8J
KSO6/GPIO26 Matrix
2

1 KSO7 SDIDI/GPXID0 C0
46 KSO7/GPIO27 SPI Device Interface
2

KSO8 47 KSI4 @C811

@ C811 1 2 100P_0402_50V8J
@ R585 KSO9 KSO8/GPIO28 FRD#
48 KSO9/GPIO29 SPIDI/RD# 119 FRD# 30
10K_0402_5% KSO10 49 120 R227 1 2 33_0402_5% FWR# KSO9 @C812
@ C812 1 2 100P_0402_50V8J
KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK FWR# 30
11/15 Delete PCI_PME# 50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 R228 1 2 47_0402_5%
SPI_CLK 30
KSO12 51 128 R229 1 2 33_0402_5% FSEL# KSI6 @C813
@ C813 1 2 100P_0402_50V8J
1

KSO13 KSO12/GPIO2C SPICS# FSEL# 30

11/07 Add SYSON and SUSP# PD EC_PME# KSO14
52 KSO13/GPIO2D KSI7
20 PCI_PME#
@ R589 1 2 53
KSO14/GPIO2E change STD_ADP to BATT_CHG_LED#. 10/25 @C814
@ C814 1 2 100P_0402_50V8J
0_0402_5% KSO15 54 73
KSO15/GPIO2F CIR_RX/GPIO40 T94 KSI1
81 74 11/09 PU +5VL move to M/B @C815
@ C815 1 2 100P_0402_50V8J
KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG T97 SPI_CLK
82 89 FSTCHG 36
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHG_LED# 10K_0402_5%
90 BATT_CHG_LED# 32
BATT_CHGI_LED#/GPIO52 CAPS_LED#
91 CAPS_LED# 32 1 2 2
CAPS_LED#/GPIO53

4.7U_0603_6.3V6K
SMB_EC_CK1 77 GPIO 92 BATT_LOW_LED# R1132
34 SMB_EC_CK1 SMB_EC_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 ON/OFFBTN_LED# BATT_LOW_LED# 32
78 93 C818
34 SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# 32

100K_0402_5%

C1408
SMB_EC_CK2 79 SM Bus 95 1 22P_0402_50V8J
6 SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56

1
+3VL +3VL SMB_EC_DA2 80 121 VR_ON 1
6 SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 41

R1133
127 AC_IN
AC_IN/GPIO59 9,33,39 SYSON
2 1
1

R586 10K_0402_5% 2
R1099 SLP_S3# 6 100 EC_RSMRST#

2
22 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 22
R1100 4.7K_0402_5% SLP_S5# 14 101 R588 1 2
22 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 22
4.7K_0402_5% EC_SMI# 15 102 EC_ON 0_0402_5%
22 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 34 R254
16 103 100_0402_5%
2

T85 ESB_CLK_R LID_SW#/GPIO0A EC_SWI#/GPXO06 PM_PWROK_R

17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 1 2 PM_PWROK SWAP follow Braxton
ESB_DAT_R PM_PWROK 9,22
Delete cap sensor function 09/22 18 GPO 105 R1131 1 2
T86 19
25
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D GPIO
BKOFF#/GPXO08
WL_OFF#/GPXO09
106
107 R_M_PWROK
WL_OFF#
1
26
2
M_PWROK
M_PWROK
0_0402_5%
9,22
BKOFF# 19
INT_KB_Conn.
19 INV_PWM EC_THERM#/GPIO11 GPXO10 JP19
28 108 EC_SEL R597 0_0402_5% R598 PV PWROK sequence issue
6 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
T95 29 1 2 PM_PWROK Current limit KSI1 1
FANFB2/GPIO15 @ 0_0402_5% KSI7 1
26 EC_TX 30 2
R5931 EC_TX/GPIO16 SLP_S4# KSI6 2
+3VL 2 26 EC_RX 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SLP_S4# 22,33 3 3
4.7K_0402_5% ON/OFFBTN 32 ENBKL KSO9
ENBKL/GPXID2 112 ENBKL 11 4
EC_PME# PCI_RST# ON/OFFBTN ON_OFF/GPIO18 KSI4 4
32 ON/OFFBTN T96 NUM_LED#
34
PWR_LED#/GPIO19 GPXID3
114
THERM_SCI#
11/07 Add SLP_S4# to South bridge KSI5
5
5
32 NUM_LED# 36
NUMLED#/GPIO1A GPI GPXID4
115 THERM_SCI# 22 6
6
1 1 116 SUSP# KSO0 7
C723 GPXID5 PWRBTN_OUT# SUSP# 33,38 KSI2 7
117 PWRBTN_OUT# 22 8
C324 C325 15P_0402_50V8J GPXID6 EC_PME# KSI3 8
0.1U_0402_16V4Z 0.1U_0402_16V4Z CRY2 GPXID7 118 KSO5
9 9
1 2 122 XCLK1 10 10
2 2 123 KSO1
XCLK0 V18R 124 +3VL KSI0
11 11
1 12 12
1

AGND

Y5 KSO2 13
GND
GND
GND
GND
GND

@ C724 KSO4 13
3 NC OUT 4 14 14

1
R595 4.7U_0603_6.3V6K R714 KSO7 15
20M_0402_5% KB926QFE0_LQFP128_14X14 2 10K_0402_5% KSO8 15
2 1 16
11
24
35
94
113

69

NC IN KSO6 16
03/13 PV2 Add EMI EC DEBUG 17
2

32.768KHZ_12.5P_1TJS125DJ2A073 KSO3 17
solution For C KSO12
18
18
D14 19
port

2
CRY1 Revision NMI_DBG# 19
1 2 1 2 PCI_SERR# PCI_SERR# 20
KSO13 20
+3VL_EC KSO14 20
21 21
EC_TX@ R233 2 1 C725 CH751H-40PT_SOD323-2 KSO11 22
ECAGND

0_0805_5% 15P_0402_50V8J KSO10 22

23 23
1

@ R605 @ R592 +3VL KSO15 24

ICH_SUSCLK 24
1 2 ICH_SUSCLK_R 1 2 +EC_AVCC L30 11/07 Correct direction pretect leakage 25
22 ICH_SUSCLK 0_0402_5% 0_0402_5% 0_0603_5% 25
26
26
1

R715
L31 150K_0402_5% 04/29 MV1 Change
2

1 2 1 2 27
C726 0.1U_0402_16V4Z 0_0603_5% to 150K GND1
28
D13 GND2
2

EC pin16/19/25/31/21/23/26/76/68/70/85/98/109/106/107/108/118. EC demand to change for common design. 1204 AC_IN 2 1 ACIN

ACIN 36
ACES_88514-2601 CONN@
CH751H-40PT_SOD323-2 Vendor
1 2
C791 100P_0402_50V8J Recommend ME ask to make
EC Pin26/28 design follow Danny's suggestion.2010/1/5 a U-turn.(05/27)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

EC Pin99/106 design follow Danny's suggestion.2010/1/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

www.vinafix.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 31 of 46
 A B C D E

Need to confirm LED courlor

System +5VALW

LED

2
R971
R1101
0_0603_5% LED1 Blue 90.9_0402_1%
ON/OFFBTN_LED# 1 2 2 1 +5VALW System

1
LED2 R120

31 BATT_CHG_LED#
BATT_CHG_LED# 1 B
Blue
2
100_0402_5%
2 1 R970 1
@
2 0_0603_5% +3VALW
HT-191NB_BLUE_0603 Power LED
1 R146 1

31 BATT_LOW_LED#
BATT_LOW_LED# 3 A 4
Amber
2
120_0402_5%
1 Battery
HT-297UD/CB _BLUE/AMB_0603
Charge LED
R1098
D53 +3VS +5VS
90.9_0402_1%
BLUE1 2 2 1 HDD LED
21 SATA_LED# +5VS

HT-191NB_BLUE_0603 Modify as NBLB2.

2
R973
R972 0_0603_5%
0_0603_5%
@

1
BT/WLAN LED
LED3 R151
WL_BT_LED#
31 WL_BT_LED# 1 2
Amber
2
150_0402_5%
1
Modify as NBLB2, need double confirm CONN pin define. 10/24 Prince
HT-191UD_Amber_0603

To TP/B Conn.
JP23
8
GND
2 Modify as new ID.2009/12/28. 6
GND
7
2
+5VS TP_CLK 6
+5VALW 31 TP_CLK
TP_DATA
5
4
5 TP Pin1
31 TP_DATA 4
SWL# 3
JP60 SWR# 3
2 2
1
1
1 TP Pin6
ON/OFFBTN_LED# 1 ON/OFFBTN_LED# ACES_85201-0605N
31 ON/OFFBTN_LED# 2
ON/OFFBTN 2 CONN@
3 3
31 ON/OFFBTN 4 ON/OFFBTN
+5VS 4
CAPS_LED# 5
31 CAPS_LED# NUM_LED# 5
6
31 NUM_LED# 6
2

7 7
8
8 D31 +5VS
9
GND SWR# TP_DATA
10
GND PSOT24C_SOT23
SWL# TP_CLK C701
1

ACES_85201-08051

3
CONN@ 0.1U_0402_16V4Z

SW8 D29 D30

6
5

@ @
ON/OFFBTN 2 4 PSOT24C_SOT23 PSOT24C_SOT23

1
1 3

SMT1-05_4P 4/2 Add by Vivian

Update Footprint
C880
TP_CLK @ 1 2 100P_0402_50V8J
3 3
SW7 C881

6
5
TP_DATA @ 1 2 100P_0402_50V8J
SWL# 2 4
C882
Left Switch 1 3 SWL# @ 1 2 100P_0402_50V8J

SMT1-05_4P C879
SWR# @ 1 2 100P_0402_50V8J

SW6

6
5
SWR# 2 4
+5VS
Right Switch 1 3

SMT1-05_4P
SWL# 2 10K_0402_5%
1
R600

SWR# 2 10K_0402_5%
1
R601

LID switch Modify as KCL00

+3VL A3212ELHLT-T SOT23W +3VL
4 4
U7
VCC

OUT

2 3 LID_SW#
LID_SW# 31
1

1 R2406
GND

100K_0402_5%
1

C4
0.1U_0402_16V4Z Security Classification Compal Secret Data Compal Electronics, Inc.
2

2
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

LID_SW#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD, ON/OFF, SW, CIR

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 32 of 46
A B C D E
 5 4 3 2 1

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

DEL DIM LED 9/30 Prince
+5VALW +5VS B+ +3VALW +3VS

B+ U32 U33
8 1 8 1 10U_0805_10V4Z
D S D S

1
10U_0805_10V4Z
7 D S 2 1 7 D S 2

10U_0805_10V4Z
0.1U_0402_16V4Z
1 6 3 R636 C759 6 3
D S D S
1

C760 5 4 1 1 5 4 1 1
D R223 D G C761 C762 330K_0402_5% 10U_0805_10V4Z D G C763 C764 D
AO4466_SO8 2 AO4466_SO8

2
330K_0402_5% 2
2 2 2 2
DIM LED
2

RUNON_3VS

1
3
RUNON R638 0.1U_0402_16V4Z

1
6

470_0402_5%
R224 SUSP 5

2
470_0402_5% 1
SUSP 2 01/03 Sparate+5VS C765

4
Q34B
1 and +3VS power 0.01U_0402_16V7K
1

Q34A 2
C65
timing 2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6 4700P_0402_25V7K
2

+1.5V to +1.5VS Transfer +3VALW +1.8V

+1.5V +1.5VS +3VL +3VL

B+ U34
U47

1
8 1
D S R639 R640
1 7 2 1 5

10U_0805_10V4Z
C D S IN OUT C
0.1U_0402_16V4Z

C766 6 3 R1114
D S
1

10U_0805_10V4Z
5 4 1 2 C1405 2 47K_0402_1% 100K_0402_5% 100K_0402_5%
D G GND

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
R647 10U_0805_10V4Z @ R1115 1

2
2
C1404

AO4466_SO8 3 4 SYSON# SUSP

SHDN BYP 40 SYSON# SUSP 40

C1407
330K_0402_5% 10K_0402_5%
2 1 G916-390T1UF_SOT23-5
2

3
2
22,31 SLP_S4# 1 2
Q13A Q13B
RUNON_1.5VS R1116 R1117
0_0402_5% 100K_0402_1% 2 5 SUSP#
9,31,39 SYSON SUSP# 31,38
1

4
R1113
1K_0402_5%
1

D
2

SUSP 2
G 1
Q44
S
VOUT=1.25(1+R912/R913)
3

2N7002_SOT23-3 C1406
0.1U_0402_25V4K
2 VOUT=1.25(1+100k/215k)=1.83V

H1 H2 H3 H4 H5 H6 H7
H_4P0 H_3P1N H_4P0 H_4P0 H_4P0 H_1P1
Discharge circuit

1
H_3P1X3P6N
+5VS +3VS +1.5VS +VCCP +1.5V +0.75VS
B B
H12 H16 H17 H18
1

1
H_3P0 H_3P0 H_3P0
R641 R642 R644 R645 R643 R646

470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

1
H_4P0X5P0N
2

2
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
H19 H20 H21 H23
6

3
FM1 FM2 FM3 FM4 H_3P0 H_3P0 H_3P0 H_3P0
Q6A Q6B Q9A Q9B Q12A Q12B 1 1 1 1
SUSP 2 SUSP 5 SUSP 2 SUSP 5 SYSON# 2 SUSP 5

1
1

Be used for Stand off. 11/06 H22

H_3P0

1
Delete H8/9/10/11/13/14/15/22 for layout demand. 11/28

A A

Add H22. 1202

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina UMA LA6121P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 33 of 46
5 4 3 2 1
 A B C D

VIN
ADPIN VIN
PD3

2
PL1
SMB3025500YA_2P
BATT+ 2 1 PD2
LL4148_LL34-2
DC_IN_S1 1 2 LL4148_LL34-2

1
PJPDC1

1
1

1
1 4 PR9 PR13 1
4 PC2 PC5 PC3 PC4 68_1206_5% 68_1206_5%
3 3
2 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K

2
2 N1 PQ1
1

2
1
@ SINGA_4TRJWT-R2513 3 1
VS

1
PR15 PC13 PC9
100K_0402_1% 0.22U_0603_25V7K 0.1U_0603_25V7K

2
PR14 TP0610K-T1-E3_SOT23-3

2
22K_0402_1%
1 2

1
2 PQ309
31 EC_ON G SSM3K7002FU_SC70-3

2
S

3
PR296
10K_0402_5%

1
PJP602
1 2
2 +CHGRTC +3VLP 2

PAD-OPEN 3x3m
BATT++ PL25
DC040003600 HCB4532KF-800T90_1812 BATT+
1 2

PJP3
1 1 1 2 +3VL
2 2
3 PR33 @ PR27
PH1 under CPU botten side :

1000P_0402_50V7K

1000P_0402_50V7K
3 100K_0402_1%
4 1 2 CPU thermal protection at 92 degree C

0.01U_0402_50V7K
4 +3VALW

1
5 5

1
PC17

PC18

PC19
@ 100K_0402_1%
6 6
7
Recovery at 70 degree C

2
7
2
1K_0402_1%

2
8
2

PR28

9 9
10
PH4 near main Battery CONN : Reverse
G1
G2 11 PR34
1K_0402_1%
BAT. thermal protection at 90 degree C
1

SUYIN_200275MR009G180ZR
Recovery at 53 degree C
1

VL
100_0402_1%
1

1
100_0402_1%
PR36

PR32

2
3 3

1
PR40
2

PC20 22K_0402_1%
0.1U_0603_25V7K

2
PR42

1
10K_0402_1%
SMB_EC_CK1 31

2
SMB_EC_DA1 31
PR43

1
14K_0402_1%
PU3
1 2 +3VL 1 8

1
VCC TMSNS1

1
PR31 2 7
GND RHYST1
6.49K_0402_1% P/N:SD034140280 PH1
1K_0402_1%
1

3 6 100K_0402_1%_NCP15WF104F03RC
OT1 TMSNS2
PR35

2
1
4 OT2 RHYST2 5
@ PR41
37 MAINPWON G718TM1U_SOT23-8 47K_0402_1%
2

BATT_TEMP 31

1
PH4
@ 100K_0402_1%_NCP15WF104F03RC

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP

www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 34 of 46
A B C D
 A B C D

PR8
A
1K_1206_5% A

1 2

PQ7
PR19 TP0610K-T1-E3_SOT23-3
PD1
VIN 1K_1206_5%
2 1 1 2 3 1
B+
PR24
LL4148_LL34-2 1K_1206_5%
1 2

100K_0402_5%

100K_0402_5%
1

1
PR20
PR38

PR23
1K_1206_5%

2
1 2

1
PR37 ACIN
1

100K_0402_5%
PQ4 Precharge detector
DTC115EUA_SC70-3
Min. typ. Max.

1 2
31,36 ACOFF 2
PQ3 H-->L 14.589V 14.84V 15.243V
DTC115EUA_SC70-3
L-->H 15.562V 15.97V 16.388V
B B
2
3

BATT ONLY
Precharge detector
3

Min. typ. Max.

H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

PR26 B+
VL 2.2M_0402_5%
2 1

N1 1
0.01U_0402_25V7K

1 PR21
PC161

511K_0402_1%
1

PR22
2

100K_0402_1% 2 N1
2

PD4

8
2 5
P

37 EN0_TRIP +
1 7 3

P
O +
36 ACON
0.01U_0402_25V7K

3 - 6 1 O
G

C C

LM393DR_SO8 2
-

G
1

PC15

RB715F_SOT323-3 PU12B PR39 LM393DR_SO8

4
1

150K_0402_1% PU12A

4
PC14 PC16 PR25
2

0.1U_0603_25V7K 1000P_0402_50V7K 255K_0402_1%

2

PRG++ 2

PR29 PR30
1

34K_0402_1% D 47K_0402_5%
2 1 PQ5
2 2 1
36 6251VREF SSM3K7002FU_SC70-3
G PACIN 36
1

S
3

PQ6
1

DTC115EUA_SC70-3
PR79
10K_0402_5% 2 +5VALW
2

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/2/6 Deciphered Date 2010/2/6 Title
DCIN & DETECTOR

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5442P
Date: Thursday, April 15, 2010 Sheet 35 of 46
A B C D
 4 3 2 1

D D

CP = 85%*Iada (Acer criteria); CP = 2.95A

ADP_I = 19.9*Iadapter*Rsense
Iada=0~3.42A(65W)
B+
PQ14 PQ15 PQ16
P2
AO4407A_SO8 S TR P1403EVG_SO8
P3 PR70 0.02_1206_1%
B+ CHG_B+
AO4407A_SO8
PL2
VIN 8 1 1 8 FBMA-L11-321611-121LMA_2 1 8
7 2 2 7 1 4 1 2 2 7
6 3 3 6 3 6
5 5 2 3 CSIN 5

CSIP

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_25V7K
0.1U_0603_25V7K
4

4
1

1
PC44

PC45
VIN
1

6251VDD PR73

PC46

PC47
5600P_0402_25V7K
PR71 47K_0402_1%

191K_0402_1%
0.1U_0603_25V7K

2
1

2
47K_0402_1% PR72 1 Structure>
<BOM 2

2.2U_0603_6.3V6K
VIN

1
PC48

200K_0402_1%

PC49

PC50

1
2

2
PD9

PR221

2
1SS355TE-17_SOD323-2

2
PD5 PR76 1 2 ACOFF

1000P_0402_25V8J

2
3

PQ19 ACSETIN RB751V-40_SOD323-2 ACSETIN 10K_0402_1%

DTA144EUA_SC70-3 PD11

1 1

1
1SS355TE-17_SOD323-2

PC214

14.3K_0402_1%
C C

1
2 1 2 PR77

10_1206_5%
200K_0402_1%

PR222

PR223
2
PR78 1 2 VIN
10K_0402_5%

1
2 1 PU5 PC67

2
31 FSTCHG
1

0.1U_0603_25V7K
1

1 2 1 24 DCIN 2 1 PD12

1
PC51 VDD DCIN PQ22 1SS355TE-17_SOD323-2

100K_0402_1%
.1U_0402_16V7K DTC115EUA_SC70-3 2 1 2
ACPRN

PR80
2 2 23
PQ20 ACSET ACPRN PR82

1
DTC115EUA_SC70-3 20_0603_5% D

0.1U_0603_25V7K
2

5
6
7
8

1
6251_EN 3 22 1 2 CSON 2 PACIN
PQ23

3
1

2
D @ PC53 EN CSON PC55 PQ25 SSM3K7002FU_SC70-3

PC52
G
3

2 PQ24 PR81 680P_0402_50V7K 0.047U_0603_16V7K AO4466_SO8 S

3
G SSM3K7002FU_SC70-3 150K_0402_1% CSON 1 2 4 21 1 2 CSOP

1
CELLS CSOP PR83
S
3

PC56 6800P_0402_25V7K 20_0603_5% 4

352
PACIN_1

1 2 5 20 2 1
ICOMP CSIN

2
PR84 20_0603_5%
PC57 PR85 10K_0402_1% PC58 0.1U_0603_25V7K
1 2 1 2 6 19 1 2

3
2
1
PR87 VCOMP CSIP PR86 PL5 PR88 0.02_1206_1%
0.01U_0402_25V7K 1 2 100_0402_1% 2.2_0603_5% S COIL 10UH +-30% SIL1045RA-100PF 4.5A BATT+
PR89 PC59 1 2 7 18 28.2
LX_CHG 1 2 CHG 1 4
1

22K_0402_5% D 100P_0402_50V8J ICM PHASE

PACIN 1 2 2 PQ26 @ 2 3
35 PACIN

1
G SSM3K7002FU_SC70-3 31 ADP_I 35 6251VREF 8 17 DH_CHG

5
6
7
8
PC60 VREF UGATE PR92 PC61 PR90
S
3

PR91 1 2 2.2_0603_5% 0.1U_0603_25V7K PQ27 4.7_1206_5%

150K_0402_1% 9 16 BST_CHG 1 2 BST_CHGA 2 1 AO4468L_SO8

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
CHLIM BOOT

1
ACON 2 1 .1U_0402_16V7K
35 ACON

1 2
31 IREF

1
PD13

PC62

PC63

PC68
0.01U_0402_25V7K

6251aclim 10 15 6251VDDP RB751V-40_SOD323-2 4

ACLIM VDDP
1

PC65

2
1

PQ28 PR93 26251VDD

PC64

1 680P_0402_50V7K

2
DTC115EUA_SC70-3 140K_0402_1% 11 14 DL_CHG

2
B
VADJ LGATE PR94 B
2

3
2
1
ACOFF 2 4.7_0603_5%
31,35 ACOFF
2

12 13 PC66

1
GND PGND 4.7U_0805_6.3V6K

6251VREF 1 2 ISL6251AHAZ-T_QSOP24
3

2.37K_0402_1%
1

PR95
11.5K_0402_1%
PR96
2

CP mode
Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05) PR97
18.2K_0402_1%
Vaclim=2.39*((11.5K//152K)/((2.37K//152K)+(11.5K//152K))) 1 2
31 CHGVADJ 6251VDD

PR224
1

10K_0402_1%
1

1
PR99 1 2 ACIN 31
31.6K_0402_1% PR225
47K_0402_1% PR226
10K_0402_1%
2

PACIN
2

1 2

CHGVADJ CV mode C

1
ACPRN 2 PQ38
B PR227
CC=0.6~4.48A E 20K_0402_1%
0V 4V per cell
3

MMBT3904W_SOT323-3
IREF=0.7224*Icharge
2

1.882V 4.2V per cell

IREF=0.43V~3.24V
A A

3.294V 4.35V per cell

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/2/6 Deciphered Date 2010/2/6 Title
- CHARGER

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS ULV 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 36 of 46
4 3 2 1
 A B C D E

2VREF_51125

1U_0603_10V6K

1
PC302

2
1 1

PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2

PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805

ENTRIP1
1 2 +3VLP

ENTRIP2
PR305 PR306
2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6
4.7U_0805_25V6-K

100K_0402_1% 130K +-1% 0402

1

1
PC316

PC301

PC303

PC317
1 2 1 2

10U_1206_25V6M
2200P_0402_50V7K

1
PC304

PC305
4.7U_0805_10V6K
2

2
PQ301

2
6

5
6
7
8
PU301

PC306

1
1 8 UG1_3V

ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
VREF
D1 1G PQ302
2 D1 1S/2D 7 25 P PAD
3 6 AO4466_SO8

2
G2 1S/2D
4 S2 1S/2D 5
7 VO2 VO1 24 4

UG1_5V
2 AO4932_2N_SO8 PR308 PC308 2
8 VREG3 PGOOD 23
PR307 2.2_0402_5% 0.1U_0402_10V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
0_0402_5% VBST2 VBST1
PL302 PC307 UG_3V 10 21 UG_5V PL303
3.3UH_SIQB74B-4R7PF_5.9A_20% 0.1U_0402_10V7K DRVH2 DRVH1 10UH +-30% SIL1045RA-100PF 4.5A
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1

5
6
7
8
LG_3V 12 19 LG_5V +5VALWP
DRVL2 DRVL1

SKIPSEL
PQ304

4.7_1206_5%

4.7_1206_5%
VREG5

150U_D_6.3VM
<BOM Structure>
1

1
VCLK
AO4712_SO8 1

GND
B++

EN0

VIN
+ PR309
PC309
220U_6.3VM_R15

+
PR315

PR316

PC310
1 2 4
499K_0402_1%

13

14

15

16

17

18
2 TPS51125RGER_QFN24_4X4
2

2
OCP= 4.8A 2
35 EN0_TRIP

1
680P_0603_50V7K

680P_0603_50V7K

3
2
1
Imax= 3A VL

100K_0402_1%
1

1
PC314

PC315
Ipeak= 4.3A OCP= 6.8A
+3VALW

PR311
2

2
1
F=305KHz Imax= 4.6A

PC311
10U_0805_10V6K

1
Rdsonmax= 19.6m Ipeak= 6.534A

2
PR504
@ 10K_0402_5% F=245KHz
ENTRIP1 ENTRIP2

1
PR318 Rdsonmax= 15m

2
3 B++ 3
1 2

0.1U_0603_25V7K
0_0402_5% R_EC_RSMRST# 22
ENTRIP1

2
PC312
2VREF_51125
D D
1

PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
+5VL
3

VL
PJP304
2 1
1 2
VL PJP302 PAD-OPEN 2x2m
PR313 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
+5VALWP
100K_0402_5%
+3VLP +3VL
PAD-OPEN 4x4m
PJP301
1

PJP303
2 1
PQ307 1 2 +3VALW (3A,120mils ,Via NO.= 6)
DTC115EUA_SC70-3 MAINPWON 34 +3VALWP PAD-OPEN 2x2m
PR605
PAD-OPEN 4x4m
2 1 2
VS
100K_0402_1%
0.1U_0603_25V7K
1

1
3

PC54

4 42.2K_0402_1% 4
2

PR314
@ Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 37 of 46

A B
www.vinafix.vn C D E
 A B C D

1 1

PR401
0_0402_5%
1 2 PL401
31,33 SUSP#
HCB1608KF-121T30_0603
1

@ PR410 1.05V_B+ 1 2 B+
10K_0402_5% PC401 @

2200P_0402_50V7K
0.1U_0402_25V6

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1000P_0402_50V7K
2

5
6
7
8

1
+5VALW
2

PC406

PC414

PC403

PC404

PC405
BST_1.05V
1 2 BST1_1.05V1 2 @ 680P_0402_50V7K

2
PR402
2.2_0603_5% PC402
2

0.1U_0402_10V7K 4
PR403 PQ401

15

14
1
100_0603_1% PU401 AO4466_SO8
PR404

EN/DEM

NC

BOOT
2 255K_0402_1% 2
PR411
1

3
2
1
1 2 2 13 DH_1.05V 1 2 PL402
TON UGATE 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
PR405 0_0402_5%
+1.05V_VCCP 2 1 3 12 LX_1.05V 1 2 +1.05V_VCCP
VOUT PHASE
0_0402_5%

1
4 VDD CS 11 1 2

5
6
7
8
PR406 PR407
1
5 10 +5VALW 17.4K +-1% 0402 PQ402 4.7_1206_5%

330U_2.5V_M
FB VDDP +
PC409

PC408
4.7U_0603_6.3V6M

6 9 PC415 FDS6690AS-G_SO8

2 2
PGOOD LGATE

1
PGND
4.7U_0805_10V6K

GND
2
4
2

PC412

2
RT8209BGQW_WQFN14_3P5X3P5 220P_0603_50V8J
7

1
3
2
1
+1.05V_VCCP DL_1.05V
1 2

PR408
3.74K_0402_1%
1

PR409
9.31K_0402_1%
2

3 3

PJP401
+1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.=12)
PAD-OPEN 4x4m
PJP402
1 2

PAD-OPEN 4x4m
PJP403
1 2

PAD-OPEN 4x4m

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05V_VCCP

www.vinafix.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 38 of 46
A B C D
 5 4 3 2 1

D D

1.5VP_B+ B+
PR521 PL502
2 1 HCB1608KF-121T30_0603
9,31,33 SYSON 2 1
0_0402_5%

1
PC524 @
1000P_0402_50V7K

2
PC511

4.7U_0805_25V6-K
0.1U_0402_10V7K

2200P_0402_50V7K

0.1U_0402_25V6
4.7U_0805_25V6-K
BST_1.5V 1 2 1 2

1
PR510

1
2.2_0603_5%

PC516
5
6
7
8

1
PC504

PC505

PC521
15

14

2
1
PU502

2
PR523 PR508

EN/DEM

NC

BOOT

2
255K_0402_1% 0_0402_5%
1 2 2 13 UG_1.5V 1 2
C TON UGATE UG1_1.5V C
4
PR522 +1.5VP 1 2 3 12 LX_1.5V PQ501
100_0603_1% PR520 0_0402_5% VOUT PHASE 14.7K +-1% 0402 AO4466_SO8
+5VALW +5VALW 1 2 4 11 1 2
VDD CS PR515 +1.5VP

3
2
1
+1.5VP 1 2 5 10 +5VALW +5VALW PL501
FB VDDP 1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%

1
PR501 6 9 LG_1.5V 1 2
PGOOD LGATE

PGND
PC522 9.76K_0402_1% PC523

GND
4.7U_0603_6.3V6M 4.7U_0805_10V6K
2

5
6
7
8
RT8209BGQW_WQFN14_3P5X3P5

8
1

1
1
PR502 PR516

330U_2.5V_M
4.7U_0603_6.3V6M
1
9.31K_0402_1% @ 4.7_1206_5% +

PC510

PC508
4

1 2

2
PQ503 2

AO4712_SO8
+1.5V PC519 @

3
2
1
680P_0603_50V7K

1
PR503
@ 10K_0402_5%
OCP= 16.05A
B B

2
Imax= 9.23A
Ipeak=13.188A

DDR3_SM_PWROK 9 F=315KHz
Rdsonmax= 5.6m

PJP501
1 2

PAD-OPEN 4x4m

PJP502
+1.5VP 1 2 +1.5V (8A,320mils ,Via NO.= 16)
PAD-OPEN 4x4m

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP
Size Document Number Rev

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 39 of 46
5 4 3 2 1
 5 4 3 2 1

D D

+1.5V

PU601
1 VIN VCNTL 6 +5VALW

@10U_0805_10V4Z
2 GND NC 5

PC602

1
PC601 3 7
VREF NC

1
10U_0805_10V4Z

2
PR601 PC603
4 VOUT NC 8
1K_0402_1% 1U_0603_16V6K

2
9

2
TP
G2992F1U_SO8

33 SYSON# 1 2
@ PR602
+0.75VSP

.1U_0402_16V7K
1
0_0402_5%
PQ601

PC604
SSM3K7002FU_SC70-3 PR603

1
D
1K_0402_1%
1 2 2 PC605
33 SUSP

2
PR604 G 10U_0805_6.3V6M

2
0_0402_5% S

3
1
C PC606 C

2
@ .1U_0402_16V7K

PJP601

+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)

PAD-OPEN 3x3m

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, April 15, 2010 Sheet 40 of 46
5 4 3 2 1

www.vinafix.vn
 5 4 3 2 1

+3VS

@ 10K_0402_5%
1.91K_0402_1%
1

1
PR119

PR120
2

2
17,22 VGATE

17 CLK_ENABLE# 1 2

9,22
DPRSLPVR
PR121 +CPU_B+ PL12
@ 0_0402_5% +3VS +5VS HCB4532KF-800T90_1812

31
VR_ON

PC247
1 2 B+

PMON
D D

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
1 1

1
0_0402_5%

0_0402_5%

1
+ +

PR124

PR235

PC94

PC95

PC96

68U_25V_M_R0.44

PC248
68U_25V_M_R0.44
2

2
@ 2 2

0_0402_5%
1CPU_VREF

499_0402_1%

5
0_0402_5%
0_0402_5%

0_0402_5%
124K_0402_1%
PQ32

2
S TR AON6410 1N DFN-8

1
1

1
@ 4

CPU_DPRSLPVR
CPU_CLK_EN#
CPU_VR_ON 2

1
CPU_TRIPSEL
CPU_OSRSEL

CPU_TONSEL

PR122
PR127

PR128
CPU_V5FILT

2
CPU_ISLEW
PL13

2
PR123

PR125

PR126
2 1 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
PC103 1 2 +VCC_CORE
1U_0402_6.3V6K

1
+5VS PR135

S TR AON6716L 1N DFN

S TR AON6716L 1N DFN

1
6.8_1206_5%

17.8K_0402_1%
41

40

39

38

37

36

35

34

33

32

31

PR129
1CPU1_SNB
2
CPU_VREF
1 2

GND

V5FILT

ISLEW

OSRSEL

TONSEL

TRIPSEL

PWRMON

VR_ON

CLK_EN#

DPRSLPVR

PGOOD

2
PR130 PD17 4 4 PR131
5.11K_0402_1% 1SS355_SOD323-2 69.8K_0402_1%

2
1 2CPU_DROOP 1 DROOP DRVH1 30 UGATE_CPU1 1 2
PC98 68P_0402_50V8J
PH2

PQ31

PQ33
CPU_CSP1 2 1 1 2CPU_VREF 2 29 BOOT_CPU1
1 PR133 2BOOT_CPU1-1
1 2 PC101

3
2
1

3
2
1
VREF VBST
PR132 470_0402_1% PC99 0.22U_0603_10V7K 0_0603_5% PC100 680P_0603_50V7K 1 2CPU_SN-1
1 2

2
2

3 GND LL1 28 PHASE_CPU1 0.22U_0603_10V7K PR134

C C

CPU_CSN1
CPU_CSP1
PC102 28.7K_0402_1% 100K_0402_1%_NCP15WF104F03RC
100P_0402_50V8J 1 2 CPU_CSP1-2 4 27 LGATE_CPU1 +CPU_B+ 1 2
1

CPU_CSN1 2 PC104 33P_0402_50V8K CSP1 DRVL1 PC105

1 +5VS

5
PR136 470_0402_1% 2 CPU_CSN1-1 0.033U_0402_16V7K

10U_1206_25V6M

10U_1206_25V6M
1 5 26 1 2

S TR AON6410 1N DFN-8
CSN1 V5IN

1
CPU_CSN2 2 1 PC106 33P_0402_50V8K PC107 10U_0603_6.3V6M

PC110
PR137 470_0402_1% 1 2 CPU_CSN2-1 6 CSN2
PU11
PGND 25
2

PC109
PC108 33P_0402_50V8K TPS51620RHAR_QFN40_6X6

2
PC111 1 2 CPU_CSP2-2 7 24 LGATE_CPU2

2
100P_0402_50V8J PC112 33P_0402_50V8K CSP2 DRVL2
4
1

PQ37
CPU_CSP2 2 1 CPU_GNDSNS 8 23 PHASE_CPU2
PR138 470_0402_1% GNDSNS LL2
CPU_VSNS 9 22 BOOT_CPU2
1 PR159 2BOOT_CPU2-1
1 2 PL14
VSNS VBST2 0_0603_5% PC113 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
CPU_THERM 21 UGATE_CPU2 0.22U_0603_10V7K
DPRSTP#

10 THERM DRVH2 1 2
1

VR_TT#

1
0_0402_5%

0_0402_5%

1 2
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

+5VS
1

1
PR140

PR141

PD16 PR142

17.8K_0402_1%
PR144
1SS355_SOD323-2 6.8_1206_5%
2

11

12

13

14

15

16

17

18

19

20

S TR AON6716L 1N DFN

S TR AON6716L 1N DFN

1CPU2_SNB
PR143

2
20K_0402_1% PR145
1CPU_DPRSTP#

69.8K_0402_1%
2

2
VID6

VID5

VID4

VID3

VID2

VID1

VID0
PSI#

4 4 1 2
PH3
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

1 2CPU_SN-2
1 2

PQ35

PQ36
PC114 PR148

3
2
1

3
2
1

2
1

CPU_CSN2
CPU_CSP2
680P_0603_50V7K 28.7K_0402_1% 100K_0402_1%_NCP15WF104F03RC
1 2
PC115
0.033U_0402_16V7K
PR149

PR150

PR151

PR152

PR153

PR154

PR155

PR157

PR158

B B
2

1
7

7
VSSSENSE

VCCSENSE

7,9,217

CPU_VID37

CPU_VID27

CPU_VID17

CPU_VID07

7
H_PSI#
H_DPRSTP#

CPU_VID6

CPU_VID5

CPU_VID4

A A

Compal Electronics, Inc.

Title
+CPU_CORE

www.vinafix.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Thursday, April 15, 2010 Sheet 41 of 46
5 4 3 2 1
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Version Change List ( P. I. R. List ) for Power Circuit

Item Page# Reason for change Description phase modify Rev.

delete: pu101 and Support Components.

D 1 36 change charge IC for cost down change charge IC from TPS24740 to ISL6251 DVT D
add: PU5 and Support Components.

35 Due to ISL6251 can't support pre-charge Add pre-charge and Vin detector function DVT add PU12
2
and Vin detector function
PC302 from 0.22U change to 1U
3 37 for common design PC302 change to 1U; PC306 change to 4.7U DVT
PC306 from 10U change to 4.7U
4 34 Change CPU OTP IC for Cost down CPU OTP IC from LM358 change to G718 DVT delete: PU1 and Support Components
PH2,PH3 size from 0603 change to 0402
5 41 PH2,PH3 size from 0603 change to 0402 DVT from SL210021F20 change to SL200000V00
for cost down.
PC510 size from 0805 change to 0603
6 39 PC510 size from 0805 change to 0603 DVT from SE093475K80 change to SE107475M80
for Cost down
for battery can not be charging full issue
7 31 CHGVADJ signal from EC 108pin change to 72pin DVT CHGVADJ signal from EC 108pin change to 72pin
(notes issue number: ACIC009)
8 41 change load line voltage change PR130 from 4.02K change to 5.11K DVT PR130 from SD034402180 change to SD028511100
C C
9 41 COST DOWN Delete CPU_core L-SIDE MOS PQ31 PQ35 DVT delete: PQ31 PQ35

10 38 COST DOWN Change PL402 from 1U to 1.8U DVT From SH000008V80 change to SH000008U80

11 41 COST DOWN Change CPU_core L-side DVT From SB00000GL00 change to SB00000HR00

12 34/35 COST DOWN Change PD1/PD2/PD3 DVT From SC11N414880 change to SC1000001Y80

13 36 COST DOWN Change PD13 DVT From SC1B751V010 change to SCS00000Z00

14 41 COST DOWN Change PL13/PL14 DVT From SH00000F000 change to SH000005680

15 37 COST DOWN Change PQ304 DVT From SB000004J80 change to SB00000AJ00

16 38 COST DOWN Change PQ401/PQ402 DVT PQ401 From SB00000BO00 change to SB00000CG00
PQ402 From SB000009F80 change to SB00000AJ00
B B

17 39 COST DOWN Change PQ501/PQ503 DVT PQ501 From SB00000BO00 change to SB00000CG00
PQ503 From SB000009F80 change to SB00000AJ00
18 34 COST DOWN Remove PU2;Connect +3VLP to +CHGRTC DVT Remove SA009200010

19 34 design change Add PQ1/PQ309 and support circuit DVT Add PQ1:SB906100210 PQ309:SB000009610

20 34 change PU3 support circuit change from EN0_TRIP to MAINPWON DVT change from EN0_TRIP to mainpwon

21 35 cost down delete VIN detector circuit DVT use ISL6251 VIN detector function

22 35 change RTCVREF to 62521VREF and PR21 change from 499k to 511k DVT PR21 change from SD034499380 to SD034511300
support circuit PR25 change from 499k to 255k PR25 change from SD034499380 to SD034255300
PR39 change from 191k to 150k PR39 change from SD034191380 to SD028150300
change RTCVREF to 62521VREF
A 23 35,36 COST DOWN Change PQ5/PQ23/PQ24/PQ26 DVT From SB502060000 change to SB000009610 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 42 of 46
5 4 3 2 1
 A B C D E

Version Change List ( P. I. R. List ) for Power Circuit

Item Page# Reason for change Description phase modify Rev.

1 PQ15 from SB00000DL00 to SB944070010 1

24 36 COST DOWN change PQ15 to AO4407L DVT

25 36 change PQ27 to AO4468L DVT change PQ27 from SB00000CG00 to

COST DOWN
SB000009510
26 36 for common design change ISL6251 ACIN function DVT change ISL6251 ACIN function

27 37 COST DOWN change PL303 to SH000002L80 DVT PL303 from SH162100M10 to SH000002L80

28 37 COST DOWN change +3/5VALW enable circuit DVT change +3/5VALW enable circuit

29 38 COST DOWN change PQ402 to FDS6690AS DVT PQ402 from SB00000AJ00 to SB000004J10

30 38 change +1.05V_VCCP OCP setting change PR406 from 13.7K to 14.7K DVT PR406 from SD034137200 to SD034147200

31 38 COST DOWN change PC408 from 220U to 330U DVT PC408 from SGA20221150 to SF000002Z00
2 2

32 39 COST DOWN change PL501 from 1UH to 2.2UH DVT PL501 from SH000008V80 to SH00000FD10

33 39 COST DOWN Change PC508 from Tantalum CAP to Aluminum DVT PC508 from SGA00000W00 to SF000002Z00
CAP
34 39 change +1.5VP OCP setting change PR515 from 8.87K to 14.7K DVT PR515 from SD034887180 to SD034147200

35 41 COST DOWN Change PQ32,PQ37 from TPCA8023 to TPCA8030 DVT PQ32,PQ37 from SB00000CK00 to SB00000HL00

36 42 shortage issue Change PR406 from 14.7K to 17.4K PVT PR406 from SD03414700 to SD03417400

37 43 Shortage issue Change PQ15 from AO4407L to S TR P1403 PVT PQ15 from SB00000DL00 to SB00000DM00

38 44 COST DOWN cause CPU hang up issue ADD PQ31,PQ35 PVT ADD PQ31,PQ35

39 Pre-MP
36 for 030 common design Change PR91, PR93, PR97 PR91,PR93,PR97 change to 150K,140K,18.2K
3 3

TPCA8030-H change to AON6410

40 41 For shortage issue Change CPU_CORE H/L side MOS Pre-MP TPCA8036-H change to AON6716L

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/02 Deciphered Date 2008/08/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-2

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 43 of 46
A B C D E
 5 4 3 2 1

Item Fixed Issue (Reason for change) PAGE Modify List Date Phase

1 Keyboard can't work. 31 Change R584/R599 pull up PWR from +3valw to +3VL 2009/12/17 DVT

2 LCD can't display. 32 Add (R2406) Lid_sw# pull up to +3VL with 100K. 2009/12/17 DVT

3 Follow Vendor's datasheet. 25 Change Lan chip pin15 to pull down with 10K. 2009/12/17 DVT
D D

4 Follow ID demand. 32 Change Wireless/BT from 2 colore to single colore(Amber) 2010/01/04 DVT

5 To meet KBC PWR plane 26 Change KILL_SW# pull high PWR plane to +3VL 2010/01/04 DVT

6 Follow ID. 31 Delete wow audio/video/dj on EC. 2010/01/04 DVT

7 Follow ME demand. 32 Change JP60 to 8pin. 2010/01/04 DVT

8 17 Delete R123 from BOM 2010/01/04 DVT

9 Kill switch is HW part. 26 Delete CONN@ from schematics. 2010/01/04 DVT

10 SYSON should be 3V. 31 Change R213(8.2K) to CAP(C1415 1U). 2010/01/04 DVT

11 Follow LAN datasheet. 17/25 Delete R191 from Bom,and add R467 to pull up LAN_CLKREQ# with 10k. 2010/01/04 DVT
C C

12 6 Change to 3pin FAN. 2010/01/04 DVT

13 Cost down. 28 Change to 2pin SPK, and change AMP to SA00003X300 2010/01/04 DVT

14 EC common design. 31 add FAN_SPEED at EC pin28, and Kill switch change to pin26. 2010/01/04 DVT

15 Follow panel PWR sequence. 19 Delete C232 from BOM. 2010/01/08 DVT

16 26 Add ESD D8 diode on Kill switch. 2010/01/11 DVT

17 Follow EC common design. 26/31 Change WL_OFF# to EC pin106 control. 2010/01/11 DVT

18 Follow EC common design. 29/31 Change BT_OFF to EC pin99 control. 2010/01/11 DVT

19 Key part demand. 29/26 Change to 8pin BT module. 2010/01/11 DVT

B B

20 For debug. 32 Add PWR button SW on M/B. 2010/01/13 DVT

21 Change WL/BT LED to be always light when WL/BT work . 31/32 Change WL_BT_LED# contral to EC pin86. 2010/01/14 DVT

22 follow PWR's suggestion. 31 Change VCTRL from EC Pin108 to 68 2010/01/14 DVT

23 Follow EC's request. 31 change EC pin108 as EC_SEL. 2010/01/18 DVT

24 Cost down. change C150/C135 to SF000002000. change C131/3200/94/98/77/115/458 to SF000001500. 2010/01/18 DVT

25 Follow PWR net name 31 2010/01/19 DVT

change VTRL to CHGVADJ on EC pin68.
26 Follow EC common design. 31 Change CHGVADJ from EC pin68 to pin72 2010/01/20 DVT

27 Follow EC common design. 29/31 Add R602/R603/Q14. change BT_OFF to BT_OFF#. 2010/01/20 DVT
A A

28 It is convenient for EC debug. 26/31 EC-TX and EC-RX should connect to WL connector(JP7) 49 pin and 51 pin. 2010/01/20 DVT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR 3

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 44 of 46
5 4 3 2 1
 5 4 3 2 1

Item Fixed Issue (Reason for change) PAGE Modify List Date Phase

1 no use ADP_ID. 31 delete location R592(10K). 2010/01/20 DVT

2 no use CIR_IN. 31 delete location R720(10K). 2010/01/20 DVT

3 no use TP_BTN#. 31 delete location R587(10K). 2010/01/20 DVT

D D

4 Modify Gain to 10db. 28 Change C504 to 0.1U. 2010/01/21 DVT

5 Modify Gain to 10db. 28 Change R436/R437 to 30K. 2010/01/21 DVT

6 Modify Gain to 10db. 28 Change R427/R428 to 10K. 2010/01/21 DVT

Change L2/L3/L4 to SM01000DS00. Change C228/C229/230 to SE07122AC80.
7 Cost down. 18 2010/01/22 DVT
Install C225/C226/C227 with SE07122AC80. Modify as KSWAA.
8 Modify Gain to 10db. 28 Change C504 back to 0.22U. 2010/01/23 DVT

9 Modify Gain to 10db. 28 Change R429 from 10K to 5K(SD00000HN80). 2010/01/23 DVT

10 Cost down. 19/29 Change Q7/Q105 from SB923010020 to SB934130000, modify as KSWAA. 2010/01/23 DVT

11 Cost down. 28 Change C66/C1450 from SE000004880 to SE053106Z80, 2010/01/23 DVT

C C

12 Cost down. 26/31 Delete R699,R700,R701,R702,R703,R443 (SD028000080) 2010/01/23 DVT

13 Modify the lighteness of LED3. 32 Change R151 from 453ohm to 300ohm (SD028300000) 2010/01/25 DVT

14 28 Uninstall C1492/C1493 (SE071470J80) 2010/01/25 DVT

15 28 Add Location R1281/R1282 at SPK side.(SD013000080) 2010/01/26 DVT

16 Cost down and modify the lighteness of LED. 32 Change R146 from SD034453080 to SD028300000(300ohm) 2010/01/26 DVT

17 Modify the lighteness of LED1/D53. 32 Change R1098/R1101 fromSD028820080 to SD028220080 (220ohm) 2010/01/26 DVT

18 Follow WLAN+BT datasheet. 26 Connect JP7 Pin37/43 to GND. 2010/01/26 DVT

19 17 Delete Location CLRP1. 2010/01/28 DVT

B B

20 32 Add ESD diode D31@ at ON/OFFBTN&ON/OFFBTN_LED# 2010/01/28 DVT

21 29 Uninstall R603. 2010/01/28 DVT

22 18 Change NET C_RED/GRN/BLU to M_RED/GREEN/BLUE. 2010/01/28 DVT

23 Follow EC common desing. 26 Add R1094(SD028100380) to pull down EC_TX with 100kohm. 2010/01/28 DVT

24 Cost down, follow PWR's demand. 8 Change C41/C42@/C43/C44 to SGA19331D10. 2010/01/29 DVT

25 Follow EC common design. 31 uninstall R590. 2010/02/01 DVT

26 Follow EC's suggestion. 22 Add location R347, and uninstall R334. 2010/02/01 DVT

27 EMI demand. 18/19/32 install D31/C223/C224/C302/303. 2010/02/01 DVT

A A

28 19/28 Change Q7/C66 back to SB923010020/SE000004880. 2010/02/02 DVT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR 3

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 45 of 46
5 4 3 2 1
 5 4 3 2 1

Item Fixed Issue (Reason for change) PAGE Modify List Date Phase

1 White screen issue. 19 Install R245(10K)-->SD028100280. 2010/03/05 PVT

2 19 Reserve location C71 for BKOFF# 2010/03/05 PVT

3 31 Change R1131 from 22ohm SD028220A80 to 0ohm SD028000080 2010/03/05 PVT

D D

4 Modify the lightness of LED2 32 Modify R120 from SD028220080(220ohm) to SD028100080(100ohm). 2010/03/15 PVT

5 Modify the lightness of LED2 32 Modify R146 from SD028300000(300ohm) to SD028120000(120ohm). 2010/03/15 PVT

6 Modify the lightness of LED1/D53 32 Modify R1098/R1101 from SD028220080(220ohm) to SD00000LK80(90.9ohm). 2010/03/15 PVT

7 Modify the lightness of LED3 32 Modify R151 from SD028300000(300ohm) to SD028150000(150ohm). 2010/03/15 PVT

8 SPK noise issue. 28 Modify R436/r437 from SD014300280(30Kohm) to SD014150280(15Kohm). 2010/03/15 PVT

9 Avoid MIC noise issue. 28 Reserve C304 for +MIC1_VREFO 2010/03/15 PVT

10 Add BT_OFF# pull high to +3VS. 29 Install R603(10K)-->SD028100280. 2010/03/24 Pre_MP

11 Can't disable BT for combo card. 26 Reserve R438 to connect BT_OFF# with JP7 pin5. 2010/03/24 Pre_MP
C C

12 Reserver ICH_susclk for EC's CLK IN. 22/31 Delete T58 and reserver R592. 2010/03/25 Pre_MP

13 Set E0 EC as main source. 31 Install R1093 and uninstall R1091 2010/03/29 Pre_MP

14 Set E0 EC as main source. 31 Change EC P/N to SA00001J5A0(E0) 2010/03/31 Pre_MP

15 Change R249 to 4.99K that have correct description. 31 Change R249 from SD00000HN80 to SD014499180. 2010/03/31 Pre_MP

16 Can't disable BT for combo card. 26/29 Add location Q15(SB570020020), add location R155/R439(SD028000080), add location(SD028100280) 2010/04/01 Pre_MP

17 Reserver ICH_susclk for EC's CLK IN. Reserver location R605 2010/04/08 Pre_MP
31
18 EMI Request. 25 Add C1409/C1410/C1411(SE070104Z80). 2010/04/08 Pre_MP

19
B B

20

21

22

23

24

25

26

27
A A

28

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR 3

www.vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Blade UMA LA4105P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 14, 2010 Sheet 46 of 46
5 4 3 2 1