A B C D E

ZZZ

PCB

DA600004Q00
1 1

Compal Confidential
2 2

Tuesday, March 06, 2007

IGT10/11 Schematics Document
Mobile Merom uFCPGA with Intel
3
Crestline_GM/PM+ICH8-M core logic 3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT10/11 LA-3591P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 48

REV:0.2

4 4

A B C D E
 A B C D E

Compal confidential
File Name : LA-3451P

1
Mobile Merom 1
LVDS uFCPGA-478 CPU
Connector

page4,5,6 Clock Gen.

ICS9LPRS355
page15
H_A#(3..35)
FSB
H_D#(0..63) 667/800MHz
VGA BOARD
PCI-E X16
DDR2 -667 DDR2-SO-DIMM X2
Intel Crestline GMCH BANK 0, 1, 2, 3 page 13,14

CRT & TV OUT PCBGA 1299 Dual Channel

LVDS I/F
page16
page7,8,9,10,11,12 MODEM
2
LVDS Ver 1.5 page 28 2

Connector page17 DMI C-Line

AMP&Audio Jack
AZALIA page30

PCI Express PCI-E BUS USB2.0

Mini card Slot
page26
Intel ICH8-M Audio Codec
mBGA-676 ALC 268
SATA page29
3.3V / 33 MHz PCI BUS
page19,20,21,22
ATA100
Finger printer
IDSEL:PCI_AD22 IDSEL:PCI_AD20 page36

BCM5906 1394+Card Reader PCMCIA

10/100 LAN ENE CB1410 PCI_REQ2# BlueTooth Conn
page23 RICOH R5C833 LPC BUS
page28 page27 PCI_GNT2# page28
3 3
PCI_REQ0#
PCI_GNT0# USB conn X3
page31
1394 Conn Card reader(XD/SD EC SIO
RJ45 CONN MMC/MS/MS-Pro PCMCIA
page24 page28 CONN ENE KB926 LPC47N217
HD SD) page37 page33
page27
SATA HDD
Connector page23
Touch Pad Int.KBD
page32
page36
PATA CDROM
TP Board USB Board Connector page23
BIOS page34

FP Board
4 4

SERIAL PORT
page35

SW Board Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 2 of 48
A B C D E
 A

Voltage Rails O MEANS ON X MEANS OFF SKU ID Table

Vcc 3.3V +/- 5%
+5VS Ra 100K +/- 5%
+3VS Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
power
+2.5VS
plane * 0 0 0 V 0 V 0 V
+1.8VS 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+B
+1.5VS 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
LDO3 +5VALW +1.8V CLOCK
+1.25VS 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
LDO5 +3VALW +5V
+VGA_CORE 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+0.9V
+CPU_CORE 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
State
+VCCP 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V

S0 O O O O O SKU ID MB ID(H) MB ID(L)

0
S3 * 1 IEL10
O O O X O 2 IDL11 IDL01
S5 S4/AC
3 HDL10 HDL00
O O X X O 4 HDL20
S5 S4/ Battery only
5 IDL12 HDL30
O X X X X 6
S5 S4/AC & Battery
7
don't exist X X X X X
MB ID
H 15"
L 14"

O MEANS ON S3 : STR
X MEANS OFF S4 : STD
S5 : SOFT OFF
1 BOM Structure USB PORT LIST 1

MARK FUNCTION
External PCI Devices @ NC FOR ALL PORT DEVICE
Device IDSEL# REQ#/GNT# Interrupts
GIGA@ BCM5787 0 LEFT SIDE
1394 AD22 0 PIRQG/H
100@ BCM5906 1 WIRELESS
UMA@ Internal 965GM 2 RIGHT SIDE
VGA@ 965PM + Ext VGA 3 CMOS
Address
4 RIGHT SIDE
5 NEW CARD
6 RIGHT SIDE
EC SM Bus1 address EC SM Bus2 address 7 BT(HDL20)
Device Address Device Address
8 FINGER PRINTER
Smart Battery 0001 011X b ADM1032 1001 100X b
9 TV TUNER
EEPROM(24C16/02) 1010 000X b

ICH6 SM Bus address

Device Address
Clock Generator
( ICS954226) 1101 001Xb
DDRII DIMM0 1010 000Xb
DDRII DIMM1 1010 010Xb

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 3 of 48
A
 5 4 3 2 1

+3VS
XDP Reserve
XDP_DBRESET#_R 1 2 @ 1K_0402_5%
R1
+VCCP

XDP_TDI R2 1 2 150_0402_1%

XDP_TMS R3 1 2 39_0402_1%

XDP_TDO R4 1 2 @ 54.9_0402_1%
D D
XDP_BPM#5 R5 1 2 54.9_0402_1%

XDP_TRST# R7 1 2 56_0402_5%
(7) H_A#[3..16]
JP1A XDP_TCK R8 1 2 54.9_0402_1%
H_A#3 J4 H1 H_ADS#
A[3]# ADS# H_ADS# (7)

0
ADDR GROUP
H_A#4 L5 E2 H_BNR#
H_A#5 L4
A[4]#
A[5]#
BNR#
BPRI# G5 H_BPRI#
H_BNR# (7)
H_BPRI# (7)
2006/09/19
H_A#6 K5
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# (7)
H_A#8 N2 F21 H_DRDY#
A[8]# DRDY# H_DRDY# (7)
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# (7)
H_A#10 N3
H_A#11 A[10]# H_BR0# R9
P5 A[11]# BR0# F1 H_BR0# (7)
H_A#12 P2 56_0402_5%
A[12]#

CONTROL
H_A#13 L2 D20 H_IERR# 2 1
H_A#14 A[13]# IERR# H_INIT# +VCCP
P4 A[14]# INIT# B3 H_INIT# (19)
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# (7)
H_ADSTB#0 M1
(7) H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# (7)
H_REQ#0 K3 F3 H_RS#0
(7) H_REQ#0 REQ[0]# RS[0]# H_RS#0 (7)
H_REQ#1 H2 F4 H_RS#1
(7) H_REQ#1 REQ[1]# RS[1]# H_RS#1 (7)
H_REQ#2 K2 G3 H_RS#2
(7) H_REQ#2 REQ[2]# RS[2]# H_RS#2 (7)
H_REQ#3 J3 G2 H_TRDY#
(7) H_REQ#3 REQ[3]# TRDY# H_TRDY# (7)
H_REQ#4 L1
(7) H_REQ#4 REQ[4]#
G6 H_HIT#
(7) H_A#[17..35] HIT# H_HIT# (7)
H_A#17 Y2 E4 H_HITM#
C A[17]# HITM# H_HITM# (7) C
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 A[19]# BPM[0]# AD4
+3VS
1
ADDR GROUP

H_A#20 W6 AD3 XDP_BPM#1 T1 PAD

H_A#21 A[20]# BPM[1]# XDP_BPM#2 T2 PAD
U4 A[21]# BPM[2]# AD1 C1
XDP/ITP SIGNALS

H_A#22 Y5 AC4 XDP_BPM#3 T3 PAD

H_A#23 A[22]# BPM[3]# XDP_BPM#4 T4 PAD
U1 A[23]# PRDY# AC2 1 2

2
H_A#24 R4 AC1 XDP_BPM#5 T5 PAD
H_A#25 A[24]# PREQ# XDP_TCK 0.1U_0402_16V4Z R10
T5 A[25]# TCK AC5
H_A#26 T3 AA6 XDP_TDI U1 10K_0402_5%
H_A#27 A[26]# TDI XDP_TDO H_THERMDA
W2 A[27]# TDO AB3 2 D+ VDD1 1
H_A#28 W5 AB5 XDP_TMS R616 C2
H_A#29 A[28]# TMS XDP_TRST# 0_0402_5% H_THERMDC THERM_SCI#

1
Y4 A[29]# TRST# AB6 1 2 3 D- ALERT# 6 2 1 EC_THERM# (20,33)
H_A#30 U2 C20 XDP_DBRESET#_R 1 2 2200P_0402_50V7K R11 @ 0_0402_5%
A[30]# DBR# XDP_DBRESET# (20)
H_A#31 V4 EC_SMB_CK2 8 4 THERM# 2 1 +3VS
A[31]# (33) EC_SMB_CK2 SCLK THERM#
H_A#32 W3 10K_0402_5% R12 Check : to sb
H_A#33 A[32]# H_CPU_PROCHOT# EC_SMB_DA2
AA4 A[33]# THERMAL 2 1 +VCCP (17,33) EC_SMB_DA2 7 SDATA GND 5
H_A#34 AB2 R13 56_0402_5%
H_A#35 A[34]#
AA3 A[35]# PROCHOT# D21
H_ADSTB#1 V1 A24 H_THERMDA G781F_MSOP8
(7) H_ADSTB#1 ADSTB[1]# THERMDA
B25 H_THERMDC Address:100_1100
H_A20M# THERMDC
(19) H_A20M# A6 A20M#
ICH

H_FERR# A5 C7 H_THERMTRIP# SA007810140

(19) H_FERR# FERR# THERMTRIP# H_THERMTRIP# (7,19)
H_IGNNE# C4
(19) H_IGNNE# IGNNE#
H_STPCLK# D5
(19) H_STPCLK# STPCLK#
H_INTR C6 H CLK
(19) H_INTR LINT0
H_NMI B4 A22 CLK_CPU_BCLK
(19) H_NMI LINT1 BCLK[0] CLK_CPU_BCLK (15)
H_SMI# A3 A21 CLK_CPU_BCLK#
(19) H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# (15)
M4 RSVD[01]
FAN1 Conn
N5 RSVD[02] H_THERMDA, H_THERMDC routing together,
T2 RSVD[03]
B V3 Trace width / Spacing = 10 / 10 mil +5VS B
B2
RSVD[04] C3 2006/09/05 +5VS
RESERVED

RSVD[05]
C3 RSVD[06] 1 2
D2 RSVD[07]

1
D22 10U_0805_10V4Z
RSVD[08] U2 D1
D3 RSVD[09]
F6 1 8 @ 1SS355_SOD323
RSVD[10] VEN GND
2 VIN GND 7
+VCC_FAN1 3 6 D2
EN_FAN1 VO GND @ 1N4148_SOT23

2
(33) EN_FAN1 4 VSET GND 5
Merom Ball-out Rev 1a 1 2
G993P1UF_SOP8

2006/09/05 C4
1 2
10U_0805_10V4Z
+3VS C5
+VCCP 1000P_0402_50V7K
1 2

1
R14
1

10K_0402_5%
R15 40mil JP2
56_0402_5% +VCC_FAN1

2
1
(33) FAN_SPEED1 2
22

3
B

1
C6 ACES_85205-03001
E

H_CPU_PROCHOT# 3 1 H_PROCHOT# 1000P_0402_50V7K ME@

H_PROCHOT# (20,46)
C

Q1
A MMBT3904_SOT23 2 A

2006/09/19

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(1/3)-AGTL+/XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 4 of 48
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE
(7) H_D#[0..15] H_D#[32..47] (7)
JP1B JP1C
H_D#0 E22 Y22 H_D#32 A7 AB20
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
F24 D[1]# D[33]# AB24 A9 VCC[002] VCC[069] AB7
H_D#2 E26 V24 H_D#34 A10 AC7
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
G22 D[3]# D[35]# V26 A12 VCC[004] VCC[071] AC9

DATA GRP 0
H_D#4 F23 V23 H_D#36 A13 AC12
H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
G25 D[5]# D[37]# T22 A15 VCC[006] VCC[073] AC13
H_D#6 E25 U25 H_D#38 A17 AC15
D H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074] D
E23 D[7]# D[39]# U23 A18 VCC[008] VCC[075] AC17
H_D#8 K24 Y25 H_D#40 A20 AC18
D[8]# D[40]# VCC[009] VCC[076]

DATA GRP 2
H_D#9 G24 W22 H_D#41 B7 AD7
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
J24 D[10]# D[42]# Y23 B9 VCC[011] VCC[078] AD9
H_D#11 J23 W24 H_D#43 B10 AD10
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
H22 D[12]# D[44]# W25 B12 VCC[013] VCC[080] AD12
H_D#13 F26 AA23 H_D#45 B14 AD14
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
K22 D[14]# D[46]# AA24 B15 VCC[015] VCC[082] AD15
H_D#15 H23 AB25 H_D#47 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
(7) H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 (7) B18 VCC[017] VCC[084] AD18
H_DSTBP#0 H26 AA26 H_DSTBP#2 B20 AE9
(7) H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 (7) VCC[018] VCC[085]
H_DINV#0 H25 U22 H_DINV#2 C9 AE10
(7) H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 (7) VCC[019] VCC[086]
(7) H_D#[16..31] H_D#[48..63] (7) C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
H_D#16 N22 AE24 H_D#48 C13 AE15
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
K25 D[17]# D[49]# AD24 C15 VCC[023] VCC[090] AE17
H_D#18 P26 AA21 H_D#50 C17 AE18
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
R23 D[19]# D[51]# AB22 C18 VCC[025] VCC[092] AE20
H_D#20 L23 AB21 H_D#52 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D10 AF10
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
L22 D[22]# D[54]# AD20 D12 VCC[028] VCC[095] AF12
H_D#23 M23 AE22 H_D#55 D14 AF14
H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
P25 D[24]# D[56]# AF23 D15 VCC[030] VCC[097] AF15
H_D#25 P23 AC25 H_D#57 D17 AF17 For testing purpose only
H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
P22 D[26]# D[58]# AE21 D18 VCC[032] VCC[099] AF18

DATA GRP 3
H_D#27 T24 AD21 H_D#59 E7 AF20 +VCCP
H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100] R16 0_0402_5%
R24 D[28]# D[60]# AC22 E9 VCC[034]
H_D#29 L25 AD23 H_D#61 E10 G21 2 1
H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01]
T25 D[30]# D[62]# AF22 E12 VCC[036] VCCP[02] V6 2 1
H_D#31 N25 AC23 H_D#63 E13 J6 R17 0_0402_5%
D[31]# D[63]# VCC[037] VCCP[03]

330U_V_2.5VK_R9
H_DSTBN#1 L26 AE25 H_DSTBN#3 E15 K6 1
(7) H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 (7) VCC[038] VCCP[04]
H_DSTBP#1 M26 AF24 H_DSTBP#3 E17 M6
(7) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (7) VCC[039] VCCP[05]

C7
C H_DINV#1 N24 AC20 H_DINV#3 E18 J21 + C
(7) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (7) VCC[040] VCCP[06]
E20 VCC[041] VCCP[07] K21
+CPU_GTLREF AD26 R26 COMP0 F7 M21
R18 GTLREF COMP[0] VCC[042] VCCP[08] 2
1 2 @ 1K_0402_5% TEST1 C23 TEST1 MISC COMP[1] U26 COMP1 F9 VCC[043] VCCP[09] N21
R19 1 2 @ 1K_0402_5% TEST2 D25 AA1 COMP2 F10 N6
T12 PAD TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
C24 TEST3 COMP[3] Y1 F12 VCC[045] VCCP[11] R21
C8 1 2 @ 0.1U_0402_16V4Z TEST4 AF26 F14 R6
T13 PAD TEST5 TEST4 H_DPRSTP# VCC[046] VCCP[12]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# (7,19,46) F15 VCC[047] VCCP[13] T21

54.9_0402_1%

27.4_0402_1%
27.4_0402_1%

54.9_0402_1%
T14 PAD TEST6 A26 B5 H_DPSLP# F17 T6
TEST6 DPSLP# H_DPSLP# (19) VCC[048] VCCP[14]

1
D24 H_DPWR# F18 V21
DPWR# H_DPWR# (7) VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
(15) CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD (19) VCC[050] VCCP[16]

R20

R21

R22

R23
CPU_BSEL1 B23 D7 H_CPUSLP# AA7
(15) CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# (7) VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
(15) CPU_BSEL2 BSEL[2] PSI# H_PSI# (46) VCC[052] VCCA[01] +1.5VS

0.01U_0402_16V7K
AA10 VCC[053] VCCA[02] C26

10U_0805_10V4Z
Merom Ball-out Rev 1a

2
AA12 VCC[054]
AA13 VCC[055] VID[0] AD6 CPU_VID0 (46)
AA15 VCC[056] VID[1] AF5 CPU_VID1 (46) 1 1
AA17 VCC[057] VID[2] AE5 CPU_VID2 (46)

C9

C10
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within AA18 VCC[058] VID[3] AF4 CPU_VID3 (46)
AA20 VCC[059] VID[4] AE3 CPU_VID4 (46)
0.5" of CPU pin.Trace AB9 AF3 CPU_VID5 (46)
2 2
VCC[060] VID[5]
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 should be at least 25 AC10 VCC[061] VID[6] AE2 CPU_VID6 (46)
AB10 VCC[062]
mils away from any other AB12 VCC[063]
AB14 AF7 VCCSENSE
toggling signal. VCC[064] VCCSENSE VCCSENSE (46)
166 0 1 1 AB15 VCC[065] Near pin B26
COMP[0,2] trace width is AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE (46)
18 mils. COMP[1,3] trace VCC[067] VSSSENSE
200 0 1 0 width is 4 mils. Merom Ball-out Rev 1a
.
B Length match within 25 mils. B
The trace width/space/other is
20/7/25.
+VCCP
1

R24
1K_0402_1%
+CPU_CORE
+CPU_GTLREF R25
2

100_0402_1%
1 2 VCCSENSE
1

R27
R26 100_0402_1%
2K_0402_1% 1 2 VSSSENSE
2

Close to CPU pin AD26

within 500mils. Close to CPU pin
within 500mils.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(2/3)-AGTL+/PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 5 of 48
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE

D D

1 1 1 1 1 1 1 1
JP1D
A4 P6 Place these capacitors on L8 C11 C12 C13 C14 C15 C16 C17 C18
VSS[001] VSS[082] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A8 VSS[002] VSS[083] P21 (North side,Secondary Layer)
2 2 2 2 2 2 2 2
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
A16 VSS[005] VSS[086] R5
A19 VSS[006] VSS[087] R22
+CPU_CORE
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1
B6 VSS[009] VSS[090] T4
B8 VSS[010] VSS[091] T23 1 1 1 1 1 1 1 1
B11 VSS[011] VSS[092] T26
B13 U3 Place these capacitors on L8 C19 C20 C21 C22 C23 C24 C25 C26
VSS[012] VSS[093] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B16 VSS[013] VSS[094] U6 (North side,Secondary Layer)
2 2 2 2 2 2 2 2
B19 VSS[014] VSS[095] U21
B21 VSS[015] VSS[096] U24
B24 VSS[016] VSS[097] V2
C5 VSS[017] VSS[098] V5
+CPU_CORE
C8 VSS[018] VSS[099] V22
C11 VSS[019] VSS[100] V25
C14 VSS[020] VSS[101] W1
C16 VSS[021] VSS[102] W4 1 1 1 1 1 1 1 1
C19 VSS[022] VSS[103] W23
C2 W26 Place these capacitors on L8 C27 C28 C29 C30 C31 C32 C33 C34
VSS[023] VSS[104] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
C22 VSS[024] VSS[105] Y3 (Sorth side,Secondary Layer)
2 2 2 2 2 2 2 2
C25 VSS[025] VSS[106] Y6
D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
D8 VSS[028] VSS[109] AA2
+CPU_CORE
D11 VSS[029] VSS[110] AA5
C C
D13 VSS[030] VSS[111] AA8
D16 VSS[031] VSS[112] AA11
D19 VSS[032] VSS[113] AA14 1 1 1 1 1 1 1 1
D23 VSS[033] VSS[114] AA16
D26 AA19 Place these capacitors on L8 C35 C36 C37 C38 C39 C40 C41 C42
VSS[034] VSS[115] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
E3 VSS[035] VSS[116] AA22 (Sorth side,Secondary Layer)
2 2 2 2 2 2 2 2
E6 VSS[036] VSS[117] AA25
E8 VSS[037] VSS[118] AB1 Mid Frequence Decoupling
E11 VSS[038] VSS[119] AB4
E14 VSS[039] VSS[120] AB8
E16 VSS[040] VSS[121] AB11
E19 VSS[041] VSS[122] AB13
E21 VSS[042] VSS[123] AB16
E24 VSS[043] VSS[124] AB19
F5 VSS[044] VSS[125] AB23
F8 VSS[045] VSS[126] AB26
F11 VSS[046] VSS[127] AC3
F13 VSS[047] VSS[128] AC6
+CPU_CORE
F16 VSS[048] VSS[129] AC8
F19 VSS[049] VSS[130] AC11
F2 VSS[050] VSS[131] AC14
F22 VSS[051] VSS[132] AC16
F25 VSS[052] VSS[133] AC19
G4 AC21
G1
VSS[053]
VSS[054]
VSS[134]
VSS[135] AC24 1 1 1 1 1 1 ESR <= 1.5m ohm
G23 AD2
G26
H3
VSS[055]
VSS[056]
VSS[136]
VSS[137] AD5
AD8 South Side Secondary
+ C43 + C44 + C45 + C46 + C47 + C48 North Side Secondary Capacitor > 1980uF
VSS[057] VSS[138] 330U_D2E_2.5VM_R9
H6 VSS[058] VSS[139] AD11
H21 AD13 330U_D2E_2.5VM_R9 2 2 2 2 2 2
VSS[059] VSS[140] 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9
H24 VSS[060] VSS[141] AD16
J2 AD19 330U_D2E_2.5VM_R9
B VSS[061] VSS[142] B
J5 VSS[062] VSS[143] AD22
J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 VSS[069] VSS[150] AE16
L6 VSS[070] VSS[151] AE19
L21 AE23 +VCCP
VSS[071] VSS[152]
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6 1
M22 VSS[075] VSS[156] AF8 1 1 1 1 1 1
M25 AF11 C49 + Place these inside
VSS[076] VSS[157] C50 C51 C52 C53 C54 C55
N1 VSS[077] VSS[158] AF13 socket cavity on L8
N4 AF16 220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
VSS[078] VSS[159] 2 2 2 2 2 2 2
N23 VSS[079] VSS[160] AF19 Secondary)
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25

Merom Ball-out Rev 1a

.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Merom(3/3)-GND&Bypass
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 6 of 48
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] (4) U3B For Crestline: 20ohm

(5) H_D#[0..63] U3A For Calero: 80.6ohm
J13 H_A#3 P36
H_D#0 H_A#_3 H_A#4 RSVD1 M_CLK_DDR0
E2 H_D#_0 H_A#_4 B11 P37 RSVD2 SM_CK_0 AV29 M_CLK_DDR0 (13)
H_D#1 G2 C11 H_A#5 R35 BB23 M_CLK_DDR1 M_CLK_DDR1 (13)
H_D#2 H_D#_1 H_A#_5 H_A#6 RSVD3 SM_CK_1 M_CLK_DDR2
G7 H_D#_2 H_A#_6 M11 N35 RSVD4 SM_CK_3 BA25 M_CLK_DDR2 (14)
H_D#3 M6 C15 H_A#7 AR12 AV23 M_CLK_DDR3

2.2U_0603_10V6K
M_CLK_DDR3 (14)

0.01U_0402_25V7K
H_D#4 H_D#_3 H_A#_7 H_A#8 +1.8V RSVD5 SM_CK_4
H7 H_D#_4 H_A#_8 F16 AR13 RSVD6
H_D#5 H3 L13 H_A#9 AM12 AW30 M_CLK_DDR#0
H_D#_5 H_A#_9 RSVD7 SM_CK#_0 M_CLK_DDR#0 (13)
H_D#6 G4 G17 H_A#10 2 2 AN13 BA23 M_CLK_DDR#1
H_D#_6 H_A#_10 RSVD8 SM_CK#_1 M_CLK_DDR#1 (13)

1
H_D#7 F3 C14 H_A#11 J12 AW25 M_CLK_DDR#2
H_D#_7 H_A#_11 RSVD9 SM_CK#_3 M_CLK_DDR#2 (14)

RSVD
H_D#8 N8 K16 H_A#12 R28 AR37 AW23 M_CLK_DDR#3
H_D#_8 H_A#_12 RSVD10 SM_CK#_4 M_CLK_DDR#3 (14)

C56

C57
H_D#9 H2 B13 H_A#13 AM36
H_D#10 H_D#_9 H_A#_13 H_A#14 1 1 1K_0402_1% RSVD11 DDR_CKE0_DIMMA
M10 H_D#_10 H_A#_14 L16 AL36 RSVD12 SM_CKE_0 BE29 DDR_CKE0_DIMMA (13)
H_D#11 N12 J17 H_A#15 AM37 AY32 DDR_CKE1_DIMMA
D H_D#_11 H_A#_15 RSVD13 SM_CKE_1 DDR_CKE1_DIMMA (13) D
H_D#12 H_A#16 SMRCOMP_VOH DDR_CKE2_DIMMB

2
N9 H_D#_12 H_A#_16 B14 D20 RSVD14 SM_CKE_3 BD39 DDR_CKE2_DIMMB (14)
H_D#13 H5 K19 H_A#17 BG37 DDR_CKE3_DIMMB
H_D#_13 H_A#_17 SM_CKE_4 DDR_CKE3_DIMMB (14)

1
H_D#14 P13 P15 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19 R29 DDR_CS0_DIMMA#
K9 H_D#_15 H_A#_19 R17 SM_CS#_0 BG20 DDR_CS0_DIMMA# (13)
H_D#16 M2 B16 H_A#20 3.01K_0402_1% BK16 DDR_CS1_DIMMA#
H_D#_16 H_A#_20 NA lead free SM_CS#_1 DDR_CS1_DIMMA# (13)
H_D#17 W10 H20 H_A#21 BG16 DDR_CS2_DIMMB#
H_D#_17 H_A#_21 SM_CS#_2 DDR_CS2_DIMMB# (14)
H_D#18 Y8 L19 H_A#22 H10 BE13 DDR_CS3_DIMMB#
H_D#_18 H_A#_22 RSVD20 SM_CS#_3 DDR_CS3_DIMMB# (14)

MUXING
H_D#19 H_A#23 SMRCOMP_VOL

2
V4 H_D#_19 H_A#_23 D17 B51 RSVD21
H_D#20 M3 M17 H_A#24 BJ20 BH18 M_ODT0 M_ODT0 (13)
H_D#_20 H_A#_24 RSVD22 SM_ODT_0

1
0.01U_0402_25V7K
2.2U_0603_10V6K
H_D#21 J1 N16 H_A#25 BK22 BJ15 M_ODT1 M_ODT1 (13)
H_D#22 H_D#_21 H_A#_25 H_A#26 R30 RSVD23 SM_ODT_1 M_ODT2 +1.8V
N5 H_D#_22 H_A#_26 J19 1 1 BF19 RSVD24 SM_ODT_2 BJ14 M_ODT2 (14)
H_D#23 N3 B18 H_A#27 BH20 BE16 M_ODT3 M_ODT3 (14)
H_D#24 H_D#_23 H_A#_27 H_A#28 1K_0402_1% RSVD25 SM_ODT_3 20_0402_1%
W6 H_D#_24 H_A#_28 E19 BK18 RSVD26

C58

C59
H_D#25 W9 B17 H_A#29 BJ18 BL15 SMRCOMP R31 2 1
H_D#26 H_D#_25 H_A#_29 H_A#30 2 2 RSVD27 SM_RCOMP SMRCOMP#

2
N2 H_D#_26 H_A#_30 B15 BF23 RSVD28 SM_RCOMP# BK14 2 1
H_D#27 Y7 E17 H_A#31 BG23 R32 20_0402_1%
H_D#28 H_D#_27 H_A#_31 H_A#32 RSVD29 SMRCOMP_VOH
Y9 H_D#_28 H_A#_32 C18 BC23 RSVD30 SM_RCOMP_VOH BK31
H_D#29 P4 A19 H_A#33 BD24 BL31 SMRCOMP_VOL

DDR
H_D#30 H_D#_29 H_A#_33 H_A#34 RSVD31 SM_RCOMP_VOL
W3 H_D#_30 H_A#_34 B19 (13) DDR_A_MA14 BJ29 RSVD32
H_D#31 N1 N19 H_A#35 BE24 AR49
H_D#_31 H_A#_35 (14) DDR_B_MA14 RSVD33 SM_VREF_0
H_D#32 AD12 BH39 AW4 +DDR_MCH_REF
H_D#33 H_D#_32 H_ADS# RSVD34 SM_VREF_1
AE3 H_D#_33 H_ADS# G12 H_ADS# (4) AW20 RSVD35
H_D#34 AD9
HOST H17 H_ADSTB#0 BK20
H_D#_34 H_ADSTB#_0 H_ADSTB#0 (4) RSVD36
H_D#35 AC9 G20 H_ADSTB#1 C48
H_D#_35 H_ADSTB#_1 H_ADSTB#1 (4) RSVD37
H_D#36 AC7 C8 H_BNR# D47 B42 CLK_MCH_DREFCLK
H_D#_36 H_BNR# H_BNR# (4) RSVD38 DPLL_REF_CLK CLK_MCH_DREFCLK (15)
H_D#37 AC14 E8 H_BPRI# B44 C42 CLK_MCH_DREFCLK#
H_D#_37 H_BPRI# H_BPRI# (4) RSVD39 DPLL_REF_CLK# CLK_MCH_DREFCLK# (15)
H_D#38 AD11 F12 H_BR0# C44 H48 MCH_SSCDREFCLK
H_D#_38 H_BREQ# H_BR0# (4) RSVD40 DPLL_REF_SSCLK MCH_SSCDREFCLK (15)
H_D#39 AC11 D6 H_DEFER# A35 H47 MCH_SSCDREFCLK#
H_D#_39 H_DEFER# H_DEFER# (4) RSVD41 DPLL_REF_SSCLK# MCH_SSCDREFCLK# (15)
H_D#40 AB2 C10 H_DBSY# B37
H_D#_40 H_DBSY# H_DBSY# (4) RSVD42
H_D#41 AD7 AM5 CLK_MCH_BCLK B36 K44 CLK_MCH_3GPLL
H_D#_41 HPLL_CLK CLK_MCH_BCLK (15) RSVD43 PEG_CLK CLK_MCH_3GPLL (15)

CLK
H_D#42 AB1 AM7 CLK_MCH_BCLK# B34 K45 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# (15) RSVD44 PEG_CLK# CLK_MCH_3GPLL# (15)
H_D#43 Y3 H8 H_DPWR# C34
C H_D#_43 H_DPWR# H_DPWR# (5) RSVD45 C
H_D#44 AC6 K7 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# (4)
H_D#45 AE2 E4 H_HIT#
H_D#_45 H_HIT# H_HIT# (4)
H_D#46 AC5 C6 H_HITM# AN47 DMI_TXN0
H_D#_46 H_HITM# H_HITM# (4) DMI_RXN_0 DMI_TXN0 (20)
H_D#47 AG3 G10 H_LOCK# AJ38 DMI_TXN1
H_D#_47 H_LOCK# H_LOCK# (4) DMI_RXN_1 DMI_TXN1 (20)
H_D#48 AJ9 B7 H_TRDY# AN42 DMI_TXN2
H_D#_48 H_TRDY# H_TRDY# (4) DMI_RXN_2 DMI_TXN2 (20)
H_D#49 AH8 AN46 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 (20)
H_D#50 AJ14
H_D#51 H_D#_50 DMI_TXP0
AE9 H_D#_51 DMI_RXP_0 AM47 DMI_TXP0 (20)
H_D#52 AE11 MCH_CLKSEL0 P27 AJ39 DMI_TXP1
+VCCP H_D#_52 (15) MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 (20)
H_D#53 AH12 K5 H_DINV#0 MCH_CLKSEL1 N27 AN41 DMI_TXP2
H_D#_53 H_DINV#_0 H_DINV#0 (5) (15) MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 (20)
H_D#54 AJ5 L2 H_DINV#1 MCH_CLKSEL2 N24 AN45 DMI_TXP3
H_D#_54 H_DINV#_1 H_DINV#1 (5) (15) MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 (20)
H_D#55 AH5 AD13 H_DINV#2 C21
H_D#_55 H_DINV#_2 H_DINV#2 (5) CFG_3
H_D#56 AJ6 AE13 H_DINV#3 C23 AJ46 DMI_RXN0
H_D#_56 H_DINV#_3 H_DINV#3 (5) CFG_4 DMI_TXN_0 DMI_RXN0 (20)
54.9_0402_1%

54.9_0402_1%

H_D#57 AE7 CFG5 F23 AJ41 DMI_RXN1

H_D#_57 (9) CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 (20)
1

H_D#58 AJ7 M7 H_DSTBN#0 CFG6 N23 AM40 DMI_RXN2

H_D#_58 H_DSTBN#_0 H_DSTBN#0 (5) CFG6 CFG_6 DMI_TXN_2 DMI_RXN2 (20)
H_D#59 AJ2 K3 H_DSTBN#1 CFG7 G23 AM44 DMI_RXN3
H_D#_59 H_DSTBN#_1 H_DSTBN#1 (5) (9) CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 (20)
R33

R34

H_D#60 AE5 AD2 H_DSTBN#2 J20

DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 (5) (9) CFG8 CFG_8

CFG
H_D#61 AJ3 AH11 H_DSTBN#3 CFG9 C20 AJ47 DMI_RXP0
H_D#_61 H_DSTBN#_3 H_DSTBN#3 (5) (9) CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 (20)
H_D#62 AH2 CFG10 R24 AJ42 DMI_RXP1
H_D#_62 CFG10 CFG_10 DMI_TXP_1 DMI_RXP1 (20)
H_D#63 H_DSTBP#0 CFG11 DMI_RXP2
2

AH13 H_D#_63 H_DSTBP#_0 L7 H_DSTBP#0 (5) CFG11 L23 CFG_11 DMI_TXP_2 AM39 DMI_RXP2 (20)
K2 H_DSTBP#1 CFG12 J23 AM43 DMI_RXP3
H_DSTBP#_1 H_DSTBP#1 (5) (9) CFG12 CFG_12 DMI_TXP_3 DMI_RXP3 (20)
AC2 H_DSTBP#2 CFG13 E23
H_DSTBP#_2 H_DSTBP#2 (5) (9) CFG13 CFG_13
H_SWNG B3 AJ10 H_DSTBP#3 E20
H_SWING H_DSTBP#_3 H_DSTBP#3 (5) CFG_14
H_RCOMP C2 K23
H_RCOMP H_REQ#0 CFG16 CFG_15
H_REQ#_0 M14 H_REQ#0 (4) (9) CFG16 M20 CFG_16
H_SCOMP H_REQ#1

GRAPHICS VID
W1 H_SCOMP H_REQ#_1 E13 H_REQ#1 (4) M24 CFG_17
H_SCOMP# W2 A11 H_REQ#2 CFG18 L32
H_SCOMP# H_REQ#_2 H_REQ#2 (4) CFG18 CFG_18
H13 H_REQ#3 CFG19 N33
H_REQ#_3 H_REQ#3 (4) (9) CFG19 CFG_19
(4) H_RESET# H_RESET# B6 B12 H_REQ#4 CFG20 L35
H_CPURST# H_REQ#_4 H_REQ#4 (4) (9) CFG20 CFG_20
(5) H_CPUSLP# H_CPUSLP# E5 H_CPUSLP# H_RS#0
H_RS#_0 E12 H_RS#0 (4)
D7 H_RS#1 H_RS#1 (4) Check : different from hdl00 E35
B H_RS#_1 H_RS#2 PM_BMBUSY# GFX_VID_0 B
H_RS#_2 D8 H_RS#2 (4) (20) PM_BMBUSY# G41 PM_BM_BUSY# GFX_VID_1 A39
B9 H_DPRSTP# L39 C38
H_AVREF (5,19,46) H_DPRSTP# PM_DPRSTP# GFX_VID_2
H_VREF A9 PM_EXTTS#0 L36 B39
H_DVREF (13) PM_EXTTS#0 PM_EXT_TS#_0 GFX_VID_3

PM
PM_EXTTS#1 J36 E36 GFX_VR_EN T31 PAD
(14) PM_EXTTS#1 PM_EXT_TS#_1 GFX_VR_EN
CRESTLINE_1p0 2 1 PM_POK_R PM_POK_R AW49
(20,33) ICH_POK PWROK +1.25VS
UMA@ R35 0_0402_5% PLT_RST#_R AV20
H_THERMTRIP# RSTIN#
(20,46) VGATE 2 1 (4,19) H_THERMTRIP# N20 THERMTRIP#
R36 @ 0_0402_5% 0309 add (20,46) DPRSLPVR DPRSLPVR G36 For AMT function
SA00000ZWA0 DPRSLPVR

1
1 2 PLT_RST#_R
(17,18,20,23,25,26) PLT_RST# CL_CLK0 (20)
layout note: R37 100_0402_5% AM49 CL_CLK0 R38
CL_CLK CL_DATA0 (20)
AK50 CL_DATA0
CL_DATA M_PWROK ICH_POK 1K_0402_1%
Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces BJ51 NC_1 CL_PWROK AT43 1 2
+3VS CL_RST# R622 0_0402_5%

ME
BK51 NC_2 CL_RST# AN49 CL_RST# (20)
CL_VREF

2
BK50 NC_3 CL_VREF AM50
Layout Note: 1 2 PM_EXTTS#0 BL50 NC_4

1
Layout Note: R39 10K_0402_5% BL49 0.1U_0402_16V4Z 1
V_DDR_MCH_REF +1.8V PM_EXTTS#1 NC_5 R41
H_RCOMP / H_VREF / H_SWNG 1 2 BL3 NC_6
trace width and R40 10K_0402_5% BL2 C60 392_0402_1%
NC_7

NC
trace width and spacing is 10/20 BK1 NC_8
1

spacing is 20/20. BJ1 H35

2
R42 NC_9 SDVO_CTRL_CLK T32 PAD

MISC

2
E1 NC_10 SDVO_CTRL_DATA K36
1K_0402_1% A5 G39 CLKREQ_3GPLL# CLKREQ_3GPLL# (15)
NC_11 CLK_REQ# MCH_ICH_SYNC#
C51 NC_12 ICH_SYNC# G40 MCH_ICH_SYNC# (20)
+VCCP B50
+VCCP +DDR_MCH_REF NC_13 +3VS
2

+DDR_MCH_REF A50 NC_14

0.1U_0402_16V4Z

A49 NC_15 TEST_1 A37

1
1K_0402_1%

221_0603_1%

BK2 NC_16 TEST_2 R32

1

1 R43

1
R45

CRESTLINE_1p0
R44

C61

1K_0402_1% UMA@ R46 R47 R48

CLKREQ_3GPLL# 2 1
0.1U_0402_16V4Z 2 20K_0402_5% 0_0402_5%
2

A
SA00000ZWA0 A
H_VREF H_RCOMP H_SWNG 10K_0402_5%
2

2
24.9_0402_1%

0.1U_0402_16V4Z
1

1
100_0402_1%
2K_0402_1%

1 1
R49

C62

R50

R51

C63

2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(1/6)-AGTL+/DMI/DDR2
within 100 mils from NB Near B3 pin Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 7 of 48
5 4 3 2 1
 5 4 3 2 1

U3

965PM
VGA@
SA00001DJA0
D D

(13) DDR_A_D[0..63] (14) DDR_B_D[0..63]

U3D U3E
DDR_A_D0 AR43 BB19 DDR_A_BS#0 DDR_B_D0 AP49 AY17 DDR_B_BS#0
SA_DQ_0 SA_BS_0 DDR_A_BS#0 (13) SB_DQ_0 SB_BS_0 DDR_B_BS#0 (14)
DDR_A_D1 AW44 BK19 DDR_A_BS#1 DDR_B_D1 AR51 BG18 DDR_B_BS#1
SA_DQ_1 SA_BS_1 DDR_A_BS#1 (13) SB_DQ_1 SB_BS_1 DDR_B_BS#1 (14)
DDR_A_D2 BA45 BF29 DDR_A_BS#2 DDR_B_D2 AW50 BG36 DDR_B_BS#2
SA_DQ_2 SA_BS_2 DDR_A_BS#2 (13) SB_DQ_2 SB_BS_2 DDR_B_BS#2 (14)
DDR_A_D3 AY46 DDR_B_D3 AW51
DDR_A_D4 SA_DQ_3 DDR_A_CAS# DDR_B_D4 SB_DQ_3 DDR_B_CAS#
AR41 SA_DQ_4 SA_CAS# BL17 DDR_A_CAS# (13) AN51 SB_DQ_4 SB_CAS# BE17 DDR_B_CAS# (14)
DDR_A_D5 AR45 DDR_B_D5 AN50
SA_DQ_5 DDR_A_DM[0..7] (13) SB_DQ_5 DDR_B_DM[0..7] (14)
DDR_A_D6 AT42 AT45 DDR_A_DM0 DDR_B_D6 AV50 AR50 DDR_B_DM0
DDR_A_D7 SA_DQ_6 SA_DM_0 DDR_A_DM1 DDR_B_D7 SB_DQ_6 SB_DM_0 DDR_B_DM1
AW47 SA_DQ_7 SA_DM_1 BD44 AV49 SB_DQ_7 SB_DM_1 BD49
DDR_A_D8 BB45 BD42 DDR_A_DM2 DDR_B_D8 BA50 BK45 DDR_B_DM2
DDR_A_D9 SA_DQ_8 SA_DM_2 DDR_A_DM3 DDR_B_D9 SB_DQ_8 SB_DM_2 DDR_B_DM3
BF48 SA_DQ_9 SA_DM_3 AW38 BB50 SB_DQ_9 SB_DM_3 BL39
DDR_A_D10 BG47 AW13 DDR_A_DM4 DDR_B_D10 BA49 BH12 DDR_B_DM4
DDR_A_D11 SA_DQ_10 SA_DM_4 DDR_A_DM5 DDR_B_D11 SB_DQ_10 SB_DM_4 DDR_B_DM5
BJ45 SA_DQ_11 SA_DM_5 BG8 BE50 SB_DQ_11 SB_DM_5 BJ7
DDR_A_D12 BB47 AY5 DDR_A_DM6 DDR_B_D12 BA51 BF3 DDR_B_DM6
DDR_A_D13 SA_DQ_12 SA_DM_6 DDR_A_DM7 DDR_B_D13 SB_DQ_12 SB_DM_6 DDR_B_DM7
BG50 SA_DQ_13 SA_DM_7 AN6 AY49 SB_DQ_13 SB_DM_7 AW2
DDR_A_D14 BH49 DDR_A_DQS[0..7] (13) DDR_B_D14 BF50
SA_DQ_14 SB_DQ_14 DDR_B_DQS[0..7] (14)
DDR_A_D15 BE45 AT46 DDR_A_DQS0 DDR_B_D15 BF49 AT50 DDR_B_DQS0

A
DDR_A_D16 SA_DQ_15 SA_DQS_0 DDR_A_DQS1 DDR_B_D16 SB_DQ_15 SB_DQS_0 DDR_B_DQS1
AW43 BE48 BJ50 BD50

B
DDR_A_D17 SA_DQ_16 SA_DQS_1 DDR_A_DQS2 DDR_B_D17 SB_DQ_16 SB_DQS_1 DDR_B_DQS2
BE44 SA_DQ_17 SA_DQS_2 BB43 BJ44 SB_DQ_17 SB_DQS_2 BK46
DDR_A_D18 BG42 BC37 DDR_A_DQS3 DDR_B_D18 BJ43 BK39 DDR_B_DQS3
DDR_A_D19 SA_DQ_18 SA_DQS_3 DDR_A_DQS4 DDR_B_D19 SB_DQ_18 SB_DQS_3 DDR_B_DQS4
BE40 SA_DQ_19 SA_DQS_4 BB16 BL43 SB_DQ_19 SB_DQS_4 BJ12
DDR_A_D20 DDR_A_DQS5 DDR_B_D20 DDR_B_DQS5

MEMORY
BF44 SA_DQ_20 SA_DQS_5 BH6 BK47 SB_DQ_20 SB_DQS_5 BL7
DDR_A_D21 DDR_A_DQS6 DDR_B_D21 DDR_B_DQS6

MEMORY
BH45 SA_DQ_21 SA_DQS_6 BB2 BK49 SB_DQ_21 SB_DQS_6 BE2
DDR_A_D22 BG40 AP3 DDR_A_DQS7 DDR_B_D22 BK43 AV2 DDR_B_DQS7
SA_DQ_22 SA_DQS_7 DDR_A_DQS#[0..7] (13) SB_DQ_22 SB_DQS_7 DDR_B_DQS#[0..7] (14)
DDR_A_D23 BF40 AT47 DDR_A_DQS#0 DDR_B_D23 BK42 AU50 DDR_B_DQS#0
DDR_A_D24 SA_DQ_23 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D24 SB_DQ_23 SB_DQS#_0 DDR_B_DQS#1
AR40 SA_DQ_24 SA_DQS#_1 BD47 BJ41 SB_DQ_24 SB_DQS#_1 BC50
DDR_A_D25 AW40 BC41 DDR_A_DQS#2 DDR_B_D25 BL41 BL45 DDR_B_DQS#2
DDR_A_D26 SA_DQ_25 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D26 SB_DQ_25 SB_DQS#_2 DDR_B_DQS#3
AT39 SA_DQ_26 SA_DQS#_3 BA37 BJ37 SB_DQ_26 SB_DQS#_3 BK38
DDR_A_D27 AW36 BA16 DDR_A_DQS#4 DDR_B_D27 BJ36 BK12 DDR_B_DQS#4
DDR_A_D28 SA_DQ_27 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D28 SB_DQ_27 SB_DQS#_4 DDR_B_DQS#5
AW41 SA_DQ_28 SA_DQS#_5 BH7 BK41 SB_DQ_28 SB_DQS#_5 BK7
C DDR_A_D29 DDR_A_DQS#6 DDR_B_D29 DDR_B_DQS#6 C
AY41 SA_DQ_29 SA_DQS#_6 BC1 BJ40 SB_DQ_29 SB_DQS#_6 BF2
DDR_A_D30 AV38 AP2 DDR_A_DQS#7 DDR_B_D30 BL35 AV3 DDR_B_DQS#7
SA_DQ_30 SA_DQS#_7 DDR_A_MA[0..13] (13) SB_DQ_30 SB_DQS#_7
DDR_A_D31 AT38 DDR_B_D31 BK37 DDR_B_MA[0..13] (14)
DDR_A_D32 SA_DQ_31 DDR_A_MA0 DDR_B_D32 SB_DQ_31 DDR_B_MA0
AV13 SA_DQ_32 SA_MA_0 BJ19 BK13 SB_DQ_32 SB_MA_0 BC18
SYSTEM

DDR_A_D33 AT13 BD20 DDR_A_MA1 DDR_B_D33 BE11 BG28 DDR_B_MA1

SA_DQ_33 SA_MA_1 SB_DQ_33 SB_MA_1

SYSTEM
DDR_A_D34 AW11 BK27 DDR_A_MA2 DDR_B_D34 BK11 BG25 DDR_B_MA2
DDR_A_D35 SA_DQ_34 SA_MA_2 DDR_A_MA3 DDR_B_D35 SB_DQ_34 SB_MA_2 DDR_B_MA3
AV11 SA_DQ_35 SA_MA_3 BH28 BC11 SB_DQ_35 SB_MA_3 AW17
DDR_A_D36 AU15 BL24 DDR_A_MA4 DDR_B_D36 BC13 BF25 DDR_B_MA4
DDR_A_D37 SA_DQ_36 SA_MA_4 DDR_A_MA5 DDR_B_D37 SB_DQ_36 SB_MA_4 DDR_B_MA5
AT11 SA_DQ_37 SA_MA_5 BK28 BE12 SB_DQ_37 SB_MA_5 BE25
DDR_A_D38 BA13 BJ27 DDR_A_MA6 DDR_B_D38 BC12 BA29 DDR_B_MA6
DDR_A_D39 SA_DQ_38 SA_MA_6 DDR_A_MA7 DDR_B_D39 SB_DQ_38 SB_MA_6 DDR_B_MA7
BA11 SA_DQ_39 SA_MA_7 BJ25 BG12 SB_DQ_39 SB_MA_7 BC28
DDR_A_D40 BE10 BL28 DDR_A_MA8 DDR_B_D40 BJ10 AY28 DDR_B_MA8
DDR_A_D41 SA_DQ_40 SA_MA_8 DDR_A_MA9 DDR_B_D41 SB_DQ_40 SB_MA_8 DDR_B_MA9
BD10 SA_DQ_41 SA_MA_9 BA28 BL9 SB_DQ_41 SB_MA_9 BD37
DDR_A_D42 BD8 BC19 DDR_A_MA10 DDR_B_D42 BK5 BG17 DDR_B_MA10
DDR_A_D43 SA_DQ_42 SA_MA_10 DDR_A_MA11 DDR_B_D43 SB_DQ_42 SB_MA_10 DDR_B_MA11
AY9 SA_DQ_43 SA_MA_11 BE28 BL5 SB_DQ_43 SB_MA_11 BE37
DDR_A_D44 BG10 BG30 DDR_A_MA12 DDR_B_D44 BK9 BA39 DDR_B_MA12
DDR_A_D45 SA_DQ_44 SA_MA_12 DDR_A_MA13 DDR_B_D45 SB_DQ_44 SB_MA_12 DDR_B_MA13
AW9 SA_DQ_45 SA_MA_13 BJ16 BK10 SB_DQ_45 SB_MA_13 BG13
DDR

DDR_A_D46 BD7 DDR_B_D46 BJ8

SA_DQ_46 SB_DQ_46

DDR
DDR_A_D47 BB9 DDR_B_D47 BJ6 AV16 DDR_B_RAS#
SA_DQ_47 SB_DQ_47 SB_RAS# DDR_B_RAS# (14)
DDR_A_D48 BB5 BE18 DDR_A_RAS# DDR_B_D48 BF4 AY18 SB_RCVEN#
SA_DQ_48 SA_RAS# DDR_A_RAS# (13) SB_DQ_48 SB_RCVEN#
DDR_A_D49 AY7 AY20 SA_RCVEN# DDR_B_D49 BH5 T15 PAD
DDR_A_D50 SA_DQ_49 SA_RCVEN# T16 PAD DDR_B_D50 SB_DQ_49 DDR_B_WE#
AT5 SA_DQ_50 BG1 SB_DQ_50 SB_WE# BC17 DDR_B_WE# (14)
DDR_A_D51 AT7 BA19 DDR_A_WE# DDR_A_WE# (13) DDR_B_D51 BC2
DDR_A_D52 SA_DQ_51 SA_WE# DDR_B_D52 SB_DQ_51
AY6 SA_DQ_52 BK3 SB_DQ_52
DDR_A_D53 BB7 DDR_B_D53 BE4
DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
AR5 SA_DQ_54 BD3 SB_DQ_54
DDR_A_D55 AR8 DDR_B_D55 BJ2
DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
AR9 SA_DQ_56 BA3 SB_DQ_56
DDR_A_D57 AN3 DDR_B_D57 BB3
DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
AM8 SA_DQ_58 AR1 SB_DQ_58
DDR_A_D59 AN10 DDR_B_D59 AT3
DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
AT9 SA_DQ_60 AY2 SB_DQ_60
B DDR_A_D61 AN9 DDR_B_D61 AY3 B
DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
AM9 SA_DQ_62 AU2 SB_DQ_62
DDR_A_D63 AN11 DDR_B_D63 AT2
SA_DQ_63 SB_DQ_63
CRESTLINE_1p0 CRESTLINE_1p0
UMA@ UMA@

SA00000ZWA0 SA00000ZWA0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((2/6)-DDR2 A/B CH
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 8 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS
Strap Pin Table

1
R52 R53 010 = FSB 800MHz
2.2K_0402_5% 2.2K_0402_5%
UMA@ UMA@ CFG[2:0] FSB Freq select 011 = FSB 667MHz
EDID_CLK_LCD

2
(22) EDID_CLK_LCD Others = Reserved
EDID_DAT_LCD
(22) EDID_DAT_LCD
PEGCOMP trace width
and spacing is 20/25 mils. 0 = DMI x 2
U3C CFG5 (DMI select)
D D
1 = DMI x 4
(22) GMCH_ENBKL GMCH_ENBKL
J40
H39
L_BKLT_CTRL
N43
R55 +VCC_PEG
24.9_0402_1%
*
R54 1 L_BKLT_EN PEG_COMPI
+3VS 2 10K_0402_5% E39 L_CTRL_CLK PEG_COMPO M43 PEGCOMP 1 2 CFG6 Reserved
R56 1 2 10K_0402_5% E40 L_CTRL_DATA PEG_RXN[0..15] (17)
EDID_CLK_LCD C37
EDID_DAT_LCD L_DDC_CLK PEG_RXN0
D35 L_DDC_DATA PEG_RX#_0 J51 CFG7 (CPU Strap) 0 = Reserved
(22) GMCH_LVDDEN GMCH_LVDDEN K40 L51 PEG_RXN1
L_VDD_EN PEG_RX#_1 PEG_RXN2
N47 1 = Mobile CPU
R57
2 1
2.4K_0402_1%
L41
L43
LVDS_IBG
PEG_RX#_2
PEG_RX#_3 T45
T50
PEG_RXN3
PEG_RXN4
*
LVDS_VBG PEG_RX#_4 PEG_RXN5
N41 LVDS_VREFH PEG_RX#_5 U40 0 = Normal mode
N40 Y44 PEG_RXN6 CFG8 (Low power PCIE)
LVDSAC- LVDS_VREFL PEG_RX#_6 PEG_RXN7
For Crestline:2.4kohm D46 Y40 1 = Low Power mode
For Calero: 1.5Kohm
LVDSAC-
LVDSAC+
LVDSAC+ C45
D44
LVDSA_CLK#
LVDSA_CLK
PEG_RX#_7
PEG_RX#_8 AB51
W49
PEG_RXN8
PEG_RXN9
*
LVDSB_CLK# PEG_RX#_9 PEG_RXN10
E42 LVDSB_CLK PEG_RX#_10 AD44 CFG9 0 = Reverse Lane

LVDS
AD40 PEG_RXN11
LVDSA0- PEG_RX#_11 PEG_RXN12
G51 AG46 (PCIE Graphics Lane Reversal) 1 = Normal Operation
LVDSA0-
LVDSA1-
LVDSA1-
LVDSA2-
E51
F49
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_12
PEG_RX#_13 AH49
AG45
PEG_RXN13
PEG_RXN14
*
LVDSA2- LVDSA_DATA#_2 PEG_RX#_14
AG41 PEG_RXN15
PEG_RX#_15 PEG_RXP[0..15] (17)
CFG[11:10] Reserved

GRAPHICS
LVDSA0+ LVDSA0+ G50 J50 PEG_RXP0
LVDSA1+ LVDSA_DATA_0 PEG_RX_0 PEG_RXP1
LVDSA1+ E50 L50
LVDSA2+ F48
LVDSA_DATA_1 PEG_RX_1
M47 PEG_RXP2 00 = Reserved
LVDSA2+ LVDSA_DATA_2 PEG_RX_2 01 = XOR Mode Enabled
U44 PEG_RXP3 CFG[13:12] (XOR/ALLZ)
PEG_RX_3
PEG_RX_4 T49 PEG_RXP4 10 = All Z Mode Enabled
G44 T41 PEG_RXP5 11 = Normal Operation (Default)
B47
B45
LVDSB_DATA#_0
LVDSB_DATA#_1
PEG_RX_5
PEG_RX_6 W45
W41
PEG_RXP6
PEG_RXP7
*
LVDSB_DATA#_2 PEG_RX_7 PEG_RXP8
C PEG_RX_8 AB50 CFG[15:14] Reserved C
Y48 PEG_RXP9
PEG_RX_9 PEG_RXP10
E44 LVDSB_DATA_0 PEG_RX_10 AC45
A47 AC41 PEG_RXP11 CFG16 (FSB Dynamic ODT) 0 = Disabled
2006/09/13 A45
LVDSB_DATA_1
LVDSB_DATA_2
PEG_RX_11
PEG_RX_12 AH47 PEG_RXP12
AG49 PEG_RXP13 1 = Enabled

PCI-EXPRESS
PEG_RX_13
PEG_RX_14 AH45
AG42
PEG_RXP14
PEG_RXP15 PEG_M_TXN[0..15] (17)
*
PEG_RX_15
CFG[18:17] Reserved
(16) TV_COMPS TV_COMPS E27 N45 PEG_TXN0 C64 VGA@ 0.1U_0402_16V7K PEG_M_TXN0
TV_LUMA TVA_DAC PEG_TX#_0 PEG_TXN1 C65 VGA@ 0.1U_0402_16V7K PEG_M_TXN1
(16) TV_LUMA G27 TVB_DAC PEG_TX#_1 U39
1 2 TV_COMPS TV_CRMA K27 U47 PEG_TXN2 C66 VGA@ 0.1U_0402_16V7K PEG_M_TXN2 0 = No SDVO Device Present
R598 UMA@ 150_0402_1%
1 2 TV_LUMA
(16) TV_CRMA
F27
TVC_DAC
TV PEG_TX#_2
PEG_TX#_3 N51
R50
PEG_TXN3
PEG_TXN4
C67
C68
VGA@
VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
PEG_M_TXN3
PEG_M_TXN4
SDVO_CTRLDATA
1 = SDVO Device Present
*
R58 UMA@ 150_0402_1% TVA_RTN PEG_TX#_4 PEG_TXN5 C69 VGA@ 0.1U_0402_16V7K PEG_M_TXN5
J27 TVB_RTN PEG_TX#_5 T42
1 2 TV_CRMA L27 Y43 PEG_TXN6 C70 VGA@ 0.1U_0402_16V7K PEG_M_TXN6
R59 UMA@ 150_0402_1% TVC_RTN PEG_TX#_6 PEG_TXN7 C71 VGA@ 0.1U_0402_16V7K PEG_M_TXN7
W46 0 = Normal Operation
1 2
M35
P33
TV_DCONSEL_0
PEG_TX#_7
PEG_TX#_8 W38
AD39
PEG_TXN8
PEG_TXN9
C72
C73
VGA@
VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
PEG_M_TXN8
PEG_M_TXN9
CFG19 (DMI Lane Reversal) (Lane number in Order) *
2006/08/30 +3VS
R60 2.2K_0402_5% TV_DCONSEL_1 PEG_TX#_9
PEG_TX#_10 AC46 PEG_TXN10 C74 VGA@ 0.1U_0402_16V7K PEG_M_TXN10 1 = Reverse Lane
AC49 PEG_TXN11 C75 VGA@ 0.1U_0402_16V7K PEG_M_TXN11
PEG_TX#_11 PEG_TXN12 C76 VGA@ 0.1U_0402_16V7K PEG_M_TXN12
PEG_TX#_12 AC42
AH39 PEG_TXN13 C77 VGA@ 0.1U_0402_16V7K PEG_M_TXN13 0 = Only PCIE or SDVO is operational.
PEG_TX#_13
PEG_TX#_14 AE49
AH44
PEG_TXN14
PEG_TXN15
C78
C79
VGA@
VGA@
0.1U_0402_16V7K
0.1U_0402_16V7K
PEG_M_TXN14
PEG_M_TXN15 PEG_M_TXP[0..15] (17)
CFG20 (PCIE/SDVO concurrent)
1 = PCIE/SDVO are operating simu.
*
PEG_TX#_15
1 2 CRT_R CRT_B H32 M45 PEG_TXP0 C80 VGA@ 0.1U_0402_16V7K PEG_M_TXP0
(16) CRT_B CRT_BLUE PEG_TX_0
R61 UMA@ 150_0402_1% G32 T38 PEG_TXP1 C81 VGA@ 0.1U_0402_16V7K PEG_M_TXP1
CRT_G CRT_G CRT_BLUE# PEG_TX_1 PEG_TXP2 C82 VGA@ 0.1U_0402_16V7K PEG_M_TXP2
1 2 (16) CRT_G K29 CRT_GREEN PEG_TX_2 T46
R62 UMA@ 150_0402_1% J29 N50 PEG_TXP3 C83 VGA@ 0.1U_0402_16V7K PEG_M_TXP3
CRT_B CRT_R CRT_GREEN# PEG_TX_3 PEG_TXP4 C84 VGA@ 0.1U_0402_16V7K PEG_M_TXP4
1 2 (16) CRT_R F29 CRT_RED PEG_TX_4 R51
VGA

R63 UMA@ 150_0402_1% E29 U43 PEG_TXP5 C85 VGA@ 0.1U_0402_16V7K PEG_M_TXP5
CRT_RED# PEG_TX_5 PEG_TXP6 C86 VGA@ 0.1U_0402_16V7K PEG_M_TXP6 R64
PEG_TX_6 W42 (7) CFG5 1 2 @ 4.02K_0402_1%
B Y47 PEG_TXP7 C87 VGA@ 0.1U_0402_16V7K PEG_M_TXP7 B
3VDDCCL PEG_TX_7 PEG_TXP8 C88 VGA@ 0.1U_0402_16V7K PEG_M_TXP8
(16) 3VDDCCL K33 CRT_DDC_CLK PEG_TX_8 Y39
3VDDCDA G35 AC38 PEG_TXP9 C89 VGA@ 0.1U_0402_16V7K PEG_M_TXP9 R65 1 2 @ 4.02K_0402_1%
(16) 3VDDCDA CRT_DDC_DATA PEG_TX_9 (7) CFG7
(16) CRT_HSYNC CRT_HSYNC 1 2 HSYNC_R F33 AD47 PEG_TXP10 C90 VGA@ 0.1U_0402_16V7K PEG_M_TXP10
R66 UMA@ 39_0402_1% CRT_HSYNC PEG_TX_10 PEG_TXP11 C91 VGA@ 0.1U_0402_16V7K PEG_M_TXP11
C32 CRT_TVO_IREF PEG_TX_11 AC50
(16) CRT_VSYNC CRT_VSYNC 1 2 VSYNC_R E33 AD43 PEG_TXP12 C92 VGA@ 0.1U_0402_16V7K PEG_M_TXP12 R68 1 2 @ 4.02K_0402_1%
CRT_VSYNC PEG_TX_12 (7) CFG8
R67 UMA@ 39_0402_1% AG39 PEG_TXP13 C93 VGA@ 0.1U_0402_16V7K PEG_M_TXP13
PEG_TX_13
1

AE50 PEG_TXP14 C94 VGA@ 0.1U_0402_16V7K PEG_M_TXP14

PEG_TX_14 PEG_TXP15 C95 VGA@ 0.1U_0402_16V7K PEG_M_TXP15 R70
PEG_TX_15 AH43 (7) CFG9 1 2 @ 4.02K_0402_1%
R69
1.3K_0402_1%
CRESTLINE_1p0 R71 1 2 @ 4.02K_0402_1%
(7) CFG12
UMA@
2

SA00000ZWA0 R72 1 2 @ 4.02K_0402_1%

(7) CFG13
R598 R58 R59
For Crestline:1.3kohm R73 1 2 @ 4.02K_0402_1%
(7) CFG16
For Calero: 255ohm
+3VS CFG[17:3] have internal pull up
0_0402_5% 0_0402_5% 0_0402_5%
VGA@ VGA@ VGA@ CFG[19:18] have internal pull down
R602 4.7K_0402_5% R61 R62 R63
1 2 3VDDCCL +3VS
R603 4.7K_0402_5%
1 2 3VDDCDA
R74 1 2 @ 4.02K_0402_1%
(7) CFG19
0_0402_5% 0_0402_5% 0_0402_5%
A VGA@ VGA@ VGA@ R75 1 2 @ 4.02K_0402_1% A
2006/09/06 (7) CFG20

2006/09/18

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((3/6)-VGA/LVDS/TV
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 9 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS VCCSYNC
+3VS L43 +3VS_DAC_BG R76
BLM18PG121SN1D_0603 2 1
2 1 0_0603_5%

0.022U_0402_16V7K

0.1U_0402_16V4Z
1 +1.25VS
+1.25VS_DPLLB

0.1U_0402_16V4Z

4.7U_0805_10V4Z
UMA@ C96 +V1.25VS_AXF
1 1 1 1
+VCCP R78 2006/12/07
1 2 +1.25VS 1 2
2

C97

C98

0.1U_0402_16V4Z

10U_0805_10V4Z

1U_0603_10V4Z
C99
UMA@ C1190 U3H

10U_0805_10V4Z
10U_0805_6.3V6M 0_0805_5% R79
2 2 2 2 330U_D2E_2.5VM_R7 0_0603_5%
J32 VCCSYNC VTT_1 U13 1 1 1 1

4.7U_0805_10V4Z

C100

C102

C103
UMA@ U12
VTT_2

C101
A33 VCCA_CRT_DAC_1 VTT_3 U11 1 1
+3VS_DAC_CRT B33 VCCA_CRT_DAC_2 VTT_4 U9
2 2 2 2

C105
U8 C104 +
VTT_5

CRT
U7 0316 add
VTT_6 2
D
+3VS_DAC_CRT +3VS_DAC_BG A30 VCCA_DAC_BG VTT_7 U5 D
+3VS 2
VTT_8 U3
R80 B32 U2 0316 add
VSSA_DAC_BG VTT_9
1 2 VTT_10 U1
0.022U_0402_16V7K

0_0603_5% T13
VTT_11 +1.25VS_DMI +1.8V_SM_CK

VTT
0.1U_0402_16V4Z

UMA@ +1.25VS_DPLLA B49 T11 +1.25VS +1.8V

VCCA_DPLLA VTT_12

0.47U_0603_10V7K

4.7U_0805_10V4Z

2.2U_0805_16V4Z
1 1 T10 R82
VTT_13
+1.25VS_DPLLB H49 VCCA_DPLLB VTT_14 T9 1 1 1 1 2 1 2
C106

C107

22U_0805_6.3V4Z

22U_0805_6.3V4Z

0.1U_0402_16V4Z
UMA@ UMA@ T7 0_0805_5%
VTT_15

PLL

0.1U_0402_16V4Z
C108

C109

C110
+1.25VS_HPLL AL2 T6 R81 1 1
2 2 VCCA_HPLL VTT_16 0_0603_5%
VTT_17 T5 1
2 2 2

C111

C112

C113
+1.25VS_MPLL AM2 VCCA_MPLL VTT_18 T3 1

C114
VTT_19 T2
2 2
VTT_20 R3
2

A LVDS
+1.8V_TXLVDS 1000P_0402_50V7K A41 R2
VCCA_LVDS VTT_21 2
1 VTT_22 R1
C115 +1.25VS_AXD
B41 VSSA_LVDS R83
+3VS_PEG_BG
VCC_AXD_1 AT23 1 2 +1.25VS
R84 2 0_0805_5%
VCC_AXD_2 AU28

1U_0603_10V4Z

10U_0805_10V6K
+3VS 2 1 K50 VCCA_PEG_BG VCC_AXD_3 AU24 1 1
+1.25VS_PEGPLL

AXD

C116

C117
0_0603_5% AT29 +1.25VS
VCC_AXD_4 L1 +1.5VS_TVDAC +1.5VS
1 K49 VSSA_PEG_BG VCC_AXD_5 AT25

A PEG
0.1U_0402_16V4Z AT30 BLM18PG121SN1D_0603 R85
VCC_AXD_6 2 2
2 1 1 2

0.022U_0402_16V7K

0.1U_0402_16V4Z
C118
2 +1.25VS_PEGPLL 20 mils U51 VCCA_PEG_PLL VCC_AXD_NCTF AR29 0_0805_5%

0.1U_0402_16V4Z

10U_0805_10V4Z
1 1 1 1

C119

C120
AW18 VCCA_SM_1 VCC_AXF_1 B23 +V1.25VS_AXF

C121

C122
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2

AXF
AU19 VCCA_SM_3 VCC_AXF_3 A21
2 2 2 2
+1.25VS_A_SM AU18 VCCA_SM_4
AU17 VCCA_SM_5 VCC_DMI AJ50 +1.25VS_DMI
R86 0317 change value

A SM
C +1.25VS 1 2 AT22 VCCA_SM_7 C
1 0_0805_5% AT21 BK24 +1.8V_SM_CK
VCCA_SM_8 VCC_SM_CK_1

SM CK
1 1 1 AT19 VCCA_SM_9 VCC_SM_CK_2 BK23
C123

+ C124 C125 C126 AT18 BJ24

VCCA_SM_10 VCC_SM_CK_3
AT17 VCCA_SM_11 VCC_SM_CK_4 BJ23
22U_0805_6.3V4Z 4.7U_0805_6.3V6K AR17 +1.25VS_HPLL
220U_D2_4VM_R15 2 2 2 2 VCCA_SM_NCTF_1 +1.25VS_DPLLA L44 +1.25VS
AR16
R89 +1.25VS_A_SM_CK
1U_0603_10V4Z VCCA_SM_NCTF_2 R87 2006/12/07
VCC_TX_LVDS A43 +1.8V_TXLVDS 1 2 +1.25VS 2 1

A CK

0.1U_0402_16V4Z

10U_0805_10V6K
2 1 BC29 MBK2012121YZF_0805
VCCA_SM_CK_1 +3VS_HV
1U_0402_6.3V4Z

22U_0805_6.3V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

0_0603_5% BB29 0_0805_5%

VCCA_SM_CK_2
VCC_HV_1 C40 1 1 1 1

C127

C128
1 1 1 1 +3VS_TVDACA C25 B40 C129 C130
VCCA_TVA_DAC_1 VCC_HV_2
C131

C132

C133

C134

HV
B25 VCCA_TVA_DAC_2

0.1U_0402_16V4Z
+3VS_TVDACB C27 0.1U_0402_16V4Z 10U_0805_10V4Z
VCCA_TVB_DAC_1 2 2 2 2
B27 VCCA_TVB_DAC_2 VCC_PEG_1 AD51 +VCC_PEG 1
2 2 2 2
TV

C135
0316 add B28 W50
+3VS_TVDACC VCCA_TVC_DAC_1 VCC_PEG_2

PEG
A28 W51 0316 add
VCCA_TVC_DAC_2 VCC_PEG_3
VCC_PEG_4 V49
0317 change value 2
VCC_PEG_5 V50
D TV/CRT

M32 VCCD_CRT
+1.5VS_TVDAC L29 VCCD_TVDAC
VCC_RXR_DMI_1 AH50 +VCCP +1.25VS_MPLL
DMI

+1.5VS_QDAC N28 VCCD_QDAC VCC_RXR_DMI_2 AH51 04/10 stuff

20mils +VCC_PEG L45 +1.25VS
+1.25VS_HPLL AN2 R90
VCCD_HPLL
VTTLF1 A7 2 1 2 1
VTTLF

+1.25VS_PEGPLL U48 F2 0_0805_5% MBK2012121YZF_0805

VCCD_PEG_PLL VTTLF2

10U_0805_10V4Z

10U_0805_10V4Z
VTTLF3 AH1 1

220U_D2_4VM
J41 VCCD_LVDS_1 1 1 +1.25VS 1 1
LVDS

0.47U_0603_10V7K

0.47U_0603_10V7K

0.47U_0603_10V7K

C1176

C137

C138
H42 + C139 C140
+1.8V_LVDS VCCD_LVDS_2
1 1 1 @ R92
C141

C142

C143
2 1 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 0_0805_5% 2 2
+3VS_TVDACC +3VS CRESTLINE_1p0
B R93 UMA@ 2 2 2 0316 add 04/10 no stuff B
2 1
0.022U_0402_16V7K

0_0603_5% SA00000ZWA0
0.1U_0402_16V4Z

UMA@
1 1
C144

C145

+VCCP_D
2 2

D3 R94 R95
UMA@ UMA@ +VCCP 2 1 2 1 2 1 +3VS_HV
10_0402_5% 0_0402_5%
CH751H-40PT_SOD323-2
+3VS
+1.5VS_QDAC +1.5VS
+3VS_TVDACA +3VS R96
R97
2 1
0.022U_0402_16V7K

2 1 0_0603_5%
0.022U_0402_16V7K

0.1U_0402_16V4Z

0_0603_5% UMA@
+1.8V_TXLVDS
0.1U_0402_16V4Z

UMA@ 1 1 40 mils
1 1 R98
C146

C147
C148

C149

1000P_0402_50V7K 2 1 +1.8V
2 2 0_0603_5%
2 2 UMA@
1
1 220U_D2_4VM_R15
UMA@ UMA@ C155 + C154
UMA@ UMA@ UMA@ UMA@
2 2

+1.8V_LVDS
A +3VS_TVDACB +3VS A
R99 R100
2 1 2 1 +1.8V
0.022U_0402_16V7K

10U_0805_10V6K

0_0603_5% 0_0603_5%
0.1U_0402_16V4Z

1U_0603_10V4Z

UMA@ 1 1 UMA@
C160

C161

1 1
C162

C163

2 2
2 2
UMA@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
UMA@
UMA@ UMA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE(4/6)-PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT10/11 LA-3591P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 10 of 48
5 4 3 2 1
 5 4 3 2 1

+VCCP
U3G +VCCP

AT35 VCC_1 Check : power

AT34 VCC_2 VCC_AXG_NCTF_1 T17
AH28 VCC_3 VCC_AXG_NCTF_2 T18
AC32 T19 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
VCC_5 VCC_AXG_NCTF_3
AC31 VCC_4 VCC_AXG_NCTF_4 T21
AK32 VCC_6 VCC_AXG_NCTF_5 T22 1 C164 1 1

C165
AJ31 T23 C166
+VCCP VCC_7 VCC_AXG_NCTF_6
AJ28 VCC_8 VCC_AXG_NCTF_7 T25
D U3F AH32 U15 D
VCC_9 VCC_AXG_NCTF_8 2 2 2

VCC CORE
AH31 VCC_10 VCC_AXG_NCTF_9 U16
AB33 VCC_NCTF_1 AH29 VCC_11 VCC_AXG_NCTF_10 U17
AB36 AF32 U19 0.22U_0402_10V4Z
VCC_NCTF_2 VCC_12 VCC_AXG_NCTF_11
AB37 VCC_NCTF_3 VCC_AXG_NCTF_12 U20
AC33 VCC_NCTF_4 VSS_NCTF_1 T27 VCC_AXG_NCTF_13 U21
AC35 T37 R101 U23
VCC_NCTF_5 VSS_NCTF_2 VCC_AXG_NCTF_14
AC36 VCC_NCTF_6 VSS_NCTF_3 U24 1 2 R30 VCC_13 VCC_AXG_NCTF_15 U26
AD35 U28 0_0603_5% V16
VCC_NCTF_7 VSS_NCTF_4 VCC_AXG_NCTF_16
AD36 VCC_NCTF_8 VSS_NCTF_5 V31 VCC_AXG_NCTF_17 V17
AF33 VCC_NCTF_9 VSS_NCTF_6 V35 VCC_AXG_NCTF_18 V19
AF36 VCC_NCTF_10 VSS_NCTF_7 AA19 VCC_AXG_NCTF_19 V20
220U_D2_4VM_R15

22U_0805_6.3V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

AH33 VCC_NCTF_11 VSS_NCTF_8 AB17 VCC_AXG_NCTF_20 V21

VSS NCTF
1 AH35 VCC_NCTF_12 VSS_NCTF_9 AB35 VCC_AXG_NCTF_21 V23
1 1 1 1 AH36 VCC_NCTF_13 VSS_NCTF_10 AD19 VCC_AXG_NCTF_22 V24
C167

C168

C169

C170

C171

+ AH37 AD37 Y15

2 2 2 2 2
AJ33
AJ35
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
AF17
AF35
POWER VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
Y16
Y17
AK33 VCC_NCTF_17 VSS_NCTF_14 AK17 AU32 VCC_SM_1 VCC_AXG_NCTF_26 Y19
AK35 AM17 330U_D2E_2.5VM_R7 AU33 Y20
VCC_NCTF_18 VSS_NCTF_15 VCC_SM_2 VCC_AXG_NCTF_27
AK36 VCC_NCTF_19 VSS_NCTF_16 AM24 +1.8V AU35 VCC_SM_3 VCC_AXG_NCTF_28 Y21
AK37 VCC_NCTF_20 VSS_NCTF_17 AP26 AV33 VCC_SM_4 VCC_AXG_NCTF_29 Y23

0.01U_0402_16V7K
AD33 VCC_NCTF_21 VSS_NCTF_18 AP28 AW33 VCC_SM_5 VCC_AXG_NCTF_30 Y24

22U_0805_6.3V4Z

22U_0805_6.3V4Z
AJ36 VCC_NCTF_22 VSS_NCTF_19 AR15 1 AW35 VCC_SM_6 VCC_AXG_NCTF_31 Y26

VCC NCTF
AM35 VCC_NCTF_23 VSS_NCTF_20 AR19 1 1 2 AY35 VCC_SM_7 VCC_AXG_NCTF_32 Y28

C173

C174

C175
AL33 AR28 C172 + BA32 Y29
VCC_NCTF_24 VSS_NCTF_21 VCC_SM_8 VCC_AXG_NCTF_33
AL35 VCC_NCTF_25 BA33 VCC_SM_9 VCC_AXG_NCTF_34 AA16
AA33 VCC_NCTF_26 BA35 VCC_SM_10 VCC_AXG_NCTF_35 AA17
2 2 2 1
AA35 VCC_NCTF_27 BB33 VCC_SM_11 VCC_AXG_NCTF_36 AB16
AA36 VCC_NCTF_28 BC32 VCC_SM_12 VCC_AXG_NCTF_37 AB19
AP35 VCC_NCTF_29 BC33 VCC_SM_13 VCC_AXG_NCTF_38 AC16
AP36 VCC_NCTF_30 BC35 VCC_SM_14 VCC_AXG_NCTF_39 AC17

VCC SM
C C
AR35 VCC_NCTF_31 BD32 VCC_SM_15 VCC_AXG_NCTF_40 AC19
AR36 VCC_NCTF_32 BD35 VCC_SM_16 VCC_AXG_NCTF_41 AD15
Y32 VCC_NCTF_33 BE32 VCC_SM_17 VCC_AXG_NCTF_42 AD16
Y33 BE33 AD17
VCC_NCTF_34
POWER VCC_SM_18 VCC_AXG_NCTF_43

VCC GFX NCTF

Y35 VCC_NCTF_35 BE35 VCC_SM_19 VCC_AXG_NCTF_44 AF16
Y36 VCC_NCTF_36 BF33 VCC_SM_20 VCC_AXG_NCTF_45 AF19
Y37 VCC_NCTF_37 VSS_SCB1 A3 BF34 VCC_SM_21 VCC_AXG_NCTF_46 AH15
T30 VCC_NCTF_38 VSS_SCB2 B2 BG32 VCC_SM_22 VCC_AXG_NCTF_47 AH16
VSS SCB
T34 VCC_NCTF_39 VSS_SCB3 C1 BG33 VCC_SM_23 VCC_AXG_NCTF_48 AH17
T35 VCC_NCTF_40 VSS_SCB4 BL1 BG35 VCC_SM_24 VCC_AXG_NCTF_49 AH19
U29 VCC_NCTF_41 VSS_SCB5 BL51 BH32 VCC_SM_25 VCC_AXG_NCTF_50 AJ16
U31 VCC_NCTF_42 VSS_SCB6 A51 BH34 VCC_SM_26 VCC_AXG_NCTF_51 AJ17
U32 VCC_NCTF_43 BH35 VCC_SM_27 VCC_AXG_NCTF_52 AJ19
U33 VCC_NCTF_44 BJ32 VCC_SM_28 VCC_AXG_NCTF_53 AK16
U35 VCC_NCTF_45 BJ33 VCC_SM_29 VCC_AXG_NCTF_54 AK19
U36 VCC_NCTF_46 BJ34 VCC_SM_30 VCC_AXG_NCTF_55 AL16
V32 VCC_NCTF_47 BK32 VCC_SM_31 VCC_AXG_NCTF_56 AL17
V33 VCC_NCTF_48 BK33 VCC_SM_32 VCC_AXG_NCTF_57 AL19
V36 VCC_NCTF_49 BK34 VCC_SM_33 VCC_AXG_NCTF_58 AL20
V37 VCC_NCTF_50 BK35 VCC_SM_34 VCC_AXG_NCTF_59 AL21
BL33 VCC_SM_35 VCC_AXG_NCTF_60 AL23
+VCCP AT33 AU30 AM15
VCC_AXM_1 +VCCP VCC_SM_36 VCC_AXG_NCTF_61
VCC_AXM_2 AT31 VCC_AXG_NCTF_62 AM16
VCC AXM

VCC_AXM_3 AK29 VCC_AXG_NCTF_63 AM19

VCC_AXM_4 AK24 VCC_AXG_NCTF_64 AM20
10U_0805_10V4Z

10U_0805_10V4Z

VCC_AXM_5 AK23 VCC_AXG_NCTF_65 AM21

1 1 AL24 VCC_AXM_NCTF_1 VCC_AXM_6 AJ26 R20 VCC_AXG_1 VCC_AXG_NCTF_66 AM23
C176

C177

AL26 VCC_AXM_NCTF_2 VCC_AXM_7 AJ23 T14 VCC_AXG_2 VCC_AXG_NCTF_67 AP15

AL28 VCC_AXM_NCTF_3 W13 VCC_AXG_3 VCC_AXG_NCTF_68 AP16
AM26 +VCCP W14 AP17
2 2 VCC_AXM_NCTF_4 VCC_AXG_4 VCC_AXG_NCTF_69
VCC AXM NCTF

AM28 VCC_AXM_NCTF_5 Y12 VCC_AXG_5 VCC_AXG_NCTF_70 AP19

AM29 10U_0805_10V4Z 0.1U_0402_16V4Z AA20 AP20
B VCC_AXM_NCTF_6 VCC_AXG_6 VCC_AXG_NCTF_71 B
AM31 VCC_AXM_NCTF_7 AA23 VCC_AXG_7 VCC_AXG_NCTF_72 AP21
AM32 VCC_AXM_NCTF_8 AA26 VCC_AXG_8 VCC_AXG_NCTF_73 AP23
AM33 VCC_AXM_NCTF_9 1 1 1 1 AA28 VCC_AXG_9 VCC_AXG_NCTF_74 AP24
AP29 C180 AB21 AR20
VCC_AXM_NCTF_10 C181 C182 VCC_AXG_10 VCC_AXG_NCTF_75
AP31 VCC_AXM_NCTF_11 AB24 VCC_AXG_11 VCC_AXG_NCTF_76 AR21
AP32 C179 AB29 AR23
VCC_AXM_NCTF_12 1U_0402_6.3V4Z 2 2 2 2 VCC_AXG_12 VCC_AXG_NCTF_77
AP33 VCC_AXM_NCTF_13 AC20 VCC_AXG_13 VCC_AXG_NCTF_78 AR24

VCC GFX
AL29 VCC_AXM_NCTF_14 AC21 VCC_AXG_14 VCC_AXG_NCTF_79 AR26
AL31 10U_0805_10V4Z AC23 V26
VCC_AXM_NCTF_15 VCC_AXG_15 VCC_AXG_NCTF_80
AL32 VCC_AXM_NCTF_16 AC24 VCC_AXG_16 VCC_AXG_NCTF_81 V28
AR31 VCC_AXM_NCTF_17 AC26 VCC_AXG_17 VCC_AXG_NCTF_82 V29
AR32 VCC_AXM_NCTF_18 AC28 VCC_AXG_18 VCC_AXG_NCTF_83 Y31
0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

AR33 VCC_AXM_NCTF_19 AC29 VCC_AXG_19

1 1 1 1 1 AD20 VCC_AXG_20
C183

C184

C185

C186

C187

AD23 VCC_AXG_21
AD24 VCC_AXG_22 VCC_SM_LF1 AW45VCCSM_LF1
AD28 VCC_AXG_23 VCC_SM_LF2 BC39 VCCSM_LF2
2 2 2 2 2

VCC SM LF
CRESTLINE_1p0 AF21 BE39 VCCSM_LF3
UMA@ VCC_AXG_24 VCC_SM_LF3
AF26 VCC_AXG_25 VCC_SM_LF4 BD17 VCCSM_LF4
AA31 VCC_AXG_26 VCC_SM_LF5 BD4 VCCSM_LF5
SA00000ZWA0 AH20 VCC_AXG_27 VCC_SM_LF6 AW8 VCCSM_LF6
AH21 VCC_AXG_28 VCC_SM_LF7 AT6 VCCSM_LF7

C188 0.1U_0402_16V4Z

C189 0.1U_0402_16V4Z

C190 0.22U_0603_10V7K

C191 0.22U_0603_10V7K

C192 0.47U_0402_6.3V6K

C193 1U_0603_10V4Z

C194 1U_0603_10V4Z
AH23 VCC_AXG_29 1 1 1 1 1 1 1
AH24 VCC_AXG_30
AH26 VCC_AXG_31
AD31 VCC_AXG_32 2 2 2 2 2 2 2
AJ20 VCC_AXG_33
AN14 VCC_AXG_34

A A

CRESTLINE_1p0
UMA@

SA00000ZWA0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((5/6)-PWR/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 11 of 48
5 4 3 2 1
 5 4 3 2 1

U3I

A13 VSS_1 VSS_100 AW24

A15 VSS_2 VSS_101 AW29
A17 VSS_3 VSS_102 AW32
A24 VSS_4 VSS_103 AW5
AA21 VSS_5 VSS_104 AW7
AA24 VSS_6 VSS_105 AY10
AA29 VSS_7 VSS_106 AY24
AB20 AY37 U3J
D VSS_8 VSS_107 D
AB23 VSS_9 VSS_108 AY42 C46 VSS_199 VSS_287 W11
AB26 VSS_10 VSS_109 AY43 C50 VSS_200 VSS_288 W39
AB28 VSS_11 VSS_110 AY45 C7 VSS_201 VSS_289 W43
AB31 VSS_12 VSS_111 AY47 D13 VSS_202 VSS_290 W47
AC10 VSS_13 VSS_112 AY50 D24 VSS_203 VSS_291 W5
AC13 VSS_14 VSS_113 B10 D3 VSS_204 VSS_292 W7
AC3 VSS_15 VSS_114 B20 D32 VSS_205 VSS_293 Y13
AC39 VSS_16 VSS_115 B24 D39 VSS_206 VSS_294 Y2
AC43 VSS_17 VSS_116 B29 D45 VSS_207 VSS_295 Y41
AC47 VSS_18 VSS_117 B30 D49 VSS_208 VSS_296 Y45
AD1 VSS_19 VSS_118 B35 E10 VSS_209 VSS_297 Y49
AD21 VSS_20 VSS_119 B38 E16 VSS_210 VSS_298 Y5
AD26 VSS_21 VSS_120 B43 E24 VSS_211 VSS_299 Y50
AD29 VSS_22 VSS_121 B46 E28 VSS_212 VSS_300 Y11
AD3 VSS_23 VSS_122 B5 E32 VSS_213 VSS_301 P29
AD41 VSS_24 VSS_123 B8 E47 VSS_214 VSS_302 T29
AD45 VSS_25 VSS_124 BA1 F19 VSS_215 VSS_303 T31
AD49 VSS_26 VSS_125 BA17 F36 VSS_216 VSS_304 T33
AD5 VSS_27 VSS_126 BA18 F4 VSS_217 VSS_305 R28
AD50 VSS_28 VSS_127 BA2 F40 VSS_218
AD8 VSS_29 VSS_128 BA24 F50 VSS_219
AE10 VSS_30 VSS_129 BB12 G1 VSS_220
AE14 VSS_31 VSS_130 BB25 G13 VSS_221 VSS_306 AA32
AE6 VSS_32 VSS_131 BB40 G16 VSS_222 VSS_307 AB32
AF20 BB44 G19 AD32
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
G24
G28
VSS_223
VSS_224
VSS_225
VSS_308
VSS_309
VSS_310
AF28
AF29
AF31 VSS_36 VSS_135 BC16 G29 VSS_226 VSS_311 AT27
AG2 VSS_37 VSS_136 BC24 G33 VSS_227 VSS_312 AV25
AG38 VSS_38 VSS_137 BC25 G42 VSS_228 VSS_313 H50
AG43 VSS_39 VSS_138 BC36 G45 VSS_229
AG47 VSS_40 VSS_139 BC40 G48 VSS_230
C C
AG50 VSS_41 VSS_140 BC51 G8 VSS_231
AH3 VSS_42 VSS_141 BD13 H24 VSS_232
AH40 VSS_43 VSS_142 BD2 H28 VSS_233
AH41 VSS_44 VSS_143 BD28 H4 VSS_234
AH7 VSS_45 VSS_144 BD45 H45 VSS_235
AH9 VSS_46 VSS_145 BD48 J11 VSS_236
AJ11 VSS_47 VSS_146 BD5 J16 VSS_237
AJ13 VSS_48 VSS_147 BE1 J2 VSS_238
AJ21 VSS_49 VSS_148 BE19 J24 VSS_239
AJ24 VSS_50 VSS_149 BE23 J28 VSS_240
AJ29 BE30 J33
AJ32
AJ43
VSS_51
VSS_52
VSS_53
VSS_150
VSS_151
VSS_152
BE42
BE51
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AJ45 VSS_54 VSS_153 BE8
AJ49 VSS_55 VSS_154 BF12 K12 VSS_245
AK20 VSS_56 VSS_155 BF16 K47 VSS_246
AK21 VSS_57 VSS_156 BF36 K8 VSS_247
AK26 VSS_58 VSS_157 BG19 L1 VSS_248
AK28 VSS_59 VSS_158 BG2 L17 VSS_249
AK31 VSS_60 VSS_159 BG24 L20 VSS_250
AK51 VSS_61 VSS_160 BG29 L24 VSS_251
AL1 VSS_62 VSS_161 BG39 L28 VSS_252
AM11 VSS_63 VSS_162 BG48 L3 VSS_253
AM13 VSS_64 VSS_163 BG5 L33 VSS_254
AM3 VSS_65 VSS_164 BG51 L49 VSS_255
AM4 VSS_66 VSS_165 BH17 M28 VSS_256
AM41 VSS_67 VSS_166 BH30 M42 VSS_257
AM45 VSS_68 VSS_167 BH44 M46 VSS_258
AN1 VSS_69 VSS_168 BH46 M49 VSS_259
AN38 VSS_70 VSS_169 BH8 M5 VSS_260
AN39 VSS_71 VSS_170 BJ11 M50 VSS_261
AN43 VSS_72 VSS_171 BJ13 M9 VSS_262
B AN5 BJ38 N11 B
VSS_73 VSS_172 VSS_263
AN7 VSS_74 VSS_173 BJ4 N14 VSS_264
AP4 VSS_75 VSS_174 BJ42 N17 VSS_265
AP48 VSS_76 VSS_175 BJ46 N29 VSS_266
AP50 VSS_77 VSS_176 BK15 N32 VSS_267
AR11 VSS_78 VSS_177 BK17 N36 VSS_268
AR2 VSS_79 VSS_178 BK25 N39 VSS_269
AR39 VSS_80 VSS_179 BK29 N44 VSS_270
AR44 VSS_81 VSS_180 BK36 N49 VSS_271
AR47 VSS_82 VSS_181 BK40 N7 VSS_272
AR7 VSS_83 VSS_182 BK44 P19 VSS_273
AT10 VSS_84 VSS_183 BK6 P2 VSS_274
AT14 VSS_85 VSS_184 BK8 P23 VSS_275
AT41 VSS_86 VSS_185 BL11 P3 VSS_276
AT49 VSS_87 VSS_186 BL13 P50 VSS_277
AU1 VSS_88 VSS_187 BL19 R49 VSS_278
AU23 VSS_89 VSS_188 BL22 T39 VSS_279
AU29 VSS_90 VSS_189 BL37 T43 VSS_280
AU3 VSS_91 VSS_190 BL47 T47 VSS_281
AU36 VSS_92 VSS_191 C12 U41 VSS_282
AU49 VSS_93 VSS_192 C16 U45 VSS_283
AU51 VSS_94 VSS_193 C19 U50 VSS_284
AV39 VSS_95 VSS_194 C28 V2 VSS_285
AV48 VSS_96 VSS_195 C29 V3 VSS_286
AW1 VSS_97 VSS_196 C33
AW12 VSS_98 VSS_197 C36
AW16 C41 CRESTLINE_1p0
VSS_99 VSS_198 UMA@

CRESTLINE_1p0 SA00000ZWA0
UMA@

A A
SA00000ZWA0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRESTLINE((6/6)-PWR/GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 12 of 48
5 4 3 2 1
 5 4 3 2 1

Layout Note:
+1.8V +1.8V
+DDR_MCH_REF
trace width and +DDR_MCH_REF1
(8) DDR_A_DQS#[0..7] +DDR_MCH_REF1 (14)

(8) DDR_A_D[0..63]
spacing is 20/20. JP3

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
(8) DDR_A_DM[0..7] +1.8V VSS DQ4

C195

C196
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
(8) DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
VSS DM0

1
DDR_A_DQS#0 2 2
(8) DDR_A_MA[0..13] 11 DQS0# VSS 12
R102 DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
1K_0402_1% DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 DQ3 DQ12 20
+DDR_MCH_REF1 DDR_A_D12

2
(14) +DDR_MCH_REF1 21 VSS DQ13 22

0.1U_0402_16V4Z
DDR_A_D8 23 24
DQ8 VSS

1
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
R103 DQ9 DM1
1 27 VSS VSS 28
Place near JP41 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 (7)
DQS1# CK0

C197
1K_0402_1% DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 (7)
33 VSS VSS 34
2 DDR_A_D9 DDR_A_D11

2
35 DQ10 DQ14 36
DDR_A_D15 37 38 DDR_A_D10
DQ11 DQ15
39 VSS VSS 40

+1.8V 41 42
2006/08/31 DDR_A_D16 43
VSS
DQ16
VSS
DQ20 44 DDR_A_D20
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 (7)
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C199

C200

C201

C202

C203

C204

C205

C206

C207
+ C198 53 54
470U_D2_2.5VM_R15 DDR_A_D18 VSS VSS DDR_A_D23
55 DQ18 DQ22 56
DDR_A_D19 57 58 DDR_A_D22
2 2 2 2 2 2 2 2 2 2 DQ19 DQ23
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
(14,33) EC_TX_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
(7) DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA (7)
81 VDD VDD 82
(14,33) EC_RX_P80_CLK 83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14
(8) DDR_A_BS#2 BA2 NC/A14 DDR_A_MA14 (7)
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 A9 A7 92 DDR_A_MA7
DDR_A_MA8 93 94 DDR_A_MA6
resistors terminated to +0.9VS A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 (8)
DDR_A_BS#0 107 108 DDR_A_RAS#
(8) DDR_A_BS#0 BA0 RAS# DDR_A_RAS# (8)
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS (8) DDR_A_WE# WE# S0# DDR_CS0_DIMMA# (7)
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
(8) DDR_A_CAS# CAS# ODT0 M_ODT0 (7)
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
(7) DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

(7) M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D33
DDR_A_D36 DQ32 DQ36 DDR_A_D39
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C208

C209

C210

C211

C212

C213

C214

C215

C216

C217

C218

C219

C220

133 134 DDR_A_D35

DDR_A_D38 VSS DQ38 DDR_A_D34
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
+0.9VS DDR_A_D48 DQ48 DQ52 DDR_A_D53
Layout Note: (14) EC_RX_P80_CLK_R 159 DQ49 DQ53 160
RP22 161 162
RP21 56_0404_4P2R_5% 56_0404_4P2R_5% Place these resistor EC_RX_P80_CLK 1 EC_RX_P80_CLK_R VSS VSS M_CLK_DDR1
2 163 NC,TEST CK1 164 M_CLK_DDR1 (7)
DDR_A_CAS# 1 4 1 4 DDR_A_BS#1 closely JP3,all R104 0_0402_5% 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 (7)
DDR_A_WE# 2 3 2 3 DDR_A_RAS# trace length Max=1.5" DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
M_ODT1 1 4 1 4 M_ODT0 171 172
DDR_CS1_DIMMA# VSS VSS
2 3 2 3 DDR_A_MA13 DDR_A_D54 173 DQ50 DQ54 174 DDR_A_D51
RP24 DDR_A_D50 175 176 DDR_A_D55
RP23 56_0404_4P2R_5% RP2556_0404_4P2R_5% DQ51 DQ55
177 VSS VSS 178
R105 1
DDR_CKE1_DIMMA 2 56_0404_4P2R_5% DDR_A_D61 179 180 DDR_A_D57
56_0402_5% DQ56 DQ60
1 4 DDR_CS0_DIMMA# DDR_A_D60 181 DQ57 DQ61 182 DDR_A_D56
RP26 56_0404_4P2R_5%
2 3 DDR_A_MA4 183 184
DDR_A_MA10 DDR_A_DM7 VSS VSS DDR_A_DQS#7
1 4 185 DM7 DQS7# 186
DDR_A_MA3 2 3 1 4 DDR_A_MA2 187 188 DDR_A_DQS7
VSS DQS7
2 3 DDR_A_MA0 DDR_A_D59 189 DQ58 VSS 190
RP27 DDR_A_D58 191 192 DDR_A_D62
RP28 56_0404_4P2R_5% DQ59 DQ62 DDR_A_D63
193 VSS DQ63 194
56_0404_4P2R_5% RP29 56_0404_4P2R_5% CLK_SMBDATA 195 196
(14,15) CLK_SMBDATA SDA VSS
DDR_A_BS#0 1 4 1 4 DDR_A_MA7 CLK_SMBCLK 197 198
(14,15) CLK_SMBCLK SCL SA0
DDR_A_MA1 2 3 2 3 DDR_A_MA6 199 200
+3VS VDDSPD SA1

1
10K_0402_5%
10K_0402_5%
DDR_A_MA8 1 4 1 4 DDR_A_MA11 1
DDR_A_MA5 2 3 2 3DDR_A_MA14 C221 FOX_ASOA426-M2RN-7F

R108

R109
A RP30 A
ME@
56_0404_4P2R_5% RP3156_0404_4P2R_5% 0.1U_0402_16V4Z
RP32 56_0404_4P2R_5% 2
DDR_A_MA9 SO-DIMM A

2
1 4
DDR_A_MA12 2 3

DDR_CKE0_DIMMA 1 4 Top side

DDR_A_BS#2 2 3

RP3356_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 13 of 48
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
(8) DDR_B_DQS#[0..7]

(8) DDR_B_D[0..63]
+DDR_MCH_REF1
+DDR_MCH_REF1 (13)
(8) DDR_B_DM[0..7] JP4

2.2U_0805_16V4Z

0.1U_0402_16V4Z
(8) DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D5
(8) DDR_B_MA[0..13] 5 DQ0 DQ5 6

C222

C223
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 17 18 D
DDR_B_D3 DQ2 VSS DDR_B_D12
Layout Note: 19 DQ3 DQ12 20
DDR_B_D13
21 VSS DQ13 22
Place near JP42 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 26
27
DQ9
VSS
DM1
VSS 28 2006/12/07
DDR_B_DQS#1 29 30 M_CLK_DDR2
DQS1# CK0 M_CLK_DDR2 (7)
DDR_B_DQS1 31 32 M_CLK_DDR#2
DQS1 CK0# M_CLK_DDR#2 (7)
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C225

C226

C227

C228

C229

C230

C231

C232

C233
+ C224 47 48
470U_D2_2.5VM_R15 DDR_B_DQS#2 VSS VSS
49 DQS2# NC 50 PM_EXTTS#1 (7)
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D25 61 62 DDR_B_D26
DDR_B_D28 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
(13,33) EC_TX_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
(7) DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB (7)
81 VDD VDD 82
Layout Note: (13,33) EC_RX_P80_CLK
DDR_B_BS#2
83 NC NC/A15 84
DDR_B_MA14
(8) DDR_B_BS#2 85 BA2 NC/A14 86 DDR_B_MA14 (7)
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 (8)
DDR_B_BS#0 107 108 DDR_B_RAS#
(8) DDR_B_BS#0 BA0 RAS# DDR_B_RAS# (8)
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
(8) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (7)
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
(8) DDR_B_CAS# CAS# ODT0 M_ODT2 (7)
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

(7) DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 M_ODT3 119 120
(7) M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C236

C238

C239

C240

C241

C242

C244

C245

C246

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 141 142 DDR_B_D45 B
DDR_B_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 160
+0.9VS Place these resistor 161
DQ49
VSS
DQ53
VSS 162 2006/12/07
EC_RX_P80_CLK_R 163 164 M_CLK_DDR3
(13) EC_RX_P80_CLK_R NC,TEST CK1 M_CLK_DDR3 (7)
closely JP4,all 165 166 M_CLK_DDR#3
M_CLK_DDR#3 (7)
RP34 56_0404_4P2R_5%
RP35 56_0404_4P2R_5% DDR_B_DQS#6 VSS CK1#
trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_WE# 1 4 1 4 DDR_B_MA13 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_CAS# M_ODT2 DQS6 DM6
2 3 2 3 171 VSS VSS 172
DDR_B_D51 173 174 DDR_B_D54
DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_B_D50 DQ50 DQ54 DDR_B_D55
1 4 1 4 175 DQ51 DQ55 176
M_ODT3 2 3 2 3 DDR_B_RAS# 177 178
DDR_B_D56 VSS VSS DDR_B_D60
179 DQ56 DQ60 180
RP36 56_0404_4P2R_5%
RP37 56_0404_4P2R_5% DDR_B_D61 181 182 DDR_B_D57
DDR_B_MA14 R110 1 RP38 56_0404_4P2R_5% DQ57 DQ61
2 183 VSS VSS 184
56_0402_5% 1 4 DDR_B_BS#1 DDR_B_DM7 185 186 DDR_B_DQS#7
RP39 56_0404_4P2R_5% DDR_B_MA0 DM7 DQS7# DDR_B_DQS7
2 3 187 VSS DQS7 188
DDR_B_BS#0 1 4 DDR_B_D58 189 190
DDR_B_MA10 DDR_B_MA4 DDR_B_D59 DQ58 VSS DDR_B_D62
2 3 1 4 191 DQ59 DQ62 192
2 3 DDR_B_MA2 193 194 DDR_B_D63
CLK_SMBDATA VSS DQ63
(13,15) CLK_SMBDATA 195 SDA VSS 196
RP40 56_0404_4P2R_5% CLK_SMBCLK 197 198 R113
(13,15) CLK_SMBCLK SCL SAO
RP41 56_0404_4P2R_5%
RP42 56_0404_4P2R_5% 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_MA1 1 4 1 4 DDR_B_MA7

1
10K_0402_5%
DDR_B_MA3 2 3 2 3 DDR_B_MA6 1 10K_0402_5%

R114
A C247 P-TWO_A5692B-A0G16-P A
DDR_B_MA9 1 4 1 4 DDR_B_MA11 ME@
DDR_B_MA5 2 3 2 3 DDR_CKE3_DIMMB 0.1U_0402_16V4Z

RP43 56_0404_4P2R_5%
RP44 56_0404_4P2R_5%
2 SO-DIMM B

2
RP45 56_0404_4P2R_5%
DDR_CKE2_DIMMB 1 4
DDR_B_BS#2 2 3

DDR_B_MA8
Security Classification Compal Secret Data Compal Electronics, Inc.
1 4 Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
DDR_B_MA12 2 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
RP46 56_0404_4P2R_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 14 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS_CK505
FSLC FSLB FSLA CPU SRC PCI L36
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz +3VS 1 2
1 1 1 1 1 1 1
KC FBM-L11-201209-221LMAT_0805 C248 C249 C250 C251 C252 C253 C254
0 1 0 200 100 33.3
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS
2 2 2 2 2 2 2
0 1 1 166 100 33.3
R116 R117
+1.25VS_CK505
FSB Frequency Selet: L37
2.2K_0402_5% 2.2K_0402_5%
+1.25VS 1 2
D D
CPU Driven Stuff R919 R940 R956 1 1 1 1 1
KC FBM-L11-201209-221LMAT_0805
C255 C256 C257 C259 C260 1 3 CLK_SMBDATA

S
(20,25,26) ICH_SMBDATA
R914 R921 R930 R943 R949 R954 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
*(Default) No Stuff 2 2 2 2 2 Q2
2N7002_SOT23

G
R959 R930 R914

2
Stuff +3VS

2
G
667MHz
No Stuff R919 R940 R956
(20,25,26) ICH_SMBCLK 1 3 CLK_SMBCLK
R949 R943 R921

S
Q3
Stuff 2N7002_SOT23
R959 R930 R921
+3VS_CK505 U5
800MHz
No Stuff R919 R940 R956 2 VDD_PCI NC 48
9 VDD48
R949 R943 R914 16 VDDPLL3
61 VDDREF
64 CLK_SMBCLK
+VCCP SCLK CLK_SMBDATA CLK_SMBCLK (13,14)
39 VDDSRC SDATA 63
55 CLK_SMBDATA (13,14)
VDDCPU
2

PCI_STOP# 38
@ R119 37 H_STP_PCI# (20)
56_0402_5% CPU_STOP# H_STP_CPU# (20)
+1.25VS_CK505 12 VDD96_IO
R120 20
2.2K_0402_5% VDDPLL3_IO
26 VDDSRC_IO
FSA 2 CLK_CPU_BCLK
1

1 1 2 MCH_CLKSEL0 (7) CPU0 54 CLK_CPU_BCLK (4)

36 53 CLK_CPU_BCLK#
VDDSRC_IO CPU0# CLK_CPU_BCLK# (4)
1 2 R121 49
C (5) CPU_BSEL0 VDDCPU_IO C
R124 1K_0402_5%
0_0402_5%
1

51 CLK_MCH_BCLK
CPU1_F CLK_MCH_BCLK (7)
R126 50 CLK_MCH_BCLK#
CPU1#_F CLK_MCH_BCLK# (7)
@ 1K_0402_5%
47 CLK_PCIE_MCARD1
SRC8/ITP CLK_PCIE_MCARD1 (26)
CLK_PCIE_MCARD1#
2

SRC8#/ITP# 46 CLK_PCIE_MCARD1# (26)

475_0402_1%1 2 R130 1
+VCCP (20) CLKSATAREQ# PCI0/CR#_A
EMI 2 1 PCI_CLK1 3 35 CLK_PCIE_NC1#
(7) CLKREQ_3GPLL# PCI1/CR#_B SRC10# CLK_PCIE_NC1# (25)
L46 FBM-L11-160808-601LMT_0603 34 CLK_PCIE_NC1
SRC10 CLK_PCIE_NC1 (25)
2

33_0402_5% 1 832@ 2 R134 PCI2_TME 4

(28) CLK_PCI_1394 PCI2/TME
R135 1 2 +3VS
33_0402_5% 1 2 R137 PCI_CLK3 5 R139 R136 10K_0402_5%
(33) CLK_PCI_LPC PCI3
1K_0402_5% 22_0402_5% 1 2 R138 33 CLKREQ#_H 2 1 475_0402_1%
(35) CLK_PCI_SIO SRC11/CR#_H CLKREQ_NC1# (25)
SERP@ CLKREQ_MCARD#R 2 475_0402_1%
FSB 33_0402_5% 1 2 R142
EMI 27_SEL
6 PCI4/27_Select SRC11#/CR#_G 32
R140
1 CLKREQ_MCARD# (26)
1

1 2 MCH_CLKSEL1 (7) (27) CLK_PCI_CB

PCMCIA@ 7 1 2 +3VS
R141 PCIF5/ITP_EN R143 10K_0402_5%
(5) CPU_BSEL1 1 2
R144 1K_0402_5% 33_0402_5% 1 2 R145 ITP_EN 30 CLK_PCIE_MCARD
(18) CLK_PCI_ICH SRC9 CLK_PCIE_MCARD (26)
0_0402_5% 31 CLK_PCIE_MCARD#
SRC9# CLK_PCIE_MCARD# (26)
1

@ CLK_XTAL_IN 60
R148 X1
@ 0_0402_5% CLK_XTAL_OUT 59 X2
SRC7/CR#_F 44
43 CLKREQ_LAN#R 2 1 475_0402_1%
SRC7#/CR#_E CLKREQ_LAN# (23)
R150
2

1 2
R151 10K_0402_5%

B +VCCP 41 CLK_PCIE_LAN B
SRC6 CLK_PCIE_LAN (23)
33_0402_5% 1 2 R153 FSA 10 40 CLK_PCIE_LAN#
(20) CLK_48M_ICH USB_48MHZ/FSLA SRC6# CLK_PCIE_LAN# (23)
2

R155 FSB 57 FSLB/TEST MODE CLK_MCH_3GPLL

SRC4 27 CLK_MCH_3GPLL (7)
R159 @ 1K_0402_5% 28 CLK_MCH_3GPLL#
SRC4# CLK_MCH_3GPLL# (7)
2.2K_0402_5% 22_0402_5% 1 2 R158 FSC 62
FSC (20) CLK_14M_ICH REF0/FSLC/TEST_SEL
1

2 1 1 2 MCH_CLKSEL2 (7)
22_0402_5% 1 2 R677
1 2 R160 (35) CLK_14M_SIO 24 CLK_PCIE_ICH
(5) CPU_BSEL2 SRC3/CR#_C CLK_PCIE_ICH (20)
R162 1K_0402_5% +1.25VS_CK505 45 25 CLK_PCIE_ICH#
VDDSRC_IO SRC3#/CR#_D CLK_PCIE_ICH# (20)
0_0402_5%
1

@
R165 For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
0_0402_5% 21 CLK_PCIE_SATA
SRC2/SATA CLK_PCIE_SATA (19)
For 27_SEL, 0 = Enable DOT96 & SRC1, 42 22 CLK_PCIE_SATA#
GNDSRC SRC2#/SATA# CLK_PCIE_SATA# (19)
2

1= Enable SRC0 & 27MHz 8 GNDPCI

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed 11 17 R_SSCDREFCLK R1681 2UMA@ 0_0402_5%
GND48 SRC1/SE1/27MHz_NonSS MCH_SSCDREFCLK (7)
18 R_SSCDREFCLK# R1691 2UMA@ 0_0402_5%
SRC1#/SE2/27MHz_SS MCH_SSCDREFCLK# (7)
1 = Overclocking of CPU and SRC NOT allowed 15 GND
RP47 UMA@
19 GND
Change cap from 13 R_MCH_DREFCLK 2 3 0_0404_4P2R_5%
+3VS_CK505 +3VS_CK505 +3VS_CK505 SRC0/DOT96 CLK_MCH_DREFCLK (7)
52 14 R_MCH_DREFCLK# 1 4
27p to 18p GNDCPU SRC0/DOT96# RP48 CLK_MCH_DREFCLK# (7)
23 GNDSRC 2 3 0_0404_4P2R_5% CLK_PCIE_VGA (17)
2

1 4 CLK_PCIE_VGA# (17)
1 2 CLK_XTAL_IN R174 R175 R176 29 VGA@
C268 18P_0402_50V8J VGA@ GNDSRC
10K_0402_5% 10K_0402_5% 10K_0402_5% CK_PWRGD/PD# 56
1

A @ 58 2 1 CK_PWRGD (20) A
GNDREF +3VS_CK505
Y1 R177 @ 10K_0402_5%
SLG8SP510_TSSOP64
1

14.31818MHZ_16PF_DSX840GA
ITP_EN 27_SEL PCI2_TME
Place close to U41
* Internal Pull-Up Resistor
ICS9LPRS365/SA00001GT00
CLK_XTAL_OUT
2

1 2
C269 18P_0402_50V8J ** Internal Pull-Down Resistor
2

R178 R179 R180

10K_0402_5% 10K_0402_5%
UMA@
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
@ Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

Clock generator
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Routing the trace at least 10mil Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 15 of 48
5 4 3 2 1
 A B C D E

Near to JP13
CRT CONNECTOR +5VS
D4
+R_CRT_VCC
F1
+CRT_VCC

1
D5 D6 D7 2 1 1 2

+3VS
CH491D_SC59 1.1A_6VDC_FUSE
1
C270
CRT Conn.
DAN217_SC59 DAN217_SC59 DAN217_SC59 0.1U_0402_16V4Z
2

3
@ @ @
JP5
6
L2 11
1 CRT_R_R 1 2 CRT_R_L 1 1
(17) CRT_R_R
FCM2012C-800_0805 7
(9) CRT_R 1 2 12
R182 UMA@ 0_0402_5% CRT_G_L 2
8
L3 13
CRT_G_R 1 2 CRT_B_L 3
(17) CRT_G_R
FCM2012C-800_0805 9
(9) CRT_G 1 2 14 16
R184 UMA@ 0_0402_5% 4 17
L4 1 10
CRT_B_R 1 2 C271 15
(17) CRT_B_R
FCM2012C-800_0805 5

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K

6P_0402_50V8K
6P_0402_50V8K

6P_0402_50V8K
1 2 220P_0402_50V7K
(9) CRT_B 2

150_0402_1%
150_0402_1%

150_0402_1%
R186 UMA@ 0_0402_5% 1 1 1 SUYIN_070549FR015S208CR

1
C272 C273 C274 1 1 1
R187 R188 R189 C275 C276 C277 DSUB_12_DATA
2 2 2 @ @ @ DSUB_15_CLK
2 2 2

68P_0402_50V8K

68P_0402_50V8K
2

2
1 1
C278 C279
+CRT_VCC
2 2
1 2 2 1
C280 0.1U_0402_16V4Z R190 10K_0402_5%

5
1
FCM1608C-121T_0603

P
OE#
CRT_HSYNC_R 2 4 D_CRT_HSYNC 1 2 HSYNC
(17) CRT_HSYNC_R A Y L5

G
1 2 U6
2 (9) CRT_HSYNC 2
R192 UMA@ 0_0402_5% SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC 1 2 VSYNC
L6

10P_0402_50V8J
+CRT_VCC

10P_0402_50V8J
FCM1608C-121T_0603
1 1
0.1U_0402_16V4Z 1 2 C282 C283
C281

5
1
2 2

P
OE#
CRT_VSYNC_R 2 4
(17) CRT_VSYNC_R A Y UMA@

G
1 2 U7 1 2 +CRT_VCC
(9) CRT_VSYNC (9) 3VDDCDA +3VS
R194 UMA@ 0_0402_5% SN74AHCT1G125GW_SOT353-5 0_0402_5% R195

3
VGA@

1
+3VS 1 2

R609 4.7K_0402_5% R197

2
G
4.7K_0402_5%

DDCDATA DSUB_12_DATA

2
(17) DDCDATA 3 1
D8 D9 D40 R196

D
@ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59 4.7K_0402_5%

2
G
Q4

1
2N7002_SOT23
DDCCLK 3 1 DSUB_15_CLK
(17) DDCCLK

D
VGA@ Q5
+3VS 1 2 2N7002_SOT23
2

3
R610 4.7K_0402_5%

3 3

+3VS UMA@
(9) 3VDDCCL 1 2
0_0402_5% R200

TV_COMPS_R L35 1 2
(17) TV_COMPS_R
FBM-11-160808-121T_0603
(9) TV_COMPS 1 2 TVOUT@
R600 UMA@ 0_0402_5%

(17) TV_LUMA_R
1 2 TV_LUMA_R L7 1 2
(9) TV_LUMA
R202 UMA@ 0_0402_5% FBM-11-160808-121T_0603
TVOUT@
TV_CRMA_R L8 1 2
(17) TV_CRMA_R
100P_0402_50V8J

FBM-11-160808-121T_0603 JP6
150_0402_1%

100P_0402_50V8J

(9) TV_CRMA 1 2 TVOUT@ 3

1

150_0402_1%

R204 UMA@ 0_0402_5% 1 TV_CRMA_L 6

1

C6461 1 TV_COMPS_L 7
100P_0402_50V8J

R206 R205 R601 1 1 1 5

150_0402_1% C287 2
TVOUT@ 2 C288 C289 C647 TV_LUMA_L 4
C286 2 2
2

1
TVOUT@ 2 2 2
2

8
TVOUT@ TVOUT@ TVOUT@ TVOUT@ 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 9

4 TVOUT@ TVOUT@ TVOUT@ SUYIN_030107FR007SX08FU 4

ME@
TV-OUT Conn. (ECQ60)
1. Y ground
2. C ground
3. Y (luminance+sync)
4. C (crominance) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 16 of 48
A B C D E
 5 4 3 2 1

PEG_M_TXP[0..15]
PEG_M_TXP[0..15] (9)
PEG_M_TXN[0..15]
PEG_M_TXN[0..15] (9)

PEG_RXP[0..15]
PEG_RXP[0:15] (9)
PEG_RXN[0..15]
PEG_RXN[0:15] (9)

MXM VGA BOARD Conn.

D D

KC FBMA-L11-321611-800LMA40T_1206 JP34A JP34B

L38
B+ 1 2 B+_MXM 1 PWR_SRC 2 PEG_RXN1 109 110
1V8RUN +1.8VS PEX_RX1# GND
3 PWR_SRC 4 PEG_RXP1 111 112 PEG_M_TXN1
VGA@ 1V8RUN PEX_RX1 PEX_TX1# PEG_M_TXP1
5 PWR_SRC 1V8RUN 6 113 GND PEX_TX1 114
7 PWR_SRC 8 PEG_RXN0 115 116
1V8RUN PEG_RXP0 PEX_RX0# GND PEG_M_TXN0
9 PWR_SRC 1V8RUN 10 117 PEX_RX0 PEX_TX0# 118
11 PWR_SRC 12 R612 119 120 PEG_M_TXP0
1V8RUN VGA@ 0_0402_5% CLK_PCIE_VGA# GND PEX_TX0
13 PWR_SRC 1V8RUN 14 (15) CLK_PCIE_VGA# 121 PEX_REFCLK# PRSNT1# 122
15 PWR_SRC 16 VGA_RUNPWROK 1 2 CLK_PCIE_VGA 123 124 TV_CRMA_R
RUNPWROK SUSP# (25,28,29,33,35,38,44,45) (15) CLK_PCIE_VGA PEX_REFCLK TV_C/HDTV_Pr TV_CRMA_R
17 GND 5VRUN 18 +5VS 125 CLK_REQ# GND 126
19 GND 20 R237 1 2 0_0402_5% PLTRST_VGA# 127 128 TV_LUMA_R
GND (7,18,20,23,25,26) PLT_RST# PEX_RST# TV_Y/HDTV_Y TV_LUMA_R
21 GND 22 VGA@ 129 130
GND RSVD GND TV_COMPS_R
23 GND GND 24 131 RSVD TV_CVBS/HDTV_Pb 132 TV_COMPS_R
(4,33) EC_SMB_DA2 0_0402_5% VGA@ 2 1 R212 133 134
0_0402_5% VGA@ 2 SMB_DAT GND
(4,33) EC_SMB_CK2 1 R210 135 SMB_CLK VGA_RED 136 CRT_R_R CRT_R_R (16)
137 THERM# GND 138
(16) CRT_HSYNC_R CRT_HSYNC_R 139 140 CRT_G_R CRT_G_R (16)
CRT_VSYNC_R VGA_HSYNC VGA_GRN
(16) CRT_VSYNC_R 141 VGA_VSYNC GND 142
C DDCCLK CRT_B_R C
DDCCLK 143 DDCA_CLK VGA_BLU 144 CRT_B_R (16)
PEG_RXN15 25 26 DDCDATA DDCDATA 145 146
PEG_RXP15 PEX_RX15# PRSNT2# PEG_M_TXN15 DDCA_DAT GND
27 PEX_RX15 PEX_TX15# 28 147 IGP_UCLK# LVDS_UCLK# 148
29 30 PEG_M_TXP15 149 150
PEG_RXN14 GND PEX_TX15 IGP_UCLK LVDS_UCLK
31 PEX_RX14# GND 32 151 GND GND 152
PEG_RXP14 33 34 PEG_M_TXN14 153 154
PEX_RX14 PEX_TX14# PEG_M_TXP14 RSVD LVDS_UTX3#
35 GND PEX_TX14 36 155 RSVD LVDS_UTX3 156
PEG_RXN13 37 38 157 158
PEG_RXP13 PEX_RX13# GND PEG_M_TXN13 RSVD GND
39 PEX_RX13 PEX_TX13# 40 159 IGP_UTX2# LVDS_UTX2# 160
41 42 PEG_M_TXP13 161 162
PEG_RXN12 GND PEX_TX13 IGP_UTX2 LVDS_UTX2
43 PEX_RX12# GND 44 163 GND GND 164
PEG_RXP12 45 46 PEG_M_TXN12 165 166
PEX_RX12 PEX_TX12# PEG_M_TXP12 IGP_UTX1# LVDS_UTX1#
47 GND PEX_TX12 48 167 IGP_UTX1 LVDS_UTX1 168
PEG_RXN11 49 50 169 170
PEG_RXP11 PEX_RX11# GND PEG_M_TXN11 GND GND
51 PEX_RX11 PEX_TX11# 52 171 IGP_UTX0# LVDS_UTX0# 172
53 54 PEG_M_TXP11 173 174
PEG_RXN10 GND PEX_TX11 IGP_UTX0 LVDS_UTX0
55 PEX_RX10# GND 56 175 GND GND 176
PEG_RXP10 57 58 PEG_M_TXN10 177 178 VGA_TXCLK- VGA_TXCLK- (22)
PEX_RX10 PEX_TX10# PEG_M_TXP10 IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# VGA_TXCLK+
59 GND PEX_TX10 60 179 IGP_LCLK/DVI_B_CLK LVDS_LCLK 180 VGA_TXCLK+ (22)
PEG_RXN9 61 62 181 182
PEG_RXP9 PEX_RX9# GND PEG_M_TXN9 DVI_B_HPD/GND GND
63 PEX_RX9 PEX_TX9# 64 183 RSVD LVDS_LTX3# 184
65 66 PEG_M_TXP9 185 186
PEG_RXN8 GND PEX_TX9 RSVD LVDS_LTX3
67 PEX_RX8# GND 68 187 GND GND 188
PEG_RXP8 69 70 PEG_M_TXN8 189 190 VGA_TXOUT2- VGA_TXOUT2- (22)
PEX_RX8 PEX_TX8# PEG_M_TXP8 IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# VGA_TXOUT2+
71 GND PEX_TX8 72 191 IGP_LTX2/DVI_B_TX2 LVDS_LTX2 192 VGA_TXOUT2+ (22)
PEG_RXN7 73 74 193 194
PEG_RXP7 PEX_RX7# GND PEG_M_TXN7 GND GND VGA_TXOUT1-
75 PEX_RX7 PEX_TX7# 76 195 IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# 196 VGA_TXOUT1- (22)
77 78 PEG_M_TXP7 197 198 VGA_TXOUT1+ VGA_TXOUT1+ (22)
PEG_RXN6 GND PEX_TX7 IGP_LTX1/DVI_B_TX1 LVDS_LTX1
79 PEX_RX6# GND 80 199 GND GND 200
PEG_RXP6 81 82 PEG_M_TXN6 201 202 VGA_TXOUT0- VGA_TXOUT0- (22)
PEX_RX6 PEX_TX6# PEG_M_TXP6 IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# VGA_TXOUT0+
83 GND PEX_TX6 84 203 IGP_LTX0/DVI_B_TX0 LVDS_LTX0 204 VGA_TXOUT0+ (22)
PEG_RXN5 85 86 205 206
B PEG_RXP5 PEX_RX5# GND PEG_M_TXN5 DVI_A_HPD GND LCD_DATA B
87 PEX_RX5 PEX_TX5# 88 207 DVI_A_CLK# DDCC_DAT 208 LCD_DATA (22)
89 90 PEG_M_TXP5 209 210 LCD_CLK LCD_CLK (22)
PEG_RXN4 GND PEX_TX5 DVI_A_CLK DDCC_CLK VGA_ENVDD
91 PEX_RX4# GND 92 211 GND LVDS_PPEN 212 VGA_ENVDD (22)
PEG_RXP4 93 94 PEG_M_TXN4 213 214
PEX_RX4 PEX_TX4# PEG_M_TXP4 DVI_A_TX2# LVDS_BL_BRGHT VGA_ENBKL
95 GND PEX_TX4 96 215 DVI_A_TX2 LVDS_BLEN 216 VGA_ENBKL (22)
PEG_RXN3 97 98 217 218
PEG_RXP3 99
PEX_RX3#
PEX_RX3
GND
PEX_TX3# 100 PEG_M_TXN3 219
GND
DVI_A_TX1#
DDCB_DAT
DDCB_CLK 220 2006/10/14
101 102 PEG_M_TXP3 221 222 +2.5VS
PEG_RXN2 GND PEX_TX3 DVI_A_TX1 2V5RUN
103 PEX_RX2# GND 104 223 GND GND 224
PEG_RXP2 105 106 PEG_M_TXN2 225 226 +3VS
PEX_RX2 PEX_TX2# PEG_M_TXP2 DVI_A_TX0# 3V3RUN
107 GND PEX_TX2 108 227 DVI_A_TX0 3V3RUN 228
229 GND 3V3RUN 230

ACES_88990-2D28_230P
ME@ footprint update OK ACES_88990-2D28_230P
ME@
footprint update OK
2006/09/13
B+ +1.8VS +3VS +2.5VS +5VS

2 1 1 1 1 1 1
C652 C653 C654 C655 C656 C657 C658
VGA@
VGA@
4.7U_0805_10V4Z VGA@
4.7U_0805_10V4Z 0.1U_0402_16V4Z
1
0.1U_0603_25V7K 2 2 VGA@ 2 2 VGA@ 2 VGA@ 2 VGA@
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MXM CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 17 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS

1 2 PCI_DEVSEL# (27,28) PCI_AD[0..31]

R256 8.2K_0402_5% U8B
1 2 PCI_STOP# PCI_AD0 D20 A4 PCI_REQ0#
AD0 REQ0# PCI_REQ0# (28)
R257 8.2K_0402_5% PCI_AD1 E19 D7 PCI_GNT0#
D 1 2 PCI_TRDY# PCI_AD2 D19
AD1 PCI GNT0#
E18 PCI_REQ1#
PCI_GNT0# (28) D
R258 8.2K_0402_5% PCI_AD3 AD2 REQ1#/GPIO50 PCI_GNT1#
A20 AD3 GNT1#/GPIO51 C18
1 2 PCI_FRAME# PCI_AD4 D17 B19 PCI_REQ2#
AD4 REQ2#/GPIO52 PCI_REQ2# (27)
R259 8.2K_0402_5% PCI_AD5 A21 F18 PCI_GNT2#
AD5 GNT2#/GPIO53 PCI_GNT2# (27)
PCI_AD6 A19 A11 PCI_REQ3#
PCI_PLOCK# PCI_AD7 AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C19 AD7 GNT3#/GPIO55 C10
R260 8.2K_0402_5% PCI_AD8 A18
PCI_IRDY# PCI_AD9 AD8 PCI_CBE#0
1 2 B16 AD9 C/BE0# C17 PCI_CBE#0 (27,28)
R261 8.2K_0402_5% PCI_AD10 A12 E15 PCI_CBE#1
AD10 C/BE1# PCI_CBE#1 (27,28)
1 2 PCI_SERR# PCI_AD11 E16 F16 PCI_CBE#2
AD11 C/BE2# PCI_CBE#2 (27,28)
R262 8.2K_0402_5% PCI_AD12 A14 E17 PCI_CBE#3
AD12 C/BE3# PCI_CBE#3 (27,28)
1 2 PCI_PERR# PCI_AD13 G16
R263 8.2K_0402_5% PCI_AD14 AD13 PCI_IRDY#
A15 AD14 IRDY# C8 PCI_IRDY# (27,28)
PCI_AD15 B6 D9 PCI_PAR
AD15 PAR PCI_PAR (27,28)
PCI_AD16 C11 G6 PCI_PCIRST#
PCI_AD17 AD16 PCIRST# PCI_DEVSEL#
A9 AD17 DEVSEL# D16 PCI_DEVSEL# (27,28)
PCI_AD18 D11 A7 PCI_PERR#
AD18 PERR# PCI_PERR# (27,28)
PCI_AD19 B12 B7 PCI_PLOCK#
PCI_AD20 AD19 PLOCK# PCI_SERR#
C12 AD20 SERR# F10 PCI_SERR# (27,28)
+3VS PCI_AD21 D10 C16 PCI_STOP#
AD21 STOP# PCI_STOP# (27,28)
PCI_AD22 C7 C9 PCI_TRDY#
AD22 TRDY# PCI_TRDY# (27,28)
PCI_AD23 F13 A17 PCI_FRAME#
AD23 FRAME# PCI_FRAME# (27,28)
1 2 PCI_PIRQA# PCI_AD24 E11
R264 8.2K_0402_5% PCI_AD25 AD24 PCI_PLTRST#
E13 AD25 PLTRST# AG24
1 2 PCI_PIRQB# PCI_AD26 E12 B10 CLK_PCI_ICH
AD26 PCICLK CLK_PCI_ICH (15)
R265 8.2K_0402_5% PCI_AD27 D8 G7 PCI_PME#
AD27 PME# PCI_PME# (33)
1 2 PCI_PIRQC# PCI_AD28 A6
R266 8.2K_0402_5% PCI_AD29 AD28
E8 AD29 1 2 +3VALW
1 2 PCI_PIRQD# PCI_AD30 D6 R267 8.2K_0402_5%
R268 8.2K_0402_5% PCI_AD31 AD30
A3 AD31
1 2 PCI_PIRQE#
R269 8.2K_0402_5%
C
1 2 PCI_PIRQF# PCI_PIRQA# F9
Interrupt I/F F8 PCI_PIRQE# C
PIRQA# PIRQE#/GPIO2 PCI_PIRQE# (27)
R270 8.2K_0402_5% PCI_PIRQB# B5 G11 PCI_PIRQF#
PCI_PIRQG# PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
1 2 (27) PCI_PIRQC# C5 PIRQC# PIRQG#/GPIO4 F12 PCI_PIRQG# (28)
R271 8.2K_0402_5% PCI_PIRQD# A10 B3 PCI_PIRQH#
PIRQD# PIRQH#/GPIO5 PCI_PIRQH# (28)
1 2 PCI_PIRQH#
R272 8.2K_0402_5% ICH8M REV 1.0
SA00001JU30

1 2 PCI_REQ0#
R273 8.2K_0402_5%
1 2 PCI_REQ1#
R274 8.2K_0402_5%
1 2 PCI_REQ2#
R275 8.2K_0402_5%
1 2 PCI_REQ3#
R276 8.2K_0402_5%

PCI_GNT3#
1

R277
@
1K_0402_5%
Boot BIOS Strap
2

B B
+3VALW

PCI_GNT0# SPI_CS#1 Boot BIOS Location

5
U9
PCI_PCIRST# 1

P
B PCI_RST#
0 1 SPI 2
Y 4 PCI_RST# (27,28,33,35)
A

1
A16 swap override Strap @ TC7SH08FU_SSOP5 R278
R279

3
Low= A16 swap override Enble 1 0 PCI 0_0402_5%
100K_0402_5%

2 1
PCI_GNT3# High= Default *

2
1 1 LPC * +3VALW

5
U10
PCI_GNT0# SB_SPI_CS#1 PCI_PLTRST# 1

P
(20) SB_SPI_CS#1 B
Y 4 PLT_RST# PLT_RST# (7,17,20,23,25,26)
Place closely pin B10 2 A
1

1
R281 @ TC7SH08FU_SSOP5 R282
CLK_PCI_ICH R280 @ 1K_0402_5%

3
100K_0402_5%
@ 1K_0402_5% R284
2

0_0402_5%
R283
2

2
2 1

@ 10_0402_5%
1

A A
1
C296

@ 8.2P_0402_50V
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(1/4)-PCI/INT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 18 of 48
5 4 3 2 1
 5 4 3 2 1

ICH8M Internal VR Enable Strap

+3VS
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

LAN100_SLP Low = Internal VR Disabled R285

GATEA20 2 1
High = Internal VR Enabled(Default)
ICH_INTVRMEN 10K_0402_5%

R286
KB_RST# 2 1

C297 15P_0402_50V8J ICH_RTCX1 10K_0402_5%

D +RTCVCC D

1
R287 330K_0402_1% Y2
1 2 LAN100_SLP 2 NC IN 1 R288 +VCCP
32.768KHZ_12.5P_1TJS125BJ2A251 10M_0402_5% R289
R290 1M_0402_5% 3 4 H_FERR# 2 1
NC OUT
1 2 SM_INTRUDER# LPC_AD[0..3] (33,35)
U8A 56_0402_5%

2
R291 330K_0402_1% AG25 E5 LPC_AD0 R292 @
RTCX1 FWH0/LAD0
1 2 ICH_INTVRMEN C298 15P_0402_50V8J ICH_RTCX2 AF24 RTCX2 FWH1/LAD1 F5 LPC_AD1 H_DPRSTP# 2 1
G8 LPC_AD2
ICH_RTCRST# FWH2/LAD2 LPC_AD3 56_0402_5%
+RTCVCC 1 2 AF23 RTCRST# FWH3/LAD3 F6
R293 20K_0402_5% R294 @
SM_INTRUDER# AD22 C4 LPC_FRAME# H_DPSLP# 2 1
INTRUDER# FWH4/LFRAME# LPC_FRAME# (33,35)
2

RTC
LPC
C299 ICH_INTVRMEN AF25 G9 LPC_DRQ0# 56_0402_5%
INTVRMEN LDRQ0# LPC_DRQ#0 (35)
CLRP1 LAN100_SLP AD21 E6
1U_0603_10V4Z LAN100_SLP LDRQ1#/GPIO23
1 JOPEN GATEA20

1
@ B24 GLAN_CLK A20GATE AF13 GATEA20 (33)
AG26 H_A20M#
A20M# H_A20M# (4)
D22 LAN_RSTSYNC
AF26 H_DPRSTP_R# 2 1 H_DPRSTP#
DPRSTP# H_DPRSTP# (5,7,46)
C21 AE26 R295 0_0402_5%
LAN_RXD0 DPSLP#
B21 LAN_RXD1 H_DPSLP# (5)
C22 AD24 H_FERR#
LAN_RXD2 FERR# H_FERR# (4)

LAN / GLAN
D21 AG29 H_PWRGOOD
LAN_TXD0 CPUPWRGD/GPIO49 H_PWRGOOD (5)
E20 LAN_TXD1
C20 AF27 H_IGNNE#
LAN_TXD2 IGNNE# H_IGNNE# (4)
within 2" from R1557
AH21 AE24 H_INIT#
GLAN_DOCK#/GPIO13 INIT# H_INIT# (4) +VCCP
AC20 H_INTR
INTR H_INTR (4)

CPU
C R296 1 C
+1.5VS 2 24.9_0402_1% GLAN_COMP D25 GLAN_COMPI RCIN# AH14 KB_RST#
KB_RST# (33)
C25 GLAN_COMPO

1
EMI AD23 H_NMI
NMI H_NMI (4)
R298 1 2 47_0402_5% HDA_BITCLK_R AJ16 AG28 H_SMI# R299
TO MDC (26) HDA_BITCLK_MDC
(26) HDA_SYNC_MDC
R300 1 2 33_0402_5% HDA_SYNC_R AJ15
HDA_BIT_CLK
HDA_SYNC
SMI#

STPCLK# AA24 H_STPCLK#

H_SMI# (4)

H_STPCLK# (4)
56_0402_5%
R301 1 2 33_0402_5% HDA_RST_R# AE14
(26) HDA_RST_MDC# HDA_RST# THRMTRIP_ICH# R302 24_0402_1%

2
THRMTRIP# AE27 1 2 H_THERMTRIP# (4,7)
ICH_AC_SDIN0 AJ17
(29) HDA_SDIN0 HDA_SDIN0
ICH_AC_SDIN1 AH17 AA23
(26) HDA_SDIN1 HDA_SDIN1 TP8 PD_D[0..15] (25)
AH15 HDA_SDIN2

IHDA
AD13 V1 PD_D0 placed within 2" from ICH8M
HDA_SDIN3 DD0 PD_D1
DD1 U2
R303 1 2 33_0402_5% HDA_SDOUT_R AE13 V3 PD_D2
(26) HDA_SDOUT_MDC HDA_SDOUT DD2
T1 PD_D3
KILL_MDC# DD3 PD_D4
(26) KILL_MDC# AE10 HDA_DOCK_EN#/GPIO33 DD4 V4
+3VS IDERST_CD# AG14 T5 PD_D5
(25) IDERST_CD# HDA_DOCK_RST#/GPIO34 DD5
AB2 PD_D6
10K_0402_5% 2 DD6
1 R304 SATA_LED# (37) SATA_LED#
SATA_LED# AF10 SATALED# DD7 T6 PD_D7
T3 PD_D8
PSATA_IRX_DTX_N0_C DD8 PD_D9
(25) PSATA_IRX_DTX_N0_C AF6 SATA0RXN DD9 R2
PSATA_IRX_DTX_P0_C AF5 T4 PD_D10
(25) PSATA_IRX_DTX_P0_C SATA0RXP DD10
PSATA_ITX_DRX_N0_C AH5 V6 PD_D11
PSATA_ITX_DRX_P0_C SATA0TXN DD11 PD_D12
AH6 SATA0TXP DD12 V5
U1 PD_D13
DD13 PD_D14 +3VS
AG3 SATA1RXN DD14 V2
PSATA_ITX_DRX_N0 1 2 PSATA_ITX_DRX_N0_C AG4 U6 PD_D15
(25) PSATA_ITX_DRX_N0 SATA1RXP DD15

IDE
C301 3900P_0402_50V7K AJ4 SATA1TXN PD_A0
AJ3 SATA1TXP DA0 AA4 PD_A0 (25)
PSATA_ITX_DRX_P0 1 2 PSATA_ITX_DRX_P0_C AA1 PD_A1 PD_IORDY R305 1 2 4.7K_0402_5%
(25) PSATA_ITX_DRX_P0 DA1 PD_A1 (25)

SATA
C302 3900P_0402_50V7K AF2 AB3 PD_A2 PD_IRQ R306 1 2 8.2K_0402_5%
SATA2RXN DA2 PD_A2 (25)
AF1 SATA2RXP
B AE4 Y6 PD_CS#1 B
SATA2TXN DCS1# PD_CS#1 (25)
AE3 Y5 PD_CS#3
SATA2TXP DCS3# PD_CS#3 (25)
CLK_PCIE_SATA# AB7 W4 PD_IOR#
(15) CLK_PCIE_SATA# SATA_CLKN DIOR# PD_IOR# (25)
CLK_PCIE_SATA AC6 W3 PD_IOW#
(15) CLK_PCIE_SATA SATA_CLKP DIOW# PD_IOW# (25)
Y2 PD_DACK#
DDACK# PD_DACK# (25)
R307 AG1 Y3 PD_IRQ
SATARBIAS# IDEIRQ PD_IRQ (25)
1 2 AG2 Y1 PD_IORDY
SATARBIAS IORDY PD_IORDY (25)
W5 PD_DREQ
DDREQ PD_DREQ (25)
24.9_0402_1%
Within 500 mils ICH8M REV 1.0

BATT1.1
XOR CHAIN ENTRANCE STRAP:RSVD Close to ICH
+3VS
TO CODEC +RTCVCC

R308 2 1 HDA_SDOUT_AUDIO
@ 1K_0402_5%
(29) HDA_SDOUT_AUDIO 1
R309
2 HDA_SDOUT_R
33_0402_5% R310
+ BATT1 -
1 2 1 2
W=20mils
(29) HDA_SYNC_AUDIO 1 2 HDA_SYNC_R 2 100_0603_1%
D12
R311 33_0402_5% C303
1 2 +CHGRTC ML1220T13RE
0.1U_0402_16V4Z 45@
A 1 A
(29) HDA_RST_AUDIO# 1 2 HDA_RST_R# RB751V_SOD323
R312 33_0402_5%

EMI 1 2 HDA_BITCLK_R
(29) HDA_BITCLK_AUDIO
R313 47_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(2/4)_LAN,HD,IDE,LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 19 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS 1 2 SIRQ Place closely pin G5 Place closely pin AG9

R314 10K_0402_5% +3VALW +3VS

1 2 PCI_CLKRUN# +3VALW CLK_48M_ICH CLK_14M_ICH

2
R315 8.2K_0402_5% 0316 change design
R316 R317 R318

1
1 2 VGA_THER_ALERT# 8.2K_0402_5%

2
R319 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% R320 R321
R322 R323 U8C
@ 1 2 EC_THERM# V 10K_0402_5% 10K_0402_5% ICH_SMBCLK @ 10_0402_5% @ 10_0402_5%

1
(15,25,26) ICH_SMBCLK AJ26 SMBCLK SATA0GP/GPIO21 AJ12
R324 8.2K_0402_5% (15,25,26) ICH_SMBDATA ICH_SMBDATA AD19 AJ10
LINKALERT# SMBDATA SATA1GP/GPIO19

2
AG21 AF11

SATA
GPIO
LINKALERT# SATA2GP/GPIO36

SMB
2 CLKSATAREQ# ME__EC_CLK1

1
1 AC17 SMLINK0 SATA3GP/GPIO37 AG11 1 1
R325 10K_0402_5% ME__EC_DATA1 AE19 C305 C306
SMLINK1 CLK_14M_ICH
CLK14 AG9 CLK_14M_ICH (15)
D 1 2 H_PROCHOT# 0320 add EC_SWI# AF17 G5 CLK_48M_ICH @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C D

Clocks
(33) EC_SWI# RI# CLK48 CLK_48M_ICH (15) 2 2
R326 10K_0402_5% +3VS T33
PAD F4 D3 ICH_SUSCLK T18 PAD
XDP_DBRESET# AD15 SUS_STAT#/LPCPD# SUSCLK
(4) XDP_DBRESET# SYS_RESET#

2
AG23 SLP_S3#
SLP_S3# SLP_S3# (33)
R328 @ R329 PM_BMBUSY# AG12 AF21 SLP_S4#
(7) PM_BMBUSY# BMBUSY#/GPIO0 SLP_S4# SLP_S4# (33)
1 2 GPIO6 10K_0402_5% 10K_0402_5% AD18 PM_SLP_S5# PM_SLP_S5# (33)
R623 100K_0402_5% SLP_S5#
(33) EC_LID_OUT# 1 2 AG22
R330 0_0402_5% SMBALERT#/GPIO11 AH27
S4_STATE#/GPIO26

GPIO
GPIO39 H_STP_PCI#

1
1 2 (15) H_STP_PCI# AE20 STP_PCI#/GPIO15

SYS
R331 10K_0402_5% 2 1 R_STP_CPU# AG18 STP_CPU#/GPIO25 AE23 ICH_POK
(15) H_STP_CPU#
R332 0_0402_5% PWROK ICH_POK (7,33)
1 2 R333 2006/10/14
1 2 GPIO48 2006/12/07 PCI_CLKRUN# AH11 AJ14 DPRSLPVR 10K_0402_5%
(27,28,33,35) PCI_CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR (7,46) AUDY DEL

Power MGT
R334 10K_0402_5%
ICH_PCIE_WAKE# AE17 AE21 ICH_LOW_BAT#
+3VALW
R335
1 2 LINKALERT#
10K_0402_5%
(23,25,26) ICH_PCIE_WAKE#
(27,28,33,35) SIRQ
SIRQ
EC_THERM#
AF12
WAKE#
SERIRQ
BATLOW#
PBTN_OUT#
PBTN_OUT# (33)
S4/S5
(4,33) EC_THERM# AC13 THRM# PWRBTN# C2
2 R680 1
1 2CL_RST# (7,46) VGATE 1 2 VRMPWRGD AJ20 VRMPWRGD LAN_RST# AH20 1 @ 2 8.2K_0402_5%
R336 10K_0402_5% R337 0_0402_5% R3380_0402_5%
PLT_RST# (7,17,18,23,25,26)
SST_CTL AJ22 AG27 EC_RSMRST#R R339
(4,46) H_PROCHOT# TP7 RSMRST#
1 2XDP_DBRESET# T19 PAD EC_RSMRST#R 1 2
R340 10K_0402_5% D43 H_PROCHOT# AJ8 E1 CK_PWRGD_R 1 2 CK_PWRGD 10K_0402_5%
TACH1/GPIO1 CK_PWRGD CK_PWRGD (15)
ACIN 1 2 GPIO6 AJ9 R341 0_0402_5%
(33,39) ACIN TACH2/GPIO6
1 2 EC_SWI# AH9 E3 CLPWROK 1 2 ICH_POK
R342 10K_0402_5% EC_SMI# TACH3/GPIO7 CLPWROK R624 0_0402_5%
(33) EC_SMI# AE16 GPIO8
CH751H-40_SC76 EC_SCI# AC19 AJ25
(33) EC_SCI# GPIO12 SLP_M#
1 2 ICH_PCIE_WAKE# AG8 TACH0/GPIO17
R343 1K_0402_5% AH12 F23 CL_CLK0
GPIO18 CL_CLK0 CL_CLK0 (7)
AE11 AE18 0.1U_0402_16V4Z 1 2 +3VS
GPIO20 CL_CLK1

GPIO
Controller Link
2 1ICH_LOW_BAT# AG10 SCLOCK/GPIO22
R344 @ 3.24K_0402_1%

1
R345 8.2K_0402_5% AH25 F22 CL_DATA0 1
C SB_INT_FLASH_SEL# QRT_STATE0/GPIO27 CL_DATA0 CL_DATA0 (7) C
PAD T20 AD16 AF19 C307 R346
+3VS QRT_STATE1/GPIO28 CL_DATA1
1 2 DPRSLPVR (15) CLKSATAREQ#
CLKSATAREQ# AG13 SATACLKREQ#/GPIO35
@ 453_0402_1%
R347 100K_0402_5% AF9 D24 CL_VREF0_ICH @
VGA_THER_ALERT# SLOAD/GPIO38 CL_VREF0 2
GPIO39 AJ11 AH23 CL_VREF1_ICH
SDATAOUT0/GPIO39 CL_VREF1
2

1 ICH_RSVD GPIO48

2
2 AD10 SDATAOUT1/GPIO48
R348 @ 1K_0402_5% AJ23 CL_RST#
CL_RST# CL_RST# (7)
R349 SB_SPKR AD9
(29) SB_SPKR SPKR
@ 330_0402_5% AJ27 EC_FLASH#
MEM_LED/GPIO24 EC_FLASH#

MISC
MCH_ICH_SYNC# AJ13 AJ24 0.1U_0402_16V4Z 1 2 +3VALW
(7) MCH_ICH_SYNC# MCH_SYNC# ME_EC_ALERT/GPIO10
2 VRMPWRGD R351 @ 3.24K_0402_1%
1

1 EC_ME_ALERT/GPIO14 AF22

1
R352 @ 0_0402_5% ICH_RSVD AJ21 AG19 1
TP3 WOL_EN/GPIO9
1

D C308 R353
2 Q9 ICH8M REV 1.0 453_0402_1%
(46) CLK_ENABLE#
G @ RHU002N06_SOT323 low-->default @ @
2
S 1 2 SB_SPKR
+3VS
R354 @ 10K_0402_5% High -->No boot 2006/09/20
3

2
U8D
(26) PCIE_RXN1
PCIE_RXN1 P27 PERN1 DMI0RXN V27 DMI_RXN0 DMI_RXN0 (7)
RSMRST circuit
MINI1@ PCIE_RXP1 P26 V26 DMI_RXP0 DMI_RXP0 (7) R355
(26) PCIE_RXP1 PERP1 DMI0RXP
MINI CARD2 (26) PCIE_TXN1 0.1U_0402_16V7K C309 PCIE_C_TXN1 N29 U29 DMI_TXN0 DMI_TXN0 (7)
0.1U_0402_16V7K C310 PCIE_C_TXP1 PETN1 DMI0TXN DMI_TXP0 0_0402_5%
(26) PCIE_TXP1 N28 U28 DMI_TXP0 (7)

Direct Media Interface

MINI1@ PETP1 DMI0TXP
1 2
PCIE_RXN2 M27 Y27 DMI_RXN1 DMI_RXN1 (7)
(26) PCIE_RXN2 PERN2 DMI1RXN
MINI2@ PCIE_RXP2 M26 Y26 DMI_RXP1 DMI_RXP1 (7) Q10
(26) PCIE_RXP2 PERP2 DMI1RXP
WLAN 0.1U_0402_16V7K C311 PCIE_C_TXN2 L29 W29 DMI_TXN1 3 1 EC_RSMRST#R

C
(26) PCIE_TXN2 PETN2 DMI1TXN DMI_TXN1 (7) (33) EC_RSMRST#
0.1U_0402_16V7K C312 PCIE_C_TXP2 L28 W28 DMI_TXP1

E
(26) PCIE_TXP2 PETP2 DMI1TXP DMI_TXP1 (7)
MINI2@ @ BAV99DW-7_SOT363 @ MMBT3906_SOT23
PCI-Express

PCIE_RXN3 K27 AB26 DMI_RXN2 1 2

B
(25) PCIE_RXN3 PERN3 DMI2RXN DMI_RXN2 (7) +3VALW
PCIE_RXP3 DMI_RXP2 R356 @ 4.7K_0402_5%

12
(25) PCIE_RXP3 K26 PERP3 DMI2RXP AB25 DMI_RXP2 (7)

2
NEW CARD (25) PCIE_TXN3 0.1U_0402_16V7K C313 PCIE_C_TXN3 J29 AA29 DMI_TXN2 DMI_TXN2 (7)
B 0.1U_0402_16V7K C314 PCIE_C_TXP3 PETN3 DMI2TXN DMI_TXP2 R357 D13B D13A @ B
(25) PCIE_TXP3 J28 PETP3 DMI2TXP AA28 DMI_TXP2 (7)
@ 2.2K_0402_5% BAV99DW-7_SOT363
PCIE_RXN4 H27 AD27 DMI_RXN3 DMI_RXN3 (7)
(23) PCIE_RXN4 PERN4 DMI3RXN
PCIE_RXP4 H26 AD26 DMI_RXP3 DMI_RXP3 (7)
(23) PCIE_RXP4 PERP4 DMI3RXP
LAN 0.1U_0402_16V7K C315 PCIE_C_TXN4 DMI_TXN3

1
(23) PCIE_TXN4 G29 PETN4 DMI3TXN AC29 DMI_TXN3 (7) R358
0.1U_0402_16V7K C316 PCIE_C_TXP4 DMI_TXP3

6
(23) PCIE_TXP4 G28 PETP4 DMI3TXP AC28 DMI_TXP3 (7) 1 2

F27 T26 CLK_PCIE_ICH# @ 2.2K_0402_5%

PERN5 DMI_CLKN CLK_PCIE_ICH# (15)
F26 T25 CLK_PCIE_ICH
PERP5 DMI_CLKP CLK_PCIE_ICH (15)
E29 PETN5
E28 Y23 R359 24.9_0402_1% Within 500 mils
PETP5 DMI_ZCOMP DMI_IRCOMP
Y24 1 2
D27
D26
PERN6/GLAN_RXN
DMI_IRCOMP
G3 USB20_N0
+1.5VS
USB PORT LIST
PERP6/GLAN_RXP USBP0N USB20_N0 (31)
C29 G2 USB20_P0
PETN6/GLAN_TXN USBP0P USB20_P0 (31)
USB20_N1
C28 PETP6/GLAN_TXP USBP1N H5
H4 USB20_P1
USB20_N1
USB20_P1
(26)
(26)
PORT DEVICE
USBP1P USB20_N2
C23 SPI_CLK USBP2N H2 USB20_N2 (31)
USB20_P2
(18) SB_SPI_CS#1
SB_SPI_CS#1
B23
E22
SPI_CS0# USBP2P H1
J3
USB20_P2 (31) 0 LEFT SIDE
SPI_CS1# USBP3N
SPI

RP13
+3VALW 8 1 USB_OC#6 D23
USBP3P J2
K5
1 WIRELESS
CPUSB# SPI_MOSI USBP4N
7
6
2
3 USB_OC#2
F21 SPI_MISO USBP4P K4
K2 USB20_N5
USB20_N5 (25)
2 RIGHT SIDE
USB_OC#4 USB_OC#0 USBP5N USB20_P5
5 4 (31)
(26)
USB_OC#0
MINI_ON# MINI_ON#
AJ19
AG16
OC0# USBP5P K1
L3 USB20_N6
USB20_P5
USB20_N6
(25)
(31)
3 CMOS
10K_1206_8P4R_5% USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6
(31) USB_OC#2
USB_OC#3
AG15
AE15
OC2#/GPIO41 USB USBP6P L2
M5 USB20_N7
USB20_P6
USB20_N7
(31)
(26)
4 RIGHT SIDE
RP14 USB_OC#4 OC3#/GPIO42 USBP7N USB20_P7
5 4 MINI_ON#
USB_OC#4
USB_OC#5
AF15
AG17
OC4#/GPIO43 USBP7P M4
M2 USB20_N8
USB20_P7
USB20_N8
(26)
(36)
5 NEW CARD
USB_OC#5 USB_OC#6 OC5#/GPIO29 USBP8N USB20_P8
6
7
3
2 USB_OC#9
(31)
(25)
USB_OC#6
CPUSB# CPUSB#
AD12
AJ18
OC6#/GPIO30 USBP8P M1
N3 USB20_N9
USB20_P8
USB20_N9
(36)
(26)
6 RIGHT SIDE
A USB_OC#0 USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9 A
8 1 USB_OC#8
USB_OC#9
AD14
AH18
OC8# USBP9P N2 USB20_P9 (26) 7 BT(HDL20)
10K_1206_8P4R_5% OC9# USBRBIAS
USBRBIAS# F2
F3
1 2
8 FINGER PRINTER
USBRBIAS
2 1 USB_OC#8 R360 22.6_0402_1%
9 TV TUNER
R361 10K_0402_5% ICH8M REV 1.0 Within 500 mils
2 1 USB_OC#3
R362 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(3/4)_PM,USB,GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 20 of 48
5 4 3 2 1
 5 4 3 2 1

+RTCVCC U8E
20 mils A23 VSS[001] VSS[099] K7
A5 VSS[002] VSS[100] L1
1 1 AA2 VSS[003] VSS[101] L13
C317 C318 AA7 L15
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VCCP VSS[004] VSS[102]
A25 VSS[005] VSS[103] L26
AB1 VSS[006] VSS[104] L27
2 2
AB24 VSS[007] VSS[105] L4
U8F 0.1U_0402_16V7K AC11 L5
VSS[008] VSS[106]
AD25 VCCRTC VCC1_05[01] A13 AC14 VSS[009] VSS[107] M12
VCC1_05[02] B13 AC25 VSS[010] VSS[108] M13
ICH_V5REF_RUN A16 C13 1 1 AC26 M14
V5REF[1] VCC1_05[03] C319 C320 0.1U_0402_16V4Z VSS[011] VSS[109]
T7 V5REF[2] VCC1_05[04] C14 AC27 VSS[012] VSS[110] M15
KC FBM-L11-201209-221LMAT_0805 D14 AD17 M16
L39 ICH_V5REF_SUS VCC1_05[05] VSS[013] VSS[111]
G4 V5REF_SUS VCC1_05[06] E14 AD20 VSS[014] VSS[112] M17
D 10U_0805_6.3V6M 2 2 D
+1.5VS 1 2 40 mils VCC1_05[07] F14 AD28 VSS[015] VSS[113] M23
1 AA25 VCC1_5_B[01] VCC1_05[08] G14 AD29 VSS[016] VSS[114] M28
1 2 1 1 1 AA26 VCC1_5_B[02] VCC1_05[09] L11 AD3 VSS[017] VSS[115] M29
L40 + C322 C323 C324 AA27 L12 AD4 M3
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[03] VCC1_05[10] VSS[018] VSS[116]
AB27 VCC1_5_B[04] VCC1_05[11] L14 AD6 VSS[019] VSS[117] N1
C321 AB28 L16 AE1 N11
220U_D2_4VM 2 2 2 2 VCC1_5_B[05] VCC1_05[12] VSS[020] VSS[118]
AB29 VCC1_5_B[06] VCC1_05[13] L17 AE12 VSS[021] VSS[119] N12
+5VS +3VS D28 L18 R364 AE2 N13
10U_0805_6.3V6M 2.2U_0603_6.3V4Z VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K VSS[022] VSS[120]
D29 VCC1_5_B[08] VCC1_05[15] M11 1 2 +1.5VS AE22 VSS[023] VSS[121] N14

CORE
E25 M18 CHB1608U301_0603 AD1 N15
VCC1_5_B[09] VCC1_05[16] VSS[024] VSS[122]
1

E26 VCC1_5_B[10] VCC1_05[17] P11 1 1 AE25 VSS[025] VSS[123] N16

R365 D14 E27 P18 C325 C326 10U_0805_6.3V6M AE5 N17
VCC1_5_B[11] VCC1_05[18] VSS[026] VSS[124]
F24 VCC1_5_B[12] VCC1_05[19] T11 AE6 VSS[027] VSS[125] N18
100_0402_5% CH751H-40_SC76 F25 T18 AE9 N26
VCC1_5_B[13] VCC1_05[20] 2 2 VSS[028] VSS[126]
20 mils G24 VCC1_5_B[14] VCC1_05[21] U11 AF14 VSS[029] VSS[127] N27
2

H23 VCC1_5_B[15] VCC1_05[22] U18 AF16 VSS[030] VSS[128] N4

ICH_V5REF_RUN H24 V11 AF18 N5
VCC1_5_B[16] VCC1_05[23] VSS[031] VSS[129]
1 J23 VCC1_5_B[17] VCC1_05[24] V12 AF3 VSS[032] VSS[130] N6
C327 J24 V14 +1.25VS AF4 P12
VCC1_5_B[18] VCC1_05[25] VSS[033] VSS[131]
K24 VCC1_5_B[19] VCC1_05[26] V16 AG5 VSS[034] VSS[132] P13
0.1U_0402_16V4Z K25 V17 1 AG6 P14
2 VCC1_5_B[20] VCC1_05[27] C328 VSS[035] VSS[133]
L23 VCC1_5_B[21] VCC1_05[28] V18 AH10 VSS[036] VSS[134] P15
L24 22U_0805_6.3V4Z AH13 P16
VCC1_5_B[22] VSS[037] VSS[135]

VCCA3GP
L25 VCC1_5_B[23] VCCDMIPLL R29 AH16 VSS[038] VSS[136] P17
2
M24 VCC1_5_B[24] AH19 VSS[039] VSS[137] P23
M25 VCC1_5_B[25] VCC_DMI[1] AE28 AH2 VSS[040] VSS[138] P28
N23 AE29 +VCCP AF28 P29
+5VALW +3VALW VCC1_5_B[26] VCC_DMI[2] VSS[041] VSS[139]
N24 VCC1_5_B[27] AH22 VSS[042] VSS[140] R11
N25 VCC1_5_B[28] V_CPU_IO[1] AC23 AH24 VSS[043] VSS[141] R12
P24 VCC1_5_B[29] V_CPU_IO[2] AC24 AH26 VSS[044] VSS[142] R13
1

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P25 VCC1_5_B[30] AH3 VSS[045] VSS[143] R14
R366 D15 R24 AF29 0.1U_0402_16V4Z +3VS 1 1 1 AH4 R15
VCC1_5_B[31] VCC3_3[01] VSS[046] VSS[144]

C329

C330

C331
C (DMI) C
R25 VCC1_5_B[32] 1 AH8 VSS[047] VSS[145] R16
10_0402_5% CH751H-40_SC76 R26 AD2 0.1U_0402_16V4Z +3VS AJ5 R17
VCC1_5_B[33] VCC3_3[02] C332 VSS[048] VSS[146]
R27 VCC1_5_B[34] 1 (SATA) B11 VSS[049] VSS[147] R18
ICH_V5REF_SUS 2 2 2
2

T23 VCC1_5_B[35] VCC3_3[03] AC8 +3VS B14 VSS[050] VSS[148] R28

C333 2
20 mils T24 VCC1_5_B[36] VCC3_3[04] AD8 B17 VSS[051] VSS[149] R4

VCCP_CORE
1 T27 VCC1_5_B[37] VCC3_3[05] AE8 B2 VSS[052] VSS[150] T12
C334 +3VS 2
T28 VCC1_5_B[38] VCC3_3[06] AF8 B20 VSS[053] VSS[151] T13
T29 VCC1_5_B[39] B22 VSS[054] VSS[152] T14
0.1U_0402_16V4Z U24 AA3 0.1U_0402_16V4Z B8 T15
2 VCC1_5_B[40] VCC3_3[07] VSS[055] VSS[153]
U25 VCC1_5_B[41] VCC3_3[08] U7 1 C24 VSS[056] VSS[154] T16
V23 V7 C335 C26 T17
VCC1_5_B[42] VCC3_3[09] VSS[057] VSS[155]
V24 VCC1_5_B[43] VCC3_3[10] W1 C27 VSS[058] VSS[156] T2
V25 VCC1_5_B[44] VCC3_3[11] W6 C6 VSS[059] VSS[157] U12

IDE
2 +3VS
W25 VCC1_5_B[45] VCC3_3[12] W7 D12 VSS[060] VSS[158] U13
R367 Y25 VCC1_5_B[46] VCC3_3[13] Y7 D15 VSS[061] VSS[159] U14
0.1U_0402_16V4Z D18 U15
VSS[062] VSS[160]
+1.5VS 1 2 AJ6 VCCSATAPLL VCC3_3[14] A8 D2 VSS[063] VSS[161] U16
1U_0603_10V4Z

VCC3_3[15] B15 1 1 1 D4 VSS[064] VSS[162] U17

10U_0805_6.3V6M

CHB1608U301_0603 AE7 B18 E21 U23

+1.5VS VCC1_5_A[01] VCC3_3[16] VSS[065] VSS[163]
1 1 AF7 B4 C336 C337 C338 E24 U26
VCC1_5_A[02] VCC3_3[17] VSS[066] VSS[164]
ARX
C339

C340

1 AG7 B9 0.1U_0402_16V4Z E4 U27

C341 VCC1_5_A[03] VCC3_3[18] 2 2 2 VSS[067] VSS[165]
AH7 VCC1_5_A[04] VCC3_3[19] C15 E9 VSS[068] VSS[166] U3
AJ7 VCC1_5_A[05] VCC3_3[20] D13 F15 VSS[069] VSS[167] U5
PCI

2 2 1U_0603_10V4Z 0.1U_0402_16V4Z
VCC3_3[21] D5 E23 VSS[070] VSS[168] V13
2
AC1 VCC1_5_A[06] VCC3_3[22] E10 F28 VSS[071] VSS[169] V15
AC2 VCC1_5_A[07] VCC3_3[23] E7 F29 VSS[072] VSS[170] V28
ATX

AC3 VCC1_5_A[08] VCC3_3[24] F11 F7 VSS[073] VSS[171] V29

AC4 VCC1_5_A[09] +3VS G1 VSS[074] VSS[172] W2
AC5 AC12 0.1U_0402_16V4Z E2 W26
VCC1_5_A[10] VCCHDA VSS[075] VSS[173]
1 G10 VSS[076] VSS[174] W27
AC10 AD11 0.1U_0402_16V4Z +3VALW G13 Y28
+1.5VS VCC1_5_A[11] VCCSUSHDA C342 VSS[077] VSS[175]
1 AC9 VCC1_5_A[12] 1 G19 VSS[078] VSS[176] Y29
B C343 J6 T22 PAD G23 Y4 B
VCCSUS1_05[1] T23 PAD C344 2 VSS[079] VSS[177]
AA5 VCC1_5_A[13] VCCSUS1_05[2] AF20 G25 VSS[080] VSS[178] AB4
1U_0603_10V4Z AA6 G26 AB23
2 VCC1_5_A[14] 2 VSS[081] VSS[179]
VCCSUS1_5[1] AC16 VCCSUS1_5_ICH_1 T24 PAD G27 VSS[082] VSS[180] AB5
G12 VCC1_5_A[15] H25 VSS[083] VSS[181] AB6
G17 J7 VCCSUS1_5_ICH_2 T25 PAD H28 AD5
VCC1_5_A[16] VCCSUS1_5[2] +3VALW VSS[084] VSS[182]
H7 VCC1_5_A[17] H29 VSS[085] VSS[183] U4
C3 0.1U_0402_16V4Z H3 W24
VCCSUS3_3[01] VSS[086] VSS[184]
AC7 VCC1_5_A[18] 1 1 H6 VSS[087]
AD7 VCC1_5_A[19] VCCSUS3_3[02] AC18 J1 VSS[088] VSS_NCTF[01] A1
AC21 C345 C346 J25 A2
VCCSUS3_3[03] 0.1U_0402_16V4Z VSS[089] VSS_NCTF[02]
+1.5VS D1 VCCUSBPLL VCCSUS3_3[04] AC22 J26 VSS[090] VSS_NCTF[03] A28
VCCPSUS

2 2
+1.5VS VCCSUS3_3[05] AG20 J27 VSS[091] VSS_NCTF[04] A29
1 1 F1 VCC1_5_A[20] VCCSUS3_3[06] AH28 J4 VSS[092] VSS_NCTF[05] AH1
USB CORE

C347 C348 L6 J5 AH29

0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5_A[21] +3VALW VSS[093] VSS_NCTF[06]
L7 VCC1_5_A[22] VCCSUS3_3[07] P6 K23 VSS[094] VSS_NCTF[07] AJ1
M6 VCC1_5_A[23] VCCSUS3_3[08] P7 K28 VSS[095] VSS_NCTF[08] AJ2
2 2
M7 VCC1_5_A[24] VCCSUS3_3[09] C1 K29 VSS[096] VSS_NCTF[09] AJ28
VCCSUS3_3[10] N7 1 K3 VSS[097] VSS_NCTF[10] AJ29
+1.5VS W23 P1 C349 K6 B1
VCC1_5_A[25] VCCSUS3_3[11] 4.7U_0603_6.3V6K VSS[098] VSS_NCTF[11]
VCCSUS3_3[12] P2 VSS_NCTF[12] B29
PAD T26 VCC_LAN1_05_INT_ICH_1 F17 P3
VCCLAN1_05[1] VCCSUS3_3[13]
VCCPUSB

+3VS PAD T27 VCC_LAN1_05_INT_ICH_2 2 ICH8M REV 1.0

G18 VCCLAN1_05[2] VCCSUS3_3[14] P4
VCCSUS3_3[15] P5
F19 VCCLAN3_3[1] VCCSUS3_3[16] R1
1 G20 VCCLAN3_3[2] VCCSUS3_3[17] R3
C350 CHB1608U301_0603 R5
0.1U_0402_16V4Z 2.2U_0603_10V6K VCCSUS3_3[18]
1 2 A24 VCCGLANPLL VCCSUS3_3[19] R6
+1.5VS R368 R369 4.7U_0805_10V4Z
2
GLAN POWER

1 1 +1.5VS 1 2 A26 VCCGLAN1_5[1] VCCCL1_05 G22 VCCCL1_05_ICH T28 PAD

CHB1608U301_0603
1 A27
C351 C352 VCCGLAN1_5[2]
B26 VCCGLAN1_5[3] VCCCL1_5 A22 1
A C353 B27 C354 A
2 2 VCCGLAN1_5[4] @ 1U_0603_10V4Z
B28 VCCGLAN1_5[5] VCCCL3_3[1] F20 +3VS
2
VCCCL3_3[2] G21
2
+3VS B25 VCCGLAN3_3
10U_0805_6.3V6M
ICH8M REV 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH8(4/4)_POWER&GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 21 of 48
5 4 3 2 1
 5 4 3 2 1

+LCDVDD +3VS
+LCDVDD
Q6

1
1 3

S
R208 AO3413_SOT23
+5VALW
100_0402_1% 1 1 1

G
C291 C292

2
2
1+LCDVDD_R2
C290 4.7U_0603_6.3V6K
R209 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2 2
100K_0402_5%

D D

1
Q7 D
2
2N7002_SOT23 G
S 1
C293

3
0.047U_0402_16V4Z

1
Q8 2
DTC124EK_SC59

(9) GMCH_LVDDEN 2 R211 1 2

0_0402_5%
UMA@

2 R611 1 2 R213
(17) VGA_ENVDD 0_0402_5%

3
VGA@ 100K_0402_5%
1

LCD/PANEL BD. Conn.

KC FBM-L11-201209-221LMAT_0805
KC FBM-L11-201209-221LMAT_0805
+3VS
B+ L10 LCD_B+
1 2
2

+LCDVDD L9 JP8
R214 1 2 1 2
KC FBM-L11-201209-221LMAT_0805 L11 DISPOFF# 1 2 DAC_BRIG +3VS
3 3 4 4 DAC_BRIG (33)
4.7K_0402_5% 1 2 5 6 INVT_PWM
5 6 INVT_PWM (33)
D10 2 1 7 8
C CH751H-40_SC76 C295 LCD_DATA 7 8 LCD_CLK C
1

9 9 10 10 LCD_CLK (17)
1 2 DISPOFF# 22U_0805_6.3V4Z (17) LCD_DATA 11 12
(33) BKOFF# 11 12
13 13 14 14
15 15 16 16 1
17 17 18 18
TXOUT2+ 19 20 TXCLK+ C294
TXOUT2- 19 20 TXCLK- 0.1U_0402_16V4Z
(33) ENBKL 21 21 22 22
2
23 23 24 24
25 25 26 26
(9) GMCH_ENBKL 2 R215 1 TXOUT0- 27 27 28 28 TXOUT1-
UMA@ 0_0402_5% TXOUT0+ 29 30 TXOUT1+
29 30
2

31 GND1
(17) VGA_ENBKL VGA_ENBKL 2 R216 1 R218 32
VGA@ 0_0402_5% GND2
100K_0402_5% ACES_88242-3001
UMA@ ME@
1

B B

UMA@ VGA@
UMA@ RP16 0_0404_4P2R_5%
LCD_CLK 1 4 EDID_CLK_LCD
EDID_CLK_LCD (9)
LCD_DATA 2 3 EDID_DAT_LCD
EDID_DAT_LCD (9)

RP49 VGA@ 0_0404_4P2R_5%

TXOUT0- UMA@1 4 TXOUT0- 2 3
LVDSA0- VGA_TXOUT0- (17)
TXOUT0+ 2 3 TXOUT0+ 1 4
LVDSA0+ VGA_TXOUT0+ (17)
RP17 0_0404_4P2R_5%

UMA@ RP50 VGA@ 0_0404_4P2R_5%

TXOUT1- 1 4 TXOUT1- 2 3
LVDSA1- VGA_TXOUT1- (17)
TXOUT1+ 2 3 TXOUT1+ 1 4
LVDSA1+ VGA_TXOUT1+ (17)
RP18 0_0404_4P2R_5%

UMA@ RP51 VGA@ 0_0404_4P2R_5%

TXOUT2- 1 4 TXOUT2- 2 3
LVDSA2- VGA_TXOUT2- (17)
TXOUT2+ 2 3 TXOUT2+ 1 4
LVDSA2+ VGA_TXOUT2+ (17)
RP19 0_0404_4P2R_5%

UMA@ RP52 VGA@ 0_0404_4P2R_5%

TXCLK- 1 4 TXCLK- 2 3
LVDSAC- VGA_TXCLK- (17)
TXCLK+ 2 3 TXCLK+ 1 4
LVDSAC+ VGA_TXCLK+ (17)
RP20 0_0404_4P2R_5%

A 2006/12/06 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 22 of 48
5 4 3 2 1
 5 4 3 2 1

Layout Notice : Filter place as close Layout Notice : Place as close

@ KC FBM-L11-201209-221LMAT_0805 Layout Notice : 1.2V filter. Place as close
chip as possible. chip as possible.
1 2 chip as possible.
L12
+2.5V_LAN +3VALW +3V_LAN

D
L13 6 +1.2V_LAN

S
2 1 +XTALVDD 4 5
FBM-L11-160808-601LMT_06032 2

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
C370

G
1 2 2 2
0.1U_0402_16V4Z Q11 C371 1 2 2 2 2 2
1

C372

C373

C374
SI3445ADV-T1-E3_TSOP6
4.7U_0603_6.3V6K C376

C377

C378

C379

C380

C382
21.6 4.7U_0603_6.3V6K
L14 2 1 1 1
D (33) EN_WOL 2 1 1 1 1 1 D
2 1 +LAN_AVDD U12
FBM-L11-160808-601LMT_06032 2 2
C386 C387 C388
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1
0.1U_0402_16V4Z 1
5787M SA00001A200
GIGA@
L15
2 1 +LAN_BIASVDD
FBM-L11-160808-601LMT_0603 1 U12
C389
41 LAN_TX0-
TRD0_N LAN_TX0- (24)
0.1U_0402_16V4Z 28 40 LAN_TX0+
2 (15) CLK_PCIE_LAN# PCIE_REFCLK_N TRD0_P LAN_TX0+ (24)
42 LAN_RX1-
TRD1_N LAN_RX1- (24)
29 43 LAN_RX1+
(15) CLK_PCIE_LAN PCIE_REFCLK_P TRD1_P LAN_RX1+ (24)
48 LAN_TX2-
TRD2_N LAN_TX2- (24)
11 47 LAN_TX2+
(15) CLKREQ_LAN# CLKREQ TRD2_P LAN_TX2+ (24)
49 LAN_TX3-
TRD3_N LAN_TX3- (24)
50 LAN_TX3+
+1.2V_LAN 2006/12/07 TRD3_P LAN_TX3+ (24)
+3V_LAN
+3VS 1 2 3 LOW PWR
2 1 +AVDDL (CLKREQ#) and (ENERGY_DET) are R377 @ 0_0402_5%
L16 FBM-L11-160808-601LMT_060
1 32 +3VS 1 2 53 2 R379 1 2 0_0402_5% LINKLED# (24) C390 1 2 0.1U_0402_16V4Z
C391 only supported in BCM5787M R378 1K_0402_5% VMAIN_PRSNT LINKLED
1 R380 1 2 0_0402_5%
4.7U_0603_6.3V6K C392 SPD100LED
+3V_LAN 1 2 54 VAUX_PRSNT SPD1000LED 67 R382 1 2 0_0402_5% C393 1 2 4.7U_0805_10V4Z
0.1U_0402_16V4Z R381 1K_0402_5% 66 ACTIVITY# (24)
TRAFFICLED

3
2 1 Q12
T40
PAD ENG_DET 59 65 LAN_CLK CTL12 1 MMJT9435T1G_SOT223
ENERGY_DET SCLK(EECLK) SI
2 1 +GPHY_PLLVDD SI 63
L17 FBM-L11-160808-601LMT_060
1 32 35 64 LAN_DATA +1.2V_LAN
C +GPHY_PLLVDD GPHY_PLLVDD SO(EEDATA) C
C394 62 CS#
4.7U_0603_6.3V6K C395 CS

2
4
(20) PCIE_TXN4 32 PCIE_RXD_N
0.1U_0402_16V4Z 1 1
2 1 C396 C397
(20) PCIE_TXP4 31 PCIE_RXD_P
14 CTL12
0.1U_0402_16V7K PCIE_MRX_C_LTX_N4 REGCTL12 CTL25 0.1U_0402_16V4Z
(20) PCIE_RXN4 25 PCIE_TXD_N REGCTL25 18
C398 2 2 10U_0805_10V4Z
2 1 +PCIE_PLLVDD RDAC 37 2 1
L18 FBM-L11-160808-601LMT_060
1 32 (20) PCIE_RXP4 0.1U_0402_16V7K PCIE_MRX_C_LTX_P4 26 R384 1.24K_0402_1%
C400 C399 PCIE_TXD_P
GIGA@
4.7U_0603_6.3V6K C401 R384
2 1
0.1U_0402_16V4Z
XTALVDD 23 +XTALVDD
2006/12/26
(7,17,18,20,25,26) PLT_RST# 10 PERST VDDIO 6 +3V_LAN
15 +3V_LAN
VDDIO
(20,25,26) ICH_PCIE_WAKE# 12 WAKE VDDIO 19
2 1 +PCIE_VDD VDDIO 56 1 2
L19 FBM-L11-160808-601LMT_060
1 32 61 1K_0402_1% C402
C403 VDDIO 100@ 0.1U_0402_16V4Z
4.7U_0603_6.3V6K C404 +3V_LAN 1 2 58 17 1 2
SMB_CLK VDDP +2.5V_LAN
0.1U_0402_16V4Z R385 @ 4.7K_0402_5% 68
2 1 VDDP 4.7U_0603_6.3V6K C405
+3V_LAN 1 2 57 SMB_DATA
R386 @ 4.7K_0402_5% 5 +1.2V_LAN
VDDC

4
13 Q13
VDDC MBT35200MT1G_TSOP6
VDDC 20
1 2 4 GPIO_0(SERIAL_DO) VDDC 34
R387 0_0402_5% 55 CTL25 3
LAN_WP VDDC
1 2 7 GPIO_1(SERIAL_DI) VDDC 60
R388 @ 4.7K_0402_5%
1 2 GPIO2 8 36 +LAN_BIASVDD
R389 @ 4.7K_0402_5% GPIO_2 BIASVDD
Layout Notice : Place as close

1
2
5
6
PCIE_PLLVDD 30 +PCIE_PLLVDD
chip as possible. +3V_LAN 1 2 9 UART_MODE PCIE_VDD 27 +PCIE_VDD
R390 @ 0_0402_5% 33
PCIE_VDD
B +2.5V_LAN 38 B
AVDD +LAN_AVDD
XTALI 21 45
XTALI AVDD
AVDD 52
XTALO 22 XTALO
0.1U_0402_16V4Z

0.1U_0402_16V4Z
22U_0805_6.3V6M

AVDDL 39 +AVDDL +2.5V_LAN

1

2 1 2 AVDDL 44
C406

R391 16 46
C407 REG_GND AVDDL
200_0402_1% 51 Notice : 4.7u 6.3V capactor Thickness 1.25mm

GND
AVDDL
24 PCIE_GND
1 2 1
C408

Y3 Layout Notice : Filter place as close

2

69
1 2 LAN_XTALO 100@
chip as possible.
1 25MHZ_20PF_6X25000017 1
SA00001I000
C409 C410 +3V_LAN
27P_0402_50V8J 27P_0402_50V8J
2 2
1 2

1
C411
0.1U_0402_16V4Z
R392 R393
4.7K_0402_5% 4.7K_0402_5%

U13

2
8 VCC A0 1
LAN_WP 7 2
LAN_CLK WP A1
6 3
LAN_DATA 5
SCL
SDA
NC
GND 4 2006/12/27
AT24C02_SO8

A LAN_CLK 1 2 A
R394 4.7K_0402_5%
SI 2 GIGA@
1
R395 4.7K_0402_5%
CS# 1 GIGA@
2
R396 4.7K_0402_5%

Security Classification Compal Secret Data 2006/12/07

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
BCM5787MKML
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 23 of 48
5 4 3 2 1
 5 4 3 2 1

D U14 D

GST5009
GIGA@

C1165
1 1
C1166 GbE Transformer: GST5009 (SP050005610)
5787 no need0.1U_0402_16V4Z 0.1U_0402_16V4Z 10/100 Transformer : TST1284-LF (SP050001X10)
@ @
external AC 2 2 +2.5V_LAN +3V_LAN 2006/12/07
termination
2006/12/07

1
300_0402_5% JP11
2006/12/21
1

1
49.9_0402_1% R630 R631 +3V_LAN R636 2 1 12
R632 R633 R634 R635 0_0603_5% 0_0603_5% Amber LED+
@ @ @ @ @ ACTIVITY# 11
49.9_0402_1% 49.9_0402_1% 49.9_0402_1% U14 (23) ACTIVITY# Amber LED-
SHLD2 16
RJ45_MIDI3-

2
8 PR4-
2

1 TCT1 MCT1 24 SHLD1 15

(23) LAN_TX3- LAN_TX3- 2 23 RJ45_MIDI3- RJ45_MIDI3+ 7
LAN_TX3+ TD1+ MX1+ RJ45_MIDI3+ PR4+
(23) LAN_TX3+ 3 TD1- MX1- 22
RJ45_MIDI1- 6 PR2-
4 TCT2 MCT2 21
(23) LAN_TX2- LAN_TX2- 5 20 RJ45_MIDI2- RJ45_MIDI2- 5
LAN_TX2+ TD2+ MX2+ RJ45_MIDI2+ PR3-
(23) LAN_TX2+ 6 TD2- MX2- 19
RJ45_MIDI2+ 4
C PR3+ C
7 TCT3 MCT3 18
(23) LAN_RX1+ LAN_RX1+ 8 17 RJ45_MIDI1+ RJ45_MIDI1+ 3
LAN_RX1- TD3+ MX3+ RJ45_MIDI1- PR2+
(23) LAN_RX1- 9 TD3- MX3- 16
RJ45_MIDI0- 2 PR1-
10 TCT4 MCT4 15 SHLD2 14
(23) LAN_TX0- LAN_TX0- 11 14 RJ45_MIDI0- RJ45_MIDI0+ 1
LAN_TX0+ TD4+ MX4+ RJ45_MIDI0+ PR1+
(23) LAN_TX0+ 12 TD4- MX4- 13 SHLD1 13
LINKLED# 10
(23) LINKLED# Green LED-
1

R637 R638 R639 R640 R641 2 1 300_0402_5% 9 Green LED+

1
49.9_0402_1% 49.9_0402_1% 0.1U_0402_16V4Z 0.5u_GST5009 +3V_LAN
49.9_0402_1% 49.9_0402_1% 100@ 100@ TYCO_3-440470-4
100@ 100@ 100@ R642 R643 ME@
75_0402_1% 75_0402_1%
2

1 1
C1168 C1170

2
1 1
C1171 C1172 0.1U_0402_16V4Z
2 2 RJ45_GND LANGND
1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1
2 100@ 2 100@ C1173
1000P_1206_2KV7K C1174 C1175
4.7U_0805_10V4Z

RJ45_TER2

RJ45_TER3
2 2

0.1U_0402_16V4Z

RJ45_MIDI3+ R644 1 2 100@ 0_0402_5%

RJ45_MIDI3- R645 1 2 100@ 0_0402_5%

RJ45_MIDI2+ R646 1 2 100@ 0_0402_5%

RJ45_MIDI2- R647 1 2 100@ 0_0402_5%
B B

1
R648 R649
75_0402_1% 75_0402_1%

RJ45_GND
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 24 of 48
5 4 3 2 1
 A B C D E

SATA HDD Conn.

JP9 +5VS +3VS

1000P_0402_50V7K
22U_1206_6.3V6M
1 GND

1000P_0402_50V7K
PSATA_ITX_DRX_P0

0.1U_0402_16V4Z

0.1U_0402_16V4Z
(19) PSATA_ITX_DRX_P0 2 HTX+
PSATA_ITX_DRX_N0 3 1 1 1 1 1 1 1 1
(19) PSATA_ITX_DRX_N0 HTX-

C357

C358

C361

C363

C366
4 C362
GND
(19) PSATA_IRX_DTX_N0_C 2 1 PSATA_IRX_DTX_N0 5 HRX-
C360 22U_0805_6.3V4Z C365
C3552 1 PSATA_IRX_DTX_P0 6 @
(19) PSATA_IRX_DTX_P0_C HRX+ 2 2 2 2 2 2 2 2
C356 7
3900P_0402_50V7K GND 1U_0603_10V4Z @ 1U_0603_10V4Z
1 1
3900P_0402_50V7K @
@ HD CONN
Pleace near
1 2 +3VS_SATA 8 Pleace near HD CONN
+3VS VCC3.3
R370 9
@ 0_0805_5% VCC3.3
10 VCC3.3
11 GND
12 GND
13 GND
+5VS 14 VCC5
15 VCC5
16 VCC5
17 GND
18 RESERVED
19 GND Main SATA +5V Default
20 JP10
VCC12
21 VCC12 G1 23 1 1 2 2
22 VCC12 G2 24 3 3 4 4
R372 1 2@ 0_0402_5% 5 5 PD_D8
(19) IDERST_CD#
R373 33_0402_5% PD_D7 6 6 PD_D9
(7,17,18,20,23,26) PLT_RST# 1 2 7 7 8 8
SUYIN_127043FB022G345ZR_NR PD_D6 9 9 PD_D10
PD_D5 10 10 PD_D11
ME@ 11 11 12 12
PD_D4 PD_D12
(NEW) PD_D3
13 13
15 15
14 14 PD_D13
PD_D2 16 16 PD_D14
Change Library PD_D1
17 17 18 18 PD_D15
19 19 20 20
+3VS PD_D0 21 21 PD_DREQ
22 22 PD_IOR#
PD_DREQ (19)
23 23 24 24 PD_IOR# (19)

1
PD_IOW# 25 25
2
(19) PD_IOW#
PD_IORDY 26 26 PD_DACK# 2
(19) PD_IORDY 27 27 28 28 PD_DACK# (19)
R374 PD_IRQ 29 29
10K_0402_5%
(19) PD_IRQ
PD_A1 30 30 PDIAG#
31 31 32 32 1 2
PD_A0 33 33 PD_A2 R375 100K_0402_5% +5VS
PD_CS#1 34 34 PD_CS#3

2
(19) PD_CS#1 35 35 36 36 PD_CS#3 (19)
ODD_LED# 37 37
+5VS
(37) ODD_LED# 38 38
39 39 40 40
+5VS 41 41 42 42 +5VS
43 43 44 44 2 1
45 45 C367 0.1U_0402_16V4Z
PRI_CSEL 46 46
1 1 47 47 48 48
49 49 50 50

2
C368 C369 53 G1 PD_D[0..15]
1U_0603_10V4Z 10U_0805_10V4Z G2 54
OCTEK_CDR-50DY1G
PD_D[0..15] (19)
2 2 R376 PD_A[0..2]
ME@ PD_A[0..2] (19)
470_0402_5%

1
+1.5VS_PEC
4.7U_0805_10V4Z JP12

0_0402_5% EXPCARD@ 1
3 Express Card Power Switch 1 1
(20) USB20_N5
USB20_N5 R415 1 2 USB5- 2
GND
USB_D-
3
C427 C428 USB20_P5 R416 1 2 USB5+ 3
(20) USB20_P5 USB_D+
+1.5VS 0.1U_0402_16V4Z EXPCARD@ EXPCARD@ EXPCARD@ CPUSB# 4
EXPCARD@ U16 +1.5VS_PEC 2 2 0_0402_5% CPUSB#
5 RSV
2 1 12 1.5Vin 1.5Vout 11 6 RSV
C429 0.1U_0402_16V4Z 14 13 ICH_SMBCLK 7
1.5Vin 1.5Vout (15,20,26) ICH_SMBCLK SMB_CLK
+3VS ICH_SMBDATA 8
+3VS_PEC (15,20,26) ICH_SMBDATA SMB_DATA
EXPCARD@ 9
+1.5VS_PEC +1.5V
2 1 2 3 EXPCARD@ 10
3.3Vin 3.3Vout +3V_PEC +1.5VS_PEC +1.5V
C430 0.1U_0402_16V4Z 4 5 (20,23,26) ICH_PCIE_WAKE# R417 1 2 PCIE_PME#_R 11
EXPCARD@ 3.3Vin 3.3Vout +3V_PEC 0_0402_5% WAKE#
+3VALW +3V_PEC 12 +3.3VAUX
2 1 17 15 PERST# 13
C431 0.1U_0402_16V4Z AUX_IN AUX_OUT PERST#
+3VS_PEC 14 +3.3V
PLT_RST# 6 19 1 1 15
(7,17,18,20,23,26) PLT_RST# SYSRST# OC# +3.3V
CLKREQ_NC1# 16
(15) CLKREQ_NC1# CLKREQ#
SYSON 20 8 PERST# C432 EXPCARD@ C433 EXPCARD@ CPUSB# 17
(33,38,44) SYSON SHDN# PERST# CPPE#
0.1U_0402_16V4Z 4.7U_0805_10V4Z CLK_PCIE_NC1# 18
2 2 (15) CLK_PCIE_NC1# REFCLK-
SUSP# 1 16 CLK_PCIE_NC1 19
(17,28,29,33,35,38,44,45) SUSP# STBY# NC (15) CLK_PCIE_NC1 REFCLK+
20 GND
10 7 PCIE_RXN3 21
CPPE# GND (20) PCIE_RXN3 PERn0
PCIE_RXP3 22
+3VS_PEC (20) PCIE_RXP3 PERp0
CPUSB# 9 23
(20) CPUSB# CPUSB# GND
4.7U_0805_10V4Z (20) PCIE_TXN3 PCIE_TXN3 24
PCIE_TXP3 PETn0
18 RCLKEN (20) PCIE_TXP3 25 PETp0
26 GND
R5538_QFN20 1 1 GND 29
27 GND GND 30
C434 EXPCARD@C435 EXPCARD@ 28
0.1U_0402_16V4Z GND
4 EXPCARD@ 4
2 2 FOX_1CH4110C

ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD/CDROM/ EXP_CARD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT10/11 LA-3591P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 25 of 48
A B C D E
 A B C D E

1
Mini-Express Card(Slot 1-WLAN) Mini-Express Card(Slot 2-TV-Tuner) 1

(20,23,25) ICH_PCIE_WAKE#
JP13 JP14
(20,23,25) ICH_PCIE_WAKE# 1 1 2 2 +3VS 1 1 2 2 +3VS
BT_AVTIVE R418 2 1 @ 0_0402_5% 3 4 BT_AVTIVE R419 2 1@ 0_0402_5% 3 4
WLAN_AVTIVE R420 2 @ 0_0402_5% 3 4 WLAN_AVTIVE R421 2 3 4
1 5 5 6 6 +1.5VS 1@ 0_0402_5% 5 5 6 6 +1.5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z
(15) CLKREQ_MCARD# 7 7 8 8 CLKREQ_MCARD1# 7 7 8 8

0.1U_0402_16V4Z

0.1U_0402_16V4Z
9 9 10 10 1 9 9 10 10 1

C436

C437
CLK_PCIE_MCARD# 11 12 1 CLK_PCIE_MCARD1# 11 12 1
(15) CLK_PCIE_MCARD# 11 12 (15) CLK_PCIE_MCARD1# 11 12

C438

C439
CLK_PCIE_MCARD 13 14 CLK_PCIE_MCARD1 13 14
(15) CLK_PCIE_MCARD 13 14 (15) CLK_PCIE_MCARD1 13 14
15 15 16 16 15 15 16 16
2 2
17 17 18 18 MINI2@ 17 17 18 18 MINI1@
RF_OFF# 2 2
19 19 20 20 MINI2@ 19 19 20 20 RF_OFF# (33) MINI1@
21 22 PLT_RST# 21 22 PLT_RST#
21 22 PLT_RST# (7,17,18,20,23,25) 21 22 PLT_RST# (7,17,18,20,23,25)
23 24 +3VALW_MINI PCIE_RXN1 23 24 +3VALW_MINI +3VALW_MINI
(20) PCIE_RXN2 23 24 (20) PCIE_RXN1 23 24
25 26 +3VALW_MINI PCIE_RXP1 25 26
(20) PCIE_RXP2 25 26 (20) PCIE_RXP1 25 26
27 27 28 28 27 27 28 28
29 30 ICH_SMBCLK ICH_SMBCLK (15,20,25) 29 30 ICH_SMBCLK ICH_SMBCLK (15,20,25)
29 30 ICH_SMBDATA PCIE_TXN1 29 30 ICH_SMBDATA
(20) PCIE_TXN2 31 31 32 32 ICH_SMBDATA (15,20,25) (20) PCIE_TXN1 31 31 32 32 ICH_SMBDATA (15,20,25)
33 34 (20) PCIE_TXP1 PCIE_TXP1 33 34
(20) PCIE_TXP2 33 34 33 34
35 35 36 36 USB20_N1 (20) 35 35 36 36 USB20_N9 (20)
37 37 38 38 USB20_P1 (20) 37 37 38 38 USB20_P9 (20)
39 39 40 40 39 39 40 40
41 41 42 42 41 41 42 42
43 43 44 44 WIRELESS_LED# (37) 43 43 44 44 WIRELESS_LED# (37)
45 45 46 46 45 45 46 46
47 47 48 48 47 47 48 48
49 49 50 50 49 49 50 50
51 51 52 52 51 51 52 52
2 2
53 GND1 GND2 54 53 GND1 GND2 54 Q43
+3VALW_MINI
AO3413_SOT23
FOX_AS0B226-S56N-7F FOX_AS0B226-S56N-7F
ME@ ME@ 1 3

S
+3VALW

G
2
C1189

MINI_ON# 0.1U_0402_16V7K
(20) MINI_ON#

2006/12/26

+5VS
BT MODULE CONN.

1
3 3

+3VALW
MDC CONN. R424
10K_0402_1%
1

C440
RF_OFF2

12
1 2
R425 JP15
10K_0402_1%
1 2 1U_0603_10V4Z
GND1 RES0
2

(19) HDA_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4

5 6 2 Q14
GND2 3.3V +3VALW (33) BT_OFF#
AZ_SYNC 7 8 DTC124EK_SC59
(19) HDA_SYNC_MDC IAC_SYNC GND3
R426 1 2 AZ_SDIN3 9 10
(19) HDA_SDIN1 IAC_SDATA_IN GND4
(19) HDA_RST_MDC# R427 2 133_0402_5% 11 12 +3VS Q15 +3VS_BT2
@ 0_0402_5% IAC_RESET# IAC_BITCLK HDA_BITCLK_MDC (19) C441
1

D16

D
3
3 1 2 1
2 AO3413_SOT23
GND
GND
GND
GND
GND
GND

1 R428 0.1U_0402_16V4Z
3 @ 10_0402_5% BTONLED

G
(19) KILL_MDC# (37) BTONLED
ACES_88018-124G JP16

2
13
14
15
16
17
18

DAP202U_SOT323 ME@
2

1 (33) EC_BT_LED# 2 1 1 1 GND 9

2 2

1
Connector for MDC Rev1.5 C442 R672 0_0402_5% @ (20) USB20_P7 USB20_P7 3
@ 10P_0402_50V8J USB20_N7 3
(20) USB20_N7 4 4
2 BT_AVTIVE 5 5
WLAN_AVTIVE 6
Q16 BTON_LED 6
2 7 7
DTC124EK_SC59 8 10
2006/12/26 8 GND
ACES_87213-0800G
ME@

3
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card / MDC CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 26 of 48
A B C D E
 A B C D E F G H

+S1_VCC +3VS
IDSEL:AD20
VPPD0
VPPD1 (PIRQE#/B#, +S1_VCC
VCCD0#
VCCD1#
GNT#2, PCMCIA Power Control VCCD0# 1 2
REQ#2) R430 PCMCIA@
10K_0402_5%
40mil

M13

M12

G13
N13

N12

D12
H11

G1
C8

N4
U17 VCCD1#

A7

B4

K2

F3
L9
L6
1 2
U18 13 R431 PCMCIA@
10K_0402_5%
VCC
12

VCCD1#
VCCD0#

VPPD1
VPPD0

VCCA2
VCCA1

VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
VCC
9 12V VCC 11
+S1_VPP

+5VS 40mil
PCI_AD31 C2 B2 S1_D10 W=40mil 1
1 PCI_AD30 AD31 CAD31/D10 S1_D9 1
C1 AD30 CAD30/D9 C3 VPP 10
PCI_AD29 D4 B3 S1_D1 1 1 C443
PCI_AD28 AD29 CAD29/D1 S1_D8 C444 0.1U_0402_16V4Z
D2 AD28 CAD28/D8 A3 5 5V
PCI_AD27 S1_D0 C445 2 PCMCIA@
D1 AD27 CAD27/D0 C4 6 5V
PCI_AD26 E4 A6 S1_A0 PCMCIA@
10U_0805_10V4Z
PCI_AD25 AD26 CAD26/A0 S1_A1 2 2
0.1U_0402_16V4Z VCCD0#
E3 AD25 CAD25/A1 D7 VCCD0 1
PCI_AD24 E2 C7 S1_A2 PCMCIA@ 2 VCCD1#
PCI_AD23 AD24 CAD24/A2 S1_A3 +3VS VCCD1 VPPD0
F2 AD23 CAD23/A3 A8 VPPD0 15
(18,28) PCI_AD[0..31] PCI_AD[0..31] PCI_AD22 F1 D8 S1_A4 14 VPPD1
PCI_AD21 AD22 CAD22/A4 S1_A5 VPPD1
PCI_CBE#[0..3] PCI_AD20
G2 AD21 CAD21/A5 A9
S1_A6
W=40mil
(18,28) PCI_CBE#[0..3] G3 AD20 CAD20/A6 C9 3 3.3V
PCI_AD19 H3 A10 S1_A25 1 1 4 8
AD19 CAD19/A25 3.3V OC

SHDN
PCI_AD18 H4 B10 S1_A7 C446 C447

GND
PCI_AD17 AD18 CAD18/A7 S1_A24
J1 AD17 CAD17/A24 D10
PCI_AD16 J2 E12 S1_A17 PCMCIA@
10U_0805_10V4Z
AD16 CAD16/A17

1
PCI_AD15 S1_IOWR# 2 2
0.1U_0402_16V4Z CP2211FD3_SSOP16
N2 F10

16
CLK_PCI_CB PCI_AD14 AD15 CAD15/IOWR# S1_A9 PCMCIA@ R432

7
M3 AD14 CAD14/A9 E13 PCMCIA@
PCI_AD13 N3 F13 S1_IORD# 10K_0402_5%
AD13 CAD13/IORD#
1

PCI_AD12 K4 F11 S1_A11 PCMCIA@

R433 PCI_AD11 AD12 CAD12/A11 S1_OE#
M4 AD11 CAD11/OE# G10
@ 10_0402_5% PCI_AD10 S1_CE2#

2
K5 AD10 CAD10/CE2# G11
PCI_AD9 L5 G12 S1_A10
PCI_AD8 AD9 CAD9/A10 S1_D15
M5 AD8 CAD8/D15 H12
PCI_AD7 S1_D7
2

1 K6 H10
C448 PCI_AD6
PCI_AD5
M6
N6
AD7
AD6
CAD7/D7
CAD6/D13 J11
J12
S1_D13
S1_D6
PCMCIA Socket 1
JP17
ME@
@ 15P_0402_50V8J PCI_AD4 AD5 CAD5/D6 S1_D12 GND
M7 AD4 CAD4/D12 K13 35 GND
2 PCI_AD3 S1_D5 S1_D3
N7 J10 2

PCI Interface
PCI_AD2 AD3 CAD3/D5 S1_D11 S1_CD1# DATA3
L7 AD2 CAD2/D11 K10 36 CD1#
PCI_AD1 S1_D4 S1_D4

CARDBUS
K7 AD1 CAD1/D4 K12 3 DATA4
PCI_AD0 N8 L13 S1_D3 S1_D11 37
AD0 CAD0/D3 S1_D5 DATA11
4 DATA5
2 PCI_CBE#3 S1_REG# S1_A[0..25] S1_D12 2
E1 CBE3# CCBE3#/REG# B7 S1_A[0..25] 38 DATA12
PCI_CBE#2 J3 A11 S1_A12 S1_D6 5
PCI_CBE#1 CBE2# CCBE2#/A12 S1_A8 S1_D[0..15] S1_D13 DATA6
N1 CBE1# CCBE1#/A8 E11 S1_D[0..15] 39 DATA13
PCI_CBE#0 N5 H13 S1_CE1# S1_D7 6
CBE0# CCBE0#/CE1# S1_D14 DATA7
40 DATA14
PCI_RST# G4 B9 S1_RST S1_CE1# 7
(18,28,33,35) PCI_RST# PCIRST# CRST#/RESET CE1#
(18,28) PCI_FRAME# J4 B11 S1_A23 S1_D15 41
FRAME# CFRAME#/A23 S1_A15 S1_A10 DATA15
(18,28) PCI_IRDY# K1 IRDY# CIRDY#/A15 A12 8 ADD10
(18,28) PCI_TRDY# K3 A13 S1_A22 S1_CE2# 42
TRDY# CTRDY#/A22 S1_A21 S1_OE# CE2#
(18,28) PCI_DEVSEL# L1 DEVSEL# CDEVSEL#/A21 B13 9 OE#
L2 C12 S1_A20 S1_VS1 43
(18,28) PCI_STOP# STOP# CSTOP#/A20 VS1#
L3 C13 S1_A14 S1_A11 10
(18,28) PCI_PERR# PERR# CPERR#/A14 ADD11
M1 A5 S1_WAIT# S1_IORD# 44
(18,28) PCI_SERR# SERR# CSERR#/WAIT# IORD#
(18,28) PCI_PAR M2 D13 S1_A13 S1_A9 11
PCI_REQ#2 PAR CPAR/A13 S1_INPACK# S1_IOWR# ADD9
(18) PCI_REQ2# A1 PCIREQ# CREQ#/INPACK# B8 45 IOWR#
B1 C11 S1_WE# S1_A8 12
(18) PCI_GNT2# PCIGNT# CGNT#/WE# ADD8
CLK_PCI_CB H1 B12 1 2 S1_A16 S1_A17 46
(15) CLK_PCI_CB PCICLK CCLK/A16 ADD17
R434 PCMCIA@
33_0402_5% S1_A13 13
S1_BVD1 S1_A18 ADD13
L8 RIOUT#_PME# CSTSCHG/BVD1_STSCHG# C5 47 ADD18
+3VS 1 2 L11 D5 S1_WP S1_A14 14
R435 PCMCIA@
10K_0402_5% SUSPEND# CCLKRUN#/WP_IOIS16# S1_A19 ADD14
48 ADD19
PCI_AD20 1 2 F4 D11 S1_A19 S1_WE# 15
R436 PCMCIA@
100_0402_5% IDSEL CBLOCK#/A19 S1_A20 WE#
49 ADD20
R6661 2 0_0402_5% PCI_PIRQ_CB K8 D6 S1_RDY# S1_RDY# 16
(18) PCI_PIRQE# MFUNC0 CINT#/READY_IREQ# READY
R6671 2 0_0402_5% PAD SD_PULLHIGH N9 S1_A21 50
(18) PCI_PIRQC# MFUNC1 ADD21
@ T42 MFUNC2 K9 M9 PCM_SPK# +S1_VCC 17
MFUNC2 SPKROUT PCM_SPK# (29) VCC
N10 B5 S1_BVD2 +S1_VCC 51
(20,28,33,35) SIRQ MFUNC3 CAUDIO/BVD2_SPKR# VCC
SM_CD# L10 +S1_VPP 18
5IN1_LED# MFUNC4 S1_CD2# +S1_VCC VPP
N11 MFUNC5 CCD2#/CD2# A4 +S1_VPP 52 VPP
0_0402_5% M11 L12 S1_CD1# S1_A16 19
R6791 MFUNC6 CCD1#/CD1# ADD16
(20,28,33,35) PCI_CLKRUN# 2 SDOC# J9 MFUNC7 CVS2/VS2# D9 S1_VS2 S1_A22 53 ADD22
@ C6 S1_VS1 1 1 S1_A15 20
3 CVS1/VS1 S1_D2 C449 C450 S1_A23 ADD15 3
CRSV3/D2 A2 54 ADD23
PCI_RST# M10 E10 S1_A18 S1_A12 21
GRST# CRSV2/A18 S1_D14 10U_0805_10V4Z 0.1U_0402_16V4Z S1_A24 ADD12
MFUNC5[3:0] = (0 1 0 1) CRSV1/D14 J13
PCMCIA@ 2 2 PCMCIA@ S1_A7
55 ADD24
22 ADD7
MFUNC5[4] = 1 +3VS S1_A25 56
S1_A6 ADD25
1 2 SM_CD# E7
SD/MMC/MS/SM H7 S1_CD2# S1_VS2
23
57
ADD6
R438 43K_0402_5% VCC_SD MSINS# S1_A5 VS2#
MSPWREN#/SMPWREN# J8 2 24 ADD5
@ E8 H8 C451 S1_RST 58
SDCD# MSBS/SMDATA1 RESET
1 2 5IN1_LED# F8 SDWP/SMWPD# MSCLK/SMRE# E9 S1_A4 25 ADD4
R614 10K_0402_5% G7 G9 PCMCIA@
10P_0402_50V8K +S1_VPP S1_WAIT# 59
SDPWREN33# MSDATA0/SMDATA2 1 S1_A3 WAIT#
@ MSDATA1/SMDATA6 H9 26 ADD3
SDOC# S1_INPACK#

2006/06/08
1 2 H5 SDCLKI MSDATA2/SMDATA5 G8 60 INPACK#
R615 10K_0402_5% F9 1 1 S1_A2 27
MSDATA3/SMDATA3 C452 C453 S1_REG# ADD2
@ F6 SDCLK/SMWE# 61 REG#
1 2 MFUNC2 E5 S1_A1 28
R620 10K_0402_5% SDCMD/SMALE 0.1U_0402_16V4Z S1_BVD2 ADD1
E6 SDDAT0/SMDATA7 SMBSY# H6 62 BVD2
+3VS 2
10U_0805_10V4Z 2 PCMCIA@ S1_A0
@ F7 SDDAT1/SMDATA0 SMCD# J7 29 ADD0
+S1_VCC PCMCIA@ S1_BVD1
F5
G6
SDDAT2/SMCLE SMWP# J6
J5 S1_CD1# S1_D0
63
30
BVD1 (NEW)
SDDAT3/SMDATA4 SMCE# S1_D8 DATA0
1 1 2 64 DATA8
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

C454 C455 1 1 G5 GND_SD C456 S1_D1 31

PCMCIA@ PCMCIA@ C457 C458 S1_D9 DATA1
65 DATA9 GND 69
4.7U_0805_10V4Z 0.1U_0402_16V4Z PCMCIA@ PCMCIA@ PCMCIA@
10P_0402_50V8K S1_D2 32 70
2 2 1 DATA2 GND
C10
K11

0.1U_0402_16V4Z 0.1U_0402_16V4Z CB714_LFBGA169 S1_OE# S1_D10

F12

1 2 66 71
M8

+S1_VCC
D3
H2

B6
L4

2 2 PCMCIA@ R439 PCMCIA@

43K_0402_5% S1_WP DATA10 GND
33 WP GND 72
S1_WP 2 1 +S1_VCC S1_CD2# 67
SA014100310 R440 PCMCIA@
43K_0402_5% CD2#
34 GND
S1_RST 1 2 +S1_VCC 68
R441 PCMCIA@
43K_0402_5% GND
S1_CE1# 1 2 +S1_VCC SANTA_130601-7_LT
+3VS R442 PCMCIA@
43K_0402_5%
4
40mil S1_CE2# 4
1 2
0.1U_0402_16V4Z
PCMCIA@
0.1U_0402_16V4Z
PCMCIA@ CB1410 P/N: SA014100310
R443 PCMCIA@
43K_0402_5%
+S1_VCC
4 IN 1 Socket
1 1 1 1 1 1
(HDQ70)
C459 C460 C461 C463 C464 C465

0.1U_0402_16V4Z
PCMCIA@ 2 2 2 2 2 2
Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
PCMCIA@ PCMCIA@ PCMCIA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCMCIA_ENE CB1410
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 27 of 48
A B C D E F G H
 5 4 3 2 1

+3VS
SD,MMC,MS,XD muti-function pin define
MDIO SD Card MMC Card MS Card XD Card
U19
(18,27) PCI_AD[0..31] PIN Name PIN Name PIN Name PIN Name PIN Name

0.01U_0402_16V7K
PCI_AD31 125 10 1 1
PCI_AD30 AD31 VCC_PCI3V
126 AD30 VCC_PCI3V 20 MDIO00 SDCD# MMCCD# XDCD0#

C466
PCI_AD29 127 27 C467
PCI_AD28 AD29 VCC_PCI3V
1 32 MDIO01 MSCD# XDCD1#
PCI_AD27
PCI_AD26
2
3
AD28
AD27 R5C832 VCC_PCI3V
VCC_PCI3V 41
128
2 832@ 2 10U_0805_10V4Z
832@
+3VS
MDIO02 XDCE#
PCI_AD25 AD26 VCC_PCI3V R625
5 AD25
PCI_AD24 6 61 1 2 0_0805_5% MDIO03 SDWP# XDR/B#
PCI_AD23 AD24 VCC_RIN
9 AD23

0.01U_0402_16V7K
PCI_AD22 11 16 MDIO04 SDPWR0 MMCPWR MSWR XDPWR
PCI_AD21 AD22 VCC_ROUT
12 AD21 VCC_ROUT 34 1 1
D PCI_AD20 D
14 AD20 VCC_ROUT 64 MDIO05 SDPWR1 XDWP#

C468
0.01U_0402_16V7K

0.01U_0402_16V7K
U19 PCI_AD19 C471

0.47U_0603_16V4Z

0.47U_0603_16V4Z
15 AD19 VCC_ROUT 114 1 1 1 1
PCI_AD18 17 120 MDIO06 SDLED# MMCLED# MSLED# XDLED#
AD18 VCC_ROUT 2 832@ 2 10U_0805_10V4Z

C472

C473

C474

C475
PCI_AD17 18 R626
PCI_AD16 AD17 832@ 2 0_0805_5% 832@
19 AD16 VCC_3V 67 1 +3VS 2 832@ 2 832@ 2 2
MDIO07 MSEXTCK
PCI_AD15 36 R627
AD15

0.01U_0402_16V7K
PCI_AD14 37 86 1 832@ 2 0_0805_5% 1 1 MDIO08 SDCCMD MMCCMD MSBS XDWE#
PCI_AD13 AD14 VCC_MD3V
R5C833 38 AD13

C476
833@ PCI_AD12 39 98 +3V_PHY C477 MDIO09 SDCCLK MMCCLK MSCCLK XDRE#
SA00001HX10 PCI_AD11 AD12 AVCC_PHY3V 10U_0805_10V4Z
40 AD11 AVCC_PHY3V 106
PCI_AD10 2 832@ 2
42 AD10 AVCC_PHY3V 110 832@ MDIO10 SDCDAT0 MMCDAT MSCDAT0 XDCDAT0
PCI_AD9 43 112 832@
PCI_AD8 AD9 AVCC_PHY3V
44 AD8 MDIO11 SDCDAT1 MSCDAT1 XDCDAT1
PCI_AD7 46 113 IEEE1394_TPBIAS0
PCI_AD6 AD7 TPBIAS0 +3V_PHY
47 AD6 MDIO12 SDCDAT2 MSCDAT2 XDCDAT2
PCI_AD5 48 109 IEEE1394_TPAP0 L20
PCI_AD4 AD5 TPAP0 IEEE1394_TPAN0
49 AD4 TPAN0 108 +3VS 1 2 MDIO13 SDCDAT3 MSCDAT3 XDCDAT3
PCI_AD3 50 AD3

1000P_0402_50V7K
PCI_AD2 IEEE1394_TPBP0 832@ MDIO14 XDCDAT4

0.1U_0402_16V4Z
22U_0805_6.3V6M
51 AD2 TPBP0 105
PCI_AD1 52 104 IEEE1394_TPBN0 BLM21A601SPT_0805
PCI_AD0 AD1 TPBN0
53 AD0 1 1 1 MDIO15 XDCDAT5
80 SDCD#_XDCD0#
MDIO00 SDCD#_XDCD0# (37)

C478

C479

C481
79 MSCD#_XDCD1 MDIO16 XDCDAT6
MDIO01 MSCD#_XDCD1 (37)
PCI_CBE#3 7 78 XD_CE# 832@
(18,27) PCI_CBE#3 C/BE3# MDIO02 PAD T34 2
(18,27) PCI_CBE#2
PCI_CBE#2 21 77 SDWP#_XDRB#
SDWP#_XDRB# (37) 832@2 2 832@ MDIO17 XDCDAT7
PCI_CBE#1 C/BE2# MDIO03 SDPWR0_MSPWR_XDPWR
(18,27) PCI_CBE#1 35 C/BE1# MDIO04 76
PCI_CBE#0 45 75 XDWP# MDIO18 XDCLE
(18,27) PCI_CBE#0 C/BE0# MDIO05 PAD T35
MDIO06 74
73 TP_MSEXTCK MDIO19 XDALE
PCI_PAR MDIO07 SDCMD_MSBS
(18,27) PCI_PAR 33 PAR MDIO08 88 SDCMD_MSBS (37)
PCI_FRAME# 23 84 SDCLK_MSCLK
(18,27) PCI_FRAME# FRAME# MDIO09 SDCLK_MSCLK
PCI_TRDY# 25 82 SDDATA0_MSDATA0
C (18,27) PCI_TRDY#
PCI_IRDY# 24
TRDY# MDIO10
81 SDDATA1_MSDATA1
SDDATA0_MSDATA0 (37) Function set pin define C
(18,27) PCI_IRDY# IRDY# MDIO11 SDDATA1_MSDATA1 (37)
PCI_STOP# 29 93 SDDATA2_MSDATA2 UDIO3 UDIO4 MSEN XDEN Function
(18,27) PCI_STOP# STOP# MDIO12 SDDATA2_MSDATA2 (37)
832@ PCI_DEVSEL# 26 90 SDDATA3_MSDATA3
(18,27) PCI_DEVSEL# DEVSEL# MDIO13 SDDATA3_MSDATA3 (37)
PCI_AD22 1 2 CBS_IDSEL 8 91 XDD4 Pull-up Pull-up Pull-up Pull-up Enable
IDSEL MDIO14 PAD T36
R444 100_0402_5% PCI_PERR# 30 89 XDD5
(18,27) PCI_PERR# PERR# MDIO15 PAD T37 SD,XD,MS,MMC Card
PCI_SERR# 31 92 XDD6
(18,27) PCI_SERR# SERR# MDIO16 PAD T38
87 XDD7
MDIO17 PAD T39 +3VS
85 XDCLE
PCI_REQ0# MDIO18 XDALE
(18) PCI_REQ0# 124 REQ# MDIO19 83
PCI_GNT0# 123
(18) PCI_GNT0# GNT#
58 MSEN MSEN R445 1 2 10K_0402_5%
MSEN XDEN UDIO3 R446 10K_0402_5%
XDEN 55 Layout Note: Place close to R5C832 Layout Note: Place close to R5C832 1 2
121 and Shield GND for SDCLK_MSCLK and Shield GND for SD_CLK UDIO4 R447 1 2 10K_0402_5%
(15) CLK_PCI_1394 PCICLK
119 94 R5C832XI 832@ UDIO5 R448 1 2 100K_0402_5%
(18,27,33,35) PCI_RST# PCIRST# XI 832@
CBS_GRST# 71 95 R5C832XO 1 2
R449 1 GBRST# XO R450 1 832@
2@ 10K_0402_5% 117 CLKRUN#
C483 XDEN 2 10K_0402_5%
70 96 0.01U_0402_16V7K 832@
R451 1 832@ PME# FIL0 832@
(20,27,33,35) PCI_CLKRUN# 2 0_0402_5% REXT 101 C484 832@
R5_PME# 100 1 2 R5C832XI
(33) R5_PME# VREF

10K_0603_1%
0.01U_0402_16V7K
(18) PCI_PIRQG# 115 INTA#

2
116 72 SIRQ 2 15P_0603_50V8J
(18) PCI_PIRQH# INTB# UDIO0/SERIRQ# SIRQ (20,27,33,35)

2
R452
60 TP_UDIO1 X1 832@ Solve MS Duo Adaptor short problem
UDIO1 PAD T29

C485
56 TP_UDIO2 832@
UDIO2 PAD T30
1 2 69 65 UDIO3 832@ 24.576MHz_16P_1BG24576CKIA
+3VS HWSPND# UDIO3 1
R453 10K_0402_5% 66 59 UDIO4 832@ C486
TEST UDIO4 UDIO5 R5C832XO R454 2 1 0_0402_5%

1
832@ UDIO5 57 1 2
(17,25,29,33,35,38,44,45) SUSP# 1 2
R455 @ 0_0402_5% 111 4 15P_0603_50V8J @ Q17
AGND GND SDDATA1_MSDATA1
107 13 1 3 2N7002_SOT23 SD_MSDATA1

S
AGND GND 832@ R456 2 SD_MSDATA1 (37)
103 AGND GND 22 832@ 1 0_0402_5%
102 AGND GND 28
99 54 Layout Note: Shield GND for @ Q18

G
B AGND GND SDDATA2_MSDATA2 B
CBS_CCLK_INTERNAL and CBS_CCLK 32N7002_SOT23 SD_MSDATA2

2
62 1

S
GND SD_MSDATA2 (37)
GND 63
97 NC GND 68
118

G
GND

2
GND 122
+5VS
R5C832_TQFP128~D
@ SA00000FU30 40mil 1
R458
2
@ 10K_0402_5%

+3VS U20 +VCC_SD

1
+VCC_SD D
3 1 SDCD#_XDCD0# 2
SDPWR0_MSPWR_XDPWR VIN VOUT
270P_0402_50V7K

4 5 G
VIN/CE VOUT
1

5.1K_0402_1%

1U_0603_10V4Z

0.1U_0402_16V4Z
10U_1206_6.3V6M
1 S

1
C487

150K_0402_5%
@ Q20

3
0.1U_0402_16V4Z

2 GND 1 1 1
R460

C488

R461
832@ 832@ 2N7002_SOT23

C489

C490
CLK_PCI_1394 1 RT9701CB_SOT25
2
2 2 2
C491

832@ 832@
2
1

4.7P_0402_50V8C10_0402_5%

2
R462

Z3008 832@ 832@

@ 832@
2

2
56.2_0402_1%

56.2_0402_1%

832@
2

R464

+3VS
R463

832@ 832@
2
100K_0402_5%
1
C492

1
R465

ME@ FOX_UV31413-4R1-TR
1 @ IEEE1394_TPBN0 1 1
A IEEE1394_TPBP0 2 5 A
832@ 2 5
IEEE1394_TPAN0 3 6
IEEE1394_TPAP0 3 6
2

4 4
CBS_GRST#
JP18
0.01U_0402_16V7K

0.33U_0603_16V4Z
2

2
56.2_0402_1%

56.2_0402_1%

1 832@
832@ 832@ Layout Note: Shield GND for
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
C494

C495

832@
R466

R467

C493 IEEE1394_TPA and TPB

1U_0603_10V6K Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title
2
832@
1 1 1394+3 in 1 Card
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
IEEE1394_TPBIAS0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT10/11 LA-3591P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 28 of 48
5 4 3 2 1
 A B C D E

+VDDA
HD Audio Codec

1
+AVDD_AC97 +3VS_DVDD
L22 R468
L21 1 2 0.1U_0402_16V4Z 680P_0402_50V7K 40mil 0.1U_0402_16V4Z 680P_0402_50V7K 1 2 10K_0402_5%
+VDDA +3VS
FBM-L11-160808-800LMT_0603 1 1 1 1 FBM-L11-160808-800LMT_0603
C497 C498 C499 C500 1 10U_0805_10V4Z
C496 20mil 1
C501
1
C502 C503 C504 C505
1
C506

2
1 2
10U_0805_10V4Z 2 2 2 2 C507 1U_0402_6.3V4Z

1
0.1U_0402_16V4Z 100P_0402_50V8J 2 2 2 2
R469
0.1U_0402_16V4Z 680P_0402_50V7K 100P_0402_50V8J 10K_0402_5%
1 Int MIC Conn. EC Beep 1

25

38
R470

9
U21 (33) BEEP# C508 1 2 1 2
1U_0402_6.3V4Z C509

2
560_0402_5%

DVDD
AVDD1

AVDD2

DVDD_IO
+MIC2_VREFO 1 2 1 2 MONO_IN
R471 4.7K_0402_5% 1 2 MIC2_L
MIC1 MIC@ C510 100P_0402_50V8J 1U_0402_6.3V4Z
PCI Beep

1
1 INT_MIC 1 2 14 35 AMP_LEFT C 1 2
1 NC LINE_OUT_L AMP_LEFT (30) R473
2 2 1 C513 1U_0402_6.3V4Z (20) SB_SPKR C515 1 2 1 2 2 Q39
2 C514 MIC2_R AMP_RIGHT 1U_0402_6.3V4Z B R472 2.4K_0402_1%
1 2 15 NC LINE_OUT_R 36 AMP_RIGHT (30) 560_0402_5%
3 220P_0402_50V7K C516 1U_0402_6.3V4Z E 2SC2411K_SC59
GND MIC@ AMP_LEFT_HP

3
GND 4 1 2 16 MIC2_L HP_OUT_L 39 AMP_LEFT_HP (30)
C517 100P_0402_50V8J
ACES_88231-02001 17 MIC2_R HP_OUT_R 41 AMP_RIGHT_HP
AMP_RIGHT_HP (30)
CardBus Beep R474
ME@ C518 1 2 1 2
(27) PCM_SPK#
1 2 100P_0402_50V8J LINE1_C_L 23 LINE1_L NC 45 1U_0402_6.3V4Z 560_0402_5%
3

1
C519 2 D18
SM05_SOT23

1 2 100P_0402_50V8J LINE1_C_R 24 LINE1_R DMIC_CLK 46

@ C520 C521 R475
1 2 18 43 0.01U_0402_16V7K 10K_0402_5% RB751V_SOD323
C1163 100P_0402_50V8J CD_L NC 1

2
1 2 20 CD_R NC 44
D48 C522 100P_0402_50V8J
1

1 2 19 CD_GND
C1164 100P_0402_50V8J 6 ICH_BITCLK_AUDIO 1 2
BIT_CLK HDA_BITCLK_AUDIO (19)
MIC1_L C524 1 2 2.2U_0603_6.3V4Z MIC1_C_L 21 R476 22_0402_5%
(30) MIC1_L MIC1_L
MIC1_R C525 1 2 2.2U_0603_6.3V4Z MIC1_C_R 22 8 1 2 HDA_BITCLK_AUDIO
(30) MIC1_R MIC1_R SDATA_IN HDA_SDIN0 (19)

2
R477 33_0402_5%
MONO_IN 12 37 R478
2006/12/07 PCBEEP MONO_OUT
2006/09/04 10_0402_5%
1 2 100P_0402_50V8J LINE1_VREFO 29 @
C527 11 1
2 (19) HDA_RST_AUDIO# RESET# 2

1
GPIO1 31
10 C528
(19) HDA_SYNC_AUDIO SYNC
5
MIC1_VREFO_L 28 10mil +MIC1_VREFO_L 2
10P_0402_50V8J
(19) HDA_SDOUT_AUDIO SDATA_OUT @
2
MIC1_VREFO_R 32 10mil +MIC1_VREFO_R
2006/09/04 3
GPIO0
GPIO3 MIC2_VREFO 30 10mil +MIC2_VREFO
SPK_SEL HIGH: HARMAN SENSE_A
SENSE_B
13
34
SENSE A
27 ACZ_VREF 10mil
LOW: SENSE B VREF
NO-BRAND T41 EAPD 47 40 ACZ_JDREF 20K_0402_1%
EAPD JDREF

1
48 33 10U_0805_10V4Z
2006/09/04 PAD SPDIFO NC 1
C529 1 1
4 26 R480 C530
DVSS1 AVSS1 100P_0402_50V8J C531
7 DVSS2 AVSS2 42
2
SENSE FOR Ext. ALC268-GR_LQFP48 2 2

2
Mic.
SA00001GD00 100P_0402_50V8J
R481
1 2 SENSE_A
(30) MIC_SENSE
20K_0402_1%

Sense Pin Impedance Codec Signals Regulator for CODEC

39.2K PORT-A (PIN 39, 41)
SENSE FOR Int. Mic. Adjustable Output
+5VS +5VS_VDDA +VDDA
3
20K PORT-B (PIN 21, 22) L23
U22 3
SENSE A +VDDA
1 2 4 VIN VOUT 5

4.7U_0805_10V4Z
R482 10K PORT-C (PIN 23, 24)

4.7U_0805_10V4Z
0.1U_0402_16V4Z
1 2 SENSE_B KC FBM-L11-201209-221LMAT_0805 2 6
DELAY SENSE or ADJ

1
20K_0402_1% R483

0.1U_0402_16V4Z
MIC@ 5.1K PORT-D (PIN 35, 36) 7 1 69.8K_0603_1%
ERROR CNOISE

R485
C532 C533
8 SD GND 3

1
39.2K PORT-E (PIN 14, 15) SI9182DH-AD_MSOP8

0_0402_5% 2

1
20K PORT-F (PIN 16, 17) SA091820030
R484
SENSE B

C534
24K _0402_1%
10K PORT-G (PIN 43, 44) 2006/12/07

C535
R676
SENSE FOR HP

2
(17,25,28,33,35,38,44,45) SUSP# 2 1
5.1K PORT-H (PIN 45, 46) @
R487 0_0402_5%
2 1 SENSE_A
(30) HP_SENSE
39.2K_0402_1%

1 2
R659 0_0603_5%
1 2
R660 0_0603_5%

4 4

2006/09/04
2006/10/20 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ALC861 VD Codec
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 29 of 48
A B C D E
 A B C D E

+MIC1_VREFO_L +MIC1_VREFO_R
APA2056 SPK/HP Amplifier
10mil 10mil

1
+5VALW
L42
+5VS_VDDA KC FBM-L11-201209-221LMAT_0805 MICROPHONE
1 2 2006/09/05 R492 R493
IN JACK
W=40mil 4.7K_0402_5% 4.7K_0402_5%
1 2 ME@

2
680P_0402_50V7K
SINGA_2SJ-S351-012

10U_0805_10V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
L34 KC FBM-L11-201209-221LMAT_0805 1 2 1
C536 C537 C538 C539 5
@ (29) MIC_SENSE
+3VALW 10
4 9
fo=1/(2*3.14*R*C)=106Hz 2 1 2
MIC1_R 1 2 L24 MIC1_R_1 3
1
R=1.5K / C= 1uF (29) MIC1_R
KC FBM-L11-160808-121LMT 0603 1
6
R494 1.5K_0402_1% MIC1_L L25 MIC1_L_1

11

19

20
10
(29) MIC1_L 1 2 2

1
1 2 U23 KC FBM-L11-160808-121LMT 0603 1

2
220P_0402_50V7K
220P_0402_50V7K
R495 1.5K_0402_1% 1 1

CVDD

HVDD

PVDD
PVDD

VDD
JP19

SM05_SOT23
1 2
C540 C541 @
(29) AMP_RIGHT 1 2 AMP_R 1 2 AMPR 1 R496 2
C542 1U_0402_6.3V4Z C543 1U_0402_6.3V4Z 0_0402_5% INR_A INTSPK_R1 2 2
3 INR_A ROUT+ 22
(29) AMP_LEFT 1 2 AMP_L 1 2 AMPL 1 R497 2 INL_A 5 21 INTSPK_R2
C544 1U_0402_6.3V4Z C545 1U_0402_6.3V4Z 0_0402_5% INL_A ROUT- D19

1
R498 1 2 100K_0402_5% AMP_EN# 27 8 INTSPK_L1
/AMP EN LOUT+ INTSPK_L2
LOUT- 9
+5VS R499 1 2 100K_0402_5% HP_EN 24 HP EN HP_R
HP_R 17
(29) AMP_RIGHT_HP 1 2 AMP_RHPIN 1 R500 2 INR_H 4 INR_H HP_L 18 HP_L
C546 2.2U_0603_10V6K 39K_0402_5%INL_H 6 INL_H
(29) AMP_LEFT_HP 1 2 AMP_LHPIN 1 R501 2
C547 2.2U_0603_10V6K 39K_0402_5% 26
EC_EAPD# /SD CVSS
CVSS 15
1 2 2 1 AMP_BEEP 28 BEEP
C548 0.47U_0402_6.3V6K R502 47K_0402_5% 16
AMP_CP+ VSS
12 CP+
1 2 AMP_CP- 14 2 1 HEADPHONE
C549 1U_0603_10V6K CP- GND
PGND 23 ME@OUT JACK
1 2 AMP_BIAS 25 7 C551
C550 2.2U_0603_10V6K BIAS PGND SINGA_2SJ-S351-013
CGND 13 1U_0603_10V6K
2
2 1 (29) HP_SENSE 5
C552 0.1U_0402_16V4Z 10
APA2056_TSSOP28 4 9
+5VALW 0_0402_5%
HP_R R6571 HP_R_R L26 1 HPR
IN_A Gain = 10dB (Internal Speaker) 2 2
KC FBM-L11-160808-121LMT 0603
3
6
1

2
IN_H Gain = 0dB (Headphone) HP_L R6581 2 HP_L_R L27 1 2
KC FBM-L11-160808-121LMT 0603
HPL 2 2
1

10P_0402_50V8J

10P_0402_50V8J
4.7K_0402_5% 0_0402_5% 1 1

2
R681 JP20
D51 D20
EC_EAPD EC_EAPD# C553 C554 @
2

(33) EC_EAPD 1 2
2 2
2

SM05_SOT23
CH751H-40_SC76 R682

1
12K_0402_5%
for APA 2057
1

GAIN setting
SM05_SOT23 D22
3
1
2
APA2057 gain setting table @
JP21
gain
V V(low) V(high) INTSPK_L1 L30 1 2 HLMA-160808-39NKT SPK_L1 1
INTSPK_L2 L31 HLMA-160808-39NKT SPK_L2 1
1 2 2 2
INTSPK_R1 L28 1 2 HLMA-160808-39NKT SPK_R1 3
INTSPK_R2 L29 HLMA-160808-39NKT SPK_R2 3
8 3.21 3.27 1 2 4 4
5 G1
SM05_SOT23 D21 6 G1
9 3.33 3.39 2
1 ACES_88231-04001
3 @
10 3.45 3.51 current @
3 3
(dB) setting(3.48V)

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 30 of 48
A B C D E
 USB Port
USB Port 1 +USB_VCCB
USB Port 2 +USB_VCCC

1000P_0402_50V7K 1000P_0402_50V7K
+5VALW
1
1 1 1 1 1
C555 + C557 C558 C561 C562
150U_D_6.3VM C556 +
+USB_VCCA 150U_D_6.3VM
U24 2 2 2 2 2
2
1 GND OUT 8
C565 0.1U_0402_16V4Z 2 7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
IN OUT JP23 JP24
2 1 3 IN OUT 6
4 EN# FLG 5 USB_OC#0 (20) 1 VCC 1 VCC
(20) USB20_N2 2 D- (20) USB20_N6 2 D-
G545C1P1U_SO8 3 3
(20) USB20_P2 D+ (20) USB20_P6 D+
4 GND 4 GND

2
1

2
C566 5 D24 5
USB_ON# @ 1000P_0402_50V7K D23 GND1 @ PSOT24C_SOT23 GND1
(33) USB_ON# 6 GND2 6 GND2
@ PSOT24C_SOT23 7 7
2 GND3 GND3
8 GND4 8 GND4
SUYIN_020173MR004G565ZR For EMI SUYIN_020173MR004G565ZR

1
For EMI

1
ME@ ME@

+5VALW
+USB_VCCB
U25

C568 0.1U_0402_16V4Z
1
2
GND OUT 8
7
USB Port 3
IN OUT
2 1 3 IN OUT 6
4 EN# FLG 5 USB_OC#2 (20)
G545A1P1U_SO8 1
C573
USB_ON1# @ 1000P_0402_50V7K
(33) USB_ON1#
2

2006/10/18

USB board
+USB_VCCA

1000P_0402_50V7K
1
+5VALW
1 1
+USB_VCCC C567 + C569 C570
U26 150U_D_6.3VM
1 GND OUT 8
C574 0.1U_0402_16V4Z 2 2 2
2 IN OUT 7
2 1 3 IN OUT 6
4 5 0.1U_0402_16V4Z
EN# FLG USB_OC#6 (20)
G545A1P1U_SO8
JP36
6 6 G2 8
USB_ON2# 1 5 7
(33) USB_ON2# 5 G1
C575 4
(20) USB20_N0 4
@ 1000P_0402_50V7K 3
(20) USB20_P0 3
2
2006/10/18 2
1
2
1
ACES_87212-06G0
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Bluetooth & USB CONN.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 31 of 48
 5 4 3 2 1

Power BTN
TOP Side
D INT_KBD CONN J3
2 1
@ JOPEN +EC_DVCC 2006/12/07
D

2 1
J4 @ JOPEN

1
KSI[0..7] KSI1 @ C576 1
Bottom Side
KSI[0..7] (33) 2 100P_0402_50V8J R507
100K_0402_5%
KSI7 @ C577 1 2 100P_0402_50V8J
KSO[0..15]
KSO[0..15] (33)
KSI6 @ C578 1 2 100P_0402_50V8J D26

2
2 ON/OFF# ON/OFF# (33)
KSO9 @ C579 1 2 100P_0402_50V8J ON/OFFBTN# 1
(36) ON/OFFBTN#
3 51_ON# 51_ON# (33,39)
KSI4 @ C580 1 2 100P_0402_50V8J
DAN202U_SC70
KSI5 @ C581 1 2 100P_0402_50V8J

1
KSO0 @ C582 1 2 100P_0402_50V8J 1
(Right) D27
JP26 KSI2 @ C583 1 2 100P_0402_50V8J RLZ20A_LL34
KSI1
KSI7 1 KSI3 @ C585 1 2 C584
2 2 100P_0402_50V8J
KSI6 1000P_0402_50V7K

2
KSO9 3 KSO5 @ C586 1
4 2 100P_0402_50V8J
KSI4
KSI5 5 KSO1 @ C587 1
6 2 100P_0402_50V8J
KSO0
KSI2 7 KSI0 @ C588 1
8 2 100P_0402_50V8J
KSI3
KSO5 9 KSO2 @ C589 1
10 2 100P_0402_50V8J
KSO1
11

1
KSI0 KSO4 @ C590 1 D
12 2 100P_0402_50V8J
C KSO2 EC_ON Q40 C
13 (33,41) EC_ON 2
KSO4 KSO7 @ C591 1 2 100P_0402_50V8J G
14

2
KSO7 S 2N7002_SOT23
KSO8 15 KSO8 @ C592 1 2 100P_0402_50V8J R613

3
KSO6 16
KSO3 17 KSO6 @ C593 1
18 2 100P_0402_50V8J 10K_0402_5%
KSO12
KSO13 19 KSO3 @ C594 1 2 100P_0402_50V8J

1
KSO14 20
KSO11 21 KSO12 @ C595 1
22 2 100P_0402_50V8J
KSO10
KSO15 23 KSO13 @ C596 1
24 2 100P_0402_50V8J

KSO14 @ C597 1 2 100P_0402_50V8J

(Left) ACES_85201-24051
ME@ KSO11 @ C598 1 2 100P_0402_50V8J

KSO10 @ C599 1 2 100P_0402_50V8J

KSO15 @ C600 1 2 100P_0402_50V8J

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD,ON/OFF,T/P,LED/B,DEBUG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 32 of 48
5 4 3 2 1
 5 4 3 2 1

+3VALW L41 Analog Board ID definition,

1 2 FBM-11-160808-601-T_0603 Please see page 3.
+EC_DVCC

L32 +EC_AVCC
+3VALW 1 2 +EC_AVCC
FBM-11-160808-601-T_0603 2 1
C602 1 1 1 1 1 1
C601

0.1U_0402_16V4Z
C603

0.1U_0402_16V4Z
C604

0.1U_0402_16V4Z
C605

0.1U_0402_16V4Z
C606

1000P_0402_50V7K
C607

1000P_0402_50V7K
C608
0.1U_0402_16V4Z
1000P_0402_50V7K
1 ECAGND 2
1 2 ECAGND (34) 2
L33 FBM-11-160808-601-T_0603 2 2 2 2 2

D D

111
125
22
33
96

67
U27

9VCC
VCC
VCC
VCC
VCC
VCC

AVCC
RB751V_SOD323 1 21 INVT_PWM
(19) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM
2 1 KB_RST#R 2 23 BEEP#
(19) KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# (29)
D28 3 26 CHGSEL
(20,27,28,35) SIRQ SERIRQ# FANPWM1/GPIO12 CHGSEL (41)
@ 4 27 ACOFF
(19,35) LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (39,41)
C610 22P_0402_50V8J LPC_AD3 5
(19,35) LPC_AD3 LAD3
LPC_AD2 7 PWM Output 2 1 ECAGND
(19,35) LPC_AD2 LAD2
2 1 2 1 LPC_AD1 8 63 BATT_TEMP C609 0.01U_0402_16V7K
(19,35) LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (40)
R510@ 10_0402_5% LPC_AD0 BATT_OVP
(19,35) LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP (41)
ADP_I/AD2/GPIO3A 65 APS_X (34)
(15) CLK_PCI_LPC 12 PCICLK AD Input AD3/GPIO3B 66 APS_Y (34)
+3VALW 13 75
(18,27,28,35) PCI_RST# PCIRST#/GPIO05 AD4/GPIO42 ADP_I (41)
1 2 EC_RST# 37 76
+3VALW ECRST# SELIO2#/AD5/GPIO43
R511 47K_0402_5% EC_SCI# 20
(20) EC_SCI# SCI#/GPIO0E
(20,27,28,35) PCI_CLKRUN# 1 2 38 CLKRUN#/GPIO1D
2 R513 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG
2

C611 0_0402_5% @ 70 EN_FAN1

EN_DFAN1/DA1/GPIO3D EN_FAN1 (4)
R515 0.1U_0402_16V4Z DA Output 71 IREF
IREF/DA2/GPIO3E IREF (41)
10K_0402_5% KSI0 55 72
1 KSI1 KSI0/GPIO30 DA3/GPIO3F
56 KSI1/GPIO31
KSI2 57
KSI3 KSI2/GPIO32
1

58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_EAPD (30)

1 2 EC_PME# KSI4 59 84
(28) R5_PME# KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# (31)
R516 @ 0_0402_5% KSI5 60 85
C KSI5/GPIO35 PSCLK2/GPIO4C USB_ON1# (31) C
1 2 KSI6 61 PS2 Interface 86
(18) PCI_PME# KSI6/GPIO36 PSDAT2/GPIO4D USB_ON2# (31)
R518 0_0402_5% KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK (36)
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA (36)
1 @ 2 KSO1 40
(35) SIO_PME# R608 0_0402_5% KSO2 KSO1/GPIO21
41 2 1
KSO3 42
KSO2/GPIO22
97 R66510K_0402_5% 2006/12/07
2006/09/11 KSO4 43
KSO3/GPIO23
KSO4/GPIO24
SDICS#/GPXOA00
SDICLK/GPXOA01 98 EN_WOL
EN_WOL (23)
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 ITES_ST (34)
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109
+3VS KSO[0..15] KSO7 46 SPI Device Interface
(32) KSO[0..15] KSO8 KSO7/GPIO27
47 KSO8/GPIO28
1 2 AMP_MUTE_BTN# KSI[0..7] KSO9 48 KSO9/GPIO29 SPIDI/RD# 119 FRD#SPI_SO
FRD#SPI_SO (34)
R519 10K_0402_5% (32) KSI[0..7] KSO10 49 120 FWR#SPI_SI
+EC_DVCC KSO10/GPIO2A SPIDO/WR# FWR#SPI_SI (34)
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK (34)
KSO12 51 128 FSEL#SPICS#
KSO12/GPIO2C SPICS# FSEL#SPICS# (34)
1 2 USER_BTN# KSO13 52 KSO13/GPIO2D
R521 10K_0402_5% KSO14 53
1 2 EC_NOVO_BTN# KSO15 54
KSO14/GPIO2E
KSO15/GPIO2F CIR_RX/GPIO40 73
BT_OFF# (26) 2006/12/21
R522 10K_0402_5% KSO16 81 74
KSO17 82
KSO16/GPIO48 CIR_RLC_TX/GPIO41
89
ALI/MH# (40,41) 2006/12/07 +5VS
2006/10/31 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52 90
FSTCHG (41)
CHARGE_LED0# (37)
91 TP_CLK 1 2
CAPS_LED#/GPIO53 CAPS_LED# (37) 4.7K_0402_5%
EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 R524
(34,40) EC_SMB_CK1 SCL1/GPIO44 CHARGE_LED1# (37)
D50 EC_SMB_DA1 78 93 TP_DATA 1 2
2
(34,40)
(4)
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_CK2 79
SDA1/GPIO45
SCL2/GPIO46 SM Bus
SUSP_LED#/GPIO55
SYSON/GPIO56 95
EC_BT_LED# (26)
SYSON (25,38,44)
2006/12/26 R526 4.7K_0402_5%
1 EC_SMB_DA2 80 121
(36) NOVO_BTN# (4,17) EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON (46)
3 51_ON# (32,39) AC_IN/GPIO59 127 ACIN (20,39)
DAN202U_SC70
(20) SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# (20)
PM_SLP_S5# 14 101
B 2006/12/28 (20) PM_SLP_S5#
(20) EC_SMI#
EC_SMI# 15
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
EC_LID_OUT#/GPXO04
EC_ON/GPXO05 102 EC_ON
EC_LID_OUT# (20)
EC_ON (32,41)
R533 B
LID_SWITCH# 16 103 2 1 0_0402_5%
+5VALW (36) LID_SWITCH# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# (20)
SUSP# 17 104 ICH_POK
(17,25,28,29,35,38,44,45) SUSP# SUSP#/GPIO0B ICH_PWROK/GPXO06 ICH_POK (7,20)
PBTN_OUT# 18 GPO 105
(20) PBTN_OUT# PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# (22)
1 2 EC_SMB_CK1 EC_PME# 19 GPIO 106
R530 4.7K_0402_5% EC_PME#/GPIO0D WL_OFF#/GPXO09 RF_OFF# (26)
(4,20) EC_THERM# 25 EC_THERM#/GPIO11 GPXO10 107
1 2 EC_SMB_DA1 28 108 ITES_EN# (34)
(4) FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 SCROLL_LED# (37)
R531 4.7K_0402_5% 29
EC_TX_P80_DATA FANFB2/GPIO15 XCLKO 1 R532
(13,14) EC_TX_P80_DATA 30 EC_TX/GPIO16 2 XCLKI
+3VS EC_RX_P80_CLK 31 110 @ 20M_0603_5%
(13,14) EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 SLP_S4# (20)
(32) ON/OFF# 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL (22)
1 2 EC_SMB_CK2 34 114
R534 4.7K_0402_5%
(36,37) PWR_SUSP_LED#
(37) NUM_LED# 36
PWR_LED#/GPIO19
NUMLED#/GPIO1A GPI
GPXID3
GPXID4 115 KILL_SW# (36)
2006/12/22
1 2 EC_SMB_DA2 116
GPXID5 AMP_MUTE_BTN# (36)
R535 4.7K_0402_5% 117
GPXID6 USER_BTN# (36)
118 EC_NOVO_BTN#
XCLKI GPXID7
122 XCLK1
XCLKO 123 124
XCLK0 V18R C614 C615

4
AGND
GND
GND
GND
GND
GND

15P_0402_50V8J

15P_0402_50V8J
OUT
IN
KB926_LQFP128
113
11
24
35
94

69

SA00001J510

NC

NC
ECAGND

3
EC DEBUG PORT
A X2 32.768KHZ_12.5P_1TJS125BJ2A251 A
JP27
+3VALW 1 1
EC_TX_P80_DATA 2
EC_RX_P80_CLK 2
3 3
4 4
ACES_85205-0400 Security Classification Compal Secret Data Compal Electronics, Inc.
ME@
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB925
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT10/11 LA-3591P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 33 of 48
5 4 3 2 1
 SPI Flash (8Mb*1) +5VALW

+5VALW

1
+EC_DVCC C618
1 2 0.1U_0402_16V4Z R542
100K_0402_1%
1 20mils
C620 U32 U30

2
8 VCC VSS 4 8 VCC A0 1
0.1U_0402_16V4Z 7 2
2 WP A1
3 W (33,40) EC_SMB_CK1 6 SCL A2 3
(33,40) EC_SMB_DA1 5 SDA GND 4
7 HOLD AT24C16AN-10SU-2.7_SO8
FSEL#SPICS# 2 1 SPI_CS# 1
(33) FSEL#SPICS# S
R547 0_0402_5%

1
SPI_CLK 2 1 SPI_CLK_R 6 SA024160140
(33) SPI_CLK
R548 33_0402_5% C 2006/12/28 R545
FWR#SPI_SI 2 1 SPI_SI 5 2 SPI_SO 2 1 100K_0402_1%
(33) FWR#SPI_SI D Q FRD#SPI_SO (33)
R549 0_0402_5% R550 0_0402_5%
SST25LF080A_SO8-200mil
EMI

2
SPI_CLK_R +EC_DVCC
JP29
1

SPI_CS# 1 2
R618 SPI_SO 1 2
3 3 4 4
@ 10_0402_5% 5 6 SPI_CLK_R
+EC_DVCC 5 6 SPI_SI
7 7 8 8

E&T_2941-G08N-00E~D
2

1
ME@
C1161
@18P_0402_50V8J
2

+EC_AVCC

47K

10K 2 ITES_EN# (33)

DTA114YKA_SC59
Q41 APS@
2 +3VS_ITES_R 1

R651
47_0402_5%
+3VS_ITES APS@
1

0.1U_0402_16V4Z
1 1 APS@ 1
C1178

2 2 2 ECAGND
C1179
+3VALW C1177 ECAGND (33)
0.1U_0402_16V4Z 0.1U_0402_16V4Z
APS@ APS@
2

R652
10K_0402_5%
APS@
U40
D47 RB751V_SOD323 R653 10K_0402_1%
1

APS@
1 2 ST 2 12 X 1 APS@
2
(33) ITES_ST ST Xout APS_X (33)
10 Y 1 2
Yout R654 10K_0402_1% APS_Y (33)
1

14 APS@
R655 15
Vs
Vs
C1180
1 1
C1181 2006/10/14
100K_0402_5% 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ NC
NC 4 APS@
2 2
APS@ DEL ISA
8 ECAGND
ECAGND NC BIOS
2

3 COM NC 9
5 COM NC 11
6 COM NC 13
7 COM NC 16

ADXL322JCP-REEL_LFCSP16P_4*4
APS@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & APS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 34 of 48
 A B C D E F G H I J

SUPER I/O SMsC LPC47N217

1 1

+3VS

2
R552
10K_0402_5% @
+3VS
Base I/O Address
RP15

1
* 0 = 02Eh CTS#1 1 8
SIO_SYSOPT 1 = 04Eh RI#1 2 7
2 DCD#1 3 6 2

2
DSR#1 4 5
R554
SERP@ 1K_0402_5% 4.7K_8P4R_1206_5%

SERP@

1
2006/09/11

3 3
(19,33) LPC_AD[0..3] LPC_AD[0..3]
VTR_PW

U33
LPC_AD0
LPC_AD1
10
12
LAD0
SERIAL I/F
RXD1 62
63
RXD1
TXD1
VTR_PW 40mil
LAD1 TXD1 2
LPC_AD2 13 64 DSR#1 SERP@
LPC_AD3 LAD2 DSR1# RTS#1 C624
14 LAD3 RTS1# 1
2 CTS#1 0.1U_0402_16V4Z
LPC_FRAME# CTS1# DTR#1 1
(19,33) LPC_FRAME# 15 LFRAME# DTR1# 3
LPC_DRQ#0 RI#1

26
(19) LPC_DRQ#0 16 LDRQ# RI1# 4
LPC I/F

1 2 5 DCD#1 U34
4 (18,27,28,33) PCI_RST# R664 0_0402_5% 17
DCD1#
28
4
2

VCC
SERP@ 10K_0402_5% PCI_RESET# 0.1U_0603_25V7K C1+
18 LPCPD# IRRX2 37 V+ 27 2 1
+3VS 1 R558 2 SIO_PD# FIR 38 SERP@ C625 0.1U_0402_16V4Z
PCI_CLKRUN# IRTX2 C626
19 39 24
(20,27,28,33) PCI_CLKRUN#
CLK_PCI_SIO 20
CLKRUN#
PCI_CLK
IRMODE/IRRX3
2
1
1
C1-
C2+ V- 3 2
SERP@
1 SERIAL PORT
SIRQ 21 41 0.1U_0603_25V7K C627 0.1U_0402_16V4Z
2006/09/11 (20,27,28,33) SIRQ
6
SER_IRQ
IO_PME#
INIT#
SLCTIN# 42 SERP@ SERP@ JP30
SIO_PME# 44 C628 2
PD0 DTR#1 1 C2- DTR# DCD# R560 0_0402_5% DCD#_R
9 CLK14 PD1 46 14 TIN1 TOUT1 9 1 2 5
VTR_PW VTR_PW R5591 SERP@ 2 CLOCK 47 RTS#1 13 10 RTS# DSR# R561 1 2 0_0402_5% DSR#_R 9
10K_0402_5% PD2 TXD1 TIN2 TOUT2 TXD RXD R562 0_0402_5% RXD_R
23 GPIO40 PD3 48 12 TIN3 TOUT3 11 1 SERP@ 2 4
PARALLEL I/F

24 49 CTS#1 19 4 CTS# RTS# R563 1 SERP@ 2 0_0402_5% RTS#_R 8

(33) SIO_PME# GPIO41 PD4 ROUT1 RIN1
25 50 RI#1 18 5 RI# TXD R564 1 SERP@ 2 0_0402_5% TXD_R 3
CLK_14M_SIO GPIO42 PD5 RXD1 ROUT2 RIN2 RXD CTS# R565 0_0402_5% CTS#_R
27 GPIO43 PD6 51 17 ROUT3 RIN3 6 1 SERP@ 2 7
(15) CLK_14M_SIO +3VS DCD#1 DCD# DTR# R566 0_0402_5% DTR#_R
GPIO

28 GPIO44 PD7 53 16 ROUT4 RIN4 7 1 SERP@ 2 2 12

29 55 DSR#1 15 8 DSR# RI# R567 1 SERP@ 2 0_0402_5% RI#_R 6 13
5 GPIO45 SLCT R607 ROUT5 RIN5 5
30 GPIO46 PE 56 20 ROUTB2 SERP@ 1
2

31 57 VTR_PW 21 SERP@
+3VS GPIO47 BUSY INVLD#
SERP@

32 GPIO10 ACK# 58 (17,25,28,29,33,38,43,44,45) SUSP# 23 FORCEON

SIO_SYSOPT 33 59 25 FOX_DZ10191-H2-HT
GPIO11/SYSOPT ERROR# GND ME@
1 2 34 60 22
R555 SERP@10K_0402_5% 35
GPIO12/IO_SMI#
GPIO13/IRQIN1
ALF#
STROBE# 61 2006/09/11 FORCEOFF#
0_0805_5% C651 SERP@ MAX3243CAI_SSOP28
1

1 2 36 GPIO14/IRQIN2
R556 40 1 2
SERP@ 10K_0402_5% GPIO23
8 7 VTR_PW 0.1U_0402_16V4Z SERP@
VSS VTR
22 VSS VCC 11 +3VS
43 VSS POWER VCC 26
52 VSS VCC 45
VCC 54

6 LPC47N217_STQFP64 1 1 1 1
LPC DEBUG PORT 6
C621 C622 C623 C648 +3VS need to add R138(No
SERP@ SIO sku , and Debug
2 2 2 2
port is used )

CLK_PCI_SIO 1 2 CLK_PCI_DB 0.1U_0402_16V4Z 0.1U_0402_16V4Z JP38

(15) CLK_PCI_SIO R661 0_0402_5% 0.1U_0402_16V4Z 4.7U_0805_10V4Z 1
1 CLK_PCI_DB
2 2
SERP@ SERP@ 3
SERP@ SERP@ 3 LPC_AD0
4 4
5 LPC_AD1
5 LPC_AD2
6 6
7 LPC_AD3
Close to u33 pin 7
8 8 LPC_FRAME#
7 9 9 7
10 PCI_RST#
10
GND 11
GND 12
CLK_PCI_SIO CLK_14M_SIO
ACES_85201-1005N
1

@
R604 R605
@ 10_0402_5% @ 10_0402_5%
2

1 1
C649 C650
@18P_0402_50V8J @10P_0402_25V8K
2 2
8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RS232_Serial Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT10/11 LA-3591P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 35 of 48
A B C D E F G H I J
 5 4 3 2 1

Finger Print 2006/12/22

C1182 47P_0402_50V8J
USB20_P8_FP 1
USB20_N8_FP 1
2
2
T/P Board
For EMI

1
C1183 47P_0402_50V8J
D D29 D
PSOT24C_SOT23
JP31
@
2006/12/07 1 1 TP_CLK (33)
27.4_0402_1% JP32 2 TP_DATA (33)
USB20_P8 R6691 USB20_P8_FP 2
2

3
(20) USB20_P8 2 1 1 3 3
USB20_N8 1 2 USB20_N8_FP 2 4
(20) USB20_N8 2 4
R670 27.4_0402_1% 3 5
3 5

2
4 4 6 6
+3VS 5 7 +5VS D42
5 GND
6 6 GND 8 PSOT24C_SOT23
2 1 7 GND @
8 ACES_85201-06051
C629 C630 GND
ME@
@ 0.1U_0402_10V6K ACES_85201-06051

1
4.7U_0603_6.3V6M 1 2
@

Kill Switch

C C

SW Board
+3VS
KILLSW@ SW3
1 2 3 3 G2 5
R568 10K_0402_5% 4
G1
(33) KILL_SW# 2 2
KILL_SW#
1 +5VALW
1
JP35
1BS003-1211L_3P 1 2 USER_BTN#
KILLSW@ 1 2 AMP_MUTE_BTN# USER_BTN# (33)
3 3 4 4
5 6 NOVO_BTN# AMP_MUTE_BTN# (33)
(33,37) PWR_SUSP_LED# 5 6 NOVO_BTN# (33)
7 8 ON/OFFBTN#
7 8 ON/OFFBTN# (32)
9 9 10 10
11 11 12 12
13 13 14 14
15 15 16 16

ACES_88018-1610
ME@

LID Switch
B B

+3VALW
1

R629
Lid Switch 100K_0402_5%

Change P/N : SN111000207

2

SW6
3 1 LID_SWITCH# (33)
2

4 2
D44
MPU-101-81_4P @
PSOT24C_SOT23
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP/SW/TP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 36 of 48
5 4 3 2 1
 5 4 3 2 1

3 in 1 Card Reader
+VCC_SD
JP33
6 VDD_SD
SDDATA0_MSDATA0 9
(28) SDDATA0_MSDATA0 SD_MSDATA1 DAT0_SD
10 DAT1_SD
(28) SD_MSDATA1 SD_MSDATA2 2
(28) SD_MSDATA2 SDDATA3_MSDATA3 DAT2_SD
3 CD/DAT3_SD
(28) SDDATA3_MSDATA3 SDCLK_MSCLK 1 R572 2 SDCLK 7
D SDCLK_MSCLK SDWP#_XDRB# 22_0402_5% CLK_SD D
11 WP_SD
(28) SDWP#_XDRB# SDCMD_MSBS 4
(28) SDCMD_MSBS SDCD#_XDCD0# CMD_SD
1 CD_SD
(28) SDCD#_XDCD0# 5 VSS_SD
8 VSS_SD
R6280_0402_5%
(28) SDDATA1_MSDATA1 SDDATA1_MSDATA11 2 19 VCC_MS
+VCC_SD 13 VCC_MS
SDCLK_MSCLK 1 2 MSCLK 14
MSCD#_XDCD1 R573 22_0402_5% SCLK_MS
16 INS_MS
(28) MSCD#_XDCD1 SDDATA0_MSDATA0 18
(28) SDDATA0_MSDATA0 SDCMD_MSBS SDIO_MS
20 BS_MS
SDCLK_MSCLK (28) SDCMD_MSBS SDDATA3_MSDATA3 15 CF1 CF2 CF3 CF4 CF5 CF6 CF7 CF8
(28) SDDATA3_MSDATA3 SDDATA2_MSDATA2 RESERVED_MS
17 RESERVED_MS

1
(28) SDDATA2_MSDATA2 21
R619 VSS_MS @ @ @ @ @ @ @ @
12 VSS_MS
@ 10_0402_5%

1
22 GND
23 CF9 CF10 CF11 CF12 CF13 CF14 CF15 CF16
GND
PROCO_MDR019-C0-1202

2
1
@ @ @ @ @ @ @ @ @
C1162

1
@10P_0402_25V8K
2 CF17 CF18

@ @

1
C C

H1 H2 H3 H4 H5
HOLEA HOLEA HOLEA HOLEA HOLEA

1
Front LEDs SWAP BY EC +5VS

H6 H7 H8 H9 H10
D32
+5VS HOLEA HOLEA HOLEA HOLEA HOLEA
(33) NUM_LED# 1 2 1 2

D33 R575 300_0402_5%

HT-191NB_BLUE_0603

1
(26) WIRELESS_LED# 1 2 1 2
D35
R576 300_0402_5%
D34
HT-191NB_BLUE_0603
(33) CAPS_LED# 1 2 1 2
(26) BTONLED 1 2 1 2
R578 300_0402_5% H11 H12 H13 H14 H15
R577 300_0402_5% HT-191NB_BLUE_0603 HOLEA HOLEA HOLEA HOLEA HOLEA
HT-191UD_AMBER_0603
D36
+5VALW 1 2 1 2
B (33) SCROLL_LED# B

1
R579 300_0402_5%
HT-191NB_BLUE_0603
D41 HT-191NB_BLUE_0603
H16 H17 H24 H25 H22
1 2 CHARGE0 1 2 HOLEA HOLEA HOLEA HOLEA HOLEA
(33) CHARGE_LED0#
+5VS
R581 300_0402_5%

CHARGE1

1
(33) CHARGE_LED1# 1 2 1 2

2
+5VS
R582 300_0402_5% D45 R583
HT-191UD_AMBER_0603 H23 H26 H27 H28 H29
300_0402_5%
HOLEA HOLEA HOLEA HOLEA HOLEA
5

+5VALW U36 1
D39
ODD_LED# 1
P

(25) ODD_LED# B DRIVE_LED#

1
Y 4 1 2
D46 HT-191NB_BLUE_0603 SATA_LED# 2
(19) SATA_LED# A
G

TC7SH08FUF_SSOP5 HT-191NB_BLUE_0603 H30 H31

(33,36) PWR_SUSP_LED# 1 2 1 2
HOLEA HOLEA H32 H33 H34
3

R650 300_0402_5% HOLEA HOLEA HOLEA

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INDICATE LED
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom IGT10/11 LA-3591P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 37 of 48
5 4 3 2 1
 A B C D E F G H I J

+5VALW

+5VALW

1
R584
+5VALW to +5VS Transfer

1
1 R586 47K_0402_5% 1
+5VALW +5VS 10K_0402_5% SYSON#

2
1
U37 0.1U_0402_16V4Z SUSP

2
(45) SUSP
8 D S 1

1
C633 D Q27
1 7 D S 2
+VSB 10U_0805_10V4Z 6 3 2 Q29
D S 1 1 (17,25,28,29,33,35,44,45) SUSP#
5 4 G 2
D G 2N7002_SOT23 (25,33,44) SYSON

2
C634 C635 S

1
2 SI4800DY_SO8 10U_0805_10V4Z R678

3
R585 2 2
22K_0402_5% 10K_0402_5% DTC124EK_SC59

3
1
RUNON
2 2 2
1
1
D C636
SUSP 2 Q28 0.1U_0603_25V7K
G
2N7002_SOT23 2
S
+1.5VS
3

+1.5VSP
Q42
SI7326DN-T1-E3_PAK1212-8
1
2
5 3

3 3
LAN_LDO@

4
+3VS_GATE

+3VALW to +3VS Transfer

+3VALW
+3VS +5VALWP
U38 0.1U_0402_16V4Z +1.5VSP_LAN
8 D S 1
1 7 D S 2
+VSB C637 6 3
D S 1 1

1
10U_0805_10V4Z 5 4 C638 C639 C1184
4 D G 4
1

2 SI4800DY_SO8 10U_0805_10V4Z 1U_0603_6.3V6M

R587 2 2

2
LAN_LDO@
33K_0402_5% 1

6
U41 C1185
5

VCNTL
VIN

2
+3VS_GATE R591 1 RUNON 10U_0805_10V4Z
2

2 7 POK
@ 0_0402_5% R673 2
VOUT 4 LAN_LDO@
1 12K_0402_1%
1

D C640
LAN_LDO@ VOUT 3 +1.2V_LAN
SUSP 2 Q30 0.1U_0603_25V7K 1
C1186

1
G 8 2
2N7002_SOT23 EN FB

1
S 2

GND
R674 C1187 10U_0805_10V4Z
3

VIN 9
2
LAN_LDO@
LAN_LDO@ 1K_0402_1%

2
5 LAN_LDO@ LAN_LDO@ 5

1
APL5912-KAC-TRL_SO8

2
1
0.01U_0402_25V7K

R675
2K_0402_1%
LAN_LDO@
+1.8V to +1.8VS Transfer OCP==>8A

2
+1.8V
+1.8VS VGA@
Vripple==
U39 0.1U_0402_16V4Z
8 D S 1
6 1 7 D S 2 6
+VSB C641 6 3
D S 1 1
VGA@ 5 4 C642 C643
10U_0805_10V4Z D G VGA@
2

2 SI4800DY_SO8 10U_0805_10V4Z
R595 VGA@ 2 2
47K_0402_5%
VGA@
R596 1 RUNON
1

2
@ 0_0402_5%
1
1

D C644
SUSP 2 Q37 0.1U_0603_25V7K +0.9VS +2.5VS +3VS
G VGA@ +5VS +1.8V +1.8VS +1.25VS
2N7002_SOT23 2
S
VGA@

1
3

7 7
1

1
R590 R594 R593
R588 R592 R589 R597
470_0402_5% 470_0402_5% 470_0402_5%
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% VGA@
VGA@

12

12

12
D D D
12

12

12

12
D D D D SUSP
2 2 SUSP 2 SUSP
2 SUSP 2 SYSON# 2 SUSP 2 SUSP G G G
G G G G S Q33 S Q36 S Q35
Q31 Q34 Q32 Q38 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

3
S S S S
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 VGA@
3

VGA@ 3

8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2006/08/04 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuit
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom IGT10/11 LA-3591P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 38 of 48
A B C D E F G H I J
 A B C D

ACIN BATT ONLY

DC231000400
PJP1 PL1 VIN Precharge detector Precharge detector
ADPIN HCB4532KF-800T90_1812 Min. typ. Max. Min. typ. Max.

10_1206_5%
1 1 1 2
6 G H-->L 14.589V 14.84V 15.243V H-->L 6.138V 6.214V 6.359V

1
5 G

PR1
4 G 2 2
L-->H 15.562V 15.97V 16.388V L-->H 7.196V 7.349V 7.505V

100P_0402_50V8J
1000P_0402_50V7K
3 G

1000P_0402_50V7K
100P_0402_50V8J
@

1
PC1

PC2

PC3

PC4
SINGA_2DC-G213-B20

12

RLZ24B_LL34
1 PR2 1

PD1
1K_1206_5%

2
1 2

PD2 PR3

2
@ RLS4148_LLDS2 1K_1206_5% PQ1
VIN 2 1 1 2 3 TP0610K-T1-E3_SOT23-3
1

PR4
PR5 PC5 1K_1206_5%
@ 10K_0402_1% @ 0.01U_0402_25V7K 1 2

100K_0402_5%

100K_0402_5%
1 2 1 2

1
VS PR8

PR6

PR7
PR9 1K_1206_5%
VIN 1M_0402_1%

2
1 2
1 2

10K_0402_1%
1
84.5K_0402_1%

2
1

VS

PR10
PR11

PR12
1K_0402_1%

100K_0402_5%
1 2 ACIN (20,33)

1
PR14

2
8

PR13
22K_0402_1%
2

1
1 2 3
P

+ PACIN PQ2
O 1 PACIN (41)
1000P_0402_50V7K

20K_0402_1%

2 DTC115EUA_SC70-3
-
1

10K_0402_1%
RLZ4.3B_LL34
0.1U_0402_16V7K

PU1A

12
1

1
PR15

2 LM393DG_SO8 2 2

(33,41) ACOFF
PC6

PC7

PR16
PQ3
4

Vin Detector

PD3
DTC115EUA_SC70-3
2

PR17 B+
2

2
10K_0402_1% High 18.764 17.901 17.063
2

3
2 1 RTCVREF 3.3V Low 17.745 16.9 16.03

3
VIN
PR18
VL

RLS4148_LLDS2
2.2M_0402_5%

2
2 1

PD4
PD5

499K_0402_1%
1
RLS4148_LLDS2

PR19
2 1 VS
3.3V BATT+

100K_0402_1%
68_1206_5%

68_1206_5%

1
RTCVREF

PR20

PR21
VS

PR22
G920AT24U_SOT89-3

2
PR24 PU2 PR25
PR23 560_0603_5% 200_0805_5%
2

8
560_0603_5% CHGRTCP PD6

2
1 2 1 2 3 OUT IN 2 2 1 3 1
0.22U_1206_25V7K

(40,42) MAINPWON 2 5

P
3 3
+
1

PC8
4.7U_0805_6.3V6K

0.1U_0603_25V7K
1U_0805_25V4Z

+CHGRTC 1 7 O
1

GND
100K_0402_5%
PC9

191K_0402_1%

499K_0402_1%

0.01U_0402_25V7K
(41) ACON 3 - 6
1

1
G
0.1U_0603_25V7K
PR26

PC10

PC11
PU1B

1
1

1000P_0402_50V7K

PR27

PR28

PC12
RB715F_SOT323-3 LM393DG_SO8
2

1
PC13
2

PC14
PR29
2

22K_0402_1%
2

2
2

2
(32,33) 51_ON# 1 2

1 PRG++
PQ4
TP0610K-T1-E3_SOT23-3

PR30 PQ5 PR31

PJ2 34K_0402_1% D RHU002N06_SOT323-3 47K_0402_5%
PAD-OPEN 3x3m PJ3 PAD-OPEN 3x3m
2 1 2 2 1
+1.5VSP 1 2 +1.5VS 1 2 +1.8V
RTCVREF G PACIN (41)
+1.8VP

1
S

66.5K_0402_1%
PJ4 PQ6

3
1
PR32
(7A,280mils ,Via NO.=14) (8A,320mils ,Via NO.= 16) PAD-OPEN 3x3m DTC115EUA_SC70-3
1 2 +VCCP PJ14
+1.05VSP
PJ5 PJ6 PAD-OPEN 3x3m 2 +5VALWP
PAD-OPEN 3x3m PAD-OPEN 3x3m 1 2 +VCCP @
+1.05VSP
+5VALWP 1 2 +5VALW +0.9VSP 1 2 +0.9VS (16A,800mils ,Via NO.= 24)

2
(16A,800mils ,Via NO.= 24)
PJ15

3
(6A,240mils ,Via NO.= 12) (2A,80mils ,Via NO.= 4) PAD-OPEN 3x3m PJ16
1 2 +1.8V PAD-OPEN 3x3m
+1.8VP
4 PJ7 +1.5VSP 1 2 +1.5VSP_LAN 4
PJ8
PAD-OPEN 3x3m
+3VALWP 1 2 +3VALW +2.5VSP 1 1 2 2 +2.5VS (8A,320mils ,Via NO.= 16)
(6A,240mils ,Via NO.=12)
JUMP_43X79
(6A,240mils ,Via NO.=12) (1A,40mils ,Via NO.= 2)
PJ9 PJ10
Security Classification Compal Secret Data Compal Electronics, Inc.
PAD-OPEN 3x3m PAD-OPEN 3x3m Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
+1.25VSP 1 2 +1.25VS +VSBP 1 2 +VSB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
(6A,240mils ,Via NO.=12) (0.3A,40mils ,Via NO.= 2) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 39 of 48
A B C D
 A B C D

BATT++ PJ11
PAD-OPEN 3x3m
BATT+
DC040003L00 1 2
PR34 PH1 under CPU botten side :
TYCO_1909383-1
9 7 BATT++
1 2 1 2 +3VALWP CPU thermal protection at 85 degree C
GND 7 CNT1 1K_0402_1% PR33

1000P_0402_50V7K

1000P_0402_50V7K
8 GND 6 6 Recovery at 70 degree C

0.01U_0603_50V7K
5 CNT2 47K_0402_1%
5

1
4 TS_A VS
4

1
PC15

PC16

PC17
3 EC_SMDA
3 EC_SMCA
2 2
VL

0.1U_0603_25V7K
GND

2
1
1 1 1

2
VL

1
@ PJP2

PC18

150K_0402_1%
PR36

2
10.7K_0402_1%
1K_0402_1% PR39

PR37
442K_0603_1%

2
PR38
1
1 2

1
PR42

8
61.9K_0603_1% PU5A
ALI/MH# (33,41)
1 2 3 PD18

P
+
0 1 1 2
1 2 TM_REF1 2 MAINPWON (39,42)
+3VALWP -

G
100K_0603_1%_TH11-4H104FT
1SS355TE-17_SOD323-2

1
1K_0402_1%
PR44 LM358ADR_SO8

1
6.49K_0402_1%

4
PH1
PR46
1

100_0402_1%

1000P_0402_50V7K

1U_0603_6.3V6M
PR40

PC19

PC20
PR43

2
2 150K_0402_1%
1 VL
BATT_TEMP (33)
2

2
100_0402_1%

150K_0402_1%
1

1
PR41

PR45
2 2
EC_SMB_DA1 (33,34)
2

2
EC_SMB_CK1 (33,34)

PQ7
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
0.22U_1206_25V7K

0.1U_0603_25V7K
1

100K_0402_5%

1
PR47

PC21

PC22

PR48
2

22K_0402_1%
2

VL 1 2
100K_0402_5%
2
PR49

3 3

PR50
1

0_0402_5% D
1

1 2 2 PQ8
(42,43) SPOK
G RHU002N06_SOT323-3
0.1U_0402_16V7K

S
1

PC23

3
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 40 of 48
A B C D
 A B C D

65W, Iadapter=0~3.42A, Current sense=0.02ohm, PR69=39.2K, CP=3.079A 65W PQ10,PQ11,PQ9->FDS4435

90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR69=28.7K, CP=4.263A
B+ PQ9
AO4407_SO8
PQ10 P2 PQ11 P3 1 8
AO4407_SO8 AO4407_SO8 PR51 2 7
VIN 8 1 1 8 1 4 3 6
7 2 2 7 PL2 CHG_B+ 5
6 3 3 6 2 3 FBMA-L11-322513-151LMA50T_1210
5 5 1 2
0.015_2512_1% CSIN

4
1 1

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
0.1U_0603_25V7K
CSIP
PR52

1
TP0610K-T1-E3_SOT23-3

PC24

PC25
47K_0402_1%
1

1
5600P_0402_25V7K

PC26

PC27
PQ44 PQ45 DTC115EUA_SC70-3 1 2 VIN

0.1U_0603_25V7K
PR53 VIN 3 1 DCIN

2
PR54
47K_0402_1% PD16

2
1

2
PC28

PC29
2FSTCHG PD7
2 1 PR55 1 2
PR207 ACOFF (33,39)
3SUSP# 10K_0402_1%
2

1
200K_0402_1%
1SS355TE-17_SOD323-2
100K_0402_1% RB715F_SOT323-3
3

PR208 100K_0402_1%

1
PQ12

3
1 2
DTA144EUA_SC70-3 (32,33) SUSP#
2 6251VDD 1 PR56 2
PD17 VIN

2.2U_0603_6.3V6K
1SS355TE-17_SOD323-2

1
PC31
1 2 Add EPA function 200K_0402_1%

1
(33) FSTCHG 2 PR57 1 PU4 PQ13
1

10K_0402_1% DTC115EUA_SC70-3 PD9

DCIN
1

2
1 VDD DCIN 24 2 1 2

1
100K_0402_1%
6251VDD 1 2
PC161 1SS355TE-17_SOD323-2 PQ16

1
D RHU002N06_SOT323-3

PR59
2 PR58 2 23 0.1U_0603_25V7K
ACSET ACPRN
1

1
0.1U_0603_25V7K
10K_0402_1%

2
2 PACIN (39)

PC33
PQ14 PR60 20_0603_1%

3
G
PQ17 DTC115EUA_SC70-3 150K_0402_1% PC35 CHGEN CSON

2
3 EN CSON 22 1 2 S
1

2
D
RHU002N06_SOT323-3 @ 680P_0402_50V7K PC34 PR247

3
(33,40) ALI/MH# 2

5
6
7
8
0.047U_0603_16V7K
3

2
PQ15 CSON 1 CSOP
2

G 2 4 21 1 2

D
D
D
D
DTC115EUA_SC70-3 CELLS CSOP PR61 PQ18

1
S
20_0603_1% SI4800BDY-T1-E3_SO8
3

2 2

3
ADP_I = 19.9*Iadapter*Rsense 1 2 5 ICOMP CSIN 20 2 1

G
S
S
S
PC36 6800P_0402_25V7K PR62 20_0603_1% If charge current is small,
PC38 PC37 0.1U_0603_25V7K
1 PR63
you can change to 16uH choke.

4
3
2
1
1 2 2 6 VCOMP CSIP 19 1 2
10K_0402_1% PR248 2.2_0603_1% PL3

1
0.01U_0402_25V7K 1 2 PR227
PR66 PC39 1 PR64 2 7 18 LX_CHG1 1 2 LX_CHG2 1 2 CHG 1 4
ICM PHASE BATT+
1

22K_0402_5% D 100P_0402_50V8J 100_0402_1% 0_0402_5%

PACIN 1 2 2 PQ19 10UH_SIL1045RA-100PF_4.5A_30% 2 3
(39) PACIN
G RHU002N06_SOT323-3 ADP_I 6251VREF 8 17 DH_CHG
PC40 VREF UGATE PR65
S

5
6
7
8
PR68 PR67 PC41 0.02_2512_1%
3

1 2

10U_1206_25V6M

10U_1206_25V6M
143K_0402_1% 9 16 BST_CHG 1 2 BST_CHGA 2 1

D
D
D
D
CHLIM BOOT

1
ACON 2 1 0.1U_0402_16V7K 2.2_0603_5% 0.1U_0603_25V7K PQ20
(39) ACON (33) IREF

1
PC42

PC43
SI4800BDY-T1-E3_SO8
0.01U_0402_25V7K

PR69 10 15 6251VDDP PD10

Be careful the ACLIM VDDP
1

G
S
S
S
6251VREF 1 2 1SS355TE-17_SOD323-2
1

IREF voltage!!
PC44

PR70 26251VDD

2
1
100K_0402_1% 28.7K_0402_1% DL_CHG 4.7_0603_5%

4
3
2
1
11 VADJ LGATE 14

2
2 1 PR71
2

2
(33,39) ACOFF PR72 PC45
2

12 GND PGND 13
PQ21 10K_0402_1% 4.7U_0805_6.3V6K

1
DTC115EUA_SC70-3 ISL6251AHAZ-T_QSOP24
6251VREF
3

3 1 1 2
PR73
@ 274K_0402_1%
1

PR74 @
3
@ 100K_0402_1% PQ22 PR209 100K_0402_1% 3

1 26251VREF
CP mode @ SI2301BDS-T1-E3_SOT23-3
@ PC162 0.01U_0402_25V7K
2

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) 1 2 CSON
where Vaclm=0.5535V, Iinput=3.079A If this area float, Charge voltage is 4.2V/cell BATT+
where Vaclm=0.6667V, Iinput=4.263A Overshoot solution during CC<->CV
CHGEN

1
(33) CHGSEL
PR75
340K_0402_1%
CC=0.6~3.4A

1
Charge Voltage C
VS PQ46

2
2
VCHLM=0.24V~1.36V 3S CC-CV MODE : 12.6V (CELLS=GND , ALI/MH#=3.3V) B 2SC2411K_SC59

1
E @
IREF=0.972*Icharge 4S CC-CV MODE : 16.8V (CELLS=VDD , ALI/MH#=0V) PR76

3
1
499K_0402_1%
IREF=0.5832V~3.3V PR210

8
PR77 PU5B 20K_0402_1%
10K_0402_1%

2
5

P
+ @
(33) BATT_OVP 1 2 7 0
0.01U_0402_25V7K

2
6
Charging Voltage -

G
BATT Type ALI/MH# CHGSEL CV mode

1
(0x15) LM358ADR_SO8
1

1
PC47

PR78 PC48

4
105K_0402_1% 0.01U_0402_25V7K
@
2800mAH 4S pack 17400mV LOW LOW 17.20V
2

2
OVP voltage :

2
4
LI-3S :13.50V--BATT-OVP=1.5V 4

2800mAH 3S pack 13050mV HIGH LOW 12.90V BATT-OVP=0.111*BATT+

Normal 4S LI-ON Cells 16800mV LOW HIGH 16.80V

Normal 3S LI-ON Cells

Security Classification Compal Secret Data Compal Electronics, Inc.
12600mV HIGH HIGH 12.60V Issued Date 2006/05/18 Deciphered Date 2007/05/18 Title
CHARGER
Wake up charge while THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
no communication - HIGH HIGH 12.60V AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS CHARGER 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 41 of 48
A B C D
 A B C D

B+

PL4
HCB4532KF-800T90_1812

PC49
1

2
1 2 BST5B BST3B 1 2

1 B+++ 0.1U_0402_16V7K PC50 0.1U_0402_16V7K 1

SI4800BDY-T1-E3_SO8
2200P_0402_50V7K VL

8
7
6
5
4.7U_1206_25V6K
4.7U_1206_25V6K
CHP202UPT_SOT323-3
PD11 B+++

1
D
D
D
D
1

0_0603_5%
PQ23
PC52

PC53
B+++
PC51

PR79

2200P_0402_50V7K

SI4800BDY-T1-E3_SO8
2

47_0402_5%

4.7U_1206_25V6K
0.1U_0402_16V7K
1

5
6
7
8
G
S
S
S

4.7_1206_5%

4.7_1206_5%

4.7U_1206_25V6K
PR80
2

1
PR81

PR82

PC54

PC56
PR83

D
D
D
D
1

PQ24
PC55

PC57
0_0603_5%

1
2
3
4

1
5HG DH5

2
1 2

G
S
S
S
LX5

2
@

SI4810BDY-T1-E3_SO8
8
7
6
5

0_0603_5%
0.1U_0603_25V7K
PC58
1U_0805_25V4Z

4
3
2
1
PR84
VL 3HG

D
D
D
D
8734_VREF

PQ25
LX3

200K_0402_1%
2

200K_0402_1%
4.7U_0805_6.3V6K

1 PC61

PR85

5
6
7
8
G
S
S
S

1U_0805_16V7K

PR86

SI4810BDY-T1-E3_SO8
1
1

PC59

D
D
D
D
1
1 BST3A
2
3
4

PQ26
PC60

0_0603_5%
DL5

G
S
S
S
PR87
2

1
2

499K_0402_1%
18

20

13

17

499K_0402_1%
PR88
PL5

4
3
2
1
2
10UH_SIL1045RA-100PF_4.5A_30% BST5A 14

TON

VCC
LD05

V+
BST5

PR89

1
2
ILIM3 5 2

16 DL3
DH5

1
+5VALWP

2
1

15 LX5 PL6

1
19 DL5 ILIM5 11
21 OUT5
9 PU6 28 10UH_SIL1045RA-100PF_4.5A_30%
FB5 BST3
10.5K_0402_1%

1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2

DL3 24
PR90
150U_V_6.3VM_R18

1
6 SHDN# LX3 27
VS 4 22
1 ON5 OUT3
1 2 3 ON3
+
PC62

PR91 7
0_0402_5% FB3
+3VALWP
1

12 SKIP# PGOOD 2
2 8734_VREF

PRO#
LDO3
PZD1 PR93 8

GND
REF
2

2
6.81K_0402_1%

6.49K_0402_1%
RLZ5.1B_LL34 47K_0402_5% @ PR94
PR92

1 2 1 2 10_0402_5%2

PR95

150U_V_6.3VM_R18
23

25

10
0.22U_0603_16V7K
0.047U_0603_16V7K

1
100K_0402_5%

4.7U_0805_6.3V6K
2

1
+

PC65

PC63
PR211
1

1
PR96

PC64

0_0402_5%

0_0402_5%
(40,43) SPOK
2

PC66

PR97
2

10K_0402_1%
2

PR98
PR99
1

2
+5V Ipeak = 6.66A ~ 10A 47K_0402_5%

1
1 2
0.047U_0603_16V7K

3 3

1
1

PC67

VFB=2V
2

+3.3V Ipeak = 6.66A ~ 10A

MAINPWON (39,40)
1U_0603_6.3V6M
1

PC68
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 42 of 48
A B C D
 5 4 3 2 1

PJ17
B+ 2 2 1 1

@ JUMP_43X118
PHASE_1.5V

10U_1206_25V6M

10U_1206_25V6M
PR212

PC163
1 0_0603_5%
2

1
D 6269_1.5V D

PC164

1
1 2 1 2
PR214

2
10K_0402_1% PR213 0_0603_5% PC82 0.1U_0402_16V7K
+5VALWP

SI4800BDY-T1-E3_SO8
1

5
6
7
8
BOOT_1.5V

2
PR215

D
D
D
D
0_0603_5%

PQ47
PR216

16

15
8

1
PU12 4.7_0603_5%

G
S
S
S
2 6269_1.5V

2
1

PHASE
GND

PGOOD

UG

BOOT
PC165

4
3
2
1
3 VIN PVCC 14 1 2

2.2U_0603_6.3V6K

6269_1.5V 4 13 LG_1.5V 1.8UH_SIL104R-1R8PF_9.5A_30%

PR228 VCC LG PL16
+1.5VSP

1
@ 0_0402_5%
1 2 PC166
1 2 +1.5VSP OCP==>7A~~8.5A
(40,42) SPOK
2.2U_0603_6.3V6K 12 1
PGND

2
SI4810BDY-T1-E3_SO8
2
Vripple==>40mV

5
6
7
8
PR218 PR217 + PC167
0_0402_5% 4.7_1206_5% 220U_D2E_4VM_R15M

D
D
D
D
1 2 5 11 ISEN_1.5V
1 2
(17,25,28,29,33,35,38,44,45) SUSP# EN ISEN 2

PQ48
PR219

COMP
4.42K_0402_1%

FSET

1
1

2
S
S
S
PC169

VO
FB

2
@ 0.1U_0402_16V7K PC168 PR220
C ISL6268CAZ-T_SSOP16 680P_0603_50V7K C

4
3
2
1
2.26K_0402_1%

10
2

1
1
22P_0402_50V8J
1

PR221

1
PC170

6800P_0402_25V7K
49.9K_0402_1%

1
PC171
2

1
PR222 0.01U_0402_25V7K
+1.5VSP 1
PC172

57.6K_0402_1% PR223

2
2
1.5K_0402_1%
2

2
1

PJ18
1

JUMP_43X79
@
2

+5VALWP
2
1

PC174 PC173
B 10U_0805_6.3V6M B
1U_0603_6.3V6M
2

PU13
6 VCNTL
PR224 5 3 +1.25VSP
VIN VOUT
9 VIN VOUT 4 OCP==>3A
1

0_0402_5%
1

22U_1206_6.3V6M

1 2 8 1.15K_0402_1% 0.01U_0402_25V7K
(17,25,28,29,33,35,38,44,45) SUSP# EN
1

PC175

7 2 PR225
GND

POK FB PC176
2
1

PC177 APL5913-KAC-TRL_SO8
2

@ 1U_0603_6.3V6M
1

2
2

PR226
2K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
1.5VSP/1.25VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 43 of 48
5 4 3 2 1
 5 4 3 2 1

D D

PL10
HCB4532KF-800T90_1812
1 2 B+

4.7U_1206_25V6K
4.7U_1206_25V6K

4.7U_1206_25V6K
4.7U_1206_25V6K
PR229

1
0_1206_5%

1
PC114

PC115
PC95

PC96
+5VALWP

2
2

2
1

2
PC180

1
4.7U_0805_6.3V6K PC181 PR230 PC182
0.1U_0603_25V7K 2.2_0603_5% 2.2U_0805_10V6K

2
PD19

2
DAP202U_SOT323

1
8
7
6
5

3
D BST_1.05V-1
D
D
D
+1.8V PQ31

BST_1.8V-1
SI4800BDY-T1-E3_SO8
C PC183 PC184 C

14

28
G
S
S
S

+1.8VP 0.01U_0402_25V7K PU14 0.01U_0402_25V7K

5
6
7
8
2 1 12 SOFT1 17 2 1

VIN

VCC
PL11 DH_1.8V-2 SOFT2
1
2
3
4

D
D
D
D
1 2LX_1.8V PC185 PC83
1.8UH_SIL104R-1R8PF_9.5A_30% 0.1U_0402_16V7K 0.1U_0402_16V7K
1 2 1 1 2BST_1.8V-2 6 23 BST_1.05V-2
1 2 2 1
BOOT1 BOOT2
+1.05V
1

G
S
S
S
PR231 PR249
4.7_1206_5%

+ PC98 0_0603_5% 0_0603_5%

Discrete use 220u_4V_R15
8
7
6
5
PR129

220U_D2E_4VM_R15M

4
3
2
1
1 2 DH_1.8V-1 5 24 DH_1.05V-1 1 2 DH_1.05V-2 PQ33 1.8UH_SIL104R-1R8PF_9.5A_30% UMA use 330u_2.5V_R15 +1.05VSP
D
D
D
D

2 PR126 UGATE1 UGATE2 PR142 SI4800BDY-T1-E3_SO8 PL12

1

PQ32 0_0603_5% 0_0603_5% LX_1.5V

2

4 PHASE1 PHASE2 25 1 2
1

PR235 PC186 SI4810BDY-T1-E3_SO8

G
S
S
S

220U_V_4VM_R15M
10.5K_0402_1% 0.01U_0402_25V7K PR236 PR237

@ 330U_D2_2.5VY_R15M
1

5
6
7
8
2K_0402_1% 2K_0402_1% 1 1
2

1
PC102
680P_0603_50V7K

ISE_1.8V ISE_1.05V
2

1
2
3
4

1 2 7 22 1 2

D
D
D
D
ISEN1 ISEN2

1
4.7_1206_5%

PC113

PC158
+ +
2

PR141
PR238 DL_1.8V PQ34 PR240
2

2 LGATE1 LGATE2 27

1
0_0402_5% SI4810BDY-T1-E3_SO8 0_0402_5% PC188 PR241

G
2 2

S
S
S
0.01U_0402_25V7K
1

2
4
3
2
1

2
3 PGND1 PGND2 26
DL_1.05V 1.82K_0402_1%

9 VOUT1 VOUT2 20
VSE_1.8V 10 19 VSE_1.05V
VSEN1 VSEN2
2 1 8 EN1 EN2 21 1 2
25,29,31,33 SYSON 15 16
PR127 PG1 PG2/REF PR147
GND

DDR

1
0_0402_5% 11 18
OCSET1 OCSET2
1

1
680P_0603_50V7K
PC116
0_0402_5%
2

1
0.01U_0402_25V7K

B PR242 ISL6227CAZ-T_SSOP28 PR244 PR245 B

13
1

1
PC99

10K_0402_1% PR116 @ 0_0402_5% 10K_0402_1%

1

2
@ 0_0402_5% PR243 PC118
PR246 124K_0402_1% 0.1U_0402_16V7K
124K_0402_1%
2

2
@
1

2
2

@
SUSP#
17,25,29,31,32,34,40

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
1.8VP/1.05VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 44 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS

1
PJ12

1
JUMP_43X79

2
+5VS
D D

2
1
1U_0603_6.3V6M

1
PC121 PC122 1@
10U_0805_6.3V6M

2
1@

2
PU9
6 VCNTL
PR149 5 3
0_0402_5% VIN VOUT
9 VIN VOUT 4 +2.5VSP
1@
1 2 8 EN

1
(17,25,28,29,33,35,38,43,44) SUSP# 7 2

GND
POK FB

22U_1206_6.3V6M
1@
1

PC124
PR148 PC123
PC125 APL5913-KAC-TRL_SO8 2.15K_0402_1%

2
@ 0.1U_0402_16V7K

2
1@ 1@

2
1
0.01U_0402_25V7K
1@
PR150
1K_0402_1%
1@

2
C C

+1.8V

1
PJ13
2 1
2 JUMP_43X79

PU10
1 VIN VCNTL 6 +3VALWP
B B
2 GND NC 5
1

1
1
PC126 3 7 PC127
10U_0805_6.3V6M VREF NC 1U_0603_6.3V6M
PR151
2

2
4 VOUT NC 8
1K_0402_1%
TP 9
2

PR152 APL5331KAC-TRL_SO8
+0.9VSP
1

0_0402_5% D
1

1 2 2 1
(38) SUSP G PR153
S 1K_0402_1% PC129
1

22U_1206_6.3V6M
3

PC130
2

@ 0.1U_0402_16V7K
2

PQ36 PC128
RHU002N06_SOT323-3 0.1U_0402_16V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
+2.5VSP/0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 45 of 48
5 4 3 2 1
 5 4 3 2 1

+5VS

CPU_B+ B+
PR154 PL13
5VS1 2 1 HCB4532KF-800T90_1812
1 2

0.01U_0402_25V7K
0_1206_5%

2200P_0402_50V7K
PR155

0.1U_0603_25V7K
1

PC131
10_0402_5% 1

1
10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M

220U_25V_M
PC132

PC133

PC134

PC135

PC136

PC137
200K_0402_1%
+

PR156 1
2

2
D D

2
PC138

2
2
2.2U_0603_6.3V6K 2

2
PR157 PC139
13K_0402_5% 1U_0603_6.3V6M

5
1

2
PQ37
PU11 SI7686DP-T1-E3_SO8
NTC 2.2_0603_5%

1
100K_0402_5% VCC 19 25 PR158
PR159 Vcc VDD
1 2DH1_CPU-24
1 2 6 8 0_0603_5% 0.22U_0603_16V7K
THRM TON PR161 PC140
PR160 0_0402_5% 2 1 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2
(5) CPU_VID0 D0 BST1 +CPU_CORE
PR162 0_0402_5% DH1__CPU-1 PQ38 PL14

3
2
1
(5) CPU_VID1 2 1 32 D1 DH1 29
SI4856DY-T1-E3_SO8 0.36H_ETQP4LR36WFC_24A_20%

4.7_1206_5%
PR163 0_0402_5% 2 1 33 28 LX1__CPU 2 1 +CPU_CORE
(5) CPU_VID2 D2 LX1

680P_0603_50V7K 2.1K_0402_1%
PR164 0_0402_5% 2 1 34 26 DL1__CPU
(5) CPU_VID3 D3 DL1

5
6
7
8

5
6
7
8

2
PR165

PR167

10_0402_5%
PR166 0_0402_5% 2 1 35 27

D
D
D
D

D
D
D
D
(5) CPU_VID4 D4 PGND1

SI4856DY-T1-E3_SO8
PR168 0_0402_5% 2 1 36 18
(5) CPU_VID5 D5 GND

1
PQ39
3.48K_0402_1%

2
G

G
S
S
S

S
S
S
PR169 0_0402_5% CSP1__CPU PR171 PH2 NTC

1
(5) CPU_VID6 1 2 37 D6 CSP1 17

1
1 2 1 2
PR1722 71.5K_0402_1% CSN1_CPU @

4
3
2
1

4
3
2
1
1 7 16

DL1__CPU
TIME CSN1 10KB_0603_5%_ERTJ1VR103J(5) VCCSENSE

PC141
FB_CPU

2
2 1 9 CCV FB 12 1 2

PR170
47P_0402_50V8J PC142
1 2 11 10 CCI_CPU PC143 0.22U_0603_16V7K
C REF CCI C

1 2 PC144 0.22U_0603_16V7K 39 21 DH2_CPU-1

(7,20) DPRSLPVR DPRSLPVR DH2
PR173 499_0402_1%

2
1 2 40 20 BST2_CPU
(5,7,19) H_DPRSTP# DPRSTP BST2
PR174 0_0402_5% PR175
1 2 3 22 LX2_CPU PR177 0_0402_5% 0_0402_5%
(5) H_PSI# PSI LX2
PR176 0_0402_5% 1 2
+3VS 2 24 DL2__CPU
PWRGD DL2 PR178 @ 3K_0603_1% PC145 0.022U_0402_16V7K

1
2

0_0603_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2

PR179
2

38 14 CSP2_CPU PR182 4.22K_0402_1%

PR180 PR181 SHDN CSP2
1 2 1 2
PR184 10K_0402_1% @ 2K_0402_1% 5 15 CSN2__CPU
0_0402_5% VRHOT CSN2 PR183 100_0402_1%

2
4 POUT GNDS 13
PC146
1

1 2 1 2 1 2

BSTM2_CPU
(7,20) VGATE 0_0402_5% 4700P_0402_25V7K
@ PR187 NTC PR185 PR186

1
TP
1 2 @ 3K_0603_1% @ 3K_0603_1%
(20) CLK_ENABLE# MAX8770GTL+_TQFN40
41

2
1 2 1 2
(33) VR_ON 1 2
PC148 PC147
2

CPU_B+

0.22U_0603_16V7K
PR189 PR188 470P_0603_50V8J
1

1
0_0402_5% PR190 +3VS 4700P_0402_25V7K 2 20K_0402_1%

PC149
@ 10K_0402_1%
1

PR191

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K
10U_1206_25V6M

0.1U_0603_25V7K
@ PR192 100_0402_1%

2
56_0402_5%
1

1
PC150

PC151

PC152

PC153

PC154
PR193 0_0402_5% PQ40
1

B B
VSSSENSE SI7686DP-T1-E3_SO8
2

1 2 NA
(4,20) H_PROCHOT# (5) VSSSENSE 2.2_0603_5%

2
PR194
1

1 2 DH2_CPU-2 4
1 2 PR196
POUT
@ 10_0402_5%
2

PR195 10K_0402_1%
PC155
2

3
2
1
0.1U_0402_16V7K 2 1
1

4.7_1206_5%
PL15

1
0.36H_ETQP4LR36WFC_24A_20%

PR197
5
6
7
8

5
6
7
8

2.1K_0402_1%
D
D
D
D

D
D
D
D

1
SI4856DY-T1-E3_SO8

SI4856DY-T1-E3_SO8

PR198
2
G

G
S
S
S

S
S
S

680P_0603_50V7K
PQ42

1
PQ41

PC156
4
3
2
1

4
3
2
1

2
DL2__CPU
PR199
3.48K_0402_1% NTC PH3

2
1 2 1 2

10KB_0603_5%_ERTJ1VR103J

1 2

A PR200 0_0402_5% PC157 0.22U_0603_16V7K A

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 06, 2007 Sheet 46 of 48
5 4 3 2 1
 5 4 3 2 1

page Reason for change Modify list

EVT P39,P42,P43,P44,P46 Shortage issue : needs to change another source SM010018210 Replace

D P46 Shortage issue : needs to change another source Change SB578400080 to SB000008L80
D

DVT
P39 1.Inrush decrease 1.Change PC1/PC4 from 0.01U to 1000P
2.Change to Standard part 2. PR1/PD1 no function,Change PD5 from RB751V to RL4148;Add PC6

P40 1.LM358A replace of LM393 1.PU5A replace of PU3A

2.Add Diode to anti reverse voltage 2.Add PD18 close to PU5A
3.Modify component size 3.Change PC15/PC16 from 0603 to 0402

P41 1.Add BATT-OVP function 1.Change PR78 value from 150K to 105K
2.Overshoot solution during CC<->CV 2-1.Add PR209 ,PC162 ,PR210 ,PQ44 ,PC161 ,PQ45 ;Del PQ46/PC30
3.Change torlance 2-2.Del PD8 ; Add PD17
4.Change to Standard part 3. Cange torlance from 0 ohm 5% to 10Kohm 1% at PR57
5. Add PR227 to anti reverse voltage 4. PD10: Change CH751H to 1SS355TE ; original PU5B
6. 65W change to Standard part to PU5A; Del PC46;Change PQ20 from SI4810 to SI4800
7.Add EPA Function 5. PR227 : currently use 0ohm. (In the future use 2.2ohm)
C C
6. Change PQ9/P10/PQ11 to FDS4435; Change PR69 to 39.2K
7.Add PD16/PR57/PR208/PR207/PC161

1.Add PR211 (@ PR94)

P42 1.Change 5V/3.3V in SKIP mode 2-1.Change PC62/PC63 from SGA20151360 to SF22001M300
2.Change to Standard part 2-2. Change PC49/PC50 from 0603_25V7K to 0402_16V7K
3.For EPA function
2-3. Change PL5/PL6 from 4.7UH to 10UH
3.Change PR95 from 6.81K to 6.49K

P43 Update 1.5VSP/1.25VSP to Standard part 1-1.Reduce capacitor value from 22u_1206_6.3V6M to 10u_0805_6.3VM at PC174
1-2.Change from dual PWM IC to single PWM IC for 1.5VSP (PU12),
Del PU7,PC69,PC71,PC72,,PC74,PC75,PC76,PC77,PC78,PC79,PC80,PC81,PC82,PC83,PC84,
PC85,PC86,PC87,PC88,PC90,PC91,
PC93,PC94,PD12,PD13,PL7,PL8,PL9,PQ27,PQ28,PQ29,PQ30,
PR100,PR102,PR103,PR104,PR105,PR106,PR107,PR108,PR109,PR110,PR111,PR112,PR113,PR114
,PR115,PR116,PR117,PR118,PR119,PR120,PR121,PR122,PR123
Add Part:PC82,PC163,PC164,PC165,PC166,PC167,PC168,PC169PC170,PC171,PC172,PC173,PC174,
PC175,PC176,PC177,PJ17,PJ18,PL16,PQ47,PQ48,PR212,PR213,PR214,PR215,PR216,PR217,PR218,
B
PR219,PR220,PR221PR222,PR223,PR224,PR225,PR226,PR228 B
1-3.APL5913(PU13) replace of APL5912

1-1.Change PC107/PC110/PC100 size from 0603 to 0402

P44 Update 1.05VSP/1.8VP to Standard part 1-2.Change PD14/PD15 from RB751 to 1SS355TE
1-3.Change PC158 size from R9M to R15M;Change PC98 from NEC to Panasonic
1-4.Add PC113

1-1.Change PC121 capacitor from 22u_1206_6.3V6M to (@ 10U_0805_6.3VM)

P45 Update 2.5VSP/0.9VSP to Standard part 1-2. APL5913 replace of APL5912 at PU9
1-3.Change PC126 capacitor from 22u_1206_6.3V6M to 10U_0805_6.3VM
1-4. Add PR149
1-5.UMA part : Del total 2.5VSP circuit->PU9/PC122/PC121/PR148/PR150/PC123/PC124/PR149

1-1.Change PC132/PC133/PC134/PC150/PC151/PC152 size from 10u_1206_25VAK to 10u_1206_25V6M

P46 Update +CPU_CORE to Standard part 1-2.Change PQ38/PQ39/PQ41/PQ42 from 8113 to SI4856
1-3.Change PR158/PR194 from 0ohm to 2.2ohm
1-4.Change PC137 to 3000hrs
A A

Title
<Title>

Size Document Number Rev

Custom<Doc> <RevCode>

Date: Tuesday, March 06, 2007 Sheet 47 of 48

5 4 3 2 1
 5 4 3 2 1

B-TEST

page Reason for change Modify list

P22 DFX ISSUE ADD RP49- RP52

D P26 LED control by EC ADD R672 D

P30 Reduce "bo" sound when ADD L42

enter sleep mode

P35 DFX ISSUE Del SIO debug port

P36 ADD C1182 C1183 R669

F/P DFX R670

C-TEST

page Reason for change Modify list

P10 fixed tv out ripple ADD L43 C1190

C C
P35 fixed COM PORT function re connect 14M & mirror
jp30 connection

P38 fixed 1st ac plug in SUSP# pull low 1ok (add

then led flash r678)

B B

A A

Title
<Title>

Size Document Number Rev

Custom<Doc> <RevCode>

Date: Tuesday, March 06, 2007 Sheet 48 of 48

5 4 3 2 1