A B C D E

Laptopblue
Desert Eagle
1
LA-3161P 1

Compal confidential
2 2

HEL80/HEL81 Schematics Document

Mobile Yonah uFCPGA with Intel
Calistoga_GM/PM+ICH7-M
3 3

Thursday, February 23, 2006

REV:0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 43
A B C D E
 A B C D E

Compal Confidential Laptopblue Thermal Sensor Clock Generator

Model Name : HEL80 Fan Control
page 4
Yonah
ADM1032 SLG8LP465VTR
page 4 page 15
File Name : LA-3161P uPGA-478 Package
page 4-6
ZZZ1

1 1
FSB
H_A#(3..31) 533/667MHz H_D#(0..63)
CRT & TV-out
15W_PCB
page 16

LCD Conn. LVDS Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2

page 16
Intel 945PM/GM Dual Channel BANK 0, 1, 2, 3 page 13,14

1.8V DDRII 400/533

uFCBGA-1466
PCI-Express page 7-12

nVidia G73M
VGA board Conn. DMI MDC 1.5 HD Codec Audio AMP
page 17 Conn ALC883 page 29
page 27 page 28

PCI BUS 3.3V 24.576MHz/48Mhz HD Audio

2
3.3V 33 MHz Intel ICH7-M 2

IDSEL:AD16 IDSEL:AD20
(PIRQE#, (PIRQA/B#, BGA-652 USB 2.0
GNT#0, GNT#2, 3.3V ATA-100 3.3V 48MHz
REQ#0) REQ#2)
S-ATA IDE page 18-21

IEEE 1394 CardBus S-ATA Bridge CDROM USB port 1 USB port 0 USB port5
VT6311S ENE CB714 Marvell 8040 Conn.
page 25 page 23 page 22 page 22
New Card MINI CARD x2 LAN RJ45 USB Conn. x1 Bluetooth
Socket page 35 page 27 page 26 page 34 Conn page 27
1394 Conn. Slot 0 3 in 1 S-ATA HDD
socket Conn. PCI Express Realtek
page 25 page 24 page 24
page 22 LAN 8111B
page 26
3 LPC BUS TPM1.2 3

PATA Conn. SLB9635 TT 1.2

page 35
DC-DC
page 22
DC-IN' page 33
page 36
ENE KB910L
page 31 +1.05VP/+1.8VP
BATT OVP page 40
page 37
INT KB /PWR BTN /Debug Port Int.KBD Touch Pad
page 30 page 30 page 34 +0.9VPS
CHARGER /+1.5VPS /
page 38 2.5VPS page 41
CIR BIOS
D2D /CMOS /FP /LID /KILL# page 35 page 32
page 33
4
+3/5 VAWL VCORE 4

page 39 page 42

TP /SW /USB OC /LED

page 34
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HEL80 LA-3161P
Date: Thursday, February 23, 2006 Sheet 2 of 43
A B C D E
 A

Voltage Rails SKU ID Table

Laptopblue
+5VS
Vcc
Ra
3.3V +/- 5%
100K +/- 5%
+3VALW KB910L
SB
mA
160mA
+3VS RTL8110SBL/CL
power Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
plane +2.5VS
+1.8VS
0 0 0 V 0 V 0 V
+CPU_CORE CPU 36A
+B 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW +1.8V +1.5VS
LDO3 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW +5V +1.2VS +VCCP CPU 2.5A
LDO5 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+VGA_CORE NB 9.8A
+0.9VS
4 56K +/- 5% 1.036 V 1.185 V 1.264 V (14.7A)
State 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+CPU_CORE
6 200K +/- 5% 1.935 V 2.200 V 2.341 V +5VS EXPRESS CARD 1A
+VCCP
7 NC 2.500 V 3.300 V 3.300 V HDD 1.5A
ODD 1.8A
S0 O O O O SKU ID HEL80/81 SKU MDC 300mA
* 0 HEL80 SKU APA2066 1A
S1 1 HEL81 SKU TPA0211 mA
O O O O
2 TEST MODE AD1986 70mA
S3 3 USB PORT * 6 3A
O O O X
4
S5 S4/AC 5
O O X X
6 +3VS NB 480mA
7 EXPRESS CARD 1A
S5 S4/ Battery only
O X X X CLK_GEN 200mA
BOM Structure USB PORT LIST LCDVCC 1A
S5 S4/AC & Battery MARK FUNCTION VGA CARD (G7XM) 655mA
don't exist X X X X @ NC FOR ALL PORT DEVICE SB 680mA
UMA@ Internal 945GM 0 LEFT SIDE R5C832 mA
O MEANS ON S3 : STR VGA@ External G7xM 1 BLUE TOOTH BIOS ROM 15mA
X MEANS OFF S4 : STD TPM@ TPM1.2 2 RIGHT SIDE KB910L 200mA
S5 : SOFT OFF CIR@ CIR 3 CMOS CB1410 mA
1394@ 1394 4 RIGHT SIDE
1
SATA@ SATA HDD 5 FINGER PRINTER +2.5VS VGA CARD (G7XM) 130mA 1

8040@ PATA HDD 6 NEW CARD NB (143mA)

External PCI Devices IOMP@ IOMP 7 TV
Device IDSEL# REQ#/GNT# Interrupts
15W@ 15W PANEL
CardBus AD20 2 PIRQA/B
APA@ HP out from AMP DDR2_DIMM 8A
13 94 AD16 0 PIRQE +1.8V
HPA@ HP out from HP AMP NB (667Mhz) 3.1A
HP@ HP out from CODEC
+1.8VS GDDR2 6A
VGA CARD (G7XM) 4.06A

EC SM Bus1 address EC SM Bus2 address

+0.9VREF DDR2_DIMM 10mA
Device Address Device Address
Smart Battery 0001 011X b ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b +0.9VS GDDR2 1A
DDR2_DIMM 2A
ICH7 SM Bus address
+1.5V SB 40mA
Device Address
Clock Generator
(SLG8LP465VTR) 1101 001Xb
+1.5VS NB 8.9A(13.8A)
DDRII DIMM0 1010 000Xb
SB 3.8A
DDRII DIMM1 1010 010Xb
MiniCard 1A
EXPRESS CARD 0.65A
VGA CARD (G7XM) 2A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 3 of 43
A
 5 4 3 2 1

<7> H_A#[3..31]
Laptopblue H_D#[0..63] <7>
ITP_TDI
This shall place near CPU
R130 1 2 56_0402_5%
+VCCP

JP1A ITP_TMS R129 56_0402_1%

H_A#3 J4 E22 H_D#0 ITP_TDO R128 1 2 56_0402_5%

H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 ITP_BPM#5 R127 1
M3 A5# D2# E26 2 56_0402_5%
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 ITP_TRST# R119 1
M1 A7# D4# F23 2 56_0402_5%
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 ITP_TCK R120 1
J1 A9# D6# E25 2 56_0402_5%
D H_A#10 H_D#7 D
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10
H_A#14 A13# D10# H_D#11
P4 A14# D11# J23
H_A#15 P1 H26 H_D#12 ITP_DBRESET# R82 1 2 @ 200_0402_5% PAD T14
H_A#16 A15# D12# H_D#13
R1 A16# D13# F26
H_A#17 Y2 K22 H_D#14 ITP_BPM#0 PAD T18
H_A#18 A17# D14# H_D#15 ITP_BPM#1 T20
U5 A18# D15# H25 PAD
H_A#19 R3 N22 H_D#16 ITP_BPM#2 PAD T21
H_A#20 A19# D16# H_D#17 ITP_BPM#3 T17
W6 A20# D17# K25 PAD
H_A#21 U4 P26 H_D#18 ITP_BPM#4 PAD T19
H_A#22 A21# D18# H_D#19
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20
H_A#24 A23# D20# H_D#21
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22
H_A#26 A25# D22# H_D#23
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24
H_A#28
H_A#29
W5
Y4
A27#
A28#
D24#
D25# P22
P23
H_D#25
H_D#26
Thermal Sensor ADM1032AR
H_A#30 A29# D26# H_D#27 +3VS
W2 A30# D27# T24
H_A#31 Y1 R24 H_D#28
<7> H_REQ#[0..4] A31# D28#
L26 H_D#29
H_REQ#0 D29# H_D#30
K3 REQ0# D30# T25 2
H_REQ#1 H2 N24 H_D#31 C405
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33 0.1U_0402_16V4Z
H_REQ#4 REQ3# D33# H_D#34 1
L5 REQ4# D34# V24
V26 H_D#35 U24
H_ADSTB#0 D35# H_D#36 EC_SMB_CK2
<7> H_ADSTB#0 L2 ADSTB0# D36# W25 1 VDD SCLK 8 EC_SMB_CK2 <31>
H_ADSTB#1 V4 U23 H_D#37
<7> H_ADSTB#1 ADSTB1# D37#
U25 H_D#38 H_THERMDA 2 7 EC_SMB_DA2
C D38# D+ SDATA EC_SMB_DA2 <31> C
U22 H_D#39 C406
D39# H_D#40 H_THERMDC
D40# AB25 1 2 3 D- ALERT# 6
W22 H_D#41
D41# H_D#42 2200P_0402_50V7K THERM#
D42# Y23 4 THERM# GND 5
CLK_CPU_BCLK A22 AA26 H_D#43
<15> CLK_CPU_BCLK BCLK0 D43#
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44 R303
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45 ADM1032ARMZ-2REEL_MSOP8
D45# Y22 +3VS 1 2
AC26 H_D#46
D46# H_D#47 10K_0402_5%
D47# AA24 Address:100_1100
H_ADS# H1 AC22 H_D#48
<7> H_ADS# ADS# D48#
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49# Note : ADM1032 has no SO8 lead free ones.Only MSO8
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53
<7> H_DRDY# DRDY# D53#
R69 H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
<7> H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56
+VCCP H_LOCK# IERR# D56# H_D#57 +5VS
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
<7> H_RESET# RESET# D58#
AD21 H_D#59
D59#

1
<7> H_RS#[0..2] AE25 H_D#60 D16
H_RS#0 D60# H_D#61
F3 RS0# D61# AF25
H_RS#1 F4 AF22 H_D#62 1SS355_SOD323
H_RS#2 RS1# D62# H_D#63 +5VS
G3 RS2# D63# AF26
H_TRDY# G2 C399 10U_1206_16V4Z D15
<7> H_TRDY#

2
TRDY#
1 2
J26 H_DINV#0 2
DINV0# H_DINV#0 <7>
M26 H_DINV#1
DINV1# H_DINV#1 <7>
ITP_BPM#0 AD4 V23 H_DINV#2 U23 1
BPM0# DINV2# H_DINV#2 <7>
ITP_BPM#1 AD3 AC20 H_DINV#3 1 8
BPM1# DINV3# H_DINV#3 <7> VEN GND
ITP_BPM#2 AD1 2 7 3
B ITP_BPM#3 BPM2# +VCC_FAN1 VIN GND B
AC4 BPM3# H_DSTBN#[0..3] <7> 3 VO GND 6
H23 H_DSTBN#0 EN_FAN1 4 5
DSTBN0# <31> EN_FAN1 VSET GND
ITP_DBRESET# C20 M24 H_DSTBN#1 1N4148_SOT23
<20> ITP_DBRESET# DBR# DSTBN1#
H_DBSY# E1 W24 H_DSTBN#2 G993P1UF_SOP8
<7> H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
<19> H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] <7>
H_DPRSTP# E5 G22 H_DSTBP#0 C397
<19,42> H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1 1 2
<7> H_DPWR# DPWR# DSTBP1#
ITP_BPM#4 AC2 MISC Y25 H_DSTBP#2
<42> H_PROCHOT# ITP_BPM#5 PRDY# DSTBP2# H_DSTBP#3 +3VS 10U_1206_16V4Z
AC1 PREQ# DSTBP3# AE24
H_PROCHOT# D21 C401
+VCCP R68 68_0402_5% PROCHOT#
1 2

1
H_PW RGOOD D6
<19> H_PWRGOOD H_CPUSLP# PWRGOOD R297 1000P_0402_50V7K
<7,19> H_CPUSLP# D7 SLP#
ITP_TCK AC5
ITP_TDI TCK H_A20M# 10K_0402_5%
ITP_TDO
AA6 TDI A20M# A6
H_FERR#
H_A20M# <19> 40mil JP2
AB3 A5 H_FERR# <19>

2
R71 TEST1 TDO FERR# H_IGNNE# +VCC_FAN1
1 2 @ 1K_0402_5% C26 TEST1 IGNNE# C4 H_IGNNE# <19> 1 1
R70 1 2 51_0402_5% TEST2 D25 B3 H_INIT# 2
TEST2 INIT# H_INIT# <19> <31> FAN_SPEED1 2
ITP_TMS AB5 C6 H_INTR 3
TMS LINT0 H_INTR <19> 3
ITP_TRST# AB6 B4 H_NMI 1
TRST# LINT1 H_NMI <19>
LEGACY CPU C402 4 GND
THERMAL 5 GND
H_THERMDA A24 D5 H_STPCLK# 1000P_0402_50V7K
H_THERMDC A25
THERMDA DIODE STPCLK#
A3 H_SMI#
H_STPCLK# <19> 2
THERMDC SMI# H_SMI# <19> ACES_85205-03001
H_THERMTRIP# C7
<7,19> H_THERMTRIP# THERMTRIP#
H_THERMDA, H_THERMDC routing together.
TYCO_1-1674770-2_Yonah~D
Trace width / Spacing = 10 / 10 mil ME@

+VCCP
A A
1

R72

@ 56_0402_5%
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

B

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

E

H_PROCHOT# 3 1 OCP#
OCP# <20> Yonah CPU in mFCPGA479
C

Q4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@ MMBT3904_SOT23 2005/11/07 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom HEL80 LA-3161P 0.2
Modified Q4 part number to SB039040000. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 4 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue

+VCCP +CPU_CORE
JP1B JP1C
D D

1
<42> VCCSENSE VCCSENSE AF7 AB26 AE18 K1
R79 +CPU_CORE VSSENSE VCCSENSE VSS VCC VSS
<42> VSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
R126 AD25 AB15 M2
+CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS
VSS AC24 AC15 VCC VSS R2
R134 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1

1 2 VSSENSE 1 1 M6 AA22 AB14 A26

R67 C146 C144 VCCP VSS VCC VSS
N6 AD22 AA13 D26

2K_0402_1% 0.01U_0402_16V7K 10U_0805_10V4Z

T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
Close to CPU pin N21
T21
VCCP VSS AC19
AF19
AA12
AD12
VCC YONAH VSS E24
B21
Close to CPU pin AD26 VCCP VSS VCC VSS
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22
W21 AA16 AE12 E21

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
V6 AD16 AB10 B19
Trace / Width = 4 / 25 mils Trace / Width = 18 / 50 mils G21
VCCP
VCCP
VSS
VSS AC16 AB9
VCC
VCC
VSS
VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
<42> H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
CPU_VID0 AD6 AD13 AC10 B16
<42> CPU_VID0 VID0 VSS VCC VSS
CPU_VID1 AF5 AC14 AC9 A16
<42> CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
<42> CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
<42> CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
C <42> CPU_VID4 VID4 VSS VCC VSS C
CPU_VID5 AF2 AA11 AE9 E16
<42> CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
<42> CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
+CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
<15> CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 CPU_BSEL1
1 <15> CPU_BSEL1
CPU_BSEL2
B23
C21
BSEL1 VSS AD8
AC8
F20
E20
VCC VSS B11
A11
<15> CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+CPU_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
AB18 AD2 B15 J25
0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R123

R131
R80

R81

AA17 C5 C15 T26

mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
P6 F14 L24
B COMP 0/2Trace / Width = 18 / 25 mils VSS
VSS R5 E13
VCC
VCC
VSS
VSS P24 B
D2 V5 B12 N23
COMP 1/3Trace / Width = 5 / 25 mils F6
RSVD
RSVD
VSS
VSS U6 A12
VCC
VCC
VSS
VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

TYCO_1-1674770-2_Yonah~D TYCO_1-1674770-2_Yonah~D
ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 5 of 43
5 4 3 2 1
 5 4 3 2 1

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D +CPU_CORE D

1 1 1 1 1 1 1 1
C411 C417 C175 C193 C443 C191 C206 C208
Place these capacitors on L8
(North side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
C416 C212 C437 C201 C409 C211 C189 C438
Place these capacitors on L8
(North side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
C207 C192 C428 C412 C195 C427 C204 C199
Place these capacitors on L8
(Sorth side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2

C C
+CPU_CORE

1 1 1 1 1 1 1 1
C174 C188 C442 C196 C202 C200 C410 C205
Place these capacitors on L8
(Sorth side,Secondary Layer) 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 2 2

Mid Frequence Decoupling

+CPU_CORE
330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R9
1 1 1 1 1 1 ESR <= 1.5m ohm
Capacitor > 1980uF
C414

C198

C197

C431

C413

C415
+ + + + + + North Side Secondary
South Side Secondary
2 2 2 2 2 2
B B

+VCCP

1
1 1 1 1 1 1
C131 + C209 C176 C178 C177 C210 C213 Place these inside
socket cavity on L8
220U_D2_2VMR15 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 6 of 43
5 4 3 2 1
 5 4 3 2 1

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Note : 2005/12/26 modify pn
PM : SA00000KDC0
U22

GM : SA0000059H0
<4> H_D#[0..63] H_A#[3..31] <4> PM Description at page 11.
U22A VGA@ U22B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 <20> DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 <15>
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# <20> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <15>
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# <20> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 <15>
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T9
HD4# HA7# <20> DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T3
D H_D#6 HD5# HA8# H_A#9 CFG4 CFG5 D
G1 HD6# HA9# F9 CFG5 F15 CFG5 <11>
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 PAD T10
HD7# HA10# <20> DMI_TXP0 DMIRXP0 CFG6
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# <20> DMI_TXP1 DMIRXP1 CFG7 CFG7 <11>
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 PAD T7
HD9# HA12# <20> DMI_TXP2 DMIRXP2 CFG8

DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <20> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10
HD11# HA14# CFG10 CFG10 <11>
H_D#12 H4 H13 H_A#15 D15 CFG11
HD12# HA15# CFG11 CFG11 <11>
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <20> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <20> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>

CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T4
HD15# HA18# <20> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T8
HD16# HA19# <20> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T2
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <20> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <20> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <20> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <20> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# <13> M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 CLK_MCH_DREFCLK#

CLK
HD27# HA30# <14> M_CLK_DDR2 SM_CK2 D_REF_CLKN CLK_MCH_DREFCLK# <15>
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 CLK_MCH_DREFCLK
HD28# HA31# <14> M_CLK_DDR3 SM_CK3 D_REF_CLKP CLK_MCH_DREFCLK <15>
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0
W6 HD30# <13> M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 CLK_MCH_SSCDREFCLK# CLK_MCH_SSCDREFCLK# <15>
H_D#31 T5 M_CLK_DDR#1 AT1 D41 CLK_MCH_SSCDREFCLK
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP CLK_MCH_SSCDREFCLK <15>
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 MCH_CLKREQ#
HD33# HREQ#1 <14> M_CLK_DDR#3 SM_CK3# CLK_REQ# MCH_CLKREQ# <15>
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 <13> DDR_CKE0_DIMMA AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 DDR_CKE1_DIMMA AT20
HD36# HREQ#4 <13> DDR_CKE1_DIMMA SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# <14> DDR_CKE2_DIMMB SM_CKE2 NC0 C
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39
HD38# <14> DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 <4> NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# <13> DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1

NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 T12 PAD M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 T1 PAD AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 M_ODT0 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBP#[0..3] <4> <13> M_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 H_DSTBP#0 +1.8V M_ODT1
AB4 HD49# HDSTBP#0 K3 <13> M_ODT1 BA12 SM_ODT1 NC12 BA41
H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 <14> M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
HD51# HDSTBP#2 <14> M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R33 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 R32 1 2 80.6_0402_1% SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 +DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 T32

HD58# HDINV#3 H_DINV#3 <4> RESERVED1
1

H_D#59 AC6 R32

H_D#60 HD59# R93 PM_BMBUSY# RESERVED2
AB5 HD60# <20> PM_BMBUSY# G28 PM_BMBUSY# RESERVED3 F3
R30

R31

H_D#61 AD10 B7 H_RESET# 0_0402_5% <13,14> PM_EXTTS#0 PM_EXTTS#0 F25 F7

HD61# HCPURST# H_RESET# <4> PM_EXTTS0# RESERVED4

RESERVED
PM
H_D#62 AD4 E8 H_ADS# 2 1 PM_EXTTS#1 H26 AG11
HD62# HADS# H_ADS# <4> <20,42> DPRSLPVR PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,19> H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# <4>
2

HD63# HTRDY# H_DPWR# ICH_POK PM_THERMTRIP# RESERVED6

HDPWR# J9 H_DPWR# <4> <20,31> ICH_POK AH33 PWROK RESERVED7 H7
H8 H_DRD Y# 2 1 PLTRST_R# AH34 J19
HDRDY# H_DRDY# <4>
<17,18,20,22,26,27,31,35> PLT_RST# RSTIN# RESERVED8
J13 C3 H_DEFER# R60 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# <4> RESERVED9
+H_VREF K13 D4 H_HITM# <18> MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# <4> ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# <4> RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# <4> RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# <4> RESERVED13
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# <4>
+H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# <4>
+H_SWNG1 W1 A7 H_DBSY# UMA@
HYSWING HDBSY# H_DBSY# <4>
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# <4,19>
24.9_0402_1%

24.9_0402_1%

+DDR_MCH_REF
1

trace width and

R28

R24

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 spacing is 20/20.
D6 H_RS#2 +3VS
HRS2#
H_RS#[0..2] <4>
2

CALISTOGA_FCBGA1466~D +1.8V
UMA@
R51

1
10K_0402_5%
R27 PM_EXTTS#0 2 1

Layout Note: 100_0402_1% R56

@ 10K_0402_5%

2
H_XRCOMP / H_YRCOMP / +H_VREF / +H_SWNG0 / +DDR_MCH_REF PM_EXTTS#1 2 1
+H_SWNG1 trace width and spacing is 10/20.
1
0.1U_0402_16V4Z

1 R26
+VCCP +VCCP
C14

100_0402_1%
+VCCP
2

2
1

1
221_0603_1%

221_0603_1%
100_0402_1%
1

R25

R22
R34

A A
2

+H_SWNG0 +H_SWNG1
2

+H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
100_0402_1%

100_0402_1%
1

1 1
R23
1

200_0603_1%

R29

1
C16

C9
R38

C24

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

2
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80/81 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 7 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue

D D

U22D U22E
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
<13> DDR_A_BS#0 SA_BS0 SA_DQ0 <14> DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
<13> DDR_A_BS#1 SA_BS1 SA_DQ1 <14> DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
<13> DDR_A_BS#2 SA_BS2 SA_DQ2 <14> DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
<13> DDR_A_DM[0..7] AK35 DDR_A_D5 <14> DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
<13> DDR_A_DQS[0..7] AL27 DDR_A_D17 <14> DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
C DDR_A_DQS4 DDR_A_D22 DDR_B_DQS4 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
<13> DDR_A_DQS#[0..7] AN20 DDR_A_D27 <14> DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
<13> DDR_A_MA[0..13] SA_DQ38 AL14 <14> DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
<13> DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 <14> DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
<13> DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 <14> DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
<13> DDR_A_WE# SA_WE# SA_DQ58 <14> DDR_B_WE# SB_WE# SB_DQ58
T6 PAD SA_RCVENIN# AK23 AF6 DDR_A_D59 T5 PAD SB_RCVENIN# AK16 AK3 DDR_B_D59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
T13 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T11 PAD AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63

CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D
UMA@ UMA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80/81 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 8 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue

D D

10 mils R59 +1.5VS_PCIE

U22C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 SDVOCTRL_CLK EXP_COMPO D38 PEG_RXP[0..15] <17>
F34 PEG_RXN0
LVDSA0+ EXP_RXN0 PEG_RXN1
<16> LVDSA0+ B37 LA_DATA0 EXP_RXN1 G38
<16> LVDSA1+ LVDSA1+ B34 H34 PEG_RXN2
LVDSA2+ LA_DATA1 EXP_RXN2 PEG_RXN3
<16> LVDSA2+ A36 LA_DATA2 EXP_RXN3 J38
L34 PEG_RXN4
LVDSA0- EXP_RXN4 PEG_RXN5
<16> LVDSA0- C37 LA_DATA#0 EXP_RXN5 M38
<16> LVDSA1- LVDSA1- B35 N34 PEG_RXN6
LVDSA2- LA_DATA#1 EXP_RXN6 PEG_RXN7
<16> LVDSA2- A37 LA_DATA#2 EXP_RXN7 P38
R34 PEG_RXN8
LVDSB0+ EXP_RXN8 PEG_RXN9
<16> LVDSB0+ F30 LB_DATA0 EXP_RXN9 T38
LVDSB1+ PEG_RXN10

LVDS
<16> LVDSB1+ D29 LB_DATA1 EXP_RXN10 V34
<16> LVDSB2+ LVDSB2+ F28 W38 PEG_RXN11
LB_DATA2 EXP_RXN11 PEG_RXN12
EXP_RXN12 Y34
<16> LVDSB0- LVDSB0- G30 AA38 PEG_RXN13
LVDSB1- LB_DATA#0 EXP_RXN13 PEG_RXN14
<16> LVDSB1- D30 LB_DATA#1 EXP_RXN14 AB34
<16> LVDSB2- LVDSB2- F29 AC38 PEG_RXN15
LB_DATA#2 EXP_RXN15 PEG_RXN[0..15] <17>

<16> LVDSAC+ LVDSAC+ A32 D34 PEG_RXP0

LVDSAC- LA_CLK EXP_RXP0 PEG_RXP1
<16> LVDSAC- A33 LA_CLK# EXP_RXP1 F38
<16> LVDSBC+ LVDSBC+ E26 G34 PEG_RXP2
LVDSBC- LB_CLK EXP_RXP2 PEG_RXP3
<16> LVDSBC- E27 LB_CLK# EXP_RXP3 H38
J34 PEG_RXP4

PCI-EXPRESS GRAPHICS
EXP_RXP4 PEG_RXP5
D32 LBKLT_CTL EXP_RXP5 L38
C GMCH_ENBKL PEG_RXP6 C
<16> GMCH_ENBKL J30 LBKLT_EN EXP_RXP6 M34
H30 N38 PEG_RXP7
LCTLA_CLK EXP_RXP7 PEG_RXP8
H29 LCTLB_DATA EXP_RXP8 P34
EDID_CLK_LCD G26 R38 PEG_RXP9
EDID_DAT_LCD LDDC_CLK EXP_RXP9 PEG_RXP10
G25 LDDC_DATA EXP_RXP10 T34
<16> GMCH_LVDDEN GMCH_LVDDEN F32 V38 PEG_RXP11
LVDD_EN EXP_RXP11 PEG_RXP12
2 1 B38 LIBG EXP_RXP12 W34
R58 1.5K_0402_1%
C35 Y38 PEG_RXP13
LVBG EXP_RXP13 PEG_RXP14
C33 LVREFH EXP_RXP14 AA34
C32 AB38 PEG_RXP15 PEG_M_TXP[0..15] <17>
LVREFL EXP_RXP15
2 1 TV_COMPS F36 PEG_TXN0 C180 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN0
R286 UMA@ 150_0402_1% TV_COMPS EXP_TXN0 PEG_TXN1 C148 VGA@ 0.1U_0402_10V7K PEG_M_TXN1
<16> TV_COMPS A16 TVDAC_A EXP_TXN1 G40 1 2
2 1 TV_LUMA <16> TV_LUMA TV_LUMA C18 H36 PEG_TXN2 C163 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN2
R287 UMA@ 150_0402_1% TV_CRMA TVDAC_B EXP_TXN2 PEG_TXN3 C135 VGA@ 0.1U_0402_10V7K PEG_M_TXN3
<16> TV_CRMA A19 TVDAC_C EXP_TXN3 J40 1 2

TV
2 1 TV_CRMA L36 PEG_TXN4 C182 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN4
R288 UMA@ 150_0402_1% EXP_TXN4 PEG_TXN5 C150 VGA@ 0.1U_0402_10V7K PEG_M_TXN5
2 1 J20 TV_IREF EXP_TXN5 M40 1 2
R47 4.99K_0402_1% N36 PEG_TXN6 C167 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN6
EXP_TXN6 PEG_TXN7 C137 VGA@ 0.1U_0402_10V7K PEG_M_TXN7
B16 TV_IRTNA EXP_TXN7 P40 1 2
B18 R36 PEG_TXN8 C184 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN8
TV_IRTNB EXP_TXN8 PEG_TXN9 C152 VGA@ 0.1U_0402_10V7K PEG_M_TXN9
B19 TV_IRTNC EXP_TXN9 T40 1 2
V36 PEG_TXN10 C161 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN10
EXP_TXN10 PEG_TXN11 C139 VGA@ 0.1U_0402_10V7K PEG_M_TXN11
J29 TV_DCONSEL1 EXP_TXN11 W40 1 2
K30 Y36 PEG_TXN12 C186 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN12
TV_DCONSEL0 EXP_TXN12 PEG_TXN13 C154 VGA@ 0.1U_0402_10V7K PEG_M_TXN13
EXP_TXN13 AA40 1 2
AB36 PEG_TXN14 C165 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXN14
EXP_TXN14 PEG_TXN15 C141 VGA@ 0.1U_0402_10V7K PEG_M_TXN15
EXP_TXN15 AC40 1 2 PEG_M_TXN[0..15] <17>
3VDDCCL C26
<16> 3VDDCCL DDCCLK
CRT

3VDDCDA C25 D36 PEG_TXP0 C179 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP0

<16> 3VDDCDA DDCDATA EXP_TXP0
F40 PEG_TXP1 C147 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP1
CRT_VSYNC R50 VSYNC EXP_TXP1 PEG_TXP2 PEG_M_TXP2
<16> CRT_VSYNC 1 2 UMA@ 39_0402_5% H23 VSYNC EXP_TXP2 G36 C162 1 2 VGA@ 0.1U_0402_10V7K
<16> CRT_HSYNC CRT_HSYNC R53 1 2 UMA@ 39_0402_5% HSYNC G23 H40 PEG_TXP3 C134 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP3
B CRT_B HSYNC EXP_TXP3 PEG_TXP4 C149 VGA@ 0.1U_0402_10V7K PEG_M_TXP4 B
<16> CRT_B E23 BLUE EXP_TXP4 J36 1 2
D23 L40 PEG_TXP5 C181 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP5
CRT_G BLUE# EXP_TXP5 PEG_TXP6 C166 VGA@ 0.1U_0402_10V7K PEG_M_TXP6
<16> CRT_G C22 GREEN EXP_TXP6 M36 1 2
B22 N40 PEG_TXP7 C136 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP7
CRT_R GREEN# EXP_TXP7 PEG_TXP8 C183 VGA@ 0.1U_0402_10V7K PEG_M_TXP8
<16> CRT_R A21 RED EXP_TXP8 P36 1 2
2 1 CRT_R B21 R40 PEG_TXP9 C160 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP9
R289 UMA@ 150_0402_1% RED# EXP_TXP9 PEG_TXP10 C151 VGA@ 0.1U_0402_10V7K PEG_M_TXP10
EXP_TXP10 T36 1 2
2 1 CRT_G V40 PEG_TXP11 C138 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP11
R290 UMA@ 150_0402_1% CRT_IREF EXP_TXP11 PEG_TXP12 C185 VGA@ 0.1U_0402_10V7K PEG_M_TXP12
2 1 J22 CRT_IREF EXP_TXP12 W36 1 2
2 1 CRT_B R49 255_0402_1% Y40 PEG_TXP13 C153 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP13
R291 UMA@ 150_0402_1% EXP_TXP13 PEG_TXP14 C140 VGA@ 0.1U_0402_10V7K PEG_M_TXP14
AA36 1 2
10 mils EXP_TXP14
EXP_TXP15 AB40 PEG_TXP15 C164 1 2 VGA@ 0.1U_0402_10V7K PEG_M_TXP15

CALISTOGA_FCBGA1466~D
UMA@
2/20 modified to 0402_X7R
+3VS
1

R293 R294

2.2K_0402_5% 2.2K_0402_5%
UMA@ UMA@
2

<16> EDID_CLK_LCD EDID_CLK_LCD

A A

<16> EDID_DAT_LCD EDID_DAT_LCD

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80/81 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 9 of 43
5 4 3 2 1
 5 4 3 2 1

+VCCP Laptopblue +2.5VS

2
+2.5VS

0.01U_0402_16V7K

0.1U_0402_16V4Z
D18

0.1U_0402_16V4Z
RB751V_SOD323
1 1 1
1 1

C398

C100

C97
R299 +2.5VS
+2.5VS 2 2 2
D 10_0402_5% D
U22H
2

+VCCP H22 1 2
VCC_SYNC C400 close pin A38 close pin G41
AC14 0.1U_0402_16V4Z
VTT0
12/09 Modified AB14 VTT1 VCCTX_LVDS0 B30 +2.5VS
W14 VTT2 VCCTX_LVDS1 C30
V14 A30 +1.5VS_PCIE R63
VTT3 VCCTX_LVDS2 0_0805_5%
T14
R14
VTT4
VTT5 VCC3G0 AB41 W=60 mils 2 1 +1.5VS +1.5VS_DPLLA +1.5VS_DPLLB
P14 AJ41 L20 L2
VTT6 VCC3G1

10U_0805_10V4Z

10U_0805_10V4Z
N14 L41 1 MBK1608301YZF_0603 MBK1608301YZF_0603
VTT7 VCC3G2
M14 VTT8 VCC3G3 N41 1 1 2 1 +1.5VS 2 1 +1.5VS
L14 R41 C130 +
VTT9 VCC3G4

C103

C107

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AD13 VTT10 VCC3G5 V41
AC13 Y41 220U_D2_2VMR15 1 1
VTT11 VCC3G6 2 2 2
AB13 VTT12 CRTDAC: Route caps within 1 1

C73

C99
AA13 AC33 + C394 + C98
1 VTT13 VCCA_3GPLL +1.5VS_3GPLL
+1.5VS Y13 VTT14 VCCA_3GBG G41 +2.5VS 250mil of Alviso. Route FB
C89 + W13 H41 330U_D2E_2.5VM 330U_D2E_2.5VM
VTT15 VSSA_3GBG L1
within 3" of Calistoga 2 2 UMA@ 2 2 UMA@
V13 VTT16
2

220U_D2_2VMR15 U13 MBK1608301YZF_0603

D17 2 VTT17 +2.5VS_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 1 2 +2.5VS
R13 VTT19 VCCA_CRTDAC1 F21

0.022U_0402_16V7K

0.1U_0402_16V4Z
RB751V_SOD323 N13 G21
VTT20 VSSA_CRTDAC2
M13 1 1
1 1

VTT21
L13 VTT22 1

C69

C64
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA
R298 +3VS AA12 C39 + C187
VTT24 VCCA_DPLLB +1.5VS_DPLLB 2 2 +3VS_TVDACB +3VS +3VS_TVDACA +3VS
Y12 AF1 +1.5VS_HPLL L19 L17
10_0402_5% VTT25 VCCA_HPLL 220U_D2_4VM MBK1608301YZF_0603 MBK1608301YZF_0603
W12 VTT26 2 @
V12 2 1 2 1
2

VTT27

0.022U_0402_16V7K

0.022U_0402_16V7K
U12 VTT28 VCCA_LVDS A38 +2.5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z
T12 VTT29 VSSA_LVDS B39 1
C
R12 VTT30 1 1 1 1 C
P12 + C389
VTT31

C51

C59

C42

C43
12/09 Modified N12 VTT32 P O W E R VCCA_MPLL AF2 +1.5VS_MPLL
220U_D2_4VM
M12 VTT33 2 2 2 2 2 @
2.2U_0805_10V6K
4.7U_0805_10V4Z

L12 VTT34 VCCA_TVBG H20 +3VS_TVBG

R11 VTT35 VSSA_TVBG G20
1 1 P11 VTT36
C23

C54

N11 VTT37
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA
R10 VTT39 VCCA_TVDACA1 F19
2 2
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB
N10 VTT41 VCCA_TVDACB1 D20
M10 E20 +3VS_TVDACC L18 +3VS
VTT42 VCCA_TVDACC0 +3VS_TVDACC
P9 F20 MBK1608301YZF_0603
VTT43 VCCA_TVDACC1
N9 VTT44 2 1

0.022U_0402_16V7K
M9 VTT45

0.1U_0402_16V4Z
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2 1 1
N8 VTT48

C50
C391
M8 VTT49
P7 VTT50 VCCD_LVDS0 A28
N7 B28 2 2
VTT51 VCCD_LVDS1
M7 VTT52 VCCD_LVDS2 C28
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5VS_TVDAC
M6 VTT55 VCCDQ_TVDAC H19
0.47U_0603_16V4Z

MCH_A6 A6 VTT56
R5 VTT57 VCCHV0 A23 +3VS
1 P5 VTT58 VCCHV1 B23
C390

0.1U_0402_16V4Z

10U_0805_10V4Z

N5 VTT59 VCCHV2 B25

M5 VTT60 1 1
+3VS_TVBG +3VS
C396

P4 AK31 R285
2 VTT61 VCCAUX0
C392

N4 AF31 0_0603_5%
VTT62 VCCAUX1
M4 VTT63 VCCAUX2 AE31 2 1
2 2

0.022U_0402_16V7K
R3 AC31
VTT64 VCCAUX3
PCI-E/MEM/PSB PLL decoupling

0.1U_0402_16V4Z
B P3 VTT65 VCCAUX4 AL30 B
N3 VTT66 VCCAUX5 AK30 1 1
M3 VTT67 VCCAUX6 AJ30
+1.5VS

C60

C49
0.22U_0603_16V7K

R2 VTT68 VCCAUX7 AH30

P2 VTT69 VCCAUX8 AG30
2 2 +1.5VS_3GPLL R61 +1.5VS +1.5VS_TVDAC R292 +1.5VS
1 M2 VTT70 VCCAUX9 AF30
C93

0.1U_0402_16V4Z

MCH_D2 D2 AE30 0_0603_5% 0_0603_5%

VTT71 VCCAUX10
0.22U_0603_16V7K

AB1 VTT72 VCCAUX11 AD30 1 2 1 2 1

0.022U_0402_16V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z
R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C393

10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z
1 P1 VTT74 VCCAUX13 AG29
C15

N1 VTT75 VCCAUX14 AF29 1 1 1 1 1 1

2

C96

C65
C108

C395
M1 VTT76 VCCAUX15 AE29

C95

C35
0.47U_0603_16V4Z

VCCAUX16 AD29
2 @ @
1 VCCAUX17 AC29
2 2 2 2 2 2
VCCAUX18 AG28
C8

VCCAUX19 AF28
VCCAUX20 AE28
2 AH22
VCCAUX21
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
+1.5VS_MPLL R20 +1.5VS_HPLL R21
AF13 VCCAUX36 VCCAUX27 P19
AE13 P16 0_0603_5% 0_0603_5%
+1.5VS VCCAUX37 VCCAUX28
AF12 VCCAUX38 VCCAUX29 AH15 2 1 +1.5VS 2 1 +1.5VS
AE12 VCCAUX39 VCCAUX30 P15

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AD12 VCCAUX40 VCCAUX31 AH14

10U_0805_10V4Z

10U_0805_10V4Z
45mA Max. 45mA Max.
1 1 1 1

C10

C11
CALISTOGA_FCBGA1466~D

C6

C7
UMA@
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom HEL80/81 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 10 of 43
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

Laptopblue CFG[3:17] have internal pull up
CFG[19:18] have internal pull down
+VCCP U22F +1.5VS +VCCP U22G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_16V4Z

0.47U_0603_16V4Z
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C102

C101
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_16V7K

0.22U_0603_16V7K

0.22U_0603_16V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34

2 2 0 = Lane Reversal Enable
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)*
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
C47

C57

C22

AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 CFG6 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 10 = 1.05V*(Default)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG10 CFG18 01 = 1.5V
1U_0603_10V4Z

T25 W17 T30 AJ27

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
10U_0805_10V4Z

10U_0805_10V4Z

R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C19

C17

C88

C44
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C45

C94

C29

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25 Place near pin BA23
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_16V4Z
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1

C25
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22
C18 + R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22
220U_D2_2VMR15 2
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 VCC_NCTF53 VCCAUX_NCTF53 W15 L28 VCC53 VCC_SM53 AK22
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 VCC_NCTF55 VCCAUX_NCTF55 U15 N27 VCC55 VCC_SM55 AK21
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20
U20 VCC_NCTF57 VCCAUX_NCTF57 R15 L27 VCC57 VCC_SM57 BA19
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 VCC_NCTF59 N26 VCC59 VCC_SM59 AW19

10U_0805_10V4Z

10U_0805_10V4Z
AD19 AE27 L26 AV19 1 R36 1 2 @ 2.2K_0402_5%
VCC_NCTF60 VSS_NCTF0 VCC60 VCC_SM60 <7> CFG5
V19 VCC_NCTF61 VSS_NCTF1 AE26 N25 VCC61 VCC_SM61 AU19 1 1
U19 AE25 M25 AT19 + C72 R44 1 2 @ 2.2K_0402_5%
VCC_NCTF62 VSS_NCTF2 VCC62 VCC_SM62 <7> CFG7

C36

C76
T19 VCC_NCTF63 VSS_NCTF3 AE24 L25 VCC63 VCC_SM63 AR19
1 AD18 AE23 P24 AP19 220U_D2_4VM R40 1 2 @ 2.2K_0402_5%
VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2 @ <7> CFG9
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
C77 + AB18 AE21 M24 AJ19 R41 1 2 @ 2.2K_0402_5%
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66 <7> CFG10
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
220U_D2_2VMR15 Y18 AE19 AA23 AJ17 R39 1 2 @ 2.2K_0402_5%
2 VCC_NCTF68 VSS_NCTF8 VCC68 VCC_SM68 <7> CFG11
@ W18 AE18 Y23 AH17
VCC_NCTF69 VSS_NCTF9 VCC69 VCC_SM69 R37
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16 <7> CFG12 1 2 @ 2.2K_0402_5%
B B
U18 VCC_NCTF71 VSS_NCTF11 Y17 N23 VCC71 VCC_SM71 AH16
T18 U17 M23 BA15 R42 1 2 @ 2.2K_0402_5%
VCC_NCTF72 VSS_NCTF12 VCC72 VCC_SM72 <7> CFG13
L23 VCC73 VCC_SM73 AY15
+VCCP

0.47U_0603_16V4Z
AC22 AW15 R35 1 2 @ 2.2K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG16
M19 VCC100 AB22 VCC75 VCC_SM75 AV15
L19 VCC101 VCC_SM100 AR6 Y22 VCC76 VCC_SM76 AU15 1

C91
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 AJ6 L22 AJ13 +3VS
VCC106 VCC_SM105 VCC81 VCC_SM81
M17 VCC107 VCC_SM106 AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 AA21 VCC83 VCC_SM83 AK12
M16 W21 AJ12 R52 1 2 @ 1K_0402_5%
VCC109 VCC84 VCC_SM84 <7> CFG18
0.47U_0603_16V4Z

0.47U_0603_16V4Z

L16 N21 AH12 R54 1 2 @ 1K_0402_5%

VCC110 VCC85 VCC_SM85 <7> CFG19
M21 AG12 Place near pin BA15 R55 1 2 @ 1K_0402_5%
VCC86 VCC_SM86 <7> CFG20
1 1 L21 VCC87 VCC_SM87 AK11
C12

C13

CALISTOGA_FCBGA1466~D AC20 BA8

VCC88 VCC_SM88
UMA@ AB20 VCC89 VCC_SM89 AY8
Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A
UMA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80/81 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 11 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue
U22I U22J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23 UMA@
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A
UMA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80/81 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 12 of 43
5 4 3 2 1
 5 4 3 2 1

<8> DDR_A_DQS#[0..7] Laptopblue +1.8V

+1.8V +1.8V

1
<8> DDR_A_D[0..63] JP3
R92 +DDR_MCH_REF1 1 2
VREF VSS DDR_A_D6
<8> DDR_A_DM[0..7] 3 VSS DQ4 4
1K_0402_1% DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 8

2
DQ1 VSS

2.2U_0805_10V6K

0.1U_0402_16V4Z
+DDR_MCH_REF1 1 1 9 10 DDR_A_DM0
<14> +DDR_MCH_REF1 VSS DM0
C171 C158 DDR_A_DQS#0 11 12
<8> DDR_A_MA[0..13] DQS0# VSS

1
DDR_A_DQS0 13 14 DDR_A_D5
R87 DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
2 2 DDR_A_D2 17 DQ2 VSS 18
D 1K_0402_1% DDR_A_D3 DDR_A_D13 D
Layout Note: 19 DQ3 DQ12 20
21 22 DDR_A_D12
+DDR_MCH_REF

2
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: trace width and DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
spacing is 20/20. 27 VSS VSS 28
Place near JP41 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D9 35 36 DDR_A_D11
DDR_A_D15 DQ10 DQ14 DDR_A_D10
37 DQ11 DQ15 38
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,14>
2.2U_0805_10V6K

2.2U_0805_10V6K

2.2U_0805_10V6K

2.2U_0805_10V6K

2.2U_0805_10V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C84

C83

C27

C90

C26

C85

C55

C41

C81
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
<7> M_ODT1 M_ODT1 119 120
NC/ODT1 NC
121 VSS VSS 122
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D39

DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C70

C63

C56

C46

C78

C31

C38

C52

C61

C75

C40

C67

C34

133 134 DDR_A_D34

DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
+0.9VS DDR_A_D48 DQ48 DQ52 DDR_A_D53
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
RP1 RP2 163 164 M_CLK_DDR1
closely JP41,all NC,TEST CK1 M_CLK_DDR1 <7>
DDR_A_WE# 1 8 8 1 DDR_A_RAS# 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_CAS# 2 7 7 2 DDR_CS0_DIMMA# trace length Max=1.5" DDR_A_DQS#6 167 168
DDR_CS1_DIMMA# M_ODT0 DDR_A_DQS6 DQS6# VSS DDR_A_DM6
3 6 6 3 169 DQS6 DM6 170
M_ODT1 4 5 5 4 DDR_A_MA13 171 172
DDR_A_D54 VSS VSS DDR_A_D51
173 DQ50 DQ54 174
56_0804_8P4R_5% 56_0804_8P4R_5% DDR_A_D50 175 176 DDR_A_D55
DQ51 DQ55
177 VSS VSS 178
RP6 DDR_A_D61 179 180 DDR_A_D57
56_0402_5% DDR_A_BS#1 DDR_A_D60 DQ56 DQ60 DDR_A_D56
5 4 181 DQ57 DQ61 182
DDR_A_BS#0 R43 1 2 6 3 DDR_A_MA0 183 184
DDR_A_MA2 DDR_A_DM7 VSS VSS DDR_A_DQS#7
7 2 185 DM7 DQS7# 186
DDR_A_MA10 R46 1 2 8 1 DDR_A_MA4 187 188 DDR_A_DQS7
56_0402_5% DDR_A_D59 VSS DQS7
189 DQ58 VSS 190
56_0804_8P4R_5% DDR_A_D58 191 192 DDR_A_D62
DQ59 DQ62 DDR_A_D63
193 VSS DQ63 194
RP7 RP9 CLK_SMBDATA 195 196
<14,15> CLK_SMBDATA SDA VSS
DDR_A_MA1 4 5 5 4 DDR_A_MA6 CLK_SMBCLK 197 198
<14,15> CLK_SMBCLK SCL SA0
DDR_A_MA3 3 6 6 3 DDR_A_MA7 199 200
+3VS VDDSPD SA1
DDR_A_MA5 2 7 7 2 DDR_A_MA11

1
DDR_A_MA8 1 8 8 1 DDR_CKE1_DIMMA
FOX_ASOA426-M2RN-7F
A 56_0804_8P4R_5% 56_0804_8P4R_5% R18 R16 A
ME@
RP10 11/9 Modify pn to SP070006V00 10K_0402_5% 10K_0402_5%
SO-DIMM A

2
DDR_A_MA9 4 5
DDR_A_MA12 3 6
DDR_A_BS#2 2 7
DDR_CKE0_DIMMA 1 8 Top side
56_0804_8P4R_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 13 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue
+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
+DDR_MCH_REF1
+DDR_MCH_REF1 <13>
<8> DDR_B_DM[0..7]
JP4
<8> DDR_B_DQS[0..7] 1 VREF VSS 2

2.2U_0805_10V6K

0.1U_0402_16V4Z
3 4 DDR_B_D5 1 1
VSS DQ4

C172

C159
DDR_B_D0 5 6 DDR_B_D4
<8> DDR_B_MA[0..13] DQ0 DQ5
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP42 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
DDR_B_D17 43 44 DDR_B_D21
DQ16 DQ20
2.2U_0805_10V6K

2.2U_0805_10V6K

2.2U_0805_10V6K

2.2U_0805_10V6K

2.2U_0805_10V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 DDR_B_D20 45 46 DDR_B_D16
DQ17 DQ21
C28

C21

C87

C92

C20

C66

C71

C86

C30
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,13>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
<8> DDR_B_BS#2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9VS 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120

<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C68

C79

C74

C32

C39

C53

C80

C58

C48

C82

C62

C37

C33

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9VS 163 164 M_CLK_DDR2
closely JP42,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP3 RP4 trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_CAS# 8 1 4 5 DDR_B_MA13 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_WE# M_ODT2 DQS6 DM6
7 2 3 6 171 VSS VSS 172
DDR_CS3_DIMMB# 6 3 2 7 DDR_CS2_DIMMB# DDR_B_D51 173 174 DDR_B_D54
M_ODT3 DDR_B_RAS# DDR_B_D50 DQ50 DQ54 DDR_B_D55
5 4 1 8 175 DQ51 DQ55 176
177 VSS VSS 178
56_0804_8P4R_5% 56_0804_8P4R_5% DDR_B_D56 179 180 DDR_B_D60
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 DQ57 DQ61 182
RP5 183 184
DDR_B_BS#1 DDR_B_DM7 VSS VSS DDR_B_DQS#7
4 5 185 DM7 DQS7# 186
DDR_B_BS#0 R48 1 2 3 6 DDR_B_MA0 187 188 DDR_B_DQS7
56_0402_5% DDR_B_MA2 DDR_B_D59 VSS DQS7
2 7 189 DQ58 VSS 190
DDR_B_MA10 R45 1 2 1 8 DDR_B_MA4 DDR_B_D58 191 192 DDR_B_D62
DQ59 DQ62 DDR_B_D63
193 VSS DQ63 194
56_0804_8P4R_5% CLK_SMBDATA 195 196
<13,15> CLK_SMBDATA SDA VSS R17
CLK_SMBCLK 197 198
<13,15> CLK_SMBCLK SCL SAO
RP8 RP11 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_MA1 5 4 4 5 DDR_B_MA7

1
DDR_B_MA3 6 3 3 6 DDR_B_MA11 10K_0402_5%
A DDR_B_MA5 DDR_B_MA6 P-TWO_A5692B-A0G16-P A
7 2 2 7
DDR_B_MA9 8 1 1 8 DDR_CKE3_DIMMB ME@ R19

56_0804_8P4R_5% 56_0804_8P4R_5% SO-DIMM B 10K_0402_5%

2
RP12 11/9 Modify pn to SP07000BY00
DDR_CKE2_DIMMB 8 1
DDR_B_BS#2 7 2
DDR_B_MA12
DDR_B_MA8
6 3
Security Classification Compal Secret Data Compal Electronics, Inc.
5 4 Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

56_0804_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 14 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue
+3VS +CK_VDD_MAIN1
FSLC FSLB FSLA CPU SRC PCI

1
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz R479 R468
+3VS 1
R208
2
0_0805_5% 1 1 1 1 1 1 1
2.2K_0402_5% 2.2K_0402_5% C285 C263 C264 C494 C278 C302 C301
0 0 1 133 100 33.3
Q22 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2
2N7002_SOT23 2 2 2 2 2 2 2
0 1 1 166 100 33.3
CLK_SMBDATA

S
<20,27,35> ICH_SMBDATA 1 3

Table : ICS954306 +CK_VDD_MAIN2

G
2
D D
FSB Frequency Selet: +3VS +3VS 1 2 1 2 +CK_VDD_REF C499 2 1 33P_0402_50V8J
R399 0_0805_5% 1 1 1 R397 1_0603_5%

1
C490 C507 C506

2
2 +CK_VDD_48 Y5

G
Stuff CLK_Ra CLK_Rb CLK_Rc 1
CPU Driven 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R482 2.2_0603_5% CLK_XTAL_IN 14.31818MHz_20P_1BX14318BE1A
CLK_SMBCLK 2 2 2
<20,27,35> ICH_SMBCLK 1 3

2
CLK_XTAL_OUT C503 2 1 33P_0402_50V8J
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf

S
Q21
Stuff CLK_Rd CLK_Re CLK_Rf 2N7002_SOT23 R220 2.2_0603_5%
533MHz U30 1 2 +3VS
+CK_VDD_MAIN1
1 1
No Stuff CLK_Ra CLK_Rb CLK_Rc C304 C313 Place crystal within
1 VDDSRC VDDA 7 500 mils of CK410
49 0.1U_0402_16V4Z 10U_0805_10V4Z
VDDSRC 2 2
Stuff CLK_Rd CLK_Rf 54 8
65
VDDSRC
VDDSRC
GNDA Place near U4
667MHz Place these components
No Stuff CLK_Ra CLK_Rb CLK_Rc 25 H_STP_PCI#
PCI_SRC_STOP# H_STP_PCI# <20>
30
CLK_Re 36
VDDPCI
VDDPCI CPU_STOP# 24 H_STP_CPU#
H_STP_CPU# <20>
near each pin within 40
+VCCP
12 VDDCPU MCH_BCLK CLK_MCH_BCLK
mils.
CPUCLKT1LP 11 1 2 CLK_MCH_BCLK <7>
1 2 +CK_VDD_REF 18 R476 0_0402_5%
C505 0.1U_0402_16V4Z VDDREF MCH_BCLK# 1 CLK_MCH_BCLK#
CPUCLKC1LP 10 2 CLK_MCH_BCLK# <7>
2

1 2 +CK_VDD_48 40 R475 0_0402_5% CLK_CPU_BCLK 2 1

R398 C492 0.1U_0402_16V4Z VDD48 R487 @ 49.9_0402_1%
@ 56_0402_5% 14 CPU_BCLK 1 2 CLK_CPU_BCLK CLK_CPU_BCLK# 2 1
CPUCLKT0LP CLK_CPU_BCLK <4>
R407 CLK_Rd CLK_XTAL_IN 20 R478 0_0402_5% R486 @ 49.9_0402_1%
8.2K_0402_5% X1 CPU_BCLK# 1 CLK_CPU_BCLK#
13 2 CLK_CPU_BCLK# <4>
1

FSA 2 CPUCLKC0LP R477 0_0402_5% CLK_MCH_BCLK

1 1 2 MCH_CLKSEL0 <7> 2 1
C CLK_XTAL_OUT R485 @ 49.9_0402_1% C
19 X2
1 2 R395 6 CLK_MCH_BCLK# 2 1
<5> CPU_BSEL0 CPUCLKT2_ITP/SRCCLKT10LP
R393 1K_0402_5% <20> CLK_48M_ICH CLK_48M_ICH R4152 1 12_0402_5% R484 @ 49.9_0402_1%
0_0402_5% <23> CLK_SD_48M CLK_SD_48M 2 1 FSA 41 5
USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1

CLK_Ra R400 12_0402_5%

R394 FSB 45 FSLB/TEST_MODE/24Mhz PCIE_VGA CLK_PCIE_VGA CLK_MCH_SSCDREFCLK
SRCCLKT9LP 3 1 2 CLK_PCIE_VGA <17> 1 2
@ 1K_0402_5% CLK_14M_ICH 2 1 CLKREF1 23 R473 VGA@ 0_0402_5% R406 @ 49.9_0402_1%
<20> CLK_14M_ICH REF0/FSLC/TEST_SEL
R461 33_0402_5% 2 PCIE_VGA# 1 2 CLK_PCIE_VGA# CLK_MCH_SSCDREFCLK#
1 2
CLK_PCIE_VGA# <17>
2

SRCCLKC9LP R474 VGA@ 0_0402_5% R405 @ 49.9_0402_1%

33_0402_5% 2 1 R431 PCI_1394 34 72 CLK_MCH_3GPLL 1 2
<25> CLK_PCI_1394 PCICLK4/FCTSEL1 CLKREQ9# R471 @ 49.9_0402_1%
+VCCP 12_0402_5% 2 1 R435 PCI_LPC 33 70 MCH_3GPLL 1 2 CLK_MCH_3GPLL CLK_MCH_3GPLL# 1 2
<31> CLK_PCI_LPC SEL_48M/PCICLK3 SRCCLKT8LP CLK_MCH_3GPLL <7>
12_0402_5% 2 1 R437 R472 0_0402_5% R469 @ 49.9_0402_1%
<35> CLK_PCI_TPM
<23> CLK_PCI_PCM 33_0402_5% 2 1 R445 PCI_PCM 32 69 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_PCIE_VGA 1 2
SEL_24M/PCICLK2 SRCCLKC8LP CLK_MCH_3GPLL# <7>
2

R470 0_0402_5% R480 @ 49.9_0402_1%

R158 33_0402_5% 2 1 R453 PCI_DB 27 71 CLKREQ8# 2 1 MCH_CLKREQ# CLK_PCIE_VGA# 1 2
<30> CLK_PCI_DB SEL_PCI6/PCICLK1 CLKREQ8# MCH_CLKREQ# <7>
R214 0_0402_5% R481 @ 49.9_0402_1%
@ 1K_0402_5% 66 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_ICH 1 2
SRCCLKT7LP CLK_PCIE_SATA <19>
33_0402_5% 2 1 R464 PCI_SIO 22 R462 0_0402_5% R433 @ 49.9_0402_1%
<30> CLK_14M_SIO
1

FSB SEL_PCI5/REF1 PCIE_SATA# 1 CLK_PCIE_SATA# CLK_PCIE_ICH#

1 2 MCH_CLKSEL1 <7> SRCCLKC7LP 67 2 CLK_PCIE_SATA# <19> 1 2
R467 0_0402_5% R442 @ 49.9_0402_1%
1 2 R157 <7> CLK_MCH_DREFCLK CLK_MCH_DREFCLK 1 2 MCH_DREFCLK 43 38 SATAREQ# CLK_MCH_DREFCLK 1 2
<5> CPU_BSEL1 DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1 SATAREQ# <20>
R154 1K_0402_5% R409 UMA@ 0_0402_5% R402 @ 49.9_0402_1%
0_0402_5% <7> CLK_MCH_DREFCLK# CLK_MCH_DREFCLK# 1 2 MCH_DREFCLK# 44 63 CLK_MCH_DREFCLK#1 2
DOTC_96MHz/27MHz_spread SRCCLKT6LP
1

CLK_Rb R408 UMA@ 0_0402_5% R401 @ 49.9_0402_1%

R156 64 CLK_PCIE_SATA 1 2
CLK_PCI_ICH SRCCLKC6LP
<18> CLK_PCI_ICH 2 1 PCI_ICH 37 ITP_EN/PCICLK_F0
R463 @ 49.9_0402_1%
@ 1K_0402_5% 33_0402_5% R423 62 CLK_PCIE_SATA# 1 2
CLKREQ6# R466 @ 49.9_0402_1%
CLK_Re
2

+3VS R410 1 2 10K_0402_5% CLK_ENABLE# 39 60 PCIE_LAN 1 2 CLK_PCIE_LAN CLK_PCIE_NC1 2 1

VTT_PWRGD#/PD SRCCLKT5LP CLK_PCIE_LAN <26>
R451 0_0402_5% R421 @ 49.9_0402_1%
B PCIE_LAN# B
<42> CLK_ENABLE# SRCCLKC5LP 61 1 2 CLK_PCIE_LAN# CLK_PCIE_LAN# <26>
CLK_PCIE_NC1# 2 1
+VCCP R458 0_0402_5% R428 @ 49.9_0402_1%
1

D CLK_SMBCLK CLKREQ_LAN# 2 CLK_PCIE_LAN

<13,14> CLK_SMBCLK 16 SMBCLK CLKREQ5#/PCICLK6 29 1 2 1
2 R447 10K_0402_5% R450 @ 49.9_0402_1%
<20,31,42> VGATE
2

G 58 PCIE_ICH 1 2 CLK_PCIE_ICH CLK_PCIE_LAN# 2 1

SRCCLKT4LP CLK_PCIE_ICH <20>
R430 Q5 S R434 0_0402_5% R457 @ 49.9_0402_1%
3

2N7002_SOT23 CLK_SMBDATA 17 59 PCIE_ICH# 1 2 CLK_PCIE_ICH# CLK_PCIE_MCARD1 1 2

<13,14> CLK_SMBDATA SMBDAT SRCCLKC4LP CLK_PCIE_ICH# <20>
R448 @ 1K_0402_5% R441 0_0402_5% R404 @ 49.9_0402_1%
8.2K_0402_5% 57 CLKREQ_ICH# 2 1 CLK_PCIE_MCARD1# 1 2
1

CLKREF1 2 CLKREQ4# R170 10K_0402_5% R403 @ 49.9_0402_1%

1 1 2 MCH_CLKSEL2 <7>
0_0402_5% 1 2 R483 CLKIREF 9 55 PCIE_NC1 1 2 CLK_PCIE_NC1
GND SRCCLKT3LP CLK_PCIE_NC1 <35>
1 2 R456 R422 0_0402_5%
<5> CPU_BSEL2
R449 1K_0402_5% 4 56 PCIE_NC1# 1 2 CLK_PCIE_NC1#
GNDSRC SRCCLKC3LP CLK_PCIE_NC1# <35>
0_0402_5% R427 0_0402_5%
1

CLK_Rc 15 28 CLKREQ_NC#
+3VS +3VS +3VS GNDCPU CLKREQ3#/PCICLK5 CLKREQ_NC# <35>
R439
ITP PCI6 PCI5 21 52 PCIE_MCARD1 1 2 CLK_PCIE_MCARD1
@ 1K_0402_5% GNDREF SRCCLKT2LP CLK_PCIE_MCARD1 <27>
R412 0_0402_5%
1

PCIE_MCARD1# 1 2 CLK_PCIE_MCARD1# +3VS

CLK_Rf 31 53 CLK_PCIE_MCARD1# <27>
2

R419 R429 R455 GNDPCI SRCCLKC2LP R411 0_0402_5%

35 26 CLKREQ_MCARD1# CLKREQ8# 2 1
GNDPCI CLKREQ2# CLKREQ_MCARD1# <27>
10K_0402_5% @ 10K_0402_5% @ 10K_0402_5% R213 10K_0402_5%
42 50 SATAREQ# 2 1
2

PCI_ICH PCI_DB PCI_SIO GND48 SRCCLKT1LP R417 10K_0402_5%

68 51 CLKREQ_NC# 2 1
GNDSRC SRCCLKC1LP
1

R189 10K_0402_5%
R418 R438 R454 46 CLKREQ_MCARD1# 2 1
CLKREQ1# R193 10K_0402_5%
73 THRM_PAD
@ 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5% 74 47 SSCDREFCLK 1 2 CLK_MCH_SSCDREFCLK
THRM_PAD LCD100/96/SRC0_TLP CLK_MCH_SSCDREFCLK <7>
75 R414 UMA@ 0_0402_5%
2

+3VS THRM_PAD SSCDREFCLK# 1

76 THRM_PAD LCD100/96/SRC0_CLP 48 2 CLK_MCH_SSCDREFCLK# CLK_MCH_SSCDREFCLK# <7>
R413 UMA@ 0_0402_5%
A A
1

PCI_1394 = FCTSEL1
R425 PCI_DB=SEL_PCI6 ICS9LPR325AKLFT_MLF72
FCTSEL1 ICS9LPR325CKLFT_MLF72: SA00000RE20
@ 10K_0402_5% PIN43 PIN44 PIN47 PIN48
(PIN34) PCI_DB PIN27 SLG8LP465VTR: SA00000TS00 2005/11/8 modify footprint to ICS954305DKLFT_MLF72 for Thermal Pad use
2

PCI_1394
0 CLKREQ5 Security Classification Compal Secret Data Compal Electronics, Inc.
1

0 DOT96T DOT96C 96/100M_T 96/100M_C

R424 1 PCICLK6 2005/03/10 2006/03/10 Title
Issued Date Deciphered Date
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
1 27Mout 27MSSout SRCT0 SRCC0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 15 of 43
5 4 3 2 1
 A B C D E

TV-OUT Conn.
Laptopblue UMA LCD / PANEL Conn.
VGA I/O PORT Conn.
JP42
JP6 LVDSA0- 1 2 LVDSB0-
<9> LVDSA0- 1 2 LVDSB0- <9>
R65 2 VGA@ 1 0_0402_5% LUMA VGA_DDC_DAT 1 2 LVDSA0+ 3 4 LVDSB0+
<17> CARD_LUMA 1 2 <9> LVDSA0+ 3 4 LVDSB0+ <9>
VGA_DDC_CLK 3 4 CRMA 5 6
JVGA_HS 3 4 LVDSA1- 5 6 LVDSB1-
5 5 6 6 <9> LVDSA1- 7 7 8 8 LVDSB1- <9>
R64 2 VGA@ 1 0_0402_5% CRMA JVGA_VS 7 8 LUMA <9> LVDSA1+ LVDSA1+ 9 10 LVDSB1+
<17> CARD_CRMA 7 8 9 10 LVDSB1+ <9>
9 9 10 10 11 11 12 12
1 RED COMP LVDSA2- LVDSB2- 1
11 11 12 12 <9> LVDSA2- 13 13 14 14
R66 LVDSB2- <9>
<17> CARD_COMP 2 VGA@ 1 0_0402_5% COMP 13 13 14 14 <9> LVDSA2+
LVDSA2+ 15 15 16 16 LVDSB2+
LVDSB2+ <9>

150_0402_1%
GREEN 15 16 +3VS 17 18
15 16 17 18

1
150_0402_1%

150_0402_1%
17 18 +5VS LVDSAC- 19 20 LVDSBC-
17 18 <9> LVDSAC- 19 20 LVDSBC- <9>
BLUE 19 20 LVDSAC+ 21 22 LVDSBC+
19 20 <9> LVDSAC+ 21 22 LVDSBC+ <9>

R9
2 R10

2 R11
R301 2 UMA@ 1 0_0402_5% 23 24
<9> TV_LUMA 23 24
21 22 +LCDVDD 2 1 25 26 EDID_DAT_LCD
G1 G2 25 26 EDID_DAT_LCD <9>
R302 2 UMA@ 1 0_0402_5% @ @ @ 27 28 EDID_CLK_LCD
<9> TV_CRMA EDID_CLK_LCD <9>

2
ACES_87216-2016 L37 27 28
29 29 30 30 +3VS
R300 2 UMA@ 1 0_0402_5% UMA@ KC FBM-L11-201209-221LMAT_0805
<9> TV_COMPS
31 GND1
(60 MIL) 32 GND2
Pop when with internal graphics
ACES_88242-3001

Reverse pin 1 to 29

+LCDVDD +5VALW

+LCDVDD Q13 +3VS

CRT Conn. 2/09 Add for Compliance Engineering request

2
UMA@
R278 R281 SI2301BDS_SOT23

300_0402_5% 100K_0402_5%

S
1 3

D
UMA@ UMA@

1 2

1
R74 2 VGA@ 1 0_0402_5% 1 2 RED
<17> CARD_VGA_R D
L39 FCM1608C-121T_0603

G
2
Q14 2
R76 2 VGA@ 1 0_0402_5% 1 2 GREEN 2N7002_SOT23 G
<17> CARD_VGA_G
L40 FCM1608C-121T_0603 UMA@ S 1 1 1 1

3
2 C383 C381 C382 C384 2
R78 2 VGA@ 1 0_0402_5% 1 2 BLUE UMA@
<17> CARD_VGA_B
L41 FCM1608C-121T_0603 0.047U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
UMA@ 2 UMA@ 2 2 UMA@ 2
1

1
D
150_0402_1%

150_0402_1%

150_0402_1%

8P_0402_50V8K

8P_0402_50V8K

8P_0402_50V8K

8P_0402_50V8K

8P_0402_50V8K

8P_0402_50V8K
C537

C538

C539
C3

C2

C1
1 1 1 1 1 1 R282
R73 2 UMA@ 1 0_0402_5% <9> GMCH_LVDDEN 2 1 2 Q15
<9> CRT_R
R2

R3

R4

UMA@ 0_0402_5% G 2N7002_SOT23 4.7U_0805_10V4Z

@ @ @ @ @ @ S UMA@

3
R75 2 2 2 2 2 2
<9> CRT_G 2 UMA@ 1 0_0402_5% @ @ @
2

R77 2 UMA@ 1 0_0402_5%

<9> CRT_B

Pop when with internal graphics

INVERTER Conn.
D12 JP40
+3VS +3VS RB751V_SOD323
1
1 2 +5VS 2
+3VS <31> INVT_PWM 3
DISPOFF#
+3VS 4
<31> DAC_BRIG 5
1

1
INVPWR_B+ 6
R14 R13 R280 R279
7
2
G

4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% MOLEX_53780-0790

2

3 R89 3
<17> CARD_DDCDATA 2 VGA@ 1 0_0402_5% 3 1 VGA_DDC_DAT
S

2
G

Q1 +3VS
2N7002_SOT23
R88 2 VGA@ 1 0_0402_5% 3 1 VGA_DDC_CLK
<17> CARD_DDCCLK

2
S

Q2 R283
R83 1 UMA@ 2 0_0402_5% 2N7002_SOT23
<9> 3VDDCDA +5VS
R86 1 UMA@ 2 0_0402_5% 4.7K_0402_5%
<9> 3VDDCCL
D13

1
RB751V_SOD323
1 2 1 2 DISPOFF#
10K_0402_5% R1 <31> BKOFF#
1
C5 <9> GMCH_ENBKL 2 1 ENBKL
ENBKL <31>
R57 UMA@ 0_0402_5%

2
0.1U_0402_16V4Z <17> G7X_ENBKL 2 1
2 R94 VGA@ 0_0402_5% R284
5

U1
100K_0402_5%
P

OE#

R91 2 VGA@ 1 0_0402_5% HSYNC_R 2 4 1 2 JVGA_HS

<17> CARD_HSYNC

1
A Y R12 39_0402_5%
G

R90 2 VGA@ 1 0_0402_5% VSYNC_R +5VS SN74AHCT1G125DCKR_SC70-5

<17> CARD_VSYNC
3

1
R85 1 2 UMA@ 0_0402_5% C4 B+ INVPWR_B+ C387
<9> CRT_HSYNC
L16 0.1U_0603_50V4Z
0.1U_0402_16V4Z 1 2
5

R84 2
<9> CRT_VSYNC 1 2 UMA@ 0_0402_5% U2 KC FBM-L11-201209-221LMAT_0805
L15
P

OE#

2 4 1 2 JVGA_VS 1 2 2 1
4 A Y R15 39_0402_5% @ KC FBM-L11-201209-221LMAT_0805 C388 4
Pop when with internal graphics
G

68P_0402_50V8K
SN74AHCT1G125DCKR_SC70-5
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 16 of 43
A B C D E
 5 4 3 2 1

Laptopblue

D D
MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V

PEG_M_TXP[0..15]
PEG_M_TXP[0..15] <9>
PEG_M_TXN[0..15]
PEG_M_TXN[0..15] <9>

PEG_RXP[0..15]
PEG_RXP[0..15] <9>
JP7 JP8
1 41 1 41 PEG_RXN[0..15]
1 41 1 41 PEG_RXN[0..15] <9>
PEG_M_TXP1 2 42 PEG_RXP1 PEG_M_TXP0 2 42 PEG_RXP0
PEG_M_TXN1 2 42 PEG_RXN1 PEG_M_TXN0 2 42 PEG_RXN0
3 3 43 43 3 3 43 43
4 4 44 44 4 4 44 44
PEG_M_TXP3 5 45 PEG_RXP3 PEG_M_TXP2 5 45 PEG_RXP2
PEG_M_TXN3 5 45 PEG_RXN3 PEG_M_TXN2 5 45 PEG_RXN2
6 6 46 46 6 6 46 46
7 7 47 47 7 7 47 47
PEG_M_TXP5 8 48 PEG_RXP5 PEG_M_TXP4 8 48 PEG_RXP4
PEG_M_TXN5 8 48 PEG_RXN5 PEG_M_TXN4 8 48 PEG_RXN4
9 9 49 49 9 9 49 49
10 10 50 50 10 10 50 50
PEG_M_TXP7 11 51 PEG_RXP7 PEG_M_TXP6 11 51 PEG_RXP6
PEG_M_TXN7 11 51 PEG_RXN7 PEG_M_TXN6 11 51 PEG_RXN6
12 12 52 52 12 12 52 52
13 13 53 53 13 13 53 53
C PEG_M_TXP9 PEG_RXP9 PEG_M_TXP8 PEG_RXP8 C
14 14 54 54 14 14 54 54
PEG_M_TXN9 15 55 PEG_RXN9 PEG_M_TXN8 15 55 PEG_RXN8
15 55 15 55
16 16 56 56 16 16 56 56
PEG_M_TXP11 17 57 PEG_RXP11 PEG_M_TXP10 17 57 PEG_RXP10 +5VS +2.5VS
PEG_M_TXN11 17 57 PEG_RXN11 PEG_M_TXN10 17 57 PEG_RXN10
18 18 58 58 18 18 58 58
19 19 59 59 19 19 59 59
PEG_M_TXP13 20 60 PEG_RXP13 PEG_M_TXP12 20 60 PEG_RXP12
20 60 20 60

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PEG_M_TXN13 21 61 PEG_RXN13 PEG_M_TXN12 21 61 PEG_RXN12
21 61 21 61

C156

C157

C132

C133
22 22 62 62 22 22 62 62 2 2 2 2
PEG_M_TXP15 23 63 PEG_RXP15 PEG_M_TXP14 23 63 PEG_RXP14
PEG_M_TXN15 23 63 PEG_RXN15 PEG_M_TXN14 23 63 PEG_RXN14
24 24 64 64 24 24 64 64
25 25 65 65 25 25 65 65
+1.8VS SUSP# 1 1 1 1
+3VS 26 26 66 66 +5VS <15> CLK_PCIE_VGA 26 26 66 66 SUSP# <31,32,33,35,40,41>
+1.5VS 27 67 27 67 G7X_THER_ALERT# VGA@ VGA@ VGA@ VGA@
27 67 <15> CLK_PCIE_VGA# 27 67 G7X_THER_ALERT# <20>
28 28 68 68 28 28 68 68
29 29 69 69 <16> CARD_DDCCLK 29 29 69 69
+2.5VS 30 70 30 70
30 70 <16> CARD_DDCDATA 30 70 G7X_ENBKL <16>
31 71 31 71 PLT_RST#
31 71 31 71 PLT_RST# <7,18,20,22,26,27,31,35>
32 32 72 72 <16> CARD_VSYNC 32 32 72 72
33 33 73 73 33 33 73 73
34 34 74 74 <16> CARD_HSYNC 34 34 74 74
35 35 75 75 2 1 B+ 35 35 75 75
36 76 36 76 +3VS
36 76 <16> CARD_VGA_R 36 76 CARD_COMP <16>
37 77 L3 VGA@ KC FBM-L11-201209-221LMAT_0805 37 77
37 77 37 77
38 38 78 78 <16> CARD_VGA_G 38 38 78 78 CARD_LUMA <16>
39 39 79 79 39 39 79 79

0.047U_0402_16V4Z

0.047U_0402_16V4Z
40 40 80 80 <16> CARD_VGA_B 40 40 80 80 CARD_CRMA <16>
ACES_88363-08001 ACES_88363-08001 1 1

C142

C143
B 2 2 B
VGA@ VGA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA/B connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 17 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue

D D

+3VS

R343 1 2 8.2K_0402_5% PCI_DEVSEL#

R341 1 2 8.2K_0402_5% PCI_STOP#

R342 1 2 8.2K_0402_5% PCI_TRDY#

R337 1 2 8.2K_0402_5% PCI_FRAME# <23,25,30> PCI_AD[0..31] U4B

PCI_AD0 E18 D7 PCI_REQ0#
AD0 REQ0# PCI_REQ0# <25>
R346 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 E7 PCI_GNT0#
AD1 GNT0# PCI_GNT0# <25>
PCI_AD2 A16 C16 PCI_REQ1#
R361 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16
PCI_AD4 AD3 GNT1# PCI_REQ2#
E16 AD4 REQ2# C17 PCI_REQ2# <23>
R347 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT2#
AD5 GNT2# PCI_GNT2# <23>
PCI_AD6 E17 E13 PCI_REQ3#
R350 1 PCI_PERR# PCI_AD7 AD6 REQ3#
2 8.2K_0402_5% A17 AD7 GNT3# F13
PCI_AD8 A15 A13 PCI_REQ4#
R345 1 PCI_REQ4# PCI_AD9 AD8 REQ4# / GPIO22 +3VS
2 8.2K_0402_5% C14 AD9 GNT4# / GPIO48 A14
PCI_AD10 E14 C8 PCI_REQ5#
R344 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% PCI_REQ3# PCI_AD11 D14 AD11 GPIO17 / GNT5# D8

5
PCI_AD12 B12
PCI_AD13 AD12 PCI_CBE#0 PCI_PCIRST#
C13 B15 2

P
AD13 C/BE0# PCI_CBE#0 <23,25,30> B
PCI_AD14 G15 C12 PCI_CBE#1 4 PCI_RST#
AD14 C/BE1# PCI_CBE#1 <23,25,30> Y U27 PCI_RST# <23,25,30>
PCI_AD15 G13 D12 PCI_CBE#2 1
AD15 C/BE2# PCI_CBE#2 <23,25,30> A

G
PCI_AD16 E12 C15 PCI_CBE#3 @
AD16 C/BE3# PCI_CBE#3 <23,25,30>
PCI_AD17 C11 NC7SZ08P5X_NL_SC70-5

3
PCI_AD18 AD17 PCI _IRDY#
D11 AD18 IRDY# A7 PCI_IRDY# <23,25>
C PCI_AD19 PCI_PAR C
A11 AD19 PAR E10 PCI_PAR <23,25>
PCI_AD20 A10 B18 PCI_PCIRST# 2 1
PCI_AD21 AD20 PCIRST# PCI_DEVSEL# R332 0_0402_5%
F11 AD21 DEVSEL# A12 PCI_DEVSEL# <23,25>
+3VS PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# <23,25> +3VS
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# <23>
R375 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP#
AD25 STOP# PCI_STOP# <23,25>

5
PCI_AD26 A8 F14 PCI_TRDY#
AD26 TRDY# PCI_TRDY# <23,25,30>
R377 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME# PCI_PLTRST# 2

P
AD27 FRAME# PCI_FRAME# <23,25,30> B
PCI_AD28 C7 4 PLT_RST#
AD28 Y U26 PLT_RST# <7,17,20,22,26,27,31,35>
R371 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD29 B6 C26 PCI_PLTRST# 1
AD29 PLTRST# A

G
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH <15>
R366 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME# NC7SZ08P5X_NL_SC70-5
PCI_PME# <31>

3
AD31 PME# @
R357 1 2 8.2K_0402_5% PCI_PIRQE#

R367 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3

Interrupt I/F G8 PCI_PIRQE# 2 1
<23> PCI_PIRQA# PIRQA# GPIO2 / PIRQE# PCI_PIRQE# <25>
PCI_PIRQB# B4 F7 PCI_PIRQF# R311 0_0402_5%
<23> PCI_PIRQB# PIRQB# GPIO3 / PIRQF#
R352 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQC# C5 F8 PCI_PIRQG#
PCI_PIRQD# PIRQC# GPIO4 / PIRQG# PCI_PIRQH#
B5 PIRQD# GPIO5 / PIRQH# G7
R360 1 2 8.2K_0402_5% PCI_PIRQH#

R362 1 2 8.2K_0402_5% PCI_REQ0# AE5

MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R340 1 2 8.2K_0402_5% PCI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R335 1 2 8.2K_0402_5% PCI_REQ2# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# <7>
R358 1 2 8.2K_0402_5% PCI_REQ5# Place closely pin A9
ICH7_BGA652~D

CLK_PCI_ICH
B B

2
R351
10_0402_5%
@

1
1
C460
10P_0402_50V8K
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 18 of 43
5 4 3 2 1
 5 4 3 2 1

2
C215
Laptopblue
18P_0402_50V8J
1 ICH_RTCX1

10M_0402_5%
1
Y2

R139
2 NC IN 1
32.768KHZ_12.5P_1TJS125BJ2A251
3 NC OUT 4
U4A
LPC_AD[0..3] <30,31,35>

2
C214

RTC
18P_0402_50V8J AB1 AA6 LPC_AD0
ICH_RTCX2 RTXC1 LAD0 LPC_AD1 +VCCP
2 1 AB2 RTCX2 LAD1 AB5
D LPC_AD2 D
LAD2 AC4
+RTCVCC 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3 R124
RTCRST# LAD3

LPC
R369 H_DPSLP# 1 2
20K_0402_5% 1 R373 2 332K_0402_1% ICH_INTVRMEN W4 AC3 LPC_DRQ#0
INTVRMEN LDRQ0# LPC_DRQ#0 <30>
+RTCVCC 1 R364 2 1M_0402_5% SM_INTRUDER# Y5 INTRUDER# LDRQ1# / GPIO23 AA5 @ 56_0402_5%
R125
2 1 AB3 LPC_FRAME# H_DPRSTP# 1 2
LFRAME# LPC_FRAME# <30,31,35>
J1 @ JOPEN W1 EE_CS R328 1 @ 56_0402_5%
Y1 EE_SHCLK 2 +3VS
C484 Y2 AE22 GATEA20 10K_0402_5%
EE_DOUT A20GATE GATEA20 <31>

LAN
1U_0603_10V4Z W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# <4>

CPU
1 2
V3 AG27 H_CPUSLP_R# 2 @ 1 R310 0_0402_5%
LAN_CLK CPUSLP# H_CPUSLP# <4,7>
U3 AF24 DPRSLP# 2 1 R319 0_0402_5%
LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# <4,42>
AH25 H_DPSLP#
TP2 / DPSLP# H_DPSLP# <4>
U5 2 R313 1 +VCCP
LAN_RXD0 H_FERR# 56_0402_5%
V4 LAN_RXD1 FERR# AG26 H_FERR# <4>
T5 LAN_RXD2
AG24 H_PW RGOOD
GPIO49 / CPUPWRGD H_PWRGOOD <4>
U7 LAN_TXD0
V6 AG22 H_IGNNE#
LAN_TXD1 IGNNE# H_IGNNE# <4>
V7 LAN_TXD2 INIT3_3V# AG21
AF22 H_INIT#
INIT# H_INIT# <4>
AF25 H_INTR
INTR H_INTR <4>
+VCCP

AC-97/AZALIA
39_0402_5% 1 R385 2 ICH_AC_BITCLK_R U1 2 R325 1
<27> ICH_BITCLK_MDC ACZ_BCLK +3VS
39_0402_5% 1 R354 2 ICH_AC_SYNC_R R6 AG23 KB_RST# 10K_0402_5%
<27> ICH_SYNC_MDC ACZ_SYNC RCIN# KB_RST# <31>

1
39_0402_5% 1 R388 2 ICH_AC_RST_R# R5 AF23 H_SMI#
<27> ICH_RST_MDC# ACZ_RST# SMI# H_SMI# <4>
AH24 H_NMI R324
NMI H_NMI <4>
ICH_AC_SDIN0 T2 56_0402_5%
C <28> ICH_AC_SDIN0 ACZ_SDIN0 C
ICH_AC_SDIN1 T3 AH22 H_STPCLK#
<27> ICH_AC_SDIN1 ACZ_SDIN1 STPCLK# H_STPCLK# <4>
T1

2
ACZ_SDIN2 THRMTRIP_ICH#
THERMTRIP# AF26 1 R312 2 H_THERMTRIP# <4,7>
39_0402_5% 1 R389 2 ICH_AC_SDOUT_R T4 24.9_0402_1%
<27> ICH_SDOUT_MDC ACZ_SDOUT
AH17 PD_A0
DA0 PD_A0 <22>
SATA_LED# AF18 AE17 PD_A1
<34> SATA_LED# SATALED# DA1 PD_A1 <22>
AF17 PD_A2
DA2 PD_A2 <22>
PSATA_IRX_DTX_N0_C AF3 AE16 PD_CS#1
<22> PSATA_IRX_DTX_N0_C SATA0RXN DCS1# PD_CS#1 <22>
PSATA_IRX_DTX_P0_C AE3 AD16 PD_CS#3
<22> PSATA_IRX_DTX_P0_C SATA0RXP DCS3# PD_CS#3 <22>
PSATA_ITX_DRX_N0_C AG2 SATA0TXN

SATA
PSATA_ITX_DRX_P0_C AH2 SATA0TXP PD_D0
DD0 AB15
PSATA_IRX_DTX_N2_C AF7 AE14 PD_D1
PSATA_IRX_DTX_P2_C SATA2RXN DD1 PD_D2
AE7 SATA2RXP DD2 AG13
AG6 AF13 PD_D3 PD_D[0..15]
SATA2TXN DD3 PD_D[0..15] <22>
AH6 AD14 PD_D4
SATA2TXP DD4 PD_D5
DD5 AC13
CLK_PCIE_SATA# AF1 AD12 PD_D6
<15> CLK_PCIE_SATA# SATA_CLKN DD6
CLK_PCIE_SATA AE1 AC12 PD_D7
<15> CLK_PCIE_SATA SATA_CLKP DD7
AE12 PD_D8
DD8 PD_D9
AH10 SATARBIASN DD9 AF12
1 R348 2 AG10 AB13 PD_D10
+3VS 24.9_0402_1% SATARBIASP DD10 PD_D11
DD11 AC14
AF14 PD_D12
DD12 PD_D13
DD13 AH13
PD_D14
4.7K_0402_5% 2 R339 1 PD _IORDY PD _IORDY AG16
IDE DD14 AH14
AC15 PD_D15
<22> PD_IORDY IORDY DD15
8.2K_0402_5% 2 R338 1 PD_IRQ PD_IRQ AH16
<22> PD_IRQ IDEIRQ
10K_0402_5% 2 R334 1 SATA_LED# PD_DACK# AF16
<22> PD_DACK# DDACK#
PD_IOW# AH15 AE15 PD_DREQ
B <22> PD_IOW# DIOW# DDREQ PD_DREQ <22> B
PD_IOR# AF15
<22> PD_IOR# DIOR#

ICH7_BGA652~D

PSATA_ITX_DRX_N0 1 2 PSATA_ITX_DRX_N0_C
<22> PSATA_ITX_DRX_N0
C479 3900P_0402_50V7K

PSATA_ITX_DRX_P0 1 2 PSATA_ITX_DRX_P0_C
<22> PSATA_ITX_DRX_P0
C480 3900P_0402_50V7K

Close to U7
D2
12/12 Added +CHGRTC 2 + BATT1 -
1 BATT1.1 1 2
<28> ICH_SDOUT_AUDIO 1 2 ICH_AC_SDOUT_R 1 2 PSATA_IRX_DTX_N2_C W=20mils
R376 39_0402_5% R531 1K_0402_5% +RTCVCC 3
1 2 PSATA_IRX_DTX_P2_C
R532 1K_0402_5% C240 2 BAS40-04_SOT23 ML1220T13RE
<28> ICH_SYNC_AUDIO 1 2 ICH_AC_SYNC_R 45@
R353 39_0402_5%
0.1U_0402_16V4Z
1
<28> ICH_RST_AUDIO# 1 2 ICH_AC_RST_R# SATA_RXn/p need tie to ground when SATA port no used
A R387 39_0402_5% A

<28> ICH_BITCLK_AUDIO 1 2 ICH_AC_BITCLK_R

R386 39_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 19 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS
Laptopblue
+3VALW +3VALW
Place closely pin B2

CLK_48M_ICH
Place closely pin AC1

CLK_14M_ICH

1
10K_0402_5% 1 R326 2 SIRQ R380 R381

1
10_0402_5% 10_0402_5%

2
R331 R321 @ @
8.2K_0402_5% 1 R333 2 PCI_CLKRUN# R317 R316 2.2K_0402_5% 2.2K_0402_5%

2
U4C
10K_0402_5% 10K_0402_5% 1 1

2
10K_0402_5% 1 R329 2G7X_THER_ALERT# <15,27,35> ICH_SMBCLK ICH_SMBCLK C22 AF19 C474 C483

1
D ICH_SMBDATA SMBCLK GPIO21 / SATA0GP 10P_0402_50V8K 10P_0402_50V8K D
<15,27,35> ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18 SB_INT_FLASH_SEL <32>

SMB
SATA
GPIO
LINKALERT# A26 AH19 @ @
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 R336 2
ICH_SMLINK1 A25 100_0402_5%
SMLINK1
+3VALW +3VALW
AC1 CLK_14M_ICH
CLK14 CLK_14M_ICH <15>

Clocks
1 R309 2 I CH_RI# A28 B2 CLK_48M_ICH
RI# CLK48 CLK_48M_ICH <15>
10K_0402_5% 1 R318 2 LINKALERT# 8.2K_0402_5%
SB_SPKR A19
<28> SB_SPKR SPKR
SUS_STAT# A27 C20 ICH_SUSCLK T37 PAD
<35> SUS_STAT# SUS_STAT# SUSCLK
10K_0402_5% 1 R322 2 ITP_DBRESET# ITP_DBRESET# A22
<4> ITP_DBRESET# SYS_RST#

SYS
B24 SLP_S3# SLP_S3# <31>
+3VALW PM_BMBUSY# SLP_S3# SLP_S4#
<7> PM_BMBUSY# AB18 GPIO0 / BM_BUSY# SLP_S4# D23 SLP_S4# <31>
10K_0402_5% 1 R323 2 OCP# F22 SLP_S5# SLP_S5# <31>
OCP# SLP_S5#
<4> OCP# B23 GPIO11 / SMBALERT#
@ AA4
PWROK ICH_POK <7,31>

POWER MGT
10K_0402_5% 1 R379 2 SPI_MISO H_STP_PCI# AC20 1 R372 2 10K_0402_5%
<15> H_STP_PCI# GPIO18 / STPPCI#

GPIO
R550 H_STP_CPU# AF21 AC22 1 R95 2 100_0402_5%
<15> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR DPRSLPVR <7,42>
@
10K_0402_5% 1 R359 2 SPI_CS# PATA@ IDERST_CD# A21 C21 ICH_LOW_BAT#
<22> IDERST_CD# GPIO26 TP0 / BATLOW#
10K_0402_5%

1
B21 C23 PBTN_OUT#
GPIO27 PWRBTN# PBTN_OUT# <31>
1K_0402_5% 1 R330 2ICH_PCIE_WAKE# T31 PAD E23 GPIO28

2
C19 PLT_RST#
LAN_RST# PLT_RST# <7,17,18,22,26,27,31,35>
R551 PCI_CLKRUN# AG18
<31,35> PCI_CLKRUN# GPIO32 / CLKRUN# EC_RSMRST#
8.2K_0402_5% 2 R327 1 ICH_LOW_BAT# Y4
RSMRST# EC_RSMRST# <31>
SATA@ T39 PAD AC19 R374 10K_0402_5%
@ 10K_0402_5% T46 PAD GPIO33 / AZ_DOCK_EN#
U2 1 2
1
10K_0402_5% GPIO34 / AZ_DOCK_RST#
1 R368 2 SPI_MOSI
ICH_PCIE_WAKE# F20 E20 EC_SCI#
<26,27,35> ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# <31>
<23,30,31,35> SIRQ SIRQ AH21 A20
C SERIRQ GPIO10 ACIN <31,36> C
EC_THERM# AF20 F19 T36 PAD
<31> EC_THERM# THRM# GPIO12
E19 EC_LID_OUT#
GPIO13 EC_LID_OUT# <31>
VGATE AD22 R4 T43 PAD
<15,31,42> VGATE VRMPWRGD GPIO14
E22
2/13 Add feature: GPIO15
R3
T32 PAD
T44 PAD
T33 PAD GPIO24 EC_FLASH#
AC21 GPIO D20
Pull high for pure IDE interface T40 PAD AC18
GPIO6 GPIO25
AD21 SATAREQ#
EC_FLASH# <32>
SATAREQ# <15>
EC_SMI# GPIO7 GPIO35 / SATAREQ# G7X_THER_ALERT#
Pull low for SATA interface <31> EC_SMI# E21 GPIO8 GPIO38 AD20
AE20 T38 PAD
G7X_THER_ALERT# <17>
GPIO39
ICH7_BGA652~D Need update symbol

U4D
PCIE_RXN1 F26 V26 DMI_RXN0
<27> PCIE_RXN1 PERn1 DMI0RXN DMI_RXN0 <7>
PCIE_RXP1 F25 V25 DMI_RXP0
<27> PCIE_RXP1 PERp1 DMI0RXP DMI_RXP0 <7>

DIRECT MEDIA INTERFACE

<27> PCIE_TXN1 0.1U_0402_10V7K 2 1 C424 PCIE_C_TXN1 E28 U28 DMI_TXN0
PETn1 DMI0TXN DMI_TXN0 <7>
<27> PCIE_TXP1 0.1U_0402_10V7K 2 1 C423 PCIE_C_TXP1 E27 U27 DMI_TXP0
PETp1 DMI0TXP DMI_TXP0 <7>
H26 Y26 DMI_RXN1
PERn2 DMI1RXN DMI_RXN1 <7>
H25 Y25 DMI_RXP1
PERp2 DMI1RXP DMI_RXP1 <7>
G28 W28 DMI_TXN1
PETn2 DMI1TXN DMI_TXN1 <7>
G27 W27 DMI_TXP1
PETp2 DMI1TXP DMI_TXP1 <7>

PCI-EXPRESS
PCIE_RXN3 K26 AB26 DMI_RXN2
<26> PCIE_RXN3 PERn3 DMI2RXN DMI_RXN2 <7>
PCIE_RXP3 K25 AB25 DMI_RXP2
<26> PCIE_RXP3 PERp3 DMI2RXP DMI_RXP2 <7>
<26> PCIE_TXN3 0.1U_0402_10V7K 2 1 C435 PCIE_C_TXN3 J28 AA28 DMI_TXN2
PETn3 DMI2TXN DMI_TXN2 <7>
<26> PCIE_TXP3 0.1U_0402_10V7K 2 1 C436 PCIE_C_TXP3 J27 AA27 DMI_TXP2
PETp3 DMI2TXP DMI_TXP2 <7>
PCIE_RXN4 M26 AD25 DMI_RXN3
B <35> PCIE_RXN4 PERn4 DMI3RXN DMI_RXN3 <7> B
PCIE_RXP4 M25 AD24 DMI_RXP3
<35> PCIE_RXP4 PERp4 DMI3RXP DMI_RXP3 <7>
<35> PCIE_TXN4 0.1U_0402_10V7K 2 1 C432 PCIE_C_TXN4 L28 AC28 DMI_TXN3
PETn4 DMI3TXN DMI_TXN3 <7>
<35> PCIE_TXP4 0.1U_0402_10V7K 2 1 C439 PCIE_C_TXP4 L27 AC27 DMI_TXP3
PETp4 DMI3TXP DMI_TXP3 <7>
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# <15>
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH <15>
N28 PETn5
N27 C25 R314 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 RP13
PERn6 USB20_N0
T24 PERp6 USBP0N F1 USB20_N0 <34> 4 5 +3VALW
R28 F2 USB20_P0 USB_OC#2 3 6
PETn6 USBP0P USB20_P0 <34>
R27 G4 USB20_N1 USB_OC#3 2 7
PETp6 USBP1N USB20_N1 <27>
G3 USB20_P1 USB_OC#1 1 8
USBP1P USB20_P1 <27>
R2 H1 USB20_N2
SPI_CLK USBP2N USB20_N2 <29>
SPI_CS# P6 H2 USB20_P2 10K_1206_8P4R_5%
SPI_CS# SPI USBP2P USB20_P2 <29>
P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 <33>
J3 USB20_P3
USBP3P USB20_P3 <33>
SPI_MOSI P5 K1 USB20_N4 RP14
SPI_MOSI USBP4N USB20_N4 <29>
SPI_MISO P2 K2 USB20_P4 USB_OC#0 4 5
SPI_MISO USBP4P USB20_P4 <29> +3VALW
L4 USB20_N5 USB_OC#5 3 6
USBP5N USB20_N5 <33>
L5 USB20_P5 USB_OC#6 2 7
USBP5P USB20_P5 <33>
USB_OC#0 D3 M1 USB20_N6 USB_OC#7 1 8
<34> USB_OC#0 OC0# USBP6N USB20_N6 <35>
USB_OC#1 C4 M2 USB20_P6
USB_OC#2 D5
OC1# USB USBP6P
N4 USB20_N7
USB20_P6 <35>
10K_1206_8P4R_5%
<34> USB_OC#2 OC2# USBP7N USB20_N7 <27>
USB_OC#3 D4 N3 USB20_P7
OC3# USBP7P USB20_P7 <27>
E5 OC4#
USB_OC#5 C3 R382 22.6_0402_1%
USB_OC#6 OC5# / GPIO29 USBRBIAS
A2 OC6# / GPIO30 USBRBIAS# D2 1 2
USB_OC#7 B3 D1
OC7# / GPIO31 USBRBIAS
Within 500 mils
A ICH7_BGA652~D A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 20 of 43
5 4 3 2 1
 5 4 3 2 1

+5VS +3VS
Laptopblue
+VCCP
U4F U4E
1

2
A4 VSS[0] VSS[98] P28
R355 D23 ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
100_0402_5% RB751V_SOD323 AD17 L14 1 B8 R12
V5REF[2] Vcc1_05[3] VSS[3] VSS[101]
L16 1 1 B11 R13
2

1 Vcc1_05[4] VSS[4] VSS[102]

+1.5VS ICH_V5REF_SUS F6 L17 C459 C454 + C447 B14 R14
ICH_V5REF_RUN V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z 220U_D2_2VMR15 D
1 1 AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
C458 C457 2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B28 VSS[9] VSS[107] R18
0.1U_0402_16V4Z 0.1U_0402_16V4Z C420 + C425 C434 C429 AB23 P18 C2 T6
2 2 Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
220U_D2_2VMR15 AC24 T18 C27 T13
2 2 2 2 Vcc1_5_B[6] Vcc1_05[12] VSS[12] VSS[110]
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
Place close pin G10 or AD17 AD27 Vcc1_5_B[10] Vcc1_05[16] V12 D21 VSS[16] VSS[114] T17
AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
Place close pin D26 Vcc1_5_B[12] Vcc1_05[18] V16 E1 VSS[18] VSS[116] U12
D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
D28,T28,AD28. D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
E25 Vcc1_5_B[16] Vcc3_3 / VccHDA U6 +3VS E15 VSS[23] VSS[120] U16
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 +VCCP C453 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3VALW VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C450 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VALW H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

K22 AB20 1 C449 G6 V28

R365 D24 Vcc1_5_B[26] Vcc3_3[5] C455 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% RB751V_SOD323 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C456 VSS[36] VSS[133]
M22 AG12 G21 W26
2

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 Place close pin AH26 G24 VSS[38] VSS[135] Y3
1 N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C467 C
N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
P22 Vcc1_5_B[34] Vcc3_3[12] A5 +3VS H3 VSS[41] VSS[138] Y28

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z P23 B13 H4 AA1
2 Vcc1_5_B[35] Vcc3_3[13] VSS[42] VSS[139]
R22 Vcc1_5_B[36] Vcc3_3[14] B16 1 1 1 H5 VSS[43] VSS[140] AA24
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C466

C446

C433
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
+3VS
R26 Vcc1_5_B[40] Vcc3_3[18] F9 Place close pin J1 VSS[47] VSS[144] AB6
T22 Vcc1_5_B[41] Vcc3_3[19] G11 J2 VSS[48] VSS[145] AB11
T23 G12 A5, B7 & C10 J5 AB14
Vcc1_5_B[42] Vcc3_3[20] VSS[49] VSS[146]
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C448 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
V22 Vcc1_5_B[48] 1 1 1 K28 VSS[55] VSS[152] AB28
2

C468
V23 A24 C476 C481 L13 AC2
0.1U_0402_16V4Z Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place close pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS R308 +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 K3 M4 AD4
0.5_0603_1% R305 Vcc3_3[1] VccSus3_3[7] +3VALW VSS[62] VSS[159]
VccSus3_3[8] K4 1 1 M5 VSS[63] VSS[160] AD7
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C465 C473 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0_0603_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C421

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C430

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C470 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
B 0.1U_0402_16V4Z
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 Place close pin L1 & K3 M27 VSS[71] VSS[168] AE8
B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
Place close pin AH5. AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C472

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

C452

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27
2 C461 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C444 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T42 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD T16 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
Place close pin AH9. AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T35 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3VALW E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C469 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C478 P15 AH3
0.1U_0402_16V4Z C464 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T45 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_ Y7 0.1U_0402_16V4Z
T41 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2] Place close pin A1 ICH7_BGA652~D
W2 VccSus3_3/VccLAN3_3[3]
+3VALW W7 VccSus3_3/VccLAN3_3[4]
1 ICH7_BGA652~D
C445
A A
0.1U_0402_16V4Z
2

Place close pin V1

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 21 of 43
5 4 3 2 1
 5 4 3 2 1

SA880400020 Marvell 8040 TQFP64_Lead Free

PIDE_DD0
PIDE_DD1
62
64
U11

HDD0 TXP 32
31
Laptopblue
SATA_DTX_IRX_P0
SATA_DTX_IRX_N0
+3VS
SATA HDD Conn.
2005/11/4 Modified library pn:DC010003J00
Main SATA +5V Default
JP9
HDD1 TXM

1
PIDE_DD2 PSATA_ITX_DRX_P0
PIDE_DD3
2
5
HDD2 SATA RXP 27
28 PSATA_ITX_DRX_N0 PSATA_ITX_DRX_P0 <19> R251 1
PIDE_DD4 HDD3 RXM PSATA_ITX_DRX_N0 <19> +3VS 100K_0402_5% SATA_ITX_C_R_DRX_P0 GND
7 HDD4 2 A+
PIDE_DD5 11 17 SATA_RESET# @ SATA_ITX_C_R_DRX_N0 3
PIDE_DD6 HDD5 RST# T0 R249 A-
13 33 4

2
PIDE_DD7 HDD6 T0 T0 R245 1 GND
15 34 2 @ 10K_0402_5% SATA_RESET# 1 2 SATA_DTX_R_IRX_N0 5

Config & Debug

HDD7 T1 PLT_RST# <7,17,18,20,26,27,31,35> B-
PIDE_DD8 14 35 T2 1 0_0402_5% SATA_DTX_R_IRX_P0 6
PIDE_DD9 HDD8 T2 T3 T2 R237 1 B+
12 HDD9 T3 36 2 @ 10K_0402_5% C338 8040@ 7 GND
PIDE_DD10 10 37 1U_0603_10V4Z
D PIDE_DD11 HDD10 T4 T5 T3 D
6 38 1 2 8040@ R226 1 2 8040@ 10K_0402_5% @ W=60mils at least

Parallel ATA
PIDE_DD12 HDD11 T5 T6 R233 10K_0402_5% 2
3 HDD12 T6 39 +3VS 8 V33

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PIDE_DD13 1 40 T6 R224 1 2 @ 10K_0402_5% 9
PIDE_DD14 HDD13 T7 V33
63 HDD14 CNFG2 20 1 1 1 1 1 10 V33
PIDE_DD15 61 19 CNFG1 1 2 8040@ ATAIOSEL R247 1 2 8040@ 10K_0402_5% C237 C236 C234 C251 C243 11
HDD15 CNFG1 R246 10K_0402_5% GND
CNFG0 18 12 GND
21 ATAIOSEL PIDE_HIOCS16# R171 1 2 8040@ 10K_0402_5% @ @ @ @ @ 13
PIDE_DA0 ATAIOSEL 2 2 2 2 2 GND
50 HDA0 14 V5
PIDE_DA1 51 22 SATA_XTALI 15
PIDE_DA2 HDA1 XTLIN/OSC SATA_XTALO V5
49 HDA2 XTLOUT 23 16 V5
PIDE_CS0# 48 PIDE_R_RESET# 2 1 PIDE_RESET# W=60mils at least 17
PIDE_CS1# HCS0# R235 8040@ 33_0402_5% GND
47 HCS1# +5VS 18 Reserved

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
26 R490 1 2 12.1K_0603_1% 19
PIDE_HIOCS16# ISET GND
52 44 +3VS 8040@ 20
PIDE_INTRQ 53
HIOCS16#
HINTRQ
VDDIO_0
VDDIO_1 4 PLACE Close to U61 1
C218
1
C217
1
C216
1
C222
1
C225 21
V12
V12
PIDE_DMACK# 54 9 +1.8VS 22
PIDE_DIORDY HDMACK# VDD_0 @ @ V12
55 HIORDY VDD_1 41
PIDE_DIOR# 2 2 2 2 2
58 HDIOR# VDD_2 56 1 2 +3VS
PIDE_DIOW# 59 24 L11 8040@ MBK1608121YZF_0603 SUYIN_127072FR022G210ZR_22P_SATA
PIDE_DREQ HDIOW# VAA1 +1.8VS_VDDA SATA@
60 HDMARQ VAA2 29 1 2 +1.8VS
PIDE_R_RESET# 16 R492 L12 @ MBK1608121YZF_0603
46
HRESET# Power 25 8040@ 0_0603_5% 1 1 1
T27 HPDIAG# VSS1 FG ND C330 C329 C344
VSS2 30 1 2
2

PAD 8 2005/11/4 Modified library pn:SP01000LU00

R212 T28 GND_0 0.01U_0402_16V7K 4.7U_0805_10V4Z
PAD
45 UAO UART GND_1 42
2 8040@ 2 8040@ 2 8040@
43 57 Reverse pin 1 to 44, pin 2 to 43
10K_0402_5%
UAI GND_2 0.1U_0402_16V4Z PATA HDD Conn. JP25
1

8040@ 88SA8040_TQFP64 +3VS

8040@
FGND Place closed to Connector 1 1 2 2
+5VS 3 3 4 4 +5VS
PIDE_DIORDY 1 2 5 6 PIDE_LED# T30
R206 8040@ 4.7K_0402_5% PIDE_CS1# 5 6 PIDE_CS0# PAD
7 7 8 8
C SATA@ PIDE_DREQ PIDE_DA2 PIDE_DA0 C
SATA_ITX_C_R_DRX_P0 2 PSATA_ITX_DRX_P0
R_SATA SATA 1
R223 8040@
2
5.6K_0402_5% T26 PIDE_PDIAG#
9 9 10 10
PIDE_DA1
Place closed to 3811 SATA_ITX_C_R_DRX_N0 1
3
PSATA_ITX_DRX_N0
R HDD PIDE_INTRQ PAD
11 11 12 12
PIDE_INTRQ
RP15
4
0_0404_4P2R_5%
Connector 1
R188 8040@
2
10K_0402_5%
13 13 14 14
PIDE_DMACK#
2005/09/04 15 15 16 16
SATA PIDE_DD7 1 2 2 1PCSEL 17 18 PIDE_DIORDY
SATA@ R263 @ 10K_0402_5% R198 17 18 PIDE_DIOR#
SATA_DTX_R_IRX_N0 SATA_DTX_IRX_N0
ICH7M Marvell 8040 475_0402_1%
19 19 20 20
PIDE_DIOW#
2 3 21 21 22 22
SATA_DTX_R_IRX_P0 1 4 SATA_DTX_IRX_P0 R_IDE PATA 23 24 PIDE_DREQ
RP16 0_0404_4P2R_5% 23 24
IDE HDD PIDE_DD15
25 25 26 26
PIDE_DD0
PSATA_IRX_DTX_N0_C SATA_DTX_IRX_N0
R R Connector PIDE_DD14
27 27 28 28
PIDE_DD1
<19> PSATA_IRX_DTX_N0_C 1 2 29 29 30 30
C336 3900P_0402_50V7K +5VS PIDE_DD13 31 32 PIDE_DD2
PIDE_DD12 31 32 PIDE_DD3
PSATA_IRX_DTX_P0_C SATA_DTX_IRX_P0
IDE SATA HDD ONLY PIDE_DD11
33 33 34 34
PIDE_DD4
<19> PSATA_IRX_DTX_P0_C 1 2 ODD SATA to PATA HDD 35 35 36 36

1
C331 3900P_0402_50V7K Connector PATA HDD ONLY PIDE_DD10 37 38 PIDE_DD5
R320 PIDE_DD9 37 38 PIDE_DD6
39 39 40 40
PIDE_DD8 41 42 PIDE_DD7
10K_0402_5% 41 42 PIDE_RESET#
2005/10/19 43 43 44 44
R_PIDE_DD2 1 2 PD_D2 R_PIDE_DD2 1 2 PIDE_DD2

2
R113 PATA@ 0_0402_5% R194 PATA@ 0_0402_5% SUYIN_200055FB044G202ZR_44P_P2_PATA_HDD
R_PIDE_DD12 1 2 PD_D12 R_PIDE_DD12 1 2 PIDE_DD12 Y4 PIDE_LED# PATA@
<34> PIDE_LED#
R114 PATA@ 0_0402_5% R199 PATA@ 0_0402_5% SATA_XTALI 1 SATA_XTALO
R_PIDE_DD3 1 2 PD_D3 R_PIDE_DD3 1 2 PIDE_DD3
2
(NEW)

1
R115 PATA@ 0_0402_5% R205 PATA@ 0_0402_5% 25MHZ_20PF_6X25000017
R_PIDE_DD11 1 2 PD_D11 R_PIDE_DD11 1 2 PIDE_DD11 8040@ R248
R116 PATA@ 0_0402_5% R210 PATA@ 0_0402_5% 0_0402_5%
R_PIDE_DD4 1 2 PD_D4 R_PIDE_DD4 1 2 PIDE_DD4 8040@
R137 PATA@ 0_0402_5% R215 PATA@ 0_0402_5%
PATA ODD Conn.
2
R_PIDE_DD10 1 2 PD_D10 R_PIDE_DD10 1 2 PIDE_DD10 PD_D[0..15]
PD_D[0..15] <19>
R117 PATA@ 0_0402_5% R217 PATA@ 0_0402_5% R250 8040@ 10M_0402_5%
R_PIDE_DD5 PD_D5 R_PIDE_DD5 PIDE_DD5 +3VS PD_A[0..2]
1 2 1 2 1 1 PD_A[0..2] <19>
R122 PATA@ 0_0402_5% R218 PATA@ 0_0402_5% C339 C340
B R_PIDE_DD9 PD_D9 R_PIDE_DD9 PIDE_DD9 27P_0402_50V8J 27P_0402_50V8J C451 B
1 2 1 2
R118 PATA@ 0_0402_5% R222 PATA@ 0_0402_5% 8040@ 8040@ 1 2 0.1U_0402_16V4Z
R_PIDE_DD6 PD_D6 R_PIDE_DD6 PIDE_DD6 2 2
1 2 1 2
R136 PATA@ 0_0402_5% R225 PATA@ 0_0402_5% JP10

5
R_PIDE_DD8 1 2 PD_D8 R_PIDE_DD8 1 2 PIDE_DD8 1 2
R121 PATA@ 0_0402_5% R227 PATA@ 0_0402_5% IDERST_CD# 1 2
2 3 4

P
<20> IDERST_CD# B 3 4
R_PIDE_DD7 1 2 PD_D7 R_PIDE_DD7 1 2 PIDE_DD7 4 IDE_RST# 5 6 PD_D8
R133 PATA@ 0_0402_5% R231 PATA@ 0_0402_5% PLT_RST# Y PD_D7 5 6 PD_D9
<7,17,18,20,26,27,31,35> PLT_RST# 1 A 7 7 8 8

G
R_PIDE_RESET# 1 2 IDE_RST# R_PIDE_RESET# 1 2 PIDE_RESET# PD_D6 9 10 PD_D10
R135 PATA@ 0_0402_5% R241 PATA@ 0_0402_5% +1.8VS U28 PD_D5 9 10 PD_D11
11 12

3
R_PIDE_DD0 PD_D0 R_PIDE_DD0 PIDE_DD0 NC7SZ08P5X_NL_SC70-5 PD_D4 11 12 PD_D12
1 2 1 2 13 13 14 14
R108 PATA@ 0_0402_5% R177 PATA@ 0_0402_5% 0.1U_0402_16V4Z PD_D3 15 16 PD_D13
R_PIDE_DD14 PD_D14 R_PIDE_DD14 1 PIDE_DD14 PD_D2 15 16 PD_D14
1 2 2 17 17 18 18
R111 PATA@ 0_0402_5% R176 PATA@ 0_0402_5% 1 1 1 PD_D1 19 20 PD_D15
R_PIDE_DD1 PD_D1 R_PIDE_DD1 PIDE_DD1 C314 C504 C498 PD_D0 19 20 PD_DREQ
1 2 1 2 21 21 22 22 PD_DREQ <19>
R110 PATA@ 0_0402_5% R175 PATA@ 0_0402_5% 23 24 PD_IOR#
23 24 PD_IOR# <19>
R_PIDE_DD13 1 2 PD_D13 R_PIDE_DD13 1 2 PIDE_DD13 8040@ 8040@ 8040@ PD_IOW# 25 26
2 2 2 <19> PD_IOW# 25 26
R112 PATA@ 0_0402_5% R190 PATA@ 0_0402_5% PD _IORDY 27 28 PD_DACK#
<19> PD_IORDY 27 28 PD_DACK# <19>
R_PIDE_DIOR# 1 2 PD_IOR# R_PIDE_DIOR# 1 2 PIDE_DIOR# PD_IRQ 29 30
<19> PD_IRQ 29 30
R106 PATA@ 0_0402_5% R181 PATA@ 0_0402_5% 0.1U_0402_16V4Z 4.7U_0805_10V4Z PD_A1 31 32 PD_DIAG# 1 2
R_PIDE_DIOW# PD_IOW# R_PIDE_DIOW# 1 PIDE_DIOW# PD_A0 31 32 PD_A2 R315 100K_0402_5% +5VS
1 2 2 33 33 34 34
R105 PATA@ 0_0402_5% R180 PATA@ 0_0402_5% PD_CS#1 35 36 PD_CS#3
<19> PD_CS#1 35 36 PD_CS#3 <19>
R_PIDE_DREQ 1 2 PD_DREQ R_PIDE_DREQ 1 2 PIDE_DREQ PIDE_LED# 37 38
37 38 +5VS

0.1U_0402_16V4Z

10U_0805_10V4Z

10U_0805_10V4Z

1U_0603_10V4Z
R107 PATA@ 0_0402_5% R179 PATA@ 0_0402_5% 39 40
R_PIDE_DD15 PD_D15 R_PIDE_DD15 1 PIDE_DD15 39 40
1 2 2 +5VS 41 41 42 42
R109 PATA@ 0_0402_5% R178 PATA@ 0_0402_5% +5VS 1 2 43 44 1 1 1 1
R_PIDE_DA1 PD_A1 R_PIDE_DA1 PIDE_DA1 +3VS R307 @ 475_0402_1% 43 44 C441 C440 C426 C422
1 2 1 2 45 45 46 46
R101 PATA@ 0_0402_5% R185 PATA@ 0_0402_5% 1 2 PRI_CSEL 47 48
47 48
0.1U_0402_16V4Z

R_PIDE_INTRQ 1 2 PD_IRQ R_PIDE_INTRQ 1 2 PIDE_INTRQ 0.1U_0402_16V4Z 4.7U_0805_10V4Z R306 475_0402_1% 49 50

R102 PATA@ 0_0402_5% R184 PATA@ 0_0402_5% SATA@ 49 50 2 2 2 2
R_PIDE_DMACK# 1 2 PD_DACK# R_PIDE_DMACK# 1 2 PIDE_DMACK# 1 1 1 1 IDE_CSEL OCTEK_CDR-50DY1G
8040@
C311

R103 PATA@ 0_0402_5% R183 PATA@ 0_0402_5% C501 C303 C375 ME@
A R_PIDE_DIORDY 1 2 PD _IORDY R_PIDE_DIORDY 1 2 PIDE_DIORDY Grounding for Master (When use SATA HDD) A
R104 PATA@ 0_0402_5% R182 PATA@ 0_0402_5% 8040@ 8040@ 8040@
R_PIDE_CS1# PD_CS#3 R_PIDE_CS1# PIDE_CS1# 2 2 2 2 Open or High for Slaver (Normal)
1 2 1 2
R97 PATA@ 0_0402_5% R207 PATA@ 0_0402_5% 0.1U_0402_16V4Z
R_PIDE_CS0# 1 2 PD_CS#1 R_PIDE_CS0# 1 2 PIDE_CS0#
R96 PATA@ 0_0402_5% R203 PATA@ 0_0402_5%
R_PIDE_DA2 1 2 PD_A2 R_PIDE_DA2 1 2 PIDE_DA2
R98 PATA@ 0_0402_5% R187 PATA@ 0_0402_5%
R_PIDE_DA0 1
R99
2
PATA@
PD_A0
0_0402_5%
R_PIDE_DA0 1
R186
2
PATA@
PIDE_DA0
0_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title
R_PIDE_PDIAG# 1 2 PD_DIAG# R_PIDE_PDIAG# 1 2 PIDE_PDIAG#
R100 PATA@ 0_0402_5% R169 PATA@ 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 22 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue
+S1_VCC +3VS
VPPD0
<24> VPPD0
VPPD1
<24> VPPD1
VCCD0#
+3VS <24> VCCD0#
40mil VCCD1#
<24> VCCD1#

M13

M12

G13
N13

N12

D12
H11
S1_A[0..25]

G1
C8

N4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A7

B4

K2

F3
L9
L6
S1_A[0..25] <24>
U9
1 1 1 1 1 1 1 S1_D[0..15]

VCCD1#
VCCD0#

VPPD1
VPPD0

VCCA2
VCCA1

VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
D
S1_D[0..15] <24> D
C258 C296 C299 C260 C259 C283 C319

0.1U_0402_16V4Z
2 2 2 2 2 2 2
PCI_AD31 C2 B2 S1_D10
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z PCI_AD30 AD31 CAD31/D10 S1_D9
C1 AD30 CAD30/D9 C3
PCI_AD29 D4 B3 S1_D1
PCI_AD28 AD29 CAD29/D1 S1_D8
D2 AD28 CAD28/D8 A3
PCI_AD27 D1 C4 S1_D0 +3VS
PCI_AD26 AD27 CAD27/D0 S1_A0
E4 AD26 CAD26/A0 A6
PCI_AD25 E3 D7 S1_A1
PCI_AD24 AD25 CAD25/A1 S1_A2
E2 AD24 CAD24/A2 C7 1 1
PCI_AD23 F2 A8 S1_A3 C321 C320
PCI_AD[0..31] PCI_AD22 AD23 CAD23/A3 S1_A4
<18,25,30> PCI_AD[0..31] F1 AD22 CAD22/A4 D8
PCI_AD21 G2 A9 S1_A5 4.7U_0805_10V4Z 0.1U_0402_16V4Z
PCI_CBE#[0..3] PCI_AD20 AD21 CAD21/A5 S1_A6 2 2
<18,25,30> PCI_CBE#[0..3] G3 AD20 CAD20/A6 C9
PCI_AD19 H3 A10 S1_A25
PCI_AD18 AD19 CAD19/A25 S1_A7
H4 AD18 CAD18/A7 B10
PCI_AD17 J1 D10 S1_A24
PCI_AD16 AD17 CAD17/A24 S1_A17
J2 AD16 CAD16/A17 E12
PCI_AD15 N2 F10 S1_IOWR#
AD15 CAD15/IOWR# S1_IOWR# <24>
CLK_PCI_PCM CLK_SD_48M PCI_AD14 M3 E13 S1_A9
PCI_AD13 AD14 CAD14/A9 S1_IORD# +S1_VCC
N3 AD13 CAD13/IORD# F13 S1_IORD# <24>

1
PCI_AD12 K4 F11 S1_A11
R204 R197 PCI_AD11 AD12 CAD12/A11 S1_OE#
M4 AD11 CAD11/OE# G10 S1_OE# <24>
PCI_AD10 K5 G11 S1_CE2# 1 1
AD10 CAD10/CE2# S1_CE2# <24>
@ 10_0402_5% @ 10_0402_5% PCI_AD9 L5 G12 S1_A10 C257 C292
+3VS PCI_AD8 AD9 CAD9/A10 S1_D15
2 M5 H12

2
PCI_AD7 AD8 CAD8/D15 S1_D7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 K6 AD7 CAD7/D7 H10
SM_CD# C295 C290 PCI_AD6 S1_D13 2 2
1 2 M6 AD6 CAD6/D13 J11
R230 43K_0402_5% PCI_AD5 N6 J12 S1_D6
@ 15P_0402_50V8J @ 15P_0402_50V8J PCI_AD4 AD5 CAD5/D6 S1_D12
M7 AD4 CAD4/D12 K13
C 2 2 PCI_AD3 S1_D5 C
N7 J10

PCI Interface
PCI_AD2 AD3 CAD3/D5 S1_D11
L7 AD2 CAD2/D11 K10

CARDBUS
PCI_AD1 K7 K12 S1_D4
PCI_AD0 AD1 CAD1/D4 S1_D3
N8 AD0 CAD0/D3 L13

PCI_CBE#3 E1 B7 S1_REG#
CBE3# CCBE3#/REG# S1_REG# <24>
PCI_CBE#2 J3 A11 S1_A12
PCI_CBE#1 CBE2# CCBE2#/A12 S1_A8
N1 CBE1# CCBE1#/A8 E11
PCI_CBE#0 N5 H13 S1_CE1#
CBE0# CCBE0#/CE1# S1_CE1# <24>
PCI_RST# G4 B9 S1_RST
<18,25,30> PCI_RST# PCIRST# CRST#/RESET S1_RST <24>
<18,25,30> PCI_FRAME# J4 B11 S1_A23
FRAME# CFRAME#/A23 S1_A15
<18,25> PCI_IRDY# K1 IRDY# CIRDY#/A15 A12
<18,25,30> PCI_TRDY# K3 A13 S1_A22
TRDY# CTRDY#/A22 S1_A21
<18,25> PCI_DEVSEL# L1 DEVSEL# CDEVSEL#/A21 B13
L2 C12 S1_A20
<18,25> PCI_STOP# STOP# CSTOP#/A20
L3 C13 S1_A14
<18,25> PCI_PERR# PERR# CPERR#/A14
M1 A5 S1_WAIT#
<18> PCI_SERR# SERR# CSERR#/WAIT# S1_WAIT# <24>
<18,25> PCI_PAR M2 D13 S1_A13
PCI_REQ2# PAR CPAR/A13 S1_INPACK#
<18> PCI_REQ2# A1 PCIREQ# CREQ#/INPACK# B8 S1_INPACK# <24>
PCI_GNT2# B1 C11 S1_WE#
<18> PCI_GNT2# PCIGNT# CGNT#/WE# S1_WE# <24>
CLK_PCI_PCM H1 B12 1 2 S1_A16
<15> CLK_PCI_PCM PCICLK CCLK/A16 R160 33_0402_5%
L8 C5 S1_BVD1
RIOUT#_PME# CSTSCHG/BVD1_STSCHG# S1_BVD1 <24>
+3VS 1 2 L11 D5 S1_WP
SUSPEND# CCLKRUN#/WP_IOIS16# S1_WP <24>
R229 10K_0402_5%
PCI_AD20 1 2 F4 D11 S1_A19
R192 100_0402_5% IDSEL CBLOCK#/A19
K8 D6 S1_RDY# S1_CD2# S1_CD1#
<18> PCI_PIRQA# MFUNC0 CINT#/READY_IREQ# S1_RDY# <24>
R228 1 2 SD_PULLHIGH N9 2 2
<24> MS_PWREN# MFUNC1
@ 0_0402_5% K9 M9 PCM_SPK# C250 C323
<18> PCI_PIRQB# MFUNC2 SPKROUT PCM_SPK# <28>
<20,30,31,35> SIRQ N10 B5 S1_BVD2
B MFUNC3 CAUDIO/BVD2_SPKR# S1_BVD2 <24> B
SM_CD# L10 10P_0402_50V8K 10P_0402_50V8K
3IN1_LED# MFUNC4 S1_CD2# 1 1
<34> 3IN1_LED# N11 MFUNC5 CCD2#/CD2# A4 S1_CD2# <24>
M11 L12 S1_CD1#
MFUNC6 CCD1#/CD1# S1_CD1# <24>
SDOC# J9 D9 S1_VS2
<24> SDOC# MFUNC7 CVS2/VS2# S1_VS2 <24>
C6 S1_VS1
CVS1/VS1 S1_VS1 <24>
A2 S1_D2
PCI_RST# CRSV3/D2 S1_A18
M10 GRST# CRSV2/A18 E10
MFUNC5[3:0] = (0 1 0 1) J13 S1_D14
CRSV1/D14
MFUNC5[4] = 1
E7
SD/MMC/MS/SM H7
+VCC_SD VCC_SD MSINS# MS_INS# <24>
MSPWREN#/SMPWREN# J8 MS_PWREN# <24>
SD_CD# E8 H8 MSBS_XDD1
<24> SD_CD# SDCD# MSBS/SMDATA1 MSBS_XDD1 <24>
SD_WP# F8 E9 MS_CLK R161 1 2 33_0402_5%
<24> SD_WP# SDWP/SMWPD# MSCLK/SMRE# MSCLK_XDRE# <24>
SD_PWREN# G7 G9 MSD0_XDD2
<24> SD_PWREN# SDPWREN33# MSDATA0/SMDATA2 MSD0_XDD2 <24>
H9 MSD1_XDD6
MSDATA1/SMDATA6 MSD1_XDD6 <24>
CLK_SD_48M H5 G8 MSD2_XDD5
<15> CLK_SD_48M SDCLKI MSDATA2/SMDATA5 MSD2_XDD5 <24>
F9 MSD3_XDD3
MSDATA3/SMDATA3 MSD3_XDD3 <24>
R209 1 2 33_0402_5% SD_CLK F6
<24> SDCK_XDWE# SDCLK/SMWE#
SDCM_XDALE E5
<24> SDCM_XDALE SDCMD/SMALE
SDDA0_XDD7 E6 H6
<24> SDDA0_XDD7 SDDAT0/SMDATA7 SMBSY#
SDDA1_XDD0 F7 J7
<24> SDDA1_XDD0 SDDAT1/SMDATA0 SMCD#
SDDA2_XDCL F5 J6
<24> SDDA2_XDCL SDDAT2/SMCLE SMWP#
SDDA3_XDD4 G6 J5
<24> SDDA3_XDD4 SDDAT3/SMDATA4 SMCE#
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

G5 GND_SD

CB714_LFBGA169
D3
H2
L4
M8
K11
F12
C10
B6

A A
**CB714 use B0 version

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cardbus Controller CB714
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HEL80 LA-3161P
Date: Thursday, February 23, 2006 Sheet 23 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue PCMCIA Socket

Note : 11/10 modify library to meet spec

S1_A[0..25]
pn: SP01000IC00
<23> S1_A[0..25]
D
PCMCIA Power Control <23> S1_D[0..15]
S1_D[0..15] 02/17 modify footprint to FOX_1CA41521-EL-4F_68P_LT D

+S1_VCC
JP17
+S1_VCC
U16
40mil S1_D3
1 GND GND 35
S1_CD1#
2 D3 CD1# 36 S1_CD1# <23>
13 S1_D4 3 37 S1_D11
VCC S1_D5 D4 D11 S1_D12
VCC 12 1 1 4 D5 D12 38
9 11 C322 C317 S1_D6 5 39 S1_D13
12V VCC +S1_VPP S1_D7 D6 D13 S1_D14
6 D7 D14 40
40mil 10U_0805_10V4Z 0.1U_0402_16V4Z S1_CE1# 7 41 S1_D15
+5VS 2 2 <23> S1_CE1# S1_A10 CE1# D15 S1_CE2#
8 A10 CE2# 42 S1_CE2# <23>
W=40mil 1 S1_OE# 9 43 S1_VS1
C359 <23> S1_OE# S1_A11 OE# VS1# S1_IORD# S1_VS1 <23>
VPP 10 10 A11 IORD# 44 S1_IORD# <23>
1 1 S1_A9 11 45 S1_IOWR#
C361 C360 0.1U_0402_16V4Z S1_A8 A9 IOWR# S1_A17 S1_IOWR# <23>
5 5V 12 A8 A17 46
2 S1_A13 S1_A18
6 5V 13 A13 A18 47
10U_0805_10V4Z 0.1U_0402_16V4Z S1_A14 14 48 S1_A19
2 2 VCCD0# +S1_VPP S1_WE# A14 A19 S1_A20
VCCD0 1 VCCD0# <23> <23> S1_WE# 15 WE# A20 49
2 VCCD1# S1_RDY# 16 50 S1_A21
+3VS VCCD1 VCCD1# <23> <23> S1_RDY# IREQ# A21
15 VPPD0 +S1_VCC 17 51 +S1_VCC
VPPD0 VPPD0 <23> VCC VCC
14 VPPD1 1 1 +S1_VPP 18 52 +S1_VPP
VPPD1 VPPD1 <23> VPP1 VPP2
W=40mil C325 C318 S1_A16 19 53 S1_A22
S1_A15 A16 A22 S1_A23
3 3.3V 20 A15 A23 54
1 1 4 8 10U_0805_10V4Z 0.1U_0402_16V4Z S1_A12 21 55 S1_A24
3.3V OC 2 2 A12 A24
SHDN

C356 C357 S1_A7 22 56 S1_A25

GND

S1_A6 A7 A25 S1_VS2

23 A6 VS2# 57 S1_VS2 <23>
10U_0805_10V4Z 0.1U_0402_16V4Z S1_A5 24 58 S1_RST
A5 RESET S1_RST <23>
1

2 2 CP2211FD3_SSOP16 S1_A4 S1_WAIT#

25 59
7

16

R253 S1_A3 A4 WAIT# S1_INPACK# S1_WAIT# <23>

26 A3 INPACK# 60 S1_INPACK# <23>
C S1_A2 S1_REG# C
27 A2 REG# 61 S1_REG# <23>
10K_0402_5% S1_A1 28 62 S1_BVD2
S1_A0 A1 SPKR# S1_BVD1 S1_BVD2 <23>
29 63
2

S1_D0 A0 STSCHG# S1_D8 S1_BVD1 <23>

30 D0 D8 64
S1_D1 31 65 S1_D9
S1_OE# S1_D2 D1 D9 S1_D10
1 2 +S1_VCC 32 D2 D10 66
R443 43K_0402_5% S1_WP 33 67 S1_CD2#
S1_WP <23> S1_WP IOIS16# CD2# S1_CD2# <23>
2 1 +S1_VCC 34 GND GND 68
VCCD0# 1 2 R503 43K_0402_5%
R254 10K_0402_5% S1_RST 1 2 +S1_VCC 69 77
VCCD1# R491 43K_0402_5% GND GND
1 2 70 GND GND 78
R257 10K_0402_5% S1_CE1# 1 2 +S1_VCC 71 79
R426 43K_0402_5% GND GND
72 GND GND 80
S1_CE2# 1 2 +S1_VCC 73 81
R432 43K_0402_5% GND GND
74 GND GND 82
75 GND GND 83
76 GND GND 84

FOX_1CA41521-EL-4F_68P_LT

+VCC_SD

1 1 1
C371 C367 C368

B 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J3IN1 B

+3VS 2 2 2
+VCC_SD 6 VDD_SD
+3VS SDDA0_XDD7
40mil <23> SDDA0_XDD7
SDDA1_XDD0
9 DAT0_SD
<23> SDDA1_XDD0 10 DAT1_SD
2

+3VS +VCC_SD SDDA2_XDCL 2

<23> SDDA2_XDCL DAT2_SD
2

R264 SDDA3_XDD4 3
<23> SDDA3_XDD4 CD/DAT3_SD
R265 U17 SDCK_XDWE# 7
<23> SDCK_XDWE# CLK_SD
1 8 10K_0402_5% SD_WP# 11
GND OUT <23> SD_WP# WP_SD
10K_0402_5% 2 7 SDCM_XDALE 4
<23> SDCM_XDALE
1

IN OUT SD_CD# CMD_SD

3 6 <23> SD_CD# 1
1

SD_PWREN# IN OUT SDOC# CD_SD

<23> SD_PWREN# 4 EN# FLG 5 SDOC# <23> 5 VSS_SD
8 VSS_SD
G528_SO8
1

R261 Reserve for SD,MS CLK. <23> MSD1_XDD6 MSD1_XDD6 1 2 19

R538 0_0402_5% VCC_MS
+VCC_SD 13 VCC_MS
0_0402_5% Close to Socket <23> MSCLK_XDRE#
MSCLK_XDRE# 14
MS_INS# SCLK_MS
<23> MS_INS# 16
2

SDCK_XDWE# 1 MSD0_XDD2 INS_MS

2 <23> MSD0_XDD2 18 SDIO_MS
MS_PWREN# C369 10P_0402_50V8K <23> MSBS_XDD1 MSBS_XDD1 20
<23> MS_PWREN# BS_MS
<23> MSD3_XDD3 MSD3_XDD3 1 2 15
MSCLK_XDRE#1 MSD2_XDD5 R539 1 RESERVED_MS
2 <23> MSD2_XDD5 2 0_0402_5% 17 RESERVED_MS
C370 10P_0402_50V8K R540 0_0402_5% 21 VSS_MS
12 VSS_MS
22 GND
23 GND
PROCO_MDR019-C0-1202

A A

12/20 modified

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCMCIA Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HEL80 LA-3161P
Date: Thursday, February 23, 2006 Sheet 24 of 43
5 4 3 2 1
 5 4 3 2 1

+3VS

1 1 1 1
+2.5VS_1394

1
Laptopblue 1 1 1 U5
+3VS

C291 C270 C232 C309 C310 C277 C231 C265 1 8

A0 VCC
2 A1 WP 7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3 6 EECK
A2 SCL

1
2 2 2 2 2 2 2 2 EEDI
1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 1394@ 4 GND SDA 5
R146
AT24C02N-10SU-2.7_SO8 510_0402_5%
1394@ 1394@

2
EECK and EEDI is pull high internal
D +2.5VS_1394 +3VS External pull high circuit is unnecessary D

20mils L7 1394@
MBK1608301YZF_0603
+1394_PLLVDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 +3VS
1 1 1 1
C230 C284 C267 C279 When use external EEPROM
4.7U_0805_10V4Z
1394@ 1394@ 1394@ 1394@
Populate U14, R246, R253

111

122
110
U10 2 2 2 2 Un-populate R261

46
30
21

99
36
17

87
86
73
72
62
59
5
0.1U_0402_16V4Z

VDD4
VDD3
VDD2
VDD1
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1

PVA5
PVA4
PVA3
PVA2
PVA1
PVA0
+3VS

PCI_AD31 94
VT6311S EECS 26
27
EECS R162 1 2 @ 4.7K_0402_5%

PCI_AD30 AD31 EEDO EEDI

PCI_AD29
95
96
AD30
AD29
EEPROM SDA/EEDI
SCL/EECK
28
29 EECK
PCI_AD[0..31] PCI_AD28 97
<18,23,30> PCI_AD[0..31] PCI_AD27 AD28 C226 1
98 AD27 PHYRST# 55 2 1394@ 1U_0603_10V4Z
PCI_AD26 101 81 R173 1 2 @ 4.7K_0402_5% +3VS
PCI_AD25 AD26 BJT_CTL I2CEEN R147 1
102 AD25 I2CEN 43 2 1394@ 4.7K_0402_5% +3VS
PCI_AD24 103 32 R152 1 2 1394@ 4.7K_0402_5%
PCI_AD23 AD24 PWRDET C238 1 2 0.1U_0402_16V4Z
PCI_AD22
106
107
AD23
AD22
others REG_FB 84 REG_FB 1394@

3
PCI_AD21 109 E
PCI_AD20 AD21 REG_OUT REG_OUT Q6
113 AD20 REG_OUT 85 2
PCI_AD19 114 C229 B 2SB1197K_SOT23
PCI_AD18 AD19 R142 1 C
115 60 2 1394@ 1K_0402_5% 10P_0402_50V8K @

1
PCI_AD17 AD18 XCPS XREXT R145 1
116 AD17 XREXT 63 2 1394@ 6.19K_0603_1% 1 2 1394@
C PCI_AD16 C227 1 C
117 AD16 10mils 2 1394@ 47P_0402_50V8J

2
PCI_AD15 2 57 1394_XI Y1 REG_FB +2.5VS_1394
PCI_AD14 AD15 XI 1394@
PCI_AD13
3
4
AD14
AD13
OSCILLATOR XO 58 1394_XO 24.576MHZ_16P_X8A024576FG1H When use external BJT
PCI_AD12 7 Populate Q35, R279

1
PCI_AD11 AD12 TPB0-
8 AD11 XTPB0M 67 1 2
PCI_AD10 9 68 TPB0+
PCI_AD9 AD10 XTPB0P TPA0- C228
PCI_AD8
10
11
AD9
AD8
PHY PORT0 XTPA0M
XTPA0P
69
70 TPA0+ 10P_0402_50V8K
IDSEL:PCI_AD16 PCI_AD7 14 71 TPBIAS0 1394@
PCI_AD6 15
AD7
AD6
PCI I/F XTPBIAS0
PCI_AD16 1 2 1394_IDSEL PCI_AD5 16 74
R219 1394@ 100_0402_5% PCI_AD4 AD5 XTPB1M
18 AD4 XTPB1P 75
PCI_AD3
PCI_AD2
19
20
AD3
AD2
PHY PORT1XTPA1M
XTPA1P
76
77
PCI_AD1 24 78
PCI_AD0 AD1 XTPBIAS1
25 AD0
<18,23,30> PCI_CBE#3 104 CBE3# NC17 83
<18,23,30> PCI_CBE#2 119 CBE2# NC16 82
<18,23,30> PCI_CBE#1 1 CBE1# NC15 64
<18,23,30> PCI_CBE#0 12 CBE0# NC14 54
PCI_STOP# 125 53
<18,23> PCI_STOP# STOP# NC13
PCI_PERR# 127 52
<18,23> PCI_PERR# PERR# NC12
PCI_PAR 128 51
<18,23> PCI_PAR PAR NC11
PCI_PIRQE# 88 50
<18> PCI_PIRQE# INTA# NC10
<18,23,30> PCI_RST# 89 PCIRST# NC9 49
CLK_PCI_1394 90 48
<15> CLK_PCI_1394 PCICLK NC8
PCI_GNT0# 92 45
<18> PCI_GNT0# GNT# NC7
PCI_REQ0# 93 44
<18> PCI_REQ0# REQ# NC6
1394_IDSEL 105 42
IDSEL NC5
34 PME# NC4 41
PCI _IRDY# 121 40
B <18,23> PCI_IRDY# IRDY# NC3 B
PCI_TRDY# 123 39
<18,23,30> PCI_TRDY# TRDY# NC2
PCI_DEVSEL# 124 37
<18,23> PCI_DEVSEL#
PCI_FRAME# 120
DEVSEL# NC1
35
2/21 Add for Compliance Engineering request
<18,23,30> PCI_FRAME# FRAME# NC0
GNDARX1

GNDARX2
GNDATX1

GNDATX2

15mils
GND19
GND18
GND17
GND16
GND15
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
GND0

L42
1 1 2 2
1

1
VT6311S_LQFP128 C252
66
65
80
79
118
112
108
100
91
61
56
47
38
33
31
23
22
6
13
126

R165 R155 0.33U_0603_10V7K 4 3

1394@ 54.9_0402_1% 54.9_0402_1% 1394@ 4 3
1394@ 1394@ 2 WCM2012F2SF-121T04_0805
1394@ JP21

2
TPBIAS0
CLK_PCI_1394 TPA0+ @ R546 1 2 0_0402_5% 4 8
TPA0- @ R547 0_0402_5% TPA+ GND
1 2 3 TPA- GND 7
1

TPB0+ @ R548 1 2 0_0402_5% 2 6

R196 TPB0- @ R549 0_0402_5% TPB+ GND
1 2 1 TPB- GND 5
@ 10_0402_5%

1
SUYIN_020115FB004S512ZL
R153 R149 1394@
2

1 54.9_0402_1% 54.9_0402_1% L43

3

C289 1394@ 1394@ 1 2

1 2
2

2
@ 10P_0402_50V8K D21 D22
2 PSOT24C_SOT23 PSOT24C_SOT23 4 4 3 3

1
@ @ 1
C241 R150 WCM2012F2SF-121T04_0805
1

270P_0402_50V7K 4.99K_0402_1% 1394@

1394@ 1394@
2

2
A A

Modify WCM2012F2SF-900T04 this symbol for WCM2012F2SF-121T04

Security Classification Compal Secret Data Compal Electronics, Inc.

2005/06/20 2006/06/20 Title
Note : This page copied from HBL50 Issued Date Deciphered Date
IEEE1394 VIA VT6311S
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HEL80 LA-3161P 25
Date: Thursday, February 23, 2006 Sheet of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue
PN : SA00000TL00 (QFN64 Lead Free)
R167 2 1 3.6K_0402_5%

2 1
+3VALW
+3VALW +3VALW

U8 R144 4.7K_0402_5%
U7
C306 1 2 0.1U_0402_10V7K PCIE_PTX_IRX_P3 29 45 4 5 2
<20> PCIE_RXP3 HSOP EEDO DO GND

3
47 3 6 C224
C307 1 0.1U_0402_10V7K PCIE_PTX_IRX_N3 EDDI/AUX DI NC
<20> PCIE_RXN3 2 30 HSON EESK 48 2 SK NC 7
44 1 8 +3VALW LAN_CTRL18 1 Q7 LAN_CTRL15 1 Q8
EECS CS VCC 1
0.1U_0402_16V4Z MMJT9435T1G_SOT223 MMJT9435T1G_SOT223
<20> PCIE_TXP3 23 HSIP AT93C46-10SI-2.7_SO8
<20> PCIE_TXN3 24

2
4

2
4
D HSIN LAN_ACTIVITY# D
LED3 54
55 LED_10/100 T25 PAD
LED2 LED_1000
<15> CLK_PCIE_LAN 26 REFCLK_P LED1 56 T24 PAD 40mil 40mil
57 LAN_LINK# +LAN_VDD18 +LAN_VDD15
LED0
<15> CLK_PCIE_LAN# 27 REFCLK_N 1 2 1 2
C347 C352 C350 C353
20 3 LAN_MDI0+
<7,17,18,20,22,27,31,35> PLT_RST# PERSTB MDIP0
4 LAN_MDI0- 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
MDIN0 LAN_MDI1+ 2 1 2 1
MDIP1 6
LAN_CTRL18 1 7 LAN_MDI1-
VCTRL18 MDIN1
LAN_CTRL15 63 9 LAN_MDI2+
VCTRL15 MDIP2 LAN_MDI2-
MDIN2 10
1 2 64 12 LAN_MDI3+
R164 2.49K_0402_1% RSET MDIP3 LAN_MDI3- +LAN_VDD18
MDIN3 13

19 L8
<20,27,35> ICH_PCIE_WAKE# LANWAKEB
15 +LAN_VDD15 AVDD18 1 2
VDD15

10U_0805_10V4Z
21 BLM18AG601SN1D_0603
R200 1 VDD15
+3VS 2 1K_0402_1% 36 ISOLATEB VDD15 32 2 2 2 2 2 2 1
33 C272 C281 C288 C300 C294 C315 C531
VDD15
VDD15 38
LAN_X1 60 41 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R201 CKXTAL1 VDD15 1 1 1 1 1 1 2
VDD15 43
LAN_X2 61 49
15K_0402_5% CKXTAL2 VDD15 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDD15 52
VDD15 58
62 GVDD
12/09 Added
1 2 VDD33 16 +3VALW
C249 37 +LAN_VDD15
C248 VDD33
VDD33 53
C 1U_0603_10V4Z EGND C
0.1U_0402_16V4Z 25 EGND VDD33 46
2 1
@
1 2 31 2 AVDD33
R221 0_0603_5% EGND AVDD33
2 2 2 2 2 2
59 C275 C297 C308 C305 C247 C245
AVDD33
17 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
NC AVDD18 1 1 1 1 1 1
18 NC AVDD18 5
35 NC AVDD18 8
Y3 34 11
LAN_X1 LAN_X2 NC AVDD18
1 2 39 NC AVDD18 14
40 NC
25MHZ_20PF_6X25000017 42 NC
1 1 50 NC EVDD18 22 +LAN_VDD18
C254 C256 51 +3VALW
NC
EVDD18 28
27P_0402_50V8J 27P_0402_50V8J
2 2
RTL8111B_QFN64
+3VALW
2 2 2 2 2
L4 C298 C246 C269 C287 C282
AVDD33 1 2
1 2 BLM18AG601SN1D_0603 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
C239 C266 1 1 1 1 1

10U_0805_10V4Z 0.1U_0402_16V4Z
2 1

B GbE Transformer: GST5009 (SP050005610) MY LAN Conn. B

T22
JP22 FOX_JM74113-P2101-7F
1 24 LAN_ACTIVITY# R132 2 1 300_0402_5% 10
LAN_MDI3- TCT1 MCT1 RJ45_MIDI3- Green LED-
2 TD1+ MX1+ 23
LAN_MDI3+ 3 22 RJ45_MIDI3+ 9
TD1- MX1- +3VALW Green LED+
4 21 RJ45_MIDI3- 1
LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- PR4-
5 TD2+ MX2+ 20
LAN_MDI2+ 6 19 RJ45_MIDI2+ RJ45_MIDI3+ 2
TD2- MX2- PR4+
7 18 RJ45_MIDI1- 3
LAN_MDI1- TCT3 MCT3 RJ45_MIDI1- PR2-
8 TD3+ MX3+ 17
LAN_MDI1+ 9 16 RJ45_MIDI1+ RJ45_MIDI2- 4
TD3- MX3- PR3-
10 15 RJ45_MIDI2+ 5
LAN_MDI0- TCT4 MCT4 RJ45_MIDI0- PR3+
11 TD4+ MX4+ 14
LAN_MDI0+ 12 13 RJ45_MIDI0+ RJ45_MIDI1+ 6
TD4- MX4- PR2+
RJ45_MIDI0- 7 PR1-
1

1 1 SHLD2 14
C475 C471 0.5u_GST5009 R349 R356 RJ45_MIDI0+ 8 PR1+
SHLD1 13
0.01U_0402_16V7K 0.01U_0402_16V7K 75_0402_1% 75_0402_1% LAN_LINK# R138 2 1 300_0402_5% 12 Yellow LED-
1

2 2
1 1
2

C463 C462 R370 R378 11

+3VALW Yellow LED+
0.01U_0402_16V7K 0.01U_0402_16V7K 75_0402_1% 75_0402_1% C220
2 2 RJ45_GND LANGND
1 2
2

RJ45_GND 1 1
1000P_1206_2KV7K C221 C219
A A
Place these components 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2
colsed to LAN chip

Compal Electronics, Inc.

Title
LAN REALTEK RTL8111B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
HEL80 LA-3161P 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 26 of 43
5 4 3 2 1
 A B C D E

Mini-Express Card(Slot 1-WLAN)

Laptopblue Mini-Express Card(Slot 2-TV)

1 1
<20,26,35> ICH_PCIE_WAKE#
JP28 JP20
1 1 2 2 +3VS 1 1 2 2 +3VS
WLAN_AVTIVE R517 2 1 0_0402_5% 3 4 3 4
BT_AVTIVE R518 2 0_0402_5% 3 4 3 4
1 5 5 6 6 +1.5VS 5 5 6 6 +1.5VS
<15> CLKREQ_MCARD1# 7 7 8 8 7 7 8 8
9 9 10 10 9 9 10 10
CLK_PCIE_MCARD1# 11 12 C511 C512 11 12 C403 C404
<15> CLK_PCIE_MCARD1# 11 12 11 12
CLK_PCIE_MCARD1 13 14 13 14
<15> CLK_PCIE_MCARD1 13 14 13 14
15 16 0.1U_0402_16V4Z 0.1U_0402_16V4Z 15 16 0.1U_0402_16V4Z 0.1U_0402_16V4Z
15 16 15 16
17 17 18 18 17 17 18 18
19 20 MINI_RF_OFF# 19 20
19 20 PLT_RST# 19 20 PLT_RST#
21 21 22 22 PLT_RST# <7,17,18,20,22,26,31,35> 21 21 22 22 PLT_RST# <7,17,18,20,22,26,31,35>
<20> PCIE_RXN1 23 23 24 24 +3VALW 23 23 24 24 +3VALW
<20> PCIE_RXP1 25 25 26 26 25 25 26 26
27 28 +3VS 27 28
27 28 ICH_SMBCLK 27 28 ICH_SMBCLK
29 29 30 30 ICH_SMBCLK <15,20,35> 29 29 30 30 ICH_SMBCLK <15,20,35>
31 32 ICH_SMBDATA ICH_SMBDATA <15,20,35> 31 32 ICH_SMBDATA ICH_SMBDATA <15,20,35>
<20> PCIE_TXN1 31 32 31 32

1
<20> PCIE_TXP1 33 33 34 34 33 33 34 34
35 36 R542 35 36 USB20_N7 USB20_N7 <20>
35 36 35 36 USB20_P7
37 37 38 38 37 37 38 38 USB20_P7 <20>
39 40 10K_0402_5% 39 40
39 40 39 40
41 42 41 42

2
41 42 W IRELESS_LED# 41 42
43 43 44 44 WIRELESS_LED# <34> 43 43 44 44
45 45 46 46 45 45 46 46
47 47 48 48 47 47 48 48
49 49 50 50 49 49 50 50
51 51 52 52 51 51 52 52

53 GND1 GND2 54 53 GND1 GND2 54

2 FOX_AS0B226-S56N-7F FOX_AS0B226-S56N-7F 2

+3VS

+3VALW
MDC CONN.
1

R500 1
C488
10K_0402_5% JP23
1U_0603_10V4Z
2

2
1 GND1 RES0 2
MINI_RF_OFF# ICH_SDOUT_MDC 3 4 20mil
<19> ICH_SDOUT_MDC IAC_SDATA_OUT RES1
5 GND2 3.3V 6 +3VALW
1

D ICH_SYNC_MDC
<19> ICH_SYNC_MDC 7 IAC_SYNC GND3 8
Q33 2 RF_ON# <19> ICH_AC_SDIN1 R363 1 2 33_0402_5% 9 10
RF_ON# <31> IAC_SDATA_IN GND4
2N7002_SOT23 G ICH_RST_MDC# 11 12 ICH_BITCLK_MDC
<19> ICH_RST_MDC# IAC_RESET# IAC_BITCLK ICH_BITCLK_MDC <19>
S 1
3

C487

GND
GND
GND
GND
GND
GND
22P_0402_50V8J
2
3 ACES_88018-124G 3

13
14
15
16
17
18
02/06 Modified
Connector for MDC Rev1.5
11/9 Modify pn to SP01000FE00

+3VS

+3VALW BT MODULE CONN

1
R541

1 10K_0402_5% +BT_VCC
C485 C486

2
JP15
0.1U_0402_16V4Z 1U_0603_10V4Z BTON_LED# 1
<34> BTON_LED# 1
3

2
S
G 2 2
BTPWR_ON# 2 1 2 Q19 <20> USB20_P1 USB20_P1 3
<31> BTPWR_ON# 3

1
R384 100K_0402_5% D USB20_N1
<20> USB20_N1 4 4
SI2301BDS_SOT23 Q20 2 BTON_LED 5
2N7002_SOT23 G WLAN_AVTIVE 5
D 6 6
S BT_AVTIVE 7
1

3
7

1
W=40mils R383
8 8
+BT_VCC 9 GND1
10 GND2
1 10K_0402_5%
C482 C477 12/09 Modified MOLEX_53780-0870

2
ME@
4 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini Card / MDC CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80/81 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 27 of 43
A B C D E
 A B C D E

+VDDA
Laptopblue

1
28.7K for Module Design (VDDA = 4.702)
R496
10K_0402_5%
(output = 250 mA)
U18
60mil 40mil

2
+5VS L10 1 2 4 5 +VDDA
KC FBM-L11-201209-221LMAT_0805 VIN VOUT
1 2

2
C510 1U_0603_10V4Z 1 1 2 6 1 4.85V
DELAY SENSE or ADJ

1
1 L9 1 C373 C364 R262 1
2
R497 @ KC FBM-L11-201209-221LMAT_0805 7 1 30K_0402_1% C366
10K_0402_5% 10U_0805_10V4Z ERROR CNOISE 10U_0805_10V4Z
2 2
0.1U_0402_16V4Z 2
8 3 1

1
C337 1 R252 SD GND C374
<31> BEEP# 2 1 2

2
1U_0603_10V4Z C509 SI9182DH-AD_MSOP8

1
560_0402_5% 1 2 MONO_IN
2
1U_0603_10V4Z R259

1
C 1 2 0.1U_0402_16V4Z 10K_0402_1%
C343 1 R255 Q24
2 1 2 2 R495

2
<23> PCM_SPK# 1U_0603_10V4Z B
560_0402_5% E 2SC2411K_SC59 2.4K_0402_5%

3
C351 1 R258
<20> SB_SPKR 2 1 2
1U_0603_10V4Z

1
560_0402_5%
D3
R256 RB751V_SOD323
10K_0402_5%

2
HD Audio Codec
+AVDD_AC97 L44
2 20mil 0.1U_0402_16V4Z 1 2 2
+3VS
L13
1 2 0.1U_0402_16V4Z 40mil 1 1 1 FBM-L11-160808-800LMT_0603
+VDDA
1 1 1 C363 C372 C376
FBM-L11-160808-800LMT_0603 C358 C378
C355 10U_0805_10V4Z
10U_0805_10V4Z 2 2 2

25

38

9
2 2 2 U19
0.1U_0402_16V4Z 0.1U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
14 35 AMP_LEFT
LINE2_L FRONT_OUT_L AMP_LEFT <29>
15 36 AMP_RIGHT
LINE2_R FRONT_OUT_R AMP_RIGHT <29>
16 39 HP_C_L
MIC2_L SURR_OUT_L HP_C_L <29>
17 41 HP_C_R
MIC2_R SURR_OUT_R HP_C_R <29>
23 LINE1_L SIDESURR_OUT_L 45
MIC1_VREFO_L MIC1_VREFO_R 24 46
LINE1_R SIDESURR_OUT_R
18 CD_L CEN_OUT 43
1

R243 R244 20 44
CD_R LFE_OUT
2.2K_0402_5% 2.2K_0402_5% 19 C365 1 2 22P_0402_50V8J
CD_GND
6 ICH_BITCLK_AUDIO <19>
2

MIC1_L MIC1_C_L BIT_CLK

<29> MIC1_L 1 2 21 MIC1_L
C342 1U_0603_10V4Z
3 MIC1_R MIC1_C_R R260 1 3
<29> MIC1_R 1 2 22 MIC1_R SDATA_IN 8 2 33_0402_5% ICH_AC_SDIN0 <19>
C341 1U_0603_10V4Z
1 1 MONO_IN 12 37
C332 C333 PCBEEP PIN37_VREFO

LINE1_VREFO 29
220P_0402_50V7K 220P_0402_50V7K 11 J3 @
2 2 <19> ICH_RST_AUDIO# RESET#
LINE2_VREFO 31 1 1 2 2
<19> ICH_SYNC_AUDIO 10 SYNC 10mil JUMP_43X79
MIC1_VREFO_L 28 MIC1_VREFO_L
<19> ICH_SDOUT_AUDIO 5 SDATA_OUT
32 J6 @
MIC1_VREFO_R MIC1_VREFO_R
2 GPIO0 1 1 2 2
3 GPIO1 MIC2_VREFO 30
13 10mil JUMP_43X79
SENSE A AC97_VREF
34 SENSE B VREF 27
1
47 SPDIFI/EAPD JDREF 40 1 2
C362 R515 0_0603_5%

1
1 2 48 33 10U_0805_10V4Z
<29> SPDIF L45 FBMA-11-100505-301T 0402 SPDIFO VAUX R266 2
4 26 20K_0402_1% 1 2
DVSS1 AVSS1 R498 @ 0_0603_5%
7 42
C540
1 2/13 modify this symbol to DVSS2 AVSS2
2005/09/20
2
ALC883-LF_LQFP48
100P_0402_25V8K FBMA-11-100505-301T 0402 1 2
2 R494 @ 0_0603_5%
DGND GNDA

GND GNDA
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD CODEC ALC883
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 28 of 43
A B C D E
 A B C D E

Laptopblue +5VAMP
W=40mil
1 1 11/10 modify pn to SP02000G100
PJP3 C354 C345 JP18
+5VALW 1 2 +5VAMP SPKL+ R514 1 2 0_0603_5% SPK_L+
0.1U_0402_16V4Z 4.7U_0805_10V4Z SPKL- R512 0_0603_5% SPK_L- 1
1 2 2
PAD-OPEN 3x3m 2 2 SPKR+ R513 0_0603_5% SPK_R+
1 2 3
SPKR- R511 1 2 0_0603_5% SPK_R-
4
20mil ACES_85204-0400

1
U34
MUTE
Speaker Conn. ME@
1
10 VDD MUTE 1

2
15 2 SHUTDOWN#
C517 2 VDD SHUTDOWN#
1 0.1U_0402_16V4Z
9 SPKL- D26 D27
VOL_AMP LOUT- PSOT24C_SOT23 PSOT24C_SOT23
7 VOLUME
16 SPKR-
VOLMAX ROUT-
2 1 8

1
R501 0_0402_5% VOLMAX SPKL+
LOUT+ 11
NBA_PLUG 13 SE/BTL# SPKR+
<28> AMP_LEFT 2 1 1 2 ROUT+ 14
C520 0.47U_0603_16V4Z C514 1U_0603_10V4Z AMP_LEFT_RC 6
AMP_RIGHT_RC LIN-
<28> AMP_RIGHT 2 1 1 2 3 RIN-
C519 0.47U_0603_16V4Z C515 1U_0603_10V4Z 5
GND

1K_0402_1%

1K_0402_1%
BYPASS 4 12
BYPASS GND

1
+5VAMP
20mil +5VAMP +5VAMP

@ R506

@ R507
1 APA2068KAI-TRL_SOP16
C513

3
S
4.7U_0805_10V4Z

2
2 R523 R516
G
2 SPDIF_PLUG#

100K_0402_5% 100K_0402_5% Q27

SI2301BDS_SOT23

1
D
+5VAMP NBA_PLUG

1
1
D

1
+5VAMP SPDIF_PLUG#
R504
2
G Q28
+5VSPDIF 20mil
S 2N7002_SOT23

3
1

10K_0402_5%
R505

2
SHUTDOWN#
2 10K_0402_5% 2

1
D
2

VOL_AMP 2 Q25
<31> EC_MUTE 2N7002_SOT23
(0.65V -> 10dB ) G
1

S SPDIF_PLUG# NBA_PLUG

3
R509 R508
@
5.1K_0402_1% 1.5K_0402_1% Un-Plug H L
1 2 MUTE
1 2

R502 10K_0402_5%
D
SPDIF_PLUG# 2 C516
1 HP_Plug_In L H
Q26 G
2N7002_SOT23 @ S 0.1U_0402_16V4Z SPDIF_Plug_In L H
3

Audio Jack/USB Conn. JP19

1 1
MIC1_L 2
<28> MIC1_L 2
INT_MIC_L 3
HEAD PHONE AMP R533 HP@
<28> MIC1_R
MIC1_R 4
5
3
4
SPDIF_PLUG# 5

+
<28> HP_C_L 2 1 1 2 6 6
HPF Fc = 338Hz 0_0402_5% C521 @ 150U_D_6.3VM HP_L 7
HP_R 7

+
<28> HP_C_R 2 1 1 2 8 8
R=1K, C=0.22U for HBQ60 0_0402_5% C522 @ 150U_D_6.3VM 9
R534 HP@ SPDIF 9
<28> SPDIF 10 10
L38 20mil R535 APA@ 11
3 +HP_VDD SPKL+ 11 3
+3VS 2 1
MBK1608301YZF_0603 SPKR+
2 1 12/12 Modified USB20_N4
12 12
2 1 0_0402_5% <20> USB20_N4 13 13
SPDIF_PLUG# HPA@ 2 0_0402_5% USB20_P4 14
<20> USB20_P4 14
C532 R536 APA@ +5VSPDIF 15 15
2
G

<20> USB20_N2 USB20_N2 16

+3VS 1U_0603_10V4Z USB20_P2 16
<20> USB20_P2 17 17
3 1 HPA@ 1 +USB_VCCB 18
Q34 18
S

19 19
1

2N7002_SOT23 20
HPA@ R537 20
19

10

EC_MUTE 100K_0402_5% U38 ACES_87213-2000

HPA@ ME@
PVDD

SVDD
2
G

14 11 HP_R
2

SHDNR# OUTR
EC_MUTE# HP_L
11/10 Modify pn to SP02000BJ00
Q35
3 1 18 SHDNL# OUTL 9
2005/12/12 Modified
S

2N7002_SOT23
HPA@ BOM Structure
C533
HPA@ 1U_0603_10V4Z
Int MIC Conn.
NC-4 4
<28> HP_C_R 2 1HP_RIGHT_C 15 INR HPA@
NC-6 6 ALC883 Head Phone 15mil
<28> HP_C_L 2 1HP_LEFT_C 13 INL AMP L46 MIC1
C534 8 INT_MIC_L 1 2 FBMA-11-100505-301T 0402 1
HPA@ 1U_0603_10V4Z NC-8 1
1 2 2 2
APA@ L47 FBMA-11-100505-301T 0402
NC-12 12
APA
2/16 Add for EMI C541
1
3 GND
1 C1P NC-16 16 AMP 4 GND
2 @
8P_0402_50V8K 2
PGND

SGND

C535 3 20 ACES_88231-02001
PVss

SVss

C1N NC-20
HP@ PN : SP02000EZ00
HPA@ 1U_0603_10V4Z C HP
4 1 MAX4411ETP+_TQFN20 4
5

17

HPA@

2
C536

1U_0603_10V4Z
HPA@ 1 Security Classification Compal Secret Data Compal Electronics, Inc.
2005/12/12 Modified Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMP & Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 29 of 43
A B C D E
 5 4 3 2 1

Laptopblue
INT_KBD CONN.( TYPE "D" KB)
D Power BTN D

KSI[0..7]
KSI[0..7] <31>

KSO[0..15]
KSO[0..15] <31>

KSI1 C109 1 2 @ 100P_0402_50V8J

KSI7 C114 1 2 @ 100P_0402_50V8J
KSI6 C118 1 2 @ 100P_0402_50V8J
KSO9 C115 1 2 @ 100P_0402_50V8J
JP13 +3VALW

KSO15
25 25 TOP Side
24 24

1
KSO10 23 KSI4 C119 1 2 @ 100P_0402_50V8J 2 1
KSO11 23 KSI5 C120 @ 100P_0402_50V8J J2 @ JOPEN R267
22 22 1 2
KSO14 21 KSO0 C121 1 2 @ 100P_0402_50V8J 2 1
KSO13 21 KSI2 C123 @ 100P_0402_50V8J J5 @ JOPEN 100K_0402_5%
20 20 1 2
KSO12 19 Bottom Side

2
KSO3 19
18 18
KSO6 17
KSO8 17 KSI3 C124 @ 100P_0402_50V8J D6
16 16 1 2
KSO7 15 KSO5 C127 1 2 @ 100P_0402_50V8J 2 ON/OFF# ON/OFF# <31>
KSO4 15 KSO1 C128 @ 100P_0402_50V8J ON/OFFBTN#
14 14 1 2 <34> ON/OFFBTN# 1
KSO2 13 KSI0 C125 1 2 @ 100P_0402_50V8J 3 51ON# 51ON# <34,36>
KSI0 13
12 12
KSO1 11 DAN202U_SC70
11

1000P_0402_50V7K
KSO5 10
KSI3 10 KSO2 C129 @ 100P_0402_50V8J
9 9 1 2

1
KSI2 8 KSO4 C126 1 2 @ 100P_0402_50V8J 2
KSO0 8 KSO7 C104 @ 100P_0402_50V8J C377 D4
7 7 1 2
C KSI5 KSO8 C105 @ 100P_0402_50V8J C
6 6 1 2
KSI4 5 RLZ20A_LL34
5

1
KSO9 D 1
4

2
KSI6 4 EC_ON
3 3 <31> EC_ON 2
KSI7 2 KSO6 C106 1 2 @ 100P_0402_50V8J G
KSI1 2 KSO3 C110 @ 100P_0402_50V8J
1 1 2 S

3
1

2
KSO12 C111 1 2 @ 100P_0402_50V8J Q11
ACES_85202-2505L_25P_P1 KSO13 C112 1 2 @ 100P_0402_50V8J R268 2N7002_SOT23

10K_0402_5%

1
2005/12/21 Modified library pn:SP01000MZ00 KSO14 C113 1 2 @ 100P_0402_50V8J
KSO11 C116 1 2 @ 100P_0402_50V8J
2005/12/21 Modified footprint : ACES_88502-2501_25P KSO10 C117 1 2 @ 100P_0402_50V8J
KSO15 C122 1 2 @ 100P_0402_50V8J

B B

JP16 JP24
1 20 PCI_CBE#0 FOR PORT 80 DEBUG PORT EC DEBUG PORT
1
2 2
+5VS FOR LPC SIO DEBUG PORT 20
19 19 PCI_AD6
PCI_CBE#0 <18,23,25>
PCI_AD6 <18,23,25>
3 +3VS 18 PCI_AD4
3 18 PCI_AD4 <18,23,25>
4 17 PCI_AD2
4 17 PCI_AD2 <18,23,25>
5 16 PCI_AD0
5 16 PCI_AD0 <18,23,25>
6 15 PCI_AD1
6 CLK_14M_SIO <15> LPC_AD[0..3] 15 PCI_AD1 <18,23,25>
7 LPC_AD0 14 PCI_AD3
7 LPC_AD[0..3] <19,31,35> 14 PCI_AD3 <18,23,25>
8 LPC_AD1 13 PCI_AD5 JP26
8 13 PCI_AD5 <18,23,25>
9 LPC_AD2 12 PCI_AD7 +5VALW 1
9 12 PCI_AD7 <18,23,25> 1
10 LPC_AD3 11 PCI_AD8 2
10 11 PCI_AD8 <18,23,25> 2
11 LPC_FRAME# LPC_FRAME# <19,31,35> 10 PCI_CBE#1 EC_TX 3
11 10 PCI_CBE#1 <18,23,25> <31> EC_TX 3
12 LPC_DRQ#0 LPC_DRQ#0 <19> 9 PCI_CBE#2 4
12 9 PCI_CBE#2 <18,23,25> 4
13 PCI_RST# 8 PCI_CBE#3
13 PCI_RST# <18,23,25> 8 PCI_CBE#3 <18,23,25>
14 2 1 7 ACES_85205-0400
14 R140 10K_0402_5% 7
15 15 CLK_PCI_DB <15> 6 6 CLK_PCI_DB <15> ME@
16 SIRQ 5 +5VS
16 SIRQ <20,23,31,35> 5
17 17 4 4 PCI_RST# <18,23,25>
18 18 3 3 PCI_FRAME# <18,23,25>
19 19 2 2 PCI_TRDY# <18,23,25>
20 1 PCI_AD9
20 1 PCI_AD9 <18,23,25>
ACES_85201-2005 ACES_85201-2005
ME@
A A

Not lead free Not lead free

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD,ON/OFF,T/P,LED/B,DEBUG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 30 of 43
5 4 3 2 1
 5 4 3 2 1
Analog Board ID definition,

Laptopblue +3VALW
Please see page 3.

+3VALW

L5
FBM-L11-160808-800LMT_0603 For HEL81

2
1 2 +EC_AVCC
+3VALW +EC_AVCC
2 1 R416 Ra
C255 C261 R420
1 1 1 1 1 1 100K_0402_5%

0.1U_0402_16V4Z
C316

0.1U_0402_16V4Z
C327

0.1U_0402_16V4Z
C328

0.1U_0402_16V4Z
C502

1000P_0402_50V7K
C276

1000P_0402_50V7K
C235
0.1U_0402_16V4Z 1000P_0402_50V7K

1
1 ECAGND 2 SKU_ID
1 2
D
L6 1 D

2
FBM-L11-160808-800LMT_0603 2 2 2 2 2 2 C493
R420 Rb 8.2K_0402_5%
0.1U_0402_16V4Z
2 0_0402_5% UMA@
VGA@

1
105
127
141
11
26
37

75
U13 2 1 ECAGND
1 71 BATT_TEMP C268 0.01U_0402_16V7K

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC

EC_AVCC / AVCC
VCC
VCC
<19> GATEA20 GA20/ GPIO00/GA20 BATTEMP/AD0/GPIO38 BATT_TEMP <37>
2 72 BATT_OVP
<19> KB_RST# KBRST#/GPIO01/KBRST# BATT OVP/AD1/GPIO39 BATT_OVP <38>
<20,23,30,35> SIRQ 3 SERIRQ ADP_I/AD2/GPIO3A 73 POUT <42>
5 74 SKU_ID
<19,30,35> LPC_FRAME# LPC_FRAME# / LFRAME# AD BID0/AD3/GPIO3B
LPC_AD3 6 1 2
<19,30,35> LPC_AD3 LPC AD3/LAD3
LPC_AD2 9 AD INtput or GPI C244 0.1U_0402_16V4Z
<19,30,35> LPC_AD2 LPC AD2/LAD2
LPC_AD1 10 Host
<19,30,35> LPC_AD1 LPC AD1/LAD1 INTERFACE
LPC_AD0 12
<19,30,35> LPC_AD0 LPC AD0/LAD0
14 76 DAC_BRIG
<15> CLK_PCI_LPC CLK_PCI_EC/PCICLK DAC_BRIG/DA0/GPIO3D DAC_BRIG <16>
15 PWR 78 EN_FAN1 +3VALW
<7,17,18,20,22,26,27,35> PLT_RST# PCIRST# EN DFAN1/DA1/GPIO3D EN_FAN1 <4>
2 1 2 1 1 2 EC_RST# 42 79 IREF
+3VALW EC RST#/ ECRST# IREF2/DA2 IREF <38>
R465 @ 10_0402_5% R143 47K_0402_5% EC_SCI# 24 80
<20> EC_SCI# EC SCI#/SCI#/GPIO0E EN DFAN2/DA3/ GPIO3F PAD T23
C500 1 2 44
<20,35> PCI_CLKRUN# PM_CLKRUN#/ CLKRUN#

2
@ 22P_0402_50V8J R148 @ 0_0402_5% DA output or GPO
C233
2
FAN/PWM
12/9 Modified with pin 35 R166 Ra
25 INVT_PWM
INVT_PWM/GPIO0F/PWM1 INVT_PWM <16>
0.1U_0402_16V4Z KSI0 63 27 BEEP# 100K_0402_5%
1 KSI0/GPIO30 BEEP#/GPIO10/PWM2 BEEP# <28>
KSI1 64 30 INTERNET# 15W@
INTERNET# <34>

1
KSI2 KSI1/GPIO31 OUT BEEP/GPIO12/PWM3 ACOFF MB_ID
65 KSI2/GPI032 ACOFF/GPIO18/PWM4 31 ACOFF <36,38>
+3VALW KSI3 66 32 FAN_SPEED1
KSI3/GPIO33 FAN SPEED1/GPIO14/FANFB1 FAN_SPEED1 <4>

2
KSI4 67 33 MB_ID
KSI5 KSI4/GPIO34 FAN SPEED2/GPIO15/FANFB2 R159
68 KSI5/GPI035 Rb
2

KSI6 69
C R440 KSI7 KSI6/GPIO36 MODE# 0_0402_5% C
70 KSI7/GPIO37 PSCLK1 91 MODE# <34>
key Matrix 92 VOL_UP# 14W@
VOL_UP# <34>

1
@ 10K_0402_5% KSO0 scan PSDAT1 VOL_DN#
47 KSO0/GPIO20 PSCLK2 93 VOL_DN# <34>
KSO1 48 PS2 interface 94 STOP#
STOP# <34>
1

KSO2 KSO1/GPIO21 PSDAT2 TP_CLK

49 KSO2/GPIO22 PSCLK3 95 TP_CLK <34>
KSO3 50 96 TP_DATA
KSO3/GPIO23 PSDAT3 TP_DATA <34>
1 2 EC_PME# KSO4 51
<18> PCI_PME# R446 0_0402_5% KSO5 KSO4/GPIO24 ADB0 +3VALW
52 KSO5/GPIO25 ADB0/D0 125
KSO6 53 126 ADB1
KSO7 KSO6/GPIO26 ADB1/D1 ADB2
54 KSO7/GPIO27 ADB2/D2 128
KSO8 55 Data 130 ADB3 EC_MUTE 1 2
KSO[0..15] KSO9 KSO8/GPIO28 BUS ADB3/ D3 ADB4 R174 10K_0402_5%
56 KSO9/GPIO29 ADB4/D4 131
<30> KSO[0..15] KSO10 57 132 ADB5 KBA[0..19] INTERNET# 1 2
+3VALW KSI[0..7] KSO11 KSO10/GPIO2A ADB5/D5 ADB6 <32> KBA[0..19] R529 10K_0402_5%
58 KSO11/GPIO2B ADB6/D6 133
RP17 <30> KSI[0..7] KSO12 59 134 ADB7 ADB[0..7] EMAIL# 1 2
KSO13 KSO12/GPIO2C ADB7/D7 KBA0 <32> ADB[0..7] R530 10K_0402_5%
1 8 60 KSO13/GPIO2D KBA0/A0 111
2 7 FR D# KSO14 61 112 KBA1
KSO15 KSO14/GPIO2E KBA1/A1 KBA2
3 6 62 KSO15/GPIO2F KBA2/A2 113
4 5 FSEL# RCIRRX 89 114 KBA3
<35> RCIRRX EC URXD/KSO16/GPIO48 KBA3/A3 +5VS
PROGRAM_BTN# 90 115 KBA4
<34> PROGRAM_BTN# EC UTXD/KSO17/GPIO49 KBA4/A4
100K_1206_8P4R_5% 116 KBA5
KBA5/A5 KBA6 TP_CLK 1
KBA6/A6 117 2
+5VALW EC_SMB_DA2 88 Address 118 KBA7 R211 4.7K_0402_5%
<4> EC_SMB_DA2 EC SMD2/ GPIO47/SDA2 KBA7/A7
EC_SMB_CK2 87 BUS 119 KBA8 TP_DATA 1 2
<4> EC_SMB_CK2 EC SMC2/GPIO46/SCL2 KBA8/A8
1 2 EC_SMB_CK1 EC_SMB_DA1 86 SM BUS 120 KBA9 R216 4.7K_0402_5%
<32,37> EC_SMB_DA1 EC SMD1/GPIO44/SDA1 KBA9/A9
R191 4.7K_0402_5% EC_SMB_CK1 85 121 KBA10
<32,37> EC_SMB_CK1 EC SMC1/GPIO44/SCL1 KBA10/A10
1 2 EC_SMB_DA1 122 KBA11
R195 4.7K_0402_5% KBA11/A11 KBA12 +3VALW
KBA12/A12 123
EC_TX 34 124 KBA13
<30> EC_TX PCM_SPK#/EMAIL_LED#/ GPIO16 KBA13/A13
35 110 KBA14 KBA1 1 2
<20> SLP_S4# SB_SPKR/PWR_SUSP_LED#/ GPIO17 KBA14/A14
PWR_LED# 38 109 KBA15 R238 1K_0402_5%
<34> PWR_LED# PWRLED#/ GPIO19 KBA15/A15
B NUM_LED# 40 108 KBA16 KBA4 1 2 B
<34> NUM_LED# NUMLED#/ GPIO1A KBA16/A16
CHARGE_LED0# 99 107 KBA17 R239 1K_0402_5%
<34> CHARGE_LED0# BATT CHGI LED#/ E51CS# KBA17/A17
CHARGE_LED1# 101 106 KBA18 KBA5 1 2
<34> CHARGE_LED1# BATT LOW LED#/ E51MR0 KBA18/A18
CAPS_LED# 100 98 KBA19 R240 1K_0402_5%
<34> CAPS_LED# CAPS LED#/ E51TMR1 KBA19/A19
+3VALW SCROLL_LED# 102
<34> SCROLL_LED# ARROW LED#/ E51 INT0
SYSON 104 84 ENBKL
<33,35,40> SYSON SYSON/GPIO56/ E51 INT1 SELIO2#/ GPIO43 ENBKL <16>
97 EMAIL#
SELIO#/ GPIO50 EMAIL# <34>
EC_RSMRST# 4 135 FR D# R242
<20> EC_RSMRST# EC_RSMRST#/ GPIO02 FRD#/RD# FRD# <32>
BKOFF# 7 136 FW R# CRY1 CRY2
<16> BKOFF# BKOFF#/GPIO03 FWR#/WR# FWR# <32>
2

SLP_S3# 8 144 FSEL#

<20> SLP_S3# PM SLP S3#/GPIO04 FSEL#/SELMEM# FSEL# <32>
R436 R202 EC_LID_OUT# 16 @ 20M_0603_5%
<20> EC_LID_OUT# EC LID OUT#/GPIO06
+3VS SLP_S5# 17 41 EC_ON
<20> SLP_S5# PM SLP S05#/ GPIO07 EC ON/ GPIO1B EC_ON <30>
4.7K_0402_5% 4.7K_0402_5% EC_SMI# 18 43 AC IN
<20> EC_SMI# EC SMI#/GPIO08 AC IN/ GPIO1C ACIN <20,36>
@ @ R460 1 2 0_0402_5% 19 29 EC_THERM#
<34> USER_DEFINED# EC_THERM# <20>
1

LID_SWITCH# EC SWI#/GPIO09 ECTHERM#/GPIO11 ON/OFF#

<33> LID_SWITCH# 20 LID SW#/ GPIO0A ONOFF/GPIO18 36 ON/OFF# <30>
1 2 EC_SMB_CK2 SUSP# 21 45 ICH_POK
<17,32,33,35,40,41> SUSP# SUSP#/GPIO0B PCMRST#/GPIO1E ICH_POK <7,20>
R444 4.7K_0402_5% PBTN_OUT# 22 46 RF_ON#
<20> PBTN_OUT# PBTN_OUT#/GPIO0C WL OFF#/GPIO1F RF_ON# <27>
1 2 EC_SMB_DA2 EC_PME# 23 1 1
R452 4.7K_0402_5% EC PME#/GPIO0D EC_MUTE C335 C334
1 1 ALI/MH#/GPIO40 81 EC_MUTE <29>

4
C496 C495 82 FSTCHG
FSTCHG/GPIO41 FSTCHG <38>
83 VR_ON 10P_0402_50V8K 10P_0402_50V8K

OUT
IN
VR ON/ GPIO42 VR_ON <42> 2 2
@ 100P_0402_50V8J @ 100P_0402_50V8J 137 BTPWR_ON#
2 2 GPIO57/GPIO57 BTPWR_ON# <27>
CRY1 140 142 VGATE
XCLKO GPIO58/GPIO58 VGATE <15,20,42>
AGND

CRY2 138 143 KILL_SW#

GND
GND
GND
GND
GND
GND

XCLKI GPIO59/GPIO59 KILL_SW# <33>

NC

NC
KB910L_LQFP144
139
129
103
13
28
39

77

3
ECAGND

X1
32.768KHZ_12.5P_1TJS125DJ2A073
A A
Pin name Pin number 2/20 New pin define
90 PROGRAM_BTN# User-1
30 INTERNET# User-2
97 EMAIL# INTERNET Compal Secret Data
Security Classification
2005/10/06 2006/10/06 Title
Compal Electronics, Inc.
19 USER_DEFINED# EMAIL Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ENE-KB910L
Size Document Number R ev
2/20 New added AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 31 of 43
5 4 3 2 1
 Laptopblue
+5VALW
+5VALW

1
C497 1 2 0.1U_0402_16V4Z R488

100K_0402_5%
+3VALW +3VALW U31

2
C508 8 VCC A0 1
7 WP A1 2

1
1 2 R493 6 3
<31,37> EC_SMB_CK1 SCL A2
100K_0402_5% 5 4
SUSP# <17,31,33,35,40,41> <31,37> EC_SMB_DA1 SDA GND
0.1U_0402_16V4Z

2
AT24C16N10SC-2.7_SO8

G
5

2
2 1 3

G Vcc
B EC_FLASH# <20>

1
FWE# 4

S
Y R459
A 1
Q23
U33 2N7002_SOT23 100K_0402_5%

3
NC7SZ32P5X_NL_SC70-5

2
FWR# <31>

FOR DEBUG ONLY INT_FLASH_EN# C489 1 0.1U_0402_16V4Z

2
+3VALW
R391 1 2 100K_0402_5%

1
P

OE#
FSEL# 2 4 1 2 INT_FSEL#
<31> FSEL# A Y R392 22_0402_5%

1
R390

3
U29 10K_0402_5%

2
SN74AHCT1G125DCKR_SC70-5

+3VALW

1 2
R396 @ 0_0402_5%

12/9 Modified BOM Structure

KBA[0..19]
<31> KBA[0..19]
ADB[0..7]
<31> ADB[0..7]
1MB Flash ROM
U32
+3VALW 1MB ROM Socket
KBA0 21 31
KBA1 A0 VCC0 JP27
20 A1 VCC1 30 1
KBA2 19 C491 KBA16 KBA17
KBA3 A2 KBA15 1 2
18 A3 3 4
KBA4 17 25 ADB0 0.1U_0402_16V4Z KBA14
KBA5 A4 D0 ADB1 2 KBA13 5 6 KBA19
16 A5 D1 26 7 8
KBA6 15 27 ADB2 KBA12 KBA10
KBA7 A6 D2 ADB3 SB_INT_FLASH_SEL tie to ATI SB KBA11 9 10 ADB7
14 A7 D3 28 11 12
KBA8 8 32 ADB4 GPIO1 and pull down KBA9 ADB6
KBA9 A8 D4 ADB5 KBA8 13 14 ADB5
7 A9 D5 33 15 16
KBA10 36 34 ADB6 FWE# ADB4
KBA11 A10 D6 ADB7 RESET# 17 18
6 A11 D7 35 19 20 +3VALW
KBA12 5 INT_FLASH_EN#
KBA13 A12 R489 SB_INT_FLASH_SEL 21 22
4 A13 <20> SB_INT_FLASH_SEL 23 24
KBA14 3 10 RESET# 1 2 +3VALW KBA18 ADB3
KBA15 A14 RP# KBA7 25 26 ADB2
2 A15 NC 11 27 28
KBA16 1 12 100K_0402_5% KBA6 ADB1
KBA17 A16 READY/BUSY# KBA5 29 30 ADB0
40 A17 NC0 29 31 32
KBA18 13 38 KBA4 FR D#
KBA19 A18 NC1 KBA3 33 34
37 A19 35 36
KBA2 FSEL#
INT_FSEL# KBA1 37 38 KBA0
22 CE# 39 40
FR D# 24 23
<31> FRD# OE# GND0
FWE# 9 39 SUYIN_80065AR-040G2T
WE# GND1

SST39VF080-70_TSOP40
Not Lead Free

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 32 of 43
 A B C D E F G H I J

+5VALW to +5VS Transfer

Laptopblue +3VALW to +3VS Transfer +1.8V to +1.8VS Transfer

1 +5VALW +5VS +3VALW +1.8V 1

+3VS +1.8VS
U37 U15 U25
8 D S 1 8 D S 1 8 D S 1
1 7 D S 2 1 7 D S 2 1 7 D S 2
+VSB C529 6 3 +VSB C346 6 3 +VSB C408 6 3
D S 1 1 D S 1 1 D S 1 1
5 4 C528 C527 5 4 C349 C348 5 4 C145 C155
10U_0805_10V4Z D G 10U_0805_10V4Z D G 10U_0805_10V4Z D G
2

1
2 SI4800BDY_SO8 10U_0805_10V4Z 0.1U_0402_16V4Z 2 SI4800BDY_SO8 10U_0805_10V4Z 0.1U_0402_16V4Z 2 SI4800BDY_SO8 10U_0805_10V4Z 0.1U_0402_16V4Z
R528 2 2 R236 2 2 R304 2 2
AOS 4422 AOS 4422
10K_0402_5% 47K_0402_5% 33K_0402_5%
AOS 4422
1

2
1 1 1
1

1
2 D C530 D D 2
SUSP 2 Q32 SUSP 2 Q9 C326 SUSP 2 Q18 C407
G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K G 2N7002_SOT23 0.1U_0603_25V7K
S 2 S 2 S 2
3

3
+5VALW +5VALW +5VS +1.8VS +0.9VS +1.8V +2.5VS

3 3
1

2
R271 R525 R527 R526 R295 R296 R62

47K_0402_5% 10K_0402_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%

@ @ @ @ @
2

1 1

1 1

1 1

1 1

1 1
SYSON# SUSP
<41> SUSP D D D D D
1

1
D D
2 SUSP 2 SUSP 2 SUSP 2 SYSON# 2 SUSP
2 Q12 2 Q31 G G G G G
<31,35,40> SYSON <17,31,32,35,40,41> SUSP#
G 2N7002_SOT23 G 2N7002_SOT23 S Q30 S Q29 S Q17 S Q16 S Q3

3
S S 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
3

3
4 4

LID Switch
CMOS Camera Conn
+3VALW 1 2 R151 1 2 100K_0402_5%
R141 0_0402_5%
U6
2

+5VS
VDD

1
C223 3 1 1
OUTPUT LID_SWITCH# <31>
C385 C386
5 0.1U_0402_16V4Z 5
2
GND

2 C242 4.7U_0805_10V4Z 0.1U_0402_16V4Z

@ 2 2
10P_0402_50V8K JP11
1

A3212ELHLT-T_SOT23W-3 1
1 1
<20> USB20_N3 USB20_N3 2
USB20_P3 2
<20> USB20_P3 3 3
4 4
5 5

2
6 GND1
D14
12/9 Change to SA032120010 PSOT24C_SOT23
7 GND2
@ ACES_88266-05001
ME@

1
6 6

Finger Print board + MP3 Module CONN.

For EMI
1

D19 Kill Switch

PSOT24C_SOT23
@
+3VS
JP14 SW5
2

USB20_P5 6 8 2 1 3
<20> USB20_P5 6 G2 3
USB20_N5 5 7 R269 10K_0402_5%
<20> USB20_N5 5 G1
7 4 4 <31> KILL_SW# 2 2 7
3 3 KILL_SW#
+3VS 2 2
T15 PAD FPR_SW 1 1
1 1
1 1
C169 C170 ACES_85202-0605L
1BS003-1211L_3P
4.7U_0805_10V4Z 0.1U_0402_16V4Z
@ 2 2

ACES
8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuit
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 33 of 43
A B C D E F G H I J
 5 4 3 2 1

USB Port Laptopblue

T/P Board IOMP Board
D1
1
R6
2
100K_0402_5%
+3VALW

JP43 JP5 2 MODE# <31>

1 SWR# <35> 1 MODE_BTN# 1
1 1 VOL_UP# 51ON#
+5VS 2 2 SWL# <35> 2 2 3 51ON# <30,36>
+USB_VCCA 3 3 VOL_DN#
U3 3 3 STOP# DAN202U_SC70
4 4 TP_CLK <31> 4 4
1 8 7 5 TP_DATA <31> 7 5 IOMP@
GND OUT G1 5 G1 5
2 IN OUT 7 8 G2 6 6 +5VS 8 G2 6 6
3 IN OUT 6
2 4 5 USB_OC#0 ACES_85202-0605L ACES_85202-0605L 1 2 +3VALW
D C203 EN# FLG USB_OC#0 <20> R5 100K_0402_5% D
G528_SO8 1
0.1U_0402_16V4Z C190
1 VOL_UP# <31>
1000P_0402_50V7K
2 @

1 2 +3VALW
R8 100K_0402_5%

+USB_VCCA
VOL_DN# <31>
1000P_0402_50V7K
1
2 1
C194 + C168 C173

150U_D_6.3VM 1 2 +3VALW
2 1 2 R7 100K_0402_5%

0.1U_0402_16V4Z
STOP# <31>
JP44
1 VCC
<20> USB20_N0 2 D-
<20> USB20_P0 3 D+
2 2 4 GND
3

C419 C418 +5VS +5VS

5 GND1
D20 10P_0402_50V8K 10P_0402_50V8K 6 GND2 R272

1
C PSOT24C_SOT23 @ 1 1 @
7 D8 C
@ GND3 R543
8 GND4 1 2 1 2
1

SUYIN_020173MR004G565ZR +3VS 10K_0402_5% 300_0402_5% HT-110UD_1204

1
D
ME@

2
2 Q36 AMBER_LED#

5
G 2N7002_SOT23-3

1
D
2 S

P
<27> WIRELESS_LED#

3
B
Y 4 2
1 G
<27> BTON_LED# A

G
Q37 S

3
U20 2N7002_SOT23-3

3
NC7SZ08P5X_NL_SC70-5
+5VS +USB_VCCB
U36 +5VS
1 8 D7
GND OUT
2 IN OUT 7 R277

1
3 6 D7
IN OUT USB_OC#2 R544
1 4 EN# FLG 5 USB_OC#2 <20> 1 2 1 2
C526
G528_SO8 1 10K_0402_5% 300_0402_5% HT-110UYG-CT_YEL/GRN

1
4.7U_0805_10V4Z C525 D VALUE@ White LED

2
2 Q38 HIGH@
2
1000P_0402_50V7K G 2N7002_SOT23-3

1
2 @ D
S

3
<23> 3IN1_LED# 2
G
Q39 S

3
2N7002_SOT23-3

B +5VS B
D11
R275

1
D11
R545 1 2 1 2
+3VS 10K_0402_5% 300_0402_5% HT-110UYG-CT_YEL/GRN

1
D VALUE@ White LED

2
2 Q40 HIGH@

5
G 2N7002_SOT23-3

1
PIDE_LED# 2 D
S

P
<22> PIDE_LED#

3
B
Y 4 2
SATA_LED# 1 G
<19> SATA_LED# A

G
Q41 S
Switch Board CONN.

3
U21 2N7002_SOT23-3

3
NC7SZ08P5X_NL_SC70-5

+5VALW +5VS

JP12 +5VALW
1 1
2 D10
2 R273
3 3 <31> CHARGE_LED0# 1 2 300_0402_5% CHARGE0 2
<31> PWR_LED# 4 4
5 1
<31> EMAIL#
6
5 2/20 Modified
<31> USER_DEFINED# 6
ON/OFFBTN# 7 R274 1 2 300_0402_5% CHARGE1 3
<30> ON/OFFBTN# 7 <31> CHARGE_LED1#
<31> PROGRAM_BTN# 8 8
9 D9
<31> INTERNET# 9
10 HT-210UD/UYG_AMB/GRN
A <31> SCROLL_LED# 10 A
<31> NUM_LED# 11 11
12 D9
<31> CAPS_LED# 12
13 15 PWR_LED# R276 1 2 300_0402_5% 1 2
13 G1 <31> PWR_LED#
14 14 G2 16
HT-110UYG-CT_YEL/GRN White LED
ACES_85202-1405L VALUE@ HIGH@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INDICATE LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 34 of 43
5 4 3 2 1
 A B C D E F G H I J

New Card Power Switch Laptopblue New Card Socket (Left)

+3VALW_CARD1 +3VS_CARD1 +1.5VS_CARD1
1 Imax = 0.275A Imax = 1.35A Imax = 0.75A JP41 1
U12
60mils 1 GND
+3VS 5 3.3Vin1 3.3Vout1 7 +3VS_CARD1 1 1 1 1 1 1 <20> USB20_N6 2 USB_D-
6 8 C274 C280 C293 C286 C253 C262 3
3.3Vin2 3.3Vout2 <20> USB20_P6 USB_D+
CP_USB# 4
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z CPUSB#
5 RSV
2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
40mil 6 RSV
+3VALW 21 3.3Vaux_in Aux_out 20 +3VALW_CARD1 <15,20,27> ICH_SMBCLK 7 SMB_CLK
<15,20,27> ICH_SMBDATA 8 SMB_DATA
40mil +1.5VS_CARD1 9 +1.5V
+1.5VS 18 1.5Vin1 1.5Vout1 16 +1.5VS_CARD1 10 +1.5V
19 1.5Vin2 1.5Vout2 17 <20,26,27> ICH_PCIE_WAKE# 11 WAKE#
+3VALW_CARD1 12 +3.3VAUX
PERST1# 13 PERST#
+3VALW R163 1 2 100K_0402_5% CP_USB# 14 CPUSB# +3VS_CARD1 14 +3.3V
2 R168 1 2 100K_0402_5% CP_PE# 15 23 +3VS +3VS 15 2
SUSP# CPPE# OC# CLKREQ1# +3.3V
<17,31,32,33,40,41> SUSP# 4 STBY# 16 CLKREQ#
SYSON 3 22 RCLKEN1 CP_PE# 17
<31,33,40> SYSON SHDN# RCLKEN CPPE#

1
PLT_RST# 2 9 PERST1# +3VS 1 18
<7,17,18,20,22,26,27,31> PLT_RST# SYSRST# PERST# <15> CLK_PCIE_NC1# REFCLK-
R232 C324 19
<15> CLK_PCIE_NC1 REFCLK+
20

GND

NC1
NC2
NC3
NC4
NC5
GND

1
10K_0402_5% 0.1U_0402_16V4Z 21
2 <20> PCIE_RXN4 PERn0
R234 22
<20> PCIE_RXP4

2
PERp0

5
TPS2231PWPR_PWP24 23

11

1
10
12
13
24
10K_0402_5% CLKREQ1# GND
2 24

G Vcc
B <20> PCIE_TXN4 PETn0
4 CLKREQ_NC# <15> <20> PCIE_TXP4 25

2
Y PETp0
1 A 26 GND

1
D U14 27

3
RCLKEN1 2 Q10 NC7SZ32P5X_NL_SC70-5 GND
28 GND
G 2N7002_SOT23
3 +3VS +3VALW +1.5VS S FOXCONN 1CH4310C 26P P1 EXP_RVS 3

3
C312
1
C271
1
C273
1 (NEW)
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2 2 2
2005/11/4 Modified library pn:SP02000JC00
2005/12/9 Modified footprint to FOX_1CX43201_26P_LB

4 4
CIR +3VALW
Update Part Number to SCR36236000
1

R270
+3VALW
100_0805_5% CIR
CIR@ TPM 1.2 +3VS
2

IR1
3 4 RCIRRX
Vs OUT RCIRRX <31>
1 GND GND 2
+3VS
1
C380 TSOP36236TR_4P 1
C379

24
19
10
CIR@

1
4.7U_0805_10V4Z U35
5 CIR@ 2 1000P_0402_50V7K Base I/O Address R524 5

VSB
VDD
VDD
VDD
2 CIR@ 0 = 02Eh 4.7K_0402_5%
TPM@
LPC_AD0
* 1 = 04Eh
<19,30,31> LPC_AD0 26 28

2
LPC_AD1 LAD0 LPCPD# SUS_STAT# <20>
<19,30,31> LPC_AD1 23 LAD1 TESTB1/BADD 9
LPC_AD2 20 8 R520 1 2 TPM@ 0_0402_5%
<19,30,31> LPC_AD2 LAD2 TEST1

1
LPC_AD3 17
<19,30,31> LPC_AD3 LAD3
14 TPM_XTALO R521
D5 XTALO TPM_XTALI 4.7K_0402_5%
XTALI 13
PSOT24C_SOT23 TPM @
CLK_PCI_TPM 21 SLB 9635 TT 1.1 12/9 Modified to @
<15> CLK_PCI_TPM

2
SWL# LPC_FRAME# LCLK
<34> SWL# 3 <19,30,31> LPC_FRAME# 22 LFRAME# GPIO2 2
1 PLT_RST# 16 6
<7,17,18,20,22,26,27,31> PLT_RST# LRESET# GPIO
SWR# 2 SIRQ 27
<34> SWR# <20,23,30,31> SIRQ SERIRQ
PCI_CLKRUN# 15
<20,31> PCI_CLKRUN# CLKRUN#
6 +3VS 1 2 7 PP NC 1 6
R522 TPM@ 4.7K_0402_5% 3
NC
12

GND
GND
GND
GND
NC
SW3 SW2
6
5

6
5

SLB-9635-TT-1.2_TSSOP28

4
11
18
25
SWL# 2 4 SWL# 2 4 TPM@
C523 TPM@
Left switch 1 3 Left switch 1 3 CLK_PCI_TPM 18P_0402_50V8J
TPM_XTALI 1 2
2

2
SMT1-05_4P SMT1-05_4P

10M_0402_5%
R519 TPM@
VALUE@ HIGH@ R510 X2

1
@ 10_0402_5% 1 2
@ ESD4 @ ESD3 IN NC
4 3

1
OUT NC
2
1

TPM@ 32.768KHZ_12.5P_1TJS125DJ2A073
7 NOT LEAD-FREE NOT LEAD-FREE 7

2
C518
@ 15P_0402_50V8J TPM_XTALO 1 2
1
C524 TPM@
18P_0402_50V8J
SW4 SW1
6
5

6
5

SWR# 2 4 SWR# 2 4

Right Switch 1 3 Right Switch 1 3 Note : TPM IC Lead free status is MN

2

SMT1-05_4P SMT1-05_4P
VALUE@ HIGH@

@ ESD1 @ ESD2
8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title
1

NOT LEAD-FREE NOT LEAD-FREE New card

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HEL80 LA-3161P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 35 of 43
A B C D E F G H I J
 A B C D

ACIN BATT ONLY

Laptopblue Precharge detector
Min. typ. Max.
Precharge detector
Min. typ. Max.
H-->L 14.589V 14.84V 15.243V H-->L 6.138V 6.214V 6.359V
PJP1
@ JST_B5B-EH-A(LF)(SN) L-->H 15.562V 15.97V 16.388V L-->H 7.196V 7.349V 7.505V
1 1 +19V VIN

2 PL17
1
2 ADPIN FBMA-L18-453215-900LMA90T_1812 PR2 1

3 1 2 1K_1206_5%
3

10_1206_5%
1 2

1
100P_0402_50V8J
560P_0402_50V7K
4 4

PR1
100P_0402_50V8J

560P_0402_50V7K
PQ1

1
5 PD2 PR3 TP0610K-T1-E3_SOT23
5

PC1

PC2

PC3

PC4
RLS4148_LLDS2 1K_1206_5%
VS 2 1 1 2 3 1

12

RLZ24B_LL34
PD1
PR4
1K_1206_5%
1 2

100K_0402_5%

100K_0402_5%
2

1
PR8

PR6

PR7
1K_1206_5%

2
PR175 PC131 1 2
10K_0402_1% 0.01U_0402_25V7K
1 2 1 2

2
VS
PR5
>17.25V VIN 1M_0402_1%
1 2

10K_0402_1%

100K_0402_5%
1

1
84.5K_0402_1%
1

VS

PR9

PR13
1
PR10

PR11
0_0402_5%
1 2

1 2
PR12 ACIN <20,31>
2

2 22K_0402_1% 2 2

1 2 3 <31,38> ACOFF
P

+ PACIN
O 1 PACIN <38>
1000P_0402_50V7K

20K_0402_1%

2 - B+
1

G
0.1U_0402_16V7K

RLZ4.3B_LL34

10K_0402_1%
PU1A PQ2 2

3
1

1
PR14

LM393DG_SO8 DTC115EUA_SC70
4
PC5

PC6

PR15
PD3
Vin Detector
2

PQ3
2

3
PR16 DTC115EUA_SC70
2

2
10K_0402_1%
2 1 RTCVREF
3.3V High 18.764 17.901 17.063
Low 17.745 16.9 16.03 VL
PR17
2.2M_0402_5%
2 1

VIN

499K_0402_1%
1
RLS4148_LLDS2
2

PR18
VS

PD4

100K_0402_1%
1
PR19
PD5

2
RB751V-40TE17_SOD323-2

1 1
2 1
3.3V BATT+ 1

68_1206_5%

68_1206_5%
PD6

8
RTCVREF
PR267

PR20
RB715F_SOT323
VS
<37,39> MAINPWON 2 5

P
3 3

PU2 PQ4 +
1 7 O

0.01U_0402_25V7K
191K_0402_1%

499K_0402_1%
PR22 G920AT24U_SOT89 PR23 TP0610K-T1-E3_SOT23 <38> ACON 3 6
2

1
0.1U_0603_25V7K
PR21 560_0603_5% 200_0805_5% PU1B

PC7
PR24

PR25
1000P_0402_50V7K
560_0603_5%
1 2 1 2 3 2 2 1 CHGRTCP 3 1 LM393DG_SO8

4
OUT IN

1
PC8
0.22U_1206_25V7K
1

PC9
4.7U_0805_6.3V6K

0.1U_0603_25V7K
PC10
1U_0805_25V4Z

+CHGRTC

2
1

GND
PC11

100K_0402_5%

PRG++ 2

2
1

1
PR26

PC12

PC13
2

1
2

PR27
2

22K_0402_1% PQ5
1 2 PR28 RHU002N06_SOT323 PR29
<30,34> 51ON#

1
PJ1 34K_0402_1% D 47K_0402_5%
PAD-OPEN 3x3m PJ2 PAD-OPEN 3x3m
2 1 2 2 1
+1.5VSP 1 2 +1.5VS 1 2 +1.8V
RTCVREF G PACIN <38>
+1.8VP

1
S

3
66.5K_0402_1%
1
(6A,240mils ,Via NO.=12) (6A,240mils ,Via NO.= 12)

PR30
PJ3 PJ4 2 +5VALWP
PAD-OPEN 3x3m PAD-OPEN 3x3m @
+5VALWP 1 2 +5VALW +0.9VSP 1 2 +0.9VS

2
PQ6

3
DTC115EUA_SC70
(5A,200mils ,Via NO.= 10) (0.3A,40mils ,Via NO.= 2)
4 PJ6 PJ11 4

PAD-OPEN 3x3m PAD-OPEN 3x3m

+3VALWP 1 2 +3VALW +2.5VSP 1 2 +2.5VS

(4.5A,180mils ,Via NO.= 9)

PJ7 PJ8 Security Classification Compal Secret Data Compal Electronics, Inc.
PAD-OPEN 3x3m PAD-OPEN 3x3m 2005/10/17 2006/10/17 Title
Issued Date Deciphered Date
1 2 1 2
+1.05VSP +VCCP +VSBP +VSB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.2
(5A,200mils ,Via NO.= 10) (0.3A,40mils ,Via NO.= 2) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 36 of 43
A B C D
 A B C D

Laptopblue
BATT++ PJ13
PAD-OPEN 3x3m
PJP2 1 2 BATT+
SUYIN_200275MR009G180ZR
PH1 under CPU botten side :
BATT++
1 1
2
1 2 +3VALWP CPU thermal protection at 85 degree C
2

1000P_0603_50V7K

1000P_0603_50V7K
CNT1 PR177 @ PR178
3 3 Recovery at 70 degree C

0.01U_0603_50V7K
4 CNT2 1 2 100K_0402_5%
4 +3VALWP

1
5 EC_SMCA VS
5

1
PC14

PC15

PC16
6 EC_SMDA @ 100K_0402_5%
6 TS_A
7

2
7

2
VL

0.1U_0603_25V7K
0_0402_5%
1 8 GND 1

2
8

2
VL

PR268
9 9

PC17
G1 10

150K_0402_1%
G2 11 PR176

2
10.7K_0402_1%
1K_0402_1%

2
1

PR32
1

PR33
PR34
1 442K_0603_1%
2

1
2
100_0402_1%
1

8
100_0402_1%
PR37

PR31

PR35
161.9K_0603_1%
2 3

P
+
O 1
TM_REF1 2 MAINPWON <36,39>
-

G
100K_0603_1%_TH11-4H104FT
PU3A
2

1
LM393DG_SO8

4
PH1
1000P_0402_50V7K
EC_SMB_CK1 <31,32>

1U_0603_6.3V6M
2
1

PC18
EC_SMB_DA1 <31,32>

PC19
PR39
2 150K_0402_1%
1 VL

2
1 2 +3VALWP

150K_0402_1%
PR36

1
1K_0402_1%

6.49K_0402_1%
1

PR40
2 2
PR38

2
2

BATT_TEMP <31>

PQ7
TP0610K-T1-E3_SOT23 VS
B+ 3 1 +VSBP
0.22U_1206_25V7K

0.1U_0603_25V7K
1

8
100K_0402_5%

1
PR41

PC20

PC21 5

P
+
O 7
6
2

G
PR42
2

22K_0402_1%

4
VL 1 2 PU3B
LM393DG_SO8
100K_0402_5%
2
PR43

3 3

PR44
1

0_0402_5% D
1 2 2
<39> SPOK G
0.1U_0402_16V7K

S PQ8
3
1

PC22

RHU002N06_SOT323
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 37 of 43
A B C D
 A B C D E

75W PR45=0.02_2512_1% PR54=23.7K_0402_1% Iadp=0~3.71A

90W PR45=0.15_2512_1% Laptopblue
PR54=28.7K_0402_1% Iadp=0~4.3A Fosc=14100/Rt=14100/47=300KHz Charger
P2 PR45
B+ PQ11
PQ10

D
PQ9
AO4407_SO8
S s AO4407_SO8 D P3
0.015_2512_1%
1
AO4407_SO8
8
8 1 1 8 4 1 2 7
PL18
VIN 7
6
2
3
2
3
7
6 3 2 FBMA-L18-453215-900LMA90T_1812 CHG_B+ 3 6
5
5 5 1 2

4.7U_1206_25V6K

4
200K_0402_1%

2200P_0402_50V7K
0.1U_0603_25V7K

4.7U_1206_25V6K

0.1U_0603_25V7K
1 1
G G

4
1
1

1
PC27

PR46

PC23

PC24

1
PC25

PC26
P2
1

47K_0402_5%

PR48

2
PR47

47K_0402_1%

2
1 2
VIN

0_0603_5%

10K_0402_1%
2

2
PR49
PQ12
E PU4

PR50
DTA144EUA_SC70 MB39A126PFV-ER_SSOP24
47K
1 -INC2 +INC2 24

3
2
1
2 PR51 PC28 PR52

2
47K
10K_0402_1% 4700P_0402_25V7K 100K_0402_1%

1
B MB39A126 1 2 1 2 2 1 2 OUTC2 GND 23
PC29 4 PQ13
ACOFF#

0.22U_0603_16V7K AO4407_SO8
1.292V

1
3 22 CS 1 2
1

+INE2 CS
1

C PC30
0.1U_0603_25V7K

10K_0402_1%
0.01U_0402_25V7K

28.7K_0402_1%
4 -INE2 VCC 21 1 2

1
2 ACOFF ACOFF <31,36>

5
6
7
8
1

PC31

PR53

PR54
2
5 ACOK OUT 20
PC32
2

5v 0.1U_0603_25V7K PQ14
2

3
PQ15 DTC115EUA_SC70

LXCHRG
6 19 1 2
3

VREF VH
1

150K_0402_1%

0.22U_0603_16V7K
DTC115EUA_SC70
PR55
1

1
D PC33 PL5 PR56
7 18
PR57 PC34 ACIN XACOK PR58 VIN 10U_LF919AS-100M-P3_4.5A_20% 0.02_2512_1%
2
G 1K_0402_1% 2200P_0402_50V7K 47K_0402_1% 1 2 1 4 BATT+ BATT+
2

2 MB39A1261 2
S 2 1 2 8 17 1 2
3

-INE1 RT

1
47K_0402_5%

EC31QS04

EC31QS04
PQ16 2 3

PD10

PD11
RHU002N06_SOT323

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
PR59
9 +INE1 -INE3 16
PR60 PR61 PR62 PC35

1
PC36

PC37

PC38
IREF 133K_0402_1%
<31> 10K_0402_1% 33K_0402_1% 1500P_0603_50V7K

2
1 2 2 1 10 15 MB39A126 1 21 2

2
OUTC1 FB123
1

2
100K_0402_1%

0.01U_0402_25V7K

2
1

PC39

G 11 14
SEL CTL

47K_0402_5%
PR63

S PQ17 PC40
3

1
RHU002N06_SOT323 10P_0402_50V8J
2

PR64
12 -INC1 +INC1 13 1 2

0_0402_5%
2

PR65

2
PD12
RLS4148_LLDS2
ACOFF# 1 2 2

PR66
22K_0402_1% +3VALWP
<36> PACIN 1 2 PC41
47K_0402_5%

CS 47P_0402_50V8J
1

IREF=0.932*Icharge 1 2
PR67

IREF=0.466~2.8V
<36> ACON
2

3 3
2
LI-3S :13.5V----BATT-OVP=1.5V
1

CC=3A
PQ18
BATT-OVP=0.111*BATT+ (100K/(100K+133K))*2.8V=1.2V
3

DTC115EUA_SC70

<31> FSTCHG
2
BATT+
1.2/(20*0.02)=3A

499K_0402_1% 340K_0402_1%
1
PQ19 VS
3

PR68
DTC115EUA_SC70

0.01U_0402_25V7K

2
CP Point=4.3A

PC42

1
5V*(10K/(28.7k+10k))=1.292V

PR69
2
1.292V/(15*0.02)=4.3A

2
8
PU12B
+ 5

P
VS <31> BATT_OVP 7 0
- 6
G

105K_0402_1%
1

0.01U_0402_25V7K
LM358ADR_SO8
4

1
PR72
Charge voltage
8

PC43
PU12A
3 3S CC-CV MODE : 12.6V
P

2
+
1

2
0
4
- 2 SEL is L 4
G

LM358ADR_SO8
4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 38 of 43
A B C D E
 A B C D

B+

2 Laptopblue
PL19
FBMA-L18-453215-900LMA90T_1812

PC45 PC46
1

0.1U_0603_25V7K 0.1U_0603_25V7K

2
1 2 BST5B PD13 BST3B 1 2

1 B+++ 1

B+++

SI4800BDY-T1-E3_SO8
2200P_0402_50V7K VL

8
7
6
5
10U_1206_25VAK
CHP202UPT_SOT323-3

1
D
D
D
D
1

2
PC48

0_0603_5%
PQ21
B+++
PC47

PR74

SI4800BDY-T1-E3_SO8
2200P_0402_50V7K
2

0.1U_0402_16V7K
47_0402_5%

10U_1206_25VAK
2

5
6
7
8
S
S
S

4.7_1206_5%

4.7_1206_5%

PR75

1
PR76

PR77

PC49
PR78

D
D
D
D
1
2
3
4

PC50

PC51

PQ20
0_0603_5%

2
5HG 1 2 DH5

2
2

G
S
S
S
LX5

SI4810BDY-T1-E3_SO8
@

4
3
2
1
8
7
6
5

2
0.1U_0603_25V7K
PC52
1U_0805_25V4Z

0_0603_5%
PR79
VL 3HG

D
D
D
D
PQ29
LX3

2
2VREF_1999

5
6
7
8
4.7U_0805_6.3V6K

1 PC55

SI4810BDY-T1-E3_SO8
1
G
S
S
S

1U_0805_16V7K

499K_0402_1% 200K_0402_1%

499K_0402_1% 200K_0402_1%

D
D
D
D
1

2
PC53

PR80

PR81
1
2
3
4

PQ30
BST3A

PC54
4.7UH_PCMC063T-4R7MN_5.5A_20%

G
S
S
S
0_0603_5%
DL5

PR82
2 1

4
3
2
1
2

18

20

13

17

2
PL7

PR83
BST5A 14

V+
LD05

TON

VCC

1
BST5

PR84
2
ILIM3 5 2

4.7UH_PCMC063T-4R7MN_5.5A_20%
16 DL3
DH5
+5VALWP
1

2
15

1
LX5
19 DL5 ILIM5 11

PL8
21 OUT5
9 PU6 28
FB5 BST3
10.2K_0402_1%

1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2

24

1
DL3
150U_V_6.3VM_R18

PR85

6 SHDN# LX3 27
VS 4 22
1 ON5 OUT3
1 2 3 ON3
PC56

+ PR86 7
1

@ 0_0402_5% FB3
12 SKIP# PGOOD 2 +3VALWP
2 2VREF_19998

PRO#
LDO3
PZD1 PR88

GND
REF
2

2
0_0402_5%

0_0402_5% @ 3.57K_0402_1%
RLZ5.1B_LL34 47K_0402_5% PR89
PR87

PR90
1 2 1 2 10_0402_5%2

150U_V_6.3VM_R18
23

25

10
0.047U_0603_16V7K

0.22U_0603_16V7K
1

14.7U_0805_6.3V6K
100K_0402_5%
1

1
2

PC59

PC58
+
PR91

PC57

2
PC60

0_0402_5%
<37> SPOK
2

2
2

PR92

2
1

PR93
PR94
+5V Ipeak = 6.66A ~ 10A 47K_0402_5%
1 2
0.047U_0603_16V7K

3 3

1
1

PC61
2

+3.3V Ipeak = 6.66A ~ 10A

MAINPWON <36,37>
1U_0603_6.3V6M
1

PC62
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 39 of 43
A B C D
 5 4 3 2 1

Laptopblue

D D

OZ813_B+

PL20
FBMA-L18-453215-900LMA90T_1812
1 2 B+
+3VALWP

10U_1206_25VAK
SI4800BDY-T1-E3_SO8

1
1K_0402_1%

PC63
1.8VS2N

D 5
D 6
D 7
D 8
1.8VS2P

PR261

2
PQ22
PR262
@ 0_0402_5%
1 2 @

4 G
3 S
2 S
1 S
PR272 PL10
+5VALWP 0_0603_5% 3.3UH_MPL73-3R3_6A_20% 28mohm
PR266 DH_1.8V-1 DH_1.8V-2
0_0402_5% 1.8VSET
1 2 1 2 +1.8VP OCP=6A

220U_D2_4VM_R15
2 1 LX_1.8V

1
<31,33,35> SYSON

51_0402_1%
SI4810BDY-T1-E3_SO8
1

5
6
7
8
0.01U_0402_25V7K

4.7_1206_5%

PR95
PC65
1

0.1U_0603_25V7K
PC184

PR274

PC66
1000P_0402_50V7K PR97 +

D
D
D
D
2
100K_0402_1%

2
1

PQ23
1 2 1 PR98
2
2

2
2

PC67
PC68 22K_0402_1%

G
S
S
S
PU7 6800P_0402_25V7K

25

24
23
22
21
20
19

1
C 1.8VS2P 1 2 C

4
3
2
1
2

2
22_0402_1%

680P_0603_50V7K
1K_0402_1%

PC185
CS2P
GNDA

CS2N
VSET2

PGD2
LX2
HDR2
PR99

PR100
@

DL_1.8V

2
RB751V-40TE17_SOD323-2

4700P_0402_25V7K
PD16 1.8VS2N
PR101 1 18 BST_1.8V 1 2

1
ON/SKIP2 BST2

1
PC69
22P_0402_50V8J

PC70
0_0402_5% 2 17
DREF VIN LDR2
2 1 3 VREF VDDP 16 +5VALWP
4 15

2
TSET GDNP

1
0.022U_0402_16V7K

0.1U_0603_25V7K

5 VDDA LDR1 14
2
24K_0402_1%

100K_0402_1%
6 13 PC71 +5VALWP
ON/SKIP1 BST1
1

0.01U_0402_25V7K
PR103

PC72

PC73

PC74
1U_0603_6.3V6M
1U_0805_16V7K
OZ813LN_QFN24

2
PR104

PC75

VSET1

PGD1

HDR1
CS1N
CS1P
2

LX1
PD17
1

2.2U_0603_6.3V6K
PR105 BST_1.05V1 2
1

@ 75K_0402_1% OZ813_B+

7
8
9
10
11
12

1
RB751V-40TE17_SOD323-2

PC156
PC76

0_0402_5%
0.1U_0603_25V7K

2
1.8VSET

PR263

2
DH_1.05V-1 PL11
3.3UH_MPL73-3R3_6A_20% 28mohm
2

1.05SET @ LX1.05V 1 2 +1.05VSP OCP=6A

1
2

1
PR106
1

51_0402_1%
1.05VS1P

DL_1.05V

4.7_1206_5%
150K_0402_1%
PR172

PR275

PR107

220U_D2_4VM_R15
61.9K_0402_1% PC77 1

2
0_0603_5%
1000P_0402_50V7K 1.05VS1N
1

PR273

PC78
PR108 +
1

2
5
6
7
8

SI4800BDY-T1-E3_SO8
100K_0402_1%

2
10U_1206_25VAK
1 2 1 PR109
2

D
D
D
D
1

1
2

1K_0402_1%
PC8029.4K_0402_1%

DH_1.05V-2
1

680P_0603_50V7K
PR264

PC79

PC186
B 5600P_0402_50V7K B

PQ24
1.05VS1P 2 1

2
G
S
S
S
PR179
2

4
3
2
1
0_0402_5% @

4700P_0402_25V7K
1 2 1.05VS1N
<17,31,32,33,35,41> SUSP#
1

1
PC81
22P_0402_50V8J

PC82
+3VALWP
PC132

5
6
7
8

SI4810BDY-T1-E3_SO8
@ 0.1U_0402_16V7K
2

2
D
D
D
D
PQ31
G
S
S
S
4
3
2
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
1.05VP/1.8VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 40 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue

PJ17
D PAD-OPEN 3x3m D

B+ 1 2

10U_1206_25VAK
PHASE_VCCPP

PC83
PR265
10K_0402_1% UG_VCCPP-1
1 2 PR110

2
1 2 1 2

0_0603_5% PC85 0.1U_0402_16V7K

+5VS

2
0_0603_5%
BOOT_VCCPP
PR111

1PR269
@4.7_0603_5%

5
6
7
8
17

16

15

14

13
PU8 PQ26

D
D
D
D
2
1 PR1122 6269_VCC

PHASE
GND

PGOOD

UG

BOOT
4.7_0603_5%

G
S
S
S
1 VIN PVCC 12 1 2 PC86
SI4800BDY-T1-E3_SO8

4
3
2
1
2.2U_0603_6.3V6K
UG_VCCPP-2 OCP=6A
6269_VCC 2 11 LG_VCCPP
VCC LG PL13
1 2 +1.5VSP
PR113 3.3UH_MPL73-3R3_6A_20%

1
1 2 3 FCCM PGND 10 1

5
6
7
8
PC87
2.2U_0603_6.3V6K 0_0402_5% PQ27 + PC88

D
D
D
D
PR114
C
2 SI4810BDY-T1-E3_SO8 220U_D2_4VM_R15 C
1 2 4 9 ISEN_VCCPP
1 2
<17,31,32,33,35,40> SUSP# EN ISEN PR115 2

COMP

G
S
S
S
8.66K_0402_1%

FSET
47K_0402_5%
1

VO
FB

4
3
2
1
PC89
0.01U_0402_25V7K
2

8
ISL6269CRZ-T_QFN16

1
22P_0402_50V8J
1

PR117
PR116 PC90
PC91

49.9K_0402_1% 0.01U_0402_25V7K

2
2

2
1
57.6K_0402_1%
PC92
6800P_0402_25V7K
2 PR118
1 2

4.53K_0402_1%

1
PR119
3K_0402_1%
+1.8VP

B +3VS B
2

1
PJ9

1
+5VS JUMP_43X118
1

2
PJ10
1

JUMP_43X79

2
1

PC93 PU9
1 6 +3VALWP
2

1U_0603_6.3V6M VIN VCNTL

2

2 GND NC 5

1
6

1
PU10 PC94 3 7 PC95
PC96 22U_1206_6.3V6M VREF NC 1U_0603_6.3V6M
5
VCNTL

2
VIN 22U_1206_6.3V6M PR120
7 4 8
2

POK 1K_0402_1% VOUT NC

VOUT 4
PR121 9

2
TP
VOUT 3 +2.5VSP
33K_0402_1% 1
1

1 2 8 2 PR123 APL5331KAC-TRL_SO8
EN FB
1

,31,32,33,35,40> SUSP#
22U_1206_6.3V6M

PR122 + PC98 RHU002N06_SOT323

GND

+0.9VSP

1
PQ28 D
PC97

9 PC99 @ 150U_D_6.3VM 0_0402_5%

2

VIN
1

1
2.15K_0402_1% 1 2 2
2

1
PC100 2 <33> SUSP G PR124 PC101
1

0.01U_0402_25V7K S 1K_0402_1% 0.1U_0402_16V7K PC102

2

2
1

APL5912-KAC-TRL_SO8 22U_1206_6.3V6M

2
1

0.01U_0402_25V7K PC103
@ 0.1U_0402_16V7K
2

PR125
1K_0402_1%
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title
+VCCPP/+2.5VSP/0.9VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 41 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue +5VS

CPU_B+ B+
PR214 PL14
5VS12 1 FBMA-L18-453215-900LMA90T_1812
1 2

0.01U_0402_25V7K
0_1206_5%

2200P_0402_50V7K
0.1U_0603_25V7K
PR215

PC157
10_0402_5% 1

1
100U_25V_M
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK
200K_0402_5%

PC159

PC160

PC161

PC162

PC163

PC158
+ PC187

2
2 PR216 1
680P_0402_50V7K

2
D D

2
PC164

2
2.2U_0603_6.3V6K 2

2
PR217 PC165

1
13K_0402_5% 1U_0603_6.3V6M

5
PQ32
PU11 SI7840DP-T1-E3_SO8

1
NTC 2.2_0603_5%
100K_0402_5% V CC 19 25 PR270
Vcc VDD
PR218 1 2DH1_CPU-2
4
1 2 6 8 0_0603_5% 0.22U_0603_16V7K
THRM TON PR220 PC166
PR219 0_0402_5% 2 1 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2
<5> CPU_VID0 D0 BST1 +CPU_CORE

3
2
1
PR221 0_0402_5% 2 1 32 29 DH1__CPU-1 PL15
<5> CPU_VID1 D1 DH1 P_0.36H_ETQP4LR36WFC_24A_20%

4.7_1206_5%
PR222 0_0402_5% 2 1 33 28 LX1__CPU 2 1 +CPU_CORE
<5> CPU_VID2 D2 LX1

680P_0603_50V7K 2.1K_0402_1%
PR223 0_0402_5% 2 1 34 26 DL1__CPU
<5> CPU_VID3 D3 DL1

5
6
7
8

5
6
7
8

10_0402_5%
PR224

PR226
PR225 0_0402_5% 2 1 35 27 PQ33
<5> CPU_VID4 D4 PGND1 AO4410_SO8
PR227 0_0402_5% 2 1 36 18
<5> CPU_VID5

2
D5 GND

1
3.48K_0402_1%

1
AO4410_SO8
PR228 0_0402_5% 1 2 37 17 CSP1__CPU 4 4 PR230 PH2 NTC
<5> CPU_VID6 D6 CSP1

1
PQ34
1 2 1 2

DL1__CPU
PR2322 71.5K_0402_1%
1 7 16 CSN1_CPU
TIME CSN1 10KB_0603_5%_ERTJ1VR103J<5> VCCSENSE

PC167

@ PR229
2

2
2 1 9 12 FB_CPU 1 2

3
2
1

3
2
1
470P_0402_50V8J PC168 CCV FB
1 2 11 10 C CI_CPU PC169 0.22U_0603_16V7K
C REF CCI C

1 2 PC170 0.22U_0603_16V7K 39 21 DH2_CPU-1

<7,20> DPRSLPVR DPRSLPVR DH2
PR233 499_0402_1%

2
1 2 40 20 BST2_CPU
<4,19> H_DPRSTP# DPRSTP BST2
PR234 0_0402_5% PR235
1 2 3 22 LX2_CPU PR237 0_0402_5% 100_0402_5%
<5> H_PSI# PSI LX2
PR236 0_0402_5% 1 2
+3VS 2 24 DL2__CPU

1
PWRGD DL2 PR238 3K_0603_1% PC171 0.022U_0402_16V7K

0_0603_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2

PR239
2

38 14 CSP2_CPU PR242 2.61K_0402_1% <BOM Structure>

PR240 PR241 SHDN CSP2
1 2 1 2
PR244 10K_0402_1% @ 2K_0402_1% 5 15 CSN2__CPU

1
0_0402_5% VRHOT CSN2 PR243 100_0402_5%

2
4 13
1

POUT GNDS PC172

1 2 1 2 1 2

BSTM2_CPU
<15,20,31> VGATE 0_0402_5% 4700P_0402_25V7K

1
@ PR247 NTC PR245 PR246
1 2 @ 3K_0603_1% @ 3K_0603_1%
<15> CLK_ENABLE# MAX8770GTL+_TQFN40

2
1 2 1 2
1 2 PC174
<31> VR_ON
1000P_0402_50V7K PC173
1
2

CPU_B+

0.22U_0603_16V7K
PR249 PR248 470P_0402_50V8J

1
0_0402_5% PR250 +3VS 2 20K_0402_1%

PC175
@ 10K_0402_5%
1

PR251

2200P_0402_50V7K
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK

0.1U_0603_25V7K
@ PR252 100_0402_5%
1

56_0402_5%

1
PC176

PC177
1

PC178

PC179

PC180
B PR253 0_0402_5% PQ35 B
2

1 2 VSSENSE SI7840DP-T1-E3_SO8
29.6

2
<4> H_PROCHOT# <5> VSSENSE 2.2_0603_5%
PR271
1

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1 2 PR255
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2

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PC181
2

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2
1
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1

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7
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6
7
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PR258

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1

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1 2 1 2

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A PR260 0_0402_5% PC183 0.22U_0603_16V7K A

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 42 of 43
5 4 3 2 1
 5 4 3 2 1

Laptopblue

D D

CF10 CF13 CF7 CF3 CF8 CF2 CF1 CF4 CF5 CF9
1 1 1 1 1 1 1 1 1 1

CF11 CF12 CF6 CF14

1 1 1 1

FM3 FM1 FM4 FM2

1 1 1 1

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
C HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA C

2/13 Modified

1
H11 H12 H13 H14 H15 H17 H18 H19 H20
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
H21 H22 H23 H24 H25 H26 H27 H16
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
B B

H28 H29 H30 H31 H32 H33 H34

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
2/13 New added

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/17 Deciphered Date 2006/10/17 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Holes
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 23, 2006 Sheet 43 of 43
5 4 3 2 1