Ordering number : EN5792B

Monolithic Digital IC

LB1991V For Fan Motor

3-phase Brushless Motor Driver
Overview
The LB1991V is a 3-phase brushless motor driver IC that is optimal for driving the DC fan motor.

Functions
• 3-phase full-wave voltage drive technique (120° voltage-linear technique)
• Torque ripple correction circuit (overlap correction)
• Speed control technique based on motor voltage and current control
• Built-in FG comparators
• Built-in thermal shutdown circuit

Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VCC1 max 10 V
VCC2 max 11 V
VS max 11 V
Applied output voltage VO max VS+2 V
Maximum output current IO max 1.0 A
Allowable power dissipation Pd max Independent IC 440 mW
Operating temperature Topr -20 to +75 °C
Storage temperature Tstg -55 to +150 °C

Allowable Operating Ranges at Ta = 25°C

Parameter Symbol Conditions Ratings Unit
Supply voltage VCC1 VCC1 ≤ VCC2 2.7 to 6.0 V
VCC2 3.5 to 9.0 V
VS Up to VCC2 V
Hall input amplitude VHALL Between Hall effect element inputs ±20 to ±80 mVp-p

Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.

10709 MS/73099TH (OT)/53098RM (OT) No.5792-1/7

 LB1991V
Electrical Characteristics at Ta = 25°C, VCC1 = 3V, VCC2 = 4.75V, VS = 1.5V
Ratings
Parameter Symbol Conditions Unit
min typ max
Supply Current
VCC1 current drain ICC1 IOUT = 100mA 3 5 mA
VCC2 current drain ICC2 IOUT = 100mA 7.0 10.0 mA
VCC1 quiescent current ICC1Q VSTBY = 0V 1.5 3.0 mA
VCC2 quiescent current ICC2Q VSTBY = 0V 100 µA
VS quiescent current ISQ VSTBY = 0V 75 100 µA
VX1
High side residual voltage VXH1 IOUT = 0.2A 0.15 0.22 0.29 V
Low side residual voltage VXL1 IOUT = 0.2A 0.15 0.20 0.25 V
VX2
High side residual voltage VXH2 IOUT = 0.5A 0.25 0.40 V
Low side residual voltage VXL2 IOUT = 0.5A 0.25 0.40 V
Output saturation voltage VO(sat) IOUT = 0.8A, Sink + Source 1.4 V
Overlap O.L RL = 39Ω × 3, Rangle = 20kΩ *2 72 80 87 %
High/low overlap difference ∆O.L (Average upper side overlap) – -8 +8 %
(Average lower side overlap) *2
Hall Amplifiers
Input offset voltage VHOFF Design target *1 -5 +5 mV
Common-mode input voltage range VHCM Rangle = 20kΩ 0.95 2.1 V
I/O voltage gain VGVH Rangle = 20kΩ 25.5 28.5 31.5 dB
Standby Pin
High-level voltage VSTH 2.5 V
Low-level voltage VSTL 0.4 V
Input current ISTIN VSTBY = 3V 25 40 µA
Leakage current ISTLK VSTBY = 0V -30 µA
FRC Pin
High-level voltage VFRCH 2.5 V
Low-level voltage VFRCL 0.4 V
Input current IFRCIN VFRC = 3V 25 30 µA
Leakage current IFRCLK VFRC = 0V -30 µA
VH
Hall supply voltage VHALL IH = 5mA, VH(+) − VH(−) 0.85 0.95 1.05 V
(−) pin voltage VH(−) IH = 5mA 0.81 0.88 0.95 V
FG Comparator
Input offset voltage VFGOFF -3 +3 mV
Input bias voltage IbFG VFGIN+ = VFGIN− = 1.5V 500 nA
Input bias current offset ∆IbFG VFGIN+ = VFGIN− = 1.5V -100 +100 nA
Common-mode input voltage range VFGCM 1.2 2.5 V
Output high-level voltage VFGOH At the internal pull-up resistors 2.8 V
Output low-level voltage VFGOL At the internal pull-up resistors 0.2 V
Voltage gain VGFG Design target *1 100 dB
Output current (sink) IFGOS For the output pin low level 5 mA
Thermal shutdown
Operating temperature TSD Design target *1 180 °C
Temperature hysteresis ∆TSD Design target *1 20 °C
*1: Design target values in the conditions column are not tested.
*2: The standard for overlap is the value as measured.

No.5792-2/7
 LB1991V
Package Dimensions
unit : mm (typ)
3175C Pd max -- Ta
0.5

Allowable power dissipation, Pd max -- W

7.8 0.44

24 13 0.4

0.3

5.6
7.6
0.264

0.5
0.2

1 12
0.65 0.15
0.1
(0.33) 0.22
1.5max
(1.3)

0
-20 0 20 40 60 75 80 100
Ambient temperature, Ta -- °C
0.1

SANYO : SSOP24(275mil)

Pin Assignment
FGOUT

FGIN+
FGIN−

STBY
WIN2

WIN1

UIN2

UIN1
VIN2

VIN1

GND
FRC

24 23 22 21 20 19 18 17 16 15 14 13

LB1991V

Top view
1 2 3 4 5 6 7 8 9 10 11 12
VCC1

VCC2

VS

NC

UOUT

RF

VOUT

RF

WOUT

VH+

VH−

ANGLE

Truth Table
Hall input
Source phase → Sink phase FRC
U V W
V→W H
1 H H L
W→V L
U→W H
2 H L L
W→U L
U→V H
3 H L H
V→U L
W→V H
4 L L H
V→W L
W→U H
5 L H H
U→W L
V→U H
6 L H L
U→V L
Note: The “H” entries in the FRC column indicate a voltage of 2.50V or higher, and the “L” entries indicate a voltage of 0.4V or lower. (When VCC1 is 3V.)
At the Hall inputs, for each phase a high-level input is the state where the (+) input is 0.02V or higher than the (−) input. Similarly, a low-level input is the
state where the (+) input is 0.02V or lower than the (−) input.

No.5792-3/7
 VCC2
2
Forward/ Power to the hatch blocks is supplied from VCC2.
FRC 14 reverse 3 VS
switching
3I Current R5
Block Diagram

UIN1 16 U-V 0 distribution

V-W 3I R5
U W-U
UIN2 17 B 5 UOUT
R5
VIN1 18
R5
V
VIN2 19 B 7 VOUT
R5
WIN1 20
R5
W

Synthesized signal level shifters

WIN2 21 B 9 WOUT

Hall input synthesis (matrix)

Drive signal current generation block
Hall amplifiers 6 RF
ANGLE 12 8 RF
I=O.L×VO1/(1.5×R5) TSD
VS/2
1.2V reference 1 VCC1
Upper/lower
voltage and bias
LB1991V

VCC2 amplitude startup circuit 15 STBY

2×R1 limiters

SBD SBD Bias supply

R1 Vx+Vf VS−Vx−Vf+2α Hall power-supply 10 VH+

R2 VO1 VO2 VO3 voltage output
O.L×VO1 circuit 11 VH−
VS/4 VCC1
R1 R2 R4 1.5×R5 R6

FG amplifier
Vx+α
Vx R3
24 FGOUT
R6
SBD (VS/2)+α

GND 13 +Vf
Vx+Vf

23 22
1 1 FGIN+ FGIN−
VO1= 14 VS+( 4 VS-Vx)= 2 VS-Vx VO3= 1 1
2 VS+α−(Vx+Vf)+ 2 VS+α=VS−Vx−Vf+2α
R3
O.L=
R3+R4

No.5792-4/7
 LB1991V
Pin Function
Pin No. Pin name Pin function Equivalent circuit
1 VCC1 Supply voltage for all circuits other than the IC internal
output block and the amplitude control block.
2 VCC2 Supply voltage for the IC internal output control block and
the amplitude control block.
3 VS Motor drive power supply. The voltage applied to this pin 2 VCC2
must not exceed VCC2. 10kΩ
3 VS
1/2×VS
5 UOUT U phase output.
5kΩ
1/4×VS Each
7 VOUT V phase output. 5
OUT
(7,9)
5kΩ
9 WOUT W phase output.
6 RF
(These outputs include built-in spark killer diodes.)
(8)
6,8 RF Ground for the output power transistors.

10 VH+ Hall element bias voltage supply.

1 VCC1
A voltage that is typically 0.95V is generated between the
VH+ and VH− pins (When IH is 5mA).

About 11 VH−
0.9V
11 VH−
10
20kΩ
About VH+

20kΩ
1.9V

13 GND Ground for circuits other than the output transistor.

The RF pin potential is the lowest output transistor potential.
14 FRC Forward/reverse selection. Applications can select motor
VCC1 VCC1
forward or reverse direction rotation using this pin. (This pin
has hysteresis characteristics.)

FRC STBY
50kΩ 100kΩ
15 STBY Selects the bias supply for all circuits other than the FG 14 15
comparators.
100kΩ

100kΩ
The bias supply is cut when this pin is set to the low level.

16 UIN1 U phase Hall element input.

17 UIN2 The logic high level is the state where the IN+ voltage is 1 VCC1
greater than the IN− voltage. 0.3V

18 VIN1 V phase Hall element input.

19 VIN2 The logic high level is the state where the IN+ voltage is 4kΩ 4kΩ
200Ω
(18,20)
Each
greater than the IN− voltage. VCC1 16 input of 1
1.2V typ
20 WIN1 W phase Hall element input. Each
17
200Ω

400Ω 400Ω input of 2

200Ω
21 WIN2 The logic high level is the state where the IN+ voltage is
(19,21)
greater than the IN− voltage.
ANGLE 17
12 ANGLE Hall input/output gain control. The gain is controlled by the
resistor connected between this pin and ground.
22 FGIN+ FG comparator non-inverting inputs.
VCC1
There is no internally applied bias.
1
15kΩ

20kΩ

23 FGIN− FG comparator inverting inputs.

There is no internally applied bias. FGIN− FGIN+ FGOUTN
200Ω 200Ω
23 22 24

24 FGOUT FG comparator outputs.

50kΩ

There is an internal 20kΩ resistor load.

No.5792-5/7
 LB1991V
Overlap Generation and Calculation Method

VS VS
Upper side
residual voltage VXH
VS−VXH Upper side clamp potential
VS−VXH
Vα
VS
O.L × ( 2 −VXH)
Absolute voltage VS
Electrical A B −
angle 2 VXH
180°

Calculated center point

VN

C D

Vβ
Lower side clamp
VXL potential VXL
Lower side
residual voltage VXL
0 Time

Overlap Generation
Since the voltage generated in the amplitude control block is, taking the center point as the reference, 2 × <overlap> ×
(1/2 VS − VX) on one side, the intersection point of the waveform will be <overlap> × (1/2 VS − VX) from the center
point.
To clamp that waveform at (1/2 VS − VX) referenced to the center point the overlap must be:
A/B × 100 = <overlap> × 100 (%).

Overlap Calculation
• Upper side overlap
(VS − VXH − VXL) (VS − VXH + VXL)
Calculated center point: VN = 2 + VXL = 2
Since A = Vα − VN, B = VS − VXH − VN, the upper side overlap will be:
A Vα − ((VS − VXH + VXL)/2)
<overlap> = B = ×100
VS − VXH − ((VS − VXH + VXL)/2)
Which can be calculated as:
2Vα − (VS − VXH) − VXL
= ×100(%)
(VS − VXH) − VXL
• Lower side overlap
Since C = VN − Vβ, and D = VN − VXL, the lower side overlap will be:
C ((VS − VXH + VXL)/2) − Vβ
<overlap> = D = ×100
((VS − VXH + VXL)/2) − VXL
Which can be calculated as:
(VS − VXH) + VXL − 2Vβ
= ×100(%)
(VS − VXH) − VXL

No.5792-6/7
 LB1991V
Test Circuit
±15V
1kΩ
1µF

100kΩ
2 2 2 VIN
3 1 3 1 3 1
2 2 VH2 f=1kHz
2 1 LA6358
3 1 3 3 1 VH1 −50dBm
SV
SQ SO SM VH3
2
A SR SP SN SL
1kΩ
Im6 SK
SW 1 0.1µF

100kΩ 2 A
A SJ
Im5
Im7 VSTBY
1kΩ 1 A
100kΩ Im4
VFRC
SU 1 2
1 ST Vm4 V
3 2 1 3 2 SS

1
LB1991V
IOUT3 VFG1 VFG2 2
5mA

SA
Vm3
A V 20kΩ
Im1 S1
VCC1 SB 1
SH IOUT2
3V A 2 1
Im2
VCC2 SC 2
4mA
4.75V A
Im3
VS
1.5V SD 39Ω × 3 The following hold
unless otherwise specified:
VCC1=3V
VCC2=4.75V
Vm1 V
1 2 3 1 2 3 VS =1.5V

VH1=1.4V
SE SF
SG VH2=4.75V
IOUT1 Vm5
100mA
V VH3=1.5V
200mA VFRC=3V
500mA V VSTBY=3V
800mA Vm2 VFG1=VFG2=1.5V

Switch status:
0 : CLOSED
X : OPEN

SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.

This catalog provides information as of January, 2009. Specifications and information herein are subject
to change without notice.

PS No.5792-7/7