Altium

Unified Electronic Product Development
Altium Designer Schematic Capture and PCB Editing training

Environment and Editor Basics
Training Module
1
Software, documentation and related materials:

Copyright © 2006 Altium Limited.
All rights reserved. You are permitted to print this document provided that (1) the use of such is
for personal use only and will not be copied or posted on any network computer or broadcast in
any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole
or part, of this document by any means, mechanical or electronic, including translation into
another language, except for brief excerpts in published reviews, is prohibited without the express
written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited
by local statute. Violators may be subject to both criminal and civil penalties, including fines
and/or imprisonment.
Altium, Altium Designer, Board Insight, CAMtastic, CircuitStudio, Design Explorer, DXP,
LiveDesign, NanoBoard, NanoTalk, Nexar, nVisage, P-CAD, Protel, SimCode, Situs, TASKING,
and Topological Autorouting and their respective logos are trademarks or registered trademarks
of Altium Limited or its subsidiaries.
Microsoft, Microsoft Windows and Microsoft Access are registered trademarks of Microsoft
Corporation. OrCAD, OrCAD Capture, OrCAD Layout and SPECCTRA are registered trademarks
of Cadence Design Systems Inc. AutoCAD is a registered trademark of AutoDesk Inc. HP-GL is a
registered trademark of Hewlett Packard Corporation. PostScript is a registered trademark of
Adobe Systems, Inc. All other registered or unregistered trademarks referenced herein are the
property of their respective owners and no trademark rights to the same are claimed.
Environment and Editor Basics Training Module ii

Environment and Editor Basics Training Module
1. Introduction to Altium Designer .............................................................................. 1-1
1.1 DXP – the Altium Designer Integration Platform ............................................ 1-1
1.2 The Altium Designer Project...........................................................................1-1
1.3 Exercise — Opening an existing Project........................................................ 1-2
2. The Altium Designer environment........................................................................... 1-3
2.1 Editor View ..................................................................................................... 1-4
2.2 Exercises — Navigating around the Altium Designer .................................... 1-5
3. Document Editor overview....................................................................................... 1-6
3.1 Working in a document editor ........................................................................ 1-6
4. Working with projects and documents................................................................. 1-10
4.1 Creating a new project ................................................................................. 1-10
4.2 Adding a new document to the project......................................................... 1-11
4.3 Renaming documents .................................................................................. 1-11
4.4 Adding an existing document to a project .................................................... 1-11
4.5 Moving or copying a document between projects ........................................ 1-11
4.6 Removing a document from the project ....................................................... 1-11
4.7 Working with old Protel designs ................................................................... 1-11
4.8 File management with the Storage Manager ............................................... 1-12
4.9 Including other files in the Altium Designer project ...................................... 1-13
4.10 Libraries........................................................................................................ 1-13
4.11 Exercise – Working with projects and documents ....................................... 1-13
5. DXP System menu .................................................................................................. 1-14
5.1 System Info .................................................................................................. 1-14
5.2 Customize .................................................................................................... 1-15
5.3 Preferences .................................................................................................. 1-15
5.4 Run Process ................................................................................................. 1-16
5.5 Licensing ...................................................................................................... 1-16
5.6 Run Script and Run Script Debugger........................................................... 1-16
5.7 Exercise – Configuring Altium Designer System Preferences ..................... 1-16
6. Customizing toolbars, menus & shortcut keys................................................... 1-17
6.1 Customizing resources.................................................................................1-17
6.2 Behind the scenes - processes and parameters.......................................... 1-18
6.3 Exercises — Customizing resources ........................................................... 1-19
6.4 Creating a new menu, toolbar or shortcut key menu ................................... 1-21
7. Schematic Editor basics......................................................................................... 1-22
7.1 View Commands .......................................................................................... 1-23
7.2 Location Markers.......................................................................................... 1-24
7.3 Selection....................................................................................................... 1-24
7.4 Other mouse actions .................................................................................... 1-26
7.5 Multiple objects at the same location ........................................................... 1-26
7.6 Exercises – Schematic Editor basics ........................................................... 1-26
8. Schematic graphical objects.................................................................................. 1-28
8.1 General......................................................................................................... 1-28
8.2 Drawing schematic graphical objects........................................................... 1-28
8.3 Smart Paste.................................................................................................. 1-32
Environment and Editor Basics Training Module iii

8.4 Modifying Polylines....................................................................................... 1-34
8.5 Font Management ........................................................................................ 1-35
8.6 Exercise – Schematic graphical objects....................................................... 1-35
9. Schematic electrical objects .................................................................................. 1-36
9.1 General......................................................................................................... 1-36
9.2 Summary of Electrical Objects ..................................................................... 1-36
9.3 Exercise – Schematic electrical objects ....................................................... 1-42
10. PCB Editor Basics................................................................................................... 1-43
10.1 PCB Editor User Interface ............................................................................ 1-43
10.2 View Commands .......................................................................................... 1-44
10.3 Selection....................................................................................................... 1-45
10.4 Other mouse operations............................................................................... 1-47
10.5 Multiple objects at the same location ........................................................... 1-47
10.6 Jump menu................................................................................................... 1-48
10.7 Exercise — PCB basics ............................................................................... 1-48
11. PCB design objects ................................................................................................ 1-50
11.1 General......................................................................................................... 1-50
11.2 Tracks........................................................................................................... 1-51
11.3 Lines ............................................................................................................. 1-52
11.4 Pads ............................................................................................................. 1-53
11.5 Vias............................................................................................................... 1-54
11.6 Strings .......................................................................................................... 1-55
11.7 Fills ............................................................................................................... 1-56
11.8 Copper Region ............................................................................................. 1-56
11.9 Arcs .............................................................................................................. 1-57
11.10 Dimensions and coordinates ........................................................................ 1-57
11.11 Keepout objects............................................................................................ 1-58
11.12 Paste commands.......................................................................................... 1-58
11.13 Exercise – PCB design objects .................................................................... 1-59
12. Project Navigation and Cross Probing ................................................................. 1-60
12.1 Compiling the PCB project ........................................................................... 1-60
12.2 Navigating .................................................................................................... 1-60
12.3 Cross probing from the schematic to the PCB ............................................. 1-61
12.4 Exercise — Navigation and Cross Probing .................................................. 1-62
13. The DXP Data Editing System................................................................................ 1-63
13.1 Finding and Selecting Objects ..................................................................... 1-64
13.2 Exercises – editing objects...........................................................................1-67
14. Text Editor................................................................................................................ 1-68
14.1 Searching for text ......................................................................................... 1-68
14.2 Text bookmarks............................................................................................ 1-68
14.3 Syntax highlighting ....................................................................................... 1-69
15. Using the Help system............................................................................................ 1-70
15.1 Dynamic On-line Help ..................................................................................1-70
15.2 Searching the Documentation Library.......................................................... 1-71
15.3 Using F1 ....................................................................................................... 1-71
15.4 What's This Help .......................................................................................... 1-71
16. Using the Altium website ....................................................................................... 1-72
16.1 Knowledge Base .......................................................................................... 1-72
Environment and Editor Basics Training Module iv

1. Introduction to Altium Designer
Underlying the Altium Designer environment is a software integration platform that brings
together all the tools necessary to create a complete environment for electronic product
development, in a single application.
Altium Designer includes tools for all design tasks: from schematic and HDL design capture,
circuit simulation, signal integrity analysis, PCB design, and FPGA-based embedded system
design and development. In addition, the Altium Designer environment can be customized to
meet a wide variety of user requirements.
1.1 DXP – the Altium Designer Integration Platform

When you select Programs » Altium » Altium Designer 6 from the Windows Start menu to run
Altium Designer, you are actually launching DXP.EXE. The DXP platform underlies Altium
Designer, supporting each of the editors that you use to create your design.
The application interface is automatically configured to suit the document you are working on.
For example, if you open a schematic sheet, appropriate toolbars, menus and shortcut keys are
activated. This feature means that you can switch from routing a PCB, to producing a Bill of
Materials report, to running a transient circuit analysis, and so on – and the correct menus,
toolbars and shortcuts will be readily available.
Also, all toolbars, menus and shortcut keys can also be configured to suit how you like to
configure your design environment.
Figure 1. Altium Designer’s software integration architecture
1.2 The Altium Designer Project

• The basis of every electronic product design is the project.
• The project links the elements of your design together, including the source schematics, the
netlist, and any libraries or models you want to keep in the project.
• The project also stores the project-level options, such as the error checking settings, the
multi-sheet connectivity mode, and the multi-channel annotation scheme.
• There are six project types – PCB projects, FPGA projects, Core Projects, Embedded
Projects, Script Projects and Library Packages (the source for an integrated library).
• Altium Designer allows you to access all documents related to a project via the Projects
panel.
• Related projects can also be linked under a common Workspace, giving easy access to all
files related to a particular product your company is developing.
• When you add documents to a project, such as a schematic sheet, a link to each document
is entered into the project file. The documents can be stored anywhere on your network; they
do not need to be in the same folder as the project file.
Environment and Editor Basics Training Module 1-1

1.3 Exercise — Opening an existing Project
1. Select the File » Open Project menu to display the Choose Project to Open dialog.
2. Navigate to the project folder, 4 Port Serial Interface, located in the \Altium
Designer 6\Examples\Reference Designs directory. Locate 4 Port Serial
Interface.PRJPCB (the project file) and double-click on it to open it.
The design will now be listed in the navigation tree of the Projects panel.
Figure 2. The open project is displayed in the Projects panel.
3. Click on the – signs to contract the folders.

4. Click on + (plus) signs to expand folders.
5. Right-click on the project name (4 Port Serial Interface.PrjPcb) to display the context
sensitive Projects menu.

2. The Altium Designer environment
The Altium Designer environment consists of two main elements:
• The main document editing area of Altium Designer, shown on the right side in Figure 3.
• The Workspace Panels. There are a number of panels in Altium Designer, the default is that
some are docked on the left side of the application, some are available in pop-out mode on
the right side, some are floating, and others are hidden.
When you open Altium Designer, the most common initial tasks are displayed for easy selection
in a special view, called the Home Page.
DXP System Menu View Navigation

Use this menu to set Document bar Workspace panels
Click on the arrows
up system preferences A tab appears for to go back and forth More pop out panels
and customize the each open document. between views. are displayed by
environment. All other clicking on these tabs.
menus and toolbars These panels can also
automatically change be moved, docked or
to suit the document clipped.
being edited.
Workspace panels
These include Files
and Projects panels. Home Page Design View
These panels can be Common tasks are listed
moved, docked or to get started quickly.
clipped by clicking on
the panel title and
dragging it to a new
location.
Click on the tab at the
bottom of the panel to
display its contents. Panel Control
Editor specific and
shared panels can be
displayed using these
Panel buttons.
Figure 3. Altium Designer with the DXP Home Page displayed.
Note: To move an individual panel, click and hold on the panel name. To move a set of panels,
click and hold on the panel caption bar away from the panel name. To prevent panels stacking
together, hold the CTRL key. To change a docked panel to pop-out mode click the small pin
icon at the top of the panel, to change it back to docked click the pin icon again.

2.1 Editor View
Each different document kind is edited in an appropriate Document Editor, for example the PCB
Editor for a PCB document, Schematic Editor for a schematic document, or VHDL Editor for a
VHDL document. Figure 4 shows a schematic open for editing in the Schematic Editor.
Figure 4. A schematic open for editing in the Schematic Editor View.
2.1.1 Document Tabs in the Documents Bar

Documents that are open are allocated a tab at the top of the application. Click on the relevant
tab to display that document and make it the active document for editing.
Figure 5. Tabs showing various documents open, note how the PCB tab is highlighted, indicating that it is
the document currently being edited.
Right-click menu in the Documents Bar

1. Right-click on any document tab in the Documents bar.
2. Select Tile All from the floating menu that appears. All the opened documents are tiled in
multiple screen regions.
Note: The number of opened documents determines the number of regions.
3. Right-click on a document tab.
4. Select Close from the menu.
5. Position the cursor at the point where two regions of a split screen meet and a double-
headed arrow will display. Click and drag to resize.

6. Right-click on any one of the tabs in the tiled display and choose Merge All. Notice that you
have converted a split screen back to a single view.
Note: Altium Designer supports multiple monitors. If you PC has multiple monitors you can
use the Open in New Window command when you right-click on a document, this will
cause it to open in a separate Altium Designer application frame, which you can then move
onto your second monitor.
2.2 Exercises — Navigating around the Altium Designer
2.2.1 Using the Projects panel

1. Open 4 Port Serial Interface.PRJPCB, located in the \Altium Designer
6\Examples\Reference Designs\4 Port Serial Interface folder.
2. Expand and then contract the contents of the navigation tree.
3. Double-click on a document in the Projects panel to open it.
4. Double-click on a few more documents in the Projects panel to open them.
2.2.2 Design Window navigation

1. Right-click on one of the document tabs in the Documents bar and select Tile All.
2. Left-click and drag on any document tab, moving it and dropping it next to another document
tab.
3. Right-click on one of the tabs in the multiple screens and select Merge All.
4. Close each of the open documents.
Note: The behavior of the tabs in the Documents bar is controlled by options in System –
View page of the Preferences dialog.

3. Document Editor overview
To display a document in its editor, double-click on a document icon in the Projects panel. The
document will be opened in the appropriate editor, e.g. Schematic Editor, PCB Editor or the
Library Editors.
When you create a new document in a design you are required to select a document type, e.g.
Schematic or PCB. The document type you select determines which editor is assigned to the
document.
3.1 Working in a document editor

The sections below describe various elements in the user interface of the Altium Designer
document editors.
Menus
Schematic Editor
displaying the active
schematic document.
The Projects panel

shows all open projects,
and all documents in Context-sensitive
each project. right-click pop-up
Icons to the right of each menu
document indicate if that
document is open, The Selection Memory button saves
hidden and/or modified. selections.
The Mask Level button allows you to
change the level of dimming of
unmasked objects. Click Clear to
clear the current mask.
The Highlight button allows you to
click to highlight nets, press Space or
Shift Space to change the behavior.
Workspace panels The Clear button will clear any filter
Click on these buttons that has been applied to the
to display the various document.
Status bar workspace panels.
Figure 6. Schematic Editor workspace
3.1.1 Menus
• Altium Designer menus are similar to standard Windows menus.
• Standard operations, e.g. opening, saving, cut, paste, etc. are consistent across editors.
• Right-click on an empty space on the menu bar or a toolbar caption to open the
Customization Editor and customize any of the resources for that editor.

3.1.2 Shortcut keys and pop-up menus
• Menu commands can also be accessed using shortcut keys. The underlined letter indicates
the shortcut key for a menu command, e.g. press F for the File menu.
• Special shortcut keys give direct access to both menus and sub-menus in the graphical
editors, e.g. pressing F in the Schematic Editor will pop up the File menu and pressing S will
pop up the Select sub-menu.
3.1.3 Toolbars
• Toolbars can be fixed to any side of the workspace or they can be floated.
• Click and drag to move a toolbar. The cursor must be within the toolbar but not actually on a
button.
• Toolbars can be reshaped, hold the cursor over the edge of the toolbar and when the
resizing cursor appears click and hold to reshape.
• New toolbars can be created and existing toolbars edited.
• Multiple toolbars can be active, right-click on a toolbar to pop up the toolbar display control
menu.
3.1.4 System and Editor Panels

• Altium Designer uses two types of panels – system-type panels, such as the Files,
Messages or Projects panels that are always available, and editor panels, such as the PCB,
schematic library or PCB library panels that are only available when a document of that type
is active.
• Panels can float, or be docked, on any edge of the Altium Designer workspace. Docked
panels can be pinned open, or set to unpinned, where they pop out when their name button
is clicked.
• Panels can be clipped together in a set by dragging and dropping one on another, and then
dragged around as a set by clicking and dragging on the area of panel title bar that contains
no text or icons.
• A panel can be unclipped from a set by clicking and dragging on the panel name.
• Panels can be prevented from docking on particular edges. Right-click on a panel title bar to
configure this.
• The hide and display speed of unpinned panels is configured in the View tab of the
Preferences dialog (DXP » System Preferences).
3.1.5 Status Bar

• The Status Bar is used to display information to the user.
• The Status Bar consists of three display fields divided by separators and a set of panel
display buttons. These three display fields are:
- Cursor position
- Prompt
- Options.
• The fields can be re-sized by clicking and dragging on the separators.
• The Status Bar is turned on and off using the menu command View » Status Bar.
• The panel display buttons can be added/removed from the Status bar. Right-click on the
Status Bar to display the control menu.

3.1.6 Command Status Bar
• The Command Status Bar displays the name and action of the command currently being
executed.
• When turned on, the Command Status Bar is located below the Status Bar.
• The Status Bar is toggled on and off using the menu command View » Command Status.
• Most users choose to turn off the Command Status Bar.
3.1.7 Tool Tips

• Tool Tips provide a brief description of how to use a particular function.
• Position the cursor over a toolbar button and leave it stationary for about a second and the
Tool Tip will appear.
3.1.8 Right mouse click context sensitive pop-up menus

• Altium Designer makes extensive use of context sensitive right mouse menus, including in
panels and dialogs.
• Right-click anywhere in the environment to pop up a context sensitive menu of commands at
the current cursor position. Supported right-click locations include:
- in a document editor, on an object
- in a document editor, in free space
- in the different sections of a panel
- on the Status bar
- on a toolbar or menu bar
- in dialogs, especially those with a grid of information.
Figure 7. A context sensitive right mouse menu

3.1.9 Dialogs
• Dialogs are used to set the parameters for various commands and objects.
• To move from one field to another in a dialog, press the tab key or use the mouse. SHIFT+TAB
takes you in the reverse direction.
• Most fields will have an underlined character associated with them that can be pressed (in
combination with the ALT key) as an alternative to a mouse click.
• When a field is highlighted, typing can overwrite it.
3.1.10 Undo/Redo
• Most commands can be undone or then redone using the Undo and Redo toolbar
buttons. The number of schematic editor and PCB editor undos is set in the Preferences
dialog (DXP » Preferences).
• The shortcut keys for Undo are CTRL+Z or ALT+BACKSPACE, and CTRL+Y or
CTRL+BACKSPACE for Redo.

4. Working with projects and documents
A project is a set of documents that together define all aspects of your design: including
schematic sheets, PCB documents, database link definition files, output job definition
documents, netlists, and so on. Each project results in a single implementation, for example a
PCB project results in one PCB design, and a library package project results in a single
integrated library.
Each document in the project is stored as a separate file on the hard drive. The project file itself
is also an ASCII document, which includes links to the documents in the project, as well as
storing project-level settings.
4.1 Creating a new project

To create a new PCB project:
1. From the Main Menu, select File » New » PCB Project.
Figure 8. The new project is displayed in the Projects panel
2. Select Save As from the File menu to name and save the project document.
3. The new project is ready to add new or existing documents to.
Environment and Editor Basics Training Module 1 - 10

4.2 Adding a new document to the project
To create a new document:
1. Right-click on the Project name in the Projects
panel, and from the Add New to Project sub-
menu, select the document kind, for example,
Schematic.
2. Right-click on the new schematic document in
the Projects panel and select Save As to name
and save the schematic.
4.3 Renaming documents

Figure 9. New schematic added to the project
To rename a document:
1. Right-click on the document in the Project panel, and choose Save As from the menu.
2. Note that a new document is created when you do this. The original file will remain on the
hard disk, but will no longer be linked to the project.
4.4 Adding an existing document to a project

To add an existing document to a project:
1. Right-click on the Project name in the Projects panel.
2. Select Add Existing to Project in the menu to display the Choose Document to Add to
Project dialog.
3. Navigate to locate required file and select it.
4. Click on Open to add it. The document is added into the currently active project. Note that
when you add a document to a project a link is added in the project file to that document.
The document can be located anywhere on the hard disk (or network).
The document icon graphic indicates which Editor will be used to edit the document, e.g. a PCB
document will have a PCB icon, indicating that it will be opened by the PCB Editor.
Note: You can add a document to a project using click and drag First, drag the document from
the Windows File Explorer into the Altium Designer Projects panel and then when it appears as
a Free Document, click and drag it into the project.
4.5 Moving or copying a document between projects

1. Since documents are only linked into the project, you can easily move a document from one
project to another simply by clicking and dragging it.
2. To copy a document to another project, hold the CTRL key as you click and drag.
4.6 Removing a document from the project

To remove a document from a project, right-click on the document icon in the Project panel and
select Remove from Project.
Note: The document is not deleted from the hard disk, but it is no longer linked into the project.
4.7 Working with old Protel designs

Schematic and PCB documents from all earlier versions of Protel can be opened directly in
Altium Designer. Protel 99 SE design databases can also be opened, the Import Wizard is used
to do this (File » Import Wizard).

The Wizard will guide you through the process of extracting all files from the design database
and build Altium Designer projects based on settings you define. The wizard extracts all files
from the design database, regardless of how you configure the mapping of individual 99SE files
into Altium Designer projects.
The created Altium Designer project files and the project group file are not saved automatically.
You will be prompted to save when you close them.
4.8 File management with the Storage Manager

The Storage Manager is a system panel that allows you to perform a variety of file management
tasks. When you open the Storage Manager (View » Workspace Panels » System » Storage
Manager) it presents a folder/file view of the active project’s documents.
The Storage Manager can be used for:
• General everyday file management functions, such as renaming and deleting, for files in the
project or within the active project’s folder structure.
• Management of Altium Designer backups, using the Local History feature.
• As a Subversion compliant interface for your Altium Designer projects.
• As a CVS compliant (Concurrent Versions System) interface for your Altium Designer
projects.
Note: right-click in
• As an SCC (Source Code Control) compliant version control the different regions
interface for your Altium Designer projects. of the panel for
• Performing a physical and electrical comparison of any 2 versions options.
in the Local History, or the CVS Revision list.
The Folders view on the left gives access to documents stored in the project folder hierarchy.
Next to this the File list shows all documents in the selected folder. A number of highlighting
modes are used to indicate the state of each document, press F1 when the cursor is over the
panel for information on highlighting.
Figure 10. Use the Storage Manager to manage project files on the hard disk, and to interface to your
Version control system.
Note: Press F1 over the panel for access to detailed help.

4.9 Including other files in the Altium Designer project
• You can include any file in your Altium Designer project, as long as the Microsoft Windows
operating system is aware of the file’s associated editor.
• Add it to the project as described in section 4.4 (you will need to change the file filter to see
non-Altium file types). The file will appear in the Project structure in the Projects panel,
under a folder icon titled Documentation.
4.10 Libraries
• Libraries can exist as individual documents, for example, schematic libraries containing
schematic symbols, PCB libraries containing PCB footprint models, discrete SPICE models
(MDL and CKT), and so on.
• Altium Designer also supports the creation of integrated libraries. An integrated library is the
compiled output from a library package. It includes all the schematic libraries in the original
library package, plus any referenced models, including footprint, simulation and signal
integrity models.
• Most of the supplied libraries are provided as integrated libraries and are stored within the
\Program Files\Altium Designer 6\Library folder. Integrated libraries can be
converted back to their constituent libraries; simply open them in Altium Designer to do this.
PCB libraries are also provided in the \Program Files\Altium Designer 6
\Library\Pcb folder.
• The Schematic Library Editor and PCB Library Editor are covered during the Schematic
Capture and PCB Design training sessions. The basics of creating an integrated library are
also covered.
Note: You can use Protel 99 SE libraries directly in Altium Designer. Add them to the
Libraries panel to use them without converting them to the Altium Designer format. Note
that you will not get all the benefits of the enhanced parameter and model support.
4.11 Exercise – Working with projects and documents

This exercise looks at creating a new project and adding documents to it.
1. Create a new PCB project in the \Altium Designer
6\Examples\Training\Temperature Sensor folder and name it Temperature
Sensor.PrjPCB. We will use this project later during the Schematic Capture training
session.
2. Add the following two schematic documents to the project from the \Altium Designer
6\Examples\Training\Temperature Sensor folder: LCD.SchDoc and
Power.SchDoc.
3. Save and close the new project Temperature Sensor.PrjPCB.
4. Check that the documents exist on the hard drive using the Windows Explorer.

5. DXP System menu
The DXP system menu provides commands for configuring the Altium Designer (DXP)
environment. You can access these commands by clicking on the DXP icon located on the left-
hand side of the Main menu. The DXP menu is always accessible in Altium Designer, regardless
of which editor is currently in use.
Figure 11. Configure the environment via the DXP menu
The following sections describe the entries in the DXP system menu.
5.1 System Info

This menu item is provided to access information about servers. Installation and removal of
servers is not carried out in this dialog, all servers found in the \Program Files\Altium
Designer 6\System folder are automatically installed in the DXP environment.
Right-click on a server to examine its properties.
Figure 12. EDA Servers dialog

5.2 Customize
The menu enables the management of resources associated with the current editor. For more on
this, refer to section 6. Customizing toolbars, menus
& shortcut keys.
5.3 Preferences
Various global system preferences can be set for the DXP environment, including file backup
and auto-save options, the system font used, the display of the Projects panel, environment view
preferences including the popup and hide delay for panels, and enabling the version control
interface. You can also access the environment preferences for each of the editors available in
Altium Designer, such as the schematic and PCB editors.
To set Altium Designer environment preferences, select Preferences from the DXP menu. This
will open the Preferences dialog shown in Figure 13.
Figure 13. Preferences dialog, used to configure Altium Designer and all editor preferences.
5.3.1 Autosave and manual save backup options

Altium Designer supports two automatic file backup modes:
1. Backup-on-save – keep a backup whenever a user-initiated save action is performed (on by
default). These files are saved in a History folder. The default is to create the History Folder
below the active project folder, to configure an alternative central folder open the Local
History page of the Version Control section of the Preferences dialog. History files are
listed in the History section of the Storage Manager panel.
2. Timed backup – automatically save a copy of all open documents at a fixed time interval (off
by default). Autosave settings, such as number of files and frequency of saves are
configured in the Backup page of the DXP System section of the Preferences dialog.
Both backup modes support multiple copies, using the naming convention of:
OriginalFileName.~(number of save).DocExtension.Zip

Backup files are automatically compressed to reduce file size.
5.4 Run Process

Selecting the Run Process command from the DXP System menu displays the Run Process
dialog, which allows you to run any process in the DXP environment. Processes are described
later in section 6.
5.5 Licensing
Selecting the Licensing command from the DXP System menu displays the Licensing View,
where you can select and configure the licensing type – Standalone or Network Client.
5.6 Run Script and Run Script Debugger

The Altium Designer includes a powerful scripting system, supporting the built-in DelphiScript
language, as well as popular Windows scripting languages, including VisualBasic Script and
JavaScript.
The built-in scripting language, DelphiScript, is a Pascal-like language. There is also a complete
Form design interface, allowing dialogs to be quickly created.
Selecting the Run Script menu entry will pop up the Select Item to Run dialog, click on the script
name to execute that script on the current document.
Selecting the Run Script Debugger menu entry will open the Script Debugger, where you can
set break points, single step through the script, and so on.
There is more information on scripting in the Scripting section of the Documentation Library,
browse to it in the Configuring the System folder in the lower section of the Knowledge Center
panel.
5.7 Exercise – Configuring Altium Designer System Preferences

1. Open the DXP Preferences dialog and click on different nodes in the tree on the left of the
dialog to get an idea of what options can be set – the options for the schematic and PCB
editors will be covered later in the course.
2. In the View page of the Preferences dialog disable the Use animation option, and reduce
the Hide delay option.
3. Close the Preferences dialog.
4. Hover the cursor over the Libraries tab on the right-hand side of the workspace to see how
the popup of the panel is affected and then move the cursor away from the Libraries panel
to check the hide delays.

6. Customizing toolbars, menus
& shortcut keys
All methods of command selection can be customized, including menus, toolbars and shortcut
key menus. These are often referred to as resources in Altium Designer.
6.1 Customizing resources

• Resources are customized via the DXP System menu, or by right-clicking on a menu or
toolbar and selecting Customize.
• Figure 14 shows the Customizing Schematic Editor dialog. When you select Customize with
a schematic as the active document, this dialog opens ready to customize the resources for
that editor. Customization options include adding, deleting or re-ordering menu entries and
toolbar buttons, and adding new shortcut key definitions.
Figure 14. Toolbar Properties dialog
6.1.1 Adding a command to a menu and toolbar

• The Commands tab of the Customizing dialog gives access to all the commands available
to this editor.
• There are essentially two ways of accessing a command:
- selecting Default Bars, then using the tree-like structure on the right, or
- choosing a flat list of commands, either All commands in one list, or clicking on a menu
name on the left to access a command in that menu.

• When the required command has been located, click and drag it to the required toolbar or
menu, then release in the required location.
• When the Customizing dialog is open, menu entries and toolbar buttons can be:
- moved, by clicking and dragging
- copied, by holding Ctrl while you click and drag
- edited, by double-clicking.
• When the Customizing dialog is open, separators can be:
- added to a menu by clicking and dragging a menu entry down slightly from the previous
entry to add a separator in between
- removed by dragging the entry that follows the separator up and releasing on top of the
separator.
- Use the same techniques to add/remove a separator from a toolbar.
• When the Customizing dialog is not open, hold Ctrl as you click on a menu entry or toolbar
button to directly access the Edit Command dialog for that command.
6.1.2 Bars – the menu bar and toolbars

• Toolbars and the main menu are all classified as bars. Set any bar to be the main menu in
the Bars tab of the Customizing dialog.
• When you create a new toolbar in the Bars tab of the Customizing dialog, the blank bar
appears just to the right of the main menu bar.
• Alternate menu bars can be created and kept as a toolbar, then switched to be the menu bar
when required.
6.1.3 Shortcut keys

• Shortcuts are defined as part of the command. To examine all shortcuts, click on All in the
Customizing dialog, then click on the Shortcut heading in the Commands section of the
dialog on the right to sort by shortcut key.
• When the Customizing dialog is open, a Shortcut menu appears on the toolbar at the top of
the workspace.
• Only one set of shortcuts can be defined for each editor.
6.2 Behind the scenes - processes and parameters

• Underlying every command in the DXP environment is a process. Each DXP server presents
its functionality to the environment as a set of processes.
• Many processes support parameters, where each parameter is used to control the behavior
of the process.
• Commands, which are edited in the Customizing dialog, are pre-packed combinations of a
process + required parameters + menu caption + shortcut keys.
6.2.1 Using parameters

• Adding parameters can further customize the operation of any process.
• An example of the use of parameters is the Digital Objects tools, available on the Utilities
toolbar in the Schematic Editor (View » Toolbars » Utilities to control the display of the
toolbar).

Figure 15. Digital Objects tools, accessed on the Utilities bar
All the buttons on this toolbar use the process:

IntegratedLibrary:PlaceLibraryComponent
it is the parameters that specify which part is placed, e.g.
LibReference=SN74F08D | Library=Texas Instruments\TI Logic Gate
2.IntLib | Orientation=0
Note: Multiple parameters are separated by a pipe symbol (|).
6.3 Exercises — Customizing resources
6.3.1 Adding a command to a toolbar

In this exercise, we will add the Find » Text command to the Schematic Editor’s Main toolbar.
1. While in a Schematic document, right-click on the main menu (or a toolbar) and select
Customize from the floating menu that appears. The Customizing dialog will appear.
2. The Find Text command is already available in the menus, so rather than finding it in the
Customizing dialog, we will simply copy the command from a menu to the toolbar.
3. Click once on Edit menu, then click once on the Find Text command. It will be highlighted
with a black box.
4. Holding the CTRL key, click and hold on the Find Text command and drag it up to the main
toolbar, dropping it before the Cut button, as shown in Figure 16.
5. Close the Customizing dialog, then click the new button to confirm that it works, the Find
Text dialog should open.
Figure 16. Copying a command from a menu to a toolbar

6.3.2 Adding an item to the main menu or right–click menu
In this exercise, you will add the Deselect All command to the right-click menu of the Schematic
Editor. Menu items that appears in the Right Mouse Click menu, Options popup menu (press
the O shortcut key) or Filter popup menu (press the Y shortcut key) are listed under the Help »
Popups menu.
1. While in a Schematic document, right-click on the main menu (or a toolbar) and select
Customize from the floating menu that appears. The Customizing dialog will appear.
Figure 17. Customizing dialog with Right Mouse Click commands displayed
2. In the dialog, select DeSelect in the Categories list, then in the Commands list on the right
locate the All on Current Document command.
3. Click and hold on this command and drag it up to the Help menu. Once it opens, drag down
to Popups, then down to Right Mouse Click, then drop the command below the Clear
Filter menu entry.
4. Before closing the menu we will edit the caption that appears in the menu. To do this,
double-click on the new menu entry to open the Edit Command dialog.
5. In the Edit Command dialog, edit the caption to read De&Select All. Note the location of the
ampersand character (&). This defines the letter that will act as the accelerator key. The
letter S has been chosen because the letters D and A are already assigned in this menu. You
are free to reassign any of the accelerator keys that are used in the menu.
Note: Resource customizations are stored in the file DXP.RCS, which is located in the
C:\Documents and Settings\<your logon name>\Application
Data\AltiumDesigner6 folder.

6.4 Creating a new menu, toolbar or shortcut key menu
Creating a new menu bar or toolbar is similar to editing one. The procedure is outlined below.
Select the Customize command from the DXP System menu (to the left of the File menu). This
displays Customize Editor dialog shown in Figure 18.
Figure 18. Bars tab of the Customizing dialog
The Bars tab can be used to create a new toolbar, control the display of toolbars and select
which bar will be the menu bar. Only one menu can be active at any one time but any toolbar
can be selected to be the menu bar. To set a new bar to be the menu bar, change the Bar to
Use as Main Menu drop down.
6.4.1 Exercise — Creating a new toolbar

1. While the Schematic Editor is active, select the Customize command from the DXP menu to
display the Customizing dialog.
2. Click on the Toolbars tab and click New. A new toolbar will appear in the list. Click Rename
and rename it as My Toolbar, then enable the Is Active check box to display it.
3. Locate the new blank bar, if the menu and toolbars are in the default locations it will be to the
right of the Help menu, and drag it so it is floating in the workspace.
4. Finally, add some buttons to your new toolbar using the steps detailed in exercise 6.3.1
Adding a command to a toolbar.

7. Schematic Editor basics
The Schematic Editor opens when you open an existing schematic document or create a new
one. This editor makes use of all the workspace features in the Altium Designer environment.
This includes multiple toolbars, resource editing, right-click menu, shortcut keys and Tool Tips.
Figure 19. Schematic Editor workspace
In this section, we will explore the basics of working in the Schematic Editor.
• If not already open, open the following project: 4 Port Serial Interface.PrjPcb,
found in the \Altium Designer 6\Examples\Reference Designs\4 Port Serial
Interface folder (as shown above in Figure 19), and then open the schematic sheet, ISA
Bus and Address Decoding.SchDoc by double-clicking on the document name in the
Projects panel.

7.1 View Commands
The View commands can be accessed from the View menu and are listed below.
Command Toolbar Shortcut Key Description
Fit Document VD Display entire document
Fit All Objects VF Fits all objects in the current document window
Area VA Display a rectangular area of document by

selecting diagonal vertices of the rectangle
Around Point VP Display a rectangular area of document by
selecting the centre and one vertex of the
rectangle
Selected VE Fits all selected objects in the current
Objects document window
50% V5 Set display magnification to 50%
Zoom In VI Zoom In around current cursor position
Zoom Out VO Zoom Out around current cursor position
Pan VN Re-centre the screen around current cursor

position
Refresh VR Update (redraw) the screen display
Table 1. View command summary
While executing commands, auto panning becomes active (a crosshair is attached to the cursor)
by touching any edge of the Design Window. While auto panning, pressing the SHIFT key will
double the panning speed. Auto panning speed is controlled via the Auto Pan Options section of
the Graphical Editing tab within the Preferences dialog (Tools » Schematic Preferences).
Auto panning can also be turned off here.
The following shortcut keys provide a very useful alternative for manipulating the view of the
workspace. These shortcut keys can be used while executing commands.
Keystroke Function
END Redraws the view
PAGE DOWN Zoom out (holds the current cursor position)
PAGE UP Zoom in (holds the current cursor position)
CTRL+PAGE DOWN View Document
HOME View pan (pan to centre the current cursor position)
SPACEBAR Stops screen redraw
ARROW KEYS Moves the cursor by one snap grid point in direction of the arrow
SHIFT+ARROW KEY Moves the cursor by 10 snap grid points in the direction of the
arrow
Table 2. Shortcut keys for view manipulation

7.1.1 Using the mouse wheel to pan & zoom
The mouse wheel can also be used to pan and zoom when in a design document.
Panning
Roll the mouse wheel upwards to pan upwards, and downwards to pan downwards.
Press SHIFT and roll the mouse wheel downwards to pan to the right.
Press SHIFT and roll the mouse wheel upwards to pan to the left.
Zoom In
Press CTRL and roll the mouse wheel upwards to zoom in.
Zoom Out
Press CTRL and roll the mouse wheel downwards to zoom out.
7.1.2 Using the right mouse button to pan

Right-click, hold down the mouse button and move the cursor to pan in a design document. The
hand-shaped cursor indicates you are in panning mode. Release the right mouse button to stop
panning.
7.2 Location Markers

These allow you to store up to ten locations in your schematic document. You can then return to
these locations using the Jump command.
To set a location marker, select Edit » Jump » Set Location Marks (Ln or JKn) and select from
location marks 1 to 10. You then use the cursor to position the location mark. To return to that
location, select Edit » Jump » Location Marks n (JMn) and the display will be centered on that
location mark.
7.3 Selection
The Schematic Editor provides selection capabilities that are similar, although not identical, to
selection in other Windows applications.
Below are some key points about selection in the Schematic Editor:
• The main use of selection is to nominate objects for a clipboard operation, i.e. which objects
will be moved or copied to the clipboard when the Cut or Copy commands are invoked.
• Once objects are on the clipboard, they can then be pasted elsewhere onto the current
schematic or into another schematic, or to another Windows application which supports the
Windows clipboard.
• Selection is not cumulative. The selected object deselects when you click on another object.
• Hold the SHIFT key to select multiple objects.
• Press DELETE to delete all selected objects.
To select an object you can use:
Keystroke Function
Click and drag Select all objects enclosed by drag area
SHIFT+click on object Select an object (on a selected object, this will de-select it)
Edit » Select menu (S) Select Inside Area, Outside Area, All, Net or Connection
Select Inside Area button on the Main toolbar

Table 3. Select command summary

Selected objects can be:
Function Keystroke
Cut, copied, pasted or cleared Using the Edit menu commands
Moved Click-and-hold on any selected object
Moved or dragged Using the Edit » Move menu commands (M)
Aligned Using the Edit » Align menu commands (A)
Deleted Using DELETE
Table 4. Selected object command summary
Note: To de-select objects, use the Edit » DeSelect menu commands (X for popup menu)
or the DeSelect All button on the Main toolbar.
7.3.1 Selection hints

• Before starting a selection, it is a good idea to de-select all objects first.
• Only items that fall completely inside the selection area are selected.
• The selection color is set in the Graphical Editing tab of the Preferences dialog (Tools »
Schematic Preferences).
• The Move menu allows you to move selections:
- without maintaining connectivity (move)
- maintaining connectivity (drag).
• The S key pops up the Select menu.
• The X key pops up the Deselect menu.
7.3.2 Selection memory

Eight selection memories are available in the Schematic and PCB editors, which can be used to
store and recall the selection state of up to eight sets of objects on the schematic or PCB. Select
the objects you want to remember using any of the methods described above in Table 3 and
then store them for quick recall later.
The following selection memory options are
available:
• Store in memory (CTRL + number 1 to 8)
• Add to memory (SHIFT + number 1 to 8)
• Recall from memory (ALT + number 1 to 8)
• Recall and Add from memory (SHIFT + ALT
+ number 1 to 8)
• Apply memory as a workspace filter (SHIFT
+ CTRL + number 1 to 8).
You can also access the selection memories
using the Edit » Selection Memory sub-menu. Figure 20. Selection Memory control panel
Alternatively, use the Selection Memory control
panel that is opened by clicking the button next to the Mask Level button ( bottom right of
the workspace), or pressing CTRL+Q. Click on a STO button to store a selection or RCL to recall
a selection. The filtering options at the bottom of the control panel will determine how the
selection is displayed.

To prevent accidentally overwriting a selection memory, enable the Confirm Selection Memory
Clear option in the Graphical Editing page of the Schematic section of the Preferences dialog
(Tools » Schematic Preferences). Selection Memory locations can be locked from being
overwritten by checking the Lock checkbox associated with the selection memory.
7.4 Other mouse actions

The mouse operations listed below are universal throughout the Schematic Editor and should be
used in preference to menu commands:
Keystroke Function
Click-and-hold on object Move an object
CTRL+click on object Drag an object whilst maintaining connectivity. Press
the SPACEBAR to change mode.
Double-click on object Edit an object’s properties
Left-click ENTER
Right-click ESC
Table 5. General mouse shortcut summary
While an object is on the cursor, the following keystrokes can be used:

• SPACEBAR to rotate
• X key to flip around the vertical axis
• Y key to flip around the horizontal axis.
7.5 Multiple objects at the same location

When working in the Schematic Editor, the situation sometimes occurs where a click to perform
an operation is made where there are multiple objects. In this situation, the Schematic Editor
pops up a menu listing all the objects it has detected at the location of the click. You can then
select the object you wish to operate on from this menu.
Figure 21. Menu listing objects at mouse click point
7.6 Exercises – Schematic Editor basics

Zooming and panning
1. Open the schematic sheet, ISA Bus and Address Decoding.SchDoc, found in the
\Altium Designer 6\Examples\Reference Designs\4 Port Serial
Interface folder.

2. Experiment with each of the display commands listed in Table 1 using the View menu,
shortcut keys and the Main toolbar.
3. Use the mouse wheel to pan and zoom.
4. Select the menu command Place » Text String (PT) and experiment with the shortcut keys
listed in Table 2 in conjunction with the display commands you have just mastered. To exit
the command, press the ESC key or right-click.
5. Now try auto panning. Select the menu command Place » Text String again, then move the
cursor to an edge of the window. The display will start panning. Hold down the SHIFT key
while the display is panning. Note the crosshair cursor displaying while the Place » Text
String command is active.
Location markers
1. Set Location Mark 2 by selecting Edit » Jump » Set Location Marks » 2 (L2) and then click
in the schematic sheet to set the position for the location mark.
2. Zoom out to another part of the schematic.
3. Select Edit » Jump » Location Marks » 2 (JK2) and the screen will centre on Location
Mark 2.
Selection and mouse actions

1. Click on a component, e.g. P1. Observe the dashed box indicating it is the selected object.
2. Click on another component, e.g. a capacitor. It will now be the selected object.
3. Click somewhere on the sheet where there are no parts. Nothing will be selected now.
4. Click on the wire to select it. Notice the handles are now displayed.
5. With a wire selected, experiment with moving a vertex and moving a segment (a length of
line between two vertices). Add a vertex by clicking and holding on the wire where you want
the new vertex, pressing INSERT and then moving the new vertex to its new location. Delete
the new vertex by clicking on it and pressing DELETE.
6. Make sure all objects on the sheet are not selected using Edit » DeSelect » All (X, A) or
on the main toolbar.
7. Using the click and drag selection feature, select a section of the circuit. Using the Edit »
Copy menu command, copy the items to the clipboard.
8. Open a new sheet and paste the clipboard contents onto it. De-select the pasted objects.
9. Close the new sheet (no need to save it).
10. Try moving the selected objects on the original sheet using the Edit » Move menu
commands. Deselect all objects.
11. While holding the CTRL key, click on the component U10. You can now drag it around and
still maintain connectivity.
12. Click and hold on capacitor C12 and start to move it. While moving it press the ALT key,
noting how the movement is now constrained to the horizontal or vertical direction only. The
choice between constraining horizontal or vertical is defined by the proximity of the cursor to
the object – simply push the object in the desired direction to see the effect.
13. Double-click on one of the capacitors. The Component Properties dialog displays. You can
now edit any of the device’s properties.
14. Close the schematic without saving any changes.

8. Schematic graphical objects
8.1 General
• Use the Drawing Tools available on the Utilities toolbar to
place the graphical objects. Turn the Utilities toolbar on and
off by selecting View » Toolbars » Utilities.
• Drawing toolbar functions can also be accessed through
the Place » Drawing Tools menu, except for Paste Array
(Edit » Paste Array).
• When placing an item, press the tab key to edit its
properties. Double-click on a placed object to modify its properties.
• When an object is selected, its handles are displayed.
• While in a command, you can select another command, without quitting the first command,
provided you use a shortcut key. This powerful feature, called re-entrant editing, will
considerably enhance your productivity.
8.2 Drawing schematic graphical objects

For an example of each graphical object, open Graphical Objects.SchDoc found in the
Altium Designer 6\Examples\Training\Practice Documents folder.
Polyline Polygon Arc Bezier curve
Text frames are used

to create blocks of text
with multiple lines.
Here is a text string Text can be copied
into a text frame via
the Windows
And here is another clipboard.
Text String Text Frame Rectangle Rounded rectangle
Data7
Data6
Data5
Data4
Data3
Data2
Data1
Data0
Data0
Ellipse Pie Graphic Array
Figure 22. Schematic graphical objects
The placement of each of these objects is described in the following sections.

8.2.1 Lines
To draw a line:
1. Select the Place Line toolbar button or Place » Drawing Tools » Line.
2. Click once to start the line.
3. Click to place each vertex. The BACKSPACE key deletes the last vertex placed.
4. Right-click once to end the line.
5. Right-click again to end the command.
8.2.2 Polygons
To draw a polygon:
1. Select the Place Polygon toolbar button or Place » Drawing Tools » Polygon.
2. Click to place each vertex.
3. Right-click to end the polygon.
4. Right-click again to end the command.
5. Turn the Draw Solid option off in the Polygon dialog to draw a polygon that is not filled.
Note: The fill color and border color of polygons are independent.
8.2.3 Arcs
To place a circular arc:
1. Select the Place » Drawing Tools » Arc menu command.
2. Click to place the arc centre.
3. Click to determine the arc radius.
4. Click to place the start of the arc and click to place the end of the arc.
5. Right-click to end the command.
8.2.4 Elliptical arcs

To place an elliptical arc:
1. Select the Place Elliptical Arc toolbar button or Place » Drawing Tools » Elliptical
Arc.
2. Click to place the arc centre.
3. Click to determine the arc X-radius.
4. Click to determine the arc Y-radius.
5. Click to place the first end of the arc and click to place the second end of the arc.
8.2.5 Bezier curves

A Bezier curve is a curve of best fit between points defined by mouse clicks.
To draw a Bezier curve:
1. Select the Place Bezier Curve toolbar button or Place » Drawing Tools » Bezier.
2. Click once to place the first control point at the start of the curve.

3. Click to place the second control point.
4. Click to place the third and fourth control points.
5. Continue to click to place further control points.
7. To reshape the curve, click on one end of the curve and then move, add (INSERT key) or
delete new control points (handles).
8.2.6 Annotation (Text)

To place a line of text:
1. Select the Place Annotation toolbar button or Place » Annotation.

2. Press Tab to edit the contents and the font of the text. You can add special strings from the
Text drop-down list as well, such as the date and document information. This topic is
covered in more detail in the Schematic Capture training session.
3. Click to position the text.
Text strings can also be edited by selecting the string and clicking again to highlight the text.
8.2.7 Text frames

Text frames are used to place paragraphs of text on the sheet.
To place a text frame:
1. Select the Place Text Frame toolbar button or Place » Text Frame.
2. Press Tab to edit the contents and properties for the text frame and click OK.
3. Click to position the top left corner of the frame and then click to position the bottom right
corner of the frame.
4. Right-click to stop placing text frames.
The following keys apply when entering text into the frame:
Action Keystroke
Insert a tab CTRL+TAB
Cut SHIFT+DELETE or
CTRL+X
Copy CTRL+INS or CTRL+C
Paste SHIFT+INS or CTRL+V
Table 6. Text Frame action summary
The Cut, Copy and Paste commands apply to the Windows clipboard. The clipboard can also be
used to bring text in from other applications.
8.2.8 Rectangles
To place a rectangle:
1. Select the Place Rectangle toolbar button or Place » Drawing Tools » Rectangle.
2. Click to place top left corner.
3. Click to place bottom right corner.

8.2.9 Rounded rectangles

Rounded rectangles are rectangles with rounded corners. The radius of the arcs at the rectangle
corners is set in the X-Radius and Y-Radius fields in the Round Rectangle dialog.
To place a rounded rectangle:
1. Select the Place Rounded Rectangle toolbar button or Place » Drawing Tools »
Rounded Rectangle.
2. Press Tab to set the corner radii and click OK.
3. Click to place top left corner and click to place bottom right corner.
8.2.10 Ellipses
Use this command to draw circles as well. To place an ellipse:
1. Select the Place Ellipse toolbar button or Place » Drawing Tools » Ellipse.
2. Click to place the ellipse centre.
3. Click to determine the ellipse X-radius.
4. Click to determine the ellipse Y-radius.
8.2.11 Pie charts

To place a pie shape:
1. Select the Place Pie Chart toolbar button or Place » Drawing Tools » Pie Chart.
2. Click to place the pie centre.
3. Click to determine the pie radius.
4. Click to place the first edge of the pie and click to place the second edge.
8.2.12 Graphic images

Graphic images with the following formats can be added to your schematic:
• .bmp, .rle, .dib
• .jpg, .tif (uncompressed)
• .wmf, .pcx, .dcx, .tga.
The file containing the graphical image can be embedded into the sheet or linked. If the image
file is linked it must be transferred with the schematic file when moving the schematic from one
location to another.
To place a graphic image:
1. Select the Place Graphic Image toolbar button or Place » Drawing Tools » Graphic.
2. Click to place the top left corner of the image and click to place the bottom right corner of the
image.
3. Locate the file that contains the image and click OK.

4. To embed the image double click on it to open the Graphic dialog.
8.2.13 Paste Array

This command places all objects on the clipboard in an array defined in the Setup Paste Array
dialog. To place an array:
1. Select and copy the required items to the clipboard. When you choose Edit » Copy, the
cursor becomes a large crosshair. Click on the selected item to set the clipboard reference
point, i.e. the point where the object will be held for pasting. The selection of this reference
point will affect how the array is pasted.
2. While in the Schematic Library Select the Setup Array Placement toolbar button or
Edit » Paste Array. The Setup Paste Array dialog displays. The Primary Increment field
allows you to specify how text will increment when pasting and array of objects in a
schematic design, e.g. the designators of components or net labels. Incremental values may
be alphabetic or numeric, positive or negative. The Secondary Increment field is only used
when placing pins in the Schematic Library Editor since pins have two incremental properties
— designators (primary) and names (secondary). This would allow you, for example, to
place a series of pins with incrementing numbers and decrementing names.
While within the Schematic Editor, the Paste Array options will be found in Smart Paste. Go to
Edit » Smart Paste. On the right side of the Smart Paste dialog you will see the section for
Paste Array, enable the Paste Array.
Figure 23. Setup Paste Array dialog
3. Set the placement variables and click OK.

4. Click to place the array. De-select all (XA).
8.3 Smart Paste

The Schematic Editor’s Smart Paste feature allows you to transform the copy of the selected
objects into other objects as you paste them. For example you could copy a selection of Net
Labels, and Smart Paste them as Ports, or the selected Sheet Entries could be pasted as
Ports+Wires+Net Labels, all in a single paste action.
• Create a set of selected objects in the normal way, for example net labels, then copy them to
the clipboard (Ctrl+C).

• Choose Edit » Smart Paste from the menus (Ctrl+Shift+V), to display the Smart Paste
dialog, as shown in Figure 24.
Figure 24 Smart Paste dialog
8.3.1 Choose the objects to paste section

This section displays a list of all the objects in the clipboard, grouped by their type. The check
box allows you to control which set of objects you would like to paste. Before you can paste you
also need to select a Paste Action, this determines how your selected objects will be placed
onto your schematic sheet.
8.3.2 Choose Paste Action section

Before you can paste you also need to select a Paste Action. This determines how your
selected objects will be transformed as they are placed onto your schematic sheet. The Paste
As action called Themselves is a standard paste operation. The other options allow you to
transform the source object into a different object, or collection of objects, when pasting.
The possible transformations include:
• Ports, Sheet Entries or Net Labels can be transformed into equivalent ports, sheet entries,
net labels, or one text frame/note or a port and net label set per object (with wires).
• Label, Text Frame or Notes can be transformed into Label, Text Frame or Note.
• Windows Clipboard Text can be transformed into net labels, ports, sheet entries, labels, text
frames, notes, or a port and net label set per object (with wires).
• Windows Clipboard Graphics can be transformed into an image.

8.3.3 Paste Array section
Enable this option to copy your selected objects as a two-dimensional array. The total number of
copies you will create are the number of columns times the number of rows. On clicking Ok, you
will be prompted to select a start location on the document, where the array will be inserted.
Simply position the cursor at the desired location and click.
Columns
This specifies the number of columns you want in your paste array. Each column will be
separated by the Column Spacing setting. Enter positive or negative values for spacing, to
determine whether the array will be pasted to the right or left respectively for horizontal
placement, or upwards or downwards respectively for vertical placement.
Rows
This specifies the number of rows you want in your paste array. Each row will be separated by
the Row Spacing setting. Enter positive or negative values for spacing, to determine whether the
array will be pasted to the right or left respectively for horizontal placement, or upwards or
downwards respectively for vertical placement.
Text Increment
Select what method you would like to use to increment strings (such as designators) on the
copies you are pasting. You can select from the following options:
• Direction
- None – do not increment, meaning each copy will have the same strings
- Horizontal First – this will increment strings increasing the value of a string from its
predecessor by the Primary amount. The successor string to increment is found by
finding the next string in the sequence immediately to the right. Once a row has been re-
sequenced, move to the start of the next row above. Pins can also be incremented using
the Secondary setting.
- Vertical First – this will increment strings increasing the value of a string from its
predecessor by the Primary amount. The successor string to increment is found by
finding the next string in the sequence immediately above. Once a column has been re-
sequenced, move to the start of the next column to the right. Pins can also be
incremented using the Secondary setting.
• Primary
- Strings are incremented/decremented from its predecessor by the Primary amount. Pins
can also be changed using the Secondary setting.
• Secondary
- Strings are incremented/decremented from its predecessor by the Primary amount. Pins
can also be changed using the Secondary setting.
8.4 Modifying Polylines

All line objects that have multiple segments are also referred to as polylines – this includes lines,
wires and buses (wires and buses are covered in the next section). Techniques for modifying a
polyline include:
• Adding or removing a vertex – To add a new vertex, click once to select the polyline object
and display the existing vertices, click and hold anywhere along a segment (the cursor will
be a double arrow), press the INSERT key, then move the mouse to position the new vertex.
To remove a vertex click and hold on the vertex, and press the DELETE key.
• Moving a segment in the polyline – Click once to select the polyline, click and hold on the
segment, and move it to the new location.

• Moving a vertex – click once to select the polyline, then click and hold on the vertex to
move it. Note that when you move an end vertex you can also move the cursor to add a new
segment. To prevent this occurring hold the ALT key as you move the end vertex.
• Move an entire polyline – while the polyline is not selected, click and hold on it and move
the mouse to relocate it.
8.5 Font Management

Fonts are controlled via the Font dialog.
• If an object supports direct font editing, you will be able to access the Font dialog when you
double-click on the string. This dialog is displayed whenever you edit text and click the font
Change button. The default font for each object-kind is set in the Default Primitives page of
the Preferences dialog.
• Changing the font for text that cannot be edited directly, such as pin names, port names and
sheet text, is done via the Change System Font button in the Document Options dialog
(Design » Document Options). This changes the system font for the active document only.
Figure 25. Font dialog
8.6 Exercise – Schematic graphical objects

1. Open Graphical Objects.SchDoc found in the Altium Designer
6\Examples\Training\ Practice Documents folder and experiment with placing
each of the drawing objects in the space provided.
2. Select each object and observe the handles.
3. Investigate the effect of moving handles.
4. Insert a new vertex into a polyline object, and then remove it.
5. Double-click on some of the objects to display and modify their properties.
6. Close the sheet without saving.

9. Schematic electrical objects
9.1 General
Schematic electrical design objects define the physical circuit you are capturing. Electrical
objects include components (parts) and connective elements, such as wires, buses and ports.
These objects are used to create a netlist from the schematic, which is then used to transfer
circuit and connection information between design tools.
• Use the Wiring toolbar to place electrical objects.
Figure 26. Schematic electrical objects
• All Wiring Tools toolbar functions can be accessed through the Place menu.
• Text in electrical objects can be over scored, typically to indicate an active low signal, by
adding ‘\’ after the character, e.g. R\ESET would display ‘R’ as over scored text. To
overscore the entire word with a single ‘\’ character, enable the Single ‘\’ Negation option in
the Schematic – Graphical Editing page of the Preferences dialog.
In the following sections, the use of each electrical object is explained.
9.2 Summary of Electrical Objects

For an example of each electrical object, open Electrical Objects.SchDoc found in the
Altium Designer 6\Examples\Training\Practice Documents folder.
9.2.1 Wires
• Select the Place Wire toolbar button or Place » Wire.
• Wires are used to represent an electrical connection between points.
Be careful to use the Place » Wire command and not use the Line command by mistake.
• Press the SPACEBAR to change the placement mode. There are six placement modes as
follows:
- 90 degree start
- 90 degree end
- 45 degree start
- 45 degree end
- any angle
- auto wire.
• The BACKSPACE key deletes the last vertex placed.
• A wire end must fall on the connection point of an electrical object to be connected to it. For
example, the end of a wire must fall on the hot end of a pin to connect.
• Wires have the Auto Junction feature, which automatically inserts a Junction object if a wire
starts or ends on another wire or runs across a pin.

9.2.2 Buses
• Buses are used to graphically represent how a group of related signals, such as a data bus,
is connected on a sheet. They are also used to collect together all the signals belonging to a
bus on a sheet and connecting them to a port to enter or leave a sheet. In this instance, they
must have a net label of this format: D[0..7].
• Select the Place Bus toolbar button or Place » Bus. Place a bus line in the same
manner as placing wires, i.e. press SPACEBAR to change placement mode and press the
BACKSPACE key to delete the last vertex placed.
• Buses can only represent connections to ports and sheet entries and only at their end points.
9.2.3 Bus Entries

Bus entries are used to represent a connection between a wire and a bus.
To place a bus entry:
1. Ensure that an appropriate snap grid is set so that connections will be made.
2. Select the Bus Entry toolbar button or Place » Bus Entry.

3. Press the SPACEBAR to rotate the bus entry.
4. Click once to position the bus entry.
5. Right-click to stop placing bus entries.
The use of bus entries is optional. Many users prefer to place a 45-degree wire.
9.2.4 Net Labels

• A net label is used to make a net easily identifiable and also provides a method of
connecting pins belonging to the same net without placing a wire.
• A connection is made between all wires with identical net labels on a sheet. In some cases,
all wires with identical net labels in a project will be connected together. Hierarchies will be
explored in more detail during the Schematic Capture training session.
• All net labels on a net must be identical.
• The net list generator will convert all net labels to upper case.
• To associate a net label with a wire, place it so that its reference point (bottom left corner)
falls on the wire.
• The electrical grid is active when placing net labels.
• If the last character in a net label is a number, it will increment when subsequent net labels
are placed.
To place a net label:
1. Ensure that an appropriate snap grid is set so that connections will be made.
2. Select the Place Net Label toolbar button or Place » Net Label.
3. Press Tab to edit the net label text. The Net Label dialog displays.

Figure 27. Net Label dialog
4. Click on the down arrow in the Net field to display the names of nets already defined on the
sheet, or type in the new net name. Click OK.
5. Press spacebar to rotate the net label.
6. Click once to position the net label.
7. Right-click to stop placing net labels.
9.2.5 Power Ports

• All power ports with the same Net property in a project will be connected.
• To connect to a power port, make sure that a wire falls on the end of the power port pin.
• The style of the power port only changes its appearance. It does not affect the connectivity
as this is established through the Net property.
• Power ports will connect to hidden pins with the same name throughout the design,
regardless of the net identifier scope used.
• The Power Port buttons on the Wiring toolbar will only place a single power port. To change
this behavior and place multiple ports, edit the button and add the parameter Repeat=True.
To place a power port:
1. Select either the GND or VCC Power Port toolbar buttons, or Place » Power Port.
2. Press TAB to edit the power port properties for a net name other than GND or VCC.

Figure 28. Power Port dialog
3. Click to position the port. Right-click to stop placing power ports.
9.2.6 Ports
• Ports provide a method of forming connections from one sheet to another sheet.
• Click on the down arrow in the Name field to list all the Port names defined on the sheet.
• The port I/O Type is used by the ERC when checking for connection errors.
• The port style only changes the appearance of the port.
To place a port:
1. Select the Port toolbar button or Place » Port.

2. Press Tab to edit the port properties.
Figure 29. Port Properties dialog
3. Press the Spacebar to rotate or X and Y to flip.

4. Click to position one end of the port. Drag the mouse to set the port length and click to finish
the port.
5. Right-click to stop placing ports.

9.2.7 Parts
• When Place » Part (PP) is selected or you click on the Place Part toolbar button , the
Place Part dialog is displayed. You can enter the name of the component in the Lib Ref field
or you can click on the Browse button (…) to locate the part by browsing and adding the
required library.
Figure 30. Place Part dialog
• Parts can also be placed using the Place button in the Schematic Library Editor.
• When placing parts, use a snap grid that will cause the pin ends to fall on a grid point, e.g.
10. Press G to cycle through the snap grid settings of 1, 5 and 10.
9.2.8 Sheet Symbols

• Sheet symbols are used when you wish to break the design into a number of sheets.
• A sheet symbol must be placed for each schematic document in the project.
• The sheet symbol name is a descriptive name for the sheet.
• The sheet symbol filename must be the document name of the schematic
document it represents. All sheets in a project should be in the same directory.
• When changing the size of the sheet symbol, make sure the edges of the sheet symbol fall
on the snap grid to ensure connection between wires and sheet entries.
To place a sheet symbol:
1. Select the Sheet Symbol toolbar button or Place » Sheet Symbol (PS).
2. Press Tab to edit the sheet symbol name and sheet symbol file name.

3. Click to place the top left corner.
4. Click to place the bottom right corner.
5. Right-click to stop placing sheet symbols.
9.2.9 Sheet Entries

• Sheet entries are used in the sheet symbols if you are doing the design in a true hierarchical
structure, with nets interconnecting the sheet symbols.
• Each sheet entry needs a matching port on the sub-sheet.
• Use Sheet Symbols / Port Connections as the Net Identifier Scope when creating netlists
or running the Electrical Rules Checker.
To place a sheet entry:
1. Select the Place Sheet Entry toolbar button or Place » Add Sheet Entry (PA).
2. Click on the sheet symbol that the sheet entry is for and the sheet entry symbol
appears within the sheet symbol box.
3. Press Tab to edit the sheet entry properties.
4. Click on the down arrow in the name field to list all the Sheet Entry names used
on the current sheet.
5. Position the sheet entry on any side of the sheet symbol and click.
6. Right-click to stop placing sheet entries.
9.2.10 Off Sheet Connectors

Off Sheet Connectors are used to connect nets across multiple schematic sheets that are
descended from sheet entries of the same parent sheet symbol. To successfully connect a
particular net across two or more sheets, the Off Sheet Connectors on each sheet must be
assigned to the same net. Off Sheet Connectors have been added primarily to handle imports
from Orcad.
1. Select Place » Off Sheet Connector (PC).
2. Press Tab to edit the Off Sheet Connector properties.
3. Click to place the Off Sheet Connector. Right-click to exit placement mode.
9.2.11 Junctions
• The software automatically adds an auto-junction at valid connection points, including ‘T’
joins, and when a wire crosses the end of a pin. Auto-Junctions are not added at crossovers.
• Manual junctions can be used to force a junction at a crossover, select Place » Manual
Junction (PJ). The crosshair cursor appears with a junction marker (red dot) on it. Click to
place the junction marker.
• The Auto-Junction display is set in the Compiler tab of the Preferences dialog (Tools »
Schematic Preferences).
9.2.12 Parameter Sets

Some objects do not support directly specifying parameters, this includes wires and buses. To
add a parameter to these place a Parameter set. PCB design rules can also be added to wires
(nets) or buses using parameter set objects, these rule specifications are then passed to the
PCB during synchronization.

1. Select Place » Directives » Parameter Set. The cursor appears with a directive symbol
attached.
2. Press TAB to edit the parameter set in the Parameters dialog. Add in the
parameters in the Parameters Properties dialog by clicking on the Add button.
3. Position the directives symbol so that its hot point (the end of the stem) touches the wire or
bus. Click to place it.
4. Right-click to stop placing routing directives.
Note: PCB routing directives are Parameter Set objects. The separate menu entry to place
PCB Routing Directives has been retained for user compatibility with earlier versions.
9.2.13 No ERC Marker

• Placing a No ERC symbol on a node in the circuit suppresses any report warnings and
errors that may be generated when compiling the schematic. These markers can also be
suppressed for printing.
• Select the Place No ERC toolbar button or Place » Directives » No ERC. Click to place
the No ERC marker on a pin or existing ERC marker. Right-click to exit placement mode.
9.3 Exercise – Schematic electrical objects

1. Open Electrical Objects.SchDoc found in the Altium Designer
6\Examples\Training\ Practice Documents folder and experiment with placing
each of the schematic electrical objects.
2. Select each object and observe the effect of moving the handles.
4. Close the sheet without saving.

10.PCB Editor Basics
The PCB Editor opens when you open or create a PCB document. It shares all the workspace
features offered by the Altium Designer environment.
10.1 PCB Editor User Interface

Use of the PCB Editor is consistent with the Schematic Editor, with additional features that are
detailed in the following sections.
Figure 31. PCB Editor workspace
10.1.1 Layer tabs

A PCB is fabricated as a series of layers, including copper electrical, insulation, protective
masking, text and graphic overlay layers. The tabs associated with each layer are located along
the bottom edge of the PCB Editor design window. They allow you to switch the current layer
and give a visual indication of which layers are currently being displayed and which is the current
layer (the highlighted tab). If there are more layer tabs than can be displayed at one time, use
the arrows to scroll through the tabs. Layer colors will be displayed to the left of the layer
tabs and clicking the layer color will launch the Board Layers and Colors dialog.

10.1.2 MiniViewer
The MiniViewer is located at the bottom of the PCB panel, and provides the following functions:
• browsing library components
• magnified viewing of the workspace
• shows the area of the workspace that is currently displaying in the Design window
• view manipulation capabilities.
Figure 32. PCB MiniViewer
The PCB Editor panel is examined in detail during the PCB Design training session.
10.2 View Commands

The View commands can be accessed in the View menu or the Main toolbar. The table below
lists the main display commands.
Menu Command Toolbar Shortcut Description
Fit Document VD Fits all objects in the current document window
Fit Board VF Fits all objects located on signal layers in the

current document window
Area VA Display a rectangular area of document by
selecting diagonal vertices of the rectangle
Around Point VP Display a rectangular area of document by
selecting the centre and then a vertex of the
rectangle
View Selected VE Fits selected objects in the current document
Objects window
View Filtered VE Fits filtered objects in the current document
Objects window
Zoom In VI Zooms in on cursor position
Zoom Out VO Zooms out from cursor position
Zoom Last VZ Returns display to its state before the last view
command
Refresh VR Updates (redraws) the screen
Table 7. View command summary
The following shortcut keys are very useful for manipulating the view of the document window.
These shortcut keys can be used at any time, i.e. even when executing commands.

Keystroke Function
END Redraws the view
ALT+END Redraw Current layer
PAGE DOWN Zoom out (holds the current cursor position)
PAGE UP Zoom in (holds the current cursor position)
CTRL+PAGE DOWN View Document
CTRL+PAGE UP Massive Zoom In around the current cursor position
HOME View pan (pan to centre the current cursor position)
SPACEBAR Stops screen redraw
ARROW KEYS Moves the cursor by one snap grid point in the direction of arrow
SHIFT+ARROW KEY Moves the cursor by 10 snap grid points in the direction of arrow
Table 8. Shortcut keys for PCB view manipulation
10.2.1 Autopanning
Autopanning becomes active when executing commands, i.e. when the cursor appears as a
crosshair. When in this state, touching any edge of the document window will initiate
autopanning.
The autopanning speed is controlled via Autopan Options section of the Options tab within the
Preferences dialog (Tools » Preferences). Autopanning can also be turned off here.
10.2.2 Right mouse panning

You can also use the Right Mouse Scroll feature to pan across your PCB document.
1. Place the cursor in the PCB Editor workspace.
2. Right-click and hold. A hand symbol displays on the cursor.
3. Move the cursor in the desired direction to pan.
Note: Once the cursor is off the sheet, the panning will stop and you will need to release the
right button and repeat the process.
10.2.3 Displaying connection lines

The View » Connections menu command displays a menu that allows displaying or not
displaying of connection lines either by net, component net or the whole board.
10.3 Selection
Use the Select function to graphically edit an object. Below are some key points about using
select:
• An object becomes selected when you click on it with the left mouse button.
• Clicking on an object that is selected allows you to move it.
• When selected, handles appear at key points on the object. The method for editing objects
varies between objects, but typically, a click on a handle enables you to move the handle.
• When placing objects, the last object placed remains selected.
• To de-select an object, simply click in an area of the workspace where there are no objects.

Note: PCB components cannot be graphically edited unless you unlock the component
primitives. Component footprints are normally only edited in the PCB footprint library.
The PCB Editor provides selection capabilities that are similar, although not identical, to
selection in other Windows applications.
Below are some key points about selection in the PCB Editor:
• Selected objects can be cut or copied to the clipboard. They can then be pasted elsewhere
onto the current PCB file or into another PCB file.
• Selection is normally cumulative. Objects that have been selected remain selected until they
are de-selected. This can be turned off by de-selecting Extend Selection in the Options tab
of the Preferences dialog.
• There are a number of PCB Editor commands that operate on the selected group of objects,
e.g. the Tools » Interactive Placement commands.
• The PCB Editor uses a special proprietary clipboard that supports PCB data such as
connectivity and layer properties of primitives. When a copy action is performed a graphical
metafile representation is also placed on the Windows clipboard, ready for pasting into
another Windows application.
To select objects, you can use the following methods.
Method Function
Click and drag box around Select all objects enclosed by drag area
SHIFT+ click Select several objects (on a selected object this will de-
select it).
Edit » Select menu (S) Select Inside Area, Outside Area or All
Select Inside Area
This button on main toolbar
Browse section of the Editor The following browsers have a Select button to select
panel the highlighted objects: Nets; Components; Net
Classes; Component Classes and Rules
Table 9. Select command summary
Once objects have been selected, you can:

Function Menu command Shortcut keys
Cut Edit » Cut CTRL+X
Copy Edit » Copy CTRL+C
Paste Edit » Paste CTRL+V
Delete Edit » Clear CTRL+DELETE
Move Edit » Move » Move Selection Click-and-hold

Rotate Edit » Move » Rotate Selection SPACEBAR
Flip Edit » Move » Flip Selection X or Y

Align Tools » Interactive Placement » Align I (Align submenu)
Jump to Edit » Jump » Selection J (Jump submenu)
View View » Selected Objects V (View submenu)
Convert Tools » Convert T (Tools submenu)
Table 10. Selected object command summary

To de-select objects, use the Edit » DeSelect menu (X) commands or the DeSelect All
button on the Main toolbar.
10.3.1 Selection hints

• Before starting a selection, it is a good idea to de-select all objects first.
• Only items that fall completely inside the selection area will be selected.
• The selection color is set in the Board Layers & Colors dialog (Design » Board Layers &
Colors).
• Pressing the S key pops up the Select menu.
• Pressing the X key pops up the DeSelect menu.
• Eight selection memories are available in the PCB editor which can be used to store and
recall the selection state of up to eight sets of objects on the PCB. See 7.3.2 Selection
memory for more information.
10.4 Other mouse operations

The mouse operations listed below are universal throughout the PCB Editor and should be used
in preference to menu commands.
Mouse Operation Function
Double-click Change an object
Click ENTER
Right-click ESCAPE
Table 11. General mouse shortcut summary
10.5 Multiple objects at the same location

When working in the PCB Editor, the situation often occurs where a click to perform an operation
is made where there are multiple objects. In this situation, the PCB Editor displays a menu listing
all the objects it has detected at the location of the click, with a small preview of the object
currently chosen in the menu. You can then select the required object off this menu.
Figure 33. Menu listing objects at mouse click point

10.6 Jump menu
The Jump menu commands provide you with a number of commands for positioning the cursor.
The Jump sub-menu commands are described as follows:
Menu Command Shortcut Description
Absolute Origin JA Positions the cursor at the Absolute Origin.
CTRL+HOME also does this.
Current Origin JO Positions the cursor at the Origin. ctrl+end also
does this.
New Location JL Positions the cursor at a specified coordinate.
Component JC Positions the cursor over the specified
component.
Net JN Positions the cursor over a pad assigned to the
specified net.
Pad JP Positions the cursor over the specified pad.
String JS Positions the cursor over the specified text
string in the PCB file.
Error Marker JE Positions the cursor over the next DRC error
marker.
Selection JT Zooms in on the selected group.
Table 12. Jump menu commands
If a Jump command does not appear to jump to the correct location, zoom in to display the
correct coordinates.
10.6.1 Location marks

You can store up to ten locations in your PCB document. You can then return to these locations
using the Jump command. To set a location marker, select Edit » Jump » Set Location Marks
and select from location marks 1 to 10. You then use the cursor to position the location mark.
To return to that location, select Edit » Jump » Location marks (JM), choose the location
marker number and the display will be centered on that location mark.
10.7 Exercise — PCB basics

1. Open 4 Port Serial Interface.PcbDoc, located in the \Altium Designer
6\Examples\Reference Designs\4 Port Serial Interface folder.
2. Work through some of the commands in Tables 9 – 13 in this section to get familiar with the
PCB display and selection commands listed. Try using the commands from the toolbar and
using shortcut keys.
3. Turn off Visible Grid 2, set Visible Grid 1 to 50 mil and set the Snap Grid to 25 mil using the
Board Options dialog (Design » Board Options).
4. Place a fill using the Place » Fill menu command. Observe that when you exit this command
the fill is selected. Move the handles by clicking on them. Move the fill by clicking on the
object. Rotate the fill by clicking on the circle within the fill. De-select the object by clicking at
a point away from any object.
5. Perform the View » Fit Document command on your PCB file.
6. Move a component by clicking and holding on it.

7. While you are moving the component, press the SPACEBAR to rotate it (SHIFT+SPACEBAR for
clockwise rotation) and press the L key to flip the component to the other side of the board
(you may need to enable layers to see all the component primitives when it is on the bottom
layer).
8. Click another component and start to move it. While moving it press the Alt key, noting how
the movement is now constrained to the horizontal or vertical direction only. The choice
between constraining horizontal or vertical is defined by the proximity of the cursor to the
object – simply push the object in the desired direction to see the effect. This feature is
particularly useful if you want to move a component and maintain its alignment.
9. Select a group of components (click-and-hold and then drag the cursor over the
components).
10. Select the Edit » Copy menu command to copy the selected group to the Altium Designer
clipboard. Don’t forget to give the reference location.
11. Select the Edit » Paste menu command. The contents of the clipboard will now be moving
with the cursor. Rotate and flip the group as you did when moving a component. Place the
group of components by clicking at the required location.
12. Close the document without saving the changes.

11.PCB design objects
11.1 General
A variety of objects is available for use in designing a PCB. Most objects placed in a PCB
document will define copper areas or voids. This applies to both electrical objects, such as tracks
and pads, and non-electrical objects, such as text and dimensioning. It is therefore important to
keep in mind the width of the lines used to define each object and the layer on which the object
is placed.
Most of the PCB design objects are also referred to as primitives that can be edited in the PCB
Editor. Components are made up of a variety of primitive objects and are editable only in the
PCB Library Editor. Placing components, polygon planes, split planes and rooms will be covered
in detail during the PCB Design training session.
For an example of each PCB design object, open PCB Objects.PcbDoc found in the
Practice Documents folder in \Altium Designer 6\Examples\Training.
Figure 34. The PCB Editor primitive objects
• The object placement commands are selected using either the Place menu or the Wiring
and Utilities toolbars.
• To set the properties of an object while placing it, press the TAB key and the Properties
dialog for that object will be displayed.
• Once an object is placed, you can change its properties by double-clicking on it to display
the Properties dialog for that object. Alternatively, you can click once to select an object, then
edit the properties in the Inspector panel (F11 to open).
• Set the default properties for each object type in the Defaults tab of the Preferences dialog
(Tools » Preferences).
• The current layer determines the layer on which the object is placed.

11.2 Tracks
The Interactive Routing command is used to place tracks with associated net information.
To start Interactive Routing, select the toolbar button or Place » Interactive Routing (PT).
Click where you wish to begin the first track and then use the track placement and start/end
modes detailed below.
Pressing TAB during interactive routing will display the Interactive Routing dialog where you can
set widths, sizes and related design rules.
You can change the signal layer that you
are routing on by pressing the * (asterisk)
shortcut key on the keypad and a via will
be automatically added.
Track Placement modes

Once you are in the interactive routing
command and have clicked to start the
first track, press SHIFT +SPACEBAR to
change the placement mode. Each mode
defines a different corner style. Check the
status bar to see which mode is active.
There are five track placement modes:
1. Any angle
2. 45 degree
3. 45 degree with arc - 45 degree line
with rounded corner.
4. 90 degree (horizontal and vertical).
5. 90 degree with arc - horizontal and
Track Placement modes
vertical orientation with rounded
corner.
Note: The two arc in corner modes use the Corner Style design rule to define the arc size. If
the rule includes a range in the setback size then you can adjust the arc within this range
during track placement by holding the comma key (,) to make it smaller, or the full stop key (.)
to make it bigger.
Start and Finish modes

In addition, the track placement modes are supplemented with a Start Mode and a Finish Mode
(see image Track Placement Modes above). After you have selected the Track Placement mode,
you can press the SPACEBAR to toggle between the Start Mode option and the Finish Mode
option.
If a track starts at an object with a net assigned to it, the track will also be assigned to the net.
The interactive routing command will adhere to any rules assigned to that net.
A routed net can be highlighted by holding down the CTRL key as you click on it. Use
SHIFT+CTRL+CLICK to highlight multiple nets.
11.2.1 Editing tracks

When a track segment is selected, three handles appear — one at each end of the segment and
one in the middle. Below are the actions that can be performed.

To re-position a segment end
1. Place the cursor on one of the end handles.
2. Click and release the left mouse button.
3. Move cursor (and the attached vertex) to new location.
Inserting a vertex in the track segment

1. Place the cursor on the middle handle.
2. Click and release the left mouse button.
3. Move the cursor (the vertex will move with the cursor).
Drag the track segment

1. Click on the track segment away from any handles.
2. Drag the segment to a new location.
11.2.2 More track editing commands

Re-route
This rerouting command allows you to break a track into several segments and move them.
1. Select Edit » Move » Re-route from the menu.
2. Click on a track segment and then re-route by moving the new vertex and clicking again to
create more segments.
3. Right-click or press ESC to end the command.
Break
Use this command to insert a new vertex anywhere on an existing track and break the track into
two segments. The new vertex may be dragged to a new location when the break is formed.
1. Select Edit » Move » Break Track from the menu.
2. Click on segment of track to insert a vertex and move it.
Alternatively, as a shortcut, hold down CTRL+SHIFT before clicking to break one track at a time.
Drag End
This command will only move the end of the track that you click on.
1. Select Edit » Move » Drag Track End from the menu.
2. Click on an existing track end and then move it. The other end of the track remains in its
original position.
11.3 Lines
The Place Line command is provided for placing lines other than tracks, such as the board
outline or keepout boundaries on non-electrical layers. Line placement behaves exactly the
same as track placement during interactive routing, however, lines have no nets associated with
them. When placed on non-electrical layers, lines are not constrained by the design rules.
Pressing TAB when placing lines displays the Line Constraints dialog. Note, however, that when
you double-click on a line to edit its properties, the Track dialog displays.
To draw lines, select the toolbar button or Place » Line.

11.4 Pads
• Place pads using the Place » Pad command or the Place Pad toolbar button .
• Pads are mainly used as part of components but can be used as individual objects, such as
testpoints or mounting holes.
Figure 35. Pad Properties dialog
• Pad properties are set in the Pad dialog that is displayed by pressing the TAB key while
placing the pad or double-clicking on a placed pad.
• If a pad is to have different sizes on the mid layers or bottom layer, check Top-Middle-
Bottom in the Size and Shape section. Click on Full Stack and then Edit Full Pad Layer
Definition to edit more complicated stack ups.
• Assign a net to the pad, define the pad’s electrical type (i.e. load, terminator or source) and
set whether or not the pad’s hole is plated. The NC drilling software selects separate drill
tools for plated and non-plated holes.
• Pads can be assigned as Top and/or Bottom Layer Testpoints.

11.5 Vias
• Vias can be placed using the Place » Via command or the Place Via toolbar button , but
they are normally placed automatically when you change layers while placing a track. The
Autorouter also places vias.
• Via properties are set in the Via dialog which is displayed by pressing the TAB key while
placing a via, or by double-clicking on a placed via. The via diameter, hole size, net and Start
and Finish layers are set in the Via dialog.
Figure 36. Via Properties dialog
• Setting the Start and Finish layers to any layers other than Top Layer and Bottom Layer
automatically assign the via as a blind or buried via. Blind and buried vias can be easily
identified as their hole is displayed as two half circles with different colors.
• Vias can be assigned as Top and/or Bottom Layer testpoints.
• If a net being manually routed is to connect to an internal power plane, press the / (forward
slash) key on the numeric keypad to place a via connecting to the appropriate power plane.
This will work in all track placement modes except ‘any angle’ mode.
Solder Mask Expansions

Checking the Specify expansions value check box allows you to override the Solder Mask
setting in the design rules by filling in the required expansion in the field provided.
Tenting
Checking the Tenting check boxes causes any Solder Mask settings in the design rules to be
ignored and results in no opening in the solder mask for this via.

11.6 Strings
• A string is a single line of text that is placed using the Place » String command or the Place
String toolbar button .
• String properties are set in the String dialog that is displayed by pressing the TAB key while
placing a string, or double-clicking on a placed string. The actual text string to be placed is
entered in the Text field.
Figure 37. String Properties dialog
11.6.1 Special Strings

To assist in producing manufacturing documentation, special strings are provided. These include
strings, such as .Arc_Count and .Component _Count, that display the number of objects in the
PCB file when the PCB document is printed or plotted. Other special strings relate to layer
names, file names and printing options. The .Comment and .Designator strings are used when
creating component footprints. The .Legend string shows a drill symbol legend when the string is
placed on the Drill Guide layer.
While most special strings are only converted during printing or plotting, .Layer_Name,
.Pcb_File_Name and .Pcb_File_Name_No_Path can be viewed on screen. To see the values of
these special strings placed on a PCB, select Convert Special Strings in the Display tab of the
Preferences dialog (Tools » Preferences). For example, the special string placed
on the Top Layer of a PCB document would now display on the screen as .
You place a special string using the Place » String command, but instead of filling in the Text
field in the String dialog, use the drop-down list to display the special strings (see Figure 38).
Select the desired special string, press OK and click to place it.
Figure 38. String dialog showing special strings

11.7 Fills
• The Fill object is a solid rectangle and can be placed on any layer. A fill is placed using the
Place » Fill command or the Place Fill toolbar button .
• To place a fill, the first click defines a corner of the fill and then the next click defines the
opposite corner of the fill. Fill properties are set in the Fill dialog that is displayed by pressing
the TAB key while placing a fill, or double-clicking on a placed fill.
• When a fill is selected, you can change its size by clicking and dragging its handles and you
can rotate it by clicking on the small circle.
Figure 39. Fill dialog
11.8 Copper Region

• The Copper Region object is a multi-sided solid object. Although it is referred to as a Copper
Region it can be placed on any design layer, including mechanical, mask, plane, or
silkscreen layers.
• A region is placed using the Place » Copper Region command, or the Place Copper
Region toolbar button .
• To place a region, click to define each vertex on the multi-sided object, when finished right-
click to drop out of vertex placement mode. Region properties are set in the Region dialog
that is displayed by pressing the TAB key while placing a region, or double-clicking on a
placed region.
• A region can also be used to create a void in a solid polygon pour (note that they cannot be
used to create a void in a hatched polygon pour).
Figure 40. Region dialog, and an example of a region

11.9 Arcs
The table below lists the arc placement options:
Place Menu Command Placement Toolbar
Arc (Edge)
Arc (Centre)
Arc (Any Angle)
Full Circle
Table 13. Arc Placement commands
• All of the above commands result in an arc object being placed.

• An arc can be placed on any layer.
• Arc properties are set in the Arc dialog that is displayed by pressing the TAB key while
placing an arc, or double-clicking on a placed arc.
Figure 41. Arc Properties dialog
11.10 Dimensions and coordinates

Dimensions and coordinates can be added to the current layer. All measurements and cursor
positions are displayed relative to the current origin. The absolute origin (0, 0) for a PCB
document is the lower left corner of the design area.
You can set the current origin to be any point in the PCB workspace by selecting Edit » Origin »
Set. Click where you want to set the new current origin. To set the current origin back to the
absolute origin, select Edit » Origin » Reset.
11.10.1 Placing dimensions

Dimensions can be added to the current layer by selecting
from the Dimension tools on the Utilities toolbar (View »
Toolbars » Utilities) or the Place » Dimension (PD)
submenu. Click to define the start and end points. Watch
the Status bar for instructions on placing the dimension.
Press TAB to set the properties, such as the text height and
width. Right-click or press ESC to exit the command.
The dimension value automatically updates as you move the start or end points.

11.10.2 Placing coordinates
A coordinate object places X,Y coordinate information measured as the horizontal (X) and
vertical (Y) distance of the coordinate marker from the current origin. Select the Place
Coordinate toolbar button or Place » Coordinate (PO). Click to place the coordinate. Right-
click or press ESC to exit the command. The position values are automatically updated when you
move a coordinate object.
11.11 Keepout objects

Tracks, fills and arcs can be used to assign an area on a specific electrical layer to act as a
routing barrier. Objects defined as keepouts are ignored by output operations, such as
photoplotting and printing.
A keepout can be defined using the commands in the Place » Keepout sub-menu (PK). Existing
tracks, fills and arcs can be defined as layer-specific keepouts by selecting the Keepout option in
the object’s Properties dialog.
11.12 Paste commands

There is an additional paste command in the PCB Editor — Edit » Paste Special. This
command can be used for panelizing an entire PCB design or pasting multiple copies of selected
objects.
Before using this command, copy selected objects to the clipboard using Edit » Copy (EC) or
Edit » Cut. Click to select a reference point, i.e. the point used to hold the selection while
positioning it during the Paste operation.
From the Paste Special dialog, you can choose to paste objects on the current layer (selected
option) or retain their original layers (deselected). Clicking on Keep Net Name retains the
original net names of pasted objects. If this option is not selected, the pasted object’s net
attribute is set to ‘No net’.
Figure 42. Paste Special dialog
If components have been copied, the other options will become selectable. The Duplicate
Designator option should be selected when panelizing an entire design to keep the designator
names the same on each panel. Otherwise, generic default designator names are used.
Select the Add to Component Class option to make sure pasted components are added to the
same class as the components from which they were copied.

11.13 Exercise – PCB design objects
1. Open PCB Objects.PcbDoc found in the \Altium Designer
6\Examples\Training\Practice Documents folder. Experiment with placing each of
the PCB design objects in the spaces provided.
2. Place a few pads and then connect them by placing tracks, using the various track
placement modes.
3. Select each object and observe the effect of moving the handles.
5. Close the PCB document without saving.

12.Project Navigation and Cross Probing
12.1 Compiling the PCB project
Compiling means creating a connective model (internal netlist) which converts a set of drawings
into an electrically wired project. Design navigation is also enabled by compiling the design. To
compile a PCB project, select Project » Compile PCB Project.
12.2 Navigating
The DXP Navigator panel supports the traditional click-to-highlight style of browsing the design.
As you click, the selected object(s) is presented on screen. You can also analyze and trace the
connectivity in the design – either spatially in the actual workspace, or in the Navigator panel.
• The Navigator panel can be used to browse and cross probe to documents, components,
buses, nets and pins. A single click on an entry in the panel will browse to that object in the
source schematics and VHDL documents.
• Hold the Alt key as you click to simultaneously cross probe to the same object(s) on the
PCB. The current document remains active, so both must be displayed for this to have any
visible effect.
Figure 43. Holding down the Alt key as you click in the Navigator panel will highlight corresponding objects
in both schematic and PCB documents.
• Navigation highlighting options are controlled from within the DXP » Preferences » System
» Navigation. Alternately this dialog can be accessed by clicking the … button to the right of
the Interactive Navigation button.

Figure 44. Preference dialogue controlling the highlighting navigation options.
The Connective Graph option is useful for showing the connection relationships between
different components (green links) and Nets (red links).
• Pressing the Interactive Navigation button causes the component instance information to be
updated in the Navigator panel when design elements are selected in the schematic sheet.
• The Navigator panel lets you view components and nets by individual sheets or hierarchical
groups. Use the flattened hierarchy to see all the components and nets in your design.
12.3 Cross probing from the schematic to the PCB

Cross Probing is a powerful searching tool to help you locate objects in other editors by selecting
the object in the current editor.
• Often when you are analyzing/debugging your design you will want to cross probe from the
schematic to the PCB. Full cross probing support is provided, for nets, pins and components.
• You can also cross probe all nets in a bus, and the contents of an entire sheet.
• Use the Cross Probe button to be able to click on an object in one view (say the schematic)
and display the same object in another view (say the PCB).
• The default behavior is to find the object in the target document then return to the source
document. Hold the CTRL key as you cross probe to jump to the target document.
• You can also cross probe using the Navigator panel. Hold the ALT key as you click on
something in the panel to highlight it in both the schematic and the PCB. This can be a pin, a
component, a net, bus, or a sheet. This works well if you split the view to display both the
schematic and the PCB.

12.4 Exercise — Navigation and Cross Probing
1. Open the project 4 Port Serial Interface.PRJPCB, found in the \Altium
Designer 6\Examples\Reference Designs\4 Port Serial Interface folder.
2. Open the schematic, ISA Bus and Address Decoding.SchDoc and the PCB
document, 4 Port Serial Interface.PcbDoc. Tile these windows vertically.
3. Make ISA Bus and Address Decoding.SchDoc the active document. Use the
Navigation panel to highlight components and nets in the schematic.
4. Hold down the Alt key when selecting a component or net from the Navigation panel to cross
probe to the PCB.
5. Make 4 Port Serial Interface.PcbDoc the active document and click on the Cross
Probe toolbar button.
6. Click on component S1. The Schematic Editor opens the related schematic document and
displays the component S1 centered in the Design window.
7. Click on the Cross Probe toolbar button in the Schematic Editor and click on D1. The PCB
document displays zoomed in on the component.
8. Now try cross probing nets and pads/pins between the open editors.
9. Close all open documents without saving any changes.

13.The DXP Data Editing System
Highlighting Engine
Design data Filtering Engine (Mask, Select, Zoom)
Display data
Query Engine
Filter FSO Navigator

panel dialog panel
Figure 45. Diagram of the filtering/highlighting system
One of the greatest challenges you face as a designer is managing the large amounts of design
data that is created during the design process. To facilitate this, Altium Designer has a powerful
data editing system. This system allows you to manage, find and edit design data in a variety of
ways.
To provide flexible and appropriate methods of editing data, three alternate views of the data can
be used to access and edit design objects:
• The traditional graphical view
• The Inspector panel (press F11 to toggle it on and off)
• The List panel (press Shift+F12 to toggle it on and off)
The Inspector displays the attributes of the currently selected object(s), with the total number
selected being listed at the bottom. Note that the Inspector can be used to edit different kinds of
objects simultaneously.
The List panel gives a spreadsheet-like, or tabular list of objects in the schematic sheet or PCB
workspace. Individual or multiple cells can be edited in the List panel.
A powerful filtering engine is used to control the amount of data that is presented for editing in all
three views. Data can be filtered using the Find Similar Objects dialog, the PCB editor panel, or
by writing a query in the Filter panel. Figure 45 shows a diagram of the data editing system.
The Filter panel is used to type in a query that filters the entire data set, reducing both the
graphical display and the List panel to display only those objects that satisfy the query. In the
graphical display this can be shown by the fading of objects that have been filtered out (and are
no longer editable).
One of the powerful features of this data editing system is the ability to edit multiple objects
simultaneously. The basic approach to use the data editing system is to:
Select the required objects for editing
Inspectthe objects
Edit the object attribute(s).

13.1 Finding and Selecting Objects
13.1.1 Using the PCB Panel

The PCB panel can be used for browsing objects in a PCB.
• The options at the top of the panel control how the chosen
object(s) will be highlighted:
- Mask: this option fades all objects except those of
interest. While masked objects are still visible, they can
not be edited. Use the control at the bottom
right to control the amount of fading.
- Select: select the target object(s). Selected objects are
highlighted using various white shading techniques.
- Zoom: zoom in to fit the highlighted objects in.
- Clear existing: enable this to automatically clear any
existing highlighting whenever you choose another
object.
• Use the CTRL+Click combination to highlight multiple objects.
• Right-click in the panel to control which primitive kinds are
displayed, this is very handy for excluding certain object
kinds.
• Click the Clear button to clear all masking and

selections.
• Highlighting results are displayed in all three views – Figure 46. Using the PCB panel
graphical, List and Inspector (if Selection is enabled). to find and select objects.
Figure 47. Using the panel to highlight two nets. Note that all other objects have been faded (masked).

13.1.2 Using the Find Similar Objects dialog
The panel is ideal when working with
group-type objects like components and
nets. When you are working at a primitive
object level, it can be more efficient to use
the Find Similar Objects dialog.
• To launch the Find Similar Objects
dialog, right-click on an object of
interest, and select Find Similar from
the floating menu.
• The dialog will appear, listing the
attributes of that object. Next to each
attribute is a drop down. Set this if you
wish to use it as a matching criteria.
• Clicking Apply will run the search for
matching objects but will leave the
dialog open. Clicking OK will close the
dialog and run the search.
• This will select all objects that match
the find criteria. Figure 48 shows the
Find Similar Objects dialog configured
to find and select all PCB text strings
that are component comments.
• Enable the Run Inspector check box
to automatically launch the Inspector, Figure 48. Using the Find Similar Objects dialog to
where you can edit any attribute(s) of highlight all component comments.
the found and selected objects.
13.1.3 Using the Filter Panel

Underlying the techniques for finding objects described so far is a powerful data filtering engine.
You can also access this engine directly by writing a query to describe the objects that you wish
to target.
• Press F12 to toggle the Filter panel on, where you write the query.
• A Query is an instruction, written using query language keywords. For example, entering the
query IsComment or IsDesignator in the PCB editor List panel will reduce the contents
of both the graphical display and the List panel to only display the component designator and
comment strings on the PCB.
• For a complete list of query keywords, click the Helper button. When the cursor is on a
keyword, press the F1 key in the Query Helper dialog for a complete description of that
keyword. Press F1 when the cursor is within an arithmetic operator for information on the
operators.
• Refer to the document, An Insiders Guide to the Query Language article.pdf for detailed
information on writing queries.
Figure 49. Use the Filter panel to query the design data and access specific objects.

13.1.4 Inspecting and editing the selected objects
The Inspector panel is used to examine the properties
of and edit the currently selected objects. Use the
Inspector when you want to apply an edit to all the
selected objects.
• Press F11 to toggle the Inspector panel on/off.
• The Inspector can be used to examine 1 or many
objects.
• The set of selected objects can be built up in many
ways, including; manually, by writing a query, or
using the Find Similar dialog.
• Dissimilar objects can be selected and edited, only
their common attributes will be available for editing.
• After changing a value in the Inspector, press
ENTER to apply it.
Figure 50. The Inspector displaying the
• String substitutions can be performed in the properties of the selected designator and
Inspector panel. comment strings.
The List panel can also be used to examine and edit the properties of objects. Use the List panel
when you want to examine/compare attributes, or edit only some of the objects.
• Press Shift+F12 to toggle the List panel on/off.
• An individual cell in the List can be edited, press the SPACEBAR or right-click and select Edit.
• Multiple cells can be edited simultaneously, select them, press the SPACEBAR, type in the
new value and press ENTER on the keyboard.
• Blocks of cell data can be copied and pasted to/from a spreadsheet.
• For group-type components, such as components or nets, you can include their primitive
parts (child objects) by right-clicking and choosing the appropriate Show Children option.
• When there are multiple object types displayed, only attributes that are common to all are
displayed. You can remove objects from display in the List panel, select those you wish to
keep, right-click and choose Remove Non-Selected from the menu.
• Column display is managed by right-clicking on the column headers and selecting Choose
Columns.
Figure 51. Using the List to examine/edit all designator and comment strings.

13.2 Exercises – editing objects
This exercise will demonstrate different ways of changing the width of the component overlay
tracks and arcs and the height of component text.
13.2.1 Editing the width of overlay tracks and arcs

1. Open the 4 Port Serial Interface example project, then open the PCB.
2. Set the PCB panel to browse Components, and enable all four of the highlight options at the
top.
3. Right-click in the Component Primitives region of the panel and, in the floating menu, disable
the display of pads and vias.
4. Right-click in the components region and choose Select All from the menu. All components
on the board will be selected.
5. If you scroll in the Component Primitives region of the panel you will notice that there are
only tracks and arcs listed. Right-click in this region and choose Select All.
6. Click once on the workspace to make it active (you will not loose the selection if you only
click once), then press F11 to display the Inspector. It should indicate 182 objects selected
and display the common attributes that both tracks and arcs share, as shown in Figure 50.
7. In the Inspector, click in the Width field, type in a new width of 6, then press ENTER on the
keyboard to apply the change. All component overlay tracks and arcs will now have a width
of 6 mils.
8. Click the Clear button (SHIFT+C) at the bottom right to remove all masks and selections.
Note: A number of useful queries have been stored in the query Filter menu. Press Y to pop
up this menu, then choose Examples. It includes an option to filter out all objects except the
component tracks and arcs on the overlay. Your own Favorite queries are automatically added
to the Filter popup menu.
13.2.2 Changing the visibility of the component Comment strings

1. Locate component S1 on the 4 Port Serial Interface PCB.
2. Right-click on the comment string and select Find Similar from the floating menu.
3. The Find Similar dialog appears, presenting the attributes of the object clicked on. Note that
the String Type attribute has a value of Comment. Set the match by setting for this attribute
to Same (as shown in Figure 48).
4. Enable the Run Inspector check box, clear the Create Expression check box and click OK.
5. The Inspector will appear with 36 objects selected. Click on the Hide attribute, clear the
checkbox and press ENTER to apply the change.
All the component comment strings will now be visible on the board.
13.2.3 Changing the height of designator and comment strings

1. In the editing region at the top of the List panel, type the query
IsDesignator or IsComment and then click the Apply button.
2. Select the contents of the Text Height column, press the SPACEBAR to edit one of the cells,
type in a new value of 40 and press ENTER on the keyboard to apply the change. Note that
the editing of the string height could also have been done in the Inspector.
For more examples on editing multiple objects, refer to the tutorial Editing Multiple Objects

14.Text Editor
The Text Editor is a general-purpose text editor that you can use to view or edit text documents.
There are a number of commands in the various document editors that generate text documents.
These automatically open the Text Editor and display the text document that was generated.
For example, if you select the Reports » Simple BOM command to generate a BOM in the
Schematic Editor two BOM files are created (*.BOM and *.CSV) and opened in the Text Editor,
displaying as shown below in Figure 52.
Figure 52. The Text Editor displaying a simple Bill of Materials (BOM) report
The Text Editor options can be set by selecting Tools » Editor Preferences.
14.1 Searching for text

To search for text, you can use either Edit » Find or alternatively, Ctrl + F to launch the Find
Text dialog. To search for a specific string, enter that string in the Text to Find field and set the
search criteria below. Clicking OK will search the referenced document(s) for text matching the
criteria specified and return a list of matching strings in the Messages panel. The asterisk ‘*’ can
be used as a wildcard while searching to expand searches to include unknown characters or
series’ of characters at the beginning, in the middle, or at the end of a search string.
14.2 Text bookmarks

Bookmarks enable you to mark a cursor location in the text file. You can then return to that
location as required. There are ten location markers in the Text Editor. The Bookmark controls
are located in the right click menu.

To set a location mark, position the cursor at the desired location and right click and select
Toggle Bookmarks to set a bookmark. To recall a specific location, right click and select the
Bookmark from the GoTo Bookmarks submenu.
14.3 Syntax highlighting

The Text Editor has a feature known as syntax highlighting, which is very useful when working
with structured documents such as source files for programming languages. Syntax highlighting
displays key words in the file in predefined colors.
The syntax highlighting style used in a document is determined by the document’s file extension.
For example, files with the extension .bas, will use the syntax highlighting defined for Visual
Basic.
You can define your own syntax highlighting and modify existing definitions in the Colors page
of the Text Editors section of the Preferences dialog (DXP » Preferences).

15.Using the Help system
15.1 Dynamic On-line Help
Altium Designer includes a dedicated panel for dynamically displaying context sensitive help as
you work. The panel, called the Knowledge Center panel (Figure 53) has two sections, the
upper section displays help about the current menu entry, toolbar button, selected object, panel,
and so on. The lower section is the library navigation area, here you can browse to open the
PDF-based articles, application notes, tutorials and other references.
The help text loads automatically into the upper region of the Knowledge Center panel if the
Autoupdate button is enabled, indicated by the outline around the button. If it is not enabled you
can force the content to load by pressing F1.
Figure 53. The Knowledge Center panel is used to access the Documentation Library.

15.2 Searching the Documentation Library
Enter a search string in the field at the bottom of the panel and click Search to search all PDF-
based documentation in the Documentation Library. Note that the scope or this searching is
controlled by your current location in the library, open a specific sub-folder to restrict searching to
that topic area, return to the top of the library to search the entire library. Figure 53 shows a
search for the string interactive routing, that is restricted to the Board Layout topics.
15.3 Using F1
The Altium Designer environment includes extensive F1 help support. Virtually every aspect of
the interface has F1 help support, for example:
• Press F1 over a menu entry, toolbar button or dialog, to directly open the help topic about
that command/dialog.
• Press F1 over a panel to obtain detailed help specific to that panel.
• Press F1 in the Editor environment for help on that editor. If there is a design object under
the cursor then you will be presented with help on the object.
15.4 What's This Help

Use the dialog What's This Help ? to gain detailed information about each of the individual
options available in a dialog.

16.Using the Altium website
The Altium website (www.altium.com)includes extensive information about Altium’s products
and services, including access to technical information and Service Packs. It is good practice to
regularly visit the website.
• Click on the Community section at the top the Home Page to access a variety of customer
resources.
• The Knowledge Base and Learning Guides are two of the sections available in the
Support sub-page. Learning guides, such as tutorials, articles and white papers, are in .PDF
format.
• The Altium Technical Forums can be joined by choosing the Forums option in the
Community menu at the top of the Home Page. The Altium Designer forum is very popular
amongst both Altium product users and Altium staff, as a meeting place where they can
exchange advice and information.
16.1 Knowledge Base

A search engine is provided to search the Knowledge Base by words, product and date.
Figure 54. The Knowledge Base search engine
• Use the four text entry boxes on the left-hand side of the search form to enter keywords and
phases that you wish to search for. Use the drop-down lists on the right-hand side of the
search form to further restrict your search, if necessary.
• The search words are not case sensitive.
• You can enter words in any or all of the text entry fields to form complex search criteria. For
example, the search shown in Figure 54 would find items that contain the words "fpga" and
contain the phrase "place and route". You may enter partial words to find multiple forms of
the word, e.g. "rout" will match route, router, autoroute and unroute.
• To find new and updated items, set the Item Updated dropdown list to the desired time span
and leave all other fields at their defaults.
• If the information you require is not available, you can email your local Altium Sales
Representative and your question will be investigated.

Creating Library Components
Training Module
Libraries and Components Training Module ii

Creating Library Components Training Module
1. Introduction to Library Editing ................................................................................ 2-1
2. Schematic Library Editor.......................................................................................... 2-2
2.1 Schematic Library Editor Terminology ........................................................... 2-3
2.2 Component Properties ................................................................................... 2-5
2.3 Exercise – Creating a new component symbol .............................................. 2-6
3. PCB Library Editor .................................................................................................... 2-8
3.1 The PCB Library workspace........................................................................... 2-8
3.2 PCB Library Editor panel................................................................................ 2-9
3.3 Creating a component using the Component Wizard .................................... 2-9
3.4 Manually creating a component ................................................................... 2-10
3.5 Copying a component .................................................................................. 2-10
3.6 Special strings in the Library Editor.............................................................. 2-10
3.7 Component Rule Check ............................................................................... 2-11
3.8 Exercise – Creating the component footprint ............................................... 2-12
4. Adding Model and Parameter Detail to a Component ........................................ 2-14
4.1 Adding a model ............................................................................................ 2-14
4.2 Exercise – Adding a footprint using the Model Manager ............................. 2-15
4.3 Component Parameters ............................................................................... 2-17
4.4 Exercise – adding a component parameter ................................................. 2-18
4.5 Exercise – Using the new component on a schematic ................................ 2-19
4.6 Adding and Modifying Component Parameters ........................................... 2-19
4.7 Exercise – Editing Parameters in the Parameter Manager.......................... 2-20
5. Creating a multi-part component........................................................................... 2-21
6. Modifying and Updating Components .................................................................. 2-22
6.1 Modifying a component used in your schematic .......................................... 2-22
6.2 Updating the components on the schematic ................................................ 2-22
7. Library Reports ....................................................................................................... 2-23
7.1 Library Editor reports.................................................................................... 2-23
Libraries and Components Training Module iii

1. Introduction to Library Editing
The Creating Library Components section explains the various types of libraries, and the
fundamental way in which library documents are created and managed in Altium Designer.
The process of using the Schematic and PCB Library editors will be explored with hands-on
exercises showing how to create single and multi-part packages in a schematic library, creating
PCB footprints, attaching models, and working with separate library files. It will also introduce
Integrated Libraries, a compiled, secure and portable form of library file.
This section will also discuss adding component parameters and provide hands-on exercises on
importing pin information from vendor pin lists.
Figure1. Outlines the workflow to follow when creating component libraries in Altium Designer.
Figure 1. The Altium Designer component creation workflow.
Libraries and Components Training Module 2-1

2. Schematic Library Editor
This section covers how to use the Schematic Library Editor and how to create a new component.
The Schematic Library Editor is used to:
• Create and modify schematic component symbols
• Attach models to the component
• Add parameters to the component
• Manage component libraries.
The Schematic Library Editor is very similar in operation to the Schematic Editor and shares the
same graphical object types (but not the electrical objects). In addition, the Schematic Library
Editor has one additional object, the Pin, which is used at points where wires connect to
components.
Figure 2. Schematic Library Editor Workspace
Integrated libraries (*.IntLib) are compiled binary files, which cannot be edited. If you attempt
to open an integrated library, it will be de-compiled, i.e. all the source libraries will be extracted
and a new Library Package will be created. All the libraries supplied with the software are
integrated libraries.
Schematic Libraries (*.SchLib) can be opened for editing using the File » Open menu
command. Navigate to the folder that the required library is stored in and locate the library, e.g.
C:\Program Files\Altium Designer 6\Examples\Training\Temperature
Sensor\Libraries\Temperature Sensor.SchLib and click on Open.

The Schematic Library Editor has a right-click menu; a Utilities toolbar and a Mode toolbar (see
Figure 3 below). The Utilities toolbar includes a range of standard drawing tools and a
comprehensive set of IEEE symbols.
Figure 3. Library Editor Toolbars and right click command options
2.1 Schematic Library Editor Terminology

• Object — any individual item that can be placed in the Schematic Library Editor workspace,
for example, a pin, line, arc, polygon, IEEE symbol etc.
Note: The IEEE range of symbols can be resized during placement. Press the + and - keys
to enlarge and shrink the symbols as you place them.
• Part — a collection of graphical objects that represent one part of a multi-part component
(e.g. one inverter in a 7404), or a library component in the case of a generic or singly
packaged device (e.g. a resistor or an 80486 microprocessor).
• Part Zero – this is a special non-visible part available only in multi-part components. Pins
added to part zero are automatically added to every part of the component when the
component is placed on a schematic. To add a pin to part zero place it on any part, edit it, and
set the Part Number attribute in the Pin Properties dialog to Zero.
• Component — either a single part (e.g. a resistor) or a set of parts that are packaged
together (e.g. a 74HCT32).
• Aliases — refer to the naming system when a library component has multiple names that
share a common component description and graphical image. For example, 74LS04 and
74ACT04 could be aliases of a 7404. Sharing graphical information makes the library more
compact.
• Hidden Pins — these are pins that exist on the component, but do not need to be displayed.
Typically, this is done for power pins, which can then be automatically connected to the net
specified in the Pin Properties dialog. This net does not need to be present on the schematic;
one will be created, connecting all hidden pins with the same Connect To net name. The pins
will NOT automatically connect if they are visible on the schematic sheet (i.e. un-hidden).
Hidden pins can be shown on the schematic sheet by selecting the Show All Pins option in
the Component Properties dialog.
• Mode – a component can have up to 255 different display modes. This can be used for things
like IEEE component representations, alternate pin arrangements for op-amps, and so on.
Use the options in the Tools » Mode submenu or the Mode toolbar to add a new mode to a
component. The displayed component mode can be changed on the schematic sheet.

2.1.1 Schematic Library Editor Panel
The Schematic Library Editor panel provides a
number of features for working with Schematic
components. These are described below. The
buttons below each region of the panel apply to
the selected entry in that region.
Components section
This section lists all the components in the
active library.
• Double-click on a component to open its
Library Component Properties dialog.
• Use the buttons and the options in the right-
click menu to manage the library.
Part section
The Part buttons allow you to step through the
parts of a multi-part component.
Aliases section
This allows you to add alternate names to a
component that share the same graphics and
description.
Pins section
This section lists the pins in the current
component.
• Edit individual pins by double-clicking.
• Select View » Show Hidden Pins to display
all those pins that are defined as hidden.
This does not change the actual pin
hidden/unhidden status; rather it only
displays the hidden pins in the Library
Editor.
• When placing multiple pins with
incrementing name/designator, press the
TAB key after selecting Place » Pin from the
menus to define the starting value. By
default, both the pin number and name will
increment.
• Increment behavior can be controlled using
the Auto-Increment during Placement Figure 4. Schematic Library panel
options in the Preferences dialog (the
primary value is the pin number). Enter a
negative sign to decrement a value. Enter an alpha value to increment alphabetically. A single
alpha followed by numbers increments the leading alpha. If there are multiple alphas, the last
character is incremented/decremented.
• The entire set of pins for the current component can also be viewed and edited in the List
panel, to filter the component to only show pins right-click in the graphical area and select
Filter » Examples » Pins from the floating context menu. If the List panel is not currently
visible press Shift+F12 to display it. Note that you can edit multiple pin properties in the List
panel, and can also copy and paste to and from a spreadsheet.

2.2 Component Properties
The Component Properties dialog is where you add model and parameter information to the
component symbol. Double-click on a component name in the Sch Library panel to display the
dialog.
Figure 5. Component Properties dialog
Information that would typically be defined for a component includes:

• Comment – description of the component. For a component whose definition is fixed, such as
a 74HC32, this standard descriptive string would be entered. For a discrete component
whose value can change, such as a resistor, the value would be entered. Note that this field
supports indirection, which allows you to display the value of any of this component’s
parameters. Indirection is enabled by entering an equals sign, then the parameter name
(spaces are not supported). If this field is left blank, the component library reference will be
entered as the comment when the component is placed, allowing you to define the comment
after it has been placed on the schematic.
Figure 6. Using the List panel to view or edit component pins

• Default Designator – defines the prefix string to be used with the component designator.
• Description – meaningful description that can be used for searching and in the BOM.
• Type – alternate component types are provided for special circumstances. Graphical
components do not get synchronized or included in the BOM. Mechanical types only get
synchronized if they exist on both the schematic and the PCB and do get included in the
BOM. Net Tie components are used for shorting two or more nets on the PCB.
• Parameters – any number of parameters can be added either in the Library Editor, or on the
schematic sheet. Parameters can be linked to a company database; add a database link
document to the project to do this.
• Models – various component models can be added, including footprint, simulation, signal
integrity, and so on.
• Lock Pins – if this option is enabled, you will not be able to edit pins, only the component as
a whole entity, when the component is placed on a schematic. Disable this option if you wish
to edit the pins and click on the Edit Pins button.
Note: Use the What’s This Help for more information about options in the dialog.
2.3 Exercise – Creating a new component symbol

1. We will now create a component – a serial temperature sensor. If it is not open, open the
schematic library \Program Files\Altium Designer 6\Training\Temperature
Sensor\ Libraries\Temperature Sensor.SchLib
2. Before creating the component, we will make this library part of the Temperature Sensor
project. If it is not already open, re-open the project created during the Environment and
Editor Basics training session, \Program Files\Altium Designer
6\Examples\Training\Temperature Sensor\Temperature Sensor.PrjPcb.
3. To add the library to the project, click and hold on the Temperature Sensor.SchLib in the
Projects panel, then drag and drop it onto the project filename, Temperature
Sensor.PrjPcb. It will disappear from the Free Documents, instead appearing under the
Libraries folder icon in the project structure.
4. Right-click on the project name and select Save Project.
5. To create a new component Select Tools » New Component to create a new component.
6. Enter TCN75 in the New Component Name dialog.
7. When the blank sheet appears, zoom in (PAGE UP) until you can see the grid. Components
generally have the top left of the component body located at co-ordinates 0,0 (indicated by
the two darker grid lines).
8. Check that the Snap Grid and Visible Grid are set to 10 (Tools » Document Options).

Figure 7. Microchip TCN75 serial temperature sensor
9. Create the graphical representation for the component as shown in Figure 7. The component
body is a Rectangle, placed at the origin in the center of the sheet. The origin is indicated by
the two darker lines that form a crosshair, zoom in/out to show the crosshair and the gridlines.
Start placing the rectangle at the origin, the body is 80 units wide by 70 units high, you can
use the coordinates shown on the Status bar to guide you.
10. Place the pins for the part. It is important to orient pins so that the 'hot' end is away from the
component body. When placing pins, the cursor will be on the 'hot' end of the pin. Press
SPACEBAR to rotate the pin or X or Y to flip it.
11. Press TAB to edit the pin properties before placing a pin. The Pin Properties dialog will open.
Remember to:
Check that the Pin Number is correct and the Pin Length is set appropriately (e.g. 20).
Set the Electrical Type according to the table below:
Pin Number Pin Name Electrical Type Note: Use the auto-
increment/decrement
1 SDA IO
feature when placing
2 SCL Input pins 5, 6 and 7.
3 INT/CMP Output
4 GND Power
5 A2 Input
6 A1 Input
7 A0 Input
8 VDD Power
12. When you have completed drawing the component, set the
- Designator to U?
- Comment to TCN75
- Description to Serial temperature sensor
At the moment this component is really just a symbol, it has no models or parameters – as a
minimum it needs a footprint. You will create the footprint for this component in the next section
and then come back to the schematic library editor to link it to the symbol.

3. PCB Library Editor
The PCB Library Editor is used to create and modify PCB component footprints and manage PCB
component libraries. The PCB Library Editor also includes a Component Wizard that you can
guide through the creation of most common PCB component types.
3.1 The PCB Library workspace

An existing PCB library (*.PcbLib) can be opened using the File » Open command, displaying the
first footprint in that library, and a list of all footprints in the library in the PCB Library panel. Click
on the required component in the Components list.
Figure 8. PCB Library Editor workspace
The view commands, primitive objects, layers, selection and focus, grids and general editing
functions are all identical to the PCB Editor.
Settings in the Preferences dialog and Board Options dialog also apply in the PCB Library Editor.

3.2 PCB Library Editor panel
The PCB Library panel of the PCB Library Editor
panel provides a number of features for working
with PCB components. These include:
• The Components section of the panel lists
all the components in the active library.
• Right-click in the Components section to
display menu options to Create New
Components, edit Component Properties,
Copy or Paste selected components, or
update the component footprints on open
PCBs.
• Note that the copy/paste commands in the
right-click menu can be used with multiple
footprints selected, and support:
- copying and pasting within a library,
- copying and pasting from a PCB into a
library,
- copying and pasting between PCB
libraries.
• The Components Primitives section lists
the primitives that belong to the currently
selected component. Click on a primitive in
the list to highlight it in the design window.
• The way that the chosen primitive is
highlighted depends on the options at the top
of the panel:
- Enabling Mask will result in only the
primitive(s) you click on remaining at
normal visibility, all others will be faded.
Click the button down the bottom
right of the Workspace to remove the
filter and restore the display.
- Enabling Select will result in the
primitive(s) you click on being selected,
ideal if you need to edit them.
• Right-click in the Component Primitives
section to control which types of primitives
are listed in this section.
Figure 9. PCB Library panel
3.3 Creating a component using the Component Wizard

The PCB Library Editor includes a Component Wizard. This Wizard allows you to select from
various package types, fill in appropriate information and it will then build the component footprint
for you.
To launch the Component Wizard, right-click on the Components section of the PCB Library
Editor panel and select Component Wizard, or select the Tools » New Component.

3.4 Manually creating a component
Components are created in the PCB Library Editor using the same set of primitive objects
available in the PCB Editor. In addition to PCB components, corner markers, phototool targets,
mechanical definitions, etc. can be saved as components.
The typical sequence for manually creating a component footprint is:
• Open the desired library in the PCB Library Editor.
• Select the Tools » New Component menu command. You will be presented with an empty
component footprint workspace, called PCBComponent_1. Rename the component by
double-clicking on the name in the Components list, select Component Properties and enter
a new name in the Component Properties dialog. Component names can be up to 255
characters.
• Use tracks or other primitive objects to place the component outline on the Silkscreen layer.
• Place the pads according to the component requirements. Prior to placing the first pad, press
the TAB key to define all the pad properties. Make sure you set the designator property
correctly. Typically, the first pad you place is pin 1, so the set designator to '1' for the first pad.
The designator automatically increments.
Note: The 0,0 coordinate is the point where the component is ‘held’ during placement.
Always confirm that it is set to a suitable location. Select Edit » Set Reference to change
the location.
3.5 Copying a component

There is often the requirement to copy components, either from one library to another or within the
same library. For a single component you can achieve this using the Edit » Copy Component
command. This command copies the current component, ready for pasting back into a PCB
library.
You can also copy/paste multiple component footprints using the commands in the PCB Library
panel’s right-click menu. Select the requires component footprints using CTRL+click in the list, then
right click and choose Copy, then right-click again and choose Paste X Components (where X is
the number of component footprints you selected).
3.6 Special strings in the Library Editor

There are two special strings that are active in the Library Editor. These are provided to allow you
to control the positioning of the designator (.Designator) and the comment (.Comment).
Place these in the PCB Library Editor workspace at the location relative to the component where
you would like the designator or comment to be placed.
When you use these, you can hide the default designator and comment that are added when the
component is placed in the PCB file.
Libraries and Components Training Module 2 - 10

3.7 Component Rule Check
The Reports » Component Rule Check command allows you to check either the current
component or the whole library for any of the objects selected in the Component Rule Check
dialog.
Figure 10. Component Rule Check dialog
The results of the component rule check are displayed in a text document.
Figure 11. Library Component Rule Check report

3.8 Exercise – Creating the component footprint
In this exercise, we will create a new component footprint called SOIC8, to use with the
Temperature Sensor component you just created, the TCN75.
1. The first thing we need is a footprint library. For this training session we will create the
footprint in a project library. If it is not open, open the footprint library \Program
Files\Altium Designer 6\Training\Temperature Sensor\
Libraries\Temperature Sensor.PcbLib
2. Before creating the footprint, we will make this footprint library part of the Temperature Sensor
project. If it is not already open, re-open the project created during the Environment and
Editor Basics training session, \Program Files\Altium Designer
3. To add the library to the project, click and hold on the Temperature Sensor.PcbLib in the
Projects panel, then drag and drop it onto the project filename, Temperature
Sensor.PrjPcb. It will disappear from the Free Documents, instead appearing under the
Libraries folder icon in the project structure.
4. Right-click on the project name and select Save Project.
5. To create the new SOIC8 footprint we will use the component Wizard, select Tools »
Component Wizard to run the Wizard.
6. In the list of pattern types, select Small Outline Packages (SOP), and set the units to Metric,
as shown below in Figure 12.
Figure 12.Choose the footprint type, and set the units in the Component Wizard
7. Referring to information in Figure 14, create the footprint with a name of SOIC8. Note that it
will be created with one rectangular pad and 7 round-ended pads. We will use the Inspector
to change the round-ended pads to rectangular once it has been created.

Figure 14. Step through the Wizard to create the footprint, as shown.
8. To set all pads to rectangular, first select the seven

round-ended pads (hold SHIFT to multi-select). These
can be edited in a single action in the Inspector
panel.
9. Press F11 to open the Inspector panel, or click the
PCB button at the bottom right of the workspace.
Note that the number of selected objects is indicated
at the bottom of the Inspector.
10. In the Pad Shape (All Layers) field, select
Rectangular, as shown in Figure 13. The selected
pads should change shape immediately.
11. Save the library, and the project.
Figure 13. Setting the pad shape

4. Adding Model and Parameter Detail
to a Component
The final stage of preparing the new component is to add model and parameter information.
4.1 Adding a model

There are a number of ways of adding a models to a component, including:
• Via the Library Component Properties dialog
• Via the models region at the bottom of the main workspace – click the small down arrow at
the bottom right of the workspace if it is not visible.
• Via the Model Manager. The Model Manager allows you to add models to multiple
components at the same time, and is ideal for reviewing model assignments across a library.
Figure 15. Add and manage component models at the bottom of the editing window, or in the Model
Manager

4.2 Exercise – Adding a footprint using the Model Manager
To add a footprint using the Model Manager:
1. If it is not already open, re-open the Temperature Sensor project (\Program
Files\Altium Designer 6\Examples\Training\Temperature
Sensor\Temperature Sensor.PrjPcb).
2. In the Projects panel, browse to and open the schematic library, Temperature
Sensor.SchLib.
3. Select Tools » Model Manager in the Schematic Library Editor to open the Model Manager.
It will show a list of all components in the current library and any models, including Footprint,
Simulation, Signal Integrity, and PCB 3D models.
4. In the Model Manager dialog click on the TCN75 component that you created, making it the
active part.
5. Click Add Footprint to launch the PCB Model dialog, as shown in Figure 16.
Figure 16. Adding the footprint model to the component.
6. If you know the footprint name, and you are confident that is in a currently available footprint
library, you can type the name directly into the Name field, an image of it will appear if it is
located. Otherwise, you can click Browse to open the Browse Libraries dialog, as shown in
Figure 17.
Note: There are different ways you can reference a footprint from the symbol, this is
determined in the PCB Library region of the PCB Model dialog. Any means find the
footprint in Any currently available library, Library Name means it must come from the
specified library, Library Path means it must come from the specified library in the specified
location, and Use from integrated is set automatically if you have compiled the library into
an integrated library.

Figure 17. Use the Browse Libraries dialog to visually select the correct footprint.
Note: The Libraries dropdown at the top of the dialog allows you to choose which library
you are currently browsing, from the available footprint libraries. The Find button is used to
search, this will be demonstrated in the Schematic Capture training module.
7. Once you have located your new SOIC8 footprint select it, and it will appear in the PCB Model
dialog. Click OK to close the dialog.
Note: If your footprint was using a different numbering scheme from the pin numbering on
the symbol you would need to define the pin-to-pad mapping, click the Pin Map button in
the PCB Models dialog to do this.
8. Click Close to close the Model Manager, you have now assigned the SOIC8 footprint to your
TCN75 component.
9. Save the library.

4.3 Component Parameters
Each component that you create can have any number of component parameters, which can be
added/edited in the library or on the schematic. Parameters can be used for any purpose you
require, including:
• component detail information, such as a voltage rating, component revision, and so on
• company component information, such as stock number or price,
• design reference information, such as special pick and place requirements,
• links to reference information, such as websites and PDFs.
Figure 18. Add parameters to fully describe your components.
Any component parameters can be included in the Bill of Materials, or any custom report you
generate via the Report generation dialog.
Figure 19. generate reports that include any component data you require.

4.4 Exercise – adding a component parameter
A useful component parameter is to add is a link from the schematic component to a datasheet. A
PDF datasheet for the serial temperature sensor component has been included, we will now add
a parameter that allows us to open the datasheet for it directly from the schematic.
1. In your Windows File Explorer, confirm that the PDF datasheet is available. Browse to the
location:
Sensor
2. In the Windows File Explorer, copy this address location (you might need to enable the
Address Bar via the View » Toolbars menu first).
3. Return to Altium Designer, then with your TCN75 component symbol open in the library
editor, double click on its name in the SCH Library panel to open the Library Component
Properties dialog.
4. In the Parameters region of the dialog, click the Add button to add a new parameter, this will
open the Parameter Properties dialog.
5. In the Name field, type HelpURL.
6. Click to position the cursor in the Value field of the dialog, then Paste in the contents of the
Windows clipboard, this should be what you copied from the Address Bar of the Windows File
Explorer, namely:
Sensor
7. Type a backslash (‘\’) character at the end of the string, then type in the name of the PDF,
namely: TCN75 - 21490b.pdf, as shown in Figure 20.
Figure 20. Add the HelpURL parameter to link the datasheet to the component.
8. Clear the Visible checkbox in the Parameter Properties dialog since there is no need to show
this string on the schematic.
9. Click OK to close the dialog, then click OK to close the Library Component Properties dialog.
We are now ready to use this new component symbol on a schematic sheet and check the
footprint and parameter.

4.5 Exercise – Using the new component on a schematic
1. Add a new A4 schematic sheet to the project and save it with the name Sensor.SchDoc in
the \Program Files\Altium Designer 6\Examples\Training\Temperature
Sensor\ folder.
2. Open the Temperature Sensor.SchLib, and make it the active document.
3. Select your TCN75 component in the SCH Library panel, then click the Place button below
the list of components in the panel to place it on the last active schematic sheet (the new
one).
4. Double-click on the placed component, and set the designator to U3.
5. While the Component Properties dialog is open, confirm that the SOIC8 footprint is listed in
the Model region of the dialog, as shown in Figure 21. If you click the Edit button below the
list of models the PCB Model dialog will open – if an image of the footprint appears then you
know that the footprint is being found in an available PCB library. This means that it is
available for when the design is transferred from schematic to PCB.
Figure 21. Confirm that the footprint model is available.
6. To confirm that the link to the datasheet is working, position the cursor over the component
and press F1 on the keyboard. If Adobe Acrobat Reader is installed the datasheet will open.
Note: for detailed information on creating components, creating footprints with unusual pad
shapes, attaching different model-kinds, and the different techniques for linking datasheets
to the component, refer to the tutorial TU0103 Creating Library Components.pdf.
7. Save the new schematic sheet with the temperature sensor component on it, you will
complete the rest of this sheet in the Schematic Capture training module.
4.6 Adding and Modifying Component Parameters

Parameters can be added to an individual component, either in the schematic library editor, or the
schematic editor. Adding parameters at the library level ensures consistency in component
information and speeds the process of component placement as parameters do not need to be
added individually.
Altium Designer also provides a powerful Parameter Manager that supports adding parameters
globally to a library, schematic, or series of schematics.
To open the Parameter Manager:
• In either the Schematic or Schematic Library editors, select Tools » Parameter Manager
from the menus to launch the Parameter Editor Options dialog.
• Enable the Include Parameters Owned By check boxes you require, if you are editing
components this would typically only be the Parts option, then click OK.
• The Parameter Table Editor will open. Column headings correspond to the parameter names,
with the contents of each column corresponds to that parameter’s value. Figure 22 shows the
Parameter Table Editor.

Figure 22. Parameter Table Editor
• Right-clicking in the Parameter Table Editor will display options, such as Add Columns, Add
Parameter Values, Copy, Paste, and so on. Data can also be pasted from standard text and
from most spreadsheet applications, such as Microsoft Excel.
• All parameter changes are controlled by an Engineering Change Order (ECO) process that
supports the controlled execution of ECO’s, including the ability to selectively include and
exclude operations as well as generate reports of all changes prior to their being executed.
4.7 Exercise – Editing Parameters in the Parameter Manager

1. From the Temperature Sensor.schlib schematic Library, select Tools » Parameter Manager
and in the initial dialog, be sure only Parts is checked in the Include Parameters Matched By
section at the top, leaving the other options set to their defaults.
2. In the Parameter Table Editor, right-click and choose Add Column.
3. In the Name field, enter Lead Time, checking the Add to all objects option. Leave the Value
field blank, and click OK. A new column will be created with the heading Lead Time, at the
right hand edge of the dialog.
4. Right click the contents of the column Lead Time for the component DMC-50448N and select
Edit. The field will change to a drop-down with a cursor. Enter 14 days in the field.
5. Right click the contents of the column Lead Time for the component PWR2.5 and select edit.
You can now select the previously entered text from the drop down.
6. Right click the previous field Lead Time for component PWR2.5 and select Copy, then right-
click the field Lead Time for the component TCN75 and select Paste.
7. Select the entire contents of the column Lead Time (not including the column heading) using
either Ctrl+Click, Shift+Click, or dragging to select the contents fields. Right-click and then
select Edit and only one of the 3 cells will appear editable. Type the text 3-5 Days and hit
Enter on the keyboard.
8. Click Accept Changes (Create ECO) to open the Engineering Change Order dialog. This is
list of changes that are about to be applied to the library, note that individual changes can be
disabled.
9. Click the Execute Changes button in the ECO dialog to propagate those changes through to
the design. The Report Changes button will generate a list of change orders, use this if you
need to keep a record of changes made to a design file.

5. Creating a multi-part component
To create a multi-part component:
• First create one part, select all, then copy the part to the clipboard using the Edit » Copy
menu command.
• Select Tools » New Part to add a new part sheet under the same component name.
• Paste the part onto the sheet and update the pin information. Note that the Part field in the
panel will now show 2/2, meaning the second of two parts.
• Finally, add hidden pins (typically power pins) to any of the parts. Edit them, enable the Hide
attribute and set their Part Number to zero. If they are to automatically connect to a net, enter
the net name in the Connect To field.
The 4 parts of a multipart 74ACT32 component. Note

the power pins on each part (hidden pins have been
displayed), these exist once, on part zero (a non-visible
part). Hidden pins must have the net that they connect
to specified in the Pin Properties dialog.
Figure 23. Creating a multi-part component.

6. Modifying and Updating Components
6.1 Modifying a component used in your schematic
Although it is generally better to edit components in their source library, components placed on a
schematic can have their pins and color attributes edited, and their pins moved.
• To edit the pins in a component, double-click on the component to display the Component
Properties dialog, and then uncheck the Lock Pins attribute. Pins can now be edited and
their location changed.
• To change the component colors, enable the Local Colors checkbox to display color
controls.
6.2 Updating the components on the schematic

There are two techniques for updating components —either pushing changes from the library onto
the schematic sheets, or pulling changes from the library onto the sheets.
These commands have important differences in how they behavior:
• From the library – after changing a component, select Tools » Update Schematic from the
Schematic Library Editor menus (or right-click on the component name in the SCH Library
panel) to update all instances of this component on every schematic sheet that is currently
open. This method performs a total update; essentially replacing the component, retaining
only the designator.
• From the schematic – this method gives complete control over what aspects and which
instances of the components are updated. To use this method, select Tools » Update From
Libraries from the Schematic Editor menus. On the first page, the Update From Library
Wizard presents all component types in all sheets of the project and options on the update
settings. On the second page, it gives access to every component in the project and update
actions to be carried out. Press F1 when the Wizard is open for detailed information on using
the Wizard.

7. Library Reports
There are several reports available in both the Schematic Library Editor and Schematic Editor that
are used to record component, library and project information, such as a Bill of Materials (BOM).
7.1 Library Editor reports

There are three reports that can be generated in the Library Editor. All have the syntax
Library_Filename.extension.
• The Reports » Component command generates a .CMP file that includes the component
name, part count, components in the same group, details of each part and details of all pins.
This report can be used to verify that the component has been correctly constructed.
• The Reports » Library List command generates a .REP file which includes a component
count as well as the name and description of each component in the library. This report can
be used to create a listing of the components in a library, handy if you need a printed
reference of a library.
• The Reports » Component Rule Check command opens the Library Component Rule
Check dialog (Figure 24). These allow you to test for:
- duplicate component names and pins
- missing description
- missing footprint
- missing default designators
- missing pin name
- missing pin number
- missing pins in sequence.
Figure 24. Library Component Rule Check dialog
Running this generates a .ERR report which reports on all components in the active library.
This report can be used to aid in library verification and library management.

• The Report » Library Report command presents the Library Report Settings, which allows
you to generate either a Microsoft Word® document, or an HTML document. An example
report is shown in Figure 25.
Figure 25. Library report, and the Library Report Settings dialog
Note: You can also generate a library report from the Libraries panel, right-click on a
component in the panel and select Library Report from the context menu.

Schematic Capture
Training Module
Schematic Capture Training Module ii

Schematic Capture Training Module
1. Introduction to Schematic Capture ......................................................................... 3-1
2. The Schematic Editor workspace............................................................................ 3-2
2.1 Document Options.......................................................................................... 3-2
2.2 Preferences .................................................................................................... 3-8
3. Libraries and components ..................................................................................... 3-21
3.1 Locating and loading libraries ...................................................................... 3-21
3.2 Locating components ...................................................................................3-22
3.3 Browsing libraries ......................................................................................... 3-23
3.4 Exercises – Libraries and components ........................................................ 3-24
4. Placing and wiring .................................................................................................. 3-26
4.1 Placing components ..................................................................................... 3-26
4.2 Pin-to-pin wiring............................................................................................ 3-26
4.3 Exercise – Drawing the schematic ............................................................... 3-27
4.4 Exercise – Setting the component’s footprint value ..................................... 3-29
4.5 Exercise – Completing the Sensor schematic.............................................. 3-30
5. Multi-Sheet Design .................................................................................................. 3-31
5.1 Structuring a multi-sheet design................................................................... 3-31
5.2 Multi-sheet design connectivity .................................................................... 3-32
5.3 Constructing the top sheet ........................................................................... 3-33
5.4 Assigning the sheet numbers and total number of sheets ........................... 3-35
5.5 Checking sheet symbol to sub-sheet synchronization ................................. 3-36
6. Assigning designators ........................................................................................... 3-37
6.1 Using Annotate to assign designators.......................................................... 3-37
6.2 Designators on multi-part components ........................................................ 3-38
6.3 Exercise – Annotating the design................................................................. 3-38
7. Compiling and verifying the project...................................................................... 3-39
7.1 Setting up to compile the design .................................................................. 3-39
7.2 Interpreting the messages and locating the errors....................................... 3-41
8. Editing Multiple Text Objects................................................................................. 3-42
8.1 Find and Replace Text .................................................................................3-42
9. Interfacing to other design tools ........................................................................... 3-43
9.1 Setting the relevant project options.............................................................. 3-43
9.2 Transferring a design to the PCB Editor ...................................................... 3-43
9.3 Netlist formats .............................................................................................. 3-44
9.4 Exercise – setting project options for design transfer .................................. 3-44
10. Parameters............................................................................................................... 3-45
10.1 The Parameter Manager .............................................................................. 3-46
10.2 Exercises – Using the Parameter Manager ................................................. 3-48
11. Reports..................................................................................................................... 3-49
11.1 Schematic Editor reports ..............................................................................3-49
12. Printing..................................................................................................................... 3-51
12.1 Setting up and printing ................................................................................. 3-51
Schematic Capture Training Module iii

1. Introduction to Schematic Capture
The Schematic Capture training session covers how to create single sheet schematics and multi-
sheet hierarchical projects from initial setup through to component placement, wiring, design
verification and printing. The functionality of the Schematic Editor will be explored and a series of
exercises will show you how to capture a design as a schematic, ready for PCB design.
Figure 1 outlines the workflow to be followed when creating a schematic in Altium Designer.
Design Concept
& Specification
Create PCB Project
Add sheets & sheet

symbols to build
design hierarchy
Find and place

components from
libraries
Wire design
Annotate design
Compile and verify

design
Add component
parameters
Add PCB design

requirements
Transfer design Back annotate

to PCB layout from PCB
Figure 1. The Altium Designer schematic capture workflow
Schematic Capture Training Module 3-1

2. The Schematic Editor workspace
This section describes how to set up and browse the Schematic Editor workspace, done via the
Document Options and Preferences dialogs. Sheet options, such as grids and templates, as well
as preferences and defaults can be set through these dialogs.
To open the Schematic Editor, simply create a new schematic document (File » New »
Schematic) or open an existing .SchDoc document in Altium Designer.
2.1 Document Options

The Document Options dialog allows you to:
• Set parameters relating to individual schematic files.
• The settings in this dialog are saved with that schematic file.
• The Document Options dialog is displayed by double-clicking on the sheet border, or by
choosing the Design » Options menu command.
The tabs of the Document Options dialog are described in the following sections.
2.1.1 Sheet Options tab

The Sheet Options tab of the Document Options dialog is shown in Figure 2. The options in each
of the sections are explained below.
Figure 2. Sheet Options tab of the Document Options dialog
Template section
Displays the filename of the associated template, if any. Use the Template options in the Design
menu to apply, update or remove the associated template. Set the default template in the System
– New Document Defaults page of the Preferences dialog.

Options section
Orientation
Sets the sheet orientation to Landscape or Portrait.
Title Block
When checked, a standard title block is attached to the sheet. The format of that title block is set
using the drop-down list next to this option. Note that this is typically only used when there is no
associated template.
Show Reference Zones

When checked, the sheet has a reference grid defined in its border.
Show Border
When checked the sheet border is displayed.
Show Template Graphics

When checked, any objects placed in the template file defined for the sheet will be displayed in
the sheet. This is typically used to display a non-standard title block, in which case you would
uncheck the Title Block option.
Border Color
Allows you to set the border color from the Choose Color dialog.
Sheet Color
Allows you to set the background color of the sheet.
Standard Style section

Allows you to select the size of the sheet from a number of standard sizes e.g. A4, A3.
Custom Style section

Allows you to define a custom sheet size and border. Use this option if you want a sheet size not
covered in the Standard Style section.
Change System Font

This button allows you to change the font used to display pin numbers, pin names, port text,
power port text and sheet border text.
Grids section
Grids Options allow you to set the size and turn on or off the Snap Grid and the Visible Grid.
SnapOn
The Snap Grid forces the mouse click location to the closest snap grid point. The Snap Grid is set
and can be turned on or off in the Document Options dialog. You can also cycle though three
predefined grids by pressing the G shortcut key at any time.
Visible
The Visible Grid displays a grid when turned on. This is independent of the Snap Grid. The Visible
Grid can also be turned on or off in the View menu (VV).

Electrical Grid section
The Electrical Grid can be turned on or off and the Electrical Grid Range can be set in the
Document Options dialog. It can also be turned on or off in the View menu (VE).
When the Electrical Grid is turned on and you are executing a command that supports the
electrical grid, the cursor overrides the Snap Grid and jumps to key points on objects.
For example, if you are using the Place » Wire command and move the cursor to a certain
distance within the Electrical Grid Range of a pin, the cursor will jump to the pin.
2.1.2 Parameters tab

The Parameters tab is used as a convenient method of editing sheet-level text. Each parameter
is automatically linked to a text string on the sheet, where the text string is the same as the
parameter name, except that it is preceded by an equals sign.
For example, the Parameter Address1 is automatically linked to the text string =Address1. The
equals sign is an instruction to the schematic editor to automatically replace the text string on the
sheet with the value of a parameter with a name of Address1. Any number of these parameters
can be added to a document, either a schematic template or a schematic sheet. Using these
special strings allows template text properties, such as font, size and color, to be predefined in the
template, while the actual text string value is defined when that template is applied to a
schematic.
This replacement occurs automatically during printing, it can also be performed on screen by
enabling the Convert Special Strings option in the Graphical Editing tab of the Preferences
dialog (Tools » Schematic Preferences).
Figure 3. Parameters tab of the Document Options dialog

The default special strings are listed in the table below, but you can create custom parameters to
suit your document and design requirements.
Special String Description Special String Description
=Address1 Line of an address =Engineer Engineer’s name
=Address2 Line of an address =ImagePath Path to image file
=Address3 Line of an address =Modified Date Computer system date of
last modification to file (value
entered automatically)
=Address4 Line of an address =Organization Organization name
=ApprovedBy Approver’s name =Revision Revision number
=Author Author’s name =Rule Rule description if added
using Add as Rule option
=Checked By Checker’s name =SheetNumber Schematic sheet number
=CompanyName Company name =SheetTotal Total number of sheets in
the project
=CurrentDate Computer system date =Time Time (not automatically
(value entered automatically) updated)
=CurrentTime Computer system time =Title Title of schematic sheet
(value entered automatically)
=Date Date (not automatically =Engineer Engineer’s name
updated)
=DocumentFullPath Filename with full path of the =ImagePath Path to image file
AndName schematic sheet (value
=DocumentName Filename without the path =Modified Date Computer system date of
(value entered automatically) last modification to file (value
=DocumentNumber Document number
=DrawnBy Draftsperson’s name
Figure 4 shows how Special Strings are entered in a title block. Text entered as the value of a
parameter in the Parameter tab will display where the special string is placed. The properties of
the special strings (i.e. font, color) determine the properties of the text that is displayed.
You place special strings by selecting Place » Text String and then pressing the TAB key. The
Annotation dialog displays. Clicking on the down arrow in the name field lists a special string for
each of the parameters defined. Click on the string required and place it. Special strings display
their content when the Convert Special Strings option is selected in the Graphical Editing tab
of the Preferences dialog (Tools » Schematic Preferences), or when the schematic is printed or
plotted.
Figure 4. Special strings in a title block, with and without the Convert Special Strings option enabled

2.1.3 Units tab
The Units tab allows you to define the various units used in the Schematic Editor. Grids will be a
multiples of these units so for example, using the DXP Default Units in which each unit is equal to
10 mils, a Snap Grid value of 5 (or 5 units) would equate to 50 mils, 10 units = 100 mils, etc. when
printed actual size or 1:1.
Figure 5. Units tab of the Document Options dialog
Imperial Unit System Section

Use Imperial Unit System
Check this option to use imperial units in your schematic(s). You will also want to specify which
imperial units to be used (DXP defaults - 10 mil, mils, inches and auto imperial units) in the
Imperial unit used drop down list.
Imperial unit used

This option is used to select from one of the available imperial units; mils, inches, DXP default
units (10 mils) and auto imperial. If the Auto-Imperial unit is selected, the system will switch from
mils to inches when the value is greater than 500 mils.
Metric Unit System Section

Use Metric Unit System
Check this option to use metric units in your schematic(s). You will also want to specify which
metric units to be used (millimeters, centimeters, meters, and Auto-Metric units) in the Metric unit
used drop down list.
Metric unit used

This option is used to select from one of the available metric units; millimeters, centimeters,
meters, and Auto-Metric. If the Auto-Metric unit is selected, the system will switch from millimeters
to centimeters when the value is greater than 100 centimeters.

2.1.4 Using templates
Standard sheet templates (*.SchDot) are supplied with Altium Designer and are accessible in
the \Altium Designer 6\Templates\folder. You can also create your own templates and
store them anywhere.
• Select Design » Template » Set Template File Name. This option removes any existing
template and uses the one you choose.
• Select Design » Template » Update. Use this command when a template is modified and
you need to refresh the sheets which use it.
• Select Design » Template » Remove Current Template. This option removes the template
but retains the old sheet size from the old template.
For each of these commands you will be prompted to indicate if the change is to apply to the
current sheet, all open, or all in project.

2.2 Preferences
The Schematic section of the Preferences dialog allows you to set up parameters relating to the
Schematic Editor workspace. This dialog is displayed using the Tools » Schematic Preferences
menu command. Settings in this dialog are saved in the Altium Designer environment and
therefore remain the same when you change active schematic documents. The options in each of
the pages are described below.
2.2.1 General page
Figure 6. General page of the Schematic preferences
Options section
Drag Orthogonal
When this option is enabled, dragging electrical objects will force wires to remain at 45/90
placement angle modes. Any angle or rubber banding wire placement is used if this option is
disabled. The SPACEBAR can be used at any time while dragging objects to toggle through the
45/90/any angle placement modes. CTRL+SPACEBAR can be used to rotate a component while
dragging.
Optimize Wires and Buses

When this option is enabled, connected independent wire and bus sections are automatically
joined whenever two ends touch.
Component Cuts Wires

When this option is enabled, a wire is automatically broken and the redundant section removed
when a component is dropped on top of an existing wire and two of its pins touch the wire.

Enable In-Place Editing
When enabled, this option allows you to edit placed text directly on the sheet, rather than by
displaying a dialog first. Focus the text string you wish to edit by clicking once. Click again to
enable In-Place Editing and the text will be selected, ready for typing.
CTRL+Double-click Opens Sheet

When this option is enabled, holding the CTRL key down while double-clicking on a sheet symbol
will open the sheet below, rather than opening the Sheet Symbol dialog.
Convert Cross Junctions

When enabled, this option will automatically convert a 4 way cross-
over connection to 2 adjacent 3 way junctions. If this is not enabled
a 4 way cross over junction is automatically converted to 2 non-
connected crossed over wires. If you require a 4-way junction, place
a manual junction at the cross-over point.
Display Cross-Overs Figure 7. Results of having the

convert cross junction option on
When enabled, all wiring cross-overs are displayed as small arcs. (top wiring), and off (bottom wire).
Pin Direction
When enabled, small arrows are displayed at each pin, indicating its IO direction.
Sheet Entry Direction

When enabled, the Sheet Entry’s Style is automatically determined from its I/O Type, combined
with the side of the sheet symbol that it is on.
Port Direction
When enabled, the Port’s Style is automatically determined from its I/O Type, combined with the
direction that the Port is wired from.
Unconnected Left to Right

When enabled, unconnected Ports are displayed according to their I/O Type, using standard
inputs on the left, outputs on the right flow notation.
Include with Clipboard and Prints section

These options control whether the red No ERC and Parameter Set objects are included with
printouts and copied onto the Windows clipboard.
Auto-Increment section
Defines the default increment value to use when placing an object that supports auto-increment.
Supported objects include component designators, component pins and all net identifiers (net
labels, ports, power ports, etc). The Secondary increment value is used for objects that include
two values that can increment/decrement, for example component pins (pin name and pin
number).
The Primary and Secondary fields both support positive and negative numeric and alpha values.
Alpha Numeric Suffix section

Determines how the designator of multi-part components is displayed, for example, Alpha = U1:B
or Numeric = U1:2.
Pin Margin section

These determine the position of the pin name and pin number on components (in hundredths of
an inch). The greater the margin entered, the greater the distance between the pin and its name
and number.
Default Power Object Names section
This allows you to set default net names for the power ports of style Power Ground, Signal
Ground and Earth. Power ports with these styles do not display their net names. This option is
provided to avoid the possibility of the net name defaulting to the name of the previously placed
power port (e.g., which could possibly be VCC).
Document Scope for Filtering and Selection

Defines the default behavior of filtering and selection in schematic documents. Note that this
option is overridden by the settings in the Schematic List panel.
Default Blank Sheet

Defines the sheet size to use when a new schematic is created and there is no Default Template
defined.
Default Template Name section

File Name
Specifies the default template (.SchDot) file to be applied when the File » New » Schematic
command is chosen. Note that Altium Designer now has a system-wide default document feature,
configured in the System – New Documents Defaults page of the Preferences dialog – if the
default schematic (in the PCB Project area) is defined it will override this older default schematic
template setting.
Clear button
Removes any default template file already set.
Browse… button
Allows you to browse available template (.SchDot) files.
Schematic Capture Training Module 3 - 10

2.2.2 Graphical Editing page
Figure 8. Graphical Editing tab of the Preferences dialog
Options section
Clipboard Reference
When this option is enabled, you are prompted to select a reference point when copying and
cutting selected objects to the clipboard.
Add Template to Clipboard

When this option is enabled, the current sheet template including border, title block and any
additional graphics, will be copied to the Windows clipboard when the Copy or Cut command is
used. The sheet template is not added to the Schematic internal clipboard.
Convert Special Strings

When this option is enabled, the special strings that have been placed onto the worksheet, for
example, ".DATE", are converted to show their true representations; in this case, the current
system date would be displayed.
Center of Object
If enabled, when you move or drag an object you will hold it by its reference point (for objects that
have one) or its centre (for objects that do not).
Object’s Electrical Hot Spot

If enabled, electrical objects will be held by their closest hot spot, e.g. the end of a pin.

Auto Zoom
When enabled, the workspace is re-drawn with the object centered in the window (not active
when using Find command or Jump from the Browser). For example, when using the Window »
Tile command, this option re-draws the whole sheet centered in the window.
Single ‘\’ Negation

When enabled, a ‘\’ at the start of a text string causes the whole string to display with an
overscore (to signify active low status). Otherwise, the overscore will only appear above the
character preceded by the overscore.
Double Click Runs Inspector

The Inspector panel appears instead of the Properties dialog when you double-click on an object,
if enabled.
Confirm Selection Memory Clear

If enabled, a confirmation dialog will appear if you try to clear a memory selection.
Mark Manual Parameters

If enabled, parameters displayed with a dot indicate that auto-positioning has been turned off and
parameters will move or rotate with the parent object, e.g. component.
Click Clears Selection

Deselects all selected objects by clicking anywhere on the schematic, if enabled.
Shift Click to Select

Enable this option to nominate which primitives are selected when you hold down the SHIFT key
and click. Set the primitives that will use this option by clicking on the Primitives button.
Always Drag
Enable this to default to dragging (keep the wires attached to the component pins) when you click,
hold and move a component.
Display Strings as Rotated

By default strings are always kept as right-reading as they are rotated. Enable this option to
display them at their rotation angle (including upside down and left-reading). Note that by default
component strings are auto-positioned as you rotate the component, to disable this behavior for a
string double click on it.
Place Sheet Entries automatically

Enable this option and sheet entries will automatically be placed when drawing a wire between a
port and a sheet symbol. These sheet entries will take on the name of the port.

Auto Pan Option’s section
Style
This field has the following options.
Auto Pan setting Auto Pan Behavior
Auto Pan Off No auto panning

Auto Pan Fixed Jump Continuous pan while the cursor touches the window edge
Auto Pan Re-center Cursor position becomes centre of screen when it touches the
window edge
Speed
Allows you to set the Auto Pan speed.
Step and Shift Step Size

Amount the sheet steps as you pan using the arrow keys, and as you hold shift and pan.
Undo/Redo section
Stack Size
This field shows the number of actions held in the Undo Buffer. The default value is 50. Enter a
value in this field to set the Undo Buffer size. There is no limit to the size of the Undo Buffer,
however, the larger the size, the more main memory is used to store undo information.
Group Undo
Check this box to undo multiple operations in which action(s) may be nested as a part of other
commands (nested Sub-Commands). For example while placing objects, Altium Designer allows
you to perform other operations, invoked using keyboard shortcuts during the placement process.
Group undo will undo all of the operations, include any nested subcommands, as a part of a
single Undo operation. Repeated commands, such as placing a wire, then another wire, and so
on, are all undone if Group Undo is enabled – disable it to remove only the last wire with each
Undo.
Color Options section

Selections
The default color for selected objects can be changed by clicking in the color box and choosing
another color from the Choose Color dialog. The Schematic Editor will display all the available
colors that your computer’s graphics adapter supports.
Cursor section
Cursor Type
Three options are available for the shape of the physical (or sheet) cursor — a large 90-degree
cross that extends to the edges of the window, a small 90-degree cross or a small 45-degree
cross. The sheet cursor is displayed when executing commands.

2.2.3 Mouse Wheel Configuration
Figure 9. Mouse Wheel Configuration page of the Schematic preferences
Use this page to configure the Mouse Key+Wheel combinations that can be used to operate
zooming, scrolling and switching channels on a multi-channel design.

2.2.4 Compiler page
Figure 10. Compiler page of the Schematic preferences
Errors & Warnings

Compiler errors and warnings can be displayed on the schematic, using a wiggly underline to
indicate the presence of an error or warning. Use the options in this tab to configure the behavior.
Hints Display
Information about errors and warnings can be displayed in floating hint boxes, when the cursor is
held over the object in error/warning.
Auto Junctions
Junctions are automatically added at all valid connection points, their display is controlled by
these options.
Manual Junctions Connection Status

These options control the display of manually placed junctions. Enable the Display check box to
add a circle around a manual junction, define its size and color with the Size and Color options.
Physical Names Expansion

These options control the display of physical names created for objects when generating a multi-
channel design. Physical names will include unique identifiers that differentiate the various objects
from one another on the repeated sheet.

2.2.5 AutoFocus page
Figure 11. Autofocus page of the Schematic preferences
The autofocus tab is used to configure a number of options that control the state of the schematic
display.
It can, for example, be configured to automatically zoom when editing text on the schematic sheet
(enable the Zoom Connected Objects – On Edit in Place & Only Text options), or to dim all
wiring not related to the wire currently being placed (enable the Dim Unconnected Objects – On
Place option).
2.2.6 Library AutoZoom
Figure 12. Use the autozoom options to control how a component is auto-zoomed when you switch
components

2.2.7 Grids page
Figure 13. Grids page of the Schematic preferences
Grid Options section

Visible Grid
The visible grid can be displayed as lines or dots.
Grid Color
The visible grid can be assigned a default color. To assign a new color to the visible grid, click in
the color box to open the Choose Color dialog. The Schematic Editor will display all the available
colors that your computer’s graphics adapter supports.
Grid Presets sections

The current working grids can be changed at any time by pressing the G key to cycle through the
grid settings shown in the Imperial or Metric Grid Presets.
The actual grid used in a document is defined as a property of the schematic sheet, select
Design » Document Options to select this. The default grid is DXP Defaults, where each grid
unit is 1 hundredth of an inch.
Presets buttons
These buttons present a number of pre-defined grid-cycle options.
Grid settings table

Current set of grids that will be cycled through as you press the G shortcut key. Click to edit an
individual setting, or right-click to remove or add a row to the table.

2.2.8 Break Wire page
Figure 14. Break Wire page of the Schematic preferences
The schematic editor includes a Break Wire command (Edit menu), which is used to cut an
existing wire or bus (it is also available in the wire right-click menu). These settings control the
break wire behavior.
2.2.9 Default Units page

Use this page to define the setting for Units when a new document is created. The behavior of the
various options is discussed in section 2.1.3. Note that once a schematic exists, the Units must be
set for that document (Design » Document Options).
Figure 15. Default Units page of the Schematic preferences

2.2.10 Default Primitives page
Figure 16. Default Primitives page of the Schematic preferences
This tab allows you to set the default state of the properties of each object. Objects take on the
property settings defined here when they are placed (these settings do not affect objects that
have already been placed). Remember that you can also change these property settings by
pressing the TAB key before placing the object.
If you enable the Permanent option, default values will not be updated when you press the TAB
key to change the properties of a placed object.

2.2.11 Orcad Options page
Figure 17. Orcad options page of the Schematic preferences
Copy Footprint From/To

Determines which Orcad Part Field is used to load the Footprint field in Schematic editor
components.
Orcad Ports
When the Mimic Orcad ports option is enabled, existing ports in a schematic design/project have
their width recalculated based on the number of characters in their name and the size of the port
is restricted from being manually edited.

3. Libraries and components
This section explores the Altium Designer libraries and how to find schematic components within
them.
3.1 Locating and loading libraries

The supplied components are stored within a set of Integrated Libraries. An integrated library
includes the schematic symbols, plus it can also include all associated models, such as footprints,
spice models, signal integrity models, and so on. Most of the supplied integrated libraries are
manufacturer-specific.
Integrated libraries are compiled from separate source schematic libraries, PCB footprint libraries,
etc. The components in an integrated library cannot be edited, to change a component the source
library is edited and recompiled to produce an updated integrated library.
There are a number of other special purpose integrated libraries, e.g. special function simulation
components.
Components can also be placed directly from schematic symbol libraries if this is preferred to
integrated libraries, and you can also place them from Protel 99 SE format schematic symbol
libraries.
Available components are listed in the Libraries panel. The libraries presented in this panel
include:
• Libraries in the active project. If the project that the currently active document belongs to
includes any libraries, they are automatically listed.
• Installed libraries. Installed libraries are those that have been made available in the
environment. Use this option for company libraries that are used across different projects.
• Libraries found down the defined project search path. This option is particularly useful for
accessing simulation models. Search paths are defined in the Project Options dialog.
3.1.1 Adding a library to make its components available

1. To add a library, press the
Libraries button in the
Libraries panel or select
Design » Add/Remove
Library. The Available
Libraries dialog displays.
2. Click on the Install button at
the bottom of the Installed Tab
of the dialog.
3. Navigate to the required
libraries directory and click on
a library to select it. The library
you selected will now be listed
in the Installed Libraries list in
the dialog.
Figure 18. Available Libraries dialog, use the Installed tab to install or
4. Click Close when you have remove libraries from the environment.
installed the libraries you need.
Note: The supplied integrated libraries are located in the:

\Program Files\Altium Designer 6\Library\ folder.

3.2 Locating components
When you do not know which library a component is located in, use the Search button in the
Libraries panel or the Tools » Find Component menu command. The Libraries Search dialog
displays.
Figure 19. Search Libraries dialog
Tips for finding components:

• The search dialog uses a standard query to search the libraries – if the string you type does
not include a query keyword it is assumed that the text is either part of the component Name
or Description and a query is built automatically, as shown in Figure 19.
• The default search Scope is Available libraries that are those libraries currently listed in the
Libraries panel. Change this to Libraries on path to search across all the supplied libraries.
• Search results are presented in the Libraries panel – note that the drop down where you
select the current library will change to Query Results.
• If you attempt to place a component in the query results from a library that is not currently
installed you will be asked if you wish to install that library now, you can still place without
installing the library if you wish.
• The search can be terminated as soon as an instance of the part is found by clicking the
button on the Libraries panel.
• If your search does not produce results, check that the search path is correct. Also, try
searching for a component you know exists in a library to check that everything is set
correctly.

3.3 Browsing libraries
The Libraries panel gives access to all
components that are currently available to be
placed.
• Select View » Workspace Panels »
Libraries from the menus, or click the
Libraries button at the bottom of the
workspace to display the Libraries panel.
• Click the Libraries button to display the
Available Libraries dialog. This dialog
displays all components currently available
to be placed in the active project. Select
the Installed tab, and click the Install
button to add libraries to the library list.
• Components contained in the selected
library are listed in the box below the Filter
field. The Filter allows you to control what
component names are listed, e.g. RES* will
display only component names starting
with RES.
• You can also type directly in the list of
components, the type-ahead feature will
automatically jump through the list as you
type. Press ESC to stop performing a type-
ahead action.
• Clicking on the name of a component will:
display that component symbol in the
viewer in the middle of the panel, list the
associated models below that, and show
the selected footprint model below that.
• The Place button places the component
currently selected. Double-clicking on the
name of a component also achieves this.
• The Search button is a powerful searching
tool, allowing you to search through
libraries for parts. Clicking this button pops
up the Libraries Search dialog.
• If a component has several parts, the sub-
parts will be shown in the symbol mini-
viewer.
• You can control what columns are
displayed in the component or model lists,
Figure 20. Browsing libraries with the Schematic
right-click and choose Select Columns to Editor Panel
do this.

3.4 Exercises – Libraries and components
3.4.1 Locating and loading libraries when the required library is known
The training design is a microcontroller driven temperature sensor. To install one of the supplied
libraries and see if it includes a PIC microcontroller library, complete the following steps:
1. Open a schematic document to activate the Schematic Editor.
2. Click the Libraries button on the Libraries panel to display the Available Libraries dialog.
3. Select the Installed tab of dialog, then click the Install button and navigate to the \Program
Files\Altium Designer 6\Library\directory. This directory contains sub directories
containing the integrated libraries supplied with Altium Designer’s Schematic Editor.
4. Scroll down through the library directories. Open the Microchip folder, select and add the
Microchip Microcontroller 8-Bit PIC16 2.IntLib.
5. Click the Close button to close the Available Libraries dialog.
6. Select this Microchip library in the list of libraries at the top of the Libraries panel. The library’s
contents will be displayed in the box below the Filter field section. Confirm that the library
includes a PIC16C72-04/SO.
3.4.2 Finding components when their library is unknown

Often you will want to locate a component but do not know which library it is in, or you may want
to see what family types are available in the libraries. To search for components, we use the
Search button or the Tools » Find Component menu command.
1. Click on the Search button and the Libraries Search dialog will appear.
2. Set the Scope to Libraries on path and set the search Path to C:\Program
Files\Altium Designer 6\Library (the Include subdirectories option should be
on).
3. The power supply in the training design uses a LM317MSTT3 adjustable regulator. To search
the supplied libraries for a suitable device type the string LM317 in the Search field at the top
of the dialog and click the Search button.
4. Note that the library currently being searched is listed in the Libraries panel. Depending on
the speed of the PC it will take a few minutes to search the entire 80,000+ components for the
required part.
5. The result set should include components in the ON Semi Power Mgt Voltage
Regulator.IntLib, confirm that the LM317MSTT3 part is listed.
6. To install this library so that component will be available later you can either right-click in the
result list and select Add or Remove Libraries (this will simply open the Available Libraries
dialog), or you can double-click on the component name in the list to place it (you can easily
delete it if it is the wrong sheet), when you do the Confirm dialog will appear, giving you an
opportunity to Install the library.
3.4.3 Locating components within an open library

1. Select the library Miscellaneous Devices.IntLib in the Libraries panel.
This library is one of two PCB libraries installed by default when the software is installed. It
includes a variety of discrete components, including resistors, capacitors, diodes, etc.
2. Type cap into the Filter field. Notice that only the capacitor-type components are listed.
3. Try diode in the Filter field. The only components listed now are the diodes whose library
reference starts with the string diode.

4. Now try *diode, this time components that include the word diode anywhere in their name or
description will be listed.
3.4.4 Finding footprints when their library is unknown

1. Footprints can be searched for in the same way as component symbols; the only difference is
that you need to set the Search type in the Libraries Search dialog to Protel Footprints
before pressing the Search button.
2. Set the Search Path to C:\Program Files\Altium Designer 6\Library\Pcb.
3. Enter the string 0805 and click Search. The search results will include a number of libraries,
including Chip Resistor – 2 Contacts.PcbLib.
4. Double-click on the CR2012-0805 footprint in the query results, a dialog will appear letting
you know that the library is not currently installed, click Yes to install the Chip Resistor –
2 Contacts.PcbLib library.
Figure 21. Searching for a footprint
3.4.5 Setting the library search order

When you type in a component name, for example in the Place Part dialog, or when you type in a
footprint name in the Footprint Model dialog, the available libraries are searched in a defined
order. This search order is the order that the libraries are listed in the Available Libraries dialog.
To configure the search order:
1. Click the Libraries button in the Libraries panel to display the Available Libraries dialog.
2. Click on the Installed tab, then in the list of Installed Libraries click to select the Chip
Resistor – 2 Contacts.PcbLib to highlight it, and then click the Move Up button to
move it to the top of the list.
3. Close the Available Libraries dialog.
You now have all the components and footprint required to complete the training design.
Note: Refer to the Component, Model and Library Concepts article in the online documentation
for further information on definitions, library search order and component to model linking.

4. Placing and wiring
This section looks at how to place components and then wire them together. The exercise takes
you through the creation of a complete schematic sheet.
4.1 Placing components

• To place a component, double-click on its name in the Libraries panel.
• To edit a component’s properties before you place it, press the TAB key. The Component
Properties dialog displays. To step through the fields in the dialog press TAB (down), or
SHIFT+TAB (up).
• New text will overwrite text that is selected.

• If you set the component designator before placing the component, then subsequent
components will be automatically designated with the next designator value.
• You can also use the Place » Part menu command if you know the name of a component.
When you select this command, you are prompted for the name of the component. Once you
type the component name in, the open libraries are searched and if the component is located,
it becomes attached to the cursor for placement.
4.1.1 Auto-incrementing designators

When placing a component, if the initial designator is set before placing, its designator will be
assigned by incrementing the designator of the last component placed. This will only occur for
subsequent parts placed after the TAB key was pressed to assign the initial designator. Once you
stop placing this type of part, the next designator in the sequence is no longer remembered.
Generally it is easier to leave the annotation of designators until the design is complete to allow
the designators to be assigned in a logical and controlled manner on each sheet. Annotation is
covered in detail later in the day in the Assigning designators topic.
4.2 Pin-to-pin wiring

• Wires are used to create an electrical connection between points.
• Be careful to use Place » Wire and not place lines by mistake.
• Press SHIFT+SPACEBAR to change the wire placement mode. Press SPACEBAR to toggle
between start and end corner modes.
• Press BACKSPACE to delete the last vertex placed.
• A point on a wire must touch on the connection point of an electrical object to be connected to
it, e.g. the wire must touch on the hot end of a pin to connect to it.
• Use buses to graphically represent how a group of related signals, such as a data bus, are
connected on a sheet. Also, use buses to connect related signals to ports and sheet entries.
• Buses must use the bus name / bus element referencing system as shown in Figure 23, and
must include the individual net labels and the bus net label.
• The bus range can increment [0..7], or decrement [7..0].
• To move a component on the schematic and maintain the wiring (referred to as dragging),
hold the CTRL key as you click, hold and move the mouse (release the CTRL key once you start
dragging). Press the SPACEBAR or SHIFT+SPACEBAR while dragging to change the wiring mode.
Press the M shortcut to drag a selection.

4.3 Exercise – Drawing the schematic
Figure 22. MCU schematic example
1. If it is not already open, re-open the project created during the Environment and Editor Basics
training session, \Program Files\Altium Designer
2. Add a new schematic document to the project, to do this right-click on the project file name in
the Projects panel and select Add New to Project » Schematic.
3. Right-click on the new schematic sheet in the Projects panel, and select Save As from the
context menu. Save the schematic as MCU.SchDoc in the \Program Files\Altium
Designer 6\Examples\Training\Temperature Sensor folder.
4. Set the template for your schematic to A4.SchDot by choosing Design » Template » Set
Template File Name and choosing the A4 size template from \Program Files\Altium
Designer 6\Templates folder.
5. Verify that the electrical grid is on and set to 4 and that the snap grip is on and set to 10
before placing any objects (double-click in the sheet border to open the Document Options
dialog).
6. Draw up the schematic shown in Figure 22 above. When placing the components, press TAB
to define the Designator and Comment (component value) before placing the component.
Component Library Reference
Microcontroller PIC16C72-04/SO
Resistors Res1
Capacitor Cap
7. To rotate a component press the SPACEBAR, press the Y key to flip it vertically, and the X key
to flip it horizontally.
8. Set the Port I/O Type to match their display Style. Set the Ground Style power port net
attribute to GND.

9. Set the bus name and port name to RB[0..7] so as to connect nets RB0 through to RB7
into a bus.
10. To build up the nets in the bus, first place the wire and bus entry for net RB0. Select them,
then use the Edit » Rubber Stamp command to create seven more. Now select the Place »
Net Label command, press TAB while the net label is floating on the cursor to edit the value,
then place net label RB0. By defining the value before placing the net label, you have invoked
the auto-increment feature and you are now ready to place net labels RB1 through to RB7.
Figure 23. Buses are defined using the referencing system shown.
11. Enter the necessary document information in the Parameters tab of the Document Options
dialog. Enter the title as PIC Microcontroller and the Sheet No. as 2 of 5.

4.4 Exercise – Setting the component’s footprint value
The footprints currently assigned to the resistor and capacitor components are not surface mount
and are not suitable for the PCB design. To change these, we will use the object Inspector.
1. Press the F11 key to display the Object Inspector. The Inspector is also available via the
View » Workspace Panels sub-menu, or by clicking the SCH button at the bottom-right of
the workspace and launching the SCH Inspector button.
2. The object Inspector is a panel which provides a view of the attributes of the currently
selected object. It is a ‘live’ panel, i.e. as you click to select from one object to the next, its
attributes are automatically loaded into the Inspector. Click once on the capacitor to display its
attributes in the Inspector.
3. To edit the capacitor footprint, type in
the new footprint string, CR2012-
0805. Press ENTER on the keyboard to
commit the change.
4. The resistors can use the same
footprint. Rather than editing them one
at a time, first select all six resistors
(use SHIFT+click to build up the
selection). Note that at the bottom of
the Inspector it indicates the number of
selected objects that you are about to
change. Change the footprint string to
CR2012-0805.
Note: As well as being able to change

multiple objects, the Inspector can be
used to change different kinds of
objects at the same time.
Figure 23. The Object Inspector, displaying the capacitor

attributes.

4.5 Exercise – Completing the Sensor schematic
At this stage in the training, your Temperature Sensor project should look like Figure 24.
Figure 24. Project structure after completing the MCU schematic.
However, the Sensor.SchDoc is incomplete, so far it only has the temperature component on it.
To complete it:
1. Add the Ports, Power Ports and Wiring to finish the schematic, as show in Figure 25.
2. Save and close the Sensor.SchDoc sheet.
Figure 25. Wired sensor schematic (Sensor.SchDoc).
The last step to complete the sensor design is to add the top schematic sheet.

5. Multi-Sheet Design
5.1 Structuring a multi-sheet design
All but the smallest designs will need to be laid out over multiple schematic sheets. There are
essentially two approaches to structuring a multi-sheet design, either flat, or hierarchical. A flat
design is one where the connectivity between nets that span sheets is directly from one sheet to
the other, or potential to many others.
While a flat design is acceptable for a design with a small number of sheets and nets, perhaps 6
sheets, it becomes unwieldy when the design is larger. Since a net can go to any of the other
sheets, a larger flat design needs navigation instructions to guide the reader as they attempt to
find that net on the other sheets. The advantage of the flat design is that there are normally fewer
sheets, and less wiring to draw.
A hierarchical design is one where the structure – or sheet-to-sheet relationships – in the design
is represented. This is done by symbols, known as sheet symbols, that represent lower sheets in
the design hierarchy. The symbol represents the sheet below, and the sheet entries in it represent
(or connect to) the ports on the sheet below. The advantage of the hierarchical design is that it
shows the reader the structure of design, and that the connectivity is completely predicable and
easily traced, since it is always from the child sheet up to the sheet symbol on the parent sheet.
The diagram below shows the top sheet for the Temperature Sensor project. Each sheet symbol
represents a child schematic in the design.
Figure 26. Temperature Sensor top sheet

5.2 Multi-sheet design connectivity
Multi-sheet designs are also defined at the electrical (or connective) level by net identifiers which
provide the ‘glue’ between nets in schematic sheets.
5.2.1 Net identifiers

Net identifiers create logical connections between points in the same net. This can be within a
sheet, or across multiple sheets. Physical connections exist when one object is attached directly
to another electrical object by a wire. Logical connections are created when 2 net identifiers of
the same type (eg, two net labels) have the same Net property. Note that logical connections are
not created between different net identifiers, for example a port and a net label. The only
exception to this is when a port connects to a sheet entry of the same name, in the sheet symbol
that represents the sheet the port is on (more on this later).
Net identifiers include:
• Net Label – Use a net label to uniquely identify a net. This net will connect to other nets of the
same name on the same sheet, and can also connect to nets of the same name on different
sheets, depending on the connectivity mode defined for the design (referred to as the net
identifier scope). Net labels are attached to individual wires, part pins and buses.
• Port – Depending on the method of connectivity, a port can connect horizontally to other ports
with the same name, or vertically to a sheet entry with the same name.
• Sheet Entry – When the connectivity is vertical, power sheet
port entries net label
you can use a sheet entry to connect to a port of
VCC
the same name on the sheet below. A sheet entry RESET
RESET
is added to a sheet using the Place » Add Sheet
Entry command. ENABLE ENABLE
port
• Power Port – All power ports with the same
name are connected throughout the entire Figure 27. Net identifiers
design.
• Hidden Pin – Hidden pins behave like power ports, connecting globally to nets of the same
name throughout the entire design.
5.2.2 Net identifier scope

When you create a connective model of a design, you must define how you want these net
identifiers to connect to each other – this is known as setting the Net Identifier Scope. The scope
of net identifiers is specified in the Options tab of the Project Options dialog. The scope of net
identifiers should be determined at the beginning of the design process.
There are essentially two ways of connecting sheets in a multi-sheet design: either horizontally,
directly from one sheet, to another sheet, to another sheet, and so on; or vertically, from a sub-
sheet to the sheet symbol that represents it on the parent sheet. In horizontal connectivity, the
connections are from port to port (net label to net label is also available). In vertical connectivity,
the connections are from sheet entry to port.
The Net Identifier Scope specifies how you want the net identifiers to connect:
• flat – ports connect globally across all sheets throughout the design. With this option, net
labels are local to each sheet; they will not connect across sheets. All ports with the same
name will be connected, on all sheets. This option can be used for flat multi-sheet designs. It
is not recommended for large designs as it can be difficult to trace a net through the sheets.
• global – ports and net labels connect across all sheets throughout the design. With this
option, all nets with the same net label will be connected together, on all sheets. Also, all
ports with the same name will be connected, on all sheets. If a net connected to a port also
has a net label, its net name will be the name of the net label. This option can also be used

for flat multi-sheet designs, however it is difficult to trace from one sheet to another, since
visually locating net names on the schematic is not always easy.
• hierarchical (sheet entry/port connections) – connect vertically between a port and the
matching sheet entry. This option makes inter-sheet connections only through sheet symbol
entries and matching sub-sheet ports. It uses ports on sheets to take nets or buses up to
sheet entries in corresponding sheet symbols on the top sheet. Ports without a matching
sheet entry will not be connected, even if a port with the same name exits on another sheet.
Net labels are local to each sheet; they will not connect across sheets. This option can be
used to create designs of any depth or hierarchy and allows a net to be traced throughout a
design on the printed schematic.
• The automatic mode automatically selects which of the three net identifier modes to use,
based on the following criteria: if there are sheet entries on the top sheet, then Hierarchical is
used; if there are no sheet entries, but there are ports present, then Flat is used; if there are
no sheet entries and no ports, then Global is used.
Note: Two special net identifier objects are always deemed to be global: power ports and
hidden pins.
Summary
• If you are using sheet symbols with sheet entries, the net identifier scope should be set to
Sheet Entries/Port Connections. If this mode is chosen, the top sheet must be wired.
• If you are not, connectivity can be established via Ports and/or Net labels, so you will use one
of the other two net identifier scopes.
• Net labels do not connect to ports of the same name.
5.3 Constructing the top sheet

The process of creating a top sheet can be done in a manual fashion, where the sheet symbols
are placed, the filename attribute for each is set to point to the correct sub-sheet and the sheet
entries are added to correspond to each port on the sub-sheet.
There are also commands to speed the process of creating a multi-sheet design.
The Create Sheet from Symbol command is for top-down design. Once the top sheet is fully
defined, this command creates the sub-sheet for the chosen sheet symbol and places matching
ports on it.
The Create Symbol from Sheet command is for bottom-up design, creating a sheet symbol with
sheet entries based on the chosen sub-sheet. This is the mode we will use now.
5.3.1 Exercise – creating the top sheet for the Temperature Sensor project
Refer to Figure 26 to complete this exercise.
1. To create the top sheet, add a new schematic document to the Temperature Sensor project,
set the template to A4 and save it as Program Files\Altium Designer
6\Training\Temperature Sensor\Temperature Sensor.SchDoc.
2. Rather than manually placing sheet symbols and editing them to reference the lower sheets,
we will use the Design » Create Sheet Symbol from Sheet or HDL command. Select this
command from the menus.
3. In the Choose Document to Place dialog, select Sensor.SchDoc.
4. You will be asked if you want to Reverse Input/Output Directions, if you say No the IO Type
of the Sheet Entries will match the Ports on the sheet below, if you say Yes they will be
reversed. Choose the No option.
5. The sheet symbol will appear floating on the cursor. Place the sheet symbol in an appropriate
position on the sheet, as shown in Error! Reference source not found..

6. Note that two of the sheet entries are on the left of the sheet symbol. This is because they are
positioned on the symbol based on their I/O type, with Input and Bidirectional on the left and
Output sheet entries on the right. Drag the two sheet entries on the left over to the right side.
7. Another important point about sheet entries, their I/O type is an independent attribute from
their style (the direction they point), unless you have the auto Sheet Entry Direction option
enabled in the Schematic tab of the Preferences dialog. The SCL sheet entry was pointing
inward when it was on the left, now that it is on the right it will be pointing out if the Sheet
Entry Direction option is currently disabled. Open the Preferences dialog and confirm that
the option is enabled.
8. Repeat this process of creating symbols for the MCU, LCD and Power sub-sheets.
9. Place the connector J1. It is a Header 3X2A, which can be found in the Miscellaneous
Connectors.IntLib (one of the two integrated libraries installed by default).
10. Wire the top sheet as shown in Error! Reference source not found..
11. Save the top sheet.
This completes the capture phase of the design process. To confirm that the project hierarchy
is correct we will now compile the design. This is covered in detail in section 7, for now we will
simply compile to show the correct structure of the design in the Projects panel.
12. To compile the project, select Projects » Compile PCB Project Temperature
Sensor.PrjPcb.
Figure 28. The project hierarchy is displayed once the project has been compiled.
13. Save the Project (right-click on the project in the Projects panel)
The design is now complete. However, before it can be transferred to PCB layout there are a
few other tasks to complete, these include:
- Assigning the sheet numbers for each sheet in the hierarchy
- Assigning the designators
- Checking the design for errors

5.4 Assigning the sheet numbers and total number of sheets
Sheet numbering is performed using documents parameters, linked to special strings placed on
the schematics, as described earlier in The Schematic Editor workspace section. Sheets can be
automatically numbered by selecting the Tools » Number Sheets command.
• The Number Sheets dialog can be used to
- number the sheets (SheetNumber parameter),
- set the document number (DocumentNumber parameter),
- and set the total number of sheets (SheetTotal parameter).
• Click in the column to be edited to access the commands to edit that column.
• The sheets and documents can be numbered in a variety of ways, to do this click in the
SheetNumber column, then click the Auto Sheet Number button.
• Cells can be edited manually, select the target cell(s), then right-click and select edit (or press
the SPACEBAR). Alternatively, use the Move Up and Move down buttons, the number the
sheets based on the Display Order.
Figure 29. Use the Sheet Numbering feature to review and update sheet numbers.
Note: Schematics appear in the Projects panel in the order they were added to the project. You
can change this order if you want, simply click, drag and drop to re-order them.

5.5 Checking sheet symbol to sub-sheet synchronization
Typically the design hierarchy is not developed in a purely top-down or bottom-up fashion, the
reality is that the design will evolve. This means that there will be modifications to the design that
affect the net connectivity established between the sheet entries in the sheet symbol and the
ports on the sub sheet below.
To manage the sheet entry to port relationships, use the Synchronize Ports to Sheet Entries
dialog. Select Design » Synchronize Sheet Entries and Ports to display the dialog.
Figure 30. Use the Synchronize dialog to ensure that sheet entries match with ports. Uncheck the checkbox
down the bottom left to show all sub-sheets in the entire design.
The Synchronize dialog can be used to:

• Match any selected Entry to any selected Port (name and IO type will be changed).
• Add or remove Entries or Ports to either the sheet symbol or the sub sheet.
• Edit the name or IO direction of a matched Entry / Port (done in the Links column on the
right).
Note that changes made in the Synchronize Ports to Sheet Entries dialog are performed
immediately, use the Undo command on each affected sheet to undo any updates.

6. Assigning designators
The Schematic Editor includes a positional-based re-annotation tool for allocating component
designators.
6.1 Using Annotate to assign designators

The Schematic Editor provides an automated method of assigning designators. This is the
Annotate command. This will take any component which has ‘?’ appended to its designator and
allocates a unique designator to those parts.
The order in which designators are assigned is based on the components’ position on the sheet.
The Annotate dialog allows you to set one of four positional annotation options. The annotation
grid is based on the sheet border reference, so change the number of regions in the border
reference to control the annotation grid.
To run Annotate, choose the Tools » Annotate menu command. This displays the Annotate
dialog shown in Figure 31.
Figure 31. Annotate dialog
The Annotate options include:

• Update Change List — this button will reassign all designators that are not currently
assigned (their designator currently ends in a ?).
• Reset All — use the Reset All button to reset all designators so that they end in a ?. You can
also limit this to resetting only duplicates.
• Order of Processing – there are four directional options available. Select the preferred one
at the top left of the dialog. This uses the sheet grid to define the across/down increments.
• Matching Options – enable the parameters to be used to package parts of a multi-part
component. Typically, this is based on the component comment. If there are particular parts

that must be packaged together, give both a common parameter and enable this parameter in
the Component Parameter list (e.g. filter-stage1). Note that the Annotation Summary down
the bottom right of the dialog gives information about the matching behavior.
• Schematic Sheets to Annotate – this section of the dialog gives sheet-by-sheet control of
the annotation, sheets can be excluded from the process and you can also control the
annotation starting number for each sheet.
• Back annotate – click this to load a Was/Is file. This is only required if the board is not being
designed in Altium Designer. If you are designing the board in Altium Designer you can back
annotate directly from the PCB to the schematic by selecting the Design » Update menu
option.
• Whenever an Update or Reset is performed an Information dialog will appear. This dialog
details how many changes have been made from the previous state (since the last Update or
Reset) and the information dialog also lists the changes from the original state (since the
Annotate dialog was opened).
• Once you are happy with the designator assignments, click the Accept Changes button to
generate an ECO. From the ECO dialog you can update the schematic.
Note: To prevent a component from having its designator changed by the Annotation process,
enable the Locked checkbox adjacent to the Designator in that component’s Component
Properties dialog.
6.2 Designators on multi-part components

The suffix for multi-part components can be either Alpha or Numeric, depending on the Alpha
Numeric Suffix option in the Preferences dialog. This is an environment setting and will apply to
all open schematic sheets.
You can change parts within a component using the Edit » Increment Part Number command.
Select this command and then click on the part of interest.
Note: To prevent multi-part component parts being swapped during the annotation process
enable the Locked checkbox adjacent to the Part selector in the Component Properties dialog.
6.3 Exercise – Annotating the design

1. Select Tools » Annotate from the menus.
2. In the Annotate dialog, click the Reset All button, then click OK in the Information dialog that
appears. Note that the Proposed Designator column in the dialog now shows all designators
having a ? as their annotation index.
3. Click the Update Changes List button to assign a unique designator to each component. The
components are annotated positionally, according to the direction setting selected at the top
left of the dialog. The Information dialog that appears indicates how many designators have
changed from their original state. Don’t be surprised if not all components get a new
designator; it may be that their position on the sheet results in the same designator being
assigned.
4. Repeat the process of resetting and assigning, changing the direction option each time and
finishing with a direction option that you prefer.
5. To commit the changes and update the components, click the Accept Changes button to
generate an ECO. Click Execute Changes in the ECO dialog, then close the ECO and the
Annotate dialogs.
6. Note that each document that has been affected by the changes has an * next to its name on
the document tab at the top of the window. Save all documents in the project.

7. Compiling and verifying the project
This section looks at how to verify a design, an essential step before transferring to PCB layout. In
Altium Designer, checking the design is done by compiling the design which checks for logical,
electrical and drawing errors.
To compile your design, select Project » Compile PCB Design.
Once the design has been compiled, it can be navigated in the Navigator panel. Compiled results
are displayed in the Messages panel; from here, you can double-click to jump to an error or
warning. The Messages panel will only open automatically if there are errors, if it is not visible
click on the System button at the bottom of the workspace to display the panel.
Note that the default error checking options are on the cautious side, so review the settings and
adjust them to suit your project and design requirements.
7.1 Setting up to compile the design

When you compile the design, DXP builds a connective
model of the design – you can think of it as an internal netlist.
The presence of the internal netlist allows you to navigate or
browse the connective structure of the design.
7.1.1 Compiler options

• Before the design can be compiled, the project options
must be configured. This is done in Options tab of the
Options for Project dialog (Project » Project Options).
• The Net Identifier Scope must be appropriate for the
structure of the design. This topic is covered in 5.2.2 Net
identifier scope in the Multi-sheet Designs section.
• When the design is compiled, it can be navigated using
the Navigator panel. Select the Flattened Hierarchy at
the top of the Navigator. When you click on a component
or a net, that component or net will be displayed in the
workspace.
• Expand the component or net using the small + sign to
access all pins in the component or all pins/net identifiers
in the net.
• Click the button to the right of the Interactive

Navigation button to configure options that control how
the workspace will be displayed.
- Zoom: jump to the sheet and zoom in on the object
of interest.
- Select: select the objects of interest.
- Mask: fade all objects except those of interest. Figure 32. Use the Navigator to check
the design connectivity
Control the mask fade level using the Mask Level
button at the lower right of the screen. Clear the Mask using the Shift+C shortcut.
- Connective Graph: show the connective relationship with either red (for net objects) or
green (components) graph lines.

• The Navigate button in the panel allows you to navigate spatially. Click it to get a crosshair
cursor, then click on an electrical object in the workspace, such as a wire, net label, port etc,
to highlight all electrical connected objects.
• The Up/Down hierarchy button can also be used to navigate the design.
7.1.2 Error Reporting options
Figure 33. Setup for Error Reporting

• Error reporting options are configured in the Error Reporting tab and the Connection Matrix
tab.
• There is an extensive array of error reporting options which have default settings that are on
the cautious side. Generally, it is better to compile the design and then if there are warnings
that are not an issue for your design, change the reporting level.
7.1.3 Connection Matrix
Figure 34. ERC Rule Matrix tab

• The Connection Matrix tab in the Options for Project dialog is shown in Figure 34. This
matrix provides a mechanism to establish connectivity rules between component pins and net
identifiers. It defines the logical or electrical conditions that are reported as warnings or errors.
• For example, an input pin connected to an input pin would not normally be regarded as an
error condition, but connected output pins would not. This is reflected in the table.
• Rules can be changed by clicking on the appropriate square in the matrix, causing it to cycle
through the available options.
7.2 Interpreting the messages and locating the errors

• When you compile the project, any conditions which generate a warning or error will be listed
in the Messages panel. Note that the Messages panel will only open automatically if there is
an error condition.
• Double-click on an warning/error to pop up the Compile Errors panel, then double-click on
an object in that list to jump to it on the schematic.
• Right-click in the Messages panel to clear messages. Click on the column headings to sort by
that column. Double-click on a message to display the Compile Errors panel in which you
can double-click to cross probe to that object.
• Subsequent compilations will remove warning/error messages once the error conditions have
been corrected.
• It is important to examine each warning/error and resolve them, change the error checking
Report Mode, or mark them with a No ERC marker. This should always be done prior to
transferring the design to PCB layout.
7.2.1 Exercise – Configuring the project options

1. Select Project » Project Options to display the Options for Project dialog and click on the
Options tab.
2. For this project, the Net Identifier Scope can be left on automatic. Enable only the Allow
Ports to Name Nets in the Netlist Options.
7.2.2 Exercise – Design verification

1. Check your design by compiling your design and checking any errors or warnings.
2. Resolve any errors. Note that ‘Nets with no driving source’ reports any net that does not
contain at least one pin of the following electrical types: IO, Output, OpenCollector, HiZ,
Emitter or Power.
3. If you have any remaining warnings that will not affect your design, you can simply ignore
them or consider turning that warning type to No Report in the Error Reporting tab of the
Options for Project dialog.
Some tips
• Examine each of the objects associated with the error.
• Enable the Graph option to examine the connectivity of a net. Once a net is selected in the
Navigator panel, it is highlighted throughout the design. You can also ALT+click on a net to
highlight it on the current sheet.
• Errors with input pins are often due to problems with their source. If the input looks OK, trace
the signal back to the source (output pin / port).
Note: To open a sub-sheet, hold CTRL as you double-click on the sheet symbol.

8. Editing Multiple Text Objects
One of the powerful features of Altium Designer is the data editing system. An overview of this
system was covered in Module 1 – Environment and Editor Basics. The Schematic Editor
includes another feature that provides a very efficient mechanism to edit text strings in your
schematics.
8.1 Find and Replace Text

You can perform complete or partial
substitutions on text using the following
methods.
• To target a section of a string, include
the * or ? wildcards as appropriate. In
Figure 35, the combination of the Text
to Find, the Sheet Scope and the
Restrict to net Identifiers option will
result in any net label, port, sheet entry
or power port whose net attribute starts
with the letters RB being found.
• If you wish to replace the entire
contents of a text field with a new
value, simply enter the new value in the
Replace With field.
• Partial string substitutions can be
performed using the syntax
{oldtext=newtext}. This means you can
change a portion of the current string
(oldtext) to a new string (newtext). In
Figure 35, the letters RB will be
replaced with LCD. Any other
characters in each found net identifier
will remain the same. For example, the
Figure 35. Performing a partial string substitution
following changes would occur:
Before Find and Replace After Find and Replace
RB1 LCD1
RB200 LCD200
RBout LCDout
RB_CLK LCD_CLK
RB[0..7] LCD[0..7]

9. Interfacing to other design tools
This section outlines how to transfer a schematic design to the PCB Editor using the Synchronizer
and netlists.
9.1 Setting the relevant project options

There are a number of settings that control what data is transferred between the schematic
design and PCB layout. Select Project » Project Options to display the Options for Project
dialog and click on the Comparator tab.
Figure 36. The Comparator options define what information is transferred to PCB.
By default, all options are on. For a simple design such as the training design, you might not want
Placement Rooms to be created for each schematic sheet.
9.2 Transferring a design to the PCB Editor

• If you are using Altium Designer's PCB Editor to do the board layout, the best method of
transferring design information between the schematic and the PCB (and from the PCB back
to the schematic) is the Design Synchronizer. Using the Synchronizer, there is no need to
create a netlist in the schematic and load that netlist into the PCB. Selecting Design »
Update PCB will start the synchronization process.
• When you have a PCB and select this command, the Engineering Change Order dialog will
be displayed. This lists all the changes that must be made to the PCB to get it to match the
schematic. This process will be covered in detail during the PCB training module.
• You can also transfer the design using the Project » Show Differences command. This uses
the design synchronizer, but gives more comprehensive control of the transfer process.

9.3 Netlist formats
A netlist is an ASCII file that contains the component and connectivity information defined in the
schematic. The netlist can be used to transfer component and connectivity information to other
design tools, including PCB Design packages from other vendors. Note that you can still use it to
transfer to Altium Designer’s PCB editor, but since it does not include unique component ID
information it is an inferior method of design transfer.
Netlists are generated by using the Design » Netlist for Project menu. By default, there are
seven netlist formats in the menu, including EDIF, Xspice and Multiwire. Other netlist formats are
also supported. Download the required netlist generator from the Downloads page of the Altium
website (www.altium.com).
9.4 Exercise – setting project options for design transfer

Open the Options for Project dialog, and display the Comparator tab.
1. Set the Extra Room Definitions option to Ignore Differences.
2. Close the dialog and save the project.

10. Parameters
• Parameters are used to add extra information to sheets, sheet symbols, components, pins
and ports. Objects that do not handle parameters through their Properties dialog, such as
wires and buses, can have parameters attached to them by using Parameter Sets.
• Components will typically have many user-defined parameters, such as electrical design
parameters like voltage or tolerance values, or purchasing and assembly information. This
information is included by adding parameters to the schematic components via the
Components Properties dialog, either in the schematic library or on the schematic sheet.
• Parameters can also be used to link the schematic components with a company database,
refer to the documents Linking Existing Components to Your Company Database and Using
Components Directly from Your Company Database for more information.
Figure 37. Parameters can are added to schematic components via their Properties dialogs in the
Schematic Editor or the Schematic Library Editor.
• System-level parameters are special strings which have the suffix = before the parameter
name, such as =CurrentDate or =Revision. These can be added to your sheet’s title block and
are updated through the Parameters tab of the
Document Options dialog (Design »
Document Options). See 2.1.2 Parameters
tab for more information. You can update
system-level parameters in multiple documents
by using the Parameter Manager.
• Parameters are used to define PCB rules on
the schematic. Where you add the parameter
dictates the scope of the PCB rule that is
created – for example a Parameter attached to
a wire will create PCB rule that applies to that
net (). Whereas attaching the parameter to a
bus would result in a PCB design rule that
targets a NetClass.
• To define a rule targeting a net, select Place »
Directives » PCB Layout from the menus. Figure 38. Define PCB rules on the schematic
using parameters.

• Project and document parameters can be extracted from the project and included in the Bill of
Materials. Document parameters are included with each component that comes from that
document. Project parameters can be mapped to pre-defined Fields in your Excel template,
as shown below.
Figure 39. Include project parameters in your BOM by defining Fields in the Excel template.
10.1 The Parameter Manager

• The Parameter Manager allows you to control all
your parameters in one single editor. Open the
Parameter Manager by selecting Tools »
Parameter Manager from the menus. User-
defined parameters can be added, removed or
renamed in the Parameter Manager. You can
modify the values of system-level parameters but
these cannot be added, removed or renamed.
• You can select which parameters will be included
in the Parameter Table Editor by limiting the
types of parameters you wish to use in the
Parameter Editor Options dialog. For example,
you can exclude all system parameters, or only
use document-level or part parameters.
• Changes to the values or names of parameters are made in the Parameter Table Editor and
then an ECO is generated to execute the changes in the design or schematic library.

Figure 40. Parameters can be modified using the Parameter Table Editor.
Tips for using the Parameter Manager

• Editing in the Parameter Table Editor is similar to editing in an Excel spreadsheet. For
example, press F2 or SPACEBAR to edit, type in the value or select it from a drop-down list, if
available, and then press Enter. Use the arrow keys to move through the spreadsheet.
• You can edit multiple instances of the same parameter value by selecting the cells, right-
clicking and selecting Edit for the drop-down menu. Type in the new value and press Enter.
Right-click and choose Revert to undo changes to selected cells.
• Cells are highlighted in the Parameter Table Editor according to whether the parameter exists
or has current values.
the object possesses the parameter and the string entry in the field is
its value.
the object possesses the parameter, but it currently has no value
the object does not possess the parameter.
• When you modify a parameter, markers in the right-hand top corner of the cell indicates what
changes will be made.
the value assigned to the parameter will be changed.
the parameter will be added to the object but, in this case, no value will
be assigned.
the parameter will be removed from the object.
• Note that any changes made within the table are virtual changes that will not be implemented
until the execution of an Engineering Change Order.
• Press F1 in the Parameter Manager dialogs for more information.

10.2 Exercises – Using the Parameter Manager
10.2.1 Adding values to parameters using the Parameter Manager

1. The first exercise will add sheet numbers and the number of sheets using the Parameter
Manager.
2. Open the Parameter Manager (Tools » Parameter Manager).
3. In the Parameter Editor Options dialog, in the Include Parameters Owned By region, enable
only the Documents checkbox, then click OK.
4. In the Parameter Table Editor for the project, check that the SheetNumber and SheetTotal
parameter fields are set appropriately. Single or multi-select and edit and right-click and Edit
if required (press Enter to update multiple fields in a single edit).
5. Check that the Title fields are defined appropriately – update if required.
6. Click on Accept Changes (Create ECO) to display the Engineering Change Order dialog,
then Validate and Execute the changes.
7. Check that the title and sheet numbers display correctly in the schematic title block. Make
sure Convert Special Strings is enabled in the Graphical Editing tab of the Schematic
Preferences dialog to view them on screen.
10.2.2 Adding new parameters using the Parameter Manager

1. This exercise adds a new parameter, named Part Number, to all components in the design.
2. In the Schematic Editor with the required schematic documents open, select Tools »
Parameter Manager to display the Parameter Editor Options dialog.
3. In the Include Parameters Owned By section of the dialog clear the Documents checkbox,
enable the Parts checkbox, then select All Objects as the criteria. Click OK.
4. In the Parameter Table Editor dialog, click on Add Column. The Add Parameter dialog
displays. Type in a new parameter name, e.g. Part Number, and enable Add to all objects.
Click OK to create the new parameter column. Enter values in the new Part Number column
as required. Click on Accept Changes (Create ECO).
5. Click on Validate Changes. If the validation is successful, click on Execute Changes.
6. When the changes have been executed, click Close. The new parameters are added to the
components in the schematic. These can be checked by double-clicking on the components
in the schematic document to display the Component Properties dialog. The new parameter is
added to the Parameters list.

11. Reports
There are reports available in the Schematic Editor that are used to create a Bill of Materials, or
list Single Pin Nets.
11.1 Schematic Editor reports

The following commands generate reports as described below:
• Reports » Bill of Materials command opens the Bill of Materials dialog. Use this dialog to:
- Choose which component attributes to include in the report (enable the required
checkboxes in the Other Columns region).
- Order the columns (drag and drop a column in the main region to define the required
order).
- Group columns (drag the required names from the Other Columns region to the Grouped
Columns region).
- Assign an Excel template to use when the report is generated via the Excel button. A
sample template is supplied. Use it as a reference to construct your own.
- Generate the BOM using either the Export, Excel, or Report buttons. Clicking the Excel
button will first load the BOM into a preview window. From there, you can open it in Excel.
Figure 41. An example of a BOM in Excel format

• For help on the various features, use the What’s This Help button or press F1 over the
dialog for a complete description of all the features in the dialog.
• Reports » Project Hierarchy generates a .rep file (i.e. <document folder name>.rep)
which includes a list of all the files (including their full path) that make up the project. The
report allows the designer to quickly verify the project file structure. Note that this report is
added to the Projects panel but does not open automatically.
• Reports » Component Cross Reference opens the Component Cross Reference Report
dialog, with a list of each of the components in the project. Note that this report is no longer
pre-formatted as it was in earlier versions; you can format it in the same way that a BOM can
be formatted.
• Reports » Simple BOM generates a Bill of Materials in the same format as generated by
earlier versions of Protel.
• Reports » Single Pin Nets generates a list of all component pins that have a wire touching
them but are not connected to any other wired pin. Note that this report is added to the
Projects panel but does not open automatically.

12. Printing
12.1 Setting up and printing
• Use the powerful Print Preview feature to view and configure the printout before sending it to
the printer (select File » Print Preview).
Figure 42. Print Preview dialog
• Right-click in the preview window and select Page Setup to configure the scaling and color.
• Right-click in the preview window and select Printer Setup to configure the target printer,
which documents to print (current or all), the number of copies, and so on.
• Right-click in the preview window to Copy the active document to the clipboard, or save it as
a metafile.
Note: Schematic printout setups can be defined in a project OutJob file. This is handy if you
need a number of different configurations of printouts for a project.

PCB Design
Training Module
PCB Design training module ii

PCB Design Training Module
1. PCB design process ................................................................................................. 4-1
1. The PCB Editor workspace ...................................................................................... 4-3
1.1 PCB Panel ...................................................................................................... 4-3
1.2 Using the PCB Editor panel to browse........................................................... 4-4
1.3 PCB Editor Preferences ................................................................................. 4-9
1.4 Board Options dialog.................................................................................... 4-25
1.5 Board Layers and Colors.............................................................................. 4-26
1.6 The PCB coordinate system......................................................................... 4-27
1.7 Grids ............................................................................................................. 4-27
2. Browsing footprint libraries ................................................................................... 4-29
3. Creating a new PCB ................................................................................................ 4-30
3.1 Creating the Blank PCB ............................................................................... 4-30
3.2 Defining a sheet template.............................................................................4-30
3.3 Defining the Board Shape, and Placement / Routing Boundary................ 4-31
3.4 Exercise – Creating a board outline & placement / routing boundary.......... 4-32
4. Transferring design information to the PCB............................................................. 4-34
4.1 Design synchronization ................................................................................4-34
4.2 Resolving synchronization errors ................................................................. 4-35
4.3 Design transfer using a netlist ...................................................................... 4-36
4.4 Exercise – Transferring the design .............................................................. 4-37
5. Setting up the PCB layers ...................................................................................... 4-38
5.1 Enabling Layers............................................................................................ 4-38
5.2 Layer definitions ........................................................................................... 4-39
5.3 Defining the Electrical Layer Stackup .......................................................... 4-41
5.4 Defining Mechanical layers .......................................................................... 4-43
5.5 Internal power planes ................................................................................... 4-43
5.6 Exercise – Setting up layers......................................................................... 4-45
6. Design rules and design rule checking ................................................................ 4-46
6.1 Adding design rules...................................................................................... 4-46
6.2 Design rules concepts .................................................................................. 4-47
6.3 How rules are checked.................................................................................4-49
6.4 Where rules apply ........................................................................................ 4-50
6.5 Object classes .............................................................................................. 4-52
6.6 From-tos ....................................................................................................... 4-53
6.7 Exercise – Setting up the design rules......................................................... 4-53
6.8 Design Rule Checking..................................................................................4-54
7. Component Placement tools.................................................................................. 4-56
7.1 Placing components ..................................................................................... 4-56
7.2 Finding components for placement .............................................................. 4-56
7.3 Moving components .....................................................................................4-57
7.4 Interactive Placement commands ................................................................ 4-58
7.5 Auto Placement ............................................................................................ 4-59
7.6 Re-Annotation .............................................................................................. 4-59
7.7 Exercise – Component Placement............................................................... 4-60
8. Routing..................................................................................................................... 4-61
PCB Design training module iii

8.1 Interactive routing......................................................................................... 4-61
8.2 Automatic routing ......................................................................................... 4-67
9. Polygons .................................................................................................................. 4-69
9.1 Placing polygons .......................................................................................... 4-69
9.2 Exercise – Working with polygons ............................................................... 4-72
10. Output Generation .................................................................................................. 4-73
10.1 Creating a new Output Job file..................................................................... 4-73
10.2 Setting up Print job options ..........................................................................4-74
10.3 Creating CAM files ....................................................................................... 4-75
10.4 Running the Output Generator ..................................................................... 4-78
10.5 Exercise – adding an OutJob file to the project............................................ 4-78
PCB Design training module iv

1. PCB design process
The PCB Design training day covers how to use the PCB Editor to create a PCB from setup,
through component placement, routing, design rule checking and CAM output. This first section
looks at the overall PCB design process.
The diagram below shows an overview of the PCB design process from schematic entry through
to PCB design completion.
Figure 1. Overview of the PCB Design Process
PCB Design training module 4-1

Once the PCB design is completed and verified, the Create Manufacturing Output process is used
to generate the PCB output files. This process is outlined below in Figure 2.
Figure 2. Work flow for generating PCB output files

2. The PCB Editor workspace
This section investigates how to browse through a PCB design and how to set up the workspace
preferences and other document options, such as layers and grids.
2.1 PCB Panel

The PCB panel provides a powerful method of
examining the contents of the PCB workspace.
Clicking on an entry in the panel will filter the
workspace to highlight that object – the highlighting
will depend on the settings of the options at the top
of the panel. To begin with, enable all the options.
2.1.1 Browse mode selection list

The drop down list at the top of the panel allows
you to list, locate or edit the following PCB object
types in the active PCB document:
• Components (and then Component Classes)
• Nets (and then Net Classes)
• From-Tos
• Split Planes
• Design Rules & Design Rule Violations.
• Differential Pairs
When you select an object in the panel, it will be
highlighted in the workspace, according to the
options at the top of the panel. Each Browse
function is described in the following pages.
2.1.2 MiniViewer
The MiniViewer is located at the bottom of the
panel and provides an overview of the workspace.
The double-lined rectangle indicates the current
region being displayed in the workspace.
The MiniViewer also has the following display
control functions:
• Click and drag in the rectangle to pan around
the workspace.
• Click and drag on a corner of the rectangle to
change the magnification of the workspace.
Figure 3. PCB Editor panel

2.2 Using the PCB Editor panel to browse
2.2.1 Browsing nets and net classes

• To browse nets, select Nets from the drop-
down list in the PCB panel.
• Click on All Nets in the Net Classes region of
the dialog to browse all nets on the PCB. The
nets are listed in the region below and they are
also highlighted on the PCB.
• If the design includes Net Classes these are
also listed. Net classes such as D[0..7] have
been generated automatically from busses in
the design.
• Click on a net name in the Nets region to
choose it – all the objects that belong to that
net are listed in the Net Items region. Also, the
net is highlighted on the PCB.
• Click on an item in the Net Items region and
note that it is highlighted on the PCB. Also note
that the object that you clicked on is selected.
• Multi-select keys are supported. Hold SHIFT or
CTRL as you click on entries in the list.
• Right-click in the Net Items section and note

that you can control which net items are
displayed.
• Double-click on a net name to open the Edit
Net dialog. Here you can change the net name,
add or remove nodes from the net and define
the color of the connection lines for this net.
• The Nets and the Net Items region have
multiple columns. Note that you can control the
sorting by clicking the heading on a column.
• Type-ahead is supported. You can type on the
keyboard to jump through the lists. Press Esc
to abort the current type-ahead search and
start another.
Figure 4. Browsing nets from the

PCB panel

2.2.2 Browsing components and component classes
• To browse components, select Components from
the drop-down list.
• When the panel is being used to filter (highlight)
components, you might find it better to have the
Select option at the top of the panel switched off.
• Click on All Components in the Components Class
region to browse all components on the PCB. The
components are listed in the Components region, as
well as being highlighted on the display.
• If the design includes component classes, these are
listed too, when you click on a component class only
the components in that class are listed and
highlighted.
• Click on a component name in the Components
region to choose it. All the objects that belong to
that component are listed in the Component
Primitives region. Also, the component is highlighted
on the PCB.
• Click on an item in the Component Items region,
Note that it is highlighted on the PCB. Also note that
the object that you clicked on is selected.
• Multi-select keys are supported. Hold SHIFT or CTRL
as you click on entries in the list.
• Right-click in the Component Items section. Note
that you can control which component primitives are
displayed.
• Double-click on a component name to open the
Component dialog where you can modify any
attribute of the component.
• The Components and the Component Items region
have multiple columns. Note that you can control
the sorting by clicking the heading on a column.
• The order of the columns can also be changed; click
and drag a column to change the column order.
This is handy when you wish to use the type-ahead
feature on a different column.
• Type-ahead is supported. You can type on the Figure 5. Browsing components from the PCB
panel
keyboard to jump through the lists. Press ESC to
abort the current type-ahead search and start
another. The type-ahead is always performed on
the left-most column, so drag any column to make it
the left-most.

2.2.3 Browsing design rules and rule violations
To browse design rules, select Rules from the
drop-down list. All Rules classes are listed.
• Click on a Rule Class and all rules defined for
that class are listed in the Rules list.
• Click on a rule in the Rules list to highlight all
objects targeted by that rule.
• Double-click on the rule to display a dialog to
edit that rule.
• If the selected rule is in violation, all violating
objects are listed in the Violations region. To
check all rules for violations, select [All Rules]
in the Rule Classes section.
• Click on a violation to highlight the object
causing the violation.
• Double-click on a violation to display the
Violation Details dialog which details the rule
that is being violated and the parameters of the
primitive that is causing the violation.
• For more information about design rule
checking and violations, refer to 7.3 How rules
are checked.
Figure 6. Browsing design rules from

the PCB panel

2.2.4 From-To editor
• Choose From-To Editor from the drop-down field at
the top of the PCB panel. The top list section of the
panel will fill with all nets currently defined for the
design.
• As you click on a net entry, all of the nodes on that
net will be loaded into the middle list section of the
panel. Filtering will be applied and a mask
automatically used in order to leave just the nodes
(pads) on the net fully visible. All other objects are
dimmed.
• Double-click on a net entry to open the Edit Net
dialog where you can edit the properties of the net.
• To add a new from-to, select the Nodes on Nets to
which you want to add the from-to and click the Add
From To button. The new from-to appears in the
From-Tos on Net section. Click on the from-to in the
From-Tos on Net section and click on Generate and
select a from-to topology, e.g. Shortest, Daisy
varieties or Starburst.
• The From-To editor can only be used to create from-
tos. To browse for existing from-tos, create a query
in the Filter panel using the IsFromto keyword.
• Note that all connection lines, other than those that
have been defined as From-Tos on the currently
selected net, will remained dimmed. Switch the
panel back to Nets to restore the display of Figure 7. The From-To Editor in the PCB
connection lines. panel
2.2.5 Split Plane editor

• You can review and edit split planes in the PCB
panel by selecting the Split Plane Editor from the
drop-down list at the top of the panel.
• Select the plane you want to display by clicking on
the Plane name. The split planes and their nets on
that power plane are listed.
• Click on a split plane name in the Split Planes and
Nets section to show the pads and vias on that split
plane.
• Double-click on a split plane name to edit the net
associated with the split plane.
• Right-click on a split plane name to select an option
from the menu.
Figure 8. Use the Split Plane Editor to

display split planes

2.2.6 Differential Pairs Editor
• You can review and edit Differential Pairs in the
PCB panel by selecting the Differential Pairs
Editor from the drop-down list at the top of the
panel.
• Select the Differential Pair Class you want to
display by clicking on the Differential Pair Class
name. The Differential Pair Designators will then
be listed.
• Click on a Differential Pair name in the
Differential Pair section to show the constituent
nets of the pair, both positive and negative.
• Double-click on a Differential Pair name to edit
the nets associated with the Pair and view the
options.
• Right-click on any Differential Pair Class listing
(Excepting the default class of All Differential
Pairs) and the Object Class Explorer dialog will
open allowing you to modify your Classes.
Figure 9. Use the Differential Pairs Editor to

display Differential Pairs.
2.2.7 Exercise – Browsing a PCB document

In this exercise, you will examine the various ways to browse through a PCB document.
1. Open the document 4 Port Serial Interface.PcbDoc located in the \Altium
2. Choose the Fit Board view command. Try the other view control options in the View menu.
3. Use the MiniViewer to move around the board.
4. Browse each object type and observe how the display changes as you click in the different
sections of the panel. As you do, try the Mask, Select and Zoom options.

2.3 PCB Editor Preferences
The Preferences dialog allows you to set up parameters relating to the PCB Editor workspace.
This dialog is displayed using the Tools » Preferences menu command. Settings in this dialog
are stored with the Altium Designer environment, so they remain the same when you change
active PCB files. The options in each of the pages are described below.
2.3.1 General page
Figure 10 General page of the PCB preferences
Editing options
Online DRC
When checked, any design rule violations are flagged as they occur. The design rules are defined
in the PCB Rules & Constraints Editor dialog (select the Design » Rules menu command).
Snap to Center
When checked, the cursor snaps to the centre when moving a free pad or via, snaps to the
reference point of a component, or snaps to the vertex when moving a track segment.
Smart Component Snap

When enabled, cursor jumps to center of nearest component pad rather than the component
reference.

Double Click Runs Inspector
When enabled, double-click opens the Inspector instead of the object’s traditional dialog.
Remove Duplicates
With this option enabled, a special pass is included when data is being prepared for output. This
pass checks for and removes duplicate primitives from the output data.
Protect Locked Objects

When checked, locked objects cannot be moved. If they are part of a selection that is being
moved, you will be asked to confirm the action.
Confirm Selection Memory Clear
Eight selection memories are available – click the button at the bottom of the workspace to
display the Selection Memory controls (press F1 over the panel for details of the shortcuts for
using the selection memory). The Selection Memories work just like a calculator — the selection
state of objects can be stored, recalled and added to on storage or recall. Enable this option to
display a warning dialog when the contents of a section are to be cleared.
Click Clears Selection

The selection behavior in Altium Designer is like all other Windows applications, i.e. when you
click on an object, it is selected and when you click away from that object, it is deselected. If this
option is disabled, clicking away from an object no longer deselects it. If this option is off, you use
the Deselect options in the Edit menu.
Shift+Click to Select
Rather than simply clicking on an object to select it, you can configure Altium Designer to require
that the SHIFT key must be depressed when clicking to select it. Press the Primitives button to
choose which objects will require Shift+Click to select. Popular choices include rooms, polygons
and components.
Preserve Angle When Dragging

Enable this option so that when the tracks are being dragged on the PCB document, the angles of
these track segments are preserved, maintaining the routing quality. You can also create new
segments by dragging the drag handles, while holding down the Alt key before performing the
drag operation will revert to the previous behavior. The new drag method also has an avoid
obstacle mode which is toggled with the Shift + R short cut.
Smart Track Ends

If this Smart Track Ends option is enabled the net analyzer will attempt to keep connection lines
attached to the ends of the tracks. For example, if you start routing from a pad, and then stop the
routing (leaving the track end in free space), the net analyzer will attach the connection line to the
track end rather than the originating pad.
Note: The connection line can be either as a solid or dotted line in this mode. A solid line denotes
that there is no routing topology rule assigned, and the net analyzer simply connects the various
sub nets at their nearest locations. A dotted connection line denotes that there is a routing
topology rule for this net and the net analyzer attempts to obey this topology rule by drawing a
partially routed connection.
PCB Design training module 4 - 10

Other section
Undo/Redo
This sets the undo stack size, i.e. the number of undo/redos available. Note that the higher the
number, the more memory required. For object intensive operations, like autorouting or copying
and pasting the entire board, the memory usage can be significant.
Rotation Step
When an object that can be rotated is floating on the cursor, press the SPACEBAR to rotate it by
this amount in an anti-clockwise direction. Hold the SHIFT key while pressing the SPACEBAR to
rotate it in a clockwise direction.
Cursor Type
Set the cursor to a small or large 90-degree cross, or a small 45-degree cross.
Component Drag
This option determines how connected tracks are dealt with when moving a component. When
Connected Tracks is selected, tracks drag with the component; otherwise, they do not.
- If the Connected Tracks option for components is set, components cannot be rotated
while being moved.
Autopan options
Style
If this option is enabled, Autopan becomes activated when there is a crosshair on the cursor.
There are six Autopan modes:
• Re-Center — re-centers the display around the location where the cursor touched the window
edge. It also holds the cursor position relative to its location on the board, bringing it back to
the centre of the display.
• Fixed Size Jump — pans across in steps defined by the Step Size. Hold the SHIFT key to pan
in steps defined by the Shift Step Size.
• Shift Accelerate — pans across in steps defined by the Step Size. Hold the SHIFT key to
accelerate the panning up to the maximum step size, defined by the Shift Step Size.
• Shift Decelerate — pans across in steps defined by the Shift Step Size. Hold the SHIFT key to
decelerate the panning down to the minimum step size, defined by the Step Size.
• Ballistic — pans at maximum speed.
• Adaptive — pans at the rate set in the Speed field.
Speed
When Adaptive is enabled, the panning speed for Autopanning is set in mils/sec or pixels/sec.
Step and Shift Step Size

Some of the Autopan styles require step sizes. These options set the distances that define the
autopanning step distance and the step distance when you hold down the SHIFT key while
autopanning. The default distances are in mils or mms and the larger the number, the faster the
panning speeds.
Polygon Repour
This has three options for determining whether a polygon repours when edited:
• Never — no automatic repour.

• Threshold — if selected, polygons with more than the Threshold Number of primitives will
prompt to confirm repour, before performing the repour.
• Always — polygon always repours.
2.3.2 Display page
Figure 11 Display page of the PCB preferences
Display options section

Convert Special Strings
When enabled, special strings that can be interpreted on screen are converted and displayed,
rather than simply displaying the special string text. Regardless of this setting, all special strings
are converted when output is generated, e.g. printed.
Redraw Layers
Forces a screen redraw as you toggle through layers with the current layer being redrawn last
Transparent Layers
Gives layer colors a ‘transparent’ nature by changing the color of an object that overlaps an object
on another layer, allowing objects that would otherwise be hidden by an object on the current
layer to be readily identified. The background color changes to black for easier viewing.

Use Alpha Blending
Toggle this option if your video card does not support Alpha Blending or if you suspect your Video
Card Drivers are having difficulty using this graphic feature.
Highlighting Options section

Highlight in Full
Completely highlights the selected object in the current selection color. With this option disabled,
the selected object is outlined in the current selection color.
Use Net Color for Highlight

This option is used on power plane layers to shade the plane in the net color.
Use Transparent Mode When Masking

Turn this option on to enable transparent object behavior for masked objects.
Show All Primitives in Highlighted Nets

Enable this option to display all primitives in a highlighted net, even if layers that net objects are
on are not currently enabled. Useful for a board with high layer count, requiring you to design with
only a few layers enabled at a time.
Apply Mask During Interactive Editing

Use masking (fading of objects that are not of interest) during interactive editing.
Apply Highlight During Interactive Editing

Highlight, or brighten objects of interest during interactive editing.
Show section
The check boxes in this section perform the following when checked.
Testpoints Displays testpoints
Origin Marker Displays the Origin Marker
Status Info Displays information about the object under the cursor in the status bar
Draft Thresholds section

Tracks
Tracks of the width entered in the check box (or narrower) will be displayed as a single line; tracks
of a greater width will be displayed as an outline (when tracks are displayed in Draft Mode).
Strings
The number entered in this field determines which strings are displayed as text and which are
displayed as an outline box. Strings that are placed at or greater than the height entered in pixels
(default 11) will be displayed as text; strings that are placed at a lesser value will be represented
by an outline box.
Plane Drawing section

These options control the display of power planes. The first two options present the plane layers
in the negative where objects on the layer represent no-copper. The Solid Net Colored option
shades each region on the plane in a semi-transparent shade of the current net color. If this mode
is selected and Single Layer Mode is enabled, pad and via plane connections are drawn in the
positive.

Layer Drawing Order button
The PCB Editor allows you to control the order in which layers are re-drawn. Click on the Layer
Drawing Order button to pop up the Layer Drawing Order dialog. The order that the layers
appear in the list is the order in which they will re-draw. The layer at the top of the list is the layer
that will appear on top of all other layers on the screen.
2.3.3 Board Insight Display page
Figure 12 Board Insight Display page of the PCB preferences
Pad and Via Display Options section

Pad Nets
Enable this option to show the Net name for all pads
Pad Numbers
Enable this option to show the pin numbers for all pads
Via Nets
Enable this option to show the Net name for all vias.
Use Smart Display Color

Enable this option for Altium Designer to control the font characteristics for the display of the pad
and via details. If this option is disabled you can set the font characteristics below.

• Font Color
• Transparent Background
1. Enable this option to use the background ground color surrounding the pad/via
details. Disable this option and set the Background Color.
• Background Color
Min/Max Font Size

• The minimum font size to be used to display the Pad and Via details, regardless of the zoom
level. This setting is not used if the Smart Display Color option is enabled.
• The maximum font size to be used to display the Pad and Via details, regardless of the zoom
level. This setting is not used if the Smart Display Color option is enabled.
Font Name
The font to be used to display the Pad and Via details. This setting is not used if the Smart
Display Color option is enabled.
Font Style
The font style to be used to display the Pad and Via details. This setting is not used if the Smart
Display Color option is enabled.
Minimum Object Size

The minimum size used to display the Pad and Via details, regardless of the zoom level. So at
low levels of zoom you can still maintain visibility of the pad and via details. This setting is not
used if the Smart Display Color option is enabled.
Net Names on Tracks section

Display
Enable this option to control the display of the net name on tracks.
You can choose from:
• Do Not Display - the net name is not displayed on the track
• Single and Centered - the net name is displayed once, in the center of the track
• Repeated - the net name is displayed all along the track
Single Layer Mode Options section

Current
Shows which Single Layer Mode option is currently in use. You can cycle through all available
modes while in PCB by pressing the SHIFT+S hotkey.
Available
Select which Single Layer Modes to cycle through when pressing SHIFT+S in the PCB editor.
• Hide Other Layers
2. Enable this option to include the Hide Other Layers as an available single layer mode
option. The SHIFT+S keyboard shortcut cycles through the available layer modes.
• Gray Scale Other Layers
3. Enable this option to include the Grey Scale Other Layers as an available single layer
mode option. The SHIFT+S keyboard shortcut cycles through the available layer modes.
• Monochrome Other Layers

4. Enable this option to include the Monochrome Other Layers as an available single
layer mode option. The SHIFT+S keyboard shortcut cycles through the available layer modes.
Note: The available Single Layer Modes here are shared with and set the same for the Board
Insight Lens although they maintain a separate setting for the current mode they are in.
2.3.4 Board Insight Modes page
Figure 13 Board Insight Modes page of the PCB preferences
Display Section
Display Heads Up Information
Enable this option to display context-sensitive information in your workspace. The information
that is displayed can be controlled with the Browse Mode settings. Most of this information is
already displayed in the status bar, however you can now raise your head up and look at this
information in the same area that you are working.
Use Background Color

Enable this option so that the Heads Up information is displayed with its background transparent.
Disable this options the Background Color setting is used.
Insert Key Resets Heads Up Delta Origin

Enable this option to reset the Delta Origin to the current mouse coordinates when the Insert Key
is pressed. The distance horizontally and vertically the mouse is moved from the Delta Origin can

be displayed in the Heads Up display. If this option is disabled then pressing Insert does not
reset the Delta Origin.
Mouse Click Resets Heads Up Delta Origin

Enable this option to reset the Delta Origin to the current mouse coordinates. The distance
horizontally and vertically the mouse is moved from the Delta Origin can be displayed in the
Heads Up display. If this option is disabled then a mouse click does not reset the Delta Origin.
Hover Mode Delay

Set the time for the mouse cursor to be idle before information of the object hovering under the
cursor is displayed.
Heads Up Transparency
Slide this bar to the right increases the level of transparency of the Heads Up display, making it
less visible.
Hover Transparency
If you pause for a moment as you are moving the cursor, the Heads-Up display will switch to
Hover mode. In Hover mode extra information is displayed, this can include a summary, available
shortcuts, rule violations, net, component and primitive details. This setting determines the
transparency of the Heads Up Display when it enters Hover Mode.
Visual Display Modes Section

Each Row within this section gives you the ability to enable or disable the information displayed in
the various available Board Insight modes as well as the Font options for each type of information
so it can be tailored to display in a way that you can quickly spot the information you are looking
for within the panel.
The Hover Preview and Heads Up Preview sections below give you the opportunity to ensure you
have not set font or color options in such a way that you will not be able to clearly see the
information in relation to various background colors at your current transparency level.

2.3.5 Board Insight Lens page
Figure 14 Board Insight Lens page of the PCB preferences
Configuration section
Visible
Enable this option to activate the Board Insight Lens facility and you can see magnified objects in
this lens facility from where the cursor is hovering on the PCB document.
X/Y Size
Click on the up or down arrow buttons to increment the X or Y coordinate by 10 units at a time to
change the size of the Board Insight Lens. Or use the slider to the right to adjust these values
Rectangular or Elliptical Radio Button

Enable this option to have the board insight lens shaped as a rectangle or elliptical. You can
change the size and the visibility of this insight lens.
Behavior section
Zoom Main Window to Lens When Routing
Enable this option and the Insight Lens is not displayed when auto-routing.

On Mouse Cursor
Enable this option to have the Insight Lens move with the cursor. Disable this option and the
Insight Lens position will be fixed location on the screen.
Animate Zoom
Enable this setting to adjust the zoom of the Insight lens as the zoom level of the main board is
adjusted.
Content section
Zoom
Click on the up or down arrow buttons to increment the zoom factor by 10 units at a time, or use
the slider on the right, to change the size of the viewable contents of the PCB document captured
by the Board Insight Lens.
Single Layer Mode

Shows which Single Layer Mode option is currently in use by the Board Insight Lens. You can
cycle through all available modes while in the PCB editor by pressing the Hotkey assigned in the
Hotkeys section of this dialog, by default this is CTRL+SHIFT+S.
Note: The Board Insight Lens maintains its own separate Single Layer Mode apart from the PCB
Editor, although they share the same Available Single Layer modes from the Board Insight
Display section
Hot Keys section

This is a list of action hot keys configured for the Board Insight Lens facility. To map new hotkeys,
while in PCB customize the commands found in ViewBoard Insight, by going to this menu and
holding CTRL before clicking on the menu item to Customize it (Environment & Editor Basics,
Section 6.)

2.3.6 Interactive Routing page
Figure 15. Interactive Routing page of the PCB preferences
Interactive Routing Conflict Resolution section

None
This is one of the three interactive routing conflict resolutions that controls how the standard
interactive router attempts to deal with obstacles during the routing process. Select this option to
do nothing. The routing mode can be changed on the fly using the Shift R hot key during
interactive routing.
Stop at First Conflicting Object

This is one of the three interactive routing conflict resolutions that controls how the standard
avoid obstacles while routing. The routing mode can be changed on the fly using the Shift R hot
key during interactive routing.
Push Conflicting Objects

This is one of the three interactive routing conflict resolutions that control how the standard
push obstacles (these conflicting objects) while routing. The routing mode can be changed on the
fly using the Shift R hot key during interactive routing.

Plow Through Polygons
Enable this option so you can route over polygons and then the polygons will be re-poured after
the route is complete. The Polygon Repour general option in the General Preferences page must
be enabled for the plow to work.
Interactive Routing Options section

Restrict to 90/45
This interactive routing mode determines the allowed directions and corner modes in which the
manual routing is done. Enable this option to restrict to 90/45 degree angled tracks when you
cycle through the modes during routing using the SHIFT+SPACEBAR keys.
Auto Complete
With this option enabled the Smart Interactive Router will try to complete the connection to the
target with the look-ahead segments.
Automatically Terminate Routing

With this option enabled, when you complete a route by terminating to the target pad the
interactive router will automatically terminate that route so you can begin routing from a new
location without escaping out of your currently selected route.
Automatically Remove Loops

With this option enabled, loops that are created during manual routing are automatically removed.
Note: Automatic Loop Removal can be disabled on an individual net to allow loops to be created
on that specific net. Access the net properties to alter this setting. An example of when this
would be necessary would be when a ground loop needs to be created.
Smart Connection Pad Exits section

Allow Diagonal
When this option is not enabled, the router will attempt to exit pads in a clean 90 degree angle
from the edge. Otherwise when the option is enabled, the pad exits are made diagonally by the
smart connection router. This option is only available when using the smart connection router.
Interactive Routing Width/Via Size Sources section

Pickup Track Width From Existing Routes
With this option enabled, if you begin a route from an existing track the width of that track will be
used for your current route.
Track Width Mode

• User Choice – With this mode enabled the Width will be determined by the width selected by
pressing Shift+W while routing.
• Rule Minimum – With this mode enabled the design rule minimum width defined for the
current net will be used.
• Rule Preferred – With this mode enabled the design rule preferred width defined for the
• Rule Maximum – With this mode enabled the design rule maximum width defined for the
Note: You can cycle between the above modes while interactive routing by pressing the 3 key.

Via Size Mode
• User Choice – With this mode enabled the Via Size will be determined by the size set after
pressing TAB while routing.
• Rule Minimum – With this mode enabled the design rule minimum Via Size defined for the
• Rule Preferred – With this mode enabled the design rule preferred Via Size defined for the
• Rule Maximum – With this mode enabled the design rule maximum Via Size defined for the
Favorite Interactive Routing Widths

Click this button to define favorite interactive routing widths that can be re-used. To use these
favorite width values during routing, the Shift W short cut will pop up the Chooser dialog which
allows you to quickly choose a value from the list of routing widths.
Smart Connection Routing Conflict Resolution section

None
This is one of the three smart connection routing conflict resolutions that will control how the
smart connection router attempts to deal with obstacles during the routing process. Select this
option to do nothing while smart connection routing. The routing mode can be changed on the fly
using the Shift R hot key during smart connection routing.
Stop at First Conflicting Object

This is one of the three smart connection routing conflict resolutions that control how the smart
connection router attempts to deal with obstacles during the routing process. Select this option to
avoid obstacles while smart connection routing. The routing mode can be changed on the fly
Walkaround Conflicting Objects

This is one of the three smart connection routing conflict resolutions that control how the smart
connection router attempts to deal with obstacles during the routing process. Select this option to
avoid obstacles while smart connection routing. The routing mode can be changed on the fly
Plow Through Polygons

Enable this option so you can route over polygons using the smart connection routing and then
the polygons will be re-poured after the route is complete. The Polygon Repour general option in
the General Preferences page must be enabled for the plow to work.
2.3.7 Show/Hide page

This dialog enables you to control which object types are displayed and how they are displayed.

2.3.8 True Type Fonts page
Figure 16 TrueType Fonts page of the PCB preferences
TrueType Fonts Save/Load Options Section

Embed TrueType fonts inside PCB documents.
True Type fonts are the fonts installed on your computer. Enable this setting to save the true type
fonts you have used in your PCB file. This will allow other machines which do not have this font to
view the design as you have intended.
Substitution font
The selected font will be used in those cases a PCB file is opened which has true type fonts
which are not installed in your computer.

2.3.9 Mouse Wheel Configuration page
Figure 17 Mouse Wheel Configuration page of the PCB preferences
This is a list of mouse wheel configurations (a mouse that normally has a wheel between two mouse
buttons) for various actions on a PCB document such as Ctrl key and mouse wheel to zoom in or out
on the main PCB window.
To modify the mouse wheel configuration, you can toggle the keyboard buttons as well as the
wheel/wheel click for each action.
2.3.10 Defaults page

This enables you to set the default properties for each primitive (object) type in the PCB Editor.
If the Permanent option is not checked on the Defaults tab, the settings in the object’s properties
dialog will change when you change the properties of an object during placement.
2.3.11 Exercises – Exploring the preferences

This exercise looks at various display options in the PCB section of the Preferences dialog.
2. Choose the Display page in the Preferences and try the following steps.
3. Enable the Show Pad Nets and Show Pad Number options.
4. Check the Single Layer Mode, click on OK and change active layers by selecting the various
layer tabs along the bottom of the PCB Design Window. Press the Shift+S shortcut keys to
turn single layer mode off.
5. Choose the Show/Hide page in the PCB section of the of the Preferences dialog.
6. Observe the effect of selecting All Draft and clicking OK. Now try the All Final and All
Hidden buttons to view different display modes.

2.4 Board Options dialog
The Board Options dialog allows you to set parameters relating to individual PCB documents.
Select Design » Board Options from the menus to open the dialog. The settings in this dialog
are saved with the PCB file.
Figure 18. Set grid options in the Board Options dialog.
Measurement Unit
Sets the coordinate system to either metric or imperial.
Snap X X value for the snap grid
Snap Y Y value for the snap grid
Component X X value for the component grid
Component Y Y value for the component grid.
Electrical Grid
When the electrical grid is enabled and you are executing a command which supports the
electrical grid and you move the cursor within the Grid Range value of an object assigned to a
net, the cursor will jump to that object.
Visible Grid
Sets the size and style of the visible grids.
Sheet Position
The sheet is a calculated object, drawn to represent the printed page. The sheet size can either
be defined by the Size and Location settings in this dialog, or it can be linked to the contents of
mechanical layer(s). If it is linked to the contents of mechanical layer(s), you can use the Design
» Board Shape » Auto-position Sheet command to recalculate it when the contents of the linked
mechanical layers change.
Typically, the linked mechanical layers would be used for drawing detail that is required on the
printout. Another advantage of linking the sheet to mechanical layers is that both the sheet and
the mechanical layers can be hidden by disabling the Display Sheet option.
Designator Display
The designator display can be either the logical designator shown on the schematic or the
physical designator assigned when the design is compiled. Normally, these are the same except
in a multi-channel design when the physical designator includes channel identifier information.

2.5 Board Layers and Colors
This dialog is used to set the display state and color of each layer in the PCB (L shortcut key).
Figure 19 Board Layers and Colors dialog
Signal Layers and Internal Planes

These layers are added too and removed from the PCB in the Layer Stack Manager. Their color
and display state is controlled in this dialog.
Note: Press the accelerator key in brackets () next to the layer name to toggle that layers show
property while in this dialog
Mechanical Layers
There are 16 mechanical layers, disable the Only Show Enabled option to display the entire set
and enable a new mechanical layer for this PCB. Press F2 to edit the name of a mechanical layer.
Layer Pairs
Layer pairs are mechanical layers that have been associated to handle layer-specific component
data. For example, if you have component footprints that require glue information, define this on a
mechanical layer in the Library Editor, then pair this mechanical layer with another. When the
footprint is flipped to the bottom of the board, the information on the first mechanical layer is
automatically transferred to the paired mechanical layer.
Color Sets
The Default Color Set button sets the colors to the default settings with a pale yellow
background. Default colors cannot be used if the Transparent Layers option (Display tab) is
selected. The Classic Color Set button sets the colors to the traditional black background setting.

Keep-Out Layer
The keep out layer is a special layer. Objects placed on the keep out layer act as an obstacle or
boundary to an object placed on any signal layer. The keep out layer is typically used to define
regions such as the board routing and placement boundary, or areas of the board that must be
kept free of components and routing. The keep out layer is discussed more in section 4.
2.6 The PCB coordinate system

The PCB Editor has a coordinate system with the origin located in the bottom left hand corner of
the workspace. This point has the coordinates of (0,0) and is known as the Absolute Origin. The
workspace size is 100 inches by 100 inches. The reference point of the coordinate system can be
re-defined at any time using the Edit » Origin » Set menu command and this sets what is known
as the relative Origin. The coordinate readout in the status bar references this relative Origin. The
Edit » Origin » Reset menu command sets the relative Origin back to the Absolute Origin.
An Origin Marker shows the location of the relative Origin. This is displayed by checking the
Display Origin Marker check box in the Display tab of the Preferences dialog.
The coordinate system units can be either metric or imperial. The View » Toggle Units menu
command or the Q shortcut key toggles the co-ordinate system between metric and imperial.
2.7 Grids
2.7.1 Snap Grid

The Snap Grid ensures accurate movement and placement of objects. The Snap Grid causes the
coordinates of a mouse click to snap to the nearest snap grid point. The Snap Grid has X and Y
values and is set in the Board Options dialog. Press G or CTRL+G shortcuts to change the grid.
2.7.2 Component Grid

The Component Grid is similar to the Snap Grid except that it is only active when placing or
moving components. The Component Grid has X and Y values and is set in the Board Options
dialog.
2.7.3 Visible Grid

The Visible Grids either display as lines or dots when turned on. They are independent of the
Snap Grid. The PCB Editor has two visual grids that you can set in the Board Options dialog and
display independently.
2.7.4 Electrical Grid

The Electrical Grid can be thought of as a range of attraction. During interactive editing the cursor
will jump to any existing electrical object when the cursor falls within the range of the electrical
grid setting.
When the Electrical Grid overrides the Snap Grid an
octagon displays on the cursor when the hot-spot (or
electrical centre-point) is under the cursor. When you see
that octagon, you know that the cursor is precisely located
on the object it has jumped to.
The Electrical Grid is set and turned on or off in the Board
Options dialog. You can also toggle the Electrical Grid on
and off using the SHIFT+E shortcut, or disable it temporarily
during an edit-type operation (such as interactive routing)
by holding down the CTRL key.

Shortcut keys for setup options
Pressing the O shortcut key displays a menu that provides a quick way of accessing the setup
dialogs. Combine this shortcut with the underlined letter in the menu options, e.g. OB to display
the board options. The options in this menu are described below.
Option Dialog displayed

Board Options Board Options dialog
Board Layers Board Layers and Colors dialog (can also use the L shortcut)
Layer Stack Manager Layer Stack Manager dialog
Classes Object Classes dialog
Preferences Preferences dialog (Tools » Preferences)
Display Display tab of Preferences dialog
Show/Hide Show/Hide tab of Preferences dialog
Defaults Defaults tab of Preferences dialog
2.7.5 Exercise – Exploring document and environment options

Use this exercise to experiment with document and environment options.
2. Experiment with the Used On, All On and All Off buttons and with turning on and off
individual layers in the Board Layers & Colors dialog.
3. Observe the display change when the Display Sheet option is toggled in the Board Options
dialog.
4. Experiment with changing the colors of various layers.
5. Now, experiment with changing the various grid settings to see changes in the grid display
and object movement in the Board Options dialog.
6. In the Defaults tab of the Preferences dialog, select Component and click on the Edit
Values button. In the Comment section of the Component dialog, make sure the Hide option
is enabled. Also check the Autoposition option is set to Left-Above in the Designator
section.

3. Browsing footprint libraries
PCB libraries are accessed through the same panel as schematic libraries – the Libraries panel.
• Enable the footprint display mode by

clicking the button at the top of the
panel and enabling the Footprints
checkbox.
• Select a library name in the drop down
list to choose it and display all the
footprints in that library. This can be
either an integrated library or a footprint
library.
• Footprint libraries that are in the active
project, currently installed or found
down the search path are available in
the panel.
• Click the Libraries button at the top
panel to install a footprint library.
• Library search paths are defined in the
Search Path tab of the Options for
Project dialog.
• To Search for a footprint, first enable
the Footprints mode, then click the
Search button.
• Click on a footprint name in the list to
display that footprint in the MiniViewer.
• Click on the Place button to place the chosen footprint in the workspace, or double-click on the
footprint name.

4. Creating a new PCB
This section looks at how to create a new PCB using the Board Wizard.
4.1 Creating the Blank PCB

There are three ways to create a new PCB:
• Select File » New » PCB from the menus. This creates an empty PCB workspace, with a 6in
by 4in board shape.
• In the New from Template region of the Files panel, select PCB Templates. This opens the
Choose Existing Document dialog where you can select from an array of template files. The
template name indicates the sheet size and each template file also includes a default board
shape, typically 6in by 4in.
• Using the Board Wizard. This is launched from the bottom of the Files panel. The Wizard can
be used to select from a pre-defined list of industry standard board shapes or generate a
simple board outline.
Figure 20. A new PCB created by using the New from Template option.
4.2 Defining a sheet template

The PCB sheet template is simply a display feature that is linked to mechanical layers in the PCB
design. In the Board Layers and Colors dialog there is a checkbox next to each mechanical layer,
titled Linked to Sheet. Any layer with this enabled is used by the software to calculate the size of
the white sheet region.
• Define a template on a mechanical layer using the standard design objects, enable the Linked
to Sheet checkbox, and enable the display of the sheet in the Board Options dialog. If you

change the shape or size of the template, select Design » Board Shape » Auto Position
Sheet from the menus to automatically resize the white sheet region to just enclose all objects
on the linked mechanical layers.
• There are a number of pre-defined PCB sheet templates in the \Altium Designer
6\Templates folder, open the required size and copy the contents of Mechanical 16 into your
own PCB to create a sheet template.
4.3 Defining the Board Shape, and Placement / Routing

Boundary
Once the blank board has been created the next step is to define the shape of the board (typically
this is the final finished board shape), and the routing and placement boundary.
• The board shape can be defined manually using the commands in the Board Shape sub-
menu, or by getting the software to define it automatically from a set of selected objects.
Defining it from selected objects is typically done when you have imported a board shape
definition from another tool, such as a mechanical CAD package.
• The placement and routing boundary is defined by placing a continuous barrier on the Keep
out layer (described later in section 6.2). Any object placed on the keep out layer is considered
an obstacle to objects on all the signal layers. Typically the keep out boundary is defined
along, or slightly in from the board outline, taking into consideration any mechanical clearance
requirements, such as brackets, card guides, and so on.
Figure 21. Board shape (black region) and keep out boundary for the 4 Port Serial Interface example PCB.
The row of small fills is there to prevent routing between the contacts of the edge connector.

4.4 Exercise – Creating a board outline & placement / routing
boundary
This exercise creates a new board outline for the training example.
1. Display the Files panel (View » Workspace Panels » Files) and click on the PCB Templates
option in the New from template section.
2. Choose A4.pcbdoc in the Choose Existing Document dialog. The new blank PCB will open,
as shown in Figure 20, where the black region on the sheet represents the board shape. We
will now redefine it based on data in a DXF mechanical file.
3. Select File » Import to display the Import File dialog.
4. Set the Files of Type option to AutoCAD (*.DXF, *.DWG)
5. Browse and locate the file \Altium Designer 6\Examples\Training\Temperature
Sensor\Outline.DXF and open it.
Figure 22. Import the board shape from a DXF file.
6. When the Import from AutoCAD dialog appears, set the following:
7. Set the Scale to inch (the imported shape should be approximately 2021mil x 2755mil)
8. In the Layer Mapping, map the source DXF layer to mechanical layer 4
9. Set the Insertion Point to something sensible, for example X=1000, Y=1000. The value is
not crucial, as you will move it after importing.
10. leave other options at their defaults

11. When the OK button is clicked, four track segments, forming a rectangle, will appear on
Mechanical layer 4.
12. We will now redefine the board shape to match this shape. Select the four track segments
(drag a rectangle around them).
13. Select Design » Board Shape » Define from selected objects. The black board shape will
redefine to match the imported tracks.
14. To move the new board shape to the centre of the sheet, drag a rectangle to select the board
shape and the mechanical layer tracks, press the M key to display the Move submenu and
select Move Selection. Click somewhere on the selection to define the point where it will be
held, then move the board outline and mechanical layer tracks approximately to the centre of
the sheet, and click to place them.
- Note: To ensure that objects remain on your preferred working grid it is generally
better to select a meaningful point when moving or copying & pasting objects, in this case
the point at the bottom left of the rectangle where the vertical and horizontal tracks meet
would be suitable. If you want to set your reference point based on an object, make the
layer that the object is on the active layer – that way the electrical grid will pull the cursor to
a meaningful point on the object.
15. Change the Visible grid 2 to 100 mils in the Board Options dialog.
16. To define the placement / routing boundary first deselect all. The easiest way to select all the
tracks on Mechanical layer 4 is to use the select on current layer command. To do this, make
the Mechanical layer the active layer (use the layer tabs at the bottom of the PCB
workspace), press S for select, then Y to select all on the current layer.
17. Choose Edit » Copy from the menus, choosing an appropriate reference point to hold the
selection by when prompted (such as one of the corners).
18. Make the Keep out layer the current layer. If the Keep out layer is not currently enabled, press
L to display the Board Layers and Colors dialog and enable it.
19. You are now going to paste the selection onto the current layer (the Keep out layer). To do
this select Edit » Paste Special from the menus, enable the Paste on Current Layer option
in the Paste Special dialog, and click OK to return to the workspace where you can paste the
tracks onto the keep out layer.
20. Save the new PCB as \Altium Designer 6\Examples\Training\Temperature
Sensor\Temperature Sensor.PcbDoc.
21. Check in the Projects panel If the board is part of the Temperature Sensor project. If it is not,
click and drag the board, dropping it on the project name.
22. Right-click on the project name and choose Save Project from the floating menu.

5. Transferring design information to the PCB
Rather than using an intermediate netlist file to transfer design changes from the schematic to the
PCB, Altium Designer has a powerful design synchronization feature.
5.1 Design synchronization
The core features of the synchroniser are:

• Difference engine — compares the schematic project to the PCB. The difference engine can
compare the component and connective information between almost all kinds of documents. It
can compare a schematic project to a PCB, one PCB to another PCB, a netlist to a PCB, a
netlist to a netlist, and so on. The differences found by the difference engine are listed in the
difference dialog.
• Difference dialog –lists all differences detected between the compared documents. You can
then define which document should be updated to synchronize the documents. This approach

allows you to make changes in both directions in a single update process, giving your bi-
directional synchronization. Right-click in the dialog for direction options.
• Engineering Change Order dialog – Once the direction of update for the differences has
been defined, a list of engineering change orders is generated. A report of these can be
generated.
There are two approaches to performing an update:
• Select Design » Update to push all changes from schematic to PCB (or PCB to schematic). If
you choose this option, you have indicated the direction to use, so you go straight to the ECO
dialog.
• Select Project » Show Differences if you need selective control of the direction. You also use
this option if you wish to compare any other document kinds, for example, to compare a netlist
to a PCB (also referred to as loading a netlist into a PCB).
5.2 Resolving synchronization errors

Most problems with synchronizing a design generally fall into two categories:
1. Missing component footprints. This occurs when:
- A footprint is missing from the component information in the schematic.
- You have forgotten to add the required PCB libraries to the currently available libraries.
- The footprint in the schematic does not match any PCB library component.
2. Footprint pin numbers not matched to schematic pin numbers. Altium Designer supports user-
definable pin-to-pad mapping, the default behavior is to expect the same number/letter on
both sides. Pin-to-pad mapping is defined in the PCB Model dialog (edit the schematic
symbol, select the footprint in the Model region of the dialog, and click Edit).
To resolve errors, perform a Show Differences, then in the Differences dialog click the Explore
Differences button. The Differences panel will appear – as well as information on what the
problem is. This panel lists the objects in question on both the schematic and PCB. Click on an
object to display it.
Note: If there are large scale net connectivity changes it can be easier to clear the netlist in the
PCB editor, the synchronisation process will reload them all. You will then need to reapply the
net information to any routing, to do this use the Update Free Primitives from Component
Pads command (Design » Netlist).

5.3 Design transfer using a netlist
For most situations, the Synchronizer has superseded netlist loading. In cases where the PCB is
being designed from a schematic drawn on another EDA vendor’s schematic editor, a netlist can
be used.
Using the difference engine, the component and connectivity information in the netlist can be
compared to the PCB.
Using a netlist is not as powerful as direct synchronization since during direct synchronization
components on both the schematic and PCB is issued with a unique ID (UID). By using UIDs, the
designators are not required as the synchronization link and can be changed at will on both sides.
5.3.1 Loading a netlist

To load a netlist:
• Select the Project » Show Differences menu command. This displays the Choose
Documents to Compare dialog.
• Enable the Advanced check box, as shown in Error! Reference source not found.4.
Figure 23. Advanced mode chosen in the Choose Documents to Compare dialog
• Select the required Netlist on one side and the PCB on the other. The Netlist must either be
open in Altium Designer or included in the Project.
• When you click OK, the Confirm dialog will indicate that it is unable to match using UIDs. Click
Yes to proceed using designators to match by.
• The Difference dialog will appear from where the process is the same as direct
synchronization.

5.4 Exercise – Transferring the design
In this exercise, you will transfer the design data from the schematic into the new PCB that you
have created. This means that all required footprints must be present in available libraries. Keep
these points in mind:
• Footprints that are in your project PcbLib are automatically available
• For components placed from an integrated library, such as the PIC Microcontroller, the default
state is to only look for the footprint in that integrated library, so it must be available during
design transfer.
To transfer the design:
1. In the Libraries panel, click the button to open the Available Libraries dialog. This
dialog shows all libraries that are currently available to you.
2. Confirm that the Temperature Sensor.PcbLib is listed in the Projects tab.
3. In the Installed tab, confirm that the following libraries are installed:
• Microchip Microcontroller 8-Bit PIC16 2.IntLib
• ON Semi Power Mgt Voltage Regulator.IntLib.
• Chip Resistor - 2 Contacts.PcbLib (for the 0805 footprint, the library is in the
\Library\PCB sub-folder)
4. The 2 default libraries must also be installed, Miscellaneous Devices.IntLib and
Miscellaneous Connectors.IntLib. If these have been uninstalled, they can be found
in the root of the \Altium Designer 6\Library folder.
5. Select Design » Import Changes from Temperature Sensor.PrjPCB from the PCB editor
menus. The ECO dialog displays, listing all the changes that must be made to the PCB so
that it matches the schematic. Note that you do not need to open the schematic sheets, this is
handled automatically.
6. Scroll down through the list of changes, they should include adding 20 components, 22 nets,
5 component classes, 1 net class and 3 design rules. Click on Validate Changes to check
the changes are valid.
7. Click on Execute Changes to transfer the design data. Close the ECO dialog.
8. The components will be placed on the new PCB, positioned to the right of the board outline.
9. Save the board.
Note: If you did not complete the exercises during the Environment & Editor Basics, Creating
Components or the Schematic Capture sessions, you can copy the following project and
schematic documents (located in the Training\Backup folder) to the Temperature Sensor
folder and then complete this exercise:
- Temperature Sensor.PRJPCB
- Temperature Sensor.SchDoc
- MCU.SchDoc
- Sensor.SchDoc

6. Setting up the PCB layers
6.1 Enabling Layers

The PCB Editor has a concept of design layers to represent the various physical layers created to
fabricate a printed circuit board. When placing objects using the PCB Editor, you need to consider
which layer they are to be placed on. Objects are placed on the current layer, shown as the active
layer tab at the bottom of the PCB workspace.
• Electrical layers are added in the Layer Stack Manager dialog (Design » Layer Stack
Manager).
Figure 24. Define the required electrical layers in the Layer Stack Manager dialog.
• Layer display and the control of other non-electrical layers are done in the Board Layers and
Colors dialog (Design » Board Layers & Colors).
Figure 25. Control the display of layers in the Board Layers and Colors dialog.

• The current layer (the layer you are placing on) is set by any of the following:
1. Clicking on the appropriate Layer tab at the bottom of the workspace,
2. Pressing the * key to toggle to the next copper layer,
3. Pressing the + or – keys on the numeric pad to move up or down to the next layer.
6.2 Layer definitions

Each of the PCB Editor layers is described below.
Signal Layers
There are 32 signal layers that can be used for track placement. Anything placed on these layers
will be plotted as solid (copper) areas on the PCB. As well as tracks, other objects (e.g. fills, text,
polygons, etc.) can be placed on these layers. The signal layers are named as follows:
Top Layer Top signal layer
MidLayer1 to MidLayer30 Inner signal layers
Bottom Layer Bottom signal layer
Signal layer names are user-definable.
Internal Planes
Sixteen layers (named Internal Plane 1–16) are available for use as power planes. Nets can be
assigned to these layers and multi-layer pads and vias automatically connect to these planes.
Plane layers can be split into any number of regions, with each region being assigned to a
different net. Nested split planes are supported. Internal Plane layer names are user-definable.
Internal planes are designed and output in the negative, objects that are placed on the plane
define regions of no copper.
Silkscreen layers
Top and Bottom Overlay (silkscreen) layers are typically used to display component outlines and
component text (designator and comment fields that are part of the component description).
Mechanical layers
Sixteen mechanical drawing layers are provided for fabrication and assembly details, such as
dimensions, alignment targets, annotation or other details. Mechanical layer items can be
automatically added to other layers when printing or plotting artwork. Mechanical layer names are
user-definable. Mechanical layers can also be paired; use this when creating library components
that require side-of-board layer-related information, such as glue dots.
Solder Mask
Top and bottom Solder Mask layers are provided for creating the artwork used to make the solder
masks. These automatically generated layers are used to create masks for soldering, usually
covering everything except component pins and vias. You can control the expansions for these
masks when printing/plotting by including a Solder Mask Expansion rule, or the manual override
feature in the pad/via dialogs. Refer to the Design Rules section for more information on the
Solder Mask Expansion rule. User-defined openings in the mask can also be created by placing
design objects directly on the mask layer. These layers are designed in the negative, the visible
objects become openings in the mask.
Paste Masks
Top and bottom Paste Mask layers are provided to generate the artwork which is used to
manufacture stencils to deposit solder paste onto surface mount pads on PCBs with surface
mount devices (SMDs). The size of the paste deposit is controlled by Paste Mask Expansion rule,

refer to the Design Rules section for further information. It can also be defined using the manual
override in the pad/via dialog, or by placing objects manually on the paste mask layer.
Drill Drawing
Coded plots of board hole locations are typically used to create a drilling drawing that shows a
unique symbol for each hole size at each hole location. Individual layer pair plots are provided
when blind/buried vias are specified. Three symbol styles are available: coded symbol;
alphabetical codes (A, B, C etc.) or the assigned size.
Drill Guide
A drill guide plots all holes in the layout. Drill guides are sometimes called pad masters. Individual
layer pair plots are provided when blind/buried vias are specified. These plots include all pads and
vias with holes greater than zero (0) size.
Keep Out layer

This layer is used to define the regions where components and routes can validly be placed. For
example, the board boundary can be defined by placing a perimeter of tracks and arcs, defining
the region within which all components and tracks must be placed. No-go areas for components
and tracks can be created inside this boundary by blocking off regions with tracks, arcs and fills.
Keepouts apply to all copper layers. The basic rule is that components cannot be placed over an
object on the Keep Out layer and routes cannot cross an object on the Keep Out layer.
Note that there are also layer-specific keepouts, each standard design object has a keepout
attribute, and when this is enabled the object behaves as a layer-specific keepout and is
automatically excluded from Gerber and ODB++ output generation.
Multi-layer
Objects placed on this layer will appear on all copper layers. This is typically used for through-
hole pads and vias, but other objects can be placed on this layer.
System section
The options described below cannot have objects placed on them but they are turned on or off in
the System Colors section of the Board Layers & Colors dialog.
DRC Errors
This option controls the display of the Design Rule Check (DRC) error marker.
Connections
This option controls the display of the connection lines. The PCB Editor displays connection lines
wherever it locates part of a net that is unrouted.
Pad and Via Holes

Controls the display of pad and via holes. To be able to distinguish pads from vias in draft mode,
pad holes are outlined in the current Pad Holes color.
Visible Grids
Controls the display of the two visible grids.

6.2.1 Exercise – Configuring the layer display
To confirm that the required layers are displayed:
1. Press the L shortcut key to display the Board Layers and Colors dialog.
2. Click the Used On button, to display all layers that have objects on them.
3. Confirm that the Connections and From Tos check box is enabled.
4. Note that mechanical layer 16 is linked to the sheet, this layer contains all the objects used to
create the sheet template.
6.3 Defining the Electrical Layer Stackup

The number and order of electrical layers is defined in the Layer Stack Manager dialog.
Figure 26 Layer Stack Manager dialog
The Layer Stack Manager allows you to visualize the ‘stack up’ of your PCB, i.e. the relationship
between copper, substrate and Prepreg. A picture of your layer stack can be copied to the
Windows clipboard and pasted into project documentation by right-clicking and selecting Copy to
Clipboard.
6.3.1 Adding layers

Adding a Signal or Plane layer
Use the buttons on the right to add signal and plane layers to the board. The new layer is added
below the layer selected in the dialog (unless the selected layer is the Bottom Layer). You can
also right-click to add new layers. Typically PCBs are fabricated from an even number of layers;
these can be any mix of signal and plane layers. Double-click on the layer name to define the
layer name, the copper thickness and assign the net name for plane layers.
Adding Insulation layers

As additional layers are added to the PCB, insulation layers are automatically added. The
insulation layer can be either Core or Prepreg and this is determined by the Stack Up style
setting.
6.3.2 Working with layers

Editing layer properties
Double click on a layer name to edit the layer properties, including the name and the physical
properties.

Deleting a layer
To delete a layer, click on the name text of an existing layer and then click on the Delete button,
or right-click and choose Delete from the right-click menu.
Editing the Stack Up order

To change the order in which layers are defined in your PCB, click on the name of the layer and
click on the Move Up or Move Down buttons, or right-click and choose Move Up or Move Down.
Editing the Stack Up style

The Stack Up style defines the order in which the PCB substrate, copper and prepreg insulation
layers are fabricated as well as the finish on the PCB. The style is selected in drop down list in the
top right corner of the Layer Stack Manager. The choices are:
• Layer Pairs
• Internal Layer Pairs
• Build Up.
The board finish is defined by selecting the buttons next to the Top and Bottom Dielectric check
boxes. Click on these to set the material, thickness and dielectric constant for the finish.
6.3.3 Where the physical properties are used

The physical properties that are defined in the different layer dialogs, including insulation type,
thickness and dielectric constant, and the copper thickness, is used by the signal integrity
analysis feature.
6.3.4 Drill pairs

The term drill pairs refers to the two layers that a drilling operation starts from and finishes at. By
default, one Top-Bottom drill pair is defined. If blind or buried vias are to be used on your PCB,
layer pairs must be defined for these. Click on the Drill Pairs button in the Layer Stack Manager
to display the Drill Pair Manager.
Figure 27 Define the drill pairs if the board uses blind/buried vias

6.4 Defining Mechanical layers
Mechanical layers are added to the PCB workspace in the Board Layers and Colors dialog.
Before a Mechanical layer can be used, it must be enabled.
• To enable a new layer first disable the Only show enabled mechanical layers check box.
This will result in all layers being listed. Enable the new layer, then turn the Only show
enabled mechanical layers on again.
• To edit a mechanical layer name, click to select the name and press F2 to edit it.
Figure 28. Setting up Mechanical Layers in the Board Layers & Colors dialog.
• The Show check box allows you to control the display of a mechanical layer.
• When checked, the Display In Single Layer Mode check box causes that layer to be
displayed when Single Layer Mode is invoked (SHIFT+S).
• Check the Linked to Sheet check box to relate a mechanical layer to the white sheet object.
Related mechanical layers are then hidden when the Display Sheet option is disabled (Board
Options dialog). They are also used to determine the extents of the sheet when the Auto-
position sheet option is chosen in the Board Shape sub-menu.
6.5 Internal power planes

The PCB Editor allows for up to sixteen power planes. These planes are defined in the negative,
so that objects placed become regions of no copper.
6.5.1 Defining an internal power plane

• An internal power plane is added, named and assigned to a net using the Layer Stack
Manager. When a net has been assigned to an internal plane layer, pins in that net
automatically connect to that plane layer using thermal relief connections.
• Double-click on the plane in the Layer Stack Manager, or in the workspace to assign the net.
The PCB Editor automatically connects pins that belong to the power plane net and isolates all
other pins from the plane.
• The style of plane connections is defined in the Power Plane Connect Style design rule. Nets
that are not connected to the plane are isolated from it by a clearance that is defined in the
Power Plane Clearance rule.
• The pullback, or region of no-copper required around the edge of the PCB, is defined in the
Edit Layer dialog. Double-click on the plane in the Layer Stack Manager to display this dialog.

6.5.2 Defining a split power plane
• Internal power planes can be split and shared amongst multiple nets.
• A plane is split by placing objects (typically lines) to divide it into separate regions (select
Place » Line). As soon as you stop placing lines on a plane. the layer is analyzed and each
separate split region detected.
• The width of the placed lines defines the clearance between the split regions. Press the TAB
key during line placement to change this width.
• Double-click on a split region to assign it to a net. Alternatively, set the display mode of the
PCB panel to Split Plane Editor.
• Splits can be created completely within another split region.
Figure 29. Split planes on an Internal plane layer with the Split Plane dialog showing the net assignment for
the large split region (Peak Detector With Banking.PcbDoc).
6.5.3 Re-defining a split plane

A split plane is defined by the set of objects that make up its boundary. Move and modify these to
redefine the split plane.
6.5.4 Deleting a split plane

Delete the split boundary lines to delete a split plane.

6.6 Exercise – Setting up layers
1. Set up the layers in the Layer Stack Manager. Select layer names, right-click and set the
properties, i.e. names and copper thickness. Note that you can use the buttons to add and
delete layers and move them up and down in the stack.
2. Open the Board Layers and Colors dialog and select the layers you need to show in the
design window, e.g. Top and Bottom layers, Keep-Out Layer, Drill Drawing, Multi Layer and
Top Overlay.
3. Show and enable Mechanical layers 1, 4 and 16. Make sure the Only Show enabled
mechanical layers are deselected first to show all mechanical layers available. Then turn this
option on again when you have set up the layers you wish to use. Link Mechanical 16 to the
sheet so that the title block of the template will appear on this layer.

7. Design rules and design rule checking
In Altium Designer, design rules are used to define the requirements of your design. These rules
cover every aspect of the design – from routing widths, clearances, plane connection styles,
routing via styles, and so on. Rules can be monitored as you work and you can also run a batch
test at any time and product a DRC report.
Altium Designer design rules are not attributes of the objects; they are defined independently of
the objects. Each rule has a scope that defines which objects it must target.
Rules are applied in a hierarchical fashion, for example, there is a clearance rule for the entire
board, then perhaps a clearance rule for a class of nets, then perhaps another for one of the nets
in that class. Using the rule priority and the scope, the PCB Editor can determine which rule
applies to each object in the design.
This section describes how design rules are defined and how to check for design rule violations.
7.1 Adding design rules

Design rules are defined in the PCB Rules and Constraints Editor dialog that is displayed by
selecting Design » Rules.
Figure 30. PCB Rules and Constraints Editor dialog.
To set up a design rule:

1. Click on the to expand the required rule category in the tree on the left.
2. Click on the next to the rule kind to display the rules of that kind that have been defined.
Notice how in Figure 30 the tree is expanded to show the four Width rules.
3. Click on a specific rule to display the properties of that rule.
4. Right-click on a rule kind to add a new rule of that kind.

• You can use the PCB panel to see the objects targeted by a rule. To do this, set the panel
display mode to Rules, then click on a rule in the list.
• Alternatively, right-click on an object in the workspace and select Applicable Rules to work
out what rules are being applied to an object.
7.2 Design rules concepts

To effectively apply the design rules, the concepts of rule type, object set, query and priority need
to be understood.
7.2.1 Rule type

There are two types of design rules – unary and binary.
Unary design rules

These apply to one object, or each object in a set of objects. For example, Width Constraint.
Binary design rules

These apply between any object in the first set to any object in the second set. Binary rules have
two object set sections that must be configured. An example of a binary rule is the Clearance rule
– it defines the clearance required between any copper object in the first set and any copper
object in the second set, as identified by the two rule queries.
7.2.2 Object set

This refers to the group of objects that the rule applies to. The scope of the object set is
determined by the rule Query.
Figure 31. The scope of the rule defines the objects it targets. This rule targets the 3V3 net.

7.2.3 Rule Query
The Query is a description of
the objects that this rule
applies to. The Query can be
typed in directly, it can be
constructed automatically
using the controls on the left
of the Full Query edit field, or
it can be constructed using
the Query Builder.
For more information on
queries, refer to the article,
An Insiders Guide to the
Query Language.
7.2.4 Query errors Figure 32. Use the Query Builder to construct the rule query.
If you are typing the query in

and you make a mistake, for example, you leave off a bracket, a message will appear warning
that there are errors when you attempt to close the Rules dialog. It is important to resolve these
errors, as if you do not, the on-line DRC can become very slow. Rules that have a query error
have their name displayed in red in the tree on the left of the dialog.
7.2.5 Setting the rule priority

The priority, or order that the rules are tested to determine the applicable rule, is user-defined.
When a new rule is added it is automatically set to the highest priority for rules of that kind. It is
essential that the priority is set appropriately for them to be applied correctly.
Figure 33 After adding a rule, make sure that the priority is appropriate
In Figure 33 a routing via style rule for the bus D[0..7] has been added (RoutingVias_DBus). Note
that it has a rule priority of 1 (the highest priority). If it had a priority lower than the RoutingVias
rule, which has a scope of All, it would never be applied.

7.3 How rules are checked
Design rules are checked by the Design Rule Checker (DRC) either online as you work or as a
report (batch). The report option is usually run as a final verification check when the board is
completed. Refer to 7.8.1 Design Rules Check report for more information on Batch DRC.
7.3.1 Online DRC

If the Online DRC option is turned on, all DRC violations are marked as you create them. This is
especially helpful when manually routing to immediately highlight clearance, width and parallel
segment violations.
Checking the Online DRC check box in the General page of the Preferences dialog (Tools »
Preferences) turns on the Online DRC.
Each rule is then enabled for online and batch DRC checking in the Online tab of the Design Rule
Checker dialog shown in Figure 34. This dialog is displayed by selecting the Tools » Design
Rule Check menu command. Enable each rule that you want to have automatically monitored as
you are working.
The DRC errors display in the color set in the Board Layers and Colors dialog when the Show
checkbox is enabled.
Figure 34. DRC Report Options in the Design Rule Checker dialog.

7.4 Where rules apply
7.4.1 Routing rules
Rule Class Manual Auto Online Batch DRC Other

Route Route DRC
Clearance Constraint Y Y Y Y Place Polygon
Routing Corners Specctra DSN export
Routing Layers Y
Routing Priority Y
Routing Topology Y
Routing Via Style Y Y
SMD Neckdown Y Y Y
Constraint
SMD To Corner Constraint Y Y
SMD To Plane Constraint Y Y
Width Constraint Y Y Y Y
7.4.2 Manufacturing rules
Rule Class Auto Online Batch Output Other

Route DRC DRC Generation
Acute Angle Constraint Y Y
Hole Size Constraint Y Y
Layer Pairs Y Y Manual route
Minimum Annular Ring Y Y
Paste Mask Exp Y
Polygon Connect Style Place Polygon
Power Plane Clearance Y Y Internal Planes
Power Plane Connect Y Y Internal Planes
Style
Solder Mask Exp Y
Testpoint Style Y Y Y Y Find Testpoint
Testpoint Usage Y Y Y Y Find Testpoint

7.4.3 High Speed rules

Daisy Chain Stub Length Y Y
Length Constraint Y Y
Matched Length Nets Y Y Equalize Net Lengths
command
Maximum Via Count Y Y
Parallel Segment Y Y
Vias Under SMD Y Y
7.4.4 Placement rules

Component Clearance Y Y Cluster Auto Placer
Constraint
Component Orientation Cluster Auto Placer
Nets To Ignore Cluster Auto Placer
Permitted Layers Cluster Auto Placer
Room Definition Y Y Arrange within room
7.4.5 Signal Integrity rules

All Signal Integrity rules apply only to Signal Integrity Analysis and Batch DRC.
7.4.6 Other design rules

Short Circuit Constraint Y Y
Unconnected pin Constraint Y
Unrouted Net Constraint Y Y

7.5 Object classes
7.5.1 Defining classes

Classes are provided to enable various commands to operate on sub-sets of object types, e.g. a
group of components or a group of nets. Any object of a particular type can belong to more than
one class.
Commands will operate on a class if a design rule for that class has been defined.
Classes can be created for:
• nets
• components
• pads
• from-tos
• layers.
To create an object class, select Design » Classes. This displays the Object Class Explorer
dialog shown in Figure 35 below.
Click on the class type of the class you want to create, right-click and select Add Class. A new
class will appear in the list with the default name of New Class. Click on the class name to edit
the class and add the members, right-click on the class name and select Rename Class to
rename it. Note that there are transfer buttons for selected objects; often it is easier to select the
objects in the workspace first, then use these transfer selected buttons to build the class.
Figure 35. Use the Object Class Explorer to create and manage Object Classes.
Objects in the PCB document can be selected by class in the PCB panel.

7.5.2 Component Class Generator
The Edit Component Class dialog includes the Class Generator button, which, when clicked,
displays the Component Class Generator dialog. This allows you to quickly create a component
class containing components based on selected properties.
7.6 From-tos
The PCB Editor allows commands to operate on a particular pin-to-pin connection in a net, in a
different manner to the rest of the net. A specific pin-to-pin connection is defined as a from-to.
Commands will operate on a from-to if a design rule for that from-to has been defined.
From-tos are created using the From-To Editor. Select From-To Editor in the PCB panel to
display this editor.
The top region of the panel lists all nets in the design. Click on a net to list that nets nodes in the
Nodes on Net region of the panel. When you click on any two nodes in the net (use CTRL+Click
to multi-select), the Add From To button will be enabled. When this is clicked, the new from-to
will appear in the From-Tos on Net section of the panel.
The Generate button allows you to create from-tos for a complete net in the pattern of the
selected topology.
7.7 Exercise – Setting up the design rules

This exercise looks at setting up the required design rules.
1. Create a Net Class called Power, which includes the following nets: 3V3, 5V and GND. To
do this:
- select Design » Classes
- right-click on Net Classes in the tree on the left and select Add Class.
- click on the New Class entry that is added to the list, and press F2 to rename the class.
- add the class members and close the dialog.
2. Confirm that the basic clearance constraint design rule is set to 8mils.
3. Add a second clearance constraint to keep polygons at least 15mils from other copper
objects. To do this:
- add a second clearance constraint rule
- for the First Object Matches query, type in the query InPolygon
- leave the Second Object Matches query as All
- set the minimum clearance to 15mils
- set the rule name to Clearance_Polygon.
4. Confirm that basic Board scope width constraint is set to 8 mils (all three settings).
5. The three power nets on the schematic included parameter set objects that defined the width
rule required for these nets. Confirm that a width constraint has been created for each of
these nets with a width of 15 mils.
6. Edit the Routing Via Style design rule, setting the via diameter to 35 and the hole size to 22
(all three settings).
7. Add a new routing via style for the Power class of nets with settings of Via diameter = 40 and
a hole size of 25. Name this rule RoutingVias_Power.
8. Save the board.

7.8 Design Rule Checking
• The Design Rules Checking (DRC) functions are provided to check that your design conforms
to the design rules.
• There are both Online and Batch DRC functions. See 7.3.1 Online DRC for more information
about Online DRC.
• A design should only be submitted for manufacturing when all DRC violations have been
resolved.
• DRC violations can be located using the Violations section when the PCB panel is set to
display the Rules.
7.8.1 Design Rules Check report

The DRC report is often referred to as the Batch DRC. This performs design rules checks based
on the options selected and marks any violations found. Selecting the Tools » Design Rule
Check menu command runs the DRC. This displays the Design Rule Checker dialog shown in
Figure 36.
Figure 36. Report Options in the Design Rules Checker dialog
The Rules to Check sections of this dialog enables you to select which design rules the DRC will
check for violations. Click on the Run Design Rule Check button to start a DRC check on the
PCB. A report (.DRC) is generated and displays in the Text Editor if the Create Report File option
is enabled.

7.8.2 Locating design rule violations
The following features are provided to locate and interpret DRC violations:
• Violations section in the PCB Editor panel. When the panel is set to display Rules, select [All
Rules] in the Rule Class section of the panel to list all violations. Click once on a violation to
display it (and mask all other objects). Double-click to open the Violations Details dialog.
• The Message panel. This panel lists all violations detected in the design. Double-clicking on
most message types will jump you to the violation (but will not mask like using the panel).
• The DRC report. This report is generated if the Create Report File option is enabled in the
Design Rule Checker dialog.
• The right-click Violations menu entry. Right-click on a violation and select Violation to display
information about the violations on that object, select a violation entry to open the Violation
Details dialog.
7.8.3 Exercise – Running a DRC

In this exercise, you will run a Design Rule Check (DRC) to check for PCB design violations.
1. Run a DRC and review the violations in the PCB panel. There should be at least three
violations as the pads in J1, the power connector, have holes that are larger than the
maximum permitted by the default hole size constraint rule.
2. Change the rule to suit the requirements of the connector and re-check the board.
3. Note that the Unrouted Net design rule is used to check for nets that have not been
completely routed, if your board is not routed yet you should disable checking of this rule in
the Design Rule Checker dialog.
4. Save the board.
Note: Make sure that all used layers are on when you are trying to resolve design rule violations.
You should also be aware that the DRC stops after 500 errors (default value).

8. Component Placement tools
8.1 Placing components

Component footprints can be placed on a PCB board manually from the PCB libraries.
Alternatively, they are placed to the side of the board when the Synchronizer is run from a
schematic document, ready for moving to their correct locations.
8.1.1 Adding libraries

• For component footprints to be placed, they must be available in a library. Footprint libraries
can be made available by including them in the project, installing them in the Libraries panel,
or defining a search path to their location. Libraries are searched in the order just mentioned.
Installed and search path libraries can have their search order defined.
• Click the Libraries button at the top of the Libraries panel to install a footprint library.
• Search paths are defined in the Project Options dialog.
• Footprint libraries included with Altium Designer are located in \Program Files\Altium
Designer 6\Library\Pcb.
8.1.2 Placing a Component

• Component footprints can be placed in a PCB document from any open footprint library by
double-clicking on the name in the Libraries panel, using the Place button on the panel, or
using the Place » Component command. If you use the Place » Component command, the
footprint name you type in must be in an available library.
• The Place Component dialog appears. Enter the designator and comment as required.
• During placement, the component may be moved, rotated (press SPACEBAR) or swapped to the
bottom layer (press L).
8.2 Finding components for placement

• If you can visually locate components that you are
positioning on the board, click and hold to move them.
• Otherwise, select Edit » Move » Component (M C) and
click where there are no objects. This displays the Choose
Component dialog.
• From this list, you can select the component to be placed.
• You also select the behavior you would like – to move the
cursor to the component, the component to the cursor or
no special action.
• Another technique to finding component footprints is to
use the schematic as a reference. Select the required
component(s) on the schematics and select Tools »
Select PCB Components from the menus.
• You can also cross select from the schematic to the PCB
by holding the ALT key as you click on a component in the
Navigator panel (note the project must be compiled).
Figure 37. Choose Component dialog

8.3 Moving components
• Click and hold on a component to move it. While you are moving the component the
connection lines directly connected to it will drag with it while all other connection lines are not
displayed.
• As you move the component, connection lines are dynamically optimized so that every
connection line is following the shortest path to any other object with the same net name.
• Also, while you are moving a component, pressing the N key will toggle the display of
connections.
• Pressing the L key while moving a component toggles the component between the top and the
bottom layer of the PCB.
8.3.1 Component unions

The Union feature allows you to group components together so that they can be moved as a
group, i.e. as if they were a single component.
• Multiple unions can be defined.
• To create a union of components, select the components then choose the Create Union from
selected components icon in the Component Placement tools in the Utilities toolbar.
• To remove a component from a union, or to remove the union, choose the Break Component
from Union icon from the Component Placement tools in the Utilities toolbar. This displays a
dialog that lists all components in the union. From here, select the component(s) to be
removed from the union. Selecting all components removes the union.
8.3.2 Rooms
A room is a region that defines an area where
components can either be kept within or kept out.
• Rooms are placed using the commands in the
Design » Rooms sub-menu, or using the Room
tools on the Utilities toolbar.
• A Room Definition design rule is created for each room that is placed. Once a room definition
object is placed, you define the components associated with it and whether they are to be kept
in or kept out. To do this, double-click on the room to display the Room Definition dialog. This
dialog can also be accessed in the Placement region of the Rules dialog. Set the scope of the
rule to the required component, component class or footprint.
Moving components into a room

• Components that have been assigned to a room can be automatically moved into it by
selecting the Tools » Interactive Placement » Arrange Within Room command, or clicking
the Arrange Components Within Room button in the Alignment tools in the Utilities toolbar.
You will be prompted to click on the room.
Moving rooms
• Once component(s) have been assigned to a room, they move when the room is moved. To
move a room without moving the components, temporarily disable the Room Definition rule in
the Placement section of the PCB Rules& Constraints dialog.
• If a component is moved such that it is in violation of the Room Definition rule, it is displayed
with a Design Rule Check (DRC) error marker.

Using a Room to scope another Rule
• Rooms have a dual nature in that they are defined as a rule themselves, but they can also be
used as the scope of other design rules.
• To use a room as the scope of another rule, for example to define a region where you require
larger routing clearances, you can set the Room rule to target nothing by setting its rule Query
to something like: Not IsComponent. You could then define a Routing Clearance design rule
that uses a Query something like WithinRoom(MyRoomDefinition).
8.3.3 Component Placement grid

When components are placed or moved, they snap to the Component Placement grid. This grid
has an X and a Y value and they are set in the Board Option dialog.
8.3.4 Density map

The Density Map command is provided to allow you to evaluate the quality of your component
placement. It generates a graphical display of the connection density of the PCB layout. It is
analogous to a thermal contour map. The ‘hot’ areas, which display in red, indicate areas that are
too dense to successfully route. Look at any red areas and try to create more routing space.
To display the Density Map, select the Tools » Density Map command. When you are finished
with the density map, select the View » Refresh command or the END shortcut key to display the
PCB Editor workspace.
8.4 Interactive Placement commands

There are a number of semi-automated tools that allow you to edit the placement of your PCB
design. They are accessed via the Edit » Align menu, the Tools » Component Placement
menu, or the Alignment tools in the Utilities toolbar. These are described in the following sub-
sections.
8.4.1 Alignment commands

The Alignment commands (Edit » Align) operate on
selected objects.
8.4.2 Spacing commands

Using the Spacing commands in the Alignment tools you
can make the horizontal and vertical spacing between
selected components equal, increased or decreased.
Increasing and decreasing the horizontal (or vertical)
Figure 38 Align selected objects using the
spacing for selected components means the horizontal
alignment tools.
(or vertical) distance between the component reference
points is increased (or decreased) by the amount specified in the X (or Y) component placement
grid.
8.4.3 Arrange commands

These commands automatically move components as follows:
Arrange Command Behavior
Arrange Within Room Components assigned to the nominated room are placed within
that room.
Arrange Within Rectangle Selected components are placed within a defined area.
Arrange Outside Board Selected components are moved outside the board area.

8.4.4 Move to Grid
All unlocked components are moved to the closest Component Placement grid point.
8.5 Auto Placement

Automatic Placement attempts to place all unlocked components in the PCB file. It uses the
largest enclosed shape on the Keep Out layer to determine the space available for placement.
Components will not be placed in any enclosed shapes on the Keep Out layer within the board
outline. The PCB Editor provides two options for auto placement, both using a different method of
calculating and optimizing component positions to suit different board densities. These options
are:
Cluster Placer
This auto placer group’s components into clusters based on their connectivity and then places
these clusters geometrically. The algorithms in this auto placer are more suited to designs with a
lower component count (less than 100).
Note: The Cluster Placer adheres to the Placement rules defined in the PCB Rules and
Constraints dialog.
Statistical Placer
The Statistical Placer uses a statistical algorithm to place the components in an attempt to
minimize the connection lengths. As it uses a statistical algorithm, it is best suited to designs with
more than 100 components.
8.5.1 Auto placement from a pick-and-place file

The PCB Editor can position components on the board based on the locations specified in a pick-
and-place file. This will move components that have already been loaded into the workspace to
the location specified for their designator in the pick-and-place (.PIK) format file. You should first
lock any components that are not to be moved by setting the Locked option in the Component
properties dialog.
Select Tools » Auto Placement » Place From File and enter a .PIK file name. Any components
listed in the .PIK file will have their positions updated, if different from the current position.
8.6 Re-Annotation
The PCB Editor provides the Re-
Annotation command to re-
number component designators,
so that they are numbered in
some kind of order. To do this,
choose the Tools » Re-
Annotate menu command. This
displays the Positional Re-
Annotate dialog shown in Error!
Reference source not
found.39. You select the method
by which you want the re-
annotation to be performed and
then click OK.
Figure 39. Positional Re-Annotate dialog
Alternatively, you can edit
individual component designators by double-clicking on the component.
Note: Update the Schematic with the designator changes using the Synchronizer. To do this,
select Design » Update Schematic.

8.7 Exercise – Component Placement
In this exercise, you will position the Temperature Sensor components. Use the following image
as a guide.
Figure 40. One possible component placement for the Temperature Sensor board.
1. The board does not need to be placed exactly as shown, this is only one solution.
2. As you press the spacebar to rotate components, you will notice that the designator remains
positioned above the top left of the component. This is controlled by the Designator
Autopostion option in the Component dialog. To manually position a designator, click and
drag it to the required location, pressing the spacebar to rotate it if required. To temporarily
filter out all objects in the workspace except the designators, type the query IsDesignator into
the Query editor at the top of the PCB List panel. Press Shift+C to clear this filter when
finished.
3. Each component also has a Comment string, you control the display of this in the Component
dialog. To toggle the Hide status of all comment strings, enter the Query IsComment into the
Filter panel (confirm that the Select check box is enabled in the Apply button dropdown), then
press F11 to open the Inspector. The Inspector can now be used to edit all selected Comment
strings, toggle the state of the Hide checkbox and press ENTER on the keyboard.
4. There is a placed copy of the board in the Backup folder. You can use this as a reference.
5. Save the board when you have finished but do not route it yet.

9. Routing
9.1 Interactive routing

Routing is the process of defining connective paths between the nodes in each net.
Altium Designer includes powerful Interactive Routing features to help you efficiently route your
board. There are two interactive routing commands, both are launched from the Place menu.
• Interactive Routing – you place track segments to route the selected connection. The look-
ahead feature allows you to predict the best location of the current segment. This mode also
supports loop removal, allowing you to re-route existing routing, with old redundant routing
being removed when you finish defining the new route path.
• Smart Interactive Routing – this command attempts to find a routing path from where you
started up to the current cursor location, walking around obstacles along the way. Clicking will
place all segments. Also includes auto-complete capability, where it attempts to complete the
connection from the cursor up to the far end of the connection line – hold CTRL as you click to
accept the entire path.
Once you have chosen one of the interactive routing commands, click on a connection line to
commence routing that connection. Interactive routing shortcuts can be accessed at any time
during routing by pressing the tilda key (~), or by displaying the Shortcuts panel.
9.1.1 Managing connectivity

Once components are placed into a PCB file, connection lines display to indicate which pads
belong in each net, and must be routed to create the connectivity defined in the schematic.
• Whenever there is an operation on a copper layer that affects connectivity, the PCB Editor
analyzes the PCB to determine if any connections have changed. If you have routed a
connection (joined 2 pads with track segments on a copper layer), the connection line between
those 2 pads is no longer displayed. Also, if a shorter path for any connection is possible
because of a routed connection, a shorter connection line is displayed.
• The arrangement or pattern of the connection lines in a net is called the topology. The default
topology for all nets in a board is Shortest, as determined by the applicable Routing Topology
design rule. Because it is shortest, as you move components around the connection lines may
jump from one pad in the net to another pad in the net, maintaining the shortest possible
length of connection lines for that net.
• You can change the color of the connection lines for a net in the Edit Net dialog, double click
on the net name in the PCB panel to open the dialog.
9.1.2 Interactive Routing track width

When you select one of the Interactive Routing
commands and start routing, the track width that you
start with is determined by the PCB Editor – Interactive
Routing settings in the Preferences dialog, working in
harmony with the applicable Width Constraint design
rules.
While the preferences allow you to change the width as
you route, it is always constrained by the applicable rule
– if you attempt to change it outside the range defined
by the rule it will automatically be clipped back to the Figure 41. Interactive routing behavior is
rule min or max, whichever is closer. determined by these settings.

Track Width / Via Size Mode
• User Choice – With this mode enabled the routing width is selected from the list of favorite
widths, press Shift+W while routing to display the list. Use the Favorite Interactive Routing
Widths button in the preferences dialog to configure the list.
• Rule Minimum – With this mode enabled the Minimum size setting in the applicable design
rule will be used.
• Rule Preferred – With this mode enabled the Preferred size setting in the applicable design
rule will be used.
• Rule Maximum – With this mode enabled the Maximum size setting in the applicable design
rule will be used.
Note: You can cycle between the above modes while interactive routing by pressing the 3 (for
Track Width) or 4 (for Via Size) shortcut keys, the current setting is indicated on the Status bar.
9.1.3 Editing during Routing

As well as SHIFT+W to change the track width, there is another level of editing available as you
route. Pressing the TAB key will open the Interactive Routing for Net dialog (Figure 42), where you
can configure many of the interactive routing options, as well as edit the routing width and via size
attributes.
Figure 42. Interactive Routing dialog

9.1.4 Handling conflicts during Interactive Routing
As you route interactively you will be placing track segments amongst other objects that are
already on the board. You can control how Altium Designer should handle a potential routing
conflict. The conflict resolution mode is set in the PCB Editor – Interactive Routing page of the
Preferences dialog, the applicable settings are shown in Figure 43.
Figure 43. Define how interactive routing conflicts are handled.
Conflict resolution modes include:

• None – in this mode conflicts are permitted, you can route over the top of existing objects.
Violations are highlighted.
• Stop at First Conflicting Object – in this mode the route you are placing is clipped back to
maintain clearances specified in the design rules.
• Push Conflicting Objects – If you are using the standard Interactive Routing command, in
this mode existing tracks will be pushed to make room for the new route, if possible.
• Walkaround Conflicting Object – if you are using the Smart Interactive Routing command, in
this mode the new route will walk around an existing obstacle, or jumped if possible.
Note: Press the Shift+R shortcut keys to cycle through the different modes while you are
routing, keep an eye on the status bar to see which mode you are currently in.
9.1.5 Additional Interactive Routing Options

Altium Designer’s routing capabilities have been developed to make the routing process efficient.
There are another set of options that go toward that efficiency, which are also set in the PCB
Editor – Interactive Routing page of the Preferences dialog (Figure 44).
These include:
• Restrict to 90/45 – there is a total of 5 possible routing
corner modes, cycled through as you press
SHIFT+SPACEBAR during interactive routing. Enabling this
option will restrict this list to 2, you will only choose between
90 degree or 45 degree corners.
• Auto Complete – if you are using the Smart Interactive Figure 44. Additional interactive
Routing command and this option is enabled, the smart routing options.
interactive routing engine will attempt to find a path to the target pad (shown as outlines). Hold
CTRL as you click to place these auto-complete segments.
• Automatically Terminate Routing – with this option enabled, when you click on the target
pad both the current track segment and the look-ahead segment are placed and you are
automatically released from that route, ready to start on another connection.
• Automatically Remove Loops – with this option enabled, loops that are created during
manual routing are automatically removed.
Note: Automatic Loop Removal can be disabled on an individual net if you require routing loops
in that net. Double-click on the net name in the PCB panel to access the net properties to alter
this setting.

9.1.6 Look-ahead routing
The PCB Editor’s interactive routing mode incorporates a look-ahead feature that operates as you
place tracks during routing. The track segment that is connected to the cursor is a look-ahead
segment and displays in an outline/draft style. The segment between this look-ahead segment
and the last-placed segment is the current track that you are placing, and displays in final mode.
Use the look-ahead segment to work out where you intend to place the next segment and to
determine where you wish to terminate the current segment. When you click to place the current
segment, its end point will be positioned exactly where you need to commence the next segment.
This feature allows you to quickly and accurately place tracks around existing objects and plan
where the next track segment can be placed.
As you use the look-ahead segment to guide your routing, you will notice that the track end does
not always remain attached to the cursor, it clips as you approach an existing obstacle (if the
conflict resolution mode is set to stop at first conflicting object). This feature prevents you from
violating any clearance constraints.
Note: The look-ahead mode can be toggled off and on while interactively routing by pressing the
1 key. If look-ahead is off each click will place both track segments.
9.1.7 Working with the Electrical Grid

Whenever you are placing an electrical object, like a track during routing, the Electrical grid is
active. An octagonal graphic on the cursor indicates that the Electrical Grid is in operation, pulling
the cursor to an existing object on the board. This feature is ideal for routing to off-grid pads. You
can inhibit the electrical grid if there is a situation where it is working against you, hold the CTRL
key during interactive routing to do this.
9.1.8 Changing the routing - automatically remove loops, or drag tracks

Altium Designer has 2 methods for changing existing routing:
rerouting using the Interactive Routing command, and
dragging track segments .
• Loop removal is a feature that automatically removes
redundant track segments as you re-route a connection.
Using loop removal you can easily re-route existing
routing, as soon as you terminate routing any redundant
routing is automatically removed. This includes complex
routes that pass through many layers, redundant vias are
automatically removed along with track segments.
• Dragging tracks, you can also drag track segments and
preserve the 45 angle to the adjoining track segments. To
do this first click to select the segment and the special
cursor will indicate the mode (Figure 45). Then click and
drag to move the segment. Alternatively, instead of
clicking once to select the track segment first, hold the
CTRL key as you click and drag on the segment.
Figure 45. Note the special cursor,

indicating that corner angles will be
preserved when the selected segment
is dragged.

9.1.9 Exercise – Interactive Routing
In this exercise, you will route all the connections between the LCD module (LCD1) and the PIC
microcontroller (U1).
1. Select Place » Interactive Routing and then, starting at the right-hand side of LCD1, route
the connections from the LCD1 pads to the U1 pads.
2. Attempt to route one of the power nets.
3. Try routing some of the connections using the Place » Smart Interactive Routing command.
You should explore the various options as you do, press the ~ key to display them.
4. If you are going well, route the rest of the board.
Figure 46. The placed board, ready to route.
Tips for routing

• It can help to change the connection line color for important nets. To do this, double-click on
the net name in the PCB panel.
• You can also control which connection lines are displayed by pressing the N shortcut to pop up
a display control menu.
• Disabling the display of specific layers, such as the component overlay, can also help. Press
the L shortcut to pop up the Board Layers and Colors dialog.
• Press the * key on the numeric keypad to switch to the next signal layer while routing.
• Press the CTRL+G shortcut keys to display and edit the current snap grid. 5 mils works well for
this design.
• For a 2 layer board it is generally advisable to have one layer for horizontal routing, and the
other for vertical routing.
• Press SPACEBAR during routing to toggle the start-end for the 45 degree track.
• Press SHIFT+SPACEBAR to toggle the corner mode.
• Press CTRL+Click as you click on a routed net to highlight the net. CTRL+CLICK in free space to
clear the highlight. Use the Mask Level button to control the fading.
• While routing a net, press the SHIFT+R shortcut keys to cycle the conflict resolution modes –
keep an eye on the status bar to check the current mode.

9.1.10 Differential Pair Interactive Routing
Differential signaling is fast becoming the preferred signaling interface method, driven by the ever
increasing signal speeds in electronic products. Altium Designer has excellent support for
differential signaling – from defining pairs on the schematic, through to interactive differential pair
routing on the PCB.
Differential pairs are routed as a pair – that is you route two nets simultaneously. To route a
differential pair select Place » Differential Pair Routing from the menus. You will be prompted to
select one of the nets in the pair, click on either to start routing.
Figure 47. a differential pair being routed, note that both connections in the pair are routed simultaneously.
Note: for more information on Altium Designer’s differential pair routing capabilities, refer to the
application note, Interactive and Differential Pair Routing.

9.2 Automatic routing
The Situs autorouter is a topological autorouter – it uses topological mapping to find routing paths
on a board. The Autorouter adheres to all electrical and routing design rules, except the Routing
Corners design rule. At this stage it does route differential pairs as a pair.
9.2.1 Autorouting tips

• The board must include a closed boundary on the Keep Out layer.
• Design rules must be correctly defined for the router to be able to route, it is not able to route
connections that would result in a design rule violation. Use the Setup Report in the Situs
Routing Strategies dialog to check that the rules are appropriately defined.
• Routing layer directions must be configured. Default directions are assigned, but these do not
take into consideration any existing manual routing, so they should always be checked.
Routing layer directions are configured by clicking the Edit Layer Directions button in the
Situs Routing Strategies dialog.
• You can protect pre-routed connections, fan-outs and entire nets by enabling the Lock all Pre-
routes option in the Situs Routing Strategies dialog (Auto Route » Setup). This option also
protects fan outs and partially routed connections.
• Objects with a net name that are not locked may be moved/ripped up during routing.
• Objects placed on the Keep Out layer create blocks for the router on all layers.
• Signal layer keepout objects create blocks for the router on that signal layer.
• The router does not consider objects on the mechanical layers.
• The router is sensitive to connection lines running at very shallow angles, experiment with the
alignment of components to observe this.
9.2.2 Running the Autorouter

The Autorouter requires minimal set
up. To run the router using a default
strategy, select Auto Route » All to
display the Situs Routing Strategies
dialog shown below. Simply click on
the strategy you would like to use.
Figure 48. Autorouter strategy dialog

9.2.3 Creating a Custom Routing Strategy
You cannot modify the default strategies, so to create a custom routing strategy, select Auto
Route » Setup from the menus. The easiest way to create a custom strategy is to duplicate an
existing one, for example, the Default 2 Layer Board.
As well as defining the set of routing passes, you can also control the via cost, and the router’s
tendency to route more diagonally or more orthogonally. If you enable the Orthogonal option in
the Situs Strategy Editor you should add a Recorner pass to the strategy.
Figure 49. Custom routing strategy using cheaper vias and orthogonal routing
9.2.4 Exercise – Autorouting

1. Select Autoroute » All from the menus. Select the Default 2 Layer Board strategy, enable the
Lock All Pre-routes option if you would like to keep your hand routing, and click the Route
All button.
2. Examine the routing results. To more easily check each layer, press the SHIFT+S shortcut to
toggle to single layer mode, then press the * key to toggle back and forth from top layer to
bottom layer. To highlight the routing of a particular net hold the CTRL key and click on the
net. Repeat this where there are no objects under the cursor to clear the highlight. If you have
the board in single layer mode, you can enable the Show All Primitives in Routed Net
check box in the Preferences dialog to show the routing on all layers.
3. Now reroute the board, this time using a custom strategy, as shown in Figure 49.
4. First, you need to unrouted the board, to do this use the Tools » Un-route sub menu.
5. Duplicate the Default 2 Layer Board strategy, set the More Vias slider to the left end, enable
the Orthogonal checkbox, and add a Recorner pass before the Straighten pass.
6. Autoroute the board with the custom strategy.
7. When you are happy with the routing results, save the board.

10. Polygons
• A polygon is an area of copper on a signal layer, usually connected to a net, which is poured
over existing objects, such as tracks and pads.
• A polygon can be any enclosed shape.
• A polygon maintains clearance (set in the design rules) from other copper objects.
• A polygon can be Solid or Hatched.
• A Solid polygon is built from Region objects. The advantage of this style of polygon is that
there is typically much less data to store in the PCB file, and also less data in the CAM (Gerber
or ODB++) files. Also region objects have sharp corners, so the polygon can sometimes better
fill the space between other objects.
• A Hatched polygon I built from tracks and arcs. The advantage of this style of polygon is that
the CAM processing software does not need to understand polygonal shape definitions.
• They can be placed on other layers. Polygons, however, do not pour around other objects
unless they are placed on signal layers.
10.1 Placing polygons

Place a polygon using the Place » Polygon Plane menu command or the toolbar icon. This
displays the Polygon Plane dialog in which you set up the parameters for the polygon. Once the
parameters are set up, click OK and draw the polygon plane in the workspace. Note that there are
2 different styles of polygons available:
• Solid polygon – the polygon is constructed from multiple, multi-sided region objects. This
style of polygon requires that your fabricator supports polygonal objects in Gerber or ODB++
files (most do). Using these polygons will give much smaller design files.
• Hatched polygon – the polygon is constructed with track segments and arcs.
Figure 50. Polygon Pour dialog

The parameters for Polygons are listed below.
Net Options
• Connect to Net – selects the net to be connected to the polygon.
• Pour Over options – existing polygons, or existing polygons and existing tracks within the
polygon which are part of the net being connected to can be covered by the new polygon.
• Remove Dead Copper – removes any part of the polygon that cannot connect to the plane
net.
Properties
• Layer – select the signal layer that the polygon is to be placed on.
• Min Primitive Length – Tracks or arcs below this setting are not placed when pouring a
polygon.
• Lock Primitives – if unchecked, individual objects (i.e. tracks or arcs) that make up the plane
can be deleted.
Plane Settings (Hatched and Outlines Only)

• Track Width – width of tracks that make up the polygon. If Track Width is equal to the Grid
Size, the polygon ends up as solid copper. If Grid Size is greater than Track Width, the
polygon ends up as hatched.
• Grid Size – spacing between tracks that make up the polygon.
• Surround Pads With
• Octagons – Places a track to form an octagon around pads.
• Arc – Places an arc around pads.
• Hatch Mode
• 90-Degree Hatch – Polygon is hatched with horizontal and vertical tracks.
• 45-Degree Hatch – Polygon is hatched with tracks at 45 degrees and 135 degrees.
• Vertical Hatch – Polygon consists of only vertical tracks.
• Horizontal Hatch — Polygon consists of only horizontal tracks.
Plane Settings (Solid)

• Remove Islands – remove any region that has an area less than specified.
• Arc Approximation – solid polygons use short straight edges to surround existing curved
shapes (such as pads). This setting defines the maximum allowable amount of deviation.
• Remove Necks – narrow necks that have a width less than this amount are removed.
10.1.1 Setting the polygon corner style (hatched polygon only)

As you place a hatched polygon, press the SPACEBAR to cycle through the four polygon corner
styles of any angle line, 90-degree arc, 45-degree or 90-degree line, as shown below.

10.1.2 Editing a polygon
To change any of the parameters once a polygon has been placed, double-click on the polygon,
or select Edit » Change and click on the polygon. This displays the Polygon Pour dialog where
you can change any of the parameters and then click OK. You are then prompted to re-pour the
polygon.
10.1.3 Moving a polygon

Move a polygon as you would any other object. Click, hold and move it to the next location. When
you release the mouse button, you are prompted to re-pour the polygon.
10.1.4 Editing polygon vertices

To move or insert vertices on a polygon, select the Edit » Move » Polygon Vertices command
and click on the polygon to be modified. This polygon will display handles at each vertex and a
small cross at the center point of each line segment of its border. To move a vertex, click and
drag on the handle for that vertex. To insert a vertex, click-and-hold on the cross in the line
segment and drag it to where the vertex is required.
10.1.5 Deleting a polygon

To delete a polygon, select the Edit » Delete command and then click on the polygon to be
deleted.
10.1.6 Pouring a polygon with a larger clearance

Often you will want the polygons to have a larger clearance than the standard track to track
clearances. This can be achieved by adding a new, higher priority clearance design rule, with one
of the object Queries set to InPolygon, and the rule clearance set to the required higher value.

10.2 Exercise – Working with polygons
In this exercise, you will place a polygon plane covering the top layer of the Temperature Sensor
PCB.
Figure 51. Placement of a solid polygon on the Temperature Sensor PCB.
1. Place a solid polygon on the top layer covering the entire PCB, connected to net GND, with the
Pour Over All Same Net Objects option selected.
2. Perform a final design rule check (DRC) to ensure there are no problems with your board.
Refer to section 7 to refresh your memory on checking the design rules.
3. Save the board.

11. Output Generation
All output generation settings (print, Gerber, NC drill, ODB++, CAM, report and netlist, etc) can
either be:
• Configured and stored as part of the project. If you select print, Gerber, and other outputs from
the PCB editor’s File, Design and Reports menu these output configurations are stored in the
project file.
• Alternatively you can add an Output Job file to the project and store the output setups there.
The advantage of an Output Job file is that it supports setting up multiple outputs of any kind. It
also allows multiple outputs to be generated in a single operation and can be copied from one
project to another. Any combination of output setups can be included in the job output file and
any number of job output files can be included in the project. Note that setting made in the
OutJob file are completely independent of the settings made in the PCB Editors menus.
11.1 Creating a new Output Job file

The Output Job file enables you to define all of your design output configurations - assembly,
fabrication, reports, netlists, etc - all in the one convenient and portable file. Each output setup
uses a specific data source including the entire project (all schematic sheets), an individual
schematic or the PCB.
• Select File » New » Output Job File to create a new output job configuration file. A new
output job configuration file (Job1.OutJob) is created and added to the Job Files sub-
folder of the focused project in the Projects panel. It opens as the active document in the
design window and defaults to include all possible output setups.
Figure 52. A Output Job file with three output setups defined.
• Selected setups can be deleted (CTRL+A to select all) and new outputs can be added at any
time by clicking on the required Add New Output.
• Double-click on an output to configure it in its Properties dialog, or right-click for a list of
options. The Data Source and Variants columns also have a drop-down list to choose from —
click once to select the item, then click a second time to display the down arrow and then
select from the list.

11.2 Setting up Print job options
• Select a print output from the Output Job file, e.g. Composite Drawing. Double-click to
configure this printout option in the PCB Printout Properties dialog.
Figure 53. Printout Properties dialog
• Click on the Preferences button to set the colors and layers to include in the printout.
Figure 54. PCB Print Preferences dialog
• Right-click on the print option in the Output Job file to configure which printer your output will
print to (Printer Setup) as the printouts will be sent directly to that printer when you run the
output generator.
• Right-click and select Print Preview to view your printout. From the preview window you can
copy the current Printout preview to the Windows clipboard by right-clicking and selecting
Copy. You can also save the image as an Enhanced Windows Metafile (.emf) by right-
clicking and selecting Export Metafile.

Figure 55. Print Preview window with all layers displayed
• When the printout is configured, you can run it as a batch job (if Batch is enabled) along with
all the other setups (F9), run the current output generator (SHIFT+F9) or run a selection of
output generators (CTRL+SHIFT+F9). These output options are also available in the right-click
menu. The printouts are sent to the printer.
11.3 Creating CAM files

You can setup and create manufacturing output files from the Output Job file, such as:
• Bill of Materials
• Gerber and ODB++ files
• NC Drill files
• Pick and Place files
• Testpoint Report.
The data is output into appropriate documents in a folder within the same folder as your PCB file
or in separate folders for each output type as determined in the Options tab of the Options for
Project dialog.

11.3.1 Bill of Materials
This option produces Bill of Materials reports (parts lists). Double-clicking on the Bill of Materials
report option in the Job Output file displays the Bill of Materials for Project dialog. Output format
options are Text, CSV (Comma Separated Variables) and Spreadsheet.
You can configure your BOM by rearranging the columns or export it to Excel and use Excel
templates to format your report.
Figure 56. Bill of Material setup dialog
11.3.2 Gerber
This option in the Job Output file produces a Photoplotter output in Gerber format. Double-clicking
on a Gerber Files output displays the Gerber Setup dialog. Consult your PCB manufacturer for
their preferred settings.
Figure 57. Gerber Setup dialog

11.3.3 NC Drill
This option produces a NC drill output in an industry standard format. Double-clicking on NC Drill
Files displays the NC Drill Setup dialog. Consult your PCB manufacturer for their preferred
settings.
Figure 58. NC Drill Setup dialog

11.3.4 ODB++ Output
This option produces ODB++
output, ready to load into any
ODB++ compliant CAM tool.
Double-clicking on ODB++ Files
displays the Select Layers to Plot
dialog.
11.3.5 Pick and Place

This option produces component
data that is used to program a
Pick and Place machine. Double-
clicking on Generates Pick &
Place Files displays the Pick
and Place Setup dialog.
11.3.6 Testpoint report

This option produces information
on the location and size of
Testpoints for use in fabricating
test fixtures and programming
testers.
Double-clicking on a Testpoints
Reports displays the Testpoint
Report Setup dialog.
11.4 Running the Output Generator

You can run the Output Generator to create your output files and printouts from within the Output
Job file itself (right-click menu) or use the Tools menu which includes a number of Run options.
When the Run Batch command is selected (F9) all output setups with the Batch checkbox ticked
will be generated.
You can also generate output for a selected group of outputs from within the Output Job file by
highlighting them and selecting the Run Selected command (SHIFT+CTRL+F9).
Fabrication CAM outputs can be set to open automatically in CAMtastic by enabling the relevant
options in the Output Job Options dialog (Tools » Output Job Options).
11.5 Exercise – adding an OutJob file to the project

1. With the Temperature Sensor project open, select File » New » Output Job File.
2. Save the document, naming it as Temperature Sensor.OutJob.
3. Select all the output setups (CTRLL+A), and press Delete to remove them.
4. Add in an Assembly Drawing, ODB++ and a Bill of Materials.
5. Click on the ODB++ output setup to select it, then select Tools » Output Job Options.
6. In the Output Job Options dialog, enable the ODB++ output check box and close the dialog.
7. Right-click on the ODB++ output setup and choose Run Output Generator from the menu.
The ODB++ files will be generated, a new CAMtastic document created and the ODB++
documents loaded into it. These can now be checked, panelized, and so on.

Notes:

FPGA Design
Training Module
All rights reserved. You are permitted to print this document provided that (1) the use of such is for
personal use only and will not be copied or posted on any network computer or broadcast in any
media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part,
of this document by any means, mechanical or electronic, including translation into another
language, except for brief excerpts in published reviews, is prohibited without the express written
permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local
statute. Violators may be subject to both criminal and civil penalties, including fines and/or
imprisonment.
Altium, Altium Designer, Board Insight, CAMtastic, CircuitStudio, Design Explorer, DXP, LiveDesign,
NanoBoard, NanoTalk, Nexar, nVisage, P-CAD, Protel, SimCode, Situs, TASKING, and Topological
Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or
its subsidiaries.
Corporation. OrCAD, OrCAD Capture, OrCAD Layout and SPECCTRA are registered trademarks of
Cadence Design Systems Inc. AutoCAD is a registered trademark of AutoDesk Inc. HP-GL is a
registered trademark of Hewlett Packard Corporation. PostScript is a registered trademark of Adobe
Systems, Inc. All other registered or unregistered trademarks referenced herein are the property of
their respective owners and no trademark rights to the same are claimed.
Module 5
Altium Designer Training Module FPGA Design
FPGA Design Training Module

1 FPGA Design..............................................................................................................5-1
1.1 Learning Objectives ........................................................................................5-1
1.2 Topic Outline...................................................................................................5-1
2 Introduction to FPGA Design ...................................................................................5-2
2.1 FPGAwhats???...............................................................................................5-2
3 Creating an FPGA project.........................................................................................5-3
3.1 Overview.........................................................................................................5-3
3.2 A quick word about projects and design workspaces.....................................5-3
3.3 FPGA project ..................................................................................................5-4
4 FPGA schematic connectivity..................................................................................5-5
4.1 Overview.........................................................................................................5-5
4.2 Wiring the design ............................................................................................5-5
4.3 Including VHDL in a schematic.......................................................................5-5
4.4 Establishing connectivity between documents ...............................................5-5
4.5 Using buses and bus joiners ..........................................................................5-6
5 FPGA ready schematic components.......................................................................5-9
5.1 Overview.........................................................................................................5-9
5.2 Processor cores..............................................................................................5-9
5.3 NanoBoard port plugins ................................................................................5-10
5.4 Peripheral Components ................................................................................5-12
5.5 Generic components.....................................................................................5-14
5.6 Vendor macro and primitive libraries ............................................................5-14
5.7 Exercise 1 – Create a PWM. ........................................................................5-14
6 Targeting the design ...............................................................................................5-16
6.1 Constraint files ..............................................................................................5-16
6.2 Creating a new constraint file .......................................................................5-17
6.3 Editing a constraint file..................................................................................5-17
6.4 NanoBoard constraint files ...........................................................................5-18
6.5 Configurations...............................................................................................5-18
6.6 Configuration Manager .................................................................................5-19
6.7 Exercise 2 – Configuring MyPWM................................................................5-20
7 Running the design .................................................................................................5-22
7.1 Overview.......................................................................................................5-22
7.2 Controlling the build process ........................................................................5-22
7.3 Understanding the build process ..................................................................5-23
7.4 Button regions...............................................................................................5-23
7.5 Accessing stage reports / outputs ................................................................5-24
7.6 Build stages ..................................................................................................5-24
7.7 Configuring a build stage ..............................................................................5-27
7.8 How Altium Designer interacts with back-end vendor tools .........................5-28
7.9 Exercise 3 – Run MyPWM on the NanoBoard .............................................5-28
8 Embedded instruments...........................................................................................5-29
8.1 Overview.......................................................................................................5-29
8.2 On-Chip debugging.......................................................................................5-29
8.3 CLKGEN .......................................................................................................5-30
8.4 FRQCNT2.....................................................................................................5-30
8.5 IOB_x ............................................................................................................5-30
8.6 LAX_x ...........................................................................................................5-31
i
8.7 Exercise 4 – Using embedded instruments ..................................................5-33

8.8 Where are the Instruments? .........................................................................5-36
8.9 Enabling embedded instruments ..................................................................5-37
9 Interacting with the NanoBoard .............................................................................5-38
9.1 Overview.......................................................................................................5-38
9.2 NanoBoard communications ........................................................................5-38
9.3 Technical background...................................................................................5-39
9.4 The NanoBoard controller ............................................................................5-41
9.5 FPGA I/O view ..............................................................................................5-42
9.6 Live cross probing.........................................................................................5-42
9.7 Exercise 5 – View MyPWM on the NanoBoard ............................................5-42
10 Creating a core component ....................................................................................5-43
10.1 Core project ..................................................................................................5-43
10.2 Creating a core component from an FPGA project. .....................................5-43
10.3 A word about EDIF .......................................................................................5-43
10.4 Setting up the core project............................................................................5-44
10.5 Constrain / configure.....................................................................................5-45
10.6 Creating a new constraint file. ......................................................................5-46
10.7 Creating a configuration ...............................................................................5-47
10.8 Synthesize ....................................................................................................5-48
10.9 Publish ..........................................................................................................5-49
10.10 Creating a core schematic symbol ...............................................................5-49
10.11 Using a core component...............................................................................5-51
10.12 Exercise 6 – Create a core component from MyPWM .................................5-52
11 FPGA design simulation .........................................................................................5-53
11.1 Creating a testbench.....................................................................................5-53
11.2 Assigning the Testbench Document.............................................................5-53
11.3 Initiating a simulation session.......................................................................5-54
11.4 Project compile order....................................................................................5-54
11.5 Setting up the simulation display ..................................................................5-55
11.6 Running and Debugging a Simulation ..........................................................5-56
11.7 Exercise 7 – Create a testbench and simulate MyPWM ..............................5-58
12 Review ......................................................................................................................5-59
ii
1 FPGA Design
The primary objective of this day of training is to make participants proficient in the process of
developing, downloading and running an FPGA design on the NanoBoard. We will go through the
FPGA design framework and demonstrate just how simple FPGA design is with Altium Designer.
1.1 Learning Objectives

• To be competent in developing FPGA designs using standard FPGA-based libraries and the
schematic capture environment
• To understand and be able to make use of the FPGA build process
• To be familiar with the peripheral capabilities of the NanoBoard and know how to incorporate their
use in custom FPGA designs.
• To appreciate the different communication mechanisms used by the software to control and probe
a running FPGA design.
• To be competent with the use of virtual instruments in an FPGA design.
1.2 Topic Outline

Core Topics
FPGA FPGA
FPGA Build
Project Schematic
Process
Creation Extensions
FPGA design
built and
loaded onto
NanoBoard
NanoBoard FPGA
Concepts Instruments
Advanced Topics (Time Permitting)
FPGA Core Digital

Components Simulation
Figure 1. Topic Outline for the FPGA Design training day.
5-1
2 Introduction to FPGA Design

2.1 FPGAwhats???
FPGA: Field Programmable Gate Array. Conceptually it can be considered as an array of
Configurable Logic Blocks (CLBs) that can be connected together through a vast interconnection
matrix to form complex digital circuits.
Figure 2. Exploded view of a typical FPGA
FPGAs have traditionally found use in high-speed custom digital applications where designs tend to
be more constrained by performance rather than cost. The explosion of integration and reduction in
price has led to the more recent widespread use of FPGAs in common embedded applications.
FPGAs, along with their non-volatile cousins CPLDs (Complex Programmable Logic Devices), are
emerging as the next digital revolution that will bring about change in much the same way that
microprocessors did.
With current high-end devices exceeding 1000 pins and topping 1 billion transistors, the complexity
of these devices is such that it would be impossible to program them without the assistance of high-
level design tools. Altera and Xilinx both offer high-end EDA tool suites designed specifically to
support their own devices however they also offer free versions aimed at supporting the bulk of
FPGA development. Both Altera and Xilinx understand the importance of tool availability to
increased silicon sales and they both seem committed to supporting a free version of their tools for
some time to come.
Through the use of EDA tools, developers can design their custom digital circuits using either
schematic based techniques, VHDL or a mixture of both. Prior to the Altium Designer system,
vendor independent FPGA development tools were extremely expensive. Furthermore they were
only useful for circuits that resided within the FPGA device. Once the design was extended to
include a PCB and ancillary circuits, a separate EDA tool was needed. Altium Designer has
changed all of this by being the first EDA tool capable of offering complete schematic to PCB tool
integration along with multi-vendor FPGA support.
Altium made the logical extrapolation of recent trends in the FPGA world and recognized that FPGAs
are no longer just for high-end designs. By making available a number of processor cores that can
be downloaded onto an FPGA device and bundling them with a complete suite of embedded
software development tools, Altium Designer represents a unified PCB and embedded systems
development tool. FPGAs are here to stay and Altium Designer ensures that you can make the leap
to the new world of digital integration with minimal pain.
5-2
3 Creating an FPGA project

3.1 Overview
All components that will be combined together into a single FPGA design must be encapsulated
within an FPGA Project.
The term “Project” refers to a group of documents that combine together to form a single target.
Care must be exercised when creating a project to ensure that the correct project type is selected for
the desired target.
3.2 A quick word about projects and design workspaces

To the uninitiated, Altium Designer projects can appear a little
confusing; especially when projects contain other projects.
The important thing to remember is that each project can only
have one output. If you have a design that requires several
PCBs then you will need a separate PCB project for each
PCB. If you have a design that uses several FPGAs then you
will also need a separate FPGA project for each FPGA used
on the final design.
Projects that are related together in some way can be grouped
together using a type of ‘super project’ called a Design
Workspace. Design Workspaces are simply a convenient
way of packaging one or more projects together so that all
projects from a single design can be opened together.
Altium Designer supports a fully hierarchical design approach.
As such it is possible for some projects to contain other
projects within them. Figure 3 shows a structural view of the
LCD_Keypad design that is distributed as an example in the
Altium Designer installation. From this view we can observe
the hierarchy of the different projects involved. The top-level
project is an FPGA project called LCD_Keypad and has the
filename extension PRJFPG. Within this FPGA design is an
Figure 3. An example of project hierarchy.
instance of the TSK51 embedded softcore. The program or
software that this embedded softcore executes is contained
within another project called LCD.PrjEmb. Furthermore the LCD_Keypad FPGA project also makes
use of a core component called KeyPadScanner which has been defined as a core project
(extension .PRJCOR).
The hierarchy of projects is given below.
PRJPCB PCB Project Output is a single PCB
PRJFPG FPGA Project Output is a single FPGA
Source code for a program that will execute

PRJEMB Embedded Project on a single softcore
Figure 4. Possible Project Hierarchy for a design containing multiple projects
A PCB Project may contain one or more FPGA projects but never the other way around. If you think
about it you will recognize that it is quite intuitive; a PCB contains FPGAs whereas an FPGA can’t
contain a PCB. Similarly, an FPGA could contain one or more custom FPGA cores or
5-3
microprocessor softcores. A unique Core Project will define each FPGA core component and a
unique Embedded Project will define the software that executes on each of the softcores.
3.3 FPGA project

An FPGA project should be used when the target is a single FPGA. The output of an FPGA project
will be a configuration bit file that can be used to program an FPGA.
The simplest way to create a project is from the File menu (File » New » Project).
Figure 5. Creating a new FPGA project
5-4
4 FPGA schematic connectivity

4.1 Overview
Schematic documents used in FPGA designs are converted to VHDL in the process of being
compiled into the design. This process is totally transparent to the user and does not require the
user to know anything specific about VHDL. However the VHDL conversion process does place
some requirements onto the schematic document that must be considered to ensure that the
conversion process goes smoothly and that the resultant VHDL is valid.
In this section we will discuss some of the extensions that have been added to the schematic
environment for the purposes of servicing FPGA designs.
4.2 Wiring the design

Connectivity between the component pins is created by physical connectivity, or logical connectivity.
Placing wires that connect component pins to each other creates physical connectivity. Placing
matching net identifiers such as net labels, power ports, ports and sheet entries creates logical
connectivity. When the design is compiled the connectivity is established, according to the net
identifier scope defined for the project.
Note that while the environment supports compiling projects using either a flat or hierarchical
connective structure, FPGA projects must be hierarchical.
4.3 Including VHDL in a schematic
Figure 6. Linking schematic sheet symbols to lower level documents
VHDL sub-documents are referenced in the same way as schematic sub-sheets, by specifying the
sub-document filename in the sheet symbol that represents it. The connectivity is from the sheet
symbol to an entity declaration in the VHDL file. To reference an entity with a name that is different
from the VHDL filename, include the VHDLEntity parameter in the sheet symbol whose value is the
name of the Entity declared in the VHDL file (as shown above).
4.4 Establishing connectivity between documents

Hierarchical net and bus connectivity between documents obeys the standard hierarchical project
connection behavior, where ports on the sub-document connect to sheet entries of the same name in
the sheet symbol that represents that document, as shown below.
5-5
Figure 7. Connectivity between sheet symbols and lower level documents
4.5 Using buses and bus joiners

Typically there are a large number of
related nets in a digital design. Buses
can play an important role in
managing these nets, and help
present the design in a more readable
form.
Buses can be re-ordered, renamed,
split, and merged. To manage the
mapping of nets in buses, there is a
special class of component, known as
a bus joiner. Bus joiners can be
placed from the FPGA
Generic.IntLib library (bus joiner
names all start with the letter J).
Figure 8 shows examples of using bus
joiners. There are also many Figure 8. Examples of using bus joiners
examples of using bus joiners in the
example designs in the software.
Note that apart from the JB-type joiner, all bus joiner pins have an IO direction – use the correct
joiner to maintain the IO flow. Pin IO can be displayed on sheet, enable the Pin Direction option
in the schematic Preferences dialog.
The use of bus joiners in FPGA designs is a significant departure from how bus connectivity is
established on other schematic documents however the benefits of bus joiners soon become clear.
Nets extracted from a bus joiner need not be related in any way – ie. have the same name and
differing only by number (Data[0], Data[1], Data[2], … etc). The bus joiner example above shows
how a single bus can be used to route a number of LCD and Keypad signals together. Previously
this was not possible in a bus.
4.5.1 Bus joiner naming convention

Bus joiners follow a standardized naming convention so that they can be easily found within the
FPGA Generic.IntLib library.
J<width><B/S>[Multiples]_<width><[B/S]>[Multiples]
For example:
J8S_8B: describes a bus joiner that routes 8 single wires to a single, 8-bit bus.
J8B_8S: describes a bus joiner that routes a single, 8-bit bus into 8 single wires.
J8B_4B2: describes a bus joiner that routes a single 8-bit bus into two 4-bit busses,
J4B4_16B: describes a bus joiner that routes four, 4-bit busses into a single 16-bit bus.
5-6
4.5.2 Bus joiner splitting / merging behaviour

The basic rule is that bus joiners separate/merge the bits (or bus slice)
from least significant bit (or slice) down to most significant bit (or slice).
For example, in Figure 12 U17 splits the incoming 8-bit bus on pin I[7..0]
into two 4-bit bus slices, OA[3..0] and OB[3..0]. Obeying the least to most
mapping at the slice level, the lower four bits of the input bus map to
OA[3..0], and the upper four bits map to OB[3..0]. Following this through to
the bit level, I0 will connect to OA0, and I7 will connect to OB3.
The joiner U27 merges the four incoming 4-bit slices into a 16-bit bus. With
this joiner IA0 connects to O0, and ID3 connects to O15.
4.5.3 Matching buses of different widths using the

JB-type bus joiner
Figure 9. Bus joiners
The JB-type bus joiner allows you to match nets in buses of different merge and split buses
widths. It does this via 2 component parameters, IndexA and IndexB that
map from one bus through to the other bus. These indices must be defined when you use a JB
joiner.
Figure 10. Join buses of different widths, and control the net-to-net mapping
Read the flow of nets through a JB-type bus joiner by matching from the nets in the attached bus, to
the first index on the bus joiner, to the second index in the bus joiner, to the nets defined in the
second bus net label.
Left Bus ↔ IndexA ↔ IndexB ↔ Right Bus
The rules for matching nets at each of the ↔ points are as follows:
Figure 11. An example of using the JB bus joiner to achieve sub-set mapping
• If both bus ranges are descending, match by same bus index (one range must lie within the other
for valid connections). In Figure 11 the matching is:
ADDR9 ↔ IndexA9 ↔ IndexB9 ↔ ROMADDR9, thru to
ADDR0 ↔ IndexA0 ↔ IndexB0 ↔ ROMADDR0
(In this example ROMADDR10 thru ROMADDR13 will be unconnected)
Figure 12. Using of a bus joiner for offset mapping
• In Figure 12 the matching is:

↔ IndexA15 ↔ IndexB31 ↔ PORTB31, thru
INPUTS15 to
INPUTS0 ↔ IndexA0 ↔ IndexB0 ↔ PORTB16
5-7
Figure 13. Using a bus joiner for range inversion
• If one bus range is descending and another is ascending, the indices are matched from left to
right. In Figure 13 the matching is:
INPUTS0↔ IndexA15 ↔ IndexB31 ↔ PORTB31, thru to
Figure 14. Another example of using a bus joiner for range inversion
• In Figure 14 the matching is:

↔ IndexA15 ↔ IndexB31 ↔ PORTB0, thru to
INPUTS15
5-8
5 FPGA ready schematic components

5.1 Overview
A wide variety of FPGA-ready schematic
components are included with the system, ranging
from processors, to peripheral components, down
to generic logic. Placing and wiring these
schematic components, or writing VHDL, captures
the hardware design. The FPGA-ready schematic
components are like traditional PCB-ready
components, except instead of the symbol being
linked to a PCB footprint each is linked to a pre-
synthesized EDIF model.
As well as components that you use to implement
your design, the available FPGA libraries include
components for the virtual instruments, and the
components that are mounted on the NanoBoard
and are accessible via the pins on the FPGA. The
role of each type of component is described
below.
Help for all FPGA-ready components can be
accessed by pressing the F1 key whilst the
component is selected in the library list.
5.2 Processor cores

Softcore processors can be placed from the
\Program Files\Altium Designer
6\Library\Fpga\FPGA Processors.IntLib
library. At the time of release of this manual, the
following processors and related embedded
software tools are supported:
• TSK165 – Microchip 165x family instruction set
compatible MCU
• TSK51/52 – 8051 instruction set compatible
MCU
• TSK80 – Z80 instruction set compatible MCU
• PPC405A – Embedded Power PC Core
available on some Virtex FPGAs.
• TSK3000 – 32-bit RISC processor.
There is also full embedded tool support for:
• Xilinx MicroBlaze soft core, which requires the
appropriate Xilinx device and license to use
• Xilinx Virtex-2 Pro based PowerPC 405
• AMCC PowerPC 405 discrete processor family Figure 15. The libraries panel
• ARM7, ARM9, ARM9E & ARM10E families, supported in the Sharp BlueStreak (ARM20T)
discrete processor family
5-9
5.3 NanoBoard port plugins

Hardware resources on the NanoBoard can be accessed via the use of components from the
\Program Files\Altium Designer 6\Library\Fpga\FPGA NanoBoard Port-
Plugin.IntLib library. A summary of the components is given below:
NanoBoard Port-Plugin.IntLib
Name in Library Description Symbol
ADCDAC_I2C The MAX1037 ADC converter
provides four multiplexed analogue SDA
inputs selectable by application SCL
software via the I2C connection.
AUDIO_DAC The NanoBoard provides and SPI-

based 8-bit audio codec, together AUDIO_DIN
AUDIO_DOUT
with relevant analogue pre and post AUDIO_SCLK
conditioning circuitry (Maxim part AUDIO_SPICS
number MAX1104).
CANCNTR The CAN Port is connected to a

CAN_TXD
Microchip MCP2551 CAN CAN_RXD
transceiver IC.
CLOCK_SUPPLY An SPI-based system clock CLK_BRD

generator provides a fixed 20MHz CLK_REF
CLOCK_BOARD clock (CLK_REF) and a user-
CLOCK_REFERENCE programmable clock providing CLK_BRD
frequencies from 6 to 200MHz
(CLK_BRD). CLK_REF
DAISYIN_SLAVEIO The NanoBoard can be connected in

a daisychain configuration, allowing DaisyIn0
DAISYOUT_MASTERIO multiple NanoBoard applications to
DaisyIn1
DaisyIn2
be controlled by the software. The DaisyIn3
Master and Slave I/O headers can
be used to provide an application-
defined communication resource DaisyOut0
DaisyOut1
between daughterboard applications DaisyOut2
on separate NanoBoards in a DaisyOut3
daisychain.
DIPSWITCH A standard DIP switch is wired as an ON
active low device to the NanoBoard SW[7..0]

daughter board.
1 2 3 4 5 6 7 8
KEYPAD The keypad array consists of 16 1 2 3 C

miniature pushbuttons arranged in a abc def
4 x 4 matrix. The keypad is KP_COL[3..0] 4

ghi
5
jkl
6
mno
D
organized so that a row-column KP_ROW[3..0]

7
pqrs
8
tuv
9
wxyz
E
scanning process can read the A

*+
0 B
#^
F
status of each key.

(
LED A set of 8 active high LEDs are

connected to separate pins of the
daughter board and can be driven by
LEDS[7..0]
a user application.
5 - 10
NanoBoard Port-Plugin.IntLib
MEMORY0 Two 128k x 8 static RAM devices are RAM0_DATA[7..0]
included on the NanoBoard and
MEMORY1 wired directly to I/O pins on the
RAM_CS
MEMORY256KX8 daughter board. The SRAM devices RAM_ADDR[16..0]
IDT
71V124
SA15TYI
N0108M
have a common Chip Select and RAM0_WE
Address signals but separate 8-bit RAM0_OE
data bus and Read/Write signals.
RAM0_DATA[7..0]
RAM1_DATA[7..0]
RAM_CS
RAM_ADDR[16..0]
RAM0_WE
256K SRAM
RAM1_WE
RAM0_OE
RAM1_OE
LCD The NanoBoard contains a 16-

LCD_LIGHT
character by 2-line industry standard
LCD_MEMORY0 LCD with LED backlight.
LCD_E
LCD_RW 2 x 1 6 Liquid Crysta l Display
LCD_MEMORY1 LCD_RS
LCD_DB[7..0]
LCD_MEMORY256KX8
NEXUS_JTAG_ The Nexus, or soft devices chain, is JTAG_NEXUS_TDI
JTAG_NEXUS_TDO
CONNECTOR implemented in the FPGA design by JTAG_NEXUS_TCK
the inclusion of this connector. JTAG_NEXUS_TMS
PS2A The NanoBoard features two PS2 PS2A_CLK

PS2A_DATA
ports – PS2A nominally may be used
PS2B for a keyboard and PS2B may be
used for a mouse. PS2B_CLK
PS2B_DATA
RS232CNTR A standard DTE RS232 port is RS_TX

RS_RX
provided with TXD, RXD, RTS and RS_CTS
CTS signals connected. RS_RTS
SERIALFMEMORY Two ST M25P40 low-cost 4-Mbit SPI_DOUT

SPI_DIN
serial flash RAM devices are SPI_CLK
installed as a non-volatile memory
2SP40V6
source. SPI_MODE
ST 93228
SPI_SEL
SPEAKER The NanoBoard’s magnetic audio

transducer can operate as a beeper
when driven by a square-wave signal SPEAKER
or can be pulse-width modulated to
produce more complex sounds.
SRAM_DAUGHTER0 Provision has been made for SRAM0_D[15..0]

connection of to up to two 128k x 8
SRAM_DAUGHTER1 SRAM devices placed on a
SRAM0_E
NanoBoard daughter board. SRAM0_A[18..0]

SRAM0_W
IDT
71V416
L1OPH
SRAM0_OE
SRAM0_UB
SRAM0_LB
TEST_BUTTON Although this button is labeled ‘Test’,

it has no intrinsic function and can be
TEST_BUTTON
used for any purpose by the user
application.
VGACNTR The VGA port provides a VGA VGA_R[1..0]

compatible RGB video monitor port. VGA_G[1..0]
With two-bits per color channel, the VGA_B[1..0]
VGA port is capable of representing VGA_HSYN
VGA_VSYN
64 colors.
5 - 11
5.4 Peripheral Components

Many of the hardware resources present on the NanoBoard come with peripheral modules that can
be included in the FPGA design to ease interfacing to the external port.
Peripherals can be placed from the \Program Files\Altium Designer
6\Library\Fpga\FPGA Peripherals.IntLib library.
FPGA Peripherals.IntLib
U?
CAN CAN Controller – parallel to serial interface,
CLK DATAO[7..0]
implementing a Controller Area Network RST DATAI[7..0]
serial communications bus on the serial side. DATAZ
The CAN serial bus provides high bit rate, CS
ENABLE ADDR[6..0]
high noise immunity and error detection. The WR
Controller implements the BOSCH CAN 2.0B INTI
AS INTO
Data Link Layer Protocol. The CAN controller RXD
can be used in conjunction with the CAN MODE TX0
interface hardware on the NanoBoard. TX1
TXEN
CLK_OUT
OUTCTRL[5..0]
CAN
U? U?
EMAC Ethernet Media Access Controller –
CLK INIT CLK INIT
provides an 8-bit IEEE802.3 compliant
EMAC_MD interface between a processor and a DELAY[7..0] DELAY[15..0]
EMAC_MD_W standard Physical Layer device (PHY). FPGA_STARTUP8 FPGA_STARTUP16
EMAC_W U?
CLK INIT
DELAY[31..0]
FPGA_STARTUP32
U? U?
FPGA_STARTUP8 FPGA Startup – user-definable power-up
CLK INIT CLK INIT
delay, used to implement power-on reset. An
FPGA_STARTUP16 internal counter starts on power up, counting DELAY[7..0] DELAY[15..0]
FPGA_STARTUP32 the number of clock cycles specified by the FPGA_STARTUP8 FPGA_STARTUP16
Delay pin, the output pin being asserted
U?
when the count is reached.
CLK INIT
DELAY[31..0]
FPGA_STARTUP32
U?
I2CM I2C – parallel to serial interface,
CLK SDATA_EN
implementing an Inter-Integrated Circuit (I2C) RST SDATAO
2-wire serial bus on the serial side. SDATAI
Controllers only support a single master I2C DATAO[7..0]
DATAI[7..0] SCLK_EN
serial bus system. The I2C controller can be SCLKO
used in conjunction with the I2C interface ADDR[2..0] SCLKI
WR
hardware on the NanoBoard. RD
INT
I2CM
U?
KEYPADA Keypad Controller – 4 x 4 keypad scanner
CLK_1MHZ COL[3..0]
with de-bounce. Can be used in a polled or RST
interrupt driven system. Also available in ROW[3..0]
either Wishbone or non-Wishbone variants. KEY[3..0]
VALIDKEY
The Keypad controller can be used in
KEYPADA
conjunction with the keypad on the
NanoBoard.
U?
LCD16X2A LCD Controller – easy to use controller for a
CLK LCD_E
2 line by 16-character LCD module. The LCD RST LCD_RW
controller can be used in conjunction with the LCD_RS
LCD display on the NanoBoard. DATA[7..0]
ADDR[3..0] LCD_DATA_TRI
LINE LCD_DATAO[7..0]
LCD_DATAI[7..0]
BUSY
STROBE
LCD16X2A
5 - 12
FPGA Peripherals.IntLib
U?
PS2 PS2 Controller – parallel to serial interface
CLK PS2CLKTRI
providing a bi-directional, synchronous serial RST PS2CLKO
interface between a host MCU and a PS/2 PS2CLKI
device (keyboard or mouse). The PS2 DATAO[7..0]
DATAI[7..0] PS2DATATRI
controller can be used in conjunction with PS2DATAO
either of the two sets of PS2 interface BUSY PS2DATAI
STROBE
hardware on the NanoBoard. INT
CLK_1MHZ
PS2
U?
SRL0 SRL0 – simple parallel to serial interface, full
CLK TX
duplex, single byte buffering. The SRL0 can RST RX
be used in conjunction with the RS-232
interface hardware on the NanoBoard. DATAI[7..0] RXO
DATAO[7..0]
ADDR[3..0]
WR
RD
INT
SRL0
U?
TMR3 TMR3 – dual timer unit, 16, 13 and 8-bit
CLK TA
timer/counter modes. RST GATEA
DATAI[7..0]
DATAO[7..0] TB
GATEB
ADDR[2..0] TB_OV
WR
RD
INT
TMR3
U?
VGA VGA – VGA controller that creates a simple
CLK HSYNC
method of implementing a VGA interface, RST VSYNC
presenting video memory as a flat address
space. Supports VGA and SVGA resolutions, RESOLUTION R1
CMOD[1..0] R0
and B&W, 16 and 64 color. Outputs digital DISPSIZE_H[9..0] G1
RGB and H+V sync. The VGA controller can DISPSIZE_V[9..0] G0
B1
be used in conjunction with the VGA output RD B0
on the NanoBoard. DATA[7..0]
ADDR_PIXEL[18..0]
VGA
U?
MAX1104_DAC DAC – This digital to analogue controller
CLK SPI_DOUT
module provides a simple interface to the RST SPI_DIN
MAX1104 8-bit CODEC device on the SPI_SCLK
NanoBoard. DATA[7..0] SPI_CS
MAX1104_DAC
U? U?
PRTIO1X8 PRTx – The PRTx Parallel Port Unit is simply CLK

RST
PAO[7..0] CLK
RST
PAO[7..0]
PAI[7..0]
a register interface for storing data to be DATAI[7..0] DATAI[7..0]
PRTIO2X8 transferred to/from another device in a

DATAO[7..0]
WR WR
PRTIO4X8 design. For example when used with a PRTO1X8 PRTIO1X8
U? U?
microcontroller such as the TSK80x, which CLK PAO[7..0] CLK PAO[7..0]
PRTIOX1X8 does not have any on-core port interfaces,

RST
DATAI[7..0]
PBO[7..0] RST
DATAI[7..0]
PAI[7..0]
PBO[7..0]
the unit provides a valuable new extension to DATAO[7..0] PBI[7..0]
PRTIOX2X8 the processor’s feature set.

ADDR
WR
PRTO2X8
ADDR
WR
PRTIO2X8
PRTIOX4X8 PRTOx – output only port devices

U?
CLK
RST
PAO[7..0]
PBO[7..0]
U?
CLK
RST
PAO[7..0]
PAI[7..0]
PCO[7..0]
PRTO1X8 DATAI[7..0] PDO[7..0] DATAI[7..0]

DATAO[7..0]
PBO[7..0]
PBI[7..0]
PRTIOx – I/O port devices ADDR[1..0] ADDR[1..0] PCO[7..0]
PRTO2X8 WR
PRTO4X8
WR PCI[7..0]
PRTIOXx – I/O port devices with additional PDO[7..0]

PDI[7..0]
PRTO4X8 tristate buffer enable output for each port. U?

PRTIO4X8
U?
CLK TRISA[7..0] CLK TRISA[7..0]
RST PAO[7..0] RST PAO[7..0]
PAI[7..0] PAI[7..0]
DATAI[7..0] DATAI[7..0]
DATAO[7..0] DATAO[7..0] TRISB[7..0]
PBO[7..0]
ADDR ADDR[2..0] PBI[7..0]
WR WR
TRISC[7..0]
PRTIOX1X8
PCO[7..0]
PCI[7..0]
U?
CLK TRISA[7..0] TRISD[7..0]
RST PAO[7..0] PDO[7..0]
PAI[7..0] PDI[7..0]
DATAI[7..0]
PRTIOX4X8
DATAO[7..0] TRISB[7..0]
PBO[7..0]
ADDR[1..0] PBI[7..0]
WR
PRTIOX2X8
5 - 13
5.5 Generic components

Generic components can be placed from the library
\Program Files\Altium Designer
6\Library\Fpga\FPGA Generic.IntLib. This
library is included to implement the interface logic
in your design. It includes pin-wide and bus-wide
versions for many components, simplifying the
wiring complexity when working with buses. As well
as a broad range of logic functions, the generic
library also includes pullup and pulldown
components as well as a range of bus joiners, used
to manage the merging, splitting and renaming of
buses.
For a definition of the naming convention used in
the generic library and a complete listing of
available devices, refer to the document: CR0118
FPGA Generic Library Guide.pdf.
Wild card characters can be used to filter when
searching the component library.
5.6 Vendor macro and

primitive libraries
If vendor independence is not required, there are
also complete primitive and macro libraries for the
currently supported vendors/device families. These
libraries can be found in the respective Actel,
Altera, Lattice and Xilinx sub-folders in \Program
Files\Altium Designer 6\Library\. The
macro and primitive library names end with the
string *FPGA.IntLib. Note that some vendors Figure 16. Using wildcards to quickly find a specific
component in the Generic Library
require you to use primitive and macro libraries that
match the target device. Designs that include
vendor components cannot be re-targeted to
another vendor’s device.
5.7 Exercise 1 – Create a PWM.

In this exercise we will create our first FPGA design. In order to complete this task you will need to
use the following components from their respective libraries:
1. Open a new FPGA Project. Save it as MyPWM.PrjFpg
2. Add a new schematic to your project and save it as MyPWM.SchDoc
U1
VCC
Q[7..0]
CE CEO
PXX CLK_BRD C TC
U2 CLR U3
I0 U4 O[7..0]
PXX TEST_BUTTON A[7..0] GT LEDS[7..0]
CB8CEB I1
B[7..0] LT
INV I2 PXX,PXX,PXX,PXX,PXX,PXX,PXX,PXX
COMPM8B I3
ON
I4
SW[7..0]
1 2 3 4 5 6 7 8 I5
PXX,PXX,PXX,PXX,PXX,PXX,PXX,PXX I6
I7
J8S_8B
Figure 17. Place and wire the components to create the Pulse Width Modulator
5 - 14
3. Using components from the two libraries FPGA Generic.IntLib and FPGA NanoBoard Port-
Plugin.IntLib, place and wire the schematic shown in Figure 17.
Component Library Name in Library
FPGA NanoBoard Port-Plugin.IntLib CLOCK_BOARD
PXX CLK_BRD
FPGA NanoBoard Port-Plugin.IntLib TEST_BUTTON

PXX TEST_BUTTON
ON
SW[7..0] FPGA NanoBoard Port-Plugin.IntLib DIPSWITCH

1 2 3 4 5 6 7 8
PXX,PXX,PXX,PXX,PXX,PXX,PXX,PXX
LEDS[7..0] FPGA NanoBoard Port-Plugin.IntLib LED

PXX,PXX,PXX,PXX,PXX,PXX,PXX,PXX
U1
FPGA Generic.IntLib CB8CEB
Q[7..0]
CE CEO
C TC
CLR
CB8CEB
U2 FPGA Generic.IntLib INV
INV
U3 FPGA Generic.IntLib COMPM8B

A[7..0] GT
B[7..0] LT
COMPM8B
I0 U4 O[7..0] FPGA Generic.IntLib J8S_8B

I1
I2
I3
I4
I5
I6
I7
J8S_8B
Figure 18. Save your work – we will continue with this schematic soon
5 - 15
6 Targeting the design

The schematic that we have just created contains all of the connectivity that must occur internally on
our FPGA device but we still need some further information to map the ports on the FPGA schematic
to physical pins on an actual FPGA device. This process is called targeting our design.
6.1 Constraint files

Rather than storing device and implementation specific data such as pin allocations and electrical
properties in the source VHDL or Schematic documents, this information is stored in separate files –
called Constraint files. This decoupling of the logical definition of an FPGA design from its physical
implementation allows for quick and easy re-targeting of a single design to multiple devices and PCB
layouts.
Below we see a conceptual representation of an FPGA design sitting inside an FPGA device. The
red lines indicate the port-to-pin mappings that would be handled by the constraint file.
Figure 19. Conceptual view showing the linkage of ports on an FPGA schematic routed to physical device pins.
5 - 16
6.2 Creating a new constraint file

A constraint file can be added to a project by right-clicking the FPGA project in the Projects panel
and selecting Add New to Project » Constraint File. A shell constraint file will be created.
6.3 Editing a constraint file

Constraint file additions / modifications can be made by manually editing the constraint file or by
using the Design » Add/Modify Constraint menu.
Figure 20. Add/Modify Constraint… menu options
The two main activities that will be performed on a newly created constraint file are specifying the
part (device) and applying port constraints.
6.3.1 Specifying the part (device)

The design can be constrained to a specific device by selecting Add/Modify Constraint » Part and
selecting the desired part from the Choose Physical Device dialog:
Figure 21. Choose Physical Device dialog box.
Select the Vendor, Family, Device and Temperature/Speed grades as desired and click OK. A line
similar to the one below will be automatically inserted into the constraint file:
Record=Constraint | TargetKind=Part | TargetId=XC2S300E-6PQ208C
5 - 17
6.3.2 Specifying port constraints

Use the Add/Modify Constraint » Port to
apply a constraint to a port in the FPGA
project.
Figure 22. Add/Modify Port Constraint dialog box.
Selecting OK from the dialog box in Figure 22 will cause the following constraint to be added to the
constraint file:
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_PIN=True
This constraint will ensure that the Vendor FPGA tools route the CLK_BRD port to a specialized
clock pin on the target device.
Alternatively, the FPGA_PINNUM
constraint can be specified to lock the port
to a specific pin on the target device.
Figure 23. Add/Modify Port Constraint dialog box.
Selecting OK from the dialog box in Figure 23 will add the constraint FPGA_PINNUM=P185 to the
CLK_BRD port constraint.
6.3.3 Applying further constraints

Additional constraints other than those discussed here are available. Consult the TR0103
Constraint File Reference.pdf document for more information.
To summarize:
• Constraint files store implementation specific information such as device pin allocations and
electrical properties.
• A Configuration is a grouping of one or more constraint files and describes how the FPGA
project should be built.
6.4 NanoBoard constraint files

Constraint files for use with the NanoBoard daughter board modules can be found in the \Program
Files\Altium Designer 6\Library\Fpga directory. To protect these system files from
inadvertent modification, it is advisable to make this directory ‘read only’.
6.5 Configurations
A Configuration is a set of one or more constraint files that must be used to target a design for a
specific output. The migration of a design from prototype to production will often involve several
PCB iterations and possibly even different FPGA devices. In this case, a separate configuration
would be used to bring together constraint file information for each design iteration. Each new
5 - 18
configuration (and its associated constraint file(s) ) is stored with the project and can be recalled at
any time.
Because configurations can contain multiple constraint files, it can sometimes be helpful to split
constraint information across multiple constraint files. Usually one would separate the constraint files
according to the class of information they contain:
6.5.1 Device and board constraint information:

The specific FPGA device must be identified and ports defined in the top level FPGA design must be
mapped to specific pin numbers.
6.5.2 Device resource constraint information:

In some designs it may be advantageous to make use of vendor specific resources that are unique
to a given FPGA device. Some examples are hardware multiplication units, clock multipliers and
memory resources.
6.5.3 Project or design constraint information:

This would include requirements which are associated with the logic of the design, as well as
constrains on its timing. For example, specifying that a particular logical port must be allocated to
global clock net, and must be able to run at a certain speed.
6.6 Configuration Manager

The grouping of multiple constraints into a single configuration is managed via the Configuration
Manager; accessible by right-clicking the FPGA project in the Projects panel and selecting
Configuration Manager from the menu.
Figure 24. Configuration Manager showing multiple configurations and constraint files.
Figure 24 shows the Configuration Manager dialog for a project that contains multiple configurations
and constraint files. The Constraint files are listed in the left column and can be included in a
Configuration (listed as the headings in the four right columns) by placing a tick at the row/column
intersection point. Although this example only shows one constraint file being used in each of the
configurations, there is no reason why a constraint file can’t be used by more than one configuration
nor is there any reason why a configuration can’t make use of multiple constraint files.
5 - 19
6.7 Exercise 2 – Configuring MyPWM

1. Right click on the MyPWM.PRJFPG in the Projects panel and select Configuration Manager
from the menu. The Configuration Manager should be empty as depicted in Figure 25.
Figure 25. Configuration Manager with no Constraint Files or Configurations defined.
2. Because we are targeting our design for the NanoBoard, we will be using an existing constraint
file that has been previously defined for the Spartan-II daughter board. Select the Add button
next to the Constraint Files label. The Choose Constraint files to add to Project dialog box will
be displayed. By default it should open in the Altium Designer 6\Library\FPGA directory. If it
hasn’t defaulted to this location then navigate to it.
3. Select the constraint file labelled NB1_6_XC2S300E-6PQ208.Constraint and click Open. You
should see the same as Figure 26.
Figure 26. Configuration Manager with Spartan-II daughter board constraint file present.
4. We shall now create a configuration that will make use of this constraint file. Select the Add
button located next to the Configurations label.
Figure 27. Specifying a new configuration.
5. Call the new configuration NB_SpartanIIE and select OK.

6. Click on the checkbox to link the NB1_6_XC2S300E-6PQ208.Constraint file to the
NB_SpartanIIE configuration.
5 - 20
Figure 28. Configuration Manager with a constraint file and configuration specified.
7. Select OK to close the Configuration Manager.

8. Notice how the newly added constraint file is now present under the Settings folder in the
Projects panel.
9. Save your project if you haven’t already done so.
Figure 29. Projects panel after a constraint file has been added.
5 - 21
7 Running the design

Having just configured our design for the NanoBoard the next step is to build and run the design on
the NanoBoard.
7.1 Overview
Before an FPGA design can be downloaded onto its target hardware, it must first undergo a multi-
stage build process. This process is akin to the compilation process that software undergoes in
order to create a self-contained program. In this section we will discuss the various steps necessary
to build an FPGA design to the point where it is ready to be downloaded onto the target device.
7.2 Controlling the build process

The process of converting a schematic or VHDL description of a digital circuit into a bit file that can
be downloaded onto an FPGA is quite complex. Fortunately, Altium Designer goes to great lengths
to ensure that navigation through this process is as easy as possible. As a vendor independent
FPGA development tool, Altium Designer provides a transparent interface to the vendor specific
back end tools. Currently Altium Designer supports interaction with Actel Designer (Actel), Quartus II
(Altera) and ISE (Xilinx) to perform FPGA processing. This is all handled seamlessly through the
Devices View (View » Devices). The Devices View provides the central location to control the
process of taking the design from the capture state through to implementing it in an FPGA.
Figure 30. Devices view of an FPGA design that is yet to be processed.
The Devices View is accessible by clicking the Devices View button or by selecting View »
Devices View from the main menu.
When run in the live mode, Altium Designer is intelligent enough to detect which daughter board
device is present on the NanoBoard. In the above instance, it has detected that the Spartan2E
daughter board is installed. With this information, it then searches the current project’s configuration
list to see if any configurations match this device. If more than one configuration is found, the drop
down list below the device icon will be populated with a list of valid configurations. If no configuration
can be found, the list will display the following:
Figure 31. This message indicates that the project is not configured to target the available FPGA.
5 - 22
Assuming a valid configuration can be found, the simplest way to build and download a design onto
the NanoBoard is to left-click on the Program FPGA button. This will invoke the appropriate build
processes that need to be run. In the above example where no previous builds have taken place, all
processes will need to be run. In other situations where a project has just been modified, it may be
necessary for only a subset of the build processes to run.
7.3 Understanding the build process
Figure 32. Navigating through the Build Process flow.
Building an FPGA project requires processing through a number of stages. Navigation through the
build process is accomplished via the four steps circled in Figure 32. The function of each stage will
be explained shortly.
7.4 Button regions

Each of the main buttons displayed in the Build Flow have several regions that provide information or
control over the individual build stage.
7.4.1 Status LED
The colored indicator tells you the status of that particular step in the overall build flow.
Grey - Not Available. The step or stage cannot be run.
Red - Missing. The step or stage has not been previously run.
Yellow - Out of Date. A source file has changed and the step or stage must be run again in order
to obtain up to date file(s).
Blue - Running. The step or stage is currently being executed.
Orange - Cancelled. The step or stage has been halted by user intervention.
Magenta - Failed. An error has occurred while running the current step of the stage.
Green - Up to Date. The step or stage has been run and the generated file(s) are up to date.
5 - 23
7.4.2 Run all
Clicking on the ‘arrow’ icon will force the current stage and all prior stages to run regardless of
whether they have run to completion previously. Selecting this icon will force a totally clean build
even if the design has been partially built.
7.4.3 Run
Selecting the ‘label’ region will run the current stage and any previous dependant stages that are not
up to date. This is the quickest way to build a design as it only builds those portions of the design
that actually require it.
7.4.4 Show sub-stages
Selecting the ‘down arrow’ will expose a drop down list of the various sub-stages for the current build
stage. The status of the various sub-stages is indicated by the color of the status ‘LED’. Where a
sub-stage has failed, the associated report file can be examined to help determine the cause of the
failure.
Figure 33. Sub-stages available under the main build stage.
7.5 Accessing stage reports / outputs

All generated output files are stored in a folder with the same name as the configuration used for the
associated project. This folder is located in accordance with the output path defined in the Options
tab of the Options for Project dialog (Project » Project Options). In general only files that are
created as part of the build process should be located here. This ensures that projects can be
compacted by deleting this directory without fear of loss of important information.
Where a report is available upon running a stage step, clicking on the associated icon can access
it. Use this feature to access detailed information relating to why a specific stage may have failed to
build.
7.6 Build stages

We will now explain the different stages in the build process.
7.6.1 Compile
Figure 34. Compile stage of the process flow.
5 - 24
This stage of the process flow is used to perform a compile of the source documents in the
associated FPGA project. If the design includes any microcontroller cores, the associated embedded
projects are also compiled – producing a Hex file in each case.
This stage can be run with the Devices view configured in either Live or Not Live mode.
The compile process is identical to that performed from the associated Project menu. Running this
stage can verify that the captured source is free of electrical, drafting and coding errors.
Note: The source FPGA (and embedded) project(s) must be compiled – either from the Projects
panel or by running the Compile stage in the Devices view – in order to see Nexus-enabled device
entries in the Soft Devices region of the Devices view.
7.6.2 Synthesize
Figure 35. Synthesize stage of the process flow.

This stage of the process flow is used to synthesize the compiled FPGA project, as well as any other
components that need to be generated and synthesized to specific device architectures. The vendor
place and route tools subsequently use the synthesis files generated, during the build stage of the
flow. Running this stage will determine whether the design is synthesizable or not.
This stage can be run with the Devices view configured in either Live or Not Live mode.
The actual steps involved in providing a top-level EDIF netlist and satellite synthesis model files for
use by the next stage in the process flow can be summarized as follows:
• The cores for any design/device specific blocks used in the FPGA design will be auto-generated
and synthesized (e.g. a block of RAM wired to an OCD-version micro controller for use as
external Program memory space). These synthesized models will contain compiled information
from the embedded project (Hex file).
• The main FPGA design is then synthesized. An intermediate VHDL file for each schematic sheet
in the design will be generated and a top-level EDIF netlist created using these and any additional
VHDL source files.
• For the particular physical device chosen, synthesized model files associated with components in
the design will be searched for and copied to the relevant output folder. Both System and User
presynthesized models are supported.
• The top-level folder for System presynthesized models is the \Program Files\Altium
Designer 6\Library\Edif folder, which is sub-divided by Vendor and then further by device
family.
• The top-level folder for user presynthesized models is defined in the FPGA – Synthesis page of
the Preferences dialog, accessed under the Tools menu.
• The following list summarizes the order (top to bottom = first to last) in which folders are searched
when looking for a synthesized model associated with a component in the design:
- FPGA project folder
- User models top folder\Vendor folder\Family folder
- User models top folder\Vendor folder
- User models top folder
- System models top folder (Edif)\Vendor Folder\Family folder
- System models top folder (Edif)\Vendor folder
- System models top folder (Edif).
5 - 25
7.6.3 Build
Figure 36. Build stage of the process flow for Xilinx (left) and Altera (right) devices.
This stage of the process flow is used to run the vendor place and route tools. This stage can be run
with the Devices view configured in either live or not live mode.
Running the tools at this stage can verify if a design will indeed fit inside the chosen physical device.
You may also wish to run the Vendor tools if you want to obtain pin assignments for importing back
into the relevant constraint file.
The end result of running this stage is the generation of an FPGA programming file that will
ultimately be used to programming the physical device with the design. There are essentially five
main stages to the build process:
• Translate Design – uses the top-level EDIF netlist and synthesized model files, obtained from
the synthesis stage of the process flow, to create a file in Native Generic Database (NGD) format
– i.e. vendor tool project file
• Map Design to FPGA – maps the design to FPGA primitives
• Place and Route - takes the low-level description of the design (from the mapping stage) and
works out how to place the required logic inside the FPGA. Once arranged, the required
interconnections are routed
• Timing Analysis – performs a timing analysis of the design, in accordance with any timing
constraints that have been defined. If there are no specified constraints, default enumeration will
be used
• Make Bit File – generates the programming file that is required for downloading the design to the
physical device.
When targeting a Xilinx device, an additional stage is available – Make PROM File. This stage is
used when you want to generate a configuration file for subsequent download to a Xilinx
configuration device on a Production board.
After the Build stage has completed, the Results Summary dialog will appear (Figure 20). This
dialog provides summary information with respect to resource usage within the target device.
Information can be copied and printed from the dialog. The dialog can be disabled from opening,
should you wish, as the information is readily available in the Output panel or from the report files
produced during the build.
Figure 37. Summarizing resource usage for the chosen device.
5 - 26
7.6.4 Program
This stage of the process flow is used to
download the design into the physical
FPGA device on a NanoBoard or production
board. This stage is only available when the
Devices view is configured in Live mode.
This stage of the flow can only be used
once the previous three stages have been
run successfully and an FPGA programming
Figure 38. Program FPGA stage of the process flow. file has been generated.
As the programming file is downloaded to

the device via the JTAG link, the progress
will be shown in the Status bar. Once
successfully downloaded, the text
underneath the device will change from
‘Reset’ to ‘Programmed’ (Figure 39) and
any Nexus-enabled devices on the soft
Figure 39. Successful programming of the physical FPGA device. chain will be displayed as ‘Running’ (Figure
40).
Figure 40. Soft devices running after successful program download.
7.7 Configuring a build stage

Should you wish to configure any of the specific options associated
with each of the different sub-stages in the FPGA build flow you can
do so by clicking on the appropriate configuration icon.
Consider the case where you want to generate a PROM file for
subsequent download to a Xilinx configuration device on a production
board. In the process flow associated to the targeted FPGA device,
expand the build section. The last entry in the build menu is Make
PROM File (Figure 41).
Clicking on the icon, to the far right of this menu entry, will open Figure 41. Accessing the
the Options for PROM File Generation dialog (Figure 42). From command to generate a
here you can choose the non-volatile configuration device that will be PROM file.
used by the production board to store the FPGA configuration.
Figure 42. Accessing the options dialog for PROM file generation.
5 - 27
7.8 How Altium Designer interacts with back-end vendor tools

If you are already familiar with the build flows offered by Altera and Xilinx, you will be familiar with
one or both of the following panels:
Figure 43. Xilinx (left) and Altera (right) vendor tool interfaces.
Although Altium Designer has its own VHDL synthesizer, it is reliant on back-end vendor tools to
implement the design on a specific device. This makes entire sense, as it is the device vendors who
have the most intimate knowledge of their specific devices and who have already developed well-
proven targeting technologies.
Most vendor specific tools have been developed in a modular fashion and contain a number of
separate executable programs for each phase of the implementation process. The vendor GUIs that
are presented to the user are co-coordinating programs that simple pass the appropriate parameters
to back-end, command-line programs.
When it comes to FPGA targeting, Altium Designer operates in a similar fashion in that it acts as a
coordinator of back-end, vendor-specific programs. Parameters that need to be passed from the
Altium Designer front-end to the vendor-specific back-end programs are handled by a series of text-
based script files. Users who are already familiar with the back-end processing tools may find some
use in accessing these script files should they wish to modify or ‘tweak’ interaction with back-end
processing tools. This however is considered a highly advanced topic and one that should be
handled cautiously. Ensure backups are taken prior to modification.
The files controlling interaction with vendor-specific back-end tools can be found in the System
directory under the Altium Designer 6 install directory. The naming convention used for these
files is:
Device[Options | Script]_<vendor>[_<tool> | <family>].txt
i.e. DeviceOptions_Xilinx_PAR.txt controls the default options for Xilinx’s Place and Route
tool.
7.9 Exercise 3 – Run MyPWM on the NanoBoard

In this exercise we shall take our previously developed PWM design and run it on the NanoBoard.
1. Ensure that the NanoBoard is correctly connected to the PC, the XC2S300E (Xilinx) daughter
board is loaded, and the NanoBoard is switched on.
2. Open the Devices View and ensure the Live checkbox is ticked.
3. Click on the ‘label’ region of the Program FPGA button in the FPGA Build flow. The design will
begin building and may take a moment or two to complete.
4. If any build errors occur, diagnose and rectify the error and attempt the build process again.
5. Once downloaded, verify the operation of the design by switching different DIP switches off and
on. You should notice a change in the LED illumination.
5 - 28
8 Embedded instruments
8.1 Overview
So far we have built our PWM FPGA design and run it on the NanoBoard. Fortunately this design
provided an output on the LEDs that enabled us to immediately verify that the circuit was performing
as we expected. But how do we verify other designs? In this section we will introduce the range of
embedded instruments that can be integrated into FPGA designs to facilitate on-chip testing and
debugging.
8.2 On-Chip debugging

A big concern of many embedded systems designers transitioning to FPGA based design is the
issue of debugging; how does one see inside an FPGA circuit to diagnose a fault? What these
people fail to recognize, however, is that the flexibility of FPGA devices enables typical test and
measurement virtual instruments to be wired inside the device leading to far easier debugging than
what has previously been possible.
The Altium Designer system includes a host of virtual instruments that can be utilized to gain visibility
into the hardware and quickly diagnose illusive bugs. These instruments can be found in the FPGA
Instruments.IntLib integrated library. The ‘hardware’ portion of the instrument is placed and
wired on the schematic like other components. Once the design has been built, real time interaction
with each instrument is possible from the Devices View.
Figure 44. Embedded instruments displayed in the devices view.
The controls for the individual embedded instruments can be accessed by double-clicking their
associated icon in the Devices View.
5 - 29
8.3 CLKGEN
Figure 45. Frequency generator, used to generate the specified frequency
The frequency generator outputs a 50% duty cycle square

wave, of the specified frequency. Clicking the appropriate
button can choose a number of predefined frequencies, or
a custom frequency can be selected using the Other
Frequency button. If the specified frequency cannot be
generated the closest possible is generated and the error
shown on the display. Note that when the frequency generator is instantiated in the FPGA it will not
be running, you must click the Run button to generate an output.
8.4 FRQCNT2
Figure 46. Frequency counter, used to measure frequency in the design
The frequency counter is a dual input counter that can display the measured
signal in 3 different modes; as a frequency, period, or number of pulses.
8.5 IOB_x
Figure 47. Digital IO module, used to monitor and control nodes in the design
The digital I/O is a general-purpose tool that can be used

for both monitoring and activating nodes in the circuit. It
is available in either 8-bit wide or 16-bit wide variants,
with 1 to 4 channels.
Each input bit presents as a LED, and the set of 8 or 16
bits also presents as a HEX value. Outputs can be set or
cleared individually by clicking the appropriate bit in the Outputs display. Alternatively typing in a
new HEX value in the HEX field can alter the entire byte or word. If a HEX value is entered you must
click the button to output it. The Synchronize button can be used to transfer the current input
value to the outputs.
5 - 30
8.6 LAX_x
Figure 48. The logic analyzer instrument at the top, with two variations of the configurable LAX shown below it.
The LAX component on the left has been configured to accept 3 different sets of 64 signals (signal sets), the
one on the right has one signal set of 16 bits. The Configure dialog is used to set the capture width, memory
size and the signal sets.
The logic analyzer allows you to capture multiple snapshots of multiple nodes in your design. Use
the LAX to monitor multiple nets in the design and display the results as a digital or an analog
waveform.
The LAX is a configurable component. Configure it to simultaneously capture 8, 16, 31 or 64 bits.
The number of capture snapshots is defined by the amount of capture memory; this ranges from 1K
to 4K of internal storage memory (using internal FPGA memory resources). It can also be configured
to use external memory. This requires you to wire it to FPGA memory resources or to off-chip
memory (eg, NanoBoard Memory).
After placing the configurable LAX from the library, right-click on the symbol and select Configure
from the floating menu to open the Configure (logic analyzer) dialog, where you can define the
Capture Width, Memory Size and the Signal Sets.
The Configurable LAX includes an internal multiplexer, this allows you to switch from one signal set
to another at run time, display the capture data of interest. You can also trigger off one signal set
while observing results of another set.
Note that the FPGA Instruments library includes a number of LAX components. The LAX
component is the configurable version, all others are legacy versions.
5 - 31
8.6.1 Waveform display features
Figure 49. Digital waveform capture results from the logic analyzer
Figure 50. Analog waveform capture results from the logic analyzer
The capture results are displayed in the instrument panel. There are also two waveform display
modes. The first is a digital mode, where each capture bit is displayed as a separate waveform and
the capture events define the timeline. Note that the capture clock must be set in the logic analyzer
options for the timeline to be calculated correctly. Click the Show Digital Waves button to display
the digital waveform.
The second waveform mode is an analog mode, where the value on all the logic analyzer inputs is
displayed as a voltage, for each capture event. The voltage range is from zero to the maximum
possible count value, scaled to a default of 3.3V. Click the Show Analog Waves button to display
the analog waveform.
8.6.2 Zooming in and out

In both the analog and digital waveform viewers it is possible to zoom in and out by hitting the Page
Up or Page Down keys respectively
8.6.3 Continuous display mode

Waveforms captured by the logic analyzer can be displayed as a single pass or as a continuously
updated display. Continuous updates can be enabled / disabled from the logic analyzer toolbar.
Figure 51. Enabling the continuous capture mode.
5 - 32
8.7 Exercise 4 – Using embedded instruments

A working design of a PWM circuit complete with embedded instruments has been prepared to
illustrate the features of FPGA instruments. Your instructor will tell you where to find it on your local
hard drive.
U5
CLK_BRD
P182 CLK_BRD CLK_BRD
CLK STATUS
CLK_TICK
CLK_CAP
IA[7..0] U6 O[15..0]
CHANNELS[15..0]
U7 VCC
CLK_BRD U1 IB[7..0]
TIMEBASE FREQ TRIGGER
Q[7..0] J8B2_16B
Frequency Generator Logic Analyser

CLKGEN CE CEO
CLK_TICK LAX_1K16
C TC
U2 CLR U3
I0 U4 O[7..0]
P3 TEST_BUTTON A[7..0] GT LEDS[7..0]
CB8CEB I1
B[7..0] LT
INV I2 P55,P56,P57,P58,P59,P60,P61,P62
U8 COMPM8B I3
I4
AIN[7..0] AOUT[7..0]
I5
I6
1 Ch x 8 Bit Digital IO I7
IOB_1X8 J8S_8B
U9
NEXUS_JTAG_PORT
NEXUS_JTAG_CONNECTOR FREQA
P8 CLK_TICK
JTAG TDI JTAG_NEXUS_TDI FREQB
JTAG P9
TDO JTAG_NEXUS_TDO
JTAG P10 CLK_BRD
TCK JTAG_NEXUS_TCK TIMEBASE
JTAG
P11
TMS JTAG_NEXUS_TMS
...
JTAG
VCC
JTAG Frequency Counter
TRST
FRQCNT2
Figure 52. PWM circuit with several embedded instruments connected.
1. Open the provided project and download it to your NanoBoard.

2. Follow on your own circuit as the instructor discusses the various embedded instruments.
3. Double-click the NanoBoard icon in the Devices View to open the instrument rack for the
NanoBoard and set its clock frequency to 50MHz.
Figure 53. NanoBoard controller.
4. Open the frequency generator’s

instrument panel. If the time base
indicated in the window next to the
Set Time Base button is not 50
MHz then press the Set Time
Base button to open a dialog box
that will enable you to set it
correctly. The Require 50/50
Duty checkbox should be
checked.
5. The frequency generator should
be set to 1MHz as indicated in
Figure 55.
Figure 54. Counter options dialog
5 - 33
Figure 55. Frequency generator Panel
6. Open the frequency counter’s

instrument panel. Select the
Counter Options button on the
frequency counter module and
make sure the Counter Time Base
is also set to 50MHz (the same as
the NanoBoard clock frequency),
as shown in Figure 56. Press OK.
7. Use the Mode button as necessary
on each channel of the frequency
counter module to toggle the
display mode between frequency,
period or count. You should get
the same display as depicted in
Figure 57.
Figure 56. Counter options dialog
Figure 57. Frequency counter control panel
8. Open the Digital IOB’s instrument panel.
Figure 58. Digital IOB instrument control panel
9. Modify the Outputs of the IOB module and observe changes in the LEDs.
10. Adjust the output frequency of the frequency generator module to a lower frequency; try 1KHz.
Observe the impact this has on the LEDs. Modify the Outputs of the IOB and observe further
changes in the LEDs.
11. Adjust the output frequency of the frequency generator module back to 1MHz.
12. Open the logic analyser’s instrument control panel.
5 - 34
Figure 59. Logic analyser instrument control panel
13. Select Show Panel on the logic analyser. Set the panel up as depicted in Figure 60
Figure 60. Logic analyser triggering options.
14. Select Options on the logic

analyser. Set the clock capture
frequency to 1MHz – the same as
the frequency generator module.
Adjust the other controls to be the
same as shown in Figure 61.
15. Select Arm and observe the
waveform displayed in the waveform
viewer. Select continuous mode
and adjust the IOB output. Observe
the change in the PWM mark-to-
space ratio.
Figure 61. Logic analyser setup options.
5 - 35
Figure 62. Logic analyser waveform with bit-7 of the IOB set.
Figure 63. Logic analyser waveform with bits 6 & 7 of the IOB set.
8.8 Where are the Instruments?

The important differentiator between Altium Designer’s embedded instruments and other simulation-
based virtual instruments is that Altium Designer’s embedded instruments are true physical devices
that are downloaded into the FPGA device as part of the design. The information provided to the
designer by the embedded instruments can be relied upon as it is taken from real physical
measurements taken on chip.
Figure 64 illustrates this point as it shows the FPGA real estate used by the embedded instruments.
5 - 36
Figure 64. Floorplan of MyPWM_withInstruments.SchDoc after it has been placed onto an FPGA.
8.9 Enabling embedded instruments

The NanoBoard hardware incorporates the entire infrastructure necessary to support Embedded
Instruments and allow them to communicate with the host PC. All virtual instruments communicate
with the host PC via a ‘soft’ JTAG chain that conforms to the Nexus standard. To enable Nexus on
the NanoBoard, the NEXUS_JTAG_PORT and NEXUS_JTAG_ CONNECTOR must be placed onto the
top level schematic. These respective components can be found in the FPGA Generic.IntLib
and FPGA NanoBoard Port-Plugin.IntLib Integrated Libraries.
NEXUS_JTAG_PORT
NEXUS_JTAG_CONNECTOR
P8
J TAG TDI JTAG_NEXUS_TDI
J TAG P9
TDO JTAG_NEXUS_TDO
J TAG P10
TCK JTAG_NEXUS_TCK
J TAG
P11
J TAG TMS JTAG_NEXUS_TMS
.. VCC
J TAG
TRST
Figure 65. NEXUS JTAG Port and NEXUS JTAG Connector.
To be able to use embedded instruments in custom designs, it is necessary to reserve 4 device pins
for the NEXUS_JTAG_CONNECTOR and ensure that sufficient device resources are present to
accommodate the virtual instruments in the device. The JTAG soft chain and other communications
chains present on the NanoBoard will be discussed further in the next section.
5 - 37
9 Interacting with the NanoBoard

9.1 Overview
The NanoBoard is pivotal to rapid embedded systems development with Altium Designer. It contains
a range of peripherals and expansion capabilities to allow it to adapt to a broad cross section of
embedded projects. In this section we will discuss the concepts necessary for a designer to make
effective use the NanoBoard’s potential.
9.2 NanoBoard communications

The NanoBoard contains 3 primary communication channels. A complete understanding of these
channels is not necessary to begin using the tool suite however it may be of interest to developers
keen to make use of Altium Designer’s debugging capabilities on their own custom designs.
The primary point of user control of the NanoBoard is via the Devices View. This view provides an
easy-to-use visualization of the various communications chains active on the NanoBoard.
NanoTalk
Chain
JTAG
Hard
Chain
JTAG
Soft
Chain
Figure 66. Devices view with its various communications channels highlighted.
5 - 38
9.2.1 NanoTalk chain

NanoTalk is the proprietary communications protocol developed by Altium to enable multiple
NanoBoards to communicate with one another. The 10 pin NanoTalk headers can be found on both
the left and right edges at the upper end of the NanoBoard. Communications via this channel is
totally transparent to the user. There should be no need to interact with this standard.
9.2.2 JTAG Hard Chain

The JTAG Hard Chain is a serial communications channel that connects physical devices together.
JTAG devices can be connected end on end by connecting the TDO pin of an upstream device to
the TDI pin of a downstream device. The hard JTAG chain is visible in the middle portion of the
Devices View. Usually this is where an FPGA will be located however if you also have other
devices that are connected to the JTAG chain such as a configuration device then these will be
visible also.
The hard JTAG chain can be extended beyond the NanoBoard through the User Board A and User
Board B connectors. When using either of these connectors, it is imperative that the JTAG chain is
not broken – i.e. the TDI/TDO chain must be looped back to the NanoBoard.
9.2.3 JTAG Soft Chain

The JTAG Soft Chain is a separate JTAG channel that provides communication with the Embedded
Instruments that can be incorporated into an FPGA design. This chain is labeled as a soft chain
since it does not connect tangible physical devices together but rather connects soft or downloadable
instruments that reside inside a hard or physical FPGA device.
9.3 Technical background

TDI
JTAG
P a r a lle l Cell
Data Flow
TDO
Figure 67. Conceptual View of JTAG data flows.
9.3.1 JTAG in depth

The acronym JTAG stands for Joint Test Application Group and is synonymous with IEEE 1149.1.
The standard defines a Test Access Port (TAP), boundary scan architecture and communications
protocol that allows automated test equipment to interact with hardware devices. Essentially it
enables you to place a device into a test mode and then control the state of each of the device’s pins
or run a built-in self-test on that device. The flexibility of the JTAG standard has also lead to its
usage in programming (configuring) devices such as FPGAs and microprocessors.
At minimum, JTAG requires that the following pins are defined on a JTAG device:
TCK: Test Clock Input
TMS: Test Mode Select
5 - 39
• TDI: Test Data Input

• TDO: Test Data Output
TCK controls the data rate of data being clocked into and out of the device. A rising TCK edge is
used by the device to sample incoming data on its TDI pin and by the host to sample outgoing data
on the devices TDO pin.
Figure 68. Using JTAG Chain to connect multiple JTAG devices together in a digital design.
Figure 69. JTAG Test Access Port (TAP) State Machine.
The Test Access Port (TAP) Controller is a state machine that controls access to two internal
registers – the Instruction Register (IR) and the Data Register (DR). Data fed into the device via TDI
or out of the device via TDO can only ever access one of these two registers at any given time. The
register being accessed is determined by which state the TAP controller is in. Traversal through the
TAP controller state machine is governed by TMS.
5 - 40
9.3.2 Nexus 5001

The flexibility of JTAG for hardware debugging purposes has flowed over into the software domain.
In the same way that test engineers have sought a standardized method for testing silicon, software
engineers have also sought a standardized means for debugging their programs.
In 1998, the Global Embedded Debug Interface Standard (GEDIS) Consortium was formed. In late
1999 the group moved operations into the IEEE-ISTO and changed their name to the Nexus 5001
Forum and released V1.0 of IEEE-ISTO – 1999. In December 2003, V2.0 was released.
The Nexus 5001 standard provides a standardized mechanism for debug tools to interact with target
systems and perform typical debugging operations such as setting breakpoints and analyzing
variables, etc. There are 4 classes of Nexus compliance – each with differing levels of supported
functionality. The lowest level uses JTAG as the low-level communications conduit.
The implementation of Nexus 5001 on the NanoBoard has been labeled as the JTAG Soft Chain. It
is a serial chain just like the hard chain however rather than connecting physical devices together, it
connects virtual devices together. These devices include the set of virtual instruments that are
supplied with Altium Designer and described in the following chapter. Control of devices on the Soft
Chain can be performed from the Devices View – Soft Chain Devices are located towards the
bottom of the Devices View under the Hard Chain.
As with the JTAG Hard Chain, the Soft Chain can be taken off the NanoBoard via the User Board A
and User Board B connectors. This provides the means for target systems to also include virtual
instruments and to benefit from the Altium Designer development environment. Similarly to the Hard
Chain, it is imperative that a complete loop be maintained between the Soft Chain TDI and TDO
connections.
9.4 The NanoBoard controller

The NanoBoard Controller can be accessed by double-clicking on the NanoBoard icon in the
Devices View.
Figure 70. The NanoBoard Controller Instrument Rack.
P182 CLK_BRD
The Clock Frequency indicated in the window will be supplied to the
CLK_BRD port on the NanoBoard. Accessing this clock on custom designs is
as simple as placing the CLOCK_BOARD component from the FPGA NanoBoard Port-
Plugin.IntLib Library.
Selecting a non-standard frequency is possible by clicking the Other Frequency button. The
NanoBoard clock system employs a serially programmable clock source (part number ICS307-02)
that is capable of synthesizing any clock frequency between 6 and 200MHz. Advanced access to
the Clock Control IC registers is available through the Clock Control Options button. A datasheet
for this device is available from the ICS website http://www.icst.com/products/pdf/ics3070102.pdf.
An online form useful for calculating settings for the clock control IC is also available at
http://www.icst.com/products/ics307inputForm.html.
To the right of the NanoBoard Controller is a section with the heading

Flash RAM. The FPGA Boot button affords the facility to store a daughter
board configuration file that will get automatically loaded into the daughter
board on power up. The Embedded button exposes memory that can be
used by the user application to store non-volatle user data. The
Embedded Memory device is accessible via the SERIALFMEMORY component in the FPGA
NanoBoard Port-Plugin.IntLib Library.
5 - 41
9.5 FPGA I/O view

Double-clicking a device icon in the JTAG Hard chain displays the Instrument Rack for that device.
Figure 71. The FPGA I/O Instrument Rack.
This interface enables the developer to see in real time the flow of signals across the device’s pins.
This can be particularly useful when ensuring that signals are being correctly propagated to and from
the device.
Placing a tick in the Live Update checkbox will cause the display to update in real time.
Alternatively, leaving the Live Update checkbox clear and selecting the update icon will
cause signal information to be latched to the display and held.
Check Hide Unassigned I/O Pins to remove clutter from the display.
The BSDL Information drop down list should only need to be accessed for devices which are
unknown to Altium Designer. In this case, you will need to provide the location of the vendor
supplied BSDL file for the device you are viewing.
The FPGA IO instrument rack is available for all devices on the JTAG Hard Chain – including
devices on a user board that is connected to the JTAG Hard Chain.
9.6 Live cross probing

Probe directives can be placed on the FPGA 00FF
schematic on any I/O net and will update in real time ON
as long as the Hard Devices Instrument Panel is SW[7..0]

1 2 3 4 5 6 7 8
displayed. Use the Place » Directives » Probe to P63,P64,P68,P69,P70,P71,P73,P74

place a cross probe on one of the I/O nets.
Figure 72. Using Live Cross Probing.
9.7 Exercise 5 – View MyPWM on the NanoBoard

1. Reload your circuit from Exercise 3 again and run it on the NanoBoard.
2. Open the FPGA IO Instrument Rack.
3. Check the Hide Unassigned I/O Pins checkbox and the Live Update checkboxes.
4. Observe the change in switch states and LEDs as you toggle the NanoBoard DIP switches.
5. Use the Place » Directives » Probe option to place a probe point on the bus connected to the
DIP Switches. Observe the probe value as the DIP Switches are changed on the NanoBoard.
5 - 42
10 Creating a core component

10.1 Core project
Altium Designer provides the ability to encapsulate an entire FPGA circuit into a single component
that can be used as a building block in other projects. These self-contained blocks are called core
components and offer the advantage of design reuse and design security. Core components can be
synthesized for a target FPGA and made available to others without exposing the underlying IP.
A Core project is used to create an FPGA component that may be used multiple times within one or
across many FPGA projects. The output of a Core project behaves in a similar fashion to a library
component in that it becomes an elemental unit that is used as a component in larger designs.
A Core project is useful when you wish to make some functionality available to a broad user base but
you do not want to expose the IP used to implement the functionality.
Figure 73. Using a Core Component in an FPGA Project.
10.2 Creating a core component from an FPGA project.

It is possible to create a core component from scratch however often we wish to create a core
component from an existing FPGA design or project. In either case a blank core project must first be
created. If the core component is to be based on an existing design then use Project » Add
Existing to Project to add the relevant VHDL and / or schematic documents to the project. If the
core component is being created from scratch then its source documents will need to be created in
the same way that an FPGA project is built.
10.3 A word about EDIF

EDIF is an acronym for Electronic Design Interchange Format. It was originally developed as a
standardized format for transferring integrated circuit design information between vendor tools.
Altium Designer creates EDIF files as part of the synthesis process and these files are then passed
to the vendor back end tools for complete FPGA place and route.
5 - 43
Although EDIF files conform to a standard, the information within a given EDIF file may contain
vendor specific constructs. EDIF files can not, therefore be considered as vendor independent.
It is also worth noting that although EDIF files do offer some form of IP protection, they are readable
by humans and can be deciphered with little effort. They should not be relied upon to maintain IP
protection.
10.4 Setting up the core project

Once the core project has been created it is important to make available its EDIF models when you
eventually ‘publish’ it. Make sure the Include models in published archive checkbox is ticked in
the Options tab of the Project Options dialog.
Figure 74. Setting options for a core component.
You must now specify the folder on your hard disk that you wish the EDIF models to be saved into.
This folder will be searched along with the standard system EDIF folders (\Altium Designer
6\Library\EDIF) when you synthesize any design. It is good practice to keep EDIF models generated
from core projects in a single location for easier searching. The location of the EDIF model folder is
specified in the Preferences – FPGA – Synthesis dialog.
5 - 44
Figure 75. Specifying the location of core component models.
10.5 Constrain / configure

The concept of constraint files and configurations is central to the flexibility of Altium Designer. They
provide a mechanism to allow FPGA circuits to be developed independent of the final physical
implementation. Rather than storing device and implementation specific data such as pin allocations
and electrical properties in the source VHDL or schematic documents, this information is stored in
separate files – called Constraint files. This decoupling of the logical definition of an FPGA design
from its physical implementation allows for quick and easy re-targeting of a single design to multiple
devices and PCB layouts.
There are a number of classes of configuration information pertinent to different aspects of an FPGA
project:
10.5.1 Device and board considerations:

The specific FPGA device must be identified and ports defined in the top level FPGA design must be
mapped to specific pin numbers.
10.5.2 Device resource considerations:

In some designs it may be advantageous to make use of vendor specific resources that are unique
to a given FPGA device. Some examples are hardware multiplication units, clock multipliers and
memory resources.
10.5.3 Project or design considerations:

This would include requirements which are associated with the logic of the design, as well as
constrains on its timing. For example, specifying that a particular logical port must be allocated to
global clock net, and must be able to run at a certain speed.
A configuration is a set of one or more constraint files that must be used to target a design for a
specific output. The migration of a design from prototype, refinement and production will often
involve several PCB iterations and possibly even different devices. In this case, a separate
5 - 45
configuration would be used to bring together constraint file information for each design iteration.
Each new configuration (and its associated constraint file(s) ) is stored with the project and can be
recalled at any time.
To summarize:
• Constraint files store implementation specific information such as device pin allocations and
electrical properties.
• A Configuration is a grouping of one or more constraint files and describes how the FPGA
project should be built.
10.6 Creating a new constraint file.

Before a configuration can be built, a constraint file must exist. Constraint files have the extension
.Constraint. Constraint files for use with the NanoBoard daughter-board modules can be found in
the \Program Files\Altium Designer 6\Library\Fpga directory. In general it is advisable
to take a copy of these files and store it in your project directory before adding it to the project. This
way the project is kept self-contained and any edits you may inadvertently make will not affect the
supplied constraint file.
• To add your own, new constraint file, right click on the project name in the Projects panel and
select Add New To Project » Constraint File.
• A new blank constraint file will appear. To specify the target device select Design » Add/Modify
Constraint » Part and the Browse Physical Devices dialog will open.
Figure 76. The Browse Physical Devices dialog, where you select the target FPGA.
5 - 46
Figure 77. Basic constraint file.
• Select the vendor, family, device and

temperature/speed grades as desired and click
OK. A line similar to the one above will be
automatically inserted into the constraint file:
• Save the constraint file. Typically it would be
named to reflect its role – for example if the
target device was a Xilinx Spartan-3 FPGA
mounted on your project PCB you might call it
MyProject_Spartan2E.Constraint. You
will notice the constraint file has been added to
the project under the settings tab.
Figure 78. Project with constraint File.
10.7 Creating a configuration

As previously mentioned, configurations group a number of constraint files together to create a set of
instructions for the FPGA build process. To define a configuration …
• Right-click on the project name in the Projects panel and select Configuration Manager
Figure 79. Specifying a configuration using the configuration manager.
• If you have just recently created a new constraints file, you will see it listed under the Constraint
Filename. Existing constraint files that currently aren’t in the project can be added by selecting
the Add button next to the Constraint Files text.
• To define a new configuration, select the Add button next to the Configurations text. A dialog
will appear requesting you to provide a name for the new configuration. The name can be
arbitrary but it is helpful if it provides some indication as to what the configuration is for.
• Having defined the new configuration, you may now assign constraint files to it by ticking their
associated checkbox. Here we have assigned the constraint file MyProject_Spartan2E to the
Target_XC2S300E configuration.
5 - 47
• Click OK to save the configuration.
Figure 80. Specifying a configuration using the configuration manager.
Although the above simplistic example only had one constraints file and one configuration, the power
of configurations really becomes apparent as the design matures. Below we see how a design has
been targeted to multiple platforms:
Figure 81. Example of a project with multiple configurations defined.
Configurations can be updated or modified as desired at any time throughout the project’s
development by returning to the Configuration Manager dialog.
10.8 Synthesize
Now that we have defined a
configuration we are ready to
synthesize the core for the
target.
• With the top level FPGA
document open select
Design » Synthesize. If we
had defined more than one
configuration and wished to
synthesize all configurations
at once we could select Figure 82. Specifying an FPGA project’s top level document.
Design » Synthesize All
Configurations.
• If you have not already nominated the top level
entity/configuration in the Synthesis tab of the
Options for Core Project, the Choose Toplevel
dialog will appear. Enter the core project name or
select from the dropdown list and click OK to continue.
• The project will be synthesized resulting in the
generation of VHDL files for the schematic, EDIF files
for the schematic wiring and parts, and a synthesis log
file. These will all be located under the Generated
folder in the project panel.
Figure 83. Files generated after synthesizing the

design
5 - 48
• You will observe the configuration name in brackets beside the Generated Folder. Had we
synthesized more than one configuration then a separate Generated folder would have appeared
for each of the defined configurations.
• Confirm that the synthesis process completed successfully by observing the synthesis log file. A
line towards the bottom of the report should indicate whether any errors were encountered.
10.9 Publish
Now we can publish the core project. This will zip together (archive) all the EDIF files in the core
project’s Project Outputs folder and then copy this to the user EDIF models folder that was specified
earlier.
• Select Design » Publish. If the error message “cannot find ‘working folder’” appears, make sure
you have set up the Use presynthesized model folder option in the FPGA Preferences dialog.
• Check the Messages panel to ensure the design has been successfully published.
• Save the core project file.
10.10 Creating a core schematic symbol

The core project has been successfully synthesized and published. It would be possible at this point
for other personnel to make use of your core through a VHDL instantiation process. This can be a
messy affair. A far simpler option would be for them to use a schematic symbol that is linked to your
core and associated EDIF files. To do this, we need to create our own schematic symbol from the
core component.
• With the top level FPGA document open select Design » Generate Symbol.
Figure 84. Creating a core component symbol.
• A new schematic library (Schlib1.SchLib) will be automatically created and opened to display the
generated symbol. By default the component name will take on the same name as the core
project name. Options controlling the new component’s appearance and style can be controlled
from the Options tab of the Project » Project Options dialog.
5 - 49
Figure 85. Specifying core component options.
• From within the library editor, select the component in the Library panel and select the Edit
button. The Library Component Properties dialog will be displayed. Note that several
parameters have been added to indicate which child models are required to be retrieved from the
published EDIF zip files.
Figure 86. Specifying the properties of the newly created core component symbol.
• Clicking on the Edit Pins button will enable further modification of the properties and appearance
of the schematic symbol.
• From the schematic library editor, adjust the symbol properties as appropriate and save the
component. Save the library before exiting.
5 - 50
Figure 87. Editing the core component pins.
10.11 Using a core component

When a core component is synthesized and published, the EDIF model is archived into the location
specified in the FPGA Preferences dialog. Any project that subsequently uses the core component
must ensure that the EDIF archive can be found within the search path. The search sequence for
EDIF models is:
$project_dir
$user_edif\$vendor\$family
$user_edif\$vendor
$user_edif
$system_edif\$vendor\$family
$system_edif\$vendor
$system_edif
5 - 51
Note that the search locations includes the project directory which makes it useful if you need to
transfer the design to another PC that does not have the user EDIF models location defined.
10.12 Exercise 6 – Create a core component from MyPWM

1. Create a new core project and call it MyPWMCore.PrjCor. Note that the filename must not have
spaces in it.
2. Follow the steps in Section 10.4 to ensure the settings are correct.
3. Attach the existing MyPWM.SchDoc that you created as part of exercise 3.
4. Create a project level constraint file and call it MyPWMPrj.Constraint. Add the following to this
constraint file:
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_PIN=True
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK=True
Record=Constraint | TargetKind=Port | TargetId=CLK_BRD | FPGA_CLOCK_FREQUENCY=50Mhz
Figure 88. Updates to be made to MyPWMPrj.Constraint file.
5. Create a constraint file each for an Altera Cyclone device as well as a Xilinx SpartanIIE device.
6. Create a configuration that links each of the individual device constraint files with the project
constraint file.
7. Synthesize all configurations and publish the design. Check the User Presynthesized model
Folder (as set in Section 10.4) using windows explorer and view the directories that are created
and their contents.
8. Create a core schematic symbol and save it to the library MyCoreLib.SchLib.
9. Create a new FPGA project and schematic that makes use of your PWM core and test it on the
NanoBoard.
U1
P182 CLK_BRD
ON
CLK_BRD LEDS[7..0] LEDS[7..0]
SW[7..0] SW[7..0] P55,P56,P57,P58,P59,P60,P61,P62
1 2 3 4 5 6 7 8
TEST_BUTTON
P63,P64,P68,P69,P70,P71,P73,P74
MyPWMCore
P3 TEST_BUTTON
Figure 89. Test project used to test the function of MyPWMCore.
5 - 52
11 FPGA design simulation

Altium Designer supports behavioral simulation of VHDL designs. This is particularly useful when
verifying the functional operation of digital circuits prior to implementing them inside an FPGA.
11.1 Creating a testbench

Before simulation can begin, a VHDL Testbench file must be created to drive the simulation
session. Conceptually, the Testbench straddles the Design Under Test (DUT) and drives the DUT’s
inputs whilst observing its outputs.
VHDL Testbench
Design Under Test (DUT)

DUT DUT
Inputs Outputs
Figure 90. Conceptual view of how a VHDL testbench interacts with the Design Under Test (DUT).
Altium Designer provides a convenient method for building a VHDL Testbench based on the inputs
and outputs of the nominated DUT. A shell testbench file can be automatically created by the
system.
• Open a schematic document and select Tools » Convert » Create VHDL Testbench from the
menu.
• Open a VHDL document and select Design » Create VHDL Testbench.
A new VHDL document will be created with the extension .VHDTST and will be added to the project.
Within the Testbench file will be a comment “—insert stimulus here”. By placing VHDL code at this
point you can control the operation of the simulation session. At a minimum, the Testbench must set
all of the DUT’s inputs to a known state. If the DUT requires a clock then that too must be provided
by the Testbench. Most simulation errors occur as a result of the Testbench failing to properly
initialize the inputs of the DUT.
11.2 Assigning the Testbench Document

Once you have created the Testbench file but before a simulation can begin, Altium Designer needs
to be formally told which VHDL document in the project will be used to drive the simulation. Select
Project Options by right clicking on the FPGA project in the Projects panel or use the menu to
select Project » Project Options Select the Simulation tab from within the Project Options dialog
and select the appropriate Testbench Document from the drop-down list.
5 - 53
Figure 91. Specifying the testbench document.
11.3 Initiating a simulation session

A simulation session can be
initiated by selecting
Simulator » Simulate from
the menu or by clicking the
simulation button in the VHDL Tools toolbar whilst a VHDL document is active in the main window.
11.4 Project compile order

When you first run a simulation from a testbench, Altium Designer may need to establish the
compilation order of the VHDL documents. Whilst performing this process, you may see an error
appear in the Messages panel with the message: “Unbound instance DUT of component …”. Do
not be concerned as this is normal when you first run a simulation.
Figure 92. Messages panel.
5 - 54
After a brief moment, the Project Compile

Order dialog will appear indicating the
suggested compilation order (Figure 93).
The compilation order of the project can be
changed at a later time if necessary by
selecting Project » Project Order or by right
clicking on the FPGA project in the Projects
panel and selecting Project Order
Figure 93. Confirming the project compiler order.
Figure 94. Specifying signals to display in the

simulation.
11.5 Setting up the simulation display

The Signals dialog (Figure 94) is automatically presented at the beginning of a simulation or it can be
accessed via Simulator » Signals.
The Watch Name is the name of the signal declared inside the block of VHDL code.
Signals must be Enabled in order to be a part of the simulation. Furthermore, if they need to be
displayed as part of the simulation output then Show Wave must also be selected.
The Waveform viewer provides a visualization of the status of each of the displayed signals.
Figure 95. The waveform viewer.
5 - 55
• The icon next to the bus name indicates a bus signal. Clicking on this icon will expand the bus
into its individual signals for closer inspection.
• The time cursor (indicated by the purple vertical bar) can be dragged along the time axis via the
mouse. The current position of the cursor is provided in the time bar across the top of the display.
• Zooming in or out is achieved by pressing the Page Up or Page Down keys respectively.
• The display format of the individual signals can be altered via the menu item Tools » Format and
Radix.
11.6 Running and Debugging a Simulation

Running a simulation is reasonably straightforward with all the
stepping/running functions that you might wish to use being
available from the Simulation menu or the VHDL Tools toolbar.
• Run Forever will run the simulation indefinitely until Stop is
pressed. This command is used to run a VHDL simulation until
there are no changes occurring in the signals enabled in the
simulation.
• Use the Run (for a time step) command to run the current
simulation for a user-specified period of time (time step).
• Run for (the last time step) will run the simulator for the same
period of time as specified in the last Run command.
• Run to Time will run the simulator to an absolute time.
Selecting a time prior to where the simulation has already
simulated to will cause the simulator to do nothing.
• Run to Cursor is useful when debugging VHDL source and
will cause the simulator to run until the defined cursor location
is encountered in a source VHDL document. The simulator will
simulate everything up to the selected line. Make sure that the
Show execution point option is enabled, in the Debugging
Options region of the FPGA – Simulation Debugger page of
the Preferences dialog (Figure 97).
• Custom Step (Run simulation to the next debug point): This
command is used to run the current simulation, up to the next
executable line of code in the source VHDL documents. The
next executable code point can be anywhere in the code and
therefore the command can be considered to be stepping
through the code in parallel, rather than the sequentially-based Figure 96. The simulation menu.
step into and step over commands.
• Step Time: This command is used to run the current simulation, executing code in the source
VHDL documents until time increments – i.e. all delta time events prior to the next time increment
will be executed.
• Delta Step: This command is used to run the current simulation for a single cycle, which can be
called a Delta step. A Delta step can be so small that no change in real time is seen.
• Step Into enables the user to single-step through the executable lines of code in the source
VHDL documents. If any procedures/functions are encountered, stepping will continue into the
called procedure or function.
• Step Over is similar to Step Into except that if any procedures/functions are encountered,
stepping will execute the entire procedure/function as a single executable line and will not step
into it.
5 - 56
Figure 97. The simulation debugger options in the preferences dialog.
• Stop will pause the simulator at its current simulation point. A paused simulation can continue to
be run with any of the above commands.
• Reset will abort the current simulation, clear any waveforms and reset the time back to 0.
• End terminates the entire simulation session. Ended simulations can not be restarted other than
by initiating another simulation session.
5 - 57
11.7 Exercise 7 – Create a testbench and simulate MyPWM

1. Open the project you created in Exercise 2 and make MyPWM.VHD the active document.
2. Select Design » Create VHDL Testbench from the menu.
3. Update the testbench to be the same as the code listed in Figure 98.
Figure 98. Testbench code for testing MyPWM.
4. Update the testbench document, top-level entity/configuration and top-level architecture fields in
the simulation tab of the Project » Project Options dialog.
5. Compile the testbench document and rectify any errors.
6. Run the simulation by selecting Simulator » Simulate.
7. Run the simulator for 2us.
8. Observe the waveforms for LEDS[0] and LEDS[1]. Is it what you expect? Try changing the
PWM period by changing the value of SW in the testbench.
5 - 58
12 Review
5 - 59
LiveDesign
Training Module
All rights reserved. You are permitted to print this document provided that (1) the use of such is for
personal use only and will not be copied or posted on any network computer or broadcast in any
media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part,
of this document by any means, mechanical or electronic, including translation into another
language, except for brief excerpts in published reviews, is prohibited without the express written
permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local
statute. Violators may be subject to both criminal and civil penalties, including fines and/or
imprisonment.
Altium, Altium Designer, Board Insight, CAMtastic, CircuitStudio, Design Explorer, DXP, LiveDesign,
NanoBoard, NanoTalk, Nexar, nVisage, P-CAD, Protel, SimCode, Situs, TASKING, and Topological
Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or
its subsidiaries.
Corporation. OrCAD, OrCAD Capture, OrCAD Layout and SPECCTRA are registered trademarks of
Cadence Design Systems Inc. AutoCAD is a registered trademark of AutoDesk Inc. HP-GL is a
registered trademark of Hewlett Packard Corporation. PostScript is a registered trademark of Adobe
Systems, Inc. All other registered or unregistered trademarks referenced herein are the property of
their respective owners and no trademark rights to the same are claimed.
Module 6
Altium Designer Training LiveDesign
LiveDesign Training Module

1 LiveDesign .................................................................................................................6-1
1.1 Learning objectives.........................................................................................6-1
1.2 Topic outline ...................................................................................................6-1
2 Introduction to LiveDesign .......................................................................................6-2
3 Embedded application development.......................................................................6-3
3.1 Creating an embedded Project.......................................................................6-3
3.2 Editor basics ...................................................................................................6-4
3.3 Exercise 1 – Editor familiarization ..................................................................6-9
4 The TASKING tool chain .........................................................................................6-10
4.1 The build flow................................................................................................6-10
4.2 Targeting the project.....................................................................................6-11
4.3 Project options ..............................................................................................6-11
4.4 C compiler options ........................................................................................6-12
4.5 Assembler options ........................................................................................6-17
4.6 Linker options ...............................................................................................6-19
4.7 Compiler output ............................................................................................6-22
4.8 Exercise 2 – First compile ............................................................................6-22
5 Utilizing microprocessor softcores .......................................................................6-23
5.1 How soft is a softcore? .................................................................................6-23
5.2 Using a softcore in an FPGA schematic.......................................................6-24
5.3 On-chip debugging or not? ...........................................................................6-24
5.4 Exercise 3 – Placing a softcore onto an FPGA schematic ...........................6-25
6 Linking an embedded project to the hardware design........................................6-27
6.1 Project Hierarchies .......................................................................................6-27
6.2 Attaching an embedded project to an FPGA project ....................................6-28
6.3 Linking program memory to the processor core...........................................6-30
6.4 Exercise 4 – Linking projects........................................................................6-31
7 Putting wheels on LiveDesign................................................................................6-32
7.1 The printf dilemma ...................................................................................6-32
7.2 Initializing the LCD........................................................................................6-32
7.3 Exercise 5 – Using LiveDesign to initialize an LCD......................................6-34
8 Debugging the design.............................................................................................6-42
8.1 A word about simulation ...............................................................................6-42
8.2 The Debug menu ..........................................................................................6-42
8.3 Embedded control panels .............................................................................6-44
8.4 Exercise 6 – Code Debug.............................................................................6-50
9 Advanced compiler features ..................................................................................6-51
9.1 C language extensions .................................................................................6-51
9.2 Supported data types....................................................................................6-51
9.3 Memory type qualifiers..................................................................................6-52
9.4 Accessing hardware from C: __sfr, __bsfr ...................................................6-54
9.5 Placing an object at an absolute address: __at() .........................................6-56
9.6 Declaring interrupt functions.........................................................................6-56
9.7 Incorporating assembly in C code ................................................................6-58
9.8 Real-Time Operating System (RTOS)..........................................................6-62
9.9 Exercise 7 – PWM measurement .................................................................6-63
10 Review ......................................................................................................................6-65
i
1 LiveDesign
The primary objective of Day 2 is to make participants proficient in the process of developing,
downloading and running Embedded Software from the Altium Designer environment. We will
highlight the software authoring and debugging features of Altium Designer as well as develop a
small, embedded application that can be run on the NanoBoard.
1.1 Learning objectives

• To be competent in developing embedded applications under the Altium Designer environment.
• To understand how to include an embedded processor core into an FPGA design and link an
embedded project to that core.
• To be competent in the debugging environment offered under Altium Designer.
• To understand how to tune the compiler settings for a given application.
1.2 Topic outline

Core topics Advanced topics (time permitting)
Introduction Advance
to the text compiler
editor features
The
TASKING
compiler
tool chain
Linking
code &
hardware
Using an
FPGA
softcore
LiveDesign
Working
“Hello World”
project
Code
debugging
Figure 1. Topic outline for Day 2 – LiveDesign
6-1
2 Introduction to LiveDesign
“Debugging is twice as hard as writing the code in the first place.
Therefore, if you write the code as cleverly as possible,
you are, by definition, not smart enough to debug it.“
Brian W. Kernighan
Altium Designer supports a new approach to electronics development – called LiveDesign.

LiveDesign is an integrated electronics system design methodology that is based on 'live'
engineering inside a programmable physical hardware design space. LiveDesign-enabled tools
provide real-time communication and ‘hands-on’ interaction between you and your design during the
development process. LiveDesign allows you to run real software on real hardware in real time, right
from the start of the design cycle!
LiveDesign is supported in Altium’s design systems with the inclusion of ready-to-use FPGA-based
components such as processor cores, generic logic blocks and FPGA-based virtual instruments.
Full software development toolchains for the supplied processors are integrated with the hardware
development environment and provide an interactive and scalable development environment for the
design of both system hardware and software.
In summary, LiveDesign allows you to:
• Reduce development costs and time-to-market by working in a fully-integrated
design/implementation/test environment
• Interact in ‘real-time’ with your design throughout the development process
• Design hardware and software concurrently and in parallel
• Probe, analyze and debug your design as you would a physical prototype using FPGA-based
virtual instruments
• Delay commitment to final hardware until late in the design cycle
• Update your design hardware at any time without time or cost penalties
• Integrate complex digital circuits, including processor-based designs, into an FPGA without the
need for HDL coding or RTL-level simulation experience
Today’s session will introduce you to the LiveDesign approach and how you can utilize it in your next
embedded design. It is assumed that attendees to this session will have completed the previous
session on FPGA design.
6-2
3 Embedded application development

3.1 Creating an embedded Project
Source code that is to execute on a single processor should be contained within an embedded
project (*.PrjEmb). Creating an embedded project is much the same as creating any project. From
the menu select File » New » Project » Embedded Project.
An empty embedded project will be created in the current workspace. We will then create a number
of source files to contain your application. Altium Designer contains a C cross compiler and
assembler for each of its supplied soft processors. The compiler determines how to treat a file
(compile or assemble) based on its file extension. C code should reside in a file with the extension
.C, assembly code should reside in files with the extension .ASM.
To add an empty source file to the embedded project, right-click the embedded project in the
Projects panel and select Add New to Project » Assembly File or C File.
Figure 2. Adding a new source file to an embedded Project.
6-3
3.2 Editor basics

• The editor included with Altium Designer is a Language
Sensitive Editor and is capable of applying a number of
visual enhancements to the source code to make it more
readable and compliant with company coding practices.
• The primary point of interaction with the Editor features is
from the Tools menu:
• Show Code Templates will allow the user to insert
predefined code templates (Figure 4) at the current cursor
location within the file. The user can add additional
templates from within the Language Setup dialog box
(Figure 5 & Figure 7).
• Indent will force the currently highlighted lines to be
indented one level.
• Unindent will remove one level of indentation from the
currently highlighted lines.
• Change Case will apply various case changing edits to
the currently selected items in the editor.
• Word Wrap will simply wrap a line that extends beyond
the page size to the next line. Figure 3. Tools menu.
• Formatting Options… launches the main Preferences dialog box and displays settings relating
to the Code Formatting (Figure 8 & Figure 9).
• Format Source Code immediately applies the current format settings to the currently opened file.
• Import Editor Settings from enables previously saved editor preferences and settings to be
imported into the current project.
• Editor Preferences launches the main Preferences dialog box and displays settings relating to
the Text Editor (Figure 10, Figure 11 & Figure 12). The Edit Syntax… button (Figure 12) is the
controlling point for setting up all features specific to a given language such as syntax highlighting
styles, reserved words, and comment handling etc. (Figure 13).
• Embedded Preferences launches the main Preferences dialog box and displays the embedded
system settings (Figure 14).
To use the editor’s autocomplete
features, type the text as it
appears in bold on the right hand
side of Figure 4 and select Ctrl-J.
Selecting Ctrl-J next to a block of
text which is not known as an
autocomplete statement will bring
up the Code Templates list as
pictured in Figure 4.
Figure 4. Predefined code templates.
Altium Designer uses two different mechanisms for determining how it handles different file types.
The Associations setting in the Language Setup dialog simply defines how the editor will display
the syntax of the file. The existence of a file association in the Language Setup dialog does not
dictate how Altium Designer will treat the file.
A system file called <Install Dir>\System\FileExtensions.Txt defines how the file is to be
treated by the Altium Designer platform. Only specific file types are considered as ‘Source
Documents’. Other file types not listed in FileExtensions.Txt are treated as ‘Documentation’. It
6-4
is therefore important how files are labeled otherwise they will not be properly included when the
project is built.
Figure 6. Only specific files known to Altium Designer

can be used as ‘Source Documents’.
Figure 5. Language setup dialog box.
Figure 7. Code templates editor.
6-5
3.2.1 Code formatting
Figure 8. Specifying general code formatting options.
Figure 9. Specifying general code formatting options to apply to how code is spaced.
6-6
3.2.2 Text editor settings
Figure 10. General text editor settings.
Figure 11. Text editor settings controlling overall visual appearance
6-7
Figure 12. Text editor settings controlling how specific items are highlighted/colored.
3.2.3 Syntax highlighting
Figure 13. Syntax editor/options.
6-8
3.2.4 General options
Figure 14. General embedded systems document options.
3.3 Exercise 1 – Editor familiarization

1. Open a new embedded project. Save it as HelloWorld.PrjEmb.
2. Open a new C File. Save it as HelloWorld.C
3. Insert the following lines of code from the Hello World application (Figure 15).
Figure 15. Hello World Source code.
4. If time permits, experiment with some of the editor settings to see their effect on the source code.
Remember to select Tools » Format Source Code after making each change.
5. Save your work.
6-9
4 The TASKING tool chain

Many long-time users of Protel are familiar with its advanced schematic and PCB capabilities and
can understand how schematic-based FPGA development is a natural extension of Altium’s core
technologies. Delving into the world of embedded systems programming however represents a
significant departure from the hardware focus that Protel has previously had and some may question
just how serious a player Altium intends to be in this market.
The reality is that Altium, through their corporate acquisition of TASKING, are already a major player
in the embedded systems marketplace. TASKING products are world-leading tools for embedded
software development, bringing together the advanced software design technology needed to
compete in the embedded communications era. The award-winning TASKING integrated
development environment, compiler, debugger, embedded Internet and RTOS offerings support a
wide range of DSPs and 8-, 16- and 32-bit microprocessors and microcontrollers for all areas of
embedded development. With over 100,000 licensed users of TASKING products, including the
world's leading telecom, datacom, wireless and peripheral manufacturers, the TASKING product
range has a long history of technology leadership and innovation.
4.1 The build flow
Figure 16. The TASKING tool chain.
6 - 10
Building an application is the process of compiling all of the top-level source documents into a binary
file that can be executed by a target processor. This is a multi-step process involving a number of
tools. In many situations, the user will be shielded from the detail of the underlying compilation
processes however in some circumstances it will be necessary to diagnose the source of build or
compilation errors and for this it is important to understand the compilation flow.
The C compiler, assembler and debugger are target dependent, whereas the linker and the librarian
are target independent. The bold names in Figure 16 are the executable names of the tools.
Substitute target with one of the supported target names, for example, c51 is the 8051 C compiler
and cz80 is the Z80 C compiler.
4.2 Targeting the project

Prior to compiling an embedded project, it is necessary to notify the compiler of which processor we
intend to use and any special compilation features we may wish to include. This is done via the
Project Options… dialogue box that can be accessed by right-clicking the Embedded Project in the
Projects panel and selecting Project Options… panel or by selecting Project » Project Options…
from the main menu.
Figure 17. Specifying options for an embedded project.
4.3 Project options
4.3.1 Processor class

Select from TASKING 165x, TASKING 8051 or TASKING Z80 processor families. These processors
are instruction set compatible with the PIC16CX, Intel 8051 and Zilog Z80 industry standard
processors respectively.
4.3.2 Processor definition

The only processor class that currently contains an option at this point is the 165x. There is a
TSK165A, TSK165B, and TSK165C variant. The following table summarizes their differences:
Feature TSK165A TSK165B TSK165C
Addressable program memory 512*12 2K*12 Same features as
TSK165B, plus
Data memory 16 + 9 bytes 64 + 9 bytes
three additional 8-
Program Counter width 9 bits 11 bits bit ports.
Stack width 9 bits 11 bits
6 - 11
4.3.3 Startup code

The defaults are generally acceptable for the majority of projects. If you should ever choose not to
include the default startup code produced by the compiler you will have to assume the responsibility
of handling the reset interrupt, initializing memory variables, and passing control to the main function
in the C source code.
4.4 C compiler options

The Compiler is functionally responsible for parsing the high-level C source commands and reducing
them to atomic operations that can be easily mapped onto the target processor’s instruction set.
This process involves a number of phases including (but not limited to):
1. Preprocessing
2. High-level Optimization
3. Instruction selection
4. Peephole Optimization / Instruction Scheduling
5. Register Allocation
6. Low-level Optimization
7. Code formatting.
Due to the vast variation in requirements and optimization goals, it is not possible to have a “one
setting suites all” compiler. Subsequently a number of compiler options are made visible to the user
so that the compilation process can be tuned to the specific application. These options are
discussed further below:
4.4.1 Memory model

Only the 8051 has options for the memory model. By default, the small memory model is selected
however the TASKING C compiler also supports a large and auxiliary page memory model:
Memory model Description Max. RAM size Default memory type
Small Direct addressable internal RAM 128 bytes __data
Auxiliary page One page of external RAM 256 bytes __pdata
Large External RAM 64 kB __xdata
The exact size of the different memory segments can be defined in the Linker – Memory section of
the Project Options… dialogue box.
By default the 8051 compiler uses the small memory model. In the small memory model all data
objects with the default memory type and the stack (used for function parameter passing) must fit in
the internal RAM. Objects with an explicit memory type qualifier can exceed this limitation (for
example an object qualified as __xdata or __pdata). Note that the stack length depends upon the
nesting depth of the various functions. Accessing data in internal RAM is considerably faster than
accessing data in external RAM. Therefore, it is useful to place often used variables in internal data
memory and less often referenced data elements in external data memory.
When the compiler uses the large memory model to access data, the produced code is larger and in
some cases slower than the code for a similar operation in one of the other memory models.
The auxiliary page memory model is especially interesting for derivatives with 256 bytes of 'external'
RAM on chip. All data objects with the default memory type must fit in one 256 bytes page.
Optionally you can choose to enable reentrancy. If you select reentrancy, a (less efficient) virtual
dynamic stack is used which allows you to call functions recursively. With reentrancy, you can call
functions at any time, even from interrupt functions.
6 - 12
C Compiler - Memory Model (8051 only)
Memory Model option Command line

Select a compiler memory model -M[a | l | s]
Allow reentrant functions --reentrant
4.4.2 Code generation

The only item that may need to be altered in this panel would be the Strings option. Copy strings
from ROM to RAM at startup may cause more RAM than would otherwise be absolutely necessary
to be consumed when the project is built. On the other hand, accessing strings from RAM is
generally quicker.
C Compiler - Code Generation
Code generation options Command line

Copy strings from ROM to RAM at startup no option
Keep strings in ROM (8051 only) --romstrings
Do not generate code for interrupt vector --novector
Reset/interrupt vector offset --vector-offset=address
Do not generate frame for interrupt handler --noframe
Do not allow absolute registers (AR0-AR7) in --noregaddr
generated code (8051 only)
4.4.3 Preprocessing
This section is helpful if it is necessary to define preprocessor macros that will direct conditional
compilation in the source. For example you may wish to declare a macro called DEBUG_MODE and
use conditional compilation in your source code depending on whether this macro was defined:
#ifdef DEBUG_MODE
do something...
#else
do normal processing...
#endif
C Compiler - Preprocessing
Preprocessing options Command line

Define macro -Dmacro[=def]
Include this file before source -Hfile
Store the C Compiler preprocess output -E
(file.pre)
4.4.4 Optimization
The TASKING C compilers offer four optimization levels and a custom level. At each level a specific
set of optimizations is enabled.
• Level 0: No optimizations are performed. The compiler tries to achieve a 1:1 resemblance
between source code and compiled code. Expressions are evaluated in the order written in the
source code, associative and commutative properties are not used.
• Level 1: Enables optimizations that do not affect the debug-ability of the source code. Use this
level when you are developing/debugging new source code.
6 - 13
• Level 2: Enables more aggressive optimizations to reduce the memory footprint and/or execution
time. The debugger can handle this code but the relation between source code and generated
instructions may be hard to understand. Use this level for those modules that are already
debugged. This is the default optimization level.
• Level 3: Enables aggressive global optimization techniques. The relation between source code
and generated instructions can be very hard to understand. The debugger does not crash, will not
provide misleading information, but does not fully understand what is going on. Use this level
when your program does not fit in the memory provided by your system anymore, or when your
program/hardware has become too slow to meet your real-time requirements.
• Custom level: you can enable/disable specific optimizations.
Figure 18. Specifying code optimization options for an embedded project.
C Compiler - Optimization
Optimization options Command line

Optimization level -O[0|1|2|3]
Custom optimization -Oflag
Optimize for size / speed -t{0|4}
6 - 14
4.4.5 Language
Defaults are usually adequate however on the odd occasion you may wish to build code that is pre
ISO C 99 compatibility and you will need the options contained in this panel.
C Compiler - Language
Language options Command line

ISO C standard 90 or 99 (default: 99) -c{90|99}
Language extensions:
Allow C++ style comments in C source -Ap
Relaxed const check for string literals -Ax
Treat 'char' variables as unsigned -u
Treat 'int' bitfields as signed --signed-bitfields
Always use 16-bit integers for enumerations --integer-enumeration
4.4.6 Debug information

In general it is helpful to always generate debug information unless building for a final production
release where debug information would be superfluous.
C Compiler - Debug Information
Debug Information options Command line

Generate symbolic debug information -g
4.4.7 Floating point

In general the default setting (i.e. floating point trap/exception handling checked) is acceptable
unless you have good reason to change it.
4.4.8 Diagnostics
This section controls how compilation warnings are reported. In some cases it may be desirable to
suppress specific warnings if they are creating too much ‘noise’ in the Messages Panel.
C Compiler - Diagnostics
Diagnostics options Command line

Report all warnings no option -w
Suppress all warnings -w
Suppress specific warnings -wnum[,num]...
Treat warnings as errors --warnings-as-errors
4.4.9 MISRA C & MISRA C Rules

The Motor Industry Software Reliability Association (MISRA) is in existence “To provide assistance
to the automotive industry in the application and creation within vehicle systems of safe and reliable
software.” Through extensive consultation within the automotive industry, MISRA has completed the
development of guidelines specifically aimed at the use of the C language in safety related systems.
These guidelines primarily identify those aspects of the C language that should be avoided in safety-
related systems, along with other recommendations on how other features of the language should be
used. It is anticipated that the guidelines will be adopted for embedded C programming throughout
the automotive industry.
Altium Designer includes a number of compilation options that can flag as a warning code that does
not comply with MISRA recommendations.
6 - 15
C Compiler - MISRA C
MISRA C options Command line

MISRA C rules --misrac={all|nr[-nr] ,...}
4.4.10 Miscellaneous
Use this section to pass any compiler flags or settings that have not been covered in the previous
panels. The Options String at the base of the Compiler settings panel provides an indication of the
options that will be passed to the C compiler. Further information about each individual setting can
be found in GU0105 Embedded Tools Users Guide.pdf or via the help system under Embedded
Software Development » Embedded Tools Options Reference » Compiler Options.
C Compiler - Miscellaneous
Miscellaneous options Command line

Merge C source code with assembly in output file (.src) -s
Additional C Compiler options options
Command line only
Description Command line

Display invocation syntax -? / --help[=item,...]
Default register bank [0..3] (8051 only) -bn
Maximum size of a match with code compaction --compact-max-size=value
(default: 200)
Show description of diagnostic(s) --diag=[fmt:]{all|nr,...}
Redirect diagnostic messages to a file --error-file[=file]
Use single precision floating point only -F
Read options from file -ffile
Always inline function calls --inline
Maximum size increment inlining (in %) (default: 25) --inline-max-incr=value
Maximum size for function to always inline (default: 10) --inline-max-size=value
Keep output file after errors -k
Maximum call depth, default infinite (-1) --max-call-depth=value
Send output to standard output -n
Do not clear non-initialized global variables --noclear
Specify name of output file -ofile
Rename default section name -R[type]={name | -f | -m | -
fm}
Treat external definitions as "static" --static
Remove preprocessor macro -Umacro
Display version header only -V
Max. nr. of bytes for automatic regs. (default: 4) (8051 -xvalue
only)
6 - 16
4.5 Assembler options

The assembler converts hand-written or compiler-generated assembly language programs into
machine language, using the IEEE-695 object format. These files serve as input for the linker.
Phases of the assembly process
1. Preprocess directives
2. Check syntax of instructions
3. Instruction grouping and reordering
4. Optimization (instruction size and jumps to branches)
5. Generation of the relocatable object file and optionally a list file
Figure 19. Specifying assembler options for an embedded project.
The Project Options… dialogue box contains a number of assembler options. The subsections of
the assembler options allow for additional control over the assembler in much the same way that the
previously mentioned compiler options do.
The default options are generally sufficient for most applications however should you find it
necessary to tune the assembler then further information can be found in GU0105 Embedded Tools
Users Guide.pdf or via the help system under Embedded Software Development » Embedded
Tools Options Reference » Assembler Options.
A summary of the available assembler options are listed below:
Assembler - preprocessing
Preprocessing options Command line

Define macro -Dmacro[=def]
Include this file before source -Hfile
Assembler - optimization

Generic instructions -Og
Instruction size -Os
6 - 17
Assembler - debug Information
Debug Information options Command line

No debug information -gAHLS
Automatic HLL or assembly level debug information -gs
Custom debug information -gflags
Assembler - list file
List File options Command line

Generate list file -l
Display section information in list file -tl
Suboptions for the Generate list file option -Lflags
Assembler - diagnostics

Assembler - miscellaneous

Assemble case sensitive no option-c
Labels are by default:
- local (default) -il
- global -ig
Additional assembler options options
Command line only

Display invocation syntax -? / --help
Emit local symbols --emit-locals
Redirect diagnostic messages to a file --error-file[=file]
Select TASKING preprocessor or no preprocessor -m{t|n}
Specify name of output file -ofile
Generate NOPs for ROM monitor support (8051 only) --rom-monitor-nops
Use strict assembly syntax (Z80 only) --strict
Enable expression type checking --type-checking
6 - 18
Verbose information -v
Use Zilog assembly syntax (Z80 only) --zilogsyntax
4.6 Linker options
Figure 20. Specifying linker options for an embedded project.
The linker combines and transforms relocatable object files (.obj) into a single absolute object file.
This process consists of two phases: the linking phase and the locating phase.
In the first phase the linker combines the supplied relocatable object files (.obj files, generated by
the assembler) and libraries into a single relocatable object file. In the second phase, the linker
assigns absolute addresses to the object file so it can actually be loaded into a target.
The linker can simultaneously link and locate all programs for all cores available on a target board.
The target board may be of arbitrary complexity. A simple target board may contain one standard
processor with some external memory that executes one task. A complex target board may contain
multiple standard processors and DSPs combined with configurable IP-cores loaded in an FPGA.
Each core may execute a different program, and external memory may be shared by multiple cores.
Most linker options can be controlled via the project options dialog but some options are only
available as command line switches. The default options are generally sufficient for most
applications however should you find it necessary to tune the linker then further information can be
found in GU0105 Embedded Tools Users Guide.pdf or via the help system under Embedded
Software Development » Embedded Tools Options Reference » Linker Options.
A summary of the available linker options are listed below:
Linker - output format
Output format options Command line

Absolute file for debuggers -o[filename][:format[:addr_size][,space]]...
Intel Hex records or Motorola S-records -c[basename]:format[:addr_size],...
for EPROM programmers
6 - 19
Linker - libraries
Libraries options Command line

Link default C libraries -lx
(Do not) rescan libraries to solve unresolved --no-rescan
externals
Linker - optimization

Use a 'first fit decreasing' algorithm -Ol / -OL
Emit smart restrictions to reduce copy table size -Ot / -OT
Linker - map file
Map File options Command line

Generate a map file (.map) -M
Suboptions for the Generate a map file option -mflags
Linker - diagnostics

Linker - miscellaneous

(Do not) include symbolic debug information -S (strip debug)
Print the name of each file as it is processed -v
Link case sensitive (required for C language) no option --case-insensitive
Dump processor and memory info from LSL file --lsl-dump[=file]
Link incrementally --incremental
Use project specific linker script file -dfile
Additional linker options options
6 - 20
Command line only

Display invocation syntax -? / --help
Define preprocessor macro -Dmacro[=def]
Specify a symbol as unresolved external -esymbol
Redirect diagnostic messages to a file with extension --error-file[=file]
.elk
Scan libraries in given order --first-library-first
Search only in -L directories, not in default path --ignore-default-library-path
Link only, do not locate --link-only
Check LSL file(s) and exit --lsl-check
Do not generate ROM copy -N
Locate all ROM sections in RAM --non-romable
6 - 21
4.7 Compiler output

Files generated as a result of the build process are, by default, stored in the same directory as the
source files. To separate generated files from the source files, place an entry into the Output
Directory (instead of project directory): text box under the Build Options tab of the Project
Options… dialogue box.
Figure 21. Controlling the location of compiler output.
4.7.1 To compile a single source file:

• Open the document in the main window and select Project » Compile Document {docname}.
• Right-click on the document in the Projects panel and select Compile Document {docname}.
4.7.2 To compile an entire embedded project:

Open any one of the project’s source documents and select Project » Compile Embedded Project
project_name or select Project » Recompile Embedded Project project_name.
Right-click on the project in the Projects panel and select Compile Embedded Project project_name
or select Recompile Embedded Project project_name.
4.8 Exercise 2 – First compile

This exercise follows on from the previous exercise.
6. Right click on the embedded project in the Projects panel and select the Project Options…
menu item.
7. Set the Configuration to TASKING TSK51x/TSK52x.
8. Under the Build Options section, ensure that the Output directory is set to ‘Generated’ (See
Figure 21).
9. Click OK to close the dialog box.
10. Compile the Project. If any errors result, fix those errors.
11. Observe the files generated by the compiler. Scan through these files to satisfy yourself of their
contents.
6 - 22
5 Utilizing microprocessor softcores

An application is of no use without a target system for it to run on. In this section we will put the
finishing touches to an FPGA project that will contain a microprocessor softcore and serve as the
basis for our embedded platform.
5.1 How soft is a softcore?

Altium Designer comes bundled with a number of pre-verified, pre-synthesized microprocessor
softcores that can be incorporated into an FPGA project and execute application code. These
processors are labeled as soft because they are implemented as a downloadable core that runs from
an FPGA device rather than as a hard physical microprocessor in its own distinct package. By
utilizing softcores, the designer can select the most appropriate core for a given application without
needing to modify hardware.
Figure 22. Pictorial representation of a softcore loaded onto an FPGA device.
6 - 23
5.2 Using a softcore in an FPGA schematic

Building an FPGA project that incorporates a softcore is no different from building any other FPGA
project; you simply select components from a library and place them onto your schematic. The
FPGA softcores can be accessed from the integrated library: <Altium>/Library/FPGA/FPGA
Processors.IntLib
Figure 23. FPGA Processors.IntLib library contents with popup Help menu.
This library will grow as more and more processor cores become available.
5.2.1 Accessing softcore datasheets

Detailed data sheets can be accessed for each device by highlighting the device and selecting the
F1 key or by right-clicking the device and selecting Show Help for … (see Figure 23).
5.3 On-chip debugging or not?

When looking through the list of processors, you will notice the existence of ‘OCD’ microcontrollers
and non-OCD microcontrollers. The OCD microcontrollers contain additional On Chip Debugging
resources which are necessary if you wish to make use of Altium Designer’s debugging features.
One notable difference between the two microcontrollers is the existence of program memory write
resources on the OCD version. This is necessary since the debugger requires write access to
program memory so that it can place breakpoints in program memory when breaking or stepping
through code. Thus when using the OCD version, program memory must be comprised of read/write
memory. In general it is advisable to use the OCD version during development and switch back to
the non-OCD version for production.
6 - 24
U1 U1_OCD
CLK P0O[7..0] CLK P0O[7..0]
RST P0I[7..0] RST P0I[7..0]
EA EA
P1O[7..0] P1O[7..0]
SFRDATAO[7..0] P1I[7..0] SFRDATAO[7..0] P1I[7..0]
SFRDATAI[7..0] SFRDATAI[7..0]
P2O[7..0] P2O[7..0]
SFRADDR[6..0] P2I[7..0] SFRADDR[6..0] P2I[7..0]
SFRWR SFRWR
SFRRD P3O[7..0] SFRRD P3O[7..0]
P3I[7..0] P3I[7..0]
ROMDATAO[7..0]
ROMDATAI[7..0] MEMDATAO[7..0] ROMDATAI[7..0] MEMDATAO[7..0]
MEMDATAI[7..0] MEMDATAI[7..0]
ROMADDR[15..0] ROMADDR[15..0]
MEMADDR[15..0] ROMWR MEMADDR[15..0]
ROMRD MEMWR ROMRD MEMWR
MEMRD MEMRD
INT0 INT0 PSWR
INT1 PSRD INT1 PSRD
T0 T0
T1 T1
RXD RXD
TXD TXD
RXDO RXDO
TSK51A Microprocessor TSK51A OCD Microprocessor

TSK51A TSK51A_D
Figure 24. Comparing non-OCD and OCD microcontrollers.
5.4 Exercise 3 – Placing a softcore onto an FPGA schematic

A semi-complete project has been created in preparation for this exercise. Your instructor will tell
you where to find it on your local hard drive.
1. Open the FPGA_HelloWorld.PrjFpg FPGA project and open FPGA_HelloWorld.SchDoc.
Observe that no softcore has currently been placed.
2. Select the TSK51A_D processor from the FPGA Processors.IntLib library and place it onto
the schematic. Your schematic should appear the same as Figure 25.
3. Ensure that the pins of the softcore component are correctly connected and save your work.
6 - 25
Altium Designer Training Module LiveDesign
U8
CLK_BRD
CLK STATUS
U9 CLK_CAP
IA[7..0] O[15..0]
CHANNELS[15..0]
IB[7..0]
TRIGGER
J8B2_16B
Logic Analyser
LAX_1K16
CLK_BRD should be
set to 50MHz
U2
LCD_LIGHT P94
LCD_E P89
[7..0] LCD_RW P166
2 x 16 Liquid Crystal Display
CLK_BRD
P182 CLK_BRD LCD_RS P164
U3 [7..0] LCD_DB[7..0]
CLK P0O[7..0] P88,P87,P86,P84,P83,P82,P81,P75
U4 Reset IOBUF8B
RST P0I[7..0]
P3 TEST_BUTTON GND EA
U6 I[7..0] U5 O0
P1O[7..0]
O1
CLK INIT SFRDATAO[7..0] P1I[7..0]
O2 U7
OR2N1S SFRDATAI[7..0]
LEDS[7..0] O3
VCC DELAY[7..0] P2O[7..0] FREQA
O4
SFRADDR[6..0] P2I[7..0] FREQB
FPGA_STARTUP8 O5
SFRWR
O6 CLK_BRD
SFRRD P3O[7..0] TIMEBASE
U1 O7
P3I[7..0]
CLK DIN[7..0] ROMDATAO[7..0] J8B_8S
Frequency Counter
DOUT[7..0] ROMDATAI[7..0] MEMDATAO[7..0] FRQCNT2
MEMDATAI[7..0] LEDS[7..0]
ADDR[11..0] ROMADDR[15..0]
[11..0] [11..0] P55,P56,P57,P58,P59,P60,P61,P62
WE ROMWR MEMADDR[15..0]
ROMRD MEMWR
RAMS_8x4K
MEMRD
INT0 PSWR
INT1 PSRD
JTAG
T0
TDI JTAG_NEXUS_TDI P8
JTAG T1
JTAG
TDO JTAG_NEXUS_TDO P11
JTAG TCK JTAG_NEXUS_TCK P9
GND RXD
JTAG TMS JTAG_NEXUS_TMS P10
... TXD
JTAG RXDO
TRST VCC
TSK51A OCD Microprocessor
TSK51A_D
Figure 25. Schematic with the TSK51A_D softcore placed.
6 - 26
6 Linking an embedded project to the

hardware design
Having created an FPGA schematic that incorporates a softcore, the next task is to link the
application code to the softcore so that they get compiled together.
6.1 Project Hierarchies

Altium Designer supports a fully hierarchical
design approach. As such it is possible for some
projects to contain other projects within them.
Figure 24 shows a structural view of the
LCD_Keypad design that is distributed as an
example in the Altium Designer installation. From
this view we can observe the hierarchy of the
different projects involved.
The top-level project is an FPGA project called
LCD_Keypad and has the filename extension
PRJFPG.
Within the FPGA design is an instance of the
TSK51 embedded softcore.
The program or software that this embedded
softcore executes is contained within another
project called LCD.PrjEmb.
Furthermore the LCD_Keypad FPGA project also
makes use of a core component called
KeyPadScanner which has been defined as a core
project (extension PRJCOR).
A PCB Project may contain one or more FPGA
projects but never the other way around. If you
think about it you will recognize that it is quite
intuitive; a PCB contains FPGAs whereas an
FPGA can’t contain a PCB. Similarly, an FPGA
could contain one or more custom FPGA cores or
microprocessor softcores. A unique Core Project
will define each FPGA core component and a
unique Embedded Project will define the software
that executes on each of the softcores.
The hierarchy of the LCD_Keypad project is given
below. Figure 26. LCD_Keypad structural view
PRJPCB PCB Project Output is a single PCB
PRJFPG FPGA Project Output is a single FPGA
Source code for a program that will execute

PRJEMB Embedded Project on a single Softcore
Figure 27. Possible project hierarchy for a design containing multiple projects.
6 - 27
6.2 Attaching an embedded project to an FPGA project

Creating a link between the softcore and its
associated embedded code ensures that
correct code / processor coupling is made. It
also ensures that subsequent project builds
incorporate all hardware and software changes
that have been made.
The process of linking an FPGA Project to its
associated embedded code first requires that
both projects are open together. Figure 28
shows two projects open together prior to being
linked. These two projects are not bound in
any way – they are just two distinct projects
that happen to be open at the same time.
To link the Embedded Project to the FPGA
Project we must utilize the Structure Editor.
6.2.1 The Structure Editor

A project can be viewed in one of two ways in Figure 28. Unlinked projects
the Projects Panel.
File View Structure Editor
Figure 29. Linked projects (File View). Figure 30. Linked projects (Structure Editor).
In the File View, files are grouped primarily In the Structure Editor, the hierarchical linkage
according to which project they are a part of between projects is shown – i.e. above we see
and secondarily according to the file type – that the HelloWorld embedded project has
schematic, PCB, settings, etc. been linked to U3 (the TSK51 core) in the
FPGA_HelloWorld FPGA project.
6 - 28
6.2.2 Linking the projects

Linkage between projects is created
and broken using drag-and-drop. By
click-and-holding the left mouse
button on a sub-project, all possible
drop locations (valid linkage points)
will highlight in blue and the sub-
project can be drag-and-dropped
onto the parent project to create the
link.
To break the linkage, drag the sub-
project away from the parent project
and drop it on a clear region of the
Structure Editor.
Alternatively you can right click on

the processor and specify the
embedded project using the Set
Embedded Project menu option Figure 31. Linking an embedded project to its hardware
(Figure 32).
Figure 32. Linking an embedded project to a processor via the schematic interface.
6 - 29
6.3 Linking program memory to the processor core

Having linked the embedded project to its hardware, the final task now is to formally notify the
softcore of which schematic component contains its program memory. This is done via the
Component Properties dialog which is accessible by double-clicking on the processor symbol in the
schematic.
U3
CLK P0O[7..0]
RST P0I[7..0]
EA
P1O[7..0]
SFRDATAO[7..0] P1I[7..0]
SFRDATAI[7..0]
P2O[7..0]
SFRADDR[6..0] P2I[7..0]
SFRWR
SFRRD P3O[7..0]
U1
P3I[7..0]
CLK DIN[7..0] ROMDATAO[7..0]
DOUT[7..0] ROMDATAI[7..0] MEMDATAO[7..0]
MEMDATAI[7..0]
ADDR[11..0] ROMADDR[15..0]
[11..0] [11..0]
WE ROMWR MEMADDR[15..0]
ROMRD MEMWR
RAMS_8x4K
MEMRD
INT0 PSWR
INT1 PSRD
T0
T1
RXD
TXD
RXDO

TSK51A_D
Figure 33. Softcore connected to its program memory.
Figure 34. Specifying which component contains the softcore’s program memory
6 - 30
Making this link in the schematic will ensure that both software and hardware is correctly loaded onto
the target processor when we build and download the design to the NanoBoard.
6.4 Exercise 4 – Linking projects

1. With Exercise 3 still open, also open the HelloWorldPrj.PrjEmb project that you will find in
the /Application directory under the main project directory.
2. Link the two projects as described in 6.2.2.
3. Once the projects have been correctly linked, they should appear as they do in Figure 29 &
Figure 30. Notice that HelloWorldPrj.PrjEmb is now listed as a sub-project of
FPGA_HelloWorld.PrjFpg.
4. Also link the program memory as describe in 0.
5. You can try unlinking the two projects again by dragging the linked embedded project off U3 in
the structure editor.
6. Save your work.
6 - 31
7 Putting wheels on LiveDesign

In this section we will demonstrate the true flexibility that the LiveDesign methodology offers as we
develop the code necessary to drive an LCD.
7.1 The printf dilemma

Our example “Hello World” application is a standard application used as an introduction to most
development environments and languages. In our system, however, it is impossible for the compiler
to know that we have an LCD connected to one of the ports and that it is capable of accepting ASCII
data. Subsequently, the printf command that we use in our code is meaningless since the output
has nowhere to go.
It would be possible to delve into the heart of the compiler’s library code and modify the printf
code to direct its output to the LCD but this would be an overly complex way of addressing our
problem. A simpler solution would be to create a custom function that accepts a string as input and
sends it to the LCD display.
7.2 Initializing the LCD

Figure 35 shows a typical flow diagram for initializing an LCD module. You will note that a number of
time delays are required between successive commands to the LCD.
Figure 35. LCD Initialization sequence.
6 - 32
7.2.1 Using the supplied LCD control module

Contained within the Altium Designer FPGA U?
Peripherals.IntLib library is the LCD16X2A CLK LCD_E
component. This component automates much of RST LCD_RW
LCD_RS
the LCD initialization process and provides an easy DATA[7..0]
method for writing to any segment of the display. ADDR[3..0] LCD_DATA_TRI
LINE
Under normal production situations, we would LCD_DATAO[7..0]
make use of this component in our schematic BUSY
however for today’s purposes we will not be using STROBE LCD_DATAI[7..0]
it. Instead we shall connect directly to the LCD LCD16X2A
peripheral and perform the initialization process Figure 36. LCD Controller
ourselves in software.
Note: The LCD control module supplied with Altium Designer is very capable for standard character
display however in our final application that we will develop to completion on Day 3, we need to be
able to create our own characters in the LCD. The LCD control module does not allow this and so
we must ‘roll our own’ LCD interface.
7.2.2 Developing a custom LCD software module

Because we will not be using the supplied LCD module, we shall have to implement a timing routine
as part of our application code. We could hand assemble a routine and calculate the number of
loops required based on the processor clock speed and the instruction timing information however
this is a time consuming activity. Utilizing the burn and learn strategy afforded by the Altium
Designer environment, we can achieve our desired outcome far quicker.
6 - 33
7.3 Exercise 5 – Using LiveDesign to initialize an LCD

In this exercise we will make use of an embedded frequency counter instrument to tune a software
delay loop to a prescribed time and a Logic Analyzer instrument to verify the operation of our LCD
Read and Write routines. A semi-complete project has been prepared and your instructor will tell
you where to find it on your local hard drive.
7.3.1 Tune software timing loop

1. Open the provided project and look at the Schematic. You will notice a Frequency Counter
instrument (U7) connected to one of the microprocessor port pins.
U8
CLK_BRD
CLK STATUS
U9 CLK_CAP
IA[7..0] O[15..0]
CHANNELS[15..0]
IB[7..0]
TRIGGER
J8B2_16B
Logic Analyser
LAX_1K16
U2
LCD_LIGHT P94
LCD_E P89
[7..0] LCD_RW 2 x 16 Liquid Crystal Display P166
LCD_RS P164
U3 [7..0] LCD_DB[7..0]
CLK P0O[7..0] P88,P87,P86,P84,P83,P82,P81,P75
IOBUF8B
RST P0I[7..0]
EA
I[7..0] U5 O0
P1O[7..0]
O1
SFRDATAO[7..0] P1I[7..0]
O2 U7
SFRDATAI[7..0]
LEDS[7..0] O3
P2O[7..0] FREQA
O4
SFRADDR[6..0] P2I[7..0] FREQB
O5
SFRWR
O6 CLK_BRD
SFRRD P3O[7..0] TIMEBASE
O7
P3I[7..0]
ROMDATAO[7..0] J8B_8S
Frequency Counter
ROMDATAI[7..0] MEMDATAO[7..0] FRQCNT2
MEMDATAI[7..0] LEDS[7..0]
ROMADDR[15..0]
P55,P56,P57,P58,P59,P60,P61,P62
ROMWR MEMADDR[15..0]
ROMRD MEMWR
MEMRD
INT0 PSWR
INT1 PSRD
T0
T1
RXD
TXD
RXDO

TSK51A_D
Figure 37. ‘Hello World’ application with Frequency counter and Logic Analyzer connected.
2. Open the HelloWorld.C file and observe the software delay loop that has been coded into the
Wait_100us function. The controlling constant is defined as US_COUNT. Currently it is set to 1.
Our task is to determine a better value for US_COUNT that will yield a delay of at least 100us.
3. Notice the use of a #ifdef CHK_TIMER statement in main(). This statement controls
conditional compilation of the program. For instance, if the constant CHK_TIMER has been
defined, the software code between the #ifdef and #else will be compiled. If CHK_TIMER has
not been defined, the code between #else and #endif at the bottom of main(). By inserting
statements such as this around code that you may wish to use for debugging purposes greatly
reduces development time.
CHK_TIMER can be defined using a #define CHK_TIMER statement earlier in the program
however we are going to pass it into the compilation as a project setting.
6 - 34
Figure 38. Using a #ifdef statement to conditional compile code
4. Open the Options for Embedded Project dialog box by right-clicking the embedded project in
the Project panel.
Figure 39. Accessing the project options dialog
5. Under the Compiler Options tab, find the Preprocessing item under the C Compiler group.
Ensure that a User Macro called CHK_TIMER is defined. This will ensure that CHK_TIMER is
defined when we compile the project.
6 - 35
Figure 40. Specifying a user defined macro
6. From the Devices View, build and download the project to the NanoBoard.
7. Set the NanoBoard clock to 50Mhz.
Figure 41. Set the NanoBoard clock to 50Mhz
8. Open the frequency counter instrument panel and ensure that its clock reference is also 50Mhz.
Observe the period recorded by the frequency counter module.
Figure 42. Observe the initial delay period
9. Try changing the value of US_COUNT to tune the software delay loop to be exactly 100us. Take
note that the period displayed is equal to twice the software delay period since the software
delay is used on both the high and low phases of the signal being fed to the frequency counter.
Note: It is not necessary to rebuild the entire project after each software update has been made.
Locate the Compile and Download button in the toolbar. Pressing this after each software
adjustment will cause only the embedded code to be recompiled and loaded into the FPGA for
immediate execution.
6 - 36
Figure 43. Adjust the value of US_COUNT to produce a period of 200us.
10. Modify the two wait statements in the main() routine from Wait_100us(1) to Wait_1ms(1).
The constant that controls this loop is ONE_MS_COUNT. Tweak the value of this constant to
achieve a 1ms delay.
Figure 44. Adjust the value of ONE_MS_COUNT to produce a 2ms period.
7.3.2 Verify LCD write operation

Our next task is to verify the operation of our LCD read and write routines and to ensure they comply
with the timing requirements of the LCD. For this we will use the logic analyser instrument.
1. In the Options For Embedded Project… dialog remove the CHK_TIMER macro and replace it
with CHK_WRITE_LCD.
2. Rebuild the embedded project and download the code to the NanoBoard.
3. Open the logic analyser control panel.
Figure 45. Logic analyser control panel
4. Select the Options button on the logic analyser

panel and check the Capture Every Clock Edge
and Enable External Trigger checkboxes. Also
ensure the Clock Capture Frequency is set to
50MHz. Click on OK to close the dialog box.
5. Click on the Arm button on the Logic Analyser
Control panel.
6. Click the Show Waves button next to the
DIGITAL label on the logic analyser control panel.
The waveform viewer window will open in the
main screen.
7. Select the Continuous Capture icon in the

main toolbar to see a continuous update of the
waveform window.
Figure 46. Logic analyser options
6 - 37
Figure 47. Digital waveform view – write LCD.
8. If the labels next to each of the signals are not set, update them to appear as they do in Figure
47.
9. To zoom in or out of the digital waveform view, first ensure that the waveform viewer has the
focus and then press the keyboard Page Up or Page Down keys as you would in any other
Altium Designer document. Ensure that you can see at least one full pulse of the Enable signal.
10. Right-click in the digital waveform view area to reveal a pop-up menu. Select the Measure Time
option. Left-click on two locations within the waveform viewer to measure the time between
them.
Figure 48. Measure time between selected events
11. Verify that the LCD write timing waveform complies with the datasheet requirements of Figure 49
and Figure 50.
Figure 49. LCD write timing requirements
6 - 38
Figure 50. LCD Write Waveform
7.3.3 Verify LCD read operation

1. In the Options for Embedded Project… dialog, remove the CHK_WRITE_LCD macro and
replace it with CHK_READ_LCD.
2. Rebuild the embedded project and download the code to the NanoBoard.
3. Once again view the logic analyser and observe the output waves.
Figure 51. Digital waveform view - read LCD
4. Verify that the LCD read timing waveform complies with the datasheet requirements of Figure 52
and Figure 53.
Figure 52. LCD read timing requirements
6 - 39
Figure 53. LCD read waveform
5. Save your work once you have finished.
7.3.4 LCD instruction definitions
6 - 40
Figure 54. LCD instruction definitions
6 - 41
8 Debugging the design

In this section we will review the debugging features that are a part of the Altium Designer
development system.
8.1 A word about simulation

In general, it is desirable to interact with real hardware when debugging rather than performing
simulations only. The presence of the NanoBoard means that most designs can be debugged in real
hardware, i.e. LiveDesign, however there may be the odd occasion when it is necessary to simulate
a design.
The Altium Designer development environment supports full simulation based debugging as well as
LiveDesign using real hardware; the interface is identical. Switching between LiveDesign and
Simulation is achieved by changing the debugger mode via the Debug » Current Debugger Mode
menu option available when editing an embedded project source document.
For our discussions we shall focus on the LiveDesign environment, as this is usually the most
desirable mode of debugging however all that is mentioned here is applicable to the simulation
environment also.
The easiest way to initiate a debugging / simulation session is to right-click the embedded project in
the Projects panel and selecting Debug or Simulate. Of course, the Debug option is only available
if a NanoBoard or target platform is present and powered up.
8.2 The Debug menu

Debug commands are available whenever an embedded source file is open in the main window. Debug
commands can be accessed via the Debug toolbar:
Figure 55. Debug toolbar
Or from the Debug menu:

Current Debugger Mode: Use this menu item to
select between simulation mode or LiveDesign. If
more than one processor is present on the target
design then you will have to select which device is
the target of debugging commands.
Run (F9): Run the current embedded project in
debug mode. After launching the command,
execution of the code in the embedded software
program will begin. If any enabled breakpoints have
been setup, code execution will halt at these points,
if encountered
Run to Cursor (Ctrl+F9): Execute the embedded
code up to the line containing the cursor.
Toggle Breakpoint (F5): This command is used to
toggle an enabled breakpoint for the current line.
After launching the command, the current line will
have an enabled breakpoint added to it or removed
from it, depending on whether or not an enabled
breakpoint currently exists for that line.
Figure 56. Debug menu
6 - 42
Enabled breakpoints are indicated in the code by a red highlight over the breakpoint line and a red
circle with a cross in the margin.
Disabled breakpoints are indicated in the code by a green highlight over the breakpoint line and a
green circle with a cross in the margin. A disabled breakpoint remains defined but will not cause
running code to halt when encountered.
If a disabled breakpoint exists for the line and this command is used, the breakpoint will be removed.
You can view a list of all breakpoints that have currently been defined in all open embedded project
source code files, in the Breakpoints panel.
Add Watch: This command enables you to define watch expressions for the current embedded
source code document. A watch expression can be a single variable or an expression containing one
or more variables and allows you to view the value of the expression as you step through the code.
Basic mathematical operations are supported (e.g. a+b, a*b, c+(b-a)).
Step Into (F7): Use this command to execute each line of the current embedded source code
sequentially, including the individual lines of code contained within any procedures/functions that are
called. The next executable line of code is highlighted in blue and is indicated by a blue circle with
an arrow in the margin.
Step Over (F8): The same as the Step Into command except procedure/function calls are treated as
a single line of code and executed as a single step.
Step Into Instruction (Shift+F7): This command is used to execute each individual instruction at the
assembly code level, in turn, including the instructions contained within any functions that are called.
When the source code document is an .asm file, the next executable instruction is highlighted in
blue and is indicated by a blue circle with an arrow in the margin. This command and the Step Into
Source command will behave in the same way.
When the source code is a high level language (.c file), use of this command should ideally be made
from within one of the two disassembly views for the code - either the extended mixed source-
disassembly view (accessed by clicking the Show Disassembly button on the debug toolbar in the
source code view), or the pure disassembly view (accessed by clicking the Toggle Source Code
button on the disassembly standard toolbar, from within the mixed source-disassembly view).
In both mixed and pure disassembly views, the next executable instruction is highlighted in dark blue
and is indicated by a dark blue circle with an arrow in the margin.
Step Over Instruction (Shift+F8): The same as the Step Into Instruction command except
procedure/function calls are treated as a single line of code and executed as a single step.
Step Out: This command is used to step out of the current function within the embedded source
code. The remaining executable code within the current function will be executed and the execution
will be passed onto the next sequential line of code after the function's calling statement.
Show Disassembly: Open an intermixed source and disassembly view for the current embedded
software project. A new view will open as the active view in the main design window. This view
shows a mixture of disassembled instructions and source (C) code. The source for all source code
files in the current embedded project will be displayed.
In this intermixed disassembly and source view, the next executable source line is highlighted in blue
and is indicated by a blue circle with an arrow in the margin. The next executable disassembled
instruction is highlighted in dark blue and is indicated by a dark blue circle with an arrow in the
margin.
Resynchronize: Use this command to synchronize the debugger execution point with the external
hardware.
Show Execution Point: Position the text cursor at the start of the next line of code to be executed. If
the next executable line of code is outside of the visible area of the main display window, the
document will be panned to bring it into view.
Break: Halt an executing processor at the next executable line of source code.
Reset (Ctrl+F2): Reset the executing processor currently being debugged, at any stage when
stepping through code or after a breakpoint has been encountered, and return the current execution
point back to the first line of executable code.
Stop Debugging (Ctrl+F3): Terminate the current debugging session.
6 - 43
8.3 Embedded control panels
Figure 57. Available embedded panels
Clicking on the Embedded button of the workspace panels will open the list of embedded control
panels. Alternatively use the menu commands by selecting View » Workspace Panels »
Embedded.
Selecting F1 whilst an item within a panel has the focus will bring up extensive help on the panel’s
operation.
8.3.1 Code Explorer

The Code Explorer provides a convenient summary and
navigation tool for accessing all of the functions and
variables defined within the source code. Double-clicking
on any of the items in the Code Explorer panel will
immediately transfer the cursor in the main window to the
location where the selected variable or function is
declared.
8.3.2 Call Stack

When an executing processor is paused, the Call Stack
panel shows the function call sequence that has lead to
the current line of execution. Beside each called function
is the source code line that processing will return to after
the subroutines are executed.
Figure 58. Code explorer panel Figure 59. Call stack panel
6 - 44
8.3.3 Watches
Use the Watches panel to see the value of selected variables. Watched variables will be updated
automatically when a running processor is paused and as each line of source code is stepped
through.
For variables to be viewable in the Watches panel they must be within the scope of the current
execution point within the source code. For example, variables local to a specific function will not be
viewable whilst code outside of that function is being executed.
Watched variables can be added, deleted, edited and enabled/disabled from the popup menu that
appears upon a mouse right-click from within the Watches panel.
Watches are extremely flexible in that they can be displayed in a number of different formats.
Formatting options can be accessed by right clicking a watch variable and selecting Edit.
Figure 61. Edit watch dialog
Figure 60. Watches panel
Changing the display style of the watch

to anything other than [Default] will
place a format specifier in the watch
declaration. This format specifier can
be used in a number of other panels
also.
Figure 63. Watches panel with format

Figure 62. Watch format dialog
specifiers
6 - 45
8.3.4 RTOS
Figure 64. RTOS panel
The RTOS panel has a number of sub-panels which can be activated via the Debug » RTOS menu
option. Note that this menu option only becomes available when an RTOS embedded project is
paused during execution.
The different sub-panels enable the user to track RTOS pertinent information such as System
Status, Concurrent Tasks, Resources, Messages, and Alarms. For further information regarding
RTOS and Altium Designer support for RTOS projects, read GU0102 8051 RTOS.pdf in the or
access this document from the help contents under Embedded Software Development » 8051
RTOS Guide.
6 - 46
8.3.5 Registers
The Registers panel provides a
central point for viewing and
modifying processor registers.
Useful when debugging lines of
assembly source, the Registers
panel provides a line-by-line update
of the state of key processor
resources.
Variables in the Registers panel
can be modified by clicking on one
of the values in the Decimal,
Hexadecimal or Binary columns and
updating the value. This value shall
remain and be used in subsequent
lines of code.
Figure 65. Registers panel
8.3.6 Locals
When an executing processor is paused, the Locals
panel will display a snapshot of the variables that
are local to the currently executing function.
Variables will be updated as each line of source
code is executed. The Locals panel is
complementary to the Watches panel as it does not
get cluttered with information of variables outside of
the scope of the currently executing function.
Figure 66. Locals panel
8.3.7 Evaluate
The Evaluate panel provides a quick means for
determining the value of a variable or expression.
Expression syntax must follow C standards and
variables contained within an expression must be
within the scope of the currently executing function.
Evaluated values or expressions are not updated
whilst the code is stepped through however repeat
evaluations can be made by selecting the Evaluate
button. Alternatively, variables can be added to the
Watches panel by selecting the Add Watch button.
The Evaluate window is also useful for determining
the address of a variable so that it can be located
within one of the memory panels or, in the case of
registers, in the registers panel.
Figure 67. Evaluate Panel
6 - 47
8.3.8 Cross References

The Cross references panel can be used to quickly find out all occurrences of a given symbol in the
source files and optionally jump to each location. For example, one could be interested to check all
the places where a specific variable is addressed, or a function is called.
Left-clicking once on the variable in the top pane of the Cross References panel will cause the
bottom pane to show the associated line of source code.
Double-clicking the variable in the top pane will cause the main editor window to jump to the
associated line of source code.
Figure 68. Using cross references to navigate around a document
8.3.9 Enabling cross references

Before cross references can be used, the feature must first be enabled in the editor. With a C file
open in the main window, select the Tools » Editor Preferences… from the menu.
Figure 69. Enabling cross reference libraries (code sources)
6 - 48
The Library Name is simply used as a meaningful identifier in the Library Databases – the system
does not use this field in any way.
The Library Root specifies the root folder where the source files are located.
Full Source controls whether C files should be processed. If this option is left unchecked only
header files (.H) will be scanned.
Once the cross reference libraries have been set up, the Cross References panel can be used from
the editor. Right click any identifier, and select Show Cross-References from the popup menu. The
Cross References panel will be displayed revealing all occurrences of the selected identifier:
8.3.10 Debug Console

The Debug Console provides a
record of the debugging session
and the debugging commands
that have been executed.
The Debug Console is based
heavily on Tasking’s CrossView
technology and so many of the
CrossView commands are also
valid here.
Figure 70. Debug console panel
8.3.11 Breakpoints
Figure 71. Specifying breakpoints
Use breakpoints to halt the processor execution at a specified line of source code. The properties of
a breakpoint accessed by right-clicking an item in the Filename/Address column of the Breakpoints
panel and selecting Properties from the popup menu.
The Count value identifies how many times the breakpoint will be hit and continue before stopping (it
stops when the count gets to 0).
Reset Count is a number that is reloaded into Count once Count gets to zero and stops.
Condition can contain a test expression that will be evaluated at the point of the breakpoint. If the
expression is true then the debugger will pause.
6 - 49
8.3.12 Memory
Altium Designer contains a powerful memory display tool that is capable of viewing multiple memory
spaces concurrently. Memory data is displayed using both hexadecimal and ASCII character
notation.
Figure 72. Memory panels
For debugging purposes it is often necessary to modify the contents of memory to provoke a certain
response from the processor. This is possible via the Memory panel. Click on one of the
hexadecimal cells and type in the new hexadecimal value. The memory will automatically refresh
with the new value. The Memory panel does not discern between read only and read-write memory.
If the user attempts to alter memory that is not writeable, the request will be rejected and the memory
location will remain unchanged.
The Memory panels always number the memory spaces they represent from 0 regardless of where
the memory space physically resides in the processor’s memory map. For instance, the Special
Function Register (SFR) space of the 8051 architecture is located between 80h and FFh of the
Internal RAM. The starting address of the SFR Memory panel is listed as 0000h (not 0080h).
Blocks of memory can be highlighted by left-click and dragging across multiple cells. Pressing the
Alt key whilst dragging will drag a rectangle. Once highlighted, memory cells can be used as the
basis for read, write or read/write breakpoints however this feature is only available in simulation
mode.
8.4 Exercise 6 – Code Debug

This exercise is based on the work previously done in exercise 5.
1. You will notice that the ’Hello World’ text scrolls across the screen but doesn’t go all the way
to the left-most character position. Your task is to rectify the problem so that ’Hello World’
scrolls across the screen and stops in the left-most character position.
2. Using breakpoints, single stepping, and variable watching, attempt to track down and rectify the
error(s) in the source code.
6 - 50
9 Advanced compiler features

9.1 C language extensions
The TASKING compiler(s) fully support the ISO C standard and add extra possibilities to program
the special functions of the individual targets.
In addition to the standard C language, the compiler supports the following:
• extra data types, like __fract and __accum for targets on which these data types can be
supported
• intrinsic (built-in) functions that result in target specific assembly instructions
• pragmas to control the compiler from within the C source
• predefined macros
• the possibility to use assembly instructions in the C source
• keywords to specify memory types for data and functions
• attributes to specify alignment and absolute addresses
• keywords for inlining functions and programming interrupt routines
• libraries
All non-standard keywords have two leading underscores (__).
In this section the target specific characteristics of the C language are described, including the above
mentioned extensions.
Note: For the 165x no compiler is available.
9.2 Supported data types

Type C Type Size Align Limits Support
(bit) (bit)
c51 cz80
Bit __bit 1 1 0 or 1
Boolean _Bool 1 8 0 or 1
7 7
Character [signed] char 8 8 -2 .. 2 -1
8
unsigned char 8 8 0 .. 2 -1
Integral [signed] short 15 15

16 8 -2 .. 2 -1
[signed] int
Enum 1 1 0 or 1
7 7
8 8 -2 .. 2 -1
15 15
16 8 -2 .. 2 -1
unsigned short 16
16 8 0 .. 2 -1
unsigned int
31 31
[signed] long 32 8 -2 .. 2 -1
32
unsigned long 32 8 0 .. 2 -1
31 31
[signed] long long 32 8 -2 .. 2 -1
32
unsigned long long 32 8 0 .. 2 -1
6 - 51
Pointer pointer to __data, __idata, 16

8 8 0 .. 2 -1
__pdat or __bit
pointer to function, 16
16 8 0 .. 2 -1
__xdata or __rom
Floating float -3.402e38 .. -

Point 1.175e-38
32 8
1.175e-38 ..
3.402e38
double -3.402e38 .. -
long double 1.175e-38
32 8
1.175e-38 ..
3.402e38
Notes
• The long long types are treated as long.
• The double and long double types are always treated as float.
• When you use the enum type, the compiler will use the smallest sufficient type (__bit, char or
int), unless you use compiler option --integer-enumeration (always use 16-bit integers for
enumeration).
The following rules apply to __bit type variables:
1. A __bit type variable is always unsigned.
2. A __bit type variable can be exchanged with all other data type-variables. The compiler
generates the correct conversion.
3. __bit type variable is like a boolean. Therefore, if you convert an int type variable to a __bit
type variable, it becomes 1 (true) if the integer is not equal to 0, and 0 (false) if the integer is 0.
The next two C source lines have the same effect:
t_variable = int_variable;
bit_variable = int_variable ? 1 : 0;
4. Pointer to __bit is allowed, but you cannot take the address of a bit on the stack.
5. The __bit type is allowed as a structure member. However, a bit structure can only contain
members of type __bit, and you cannot push a bit structure on the stack or return a bit
structure via a function.
6. A union of a __bit structure and another type is not allowed.
7. A __bit type variable is allowed as a parameter of a function.
8. A __bit type variable is allowed as a return type of a function.
9. A __bit typed expression is allowed as switch expression.
10. The sizeof of a __bit type is 1.
11. A global or static __bit type variable can be initialized.
12. A __bit type variable can be declared volatile.
9.3 Memory type qualifiers
9.3.1 Memory type qualifiers for the 8051

In the C language you can specify that a variable must be located in a specific part of memory. You
can do this with a memory type qualifier.
For the 8051 you can specify the following memory types:
Qualifier Description
__data Direct addressable on-chip RAM
6 - 52
__sfr Defines a special function register. Special optimizations are performed on

this type of variables.
__bsfr Bit-addressable special function register
__idata Indirect addressable on-chip RAM
__bdata Bit-addressable on-chip RAM
__xdata External RAM
__pdata One 256 bytes page within external RAM
__rom Data defined with this qualifier is placed in ROM. This section is excluded
from automatic initialization by the startup code. __rom always implies the
type qualifier const.
If you do not specify a memory type qualifier for the 8051, the memory type for the variable depends on the
default of the selected 8051 memory model.
Examples using explicit memory types
__data char c;
__rom char text[] = "No smoking";
__xdata int array[10][4];
__idata long l;
The memory type qualifiers are treated like any other data type specifier (such as unsigned). This
means the examples above can also be declared as:
char __data c;
char __rom text[] = "No smoking";
int __xdata array[10][4];
long __idata l;
Pointers
Pointers for the 8051 can have two types: a 'logical' type and a memory type. For example, a
function is residing in ROM (memory type), but the logical type is the return type of this function.
Example using memory types with pointers
__rom char *__data p; /* pointer residing in data,
pointing to ROM */
means p has memory type data (allocated in on-chip RAM), but has logical type 'character in target
memory space ROM'. The memory type qualifier used left to the '*', specifies the target memory of
the pointer, the memory type qualifier used right to the '*', specifies the storage memory of the
pointer.
The memory type qualifiers are treated like any other data type specifier (like unsigned). This means
the pointer above can also be declared (exactly the same) using:
char __rom *__data p; /* pointer residing in data,
pointing to ROM */
The 8051 C compiler is very efficient in allocating pointers, because it recognizes far (2 byte) and
near (1 byte) pointers. Pointers to __data, __idata and __pdata have a size of 1 byte, whereas
pointers to __rom, __xdata and functions (in ROM) have a size of 2 bytes.
Structure tags
A tag declaration is intended to specify the layout of a structure or union. If a memory type is
specified, it is considered to be part of the declarator. A tag name itself, nor its members can be
bound to any storage area, although members having type "... pointer to" do require one. A tag may
then be used to declare objects of that type, and may allocate them in different memories (if that
declaration is in the same scope). The following example illustrates this constraint.
6 - 53
struct S {
__xdat int i; /* referring to storage: not correct */
__idat char *p; /* used to specify target memory: correct */
};
In the example above the 8051 compiler ignores the erroneous __xdat memory type qualifier
(without displaying a warning message).
Typedef
Typedef declarations follow the same scope rules as any declared object. Typedef names may be
(re-)declared in inner blocks but not at the parameter level. However, in typedef declarations,
memory type qualifiers are allowed. A typedef declaration should at least contain one type
qualifier.
Example using memory types with typedefs
typedef __idat int IDATINT; /* memory type __idat: OK */
typedef int __data *DATAPTR; /* logical type __data
memory type 'default' */
9.3.2 Memory type qualifiers for the Z80

In the C language you can specify that a variable must be located in a specific part of memory. You
can do this with a memory type qualifier.
For the Z80 you can specify the following memory types:
Qualifier Description
__sfr Defines a special function register. Special optimizations are performed on
this type of variables.
__sfr8 Defines an 8-bit special function register
__rom Data defined with this qualifier is placed in ROM. This section is excluded
from automatic initialization by the startup code. __rom always implies the
type qualifier const.
Example using explicit memory types
__rom char text[] = "No smoking";

The memory type qualifiers are treated like any other data type specifier (such as unsigned). This
means the example above can also be declared as:
char __rom text[] = "No smoking";
9.4 Accessing hardware from C: __sfr, __bsfr

Using special function registers
It is easy to access Special Function Registers (SFRs) that relate to peripherals from C. The SFRs
are defined in a special function register file (*.sfr) as symbol names for use with the compiler. An
SFR file contains the names of the SFRs and the bits in the SFRs.
Example use in C:
P0 = 0x88; // use port name
P1_3 = 1; // use of bit name
if (P1_4 == 1)
{
P1_3 = 0;
}
IE1 = 1; // use of bit name
6 - 54
The compiler generates (TSK51A):

mov 128,#136
setb 144.3
gjnb 144.4,_2
clr 144.3
_2:
setb 136.3
You can easily find a list of defined SFRs and defined bits by inspecting the SFR file for a specific core. The files
are named regcore.sfr, for example regtks51a.sfr in the Altium Designer
6\System\Tasking\c51\include directory.
Defining special function registers

With the __sfr memory type qualifier you can define a symbol as an SFR. The compiler may
assume that special SFR operations can be performed on such symbols. The 8051 compiler can
decide to use bit instructions for those special function registers that are bit accessible, in this case
use __bsfr instead of __sfr. For example, if bits are defined in the SFR definition, these bits can
be accessed using bit instructions.
For the 8051 only the SFRs at addresses 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, 0xc0,
0xc8, 0xd0, 0xd8, 0xe0, 0xe8, 0xf0 and 0xf8 are bit addressable.
A typical definition of a special function register looks as follows:
typedef struct
unsigned int __b0:1;
} __t_sfrbits;
#define P0 (*(__bsfr volatile unsigned char *)0x80)
#define P0_0 ((*(__bsfr volatile __t_sfrbits *)0x80).__b0)
#define P0_1 ((*(__bsfr volatile __t_sfrbits *)0x80).__b1)
#define SP (*(__sfr volatile unsigned char *)0x81)
#define TCON (*(__bsfr volatile unsigned char *)0x88)
#define IT0 ((*(__bsfr volatile __t_sfrbits *)0x88).__b0)
#define IE0 ((*(__bsfr volatile __t_sfrbits *)0x88).__b1)
Example of access to the SFR:

P0 = 0x56;
P0_0 = IE0;
This example only contains byte and single bit SFRs. Different sized SFRs are also supported with a
specific struct definition.
For example:
typedef struct
{
unsigned int __b0s3:3;
} __t_sfr_ctrl_bit;
#define CTRL (*(__sfr volatile unsigned char *)0x95)
#define CTRL_ST ((*(__sfr volatile __t_sfr_ctrl_bit *)0x95).__b0s3)
#define CTRL_CL ((*(__sfr volatile __t_sfr_ctrl_bit *)0x95).__b3s2)
6 - 55
#define CTRL_IN ((*(__sfr volatile __t_sfr_ctrl_bit *)0x95).__b5s3)

Non-initialized global SFR variables are not cleared at startup. For example:
__sfr int i; // global SFR not cleared
It is not allowed to initialize global SFR variables. SFR variables are not initialized at startup. For example:
__sfr int j=10; // not allowed to initialize global SFR
9.5 Placing an object at an absolute address: __at()

Just like you can declare a variable in a specific part of memory (using memory type qualifiers), you
can also place an object at an absolute address in memory. This may be useful to interface with
other programs using fixed memory schemes, or to access special function registers.
With the attribute __at() you can specify an absolute address.
Examples
unsigned char Display[80*24] __at( 0x2000 );
The array Display is placed at address 0x2000. In the generated assembly, an absolute section is
created. On this position space is reserved for the variable Display.
int i __at( 0x1000 ) = 1;
The variable i is placed at address 0x1000 and is initialized at 1.
void f( void ) __at( 0xf0ff + 1 ) {}
The function f is placed at address 0xf100.
Restrictions
Take note of the following restrictions if you place a variable at an absolute address:
• The argument of the __at() attribute must be a constant address expression.
• You can place only global variables at absolute addresses. Parameters of functions, or automatic
variables within functions cannot be placed at absolute addresses.
• When declared extern, the variable is not allocated by the compiler. When the same variable is
allocated within another module but on a different address, the compiler, assembler or linker will
not notice, because an assembler external object cannot specify an absolute address.
• When the variable is declared static, no public symbol will be generated (normal C behavior).
• You cannot place structure members at an absolute address.
• Absolute variables cannot overlap each other. If you declare two absolute variables at the same
address, the assembler and / or linker issues an error. The compiler does not check this.
• When you declare the same absolute variable within two modules, this produces conflicts during
link time (except when one of the modules declares the variable 'extern').
9.6 Declaring interrupt functions

A function can be declared to serve as an interrupt service routine. You can use the function qualifier
__interrupt() for this purpose. Interrupt functions cannot return anything and must have a void argument
type list. For example, in:
void __interrupt(vector-address[, vector-address]...)
isr(void)
{
...
}
The function qualifier __interrupt() takes one or more vector addresses as arguments. All supplied vectors
will be initialized to point to the interrupt function.
If you want to use interrupt numbers instead of vector addresses for the TSK51A core, you can use the
__INTNO macro which is defined in the delivered special function register file (regtsk51a.sfr) as:
#define __INTNO(nr) ((8*nr)+3)
6 - 56
Example 8051
#include <regtsk51a.sfr>
void __interrupt( S0IR ) serial_receive( void )
{
...
}
void __interrupt( __INTNO(2) ) serial_transmit( void )

{
...
}
Example Z80
Z80 mode 2 interrupt:
void __interrupt( 0x10 ) IntHandler( void )
{
Interrupt();
}
This will reserve a word (.dw directive) on address 0x10, where the address of the interrupt function
is placed.
Z80 mode 1 interrupt or non-maskable interrupt:
void __interrupt( -1 ) IntNmHandler( void ) __at(0x66)
{
InterruptNm();
}
The vector address '-1' tells the compiler not to make a vector table entry. The __at() attribute places
the interrupt service routine on the desired absolute address.
The compiler generates the appropriate interrupt vector, consisting of a JMP instruction jumping to
the interrupt function. You can suppress this with the compiler option --novector or the #pragma
novector. The difference between a normal function and an interrupt function is that an interrupt
function ends with an RETI instruction instead of a RET instruction, and that registers that might
possibly be corrupted during the execution of the interrupt function are saved on function entry and
restored on function exit.
For certain ROM monitors it is necessary to specify an offset for all interrupt vectors. For this you can
use the command --vector-offset=value. Suppose a ROM monitor has the interrupt table at offset
0x4000. When you compile with --vector-offset=0x4000 interrupt vector 1 (vector address 11)
is being located at address 0x400B instead of 0xB.
6 - 57
9.7 Incorporating assembly in C code

With the __asm keyword you can use assembly instructions in the C source and pass C variables as
operands to the assembly code. Be aware that C modules that contain assembly are not portable
and harder to compile in other environments.
Furthermore, assembly blocks are not interpreted by the compiler: they are regarded as a black box.
So, it is your responsibility to make sure that the assembly block is syntactically correct.
General syntax of the __asm keyword
__asm( "instruction_template"
[ : output_param_list
[ : input_param_list
[ : register_save_list]]] );
instruction_template Assembly instructions that may contain parameters from the
input list or output list in the form: %parm_nr
%parm_nr[.regnum] Parameter number in the range 0 .. 31. With the optional
.regnum you can access an individual register from a register
pair. For example, with the word register R12, .0 selects
register R1.
output_param_list [[ "=[&]constraint_char"(C_expression)],...]
input_param_list [[ "constraint_char"(C_expression)],...]
& Says that an output operand is written to before the inputs are
read, so this output must not be the same register as any input.
constraint _char Constraint character: the type of register to be used for the
C_expression.
C_expression Any C expression. For output parameters it must be an lvalue,
that is, something that is legal to have on the left side of an
assignment.
register_save_list [["register_name"],...]
register_name Name of the register you want to reserve.
Typical example: adding two C variables using assembly

__data char a, b;
__data int result;
void add2( void )
{
__asm( "MOV A, %1\n\t"
"ADD A, %2\n\t"
"MOV %0, A": "=m"(result): "r"(a), "r"(b) );
}
generated code (8051):
mov R0,_b
mov R1,_a
MOV A, R0
ADD A, R1
MOV _result, A
%0 corresponds with the first C variable, %1 with the second and so on.
Specifying registers for C variables
With a constraint character you specify the register type for a parameter. In the example above, the r
is used to force the use of registers (Rn) for the parameters a and b.
6 - 58
You can reserve the registers that are already used in the assembly instructions, either in the
parameter lists or in the reserved register list (register_save_list, also called "clobber list"). The
compiler takes account of these lists, so no unnecessary register saves and restores are placed
around the inline assembly instructions.
Available operand constraints 8051
Constraint Type Operand Remark

character
a accumulator A
b bit ACC.[0..7], B.[0..7], bit registers/variables
C, AC, F0, RS1,
RS0, OV, F1, P,
_bitvar
d direct register PSW, SP, B, ACC, direct address of registers
DPH, DPL, AR[0..7]
i immediate value #data, #data16
m memory direct, label, memory variable or function
addr11, addr16, rel address
p data page DPTR
pointer
r register R[0..7]
R registers R01, R12, R23, word registers
R34, R45, R56,
R67
s register indirect @R0, @R1 register indirect addressing
number other operand same as %number used when in- and output
operands must be the same
Available operand constraints Z80
Constraint Type Operand Remark

character
i immediate value #value
m memory address, label stack or memory operand, a
fixed address or indexed
addressing
r register A, B, C, D, E, H, L, 8-bit register
I, R
IX, IY, SP, AF, BC, 16-bit register
DE, HL
number other operand same as %number Used when in- and output
operands must be the same
Loops and conditional jumps

The compiler does not detect loops with multiple __asm statements or (conditional) jumps across
__asm statements and will generate incorrect code for the registers involved.
6 - 59
If you want to create a loop with __asm, the whole loop must be contained in a single __asm
statement. The same counts for (conditional) jumps. As a rule of thumb, all references to a label in
an __asm statement must be contained in the same statement.
9.7.1 Example 1: No input or output

A simple example without input or output parameters. You can use any instruction or label.
__asm( "nop" );
Generated code:
nop
9.7.2 Example 2: Using output parameters

Assign the result of inline assembly to a variable. A register is chosen for the parameter because of
the constraint r; the compiler decides which register is best to use. The %0 in the instruction template
is replaced by the name of this register. Finally, the compiler generates code to assign the result to
the output variable.
int var1;
void main(void)
{
__asm( "mov %0,#ff" : "=r"(var1));
}
Generated assembly code (Z80 code):
mov HL,#ff
ld _var1,HL
9.7.3 Example 3: Using input and output parameters

Add two C variables and assign the result to a third C variable. Registers are used for the input
parameters (constraint r, %1 for a and %2 for b in the instruction template) and memory is used for
the output parameter (constraint m, %0 for result in the instruction template). The compiler
generates code to move the input expressions into the input registers and to assign the result to the
output variable.
__data char a, b;
__data int result;
void add2( void )
{
"ADD A, %2\n\t"
"MOV %0, A": "=m"(result): "r"(a), "r"(b) );
}
void main(void)
{
a = 3;
b = 4;
add2( );
}
Generated assembly code (8051):
_add2:
mov R0,_b
mov R1,_a
MOV A, R0
ADD A, R1
MOV _result, A
_main:
mov _a,#3
6 - 60
movx _b,#4
gcall _add2
9.7.4 Example 4: Reserve registers

Sometimes an instruction knocks out certain specific registers. The most common example of this is
a function call, where the called function is allowed to do whatever it likes with some registers. If this
is the case, you can list specific registers that get clobbered by an operation after the inputs.
Same as Example 3, but now register R0 is a reserved register. You can do this by adding a
reserved register list (: "R0"). As you can see in the generated assembly code, register R0 is not
used (the first register used is R1).
__data char a, b;
__data int result;
void add2( void )
{
"ADD A, %2\n\t"
"MOV %0, A": "=m"(result): "r"(a), "r"(b) : "R0" );
}
_add2:
mov R1,_b
mov R2,_a
MOV A, R1
ADD A, R2
MOV _result, A
Example 5: input and output are the same
If the input and output must be the same you can use a number constraint. The following example
adds two values. Input variable a has to go in the same place as the output variable a, so %2 and %0
are the same thing. That is why the constraint of argument 2 is 0, that is, the same as argument 0.
Note also that the .0 and .1 select a kid register from a register pair. Register A is reserved.
int _ADDI( int a, int b )
{
__asm("MOV A, %1.1\n\t"
"ADD A, %0.1\n\t"
"MOV %0.1, A\n\t"
"MOV A, %1.0\n\t"
"ADDC A, %0.0\n\t"
"MOV %0.0, A" : "=R"(a) : "R"(b), "0"(a) : "A" );
return a;
}
void main(void)
{
int ovar;
ovar = _ADDI(2,3);
}
__ADDI:
MOV A, R5
ADD A, R7
MOV R7, A
MOV A, R4
ADDC A, R6
MOV R6, A
ret
6 - 61
_main:
mov R6,#0
mov R7,#2
mov R4,#0
mov R5,#3
gcall __ADDI
ret
9.8 Real-Time Operating System (RTOS)

The TDK51 includes a compact RTOS, compliant with the OSEK/VDX standard. The RTOS is a real-
time, preemptive, multitasking kernel, designed for time-critical embedded applications. It offers:
• A high degree of modularity and the ability to create flexible configurations
• Time critical support, through the use of system object creation during the system generation
phase
• Well defined interfaces between application software and the operating system
• Superior application software portability, via the use of the OSEK Implementation Language, or
OIL
The RTOS panel is a runtime status panel, which can display information such as System Status,
Alarms, Tasks and Resources. Open the RTOS panel via the Embedded button at the bottom right
of the workspace, then enable the required RTOS information by clicking the RTOS button on the
Debug toolbar.
More information can be found in document GU0102 8051 RTOS.pdf or from the help contents
under Embedded Software Development » 8051 RTOS Guide.
6 - 62
9.9 Exercise 7 – PWM measurement

In this exercise we will implement an Interrupt Service Routine that will be responsible for measuring
the pulse width modulated output of a digital accelerometer. A fragment of the accelerometer’s
datasheet is shown in Figure 74:
A semi-complete project has been prepared and your instructor will tell you where to find it on your
local hard drive. The purpose of this program is to use and interrupt service routine to measure the
duration of the accelerometer high (T1) pulse and the period (T2) of the accelerometer output. The
main() routine will take values updated in the Interrupt Service Routine and display them on the
LCD display.
The basic framework of the application code has already been developed. Your task is to fill in the
missing lines of code in the Interrupt Service Routine.
1. Open the provided project and download the design to the NanoBoard.
2. Ensure that the NanoBoard Clock is set to 10MHz and the Frequency Generator is set to 1KHz.
3. Observe the contents of main(). Take note of the two variables that are to be displayed.
4. Look at TimeTSK51_Shell.C. You will notice a number of comment lines but the source code
is missing. Fill in these lines with the code in Figure 73.
5. Compile your completed code and run it on the NanoBoard.
6. Adjust the frequency of the Frequency Generator and observe the change in the LCD output.
7. Save your work.
Figure 73. Solution code for interrupt service routine
6 - 63
Note: For this exercise you may wish to refer to CR0115 TSK51x MCU.pdf for reference information
about the TSK51 processor. This document can be accessed from the help contents under FPGA
Design » Core References » Processors » TSK51x MCU.
Figure 74. Extract from accelerometer datasheet. RSET has been set to 1.25M.
6 - 64
10 Review
6 - 65

Altium

Uploaded by

Copyright:

Available Formats

Altium

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Altium

Uploaded by

Copyright:

Available Formats

What is the Altium Designer used for?

What is the Altium Designer used for?

What are some of the key features of the Altium Designer environment?

What are some of the key features of the Altium Designer environment?

Unified Electronic Product Development

Altium Designer Schematic Capture and PCB Editing training

Software, documentation and related materials:

Environment and Editor Basics Training Module ii

Environment and Editor Basics Training Module iii

Environment and Editor Basics Training Module iv

1.1 DXP – the Altium Designer Integration Platform

Figure 1. Altium Designer’s software integration architecture

1.2 The Altium Designer Project

Environment and Editor Basics Training Module 1-1

Figure 2. The open project is displayed in the Projects panel.

3. Click on the – signs to contract the folders.

Environment and Editor Basics Training Module 1-2

DXP System Menu View Navigation

Figure 3. Altium Designer with the DXP Home Page displayed.

Environment and Editor Basics Training Module 1-3

Figure 4. A schematic open for editing in the Schematic Editor View.

2.1.1 Document Tabs in the Documents Bar

Right-click menu in the Documents Bar

Environment and Editor Basics Training Module 1-4

2.2 Exercises — Navigating around the Altium Designer

2.2.1 Using the Projects panel

2.2.2 Design Window navigation

Environment and Editor Basics Training Module 1-5

3.1 Working in a document editor

The Projects panel

Figure 6. Schematic Editor workspace

Environment and Editor Basics Training Module 1-6

3.1.4 System and Editor Panels

3.1.5 Status Bar

Environment and Editor Basics Training Module 1-7

3.1.7 Tool Tips

3.1.8 Right mouse click context sensitive pop-up menus

Figure 7. A context sensitive right mouse menu

Environment and Editor Basics Training Module 1-8

Environment and Editor Basics Training Module 1-9

4.1 Creating a new project

Figure 8. The new project is displayed in the Projects panel

Environment and Editor Basics Training Module 1 - 10

4.3 Renaming documents

4.4 Adding an existing document to a project

4.5 Moving or copying a document between projects

4.6 Removing a document from the project

4.7 Working with old Protel designs

Environment and Editor Basics Training Module 1 - 11

4.8 File management with the Storage Manager

Note: Press F1 over the panel for access to detailed help.

Environment and Editor Basics Training Module 1 - 12

4.11 Exercise – Working with projects and documents

Environment and Editor Basics Training Module 1 - 13

Figure 11. Configure the environment via the DXP menu

5.1 System Info

Figure 12. EDA Servers dialog

Environment and Editor Basics Training Module 1 - 14

5.3.1 Autosave and manual save backup options

Environment and Editor Basics Training Module 1 - 15