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Design A Half Adder Using Dataflow Architecture in VHDL Code (Autorecovered)

The document describes how to design a half adder and full adder using VHDL. It first shows how to design a half adder using dataflow architecture by modeling the XOR and AND logic gates. It then shows how to design a half adder using structural modeling by defining XOR and AND components. Finally, it demonstrates how to design a full adder using a half adder, XOR, and OR components in a structural modeling approach.

Uploaded by

Amit Saha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
440 views

Design A Half Adder Using Dataflow Architecture in VHDL Code (Autorecovered)

The document describes how to design a half adder and full adder using VHDL. It first shows how to design a half adder using dataflow architecture by modeling the XOR and AND logic gates. It then shows how to design a half adder using structural modeling by defining XOR and AND components. Finally, it demonstrates how to design a full adder using a half adder, XOR, and OR components in a structural modeling approach.

Uploaded by

Amit Saha
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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➢ DESIGN A HALF ADDER USING DATAFLOW ARCHITECTURE IN VHDL CODE

A half adder is an arithmetic combinational circuit that takes in two binary digits and
adds them. The half adder gives out two outputs, the SUM of the operation and the
CARRY generated in the operation. Since this carry is not added to the final answer,
the addition process is somewhat incomplete. Hence, it’s known as the half adder.
Below you will find the logic circuit and the corresponding logic equation of the half
adder. This circuit is made using simple digital logic gates; the EX-OR and AND gates.
We will use this equation to program a half adder circuit using VHDL.

SUM =
CARRY = AB

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port(a,b: in bit;s,c: out bit);
end half_adder;

architecture half_adder of half_adder is


begin
s<=(a xor b);
c<=(a and b);

end half_adder;
RTL SCHEMATIC

TECHNOLOGY SCHEMATIC
SIMULATION RESULTS
➢ DESIGN A HALF ADDER USING STRUCTURAL MODELLING IN VHDL CODE

• FIRST COMPONENT:
XOR GATE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_2 is
port (A,B: in BIT; Z: out BIT);
end xor_2;
architecture DataFlow of xor_2 is
begin
Z <= (not A and B) or (A and not(B));
end DataFlow;

• SECOND COMPONENT:
AND GATE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_2 is
port(A,B: in BIT; Z: out BIT);
end and_2;
architecture DataFlow of and_2 is
begin
Z <= A and B;
end DataFlow;
HALF ADDER DESIGN
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Interface
entity H_ADDER is
port (A, B: in BIT; SUM, CRY: out BIT);
end H_ADDER;
--Body
architecture STRUCTURAL of H_ADDER is
component xor_2
port (A, B: in BIT; Z: out BIT);
end component;
component and_2
port (A, B: in BIT; Z: out BIT);
end component;
begin
X1: xor_2 port map (A, B, SUM);
A1: and_2 port map (A, B, CRY);
end STRUCTURAL;

RTL SCHEMATIC
➢ DESIGN A FULL ADDER USING DATAFLOW ARCHITECTURE IN VHDL CODE

SUM =
CARRY = Y(A+B) + AB

A B Y SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port(a,b,c: in bit;sum,carry: out bit);
end full_adder;

architecture full_adder of full_adder is


begin
sum<=((a xor b) xor c);
carry<=((a and b) or (b and c) or (c and a));
end full_adder;

RTL SCHEMATIC
TECHNOLOGY SCHEMATIC

SIMULATION RESULTS
➢ DESIGN A FULL ADDER USING HALF ADDER COMPONENTS (STRUCTURAL
MODELLING) IN VHDL CODE

• FIRST COMPONENT:
HALF ADDER 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Interface
entity H_ADDER is
port (A, B: in BIT; SUM, CRY: out BIT);
end H_ADDER;
--Body
architecture STRUCTURAL of H_ADDER is
component xor_2
port (A, B: in BIT; Z: out BIT);
end component;
component and_2
port (A, B: in BIT; Z: out BIT);
end component;
begin
X1: xor_2 port map (A, B, SUM);
A1: and_2 port map (A, B, CRY);
end STRUCTURAL;
• SECOND COMPONENT:
HALF ADDER 2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Interface
entity H_ADDER is
port (A, B: in BIT; SUM, CRY: out BIT);
end H_ADDER;
--Body
architecture STRUCTURAL of H_ADDER is
component xor_2
port (A, B: in BIT; Z: out BIT);
end component;
component and_2
port (A, B: in BIT; Z: out BIT);
end component;
begin
X1: xor_2 port map (A, B, SUM);
A1: and_2 port map (A, B, CRY);
end STRUCTURAL;
• THIRD COMPONENT:
OR GATE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_2 is
port (A, B: in BIT; Z: out BIT);
end or_2;
architecture DataFlow of or_2 is
begin
Z <= A or B;
end DataFlow;

FULL ADDER DESIGN


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Interface
entity FULL_ADDER is
port(A,B,C: in BIT; SUM, CRY: out BIT);
end FULL_ADDER;
--Body
architecture STRUCTURAL of FULL_ADDER is
component H_Adder
port(A, B : in BIT; SUM, CRY: out BIT);
end component;
component or_2
port(A , B : in BIT; Z: out BIT);
end component;
signal SUM1, CRY1, CRY2: BIT;
begin
HA1: H_ADDER port map(A, B, SUM1, CRY1);
HA2: H_ADDER port map(SUM1, C, SUM, CRY2);
O_2: OR_2 port map(CRY1, CRY2, CRY);
end STRUCTURAL;

RTL SCHEMATIC

TECHNOLOGY SCHEMATIC
SIMULATION RESULTS

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