7 DRAM TECHNOLOGY

OVERVIEW

DRAM (Dynamic Random Access Memory) is the main memory used for all desktop and larger
computers. Each elementary DRAM cell is made up of a single MOS transistor and a storage
capacitor (Figure 7-1). Each storage cell contains one bit of information. This charge, however,
leaks off the capacitor due to the sub-threshold current of the cell transistor. Therefore, the charge
must be refreshed several times each second.

Bit Line

Word Line Transistor

Capacitor

Plate

Source: ICE, "Memory 1997" 19941

Figure 7-1. DRAM Cell

HOW THE DEVICE WORKS

The memory cell is written to by placing a “1” or “0” charge into the capacitor cell. This is done
during a write cycle by opening the cell transistor (gate to power supply or VCC) and presenting
either VCC or 0V (ground) at the capacitor. The word line (gate of the transistor) is then held at
ground to isolate the capacitor charge. This capacitor will be accessed for either a new write, a
read, or a refresh.

Figure 7-2 shows a simplified DRAM diagram. The gates of the memory cells are tied to the
rows. The read (or write) of a DRAM is done in two main steps as illustrated in Figure 7-3. The
row (X) and column (Y) addresses are presented on the same pads and multiplexed. The first
step consists of validating the row addresses and the second step consists of validating the
column addresses.

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DRAM Technology

Address X
Row Decode
Pads

CAS
RAS

Y
Data
Sense
Data Amplifier

Data
Sense
Data Amplifier
Y Decode

Output
Dout
Buffer Data
Sense
Data Amplifier
Input
Din
Buffer
Data
Sense
Data Amplifier

Source: ICE, "Memory 1997" 22430

Figure 7-2. Simplified DRAM Diagram

RAS

Address Row Column

CAS

Step I Step II

Row Access Column Access

Source: ICE, "Memory 1997" 22431

Figure 7-3. DRAM Access Timing

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 DRAM Technology

First Step: Row Addresses

Row addresses are present on address pads and are internally validated by the RAS (Row Address
Access) clock. A bar on top of the signal name means this signal is active when it is at a low level.
The X addresses select one row through the row decode, while all the other non-selected rows
remain at 0V. Each cell of the selected row is tied to a sense amplifier. A sense amplifier is a cir-
cuit that is able to recognize if a charge has been loaded into the capacitor of the memory cell, and
to translate this charge or lack of charge into a 1 or 0. There are as many sense amplifiers as there
are cells on a row. Each sense amplifier is connected to a column (Y address). In this first step all
the cells of the entire row are read by the sense amplifier. This step is long and critical because the
row has a high time constant due to the fact that it is formed by the gates of the memory cells.
Also, the sense amplifier has to read a very weak charge (approximately 30 femtoFarads or 30fF).

Second Step: Column Addresses

Following the first step, column addresses are present on the address pads and are internally val-
idated by the Column Address Access (CAS) clock. Each selected memory cell has its data vali-
dated in a sense amplifier. Column access is fast. This step consists of transferring data present
in the sense amplifier to the Dout pin through the column decode and the output buffer. On
memory data sheets, the access time from RAS is termed tRAC and the access time from CAS is
listed as tCAC. On a typical standard DRAM of 60ns access time, tRAC = 60ns and tCAC = 15ns.

Refresh

To maintain data integrity, it is necessary to refresh each DRAM memory cell. Each row of cells
is refreshed every cycle. For example, if the product specification states, “Refresh cycle = 512
cycles per 8ms,” then there are 512 rows and each individual row must be refreshed every eight
milliseconds.

As explained above, during the row access step, all the cells from the same row are read by the
sense amplifier. The sense amplifier has two roles. Since it holds information within the cell, it is
able to transmit this data to the output buffer if it is selected by the column address. The sense
amplifier is also able to re-transmit (write) the information into the memory cell. In this case, it
“refreshes” the memory cell. When one row is selected, all the cells of that row are read by the
sense amplifiers and all these cells are refreshed one at a time.

Burst or distributed refresh methods can be used. Burst refresh is done by performing a series of
refresh cycles until all rows have been accessed. For the example given above, this is done every
8ms. During the refresh, other commands are not allowed. Using the distributed method and
the above example, a refresh is done every 12.6µs (8ms divided by 512). Figure 7-4 shows these
two modes.

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DRAM Technology

Distributed
Refresh

Burst
Refresh

Time
Required Time To
Complete Refresh Of All Rows
Each Pulse Represents
a Refresh Cycle
Source: Micron, "Memory 1997" 20843

Figure 7-4. Burst and Distributed Refresh

For standard DRAMs there are three ways to perform refresh cycles. They are RAS-only refresh,
CAS-before-RAS refresh, and hidden refresh. To perform a RAS-only refresh, a row address is put
on the address lines and then RAS goes low. To perform a CAS-before-RAS refresh, CAS first goes
low and then a refresh cycle is performed each time RAS goes low. To perform a hidden refresh
the user does a read or write cycle and then brings RAS high and then low.

MEMORY CELL

A great deal of design effort has been made to shrink the cell area, particularly, the size of the
DRAM capacitor. As memory density increases, the cell size must decrease. Designers have man-
aged to shrink overall cell size. However, due to factors such as noise sensitivity and speed, it has
been a challenge to reduce the capacitance. The capacitance must stay in the range of 30fF.

The charge (Q) stored in a capacitor is equal to capacitance times voltage (Q = C x V). Over the
years, DRAM operating voltage has decreased (i.e., 12V to 5V to 3.3V). As voltage decreases, the
stored charge will also decrease. Design improvements allow for the decrease in the cell charge
as long as the capacitance remains in the range of 30fF.

Two main developments are used to reduce capacitor area without reducing its value. These are
the use of new capacitor shapes to fit into a minimum chip surface area and increasing the
dielectric constant.

Memory Cell Shape

The 1Mbit DRAM generation was the first to abandon the classical planar capacitor and replace it
with a trench or a stacked capacitor. Figure 7-5 shows the feature sizes of some of the DRAM
devices that ICE analyzed in its laboratory these two last years. Trench capacitors are not widely
used in spite of continual research and development on that type of design. As shown, the major
64Mbit DRAMs available on the market are today made of stacked capacitors.

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 DRAM Technology

Cell Area Die Area

Name Density Date Code Gate Length Cell Type
µm2 mm2
Fujitsu 16M 9532 1.4 97.8 0.30 Stacked
Mosel-Vitelic 4M 9518 4.0 65.0 0.55 Stacked
NEC 64M 9621 1.0 161.0 0.35 Stacked
IBM/Siemens 64M 9539 1.5 197.0 0.25 Trench
Samsung 64M 9552 1.2 159.3 0.35 Crown
Mitsubishi 16M 1995 3.0 100.1 0.45 Stacked
Hitachi 64M 9351 1.6 229.4 0.35 Stacked
Source: ICE, "Memory 1997" 22432

Figure 7-5. Physical Dimensions of DRAMs

Cross sections of 64Mbit DRAMs analyzed by ICE’s laboratory illustrate three major choices for
manufacturing DRAM memory cells. Hitachi uses a stacked, multi-layer capacitor for its 64Mbit
DRAM (Figure 7-6). The trench capacitor (Figure 7-7) is used by IBM/Siemens, and the simple
stack capacitor (Figure 7-8, and 7-9) is preferred by Samsung and NEC.

Photo by ICE, “Memory 1997” 19814

Figure 7-6. Hitachi 64Mbit DRAM Cross Section

Figure 7-10 shows how size cell improvements will be necessary for the next DRAM generations.
Figure 7-11 illustrates the stacked capacitor structure evolution. The decrease of cell size without
decreasing capacitor value results in increasing complexity of memory cell technology. Most lead-
ing DRAM manufacturers are working on 1Gbit cells. Their goal is to decrease the size of the cell
without compromising the value of the capacitor.

Two types of 1Gbit cell developments are shown in the next figures. Toshiba tried to improve the
trench capacitor concept by creating a bottle-shape trench design (Figure 7-12). Hitachi tried to
improve the stack concept with a vertical and circular capacitor (Figure 7-13). NEC received a
patent from the U.S. Patent Office for its proprietary HSG (hemispherical-grain) silicon technology.

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DRAM Technology

METAL 3 METAL 2

METAL 1

POLY 1 TRENCH
CAPACITORS

Photo by ICE, “Memory 1997” 22433

Figure 7-7. IBM/Siemens 64Mbit DRAM Cross Section

POLY 5 CAPACITOR SHEET

POLY 4
CAPACITOR NITRIDE
PLATE ETCH-STOP
LAYER

“STEM” POLY 2 BIT LINE

CONTACT
REFLOW GLASS

POLY 2 BIT
CONTACT PAD

N+ S/D POLYCIDE 1 SELECT GATE

Photo by ICE, “Memory 1997” 20844

Figure 7-8. Samsung 64Mbit DRAM Cross Section

CAPACITOR POLY 4 CAPACITOR SHEET

DIELECTRIC

POLY 3
CAPACITOR
PLATE

POLY 3
“STEM”

POLY 2 BIT LINE

Photo by ICE, “Memory 1997” 22434

Figure 7-9. NEC 64Mbit DRAM Cross Section

7-6 INTEGRATED CIRCUIT ENGINEERING CORPORATION

 DRAM Technology

103 10
Chip Area

102 1.0
Chip Area (mm2), Cell Area (µm2)

Minimum

Minimum Feature Size (µm2)

Feature Size

101 0.1

1 Cell Area 0.01

10-1
256K 1M 4M 16M 64M 256M 1G 4G
DRAM Generation (bits)
Source: Hitachi/ICE, "Memory 1997" 20775A

Figure 7-10. DRAM Technology Trend

CAPACITOR DIELECTRICS

The inability to scale the capacitor value has led to the consideration of new dielectric materials for
the capacitor. It is likely that materials with higher dielectrics will see more use. Many of the mate-
rials have proven track records through their use as dielectrics in discrete capacitors. Therefore, the
main challenge is the introduction of these materials into the IC process. Figure 7-14 shows some
of the materials under consideration. Tantalum Pentoxide (Ta2O5) has been viewed in several of
the 64Mbit DRAMs analyzed by the ICE laboratory. Ta2O5 seems that it could serve as a good
dielectric since it can easily be integrated into conventional stack capacitor structure. However, it
requires higher dielectric thickness, resulting in only a marginal improvement in capacitance.

PERFORMANCE

Compared with other memory ICs, DRAMs suffer from a speed problem. The on-chip circuitry
required to read the data from each cell is inherently slow. As such, DRAM speeds have not kept
pace with the increased clock speed of CPUs.

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DRAM Technology

,,,,,
,,,,,
,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
Planar

,,,,,,,,
,,,,,,,,
HSG Crown

,,,,,,,,
Cup

,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,, Multilayer Fin

Simple Stack

,,,,,,,,
,,,,,,,, ,,,,,,,,
,,,,,,,,
,,,,,,,, ,,,,,,,,
Simple Crown Multilayer Crown
Source: IBM/Semiconductor International/ICE, "Memory 1997" 22435

Figure 7-11. Stack Capacitor Structure Evolution

,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,,,

,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,,,
,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,,,

Si RIE In-situ Doped Annealing Chemical

Poly-Si Dry Etching
Deposition Impurity
Doping Into
the Plate
Electrode
Source: Toshiba/ICE, "Memory 1997" 20767

Figure 7-12. Capacitor Manufacturing Process

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 DRAM Technology

TiN Plate Electrode

Poly-Si Electrode

Ta2O5

,,,
,,,, ,,,,,
Bit Line
,, ,,
,,,,
,,,
,,,,
,,, ,,,
,,,,,
,,,
,,,,,

,,,
Poly-Si Plug

,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,
LOCOS

Si Substrate

Source: Hitachi/ICE, "Memory 1997" 20766

Figure 7-13. Schematic Cross-Sectional View of CROWN-Type Memory Cell

Material εr
SiO2 3.8
SiN4 7.9
Ta2O5 20 - 30
BaTiO3 15 - 30
SrTiO3 15 - 30
TiO2 35 - 50
Polyimide 2 - 2.6
Source: ICE, "Memory 1997" 18741

Figure 7-14. Capacitor Dielectric Constants

Early microprocessor systems were introduced with clock speeds of 1MHz (one million cycles
per second). Today, CPUs in desktop PCs are 200MHz and faster, at least a 200x improvement.
Early DRAMs had access cycle times (the time required for the DRAM chip to supply the data
back to the CPU) of 250 nanoseconds (ns). The fastest DRAM units today are about 50ns, a five-
fold improvement.

To face this speed discrepancy, DRAMs have branched into many sub-categories. Each features a
variation of system interface circuitry with the intent of enhancing performance. Furthermore, each
design attempts to answer needs of specific applications. Current offerings are shown Figure 7-15.

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DRAM Technology

FPM (Fast Page Mode)

EDO (Extended Data Out)
Standard
BEDO (Burst EDO)
ARAM (Audio RAM)

EDRAM (Enhanced DRAM)

Cache
CDRAM (Cache DRAM)

SDRAM (Synchronous DRAM)

Synchronous SDRAM II or DDR DRAM (Double Data Rate DRAM)
SGRAM (Synchronous Graphic DRAM)

Cache Synchronous ESDRAM (Enhanced SDRAM)

DRAM
VRAM (Video RAM)
Video
WRAM (Window RAM)

PSDRAM (Pseudo Static RAM)

Pseudo Static
Fusion

RDRAM (Rambus)
SLDRAM (SyncLink)
Other Configurations 3D
nDRAM (Next Generation)
MDRAM (Multi Bank)

Other Technology FRAM (Ferroelectric DRAM)

Source: ICE, "Memory 1997" 22450

Figure 7-15. Current DRAM Varieties

Fast Page Mode DRAMs

To access DRAM data, a row address is applied, followed by a column address. The addresses of
a DRAM are multiplexed on the same package pins. When requested data is stored in the same
row as previously requested data, merely changing the column address allows access to this new
data. Therefore, with fast page mode, the data of the same row can be accessed by changing only
the column address.

As an example, consider a 1Mbit DRAM that has an array organization of 1,024 x 1,024 bits. 1,024
bits of data belong to the same row. This data will be accessible through fast page mode (a row is
considered a page). This mode is available on all the standard DRAMs. As described previously,
this access time is as fast as the data available in the sense amplifier.

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 DRAM Technology

Static column mode is similar to page mode except that only the column address needs to be
changed to obtain the new data, and no CAS pulse is needed. Nibble mode groups memory cells
in “four bits per nibble” so that whenever one bit is selected, four serial bits appear. This mode is
no longer widely used.

Extended Data Out (EDO) DRAMs

Extended data out DRAMs (EDO DRAMs), also called hyper-page-mode DRAMs, represent a
small design change in the output buffer relative to a standard fast page mode DRAM. The old
data is latched at the output while new data is addressed. EDO shortens the effective page mode
cycle time as the valid data output time is extended.

For the same technology, a product in standard mode may have a cycle time of 110ns (access time
of 60ns). This cycle time will be reduced to 40ns in fast page mode and to 25ns in EDO mode.

Burst EDO DRAMs

Several vendors offer burst versions of the EDO DRAM. The “burst” refers to the fact that all read
and write cycles occur in bursts of four, automatically sequenced by the memory chip. To accom-
plish that, a special pipeline stage and a two-bit counter are added.

The Burst EDO DRAM read access time differs from EDO DRAM in two ways. First, as the output
latch is replaced by a special pipeline stage (register), the latency will be higher but the bandwidth
will be better. Second, as the Burst EDO DRAM includes an internal address counter, only the ini-
tial address in a burst of four needs to be provided.

Manufacturers may use the same mask set for their fast page mode EDO and burst EDO DRAMs.
A wire bond option determines which product is in the final package. Figure 7-16 shows timing
differences between the various standard DRAMs. Figure 7-17 shows speed differences.

Audio DRAMs

Due to process defects during wafer probe, some DRAMs wind up with a few failed storage cells
that cannot be effectively repaired (or replaced) by the redundancy mechanism. These cannot
be sold as good devices to PC OEMs. However, a few defective bits do not affect an audio appli-
cation where there is a tolerance for error. For this reason manufacturers may sell parts with few
bad cells for use in audio applications. These devices are called Audio DRAM (ARAM). The
client can buy ARAMs cheaper than a standard DRAM.

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DRAM Technology

RAS RAS

CAS CAS

Address ,,,
,,,R C ,,,,,,
,,,,,,
Address ,,
,, R C C C C C,,,,
,,,,
Dout Dout 1 2 3 4 n

NORMAL MODE STATIC COLUMN MODE

RAS RAS

CAS CAS

Address
,,
,, R C,,,,,
,,,,,,,,,,
,,,,,
C C
,,,,,
,,,,, Address ,,
,,R C
,,
,, C ,,
,, C,,,
,,,C ,,,
,,,
Dout 1 2
Dout 1 2 3
FAST PAGE MODE
EDO

RAS RAS

CAS CAS

Address ,, ,,,,,,,,,,,,,,,
,, R C,,,,,,,,,,,,,,, Address ,, ,,,,,,,,,,,,,,,
,, R C,,,,,,,,,,,,,,,
Dout 1 2 3 4 Dout 1 2 3 4
NIBBLE MODE BURST EDO
R: Row Address
C: Column Address
Source: ICE, "Memory 1997" 22436

Figure 7-16. Comparison of Dynamic RAM High Speed Access Modes

DRAM Type
DRAM Speed
(tRAC) Fast Page Burst
EDO
Mode EDO

70ns 25MHz 33MHz 50MHz

60ns 28MHz 40MHz 60MHz

50ns 33MHz 50MHz 66MHz

Source: Micron/ICE, "Memory 1997" 19992A

Figure 7-17. Comparison of Standard DRAM Performances

Cache DRAMs

Another DRAM alternative is the cache DRAM (CDRAM) developed by Mitsubishi. This device
integrates a 16Mbit DRAM and a L2 (level two) SRAM cache memory (16Kbit SRAM) on the same
chip. The transfer between the DRAM and the SRAM is performed in one clock cycle through a
buffer of 8 x 16 bits. The SRAM is a six-transistor cell. The SRAM access/cycle time is 15ns.
Currently, Mitsubishi and Samsung offer CDRAM devices. Figure 7-18 shows the chip organiza-
tion of a CDRAM.

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 DRAM Technology

SRAM Address
4K x 4 Fast SRAM Cache
Address Latch

Clock
Cache Hit
DRAM
CS, Write Enable 64-Bit Buffer 64-Bit Buffer Data
Control
Control
Refresh

Multiplexed Address 1M x 4 DRAM Array

DRAM Address Latch
Source: EBN/ICE, "Memory 1997" 20756

Figure 7-18. Cache DRAM

Enhanced DRAMs

Enhanced DRAMs (EDRAMs) were developed by Ramtron Corporation. The EDRAM is also sold
by IBM (3.3V and 5V parts), as IBM and Ramtron have a second source agreement for this prod-
uct. The EDRAM architecture is similar to a standard 4Mbit page mode or static column DRAM
with the addition of an integrated L2 SRAM cache and internal control. Technically, the EDRAM
is a cache DRAM (CDRAM). Rather than integrate a separate SRAM cache, the EDRAM takes
advantage of the internal architecture of a standard fast page mode DRAM, which has sense
amplifiers that act like a 2Kbit SRAM cache when reading and accessing data.

Memory read cycles always occur from the cache. When the comparator detects a hit, only the
SRAM is addressed where data is available in 15ns. When a miss is detected, the entire cache is
updated and data is available at the output within a single 35ns access. Figure 7-19 shows the chip
organization of an EDRAM.

Column Access Signal Column Address 512 x 4 Page

Ground
Latch Cache (SRAM) Read
Column Data
Last Row Read Decoder I/O Set
Address Address Latch Control
Lines and
Sense Amps and Data
Row Write Select Write Latches Write Enable
Address Latch Data

Refresh Control Pin

Flow Address and DRAM Array Data
Read/Write Control Refresh
Refresh Counter (2,048 x 512 x 4)
Row Access Signal Address
Source: EBN/ICE, "Memory 1997" 20757

Figure 7-19. Enhanced DRAM (EDRAM)

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Synchronous DRAMs

Synchronous DRAMs represent the next step in the evolution of the industry standard DRAM
architecture. Synchronous DRAMs (SDRAMs) have their read and write cycles synchronized
with the processor clock. The SDRAM is designed with two separate banks. These two indepen-
dent banks allow each bank to have different rows active at the same time. This allows concur-
rent access/refresh and recharge operations. Figure 7-20 presents a block diagram organization
of an SDRAM.
DQMU
DQML

CAS#
RAS#
WE#

CKE
CLK
CS#

Address Bus
Control Logic and A8 A9-A0
Timing Generator

A9-A0 A9 A7-A0 A9-A0 Refresh Counter

Mode Register

Burst Counter Column Address Latch Row Address Latch

MUX

Row Decorder Row Decorder

512 Rows 512 Rows
Sense Amps

Sense Amps

Columns
Columns
Decoder

Decoder
Column

Column

256
256

Memory Array Bank 0 Memory Array Bank 1

CAS #
Output Latch Input Latch
Latency Control /Buffer
Output Latch

Output Buffer
Data Bus
Source: Hitachi/ICE, "Memory 1997" 22437

Figure 7-20. 4Mbit SDRAM Block Diagram

The SDRAM is programmed using a mode register. The programmable features include burst
length (1, 2, 4, 8, full page), wrap sequence (sequential/interleave), and CAS latency (1, 2, 3).
Figure 7-21 shows an SDRAM timing sequence. This timing illustrates the different possibilities
of CAS latency and of burst length.

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CLK
tRCD
Active Read
Command
Row Column
Address

CL = 1 Out 0 Out 2

Out 1 Out 3
CL = 2 Out 1 Out 3
Dout
Out 0 Out 2
CL = 3 Out 0 Out 2

Out 1 Out 3
CL: CAS Latency
Burst Length = 4

BURST LENGTH
CLK
tRCD
Active Read
Command
Row Column
Address

BL = 1 Out 0

BL = 2 Out 0
Out 1
BL = 4 Out 0 Out 2
Dout
Out 1 Out 3
BL = 8 Out 0 Out 2 Out 4 Out 6
Out 1 Out 3 Out 5 Out 7
BL = Full Page Out 0 Out 2 Out 4 Out 6 Out 8 Out 256 Out 1
Out 1 Out 3 Out 5 Out 7 Out 0
BL: Burst Length
CAS: Latency = 2
Source: Hitachi/ICE, "Memory 1997" 22439

Figure 7-21. SDRAM Timing

The size of the mode register is equivalent to the number of address pins on the device and is writ-
ten during a mode register set cycle. This mode register must be reprogrammed each time any of
the programmable features have to be modified. Figure 7-22 illustrates the content of a register
for a 4Mbit SDRAM. Figure 7-23 shows a summary of the SDRAM functionality.

SDRAM-II or DDR DRAMs (Double Data Rate DRAMs)

The purpose of the DDR DRAM is to read data of an SDRAM at two times the frequency clock. The
device delivers data on both edges of the clock, doubling effective bandwidth at a given frequency.

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DRAM Technology

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
OPCODE 0 LMODE BT BL

A6 A5 A4 CAS Latency A3 Burst Type Burst Length

0 0 0 R A2 A1 A0
0 Sequential BT=0 BT=1
0 0 1 1 1 Interleave 0 0 0 R R
0 1 0 2 0 0 1 2 2
0 1 1 3 0 1 0 4 4
1 X X R 0 1 1 8 8
1 0 0 R R
A9 A8 Write Mode 1 0 1 R R
0 0 Burst Read and Burst Write 1 1 0 R R
0 1 R 1 1 1 F.P. R
1 0 Burst Read and Single Write
1 1 R
F.P. = Full Page
R = Reserved (inhibit)
Source: Hitachi/ICE, "Memory 1997" 22438

Figure 7-22. Register Content of a 4Mbit SDRAM

CLK: External Clock Input and Synchronous DRAM Operations Synchronize with this Signal

CLK

Command:
Command Controls Synchronous DRAM Operation
Active Read
(CS,RAS,CAS,WE) Command is a Combination of CS,
RAS, CAS, and WE Signals.
Address
(A0 to A8) Row Column

Bank Select:
Bank Select A Memory Contains 2 Banks (Areas)
BS BS that can be Controlled Independently.
(A9)
BANK SELECT is used to Select a Bank.

Dout Out 0 Out 1 Out 2 Out 3

CAS Latency = 3 Burst Length = 4

Active Command Read Command
Set Cycle Set Cycle

CAS Latency: Clock Numbers from Burst Length: Possible Consecutive

Read Command Set to Data Output Input/Output Data Length

Source: Hitachi/ICE, "Memory 1997" 22440

Figure 7-23. SDRAM Functionality

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