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TS3USB221
SCDS220I – NOVEMBER 2006 – REVISED JANUARY 2016

TS3USB221 High-Speed USB 2.0 (480-Mbps) 1:2 Multiplexer – Demultiplexer

Switch With Single Enable
1 Features 3 Description
•
1 VCC Operation from 2.3 V and 3.6 V The TS3USB221 is a high-bandwidth switch specially
designed for the switching of high-speed USB 2.0
• VI/O Accepts Signals up to 5.5 V signals in handset and consumer applications, such
• 1.8-V Compatible Control-Pin Inputs as cell phones, digital cameras, and notebooks with
• Low-Power Mode When OE Is Disabled (1 μA) hubs or controllers with limited USB I/Os. The wide
• rON = 6 Ω Maximum bandwidth (1.1 GHz) of this switch allows signals to
pass with minimum edge and phase distortion. The
• ΔrON = 0.2 Ω Typical device multiplexes differential outputs from a USB
• Cio(on) = 6 pF Maximum host device to one of two corresponding outputs. The
• Low Power Consumption (30 μA Maximum) switch is bidirectional and offers little or no
attenuation of the high-speed signals at the outputs.
• ESD > 2000-V Human-Body Model (HBM) The TS3USB221 is designed for low bit-to-bit skew
• High Bandwidth (1.1 GHz Typical) and high channel to channel noise isolation. The
TS3USB221 is also compatible with various
2 Applications standards, such as high-speed USB 2.0 (480 Mbps).
• Routes Signals for USB 1.0, 1.1, and 2.0 Device Information(1)
• Mobile Industry Processor Interface (MIPI™) PART NUMBER PACKAGE BODY SIZE (NOM)
Signal Routing
VSON (10) 3.00 mm × 3.00 mm
• MHL 1.0 TS3USB221
UQFN (10) 1.50 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
Simplified Schematic, Each FET Switch (SW)
D+ 1D+
D− 1D−
A B
2D+ VCC
2D−

Charge
S Pump
Digital Control
OE

EN (see Note A)

A. EN is the internal enable signal applied to

the switch.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 12
2 Applications ........................................................... 1 8.1 Overview ................................................................. 12
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 12
4 Revision History..................................................... 2 8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Application and Implementation ........................ 13
9.1 Application Information............................................ 13
6.1 Absolute Maximum Ratings ...................................... 4
9.2 Typical Application ................................................. 13
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4 10 Power Supply Recommendations ..................... 15
6.4 Thermal Information .................................................. 4 11 Layout................................................................... 15
6.5 Electrical Characteristics........................................... 5 11.1 Layout Guidelines ................................................. 15
6.6 Dynamic Electrical Characteristics, VCC = 3.3 V ± 11.2 Layout Example .................................................... 16
10% ........................................................................... 6 12 Device and Documentation Support ................. 17
6.7 Dynamic Electrical Characteristics, VCC = 2.5 V ± 12.1 Documentation Support ........................................ 17
10% ........................................................................... 6 12.2 Trademarks ........................................................... 17
6.8 Switching Characteristics, VCC = 3.3 V ± 10% ........ 6 12.3 Electrostatic Discharge Caution ............................ 17
6.9 Switching Characteristics, VCC = 2.5 V ± 10% ........ 6 12.4 Glossary ................................................................ 17
6.10 Typical Characteristics ............................................ 7
13 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information .................. 8 Information ........................................................... 17

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (February 2015) to Revision I Page

• Changed VIH Max from 5.5 to VCC in Recommended Operating Conditions table ................................................................. 4

Changes from Revision G (September 2010) to Revision H Page

• Changed first bullet of the Features FROM: VCC Operation at 2.5 V and 3.3 V TO: VCC Operation at 2.3 V and 3.6 V ....... 1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Removed the Ordering Information table ............................................................................................................................... 1

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5 Pin Configuration and Functions

DRC Package
10-Pin VSON RSE Package
(Top View) 10-Pin UQFN
(Top View)
VCC
1D+ 1 10 VCC

1D– 2 9 S 1D+ 1 10 9 S
2D+ 3 8 D+
1D– 2 8 D+
2D– 4 7 D–
GND 5 6 OE 2D+ 3 7 D–

2D– 4 5 6 OE

GND

RSE Package
10-Pin UQFB
(Bottom View)
VCC

10
S 9 1 1D+

D+ 8 2 1D–

D– 7 3 2D+

OE 6 5 4 2D–

GND

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
1D+ 1 I/O
USB port 1
1D– 2 I/O
2D+ 3 I/O
USB port 2
2D– 4 I/O
GND 5 — Ground
OE 6 I Bus-switch enable
D– 7 I/O
Common USB port
D+ 8 I/O
S 9 I Select input
VCC 10 — Supply voltage

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 4.6 V
(2) (3)
VIN Control input voltage –0.5 7 V
VI/O Switch I/O voltage (2) (3) (4)
–0.5 7 V
IIK Control input clamp current VIN < 0 –50 mA
II/OK I/O port clamp current VI/O < 0 –50 mA
II/O ON-state switch current (5) ±120 mA
Continuous current through VCC or GND ±100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O.
(5) II and IO are used to denote specific conditions for II/O.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 2000 V

6.3 Recommended Operating Conditions

(1)
See .
MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
VCC = 2.3 V to 2.7 V
VIH High-level control input voltage 0.46 × VCC VCC V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VIL Low-level control input voltage 0 0.25 × VCC V
VCC = 2.7 V to 3.6 V
VI/O Data input/output voltage 0 5.5 V
TA Operating free-air temperature –40 85 °C

(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.4 Thermal Information

TS3USB221
THERMAL METRIC (1) DRC (VSON) RSE (UQFN) UNIT
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 57.7 169.8
RθJC(top) Junction-to-case (top) thermal resistance 87.7 84.7
RθJB Junction-to-board thermal resistance 32.6 94.9
°C/W
ψJT Junction-to-top characterization parameter 8.2 5.7
ψJB Junction-to-board characterization parameter 32.8 94.9
RθJC(bot) Junction-to-case (bottom) thermal resistance 18.5 N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT
VIK VCC = 3.6 V, 2.7 V, II = –18 mA –1.8 V
Control
IIN VCC = 3.6 V, 2.7 V, 0 V, VIN = 0 V to 3.6 V ±1 μA
inputs
(3) VCC = 3.6 V, 2.7 V, VIN = VCC or GND,
IOZ ±1 μA
VO = 0 V to 3.6 V, VI = 0 V, Switch OFF
VI/O = 0 V to 3.6 V ±2
IOFF VCC = 0 V μA
VI/O = 0 V to 2.7 V ±1
VCC = 3.6 V, 2.7 V, II/O = 0 V,
ICC 30 μA
VIN = VCC or GND, Switch ON or OFF
ICC
(low VCC = 3.6 V, 2.7 V, Switch disabled
1 μA
power VIN = VCC or GND (OE in high state)
mode)

(4) Control One input at 1.8 V, VCC = 3.6 V 20

ΔICC μA
inputs Other inputs at VCC or GND VCC = 2.7 V 0.5
Control
Cin VCC = 3.3 V, 2.5 V, VIN = 3.3 V or 0 V 1 2 pF
inputs
VI/O = 3.3 V or 0
Cio(OFF) VCC = 3.3 V, 2.5 V, Switch OFF 3 4 pF
V,
VI/O = 3.3 V or 0
Cio(ON) VCC = 3.3 V, 2.5 V, Switch ON 5 6 pF
V,

(5)
VI = 0 V, IO = 30 mA 6
ron VCC = 3 V, 2.3 V Ω
VI = 2.4 V, IO = –15 mA 6
VI = 0 V, IO = 30 mA 0.2
Δron VCC = 3 V, 2.3 V Ω
VI = 1.7, IO = –15 mA 0.2
VI = 0 V, IO = 30 mA 1
ron(flat) VCC = 3 V, 2.3 V Ω
VI = 1.7, IO = –15 mA 1

(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.

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6.6 Dynamic Electrical Characteristics, VCC = 3.3 V ± 10%

over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER TEST CONDITIONS TYP (1) UNIT
XTALK Crosstalk RL = 50 Ω, f = 250 MHz –40 dB
OIRR OFF isolation RL = 50 Ω, f = 250 MHz –41 dB
BW Bandwidth (–3 dB) RL = 50 Ω 1.1 GHz

(1) For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.

6.7 Dynamic Electrical Characteristics, VCC = 2.5 V ± 10%

over operating range, TA = –40°C to 85°C, VCC = 2.5 V ± 10%, GND = 0 V
PARAMETER TEST CONDITIONS TYP (1) UNIT
XTALK Crosstalk RL = 50 Ω, f = 250 MHz –39 dB
OIRR OFF isolation RL = 50 Ω, f = 250 MHz –40 dB
BW Bandwidth (–3 dB) RL = 50 Ω 1.1 GHz

(1) For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.

6.8 Switching Characteristics, VCC = 3.3 V ± 10%

over operating range, TA = –40°C to 85°C, VCC = 3.3 V ± 10%, GND = 0 V
PARAMETER MIN TYP (1) MAX UNIT
(2) (3)
tpd Propagation delay 0.25 ns
S to D, nD 30
tON Line enable time ns
OE to D, nD 17
S to D, nD 12
tOFF Line disable time ns
OE to D, nD 10
tSK(O) Output skew between center port to any other port (2) 0.1 0.2 ns
(2)
tSK(P) Skew between opposite transitions of the same output (tPHL – tPLH) 0.1 0.2 ns

(1) For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
(2) Specified by design
(3) The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. This time constant adds very little propagational delay to
the system because it is much smaller than the rise/fall times of typical driving signals. Propagational delay of the bus switch, when used
in a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.

6.9 Switching Characteristics, VCC = 2.5 V ± 10%

over operating range, TA = –40°C to 85°C, VCC = 2.5 V ± 10%, GND = 0 V
PARAMETER MIN TYP (1) MAX UNIT
(2) (3)
tpd Propagation delay 0.25 ns
S to D, nD 50
tON Line enable time ns
OE to D, nD 32
S to D, nD 23
tOFF Line disable time ns
OE to D, nD 12
tSK(O) Output skew between center port to any other port (2) 0.1 0.2 ns
tSK(P) Skew between opposite transitions of the same output (tPHL – tPLH) (2) 0.1 0.2 ns

(1) For Maximum or Minimum conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.
(2) Specified by design
(3) The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance.
The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. The time constraint adds very little propagational delay
to the system because it is much smaller than the rise and fall times of typical driving signals. Propagational delay of the bus switch,
when used in a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the
driven side.

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6.10 Typical Characteristics

0 0

VCC = 3.3 V
–1 VCC = 2.5 V
–20

–2
–40

Attenuation (dB)
Gain (dB)

–3
–60

–4

–80
–5

VCC = 3.3 V –100

–6 VCC = 2.5 V

–7 –120
100.0E+3 1.0E+6 10.0E+6 100.0E+6 1.0E+9 10.0E+9
100.0E+3 1.0E+6 10.0E+6 100.0E+6 1.0E+9 10.0E+9

Frequency (Hz) Frequency (Hz)

Figure 1. Gain vs Frequency Figure 2. OFF Isolation vs Frequency

0 3.5

3.4
–20

3.3
–40
Attenuation (dB)

3.2
ron (Ω)

–60
3.1

–80
3.0

–100 VCC = 3.3 V

2.9 VCC = 3.0 V
VCC = 2.5 V
VCC = 2.3 V
–120 2.8
100.0E+3 1.0E+6 10.0E+6 100.0E+6 1.0E+9 10.0E+9 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Frequency (Hz) VIN (V)

Figure 3. Crosstalk vs Frequency Figure 4. ron vs VIN (IOUT = –15 mA)

3.5

3.4

3.3

3.2
ron (Ω)

3.1

3.0

2.9 VCC = 3.0 V

VCC = 2.3 V

2.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VIN (V)
Figure 5. ron vs VIN (IOUT = –30 mA)

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7 Parameter Measurement Information

VCC

TEST RL CL VCOM
1D or 2D VOUT1 or VOUT2
tON 500 Ω 50 pF V+
VIN D
1D or 2D CL(2) RL
tOFF 500 Ω 50 pF V+

VCTRL S
Logic 1.8 V
CL(2) RL Input 50% 50%
Logic (VI) 0
GND
Input(1)
tON tOFF
Switch VOH
Output 90% 90%
(VOUT1 or VOUT2) VOL

(1) All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50W, t r < 5 ns, t f < 5 ns.
(2) CL includes probe and jig capacitance.

Figure 6. Turnon (tON) and Turnoff Time (tOFF)

VCC
Network Analyzer

Channel OFF: 1D to D
50 Ω VOUT1 1D
VCTRL = VCC or GND
D VIN
Source
50 Ω 2D
Signal Network Analyzer Setup

VCTRL S Source Power = 0 dBm

50 Ω (632-mV P-P at 50-Ω load)
+ GND
DC Bias = 350 mV

Figure 7. OFF Isolation (OISO)

VCC
Network Analyzer
Channel ON: 1D to D
50 Ω VOUT1 1D Channel OFF: 2D to D
VIN VCTRL = VCC or GND
Source
VOUT2 2D
Signal
50 Network Analyzer Setup
VCTRL S
50 Ω + Source Power = 0 dBm
GND (632-mV P-P at 50-Ω load)
DC Bias = 350 mV

Figure 8. Crosstalk (XTALK)

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Parameter Measurement Information (continued)

VCC
Network Analyzer

50 Ω VOUT1 1D Channel ON: 1D to D

D VIN VCTRL = VCC or GND
Source
2D
Signal
Network Analyzer Setup

50 Ω VCTRL S Source Power = 0 dBm

+ (632-mV P-P at 50-Ω load)
GND
DC Bias = 350 mV

Figure 9. Bandwidth (BW)

800 mV
50% 50%
Input 400 mV

tPLH tPHL

50% 50%
Output

Figure 10. Propagation Delay

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Parameter Measurement Information (continued)

800 mV

50% 50%
Input
400 mV
tPLH tPHL

VOH

50%
Output
VOL
tSK(P) = | tPHL – tPLH |

PULSE SKEW tSK(P)

800 mV

50% 50%
Input
400 mV
tPLH1 tPHL1
VOH

50% 50%
Output 1
tSK(O) VOL
tSK(O)
VOH

50% 50%
Output 2
VOL
tPLH2 tPHL2

tSK(O) = | tPLH1 – tPLH2 | or | tPHL1 – tPHL2 |

OUTPUT SKEW tSK(P)

Figure 11. Skew Test

VCC

VOUT1 1D

D VIN
+ Channel ON
VOUT2 2D
VIN VOUT2 or VOUT1
r on – Ω
IIN
VCTRL IIN
S VCTRL = VIH or VIL
+
GND

Figure 12. ON-State Resistance (ron)

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Parameter Measurement Information (continued)

VCC

VOUT1 1D

D VIN
+
VOUT2 2D +
OFF-State Leakage Current
Channel OFF
VCTRL = VIH or VIL
VCTRL S
+
GND

Figure 13. OFF-State Leakage Current

VCC

VOUT1 1D
Capacitance
Meter VBIAS = VCC or GND
VOUT2 2D
VCTRL = VCC or GND
VIN D
VBIAS Capacitance is measured at 1D,
VCTRL S 2D, D, and S inputs during ON
and OFF conditions.

GND

Figure 14. Capacitance

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8 Detailed Description

8.1 Overview
The TS3USB221 device is a 2-channel SPDT switch specially designed for the switching of high-speed USB 2.0
signals in handset and consumer applications, such as cell phones, digital cameras, and notebooks with hubs or
controllers with limited USB I/Os. The wide bandwidth (1.1 GHz) of this switch allows signals to pass with
minimum edge and phase distortion. The device multiplexes differential outputs from a USB host device to one of
two corresponding outputs. The switch is bidirectional and offers little or no attenuation of the high-speed signals
at the outputs. The device also has a low power mode that reduces the power consumption to 1 μA for portable
applications with a battery or limited power budget.
The device is designed for low bit-to-bit skew and high channel-to-channel noise isolation, and is compatible with
various standards, such as high-speed USB 2.0 (480 Mbps).
The TS3USB221 device integrates ESD protection cells on all pins, is available in a tiny μQFN package (2 mm ×
1.5 mm) and is characterized over the free-air temperature range from –40°C to 85°C.

8.2 Functional Block Diagram

D+ 1D+
D− 1D−

2D+
2D−

S
Digital Control
OE

8.3 Feature Description

8.3.1 Low Power Mode
The TS3USB221 has a low power mode that reduces the power consumption to 1 μA when the device is not in
use. The bus-switch enable pin OE must be supplied with a logic high signal to put the device in low power mode
and disable the switch.

8.4 Device Functional Modes

Table 1. Truth Table
S OE FUNCTION
X H Disconnect
L L D = 1D
H L D = 2D

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

There are many USB applications in which the USB hubs or controllers have a limited number of USB I/Os. The
TS3USB221 solution can effectively expand the limited USB I/Os by switching between multiple USB buses in
order to interface them to a single USB hub or controller. TS3USB221 can also be used to connect a single
controller to two USB connectors.

9.2 Typical Application

3.3 V

0.1 μF 0.1 μF

VCC
System
Controller TS3USB221
2-channel
SPDT
Switch S
Control Logic OE
1D+
1D- USB Port 1
D+
USB
Controller D-
2D+
USB Port 2
2D-

GND

Figure 15. Simplified Schematic

9.2.1 Design Requirements

Design requirements of the USB 1.0, 1.1, and 2.0 standards should be followed.
TI recommends that the digital control pins S and OE be pulled up to VCC or down to GND to avoid undesired
switch positions that could result from the floating pin.

9.2.2 Detailed Design Procedure

The TS3USB221 may be properly operated without any external components. However, it is recommended that
unused pins be connected to ground through a 50-Ω resistor to prevent signal reflections back into the device.

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Typical Application (continued)

9.2.3 Application Curves

0.5 0.5
0.4 0.4
0.3 0.3
Differential Signal (V)

Differential Signal (V)

0.2 0.2
0.1 0.1
0.0 0.0
–0.1 –0.1
–0.2 –0.2
–0.3 –0.3
–0.4 –0.4
–0.5 –0.5

0.0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0
–9 –9
Time (X 10 ) (s) Time (X 10 ) (s)

Figure 16. Eye Pattern: 480-Mbps USB Signal With No Figure 17. Eye Pattern: 480-Mbps USB Signal With Switch
Switch (Through Path) NC Path

0.5
0.4
0.3
Differential Signal (V)

0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
–0.5

0.0 0.2 0.4 0.5 0.8 1.0 1.2 1.4 1.6 1.8 2.0
–9
Time (X 10 ) (s)

Figure 18. Eye Pattern: 480-Mbps USB Signal With Switch NO Path

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10 Power Supply Recommendations

Power to the device is supplied through the VCC pin and should follow the USB 1.0, 1.1, and 2.0 standards. TI
recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth out lower
frequency noise to provide better load regulation across the frequency spectrum.

11 Layout

11.1 Layout Guidelines

Place supply bypass capacitors as close to VCC pin as possible. Avoid placing the bypass caps near the D+/D–
traces.
The high-speed D+/D– traces should always be matched lengths and must be no more than 4 inches, otherwise
the eye diagram performance may be degraded. A high-speed USB connection is made through a shielded,
twisted pair cable with a differential characteristic impedance. In the layout, the impedance of D+ and D– traces
should match the cable characteristic differential impedance for optimal performance.
Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points on twisted pair
lines; through-hole pins are not recommended.
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then
the stub should be less than 200 mm.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
A printed circuit board with at least four layers is recommended because of high frequencies associated with the
USB; two signal layers separated by a ground and power layer as shown in Figure 19.

Signal 1

GND Plane

Power Plane

Signal 2

Figure 19. Four-Layer Board Stack-Up

The majority of signal traces should run on a single layer, preferably Signal 1. Immediately next to this layer
should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or
power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing
the number of signal vias reduces EMI by reducing inductance at high frequencies. For more information on
layout guidelines, see High Speed Layout Guidelines (SCAA082) and USB 2.0 Board Design and Layout
Guidelines (SPRAAR7).

Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TS3USB221
TS3USB221
SCDS220I – NOVEMBER 2006 – REVISED JANUARY 2016 www.ti.com

11.2 Layout Example

LEGEND

VIA to Power Plane Polygonal Copper Pour

VIA to GND Plane

Bypass Capacitor

V+

To Microcontroller

10
1 1D+ VCC S 9
USB Port 1

2 1D- D+ 8

To USB Host
3 2D+ D- 7
USB Port 2
4 2D- OE 6
GND
5

To Microcontroller

Figure 20. Package Layout Diagram

16 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated

Product Folder Links: TS3USB221

 TS3USB221
www.ti.com SCDS220I – NOVEMBER 2006 – REVISED JANUARY 2016

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
• High Speed Layout Guidelines, SCAA082
• USB 2.0 Board Design and Layout Guidelines, SPRAAR7

12.2 Trademarks
MIPI is a trademark of Mobile Industry Processor Interface Alliance.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TS3USB221
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN080104RSER ACTIVE UQFN RSE 10 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (L57 ~ L5O ~ L5R ~
& no Sb/Br) L5V)
TS3USB221DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU | Level-2-260C-1 YEAR -40 to 85 ZWG
& no Sb/Br) CU NIPDAUAG
TS3USB221DRCRG4 ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ZWG
& no Sb/Br)
TS3USB221RSER ACTIVE UQFN RSE 10 3000 Green (RoHS CU NIPDAU | Level-1-260C-UNLIM -40 to 85 (L57 ~ L5O ~ L5R ~
& no Sb/Br) CU NIPDAUAG L5V)
TS3USB221RSERG4 ACTIVE UQFN RSE 10 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 (L57 ~ L5O ~ L5R ~
& no Sb/Br) L5V)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-May-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TS3USB221DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TS3USB221RSER UQFN RSE 10 3000 180.0 8.4 1.68 2.13 0.76 4.0 8.0 Q1
TS3USB221RSER UQFN RSE 10 3000 180.0 9.5 1.7 2.3 0.75 4.0 8.0 Q1
TS3USB221RSER UQFN RSE 10 3000 180.0 9.5 1.7 2.2 0.75 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 6-May-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TS3USB221DRCR VSON DRC 10 3000 370.0 355.0 55.0
TS3USB221RSER UQFN RSE 10 3000 202.0 201.0 28.0
TS3USB221RSER UQFN RSE 10 3000 184.0 184.0 19.0
TS3USB221RSER UQFN RSE 10 3000 189.0 185.0 36.0

Pack Materials-Page 2
www.ti.com
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