LMV 358

LMV358, LMV321, LMV324, LMV324S
SLOS263Y – AUGUST 1999 – REVISED AUGUST 2023
LMV3xx Low-Voltage Rail-to-Rail Output Operational Amplifier
1 Features 3 Description
• For an upgraded version - refer to LMV321A, For an upgraded version with enhanced performance,
LMV358A, and LMV324A please refer to LMV321A, LMV358A, and LMV324A.
• 2.7-V and 5-V performance
The LMV321, LMV358, and LMV324 devices are
• –40°C to +125°C operation
single, dual, and quad low-voltage (2.7 V to 5.5 V)
• No crossover distortion
operational amplifiers with rail-to-rail output swing.
• Low supply current
These devices are the most cost-effective solutions
– LMV321: 130 μA (typical) for applications where low-voltage operation, space
– LMV358: 210 μA (typical) saving, and low cost are needed. These amplifiers
– LMV324: 410 μA (typical) are designed specifically for low-voltage (2.7 V to 5
• Rail-to-rail output swing V) operation, with performance specifications meeting
• ESD protection exceeds JESD 22 or exceeding the LM358 and LM324 devices that
– 2000-V human-body model operate from 5 V to 30 V. With package sizes down to
– 1000-V charged-device model one-half the size of the DBV (SOT-23) package, these
2 Applications devices can be used for a variety of applications.
• Desktop PCs Device Information

PART NUMBER CHANNEL COUNT PACKAGE(1) PACKAGE SIZE(2)
• HVAC: heating, ventilating, and air conditioning
DBV (SOT-23, 5) 2.90 mm × 2.80 mm
• Motor control: AC induction LMV321 Single
DCK (SC-70, 5) 2.00 mm × 2.10 mm
• Net-books
D (SOIC, 8) 4.90 mm × 6.00 mm
• Portable media players
DDU (VSSOP, 8) 2.00 mm × 3.10 mm
• Power: telecom DC/DC module: digital LMV358 Dual
DGK (VSSOP, 8) 3.00 mm × 4.90 mm
• Professional audio mixers
PW (TSSOP, 8) 3.00 mm × 6.40 mm
• Refrigerators D (SOIC, 14) 8.65 mm × 6.00 mm
• Washing machines: high-end and low-end LMV324 Quad
PW (TSSOP, 14) 5.00 mm × 6.40 mm
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
IN–
–
OUT
IN+
+
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLOS263Y – AUGUST 1999 – REVISED AUGUST 2023 www.ti.com
Table of Contents
1 Features............................................................................1 7.1 Overview................................................................... 16
2 Applications..................................................................... 1 7.2 Functional Block Diagram......................................... 16
3 Description.......................................................................1 7.3 Feature Description...................................................17
4 Revision History.............................................................. 2 7.4 Device Functional Modes..........................................17
5 Pin Configuration and Functions...................................3 8 Application and Implementation.................................. 18
6 Specifications.................................................................. 5 8.1 Typical Application.................................................... 18
6.1 Absolute Maximum Ratings........................................ 5 8.2 Power Supply Recommendations.............................20
6.2 ESD Ratings............................................................... 5 8.3 Layout....................................................................... 21
6.3 Recommended Operating Conditions ........................5 9 Device and Documentation Support............................22
6.4 Thermal Information: LMV321.................................... 5 9.1 Receiving Notification of Documentation Updates....22
6.5 Thermal Information: LMV324.................................... 5 9.2 Support Resources................................................... 22
6.6 Thermal Information: LMV358.................................... 6 9.3 Trademarks............................................................... 22
6.7 Electrical Characteristics: VCC+ = 2.7 V......................6 9.4 Electrostatic Discharge Caution................................22
6.8 Electrical Characteristics: VCC+ = 5 V.........................7 9.5 Glossary....................................................................22
6.9 Typical Characteristics................................................ 8 10 Mechanical, Packaging, and Orderable
7 Detailed Description......................................................16 Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision X (May 2020) to Revision Y (August 2023) Page
• Updated the Device Information table to include channel count and package lead size................................... 1
Changes from Revision W (October 2014) to Revision X (May 2020) Page

• Deleted LMV324S mentions on the front page of the data sheet ......................................................................1
• Added recommended device notice for LMV321A, LMV358A, and LMV324A...................................................1
• Changed Device Information table to sort devices by channel count in ascending order.................................. 1
• Changed Pin Configuration and Functions section by dividing the Pin Functions table into separate tables
per device........................................................................................................................................................... 3
• Deleted LMV324S pinout information ................................................................................................................ 3
• Changed HBM ESD voltage from 2500 V to 2000 V.......................................................................................... 5
• Changed CDM ESD voltage from 1500 V to 1000 V.......................................................................................... 5
• Deleted Shutdown voltage threshold for LMV324S............................................................................................ 5
• Changed Thermal Information section by dividing the Thermal Information table into separate tables
per device........................................................................................................................................................... 5
• Changed Thermal Information for LMV321 ....................................................................................................... 5
• Deleted LMV324S Thermal Information ............................................................................................................ 5
• Deleted LMV324S test condition for supply current ...........................................................................................6
• Changed output short-circuit current for sourcing from 60 mA to 40 mA ...........................................................7
• Changed output short-circuit current for sinking from 160 mA to 40 mA ........................................................... 7
• Added specified by characterization table notes to output short-circuit current, output swing, and input bias
current specifications ......................................................................................................................................... 7
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: LMV358 LMV321 LMV324 LMV324S

www.ti.com SLOS263Y – AUGUST 1999 – REVISED AUGUST 2023
5 Pin Configuration and Functions
OUT 1 8 VCC+
1IN± 2 7 2OUT
1IN+ 3 6 2IN±
GND 4 5 2IN+
Not to scale
Figure 5-1. D, DDU, DGK, and PW Packages, 8-Pin SOIC, VSSOP, and TSSOP (Top View)
Table 5-1. Pin Functions: LMV358

PIN
TYPE(1) DESCRIPTION
NAME NO.
1IN+ 3 I Noninverting input
1IN– 2 I Inverting input
2OUT 7 O Output
GND 4 — Negative supply
OUT 1 O Output
VCC+ 8 — Positive supply
(1) I = input, O = output
1IN+ 1 5 VCC+
GND 2
1IN± 3 4 OUT
Not to scale
Figure 5-2. DBV and DCK Packages, 5-Pin SOT-23 and SC-70 (Top View)

PIN
TYPE(1) DESCRIPTION
NAME NO.
OUT 4 O Output
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

OUT 1 14 4OUT
1IN± 2 13 4IN±
1IN+ 3 12 4IN+
VCC+ 4 11 GND
2IN+ 5 10 3IN+
2IN± 6 9 3IN±
2OUT 7 8 3OUT
Not to scale
Figure 5-3. D and PW Packages, 14-Pin SOIC and TSSOP (Top View)

PIN
TYPE(1) DESCRIPTION
NAME NO.
3/4 SHDN — I Shutdown (logic low ) / enable (logic high)
1/2 SHDN — I Shutdown (logic low) / enable (logic high)
2OUT 7 O Output
3OUT 8 O Output
4OUT 14 O Output
OUT 1 O OUT

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage(2) 5.5 V
VID Differential input voltage(3) ±5.5 V
VI Input voltage range (either input) –0.2 5.7 V
At or below TA = 25°C,
Duration of output short circuit (one amplifier) to ground(4) Unlimited
VCC ≤ 5.5 V
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values (except differential voltages and VCC specified for the measurement of IOS) are with respect to the network GND.
(3) Differential voltages are at IN+ with respect to IN–.
(4) Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
6.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
0 2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
0 1000
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage (single-supply operation) 2.7 5.5 V
I temperature (LMV321, LMV358,
–40 125
TA Operating free-air temperature LMV324, LMV321IDCK) °C
Q temperature –40 125
6.4 Thermal Information: LMV321

LMV321
THERMAL METRIC(1) DBV (SOT-23) DCK (SC-70) UNIT
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 232.9 239.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

LMV324
THERMAL METRIC(1) D (SOIC) PW (TSSOP) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 102.1 148.3 °C/W
report.


LMV358
D (SOIC) DGK DDU (VSSOP) PW (TSSOP)
THERMAL METRIC(1) UNIT
(VSSOP)
8 PINS 8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 207.9 201.2 210 200.7 °C/W
report.
6.7 Electrical Characteristics: VCC+ = 2.7 V

VCC+ = 2.7 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIO Input offset voltage 1.7 7 mV
Average temperature coefficient of
αVIO 5 μV/°C
input offset voltage
IIB Input bias current 11 250 nA
IIO Input offset current 5 50 nA
CMRR Common-mode rejection ratio VCM = 0 to 1.7 V 50 63 dB
kSVR Supply-voltage rejection ratio VCC = 2.7 V to 5 V, VO = 1 V 50 60 dB
0 –0.2
VICR Common-mode input voltage range CMRR ≥ 50 dB V
1.9 1.7
High level VCC – 100 VCC – 10
VO Output swing RL = 10 kΩ to 1.35 V mV
Low level 60 180
LMV321I 80 170
ICC Supply current LMV358I (both amplifiers) 140 340 μA
LMV324I (all four amplifiers) 260 680
B1 Unity-gain bandwidth CL = 200 pF 1 MHz
Φm Phase margin 60 deg
Gm Gain margin 10 dB
Vn Equivalent input noise voltage f = 1 kHz 46 nV/√ Hz
In Equivalent input noise current f = 1 kHz 0.17 pA/√ Hz
(1) Typical values represent the likely parametric nominal values determined at the time of characterization. Typical values depend on the
application and configuration and may vary over time. Typical values are not ensured on production material.

6.8 Electrical Characteristics: VCC+ = 5 V

VCC+ = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
TA = 25°C 1.7 7
VIO Input offset voltage mV
TA = –40°C to +125°C 9
Average temperature
αVIO coefficient of input offset TA = 25°C 5 μV/°C
voltage
TA = 25°C 15 250(1)
IIB Input bias current nA
TA = –40°C to +125°C 500(1)
TA = 25°C 5 50(1)
IIO Input offset current nA
TA = –40°C to +125°C 150(1)
Common-mode rejection VCM = 0 to 4 V
CMRR 50 65 dB
ratio TA = 25°C
Supply-voltage rejection VCC = 2.7 V to 5 V, VO = 1 V, VCM = 1 V
kSVR 50 60 dB
ratio TA = 25°C
Common-mode input 0 –0.2

VICR CMRR ≥ 50 dB, TA = 25°C V
voltage range 4.2 4
RL = 2 kΩ to 2.5 V, high level, TA = 25°C VCC – 300 VCC – 40
RL = 2 kΩ to 2.5 V, high level, TA = –40°C to
VCC – 400(1)
+125°C
TA = 25°C, low level 120 300
TA = –40°C to +125°C, low level 400(1)
VO Output swing mV
RL = 10 kΩ to 2.5 V, high level, TA = 25°C VCC – 100 VCC – 10
RL = 10 kΩ to 2.5 V, high level, TA = –40°C to
VCC – 200(1)
+125°C
TA = 25°C, low level 65 180
TA = –40°C to +125°C, low level 280(1)
Large-signal differential RL = 2 kΩ, TA = 25°C 15 100

AVD V/mV
voltage gain RL = 2 kΩ, TA = –40°C to +125°C 10(1)
Output short-circuit Sourcing, VO = 0 V, TA = 25°C 5(1) 40

IOS mA
current Sinking, VO = 5 V, TA = 25°C 10(1) 40
LMV321I, TA = 25°C 130 250
LMV321I, TA = –40°C to +125°C 350
LMV358I (both amplifiers), TA = 25°C 210 440
ICC Supply current LMV358I (both amplifiers), TA = –40°C to μA

615
+125°C
LMV324I (all four amplifiers), TA = 25°C 410 830
LMV324I (all four amplifiers), TA = –40°C to
1160
+125°C
B1 Unity-gain bandwidth CL = 200 pF, TA = 25°C 1 MHz
Φm Phase margin TA = 25°C 60 deg
Gm Gain margin TA = 25°C 10 dB
Equivalent input
Vn f = 1 kHz, TA = 25°C 39 nV/√ Hz
noise voltage
Equivalent input
In f = 1 kHz, TA = 25°C 0.21 pA/√ Hz
noise current
SR Slew rate TA = 25°C 1 V/μs
(1) Specified by characterization. Not production tested.

6.9 Typical Characteristics

80 120 80 120
Vs = 2.7 V Vs = 5.0 V
70 RL = 100 kΩ, 2 kΩ, 600 Ω 105 70 RL = 100 kΩ, 2 kΩ, 600 Ω 105
60 Phase 90 60 90
600 Ω
Phase
Phase Margin − Deg

50 75 50 75
600 Ω
2 kΩ
Gain − dB
Gain − dB
40 60 40 60
2 kΩ 100 kΩ
30 100 kΩ 45 30 45
Gain Gain
20 30 20 100 kΩ 30
10 600 Ω 100 kΩ 15 10 15
2 kΩ 2 kΩ
0 0 0 600 Ω 0
−10 −15 −10 −15

1k 10 k 100 k 1M 10 M 1k 10 k 100 k 1M 10 M
Frequency − Hz Frequency − Hz
Figure 6-1. LMV321 Frequency Response vs Resistive Load Figure 6-2. LMV321 Frequency Response vs Resistive Load
70 100 70 100
Phase Phase
60 0 pF 80 60 80
0 pF
50 60 50 60
100 pF 1000 pF 100 pF
40 40 40 40

30 500 pF 20 30 20
Gain − dB
Gain − dB
1000 pF 500 pF
Gain
20 0 20 0
Gain
10 −20 10 −20
0 Vs = 5.0 V −40 Vs = 5.0 V 0 0 pF −40

100 pF 500 pF RL = 100 kΩ
RL = 600 Ω
−10 0 pF −60 −10 CL = 0 pF 100 pF −60
CL = 0 pF
100 pF 100 pF
500 pF
−20 500 pF 1000 pF −80 −20 500 pF −80
1000 pF 1000 pF
1000 pF
−30 −100 −30 −100
10 k 100 k 1M 10 M 10 k 100 k 1M 10 M
Figure 6-3. LMV321 Frequency Response vs Capacitive Load Figure 6-4. LMV321 Frequency Response vs Capacitive Load
80 120 10000
Vs = 5.0 V
2.5 V
70 RL = 2 kΩ 105 LMV324S
(25% Overshoot) _
VO
60 90 VI +
85°C RL CL
Capacitive Load − pF
1000 −2.5 V
50 Phase 75
25°C
Gain − dB
40 60
−40°C LMV3xx
30 Gain 45 (25% Overshoot)
100
20 85°C 30
25°C VCC = ±2.5 V
10 15 AV = +1
RL = 2 kΩ
0 −40°C 0 VO = 100 mVPP
10
−10 −15 −2 −1.5 −1 −0.5 0 0.5 1 1.5
1k 10 k 100 k 1M 10 M
Output Voltage − V
Frequency − Hz
Figure 6-5. LMV321 Frequency Response vs Temperature Figure 6-6. Stability vs Capacitive Load

6.9 Typical Characteristics (continued)

10000 10000
VCC = ±2.5 V
2.5 V RL = 2 kΩ
_ AV = 10
VO LMV324S
VO = 100 mVPP
VI + (25% Overshoot)
RL CL
Capacitive Load − nF
Capacitive Load − pF
1000 2.5 V 1000
LMV324S
(25% Overshoot)
LMV3xx
(25% Overshoot)
100 134 kΩ 1.21 MΩ

100
+2.5 V
LMV3xx VCC = ±2.5 V
_
(25% Overshoot) AV = +1 VO
RL = 1 MΩ VI +
RL CL
VO = 100 mVPP
−2.5 V
10 10
−2.0 −1.5 −1 −0.5 0 0.5 1 1.5 −2.0 −1.5 −1 −0.5 0 0.5 1 1.5
Output Voltage − V Output Voltage − V
Figure 6-7. Stability vs Capacitive Load Figure 6-8. Stability vs Capacitive Load
10000 1.500
RL = 100 kΩ
VCC = ±2.5 V
1.400
RL = 1 MΩ LMV3xx
AV = 10 (25% Overshoot) 1.300
VO = 100 mVPP
Slew Rate − V/ms

1.200 Gain
Capacitive Load − nF
1000 NSLEW
1.100
LMV324S
LMV3xx
(25% Overshoot) 1.000
PSLEW
0.900
134 kΩ 1.21 MΩ
100
+2.5 V 0.800
NSLEW
_
VO 0.700
VI + LMV324S
RL CL
0.600
−2.5 V PSLEW
10 0.500
−2.0 −1.5 −1 −0.5 0 0.5 1 1.5 2.5 3.0 3.5 4.0 4.5 5.0
Output Voltage − V V CC − Supply Voltage − V
Figure 6-9. Stability vs Capacitive Load Figure 6-10. Slew Rate vs Supply Voltage
700 −10
VCC = 5 V
LMV3xx VI = VCC/2
600
LMV324S
TA = 85°C −20
500
Supply Current − µA
Input Current − nA
TA = 25°C −30
400
LMV3xx
300
TA = −40°C −40
200
−50
100 LMV324S
0 −60
0 1 2 3 4 5 6 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80
VCC − Supply Voltage − V TA − °C
Figure 6-11. Supply Current vs Supply Voltage: Quad Amplifier Figure 6-12. Input Current vs Temperature


100 100
VCC = 2.7 V VCC = 5 V
10 10
Sourcing Current − mA
LMV3xx
LMV3xx
1 1
LMV324S
LMV324S
0.1
0.1
0.01
0.01
0.001
0.001 0.001 0.01 0.1 1 10
0.001 0.01 0.1 1 10
Output Voltage Referenced to VCC+ − V
Output Voltage Referenced to VCC+ − V
Figure 6-14. Source Current vs Output Voltage
Figure 6-13. Source Current vs Output Voltage
100 100
VCC = 2.7 V VCC = 5 V
10 10
LMV324S LMV324S
Sinking Current − mA
1 1
LMV3xx
LMV324
0.1 0.1
0.01 0.01
0.001 0.001
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Voltage Referenced to GND − V Output Voltage Referenced to GND − V
Figure 6-15. Sinking Current vs Output Voltage Figure 6-16. Sinking Current vs Output Voltage
300 120
LMV324S
270 VCC = 5 V
100
240
LMV324S
210 VCC = 5 V
LMV3xx 80
VCC = 5 V LMV3xx
180
VCC = 5 V
150 60
LMV3xx
120 VCC = 2.7 V
40
90 LMV3xx
LMV324S VCC = 2.7 V
60 VCC = 2.7 V
20 LMV324S
30 VCC = 2.7 V
0 0
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 −40 −30 −20−10 0 10 20 30 40 50 60 70 80 90
TA − °C TA − °C
Figure 6-17. Short-Circuit Current vs Temperature Figure 6-18. Short-Circuit Current vs Temperature


80 90
LMV324S LMV324S
VCC = −5 V VCC = 5 V
70 80 RL = 10 kΩ
RL = 10 kΩ
70
60
LMV3xx LMV3xx
60
50
−k SVR − dB
+k SVR − dB
50
40
40
30
30
20
20
10 10
0 0
100 1k 10k 100k 1M 100 1k 10k 100k 1M
Figure 6-19. –kSVR vs Frequency Figure 6-20. +kSVR vs Frequency
80 80
LMV324S
LMV324S VCC = −2.7 V VCC = 2.7 V
70 RL = 10 kΩ 70 RL = 10 kΩ
60 60
LMV3xx LMV3xx
50 50
−kSVR − dB
+k SVR − dB
40 40
30 30
20 20
10 10
0 0
100 1k 10k 100k 1M 100 1k 10k 100k 1M
Figure 6-21. –kSVR vs Frequency Figure 6-22. +kSVR vs Frequency
70 6
RL = 10 kΩ RL = 10 kΩ
THD > 5%
60 AV = 3
5
Output Voltage Swing − mV
Peak Output Voltage − V OPP
LMV3xx LMV3xx
50 Negative Swing LMV324S VCC = 5 V
4
LMV324S
40 VCC = 5 V
3
30 LMV3xx
VCC = 2.7 V
2
20 LMV324S
Positive Swing VCC = 2.7 V
10 1
0 0
2.5 3.0 3.5 4.0 4.5 5.0 1k 10k 100k 1M 10M
VCC − Supply Voltage − V Frequency − Hz
Figure 6-23. Output Voltage Swing From Rails vs Supply Figure 6-24. Output Voltage vs Frequency
Voltage


110 150
LMV3xx VCC = 5 V
100 LMV3xx VCC = 2.7 V RL = 5 kΩ
VCC = 5 V 140 AV = 1
90 VO = 3 VPP
Crosstalk Rejection − dB
80 130
Impedance − Ω
70
120
60 LMV324S
VCC = 2.7 V
50
LMV324S 110
VCC = 5 V
40
100
30
20 90
1 1M 2M 3M 4M 100 1k 10k 100k
Figure 6-25. Open-Loop Output Impedance vs Frequency Figure 6-26. Cross-Talk Rejection vs Frequency
Input Input
LMV3xx LMV3xx
1 V/Div
1 V/Div
LMV324S LMV324S
VCC = ±2.5 V VCC = ±2.5 V

RL = 2 kΩ RL = 2 kΩ
TA = 25°C TA = 85°C
1 µs/Div 1 µs/Div
Figure 6-27. Noninverting Large-Signal Pulse Response Figure 6-28. Noninverting Large-Signal Pulse Response
Input Input
LMV3xx
LMV3xx
50 mV/Div
1 V/Div
LMV324S
LMV324S
VCC = ±2.5 V VCC = ±2.5 V

TA = −40°C TA = 25°C
1 µs/Div 1 µs/Div
Figure 6-29. Noninverting Large-Signal Pulse Response Figure 6-30. Noninverting Small-Signal Pulse Response

Input Input
LMV3xx LMV3xx
50 mV/Div
50 mV/Div
LMV324S
LMV324S
VCC = ±2.5 V VCC = ±2.5 V

TA = 85°C TA = −40°C
1 µs/Div 1 µs/Div
Figure 6-31. Noninverting Small-Signal Pulse Response Figure 6-32. Noninverting Small-Signal Pulse Response
Input Input
LMV3xx LMV3xx
1 V/Div
1 V/Div
LMV324S LMV324S
VCC = ±2.5 V VCC = ±2.5 V

TA = 25°C TA = 85°C
1 µs/Div 1 µs/Div
Figure 6-33. Inverting Large-Signal Pulse Response Figure 6-34. Inverting Large-Signal Pulse Response
Input Input
LMV3xx
LMV3xx
50 mV/Div
1 V/Div
LMV324S LMV324S
VCC = ±2.5 V VCC = ±2.5 V

TA = −40°C TA = 25°C
1 µs/Div 1 µs/Div
Figure 6-35. Inverting Large-Signal Pulse Response Figure 6-36. Inverting Small-Signal Pulse Response

Input Input
LMV3xx LMV3xx
50 mV/Div
50 mV/Div
LMV324S
LMV324S
VCC = ±2.5 V VCC = ±2.5 V

TA = 85°C TA = −40°C
1 µs/Div 1 µs/Div
Figure 6-37. Inverting Small-Signal Pulse Response Figure 6-38. Inverting Small-Signal Pulse Response
0.80 0.50
VCC = 2.7 V VCC = 5 V
0.45
0.40
Input Current Noise − pA/ Hz
Input Current Noise − pA/ Hz

0.60
0.35
0.30
0.40 0.25
0.20
0.15
0.20
0.10
0.05
0.00 0.00
10 100 1k 10k 10 100 1k 10k
Figure 6-39. Input Current Noise Figure 6-40. Input Current Noise vs Frequency
vs Frequency
200 10.000
VCC = 2.7 V
180 RL = 10 kΩ
AV = 1
Input Voltage Noise − nV/ Hz
160 VO = 1 VPP
1.000
140
120
THD − %
LMV3xx
0.100
100
80
VCC = 2.7 V 0.010
60
40 LMV324S
VCC = 5 V
20 0.001
10 100 1k 10k 10 100 1000 10000 100000
Figure 6-41. Input Voltage Noise vs Frequency Figure 6-42. THD + N vs Frequency


10.000 10.000
VCC = 2.7 V VCC = 5 V
RL = 10 kΩ RL = 10 kΩ
AV = 10 AV = 1
VO = 1 VPP VO = 1 VPP
1.000 1.000
LMV324S
THD − %
THD − %
0.100 0.100
LMV324S
LMV3xx
0.010 0.010
LMV3xx
0.001 0.001
10 100 1000 10000 100000 10 100 1000 10000 100000
Figure 6-43. THD + N vs Frequency Figure 6-44. THD + N vs Frequency
10.000
VCC = 5 V
RL = 10 kΩ
AV = 10
VO = 2.5 VPP
1.000
LMV324S
THD − %
0.100
0.010 LMV3xx
0.001
10 100 1000 10000 100000
Frequency − Hz
Figure 6-45. THD + N vs Frequency

7 Detailed Description
7.1 Overview
The LMV321, LMV358, and LMV324 devices are single, dual, and quad low-voltage (2.7 V to 5.5 V) operational
amplifiers with rail-to-rail output swing.
The LMV321, LMV358, and LMV324 devices are the most cost-effective solutions for applications where
low-voltage operation, space saving, and low cost are needed. These amplifiers are designed specifically for
low-voltage (2.7 V to 5 V) operation, with performance specifications meeting or exceeding the LM358 and
LM324 devices that operate from 5 V to 30 V. Additional features of the LMV3xx devices are a common-mode
input voltage range that includes ground, 1-MHz unity-gain bandwidth, and 1-V/μs slew rate.
The LMV321 device is available in the ultra-small package, which is approximately one-half the size of the DBV
(SOT-23) package. This package saves space on printed circuit boards and enables the design of small portable
electronic devices. It also allows the designer to place the device closer to the signal source to reduce noise
pickup and increase signal integrity.
7.2 Functional Block Diagram
VCC
VBIAS1
+ VCC
–
VBIAS2
+
Output
–
VCC VCC
VBIAS3
+
IN-
VBIAS4–
IN+ +

7.3 Feature Description

7.3.1 Operating Voltage
The LMV321, LMV358, and LMV324 devices are fully specified and ensured for operation from
2.7 V to 5 V. In addition, many specifications apply from –40°C to 125°C. Parameters that vary significantly with
operating voltages or temperature are shown in the Typical Characteristics graphs.
7.3.2 Unity-Gain Bandwidth
The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without
greatly distorting the signal. The LMV321, LMV358, LMV324 devices have a 1-MHz unity-gain bandwidth.
7.3.3 Slew Rate
The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. The LMV321, LMV358, LMV324 devices have a 1-V/μs slew rate.
7.4 Device Functional Modes
The LMV321, LMV358, LMV324 devices are powered on when the supply is connected. Each of these devices
can be operated as a single supply operational amplifier or dual supply amplifier depending on the application.

8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Typical Application

Some applications require differential signals. Figure 8-1 shows a simple circuit to convert a single-ended input
of 0.5 to 2 V into differential output of ±1.5 V on a single 2.7-V supply. The output range is intentionally limited
to maximize linearity. The circuit is composed of two amplifiers. One amplifier acts as a buffer and creates a
voltage, VOUT+. The second amplifier inverts the input and adds a reference voltage to generate VOUT–. Both
VOUT+ and VOUT– range from 0.5 to 2 V. The difference, VDIFF, is the difference between VOUT+ and VOUT–. The
LMV358 was used to build this circuit.
R2
R1 2.7 V
VOUT-
+
R3 +
VREF
R4
2.5 V
VDIFF
±
VOUT+
+
VIN
Figure 8-1. Schematic for Single-Ended Input to Differential Output Conversion

8.1.1 Design Requirements

The design requirements are as follows:
• Supply voltage: 2.7 V
• Reference voltage: 2.5 V
• Input: 0.5 to 2 V
• Output differential: ±1.5 V
8.1.2 Detailed Design Procedure
The circuit in Figure 8-1 takes a single-ended input signal, VIN, and generates two output signals, VOUT+ and
VOUT– using two amplifiers and a reference voltage, VREF. VOUT+ is the output of the first amplifier and is a
buffered version of the input signal, VIN (see Equation 1). VOUT– is the output of the second amplifier which
uses VREF to add an offset voltage to VIN and feedback to add inverting gain. The transfer function for VOUT– is
Equation 2.
VOUT+ = VIN (1)
æ R 44 ö æ R22 ö R22
out - = VREF
VOUT ref ´ ç ÷ ´ ç1 + ÷ - VINin ´ R1
R
è 3 3+
+ R 4 ø
4 è R11ø 1 (2)
The differential output signal, VDIFF, is the difference between the two single-ended output signals, VOUT+ and
VOUT–. Equation 3 shows the transfer function for VDIFF. By applying the conditions that R1 = R2 and R3 = R4, the
transfer function is simplified into Equation 6. Using this configuration, the maximum input signal is equal to the
reference voltage and the maximum output of each amplifier is equal to the VREF. The differential output range is
2×VREF. Furthermore, the common mode voltage will be one half of VREF (see Equation 7).
æ R ö æ R4 öæ R2 ö
VD IF F = V O U T + - V O U T - = VIN ´ ç 1 + 2 ÷ - VR E F ´ ç ÷ ç1 + ÷
è R 1 ø R
è 3 + R 4 øè R1 ø (3)
VOUT+ = VIN (4)
VOUT– = VREF – VIN (5)
VDIFF = 2×VIN – VREF (6)
æV + VOUT - ö 1
Vcm = ç OUT + ÷ = VREF
è 2 ø 2 (7)
8.1.2.1 Amplifier Selection

Linearity over the input range is key for good dc accuracy. The common mode input range and the output swing
limitations determine the linearity. In general, an amplifier with rail-to-rail input and output swing is required.
Bandwidth is a key concern for this design. Because LMV358 has a bandwidth of 1 MHz, this circuit will only be
able to process signals with frequencies of less than 1 MHz.
8.1.2.2 Passive Component Selection
Because the transfer function of VOUT– is heavily reliant on resistors (R1, R2, R3, and R4), use resistors with low
tolerances to maximize performance and minimize error. This design used resistors with resistance values of
36 kΩ with tolerances measured to be within 2%. If the noise of the system is a key parameter, the user can
select smaller resistance values (6 kΩ or lower) to keep the overall system noise low. This ensures that the noise
from the resistors is lower than the amplifier noise.

8.1.3 Application Curves

The measured transfer functions in Figure 8-2, Figure 8-3, and Figure 8-4 were generated by sweeping the input
voltage from 0 V to 2.5 V. However, this design should only be used between 0.5 V and 2 V for optimum linearity.
2.5 2.5
2.0
1.5 2.0
1.0
VOUT+ (V)
VDIFF (V)
0.5 1.5
0.0
±0.5 1.0
±1.0
±1.5 0.5
±2.0
±2.5 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
VIN (V) C003 VIN (V) C001
Figure 8-2. Differential Output Voltage vs Input Figure 8-3. Positive Output Voltage Node vs Input
Voltage Voltage
3.0
2.5
2.0
VOUTt (V)
1.5
1.0
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5
VIN (V) C002
Figure 8-4. Positive Output Voltage Node vs Input Voltage
8.2 Power Supply Recommendations

The LMV321, LMV358, LMV324 devices are specified for operation from 2.7 to 5 V; many specifications apply
from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 5.5 V can permanently damage the device (see the Absolute Maximum
Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.

8.3 Layout
8.3.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Ensure to physically separate digital and
analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
8.3.2 Layout Example
RIN
VIN +
VOUT
RG
RF
Figure 8-5. Operational Amplifier Schematic for Noninverting Configuration
Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
VS+
away from the supply lines
as possible RF
OUT1 V+
RG
GND IN1í OUT2
GND
VIN IN1+ IN2í
R IN
Ví IN2+
Only needed for Use low-ESR, ceramic
dual-supply bypass capacitor
operation
VSí
GND
(or GND for single supply) Ground (GND) plane on another layer
Figure 8-6. Operational Amplifier Board Layout for Noninverting Configuration

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 27-Nov-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LMV321IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RC1F Samples
LMV321IDBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RC1F Samples
LMV321IDBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RC1F Samples
LMV321IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RC1F Samples
LMV321IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 (R3F, R3K, R3O, R3 Samples
| NIPDAUAG R, R3Z)
LMV321IDCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 (R3F, R3K, R3O, R3 Samples
R, R3Z)
LMV321IDCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 (R3C, R3F, R3R) Samples
| NIPDAUAG
LMV324ID LIFEBUY SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LMV324I
LMV324IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LMV324I Samples
LMV324IDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LMV324I Samples
LMV324IDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LMV324I Samples
LMV324IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 MV324I Samples
LMV324IPWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV324I Samples
LMV324IPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV324I Samples
LMV324QD LIFEBUY SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LMV324Q
LMV324QDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LMV324Q Samples
LMV324QDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LMV324Q Samples
LMV324QPW NRND TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV324Q
LMV324QPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 MV324Q Samples
LMV324QPWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 MV324Q Samples
LMV358ID LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358I
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LMV358IDDUR LIFEBUY VSSOP DDU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RA5R
LMV358IDDURG4 NRND VSSOP DDU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RA5R
LMV358IDG4 NRND SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358I
LMV358IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 (R5B, R5Q, R5R) Samples
LMV358IDGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 (R5B, R5Q, R5R) Samples
LMV358IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 MV358I Samples
LMV358IDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358I Samples
LMV358IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358I Samples
LMV358IPW LIFEBUY TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358I
LMV358IPWG4 NRND TSSOP PW 8 150 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358I
LMV358IPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 MV358I Samples
LMV358IPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358I Samples
LMV358QD LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358Q
LMV358QDDUR LIFEBUY VSSOP DDU 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 RAHR
LMV358QDG4 LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358Q
LMV358QDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 (RHO, RHR) Samples
LMV358QDGKRG4 ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 (RHO, RHR) Samples
LMV358QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 MV358Q Samples
LMV358QPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 MV358Q Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Feb-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV321IDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321IDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV321IDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
LMV321IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
LMV321IDCKR SC70 DCK 5 3000 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
LMV321IDCKT SC70 DCK 5 250 180.0 8.4 2.3 2.5 1.2 4.0 8.0 Q3
LMV324IDR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
LMV324IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LMV324IDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LMV324IDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LMV324IDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LMV324IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LMV324IPWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LMV324QDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LMV324QDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
LMV324QPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV358IDDUR VSSOP DDU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
LMV358IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LMV358IDR SOIC D 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
LMV358IDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LMV358QDDUR VSSOP DDU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
LMV358QDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV358QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
LMV358QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV321IDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV321IDBVT SOT-23 DBV 5 250 210.0 185.0 35.0
LMV321IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
LMV321IDCKR SC70 DCK 5 3000 180.0 180.0 18.0
LMV321IDCKR SC70 DCK 5 3000 210.0 185.0 35.0
LMV321IDCKT SC70 DCK 5 250 210.0 185.0 35.0
LMV324IDR SOIC D 14 2500 364.0 364.0 27.0
LMV324IDR SOIC D 14 2500 333.2 345.9 28.6
LMV324IDRG4 SOIC D 14 2500 340.5 336.1 32.0
LMV324IDRG4 SOIC D 14 2500 356.0 356.0 35.0
LMV324IDRG4 SOIC D 14 2500 356.0 356.0 35.0
LMV324IPWR TSSOP PW 14 2000 356.0 356.0 35.0
LMV324IPWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
LMV324QDR SOIC D 14 2500 356.0 356.0 35.0
LMV324QDR SOIC D 14 2500 356.0 356.0 35.0
LMV324QPWR TSSOP PW 14 2000 356.0 356.0 35.0
LMV324QPWR TSSOP PW 14 2000 366.0 364.0 50.0
LMV358IDDUR VSSOP DDU 8 3000 202.0 201.0 28.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV358IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
LMV358IDR SOIC D 8 2500 340.5 338.1 20.6
LMV358IDR SOIC D 8 2500 364.0 364.0 27.0
LMV358IDRG4 SOIC D 8 2500 340.5 338.1 20.6
LMV358IPWR TSSOP PW 8 2000 356.0 356.0 35.0
LMV358IPWR TSSOP PW 8 2000 356.0 356.0 35.0
LMV358QDDUR VSSOP DDU 8 3000 202.0 201.0 28.0
LMV358QDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
LMV358QDR SOIC D 8 2500 340.5 338.1 20.6
LMV358QDR SOIC D 8 2500 356.0 356.0 35.0
LMV358QPWR TSSOP PW 8 2000 366.0 364.0 50.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LMV324ID D SOIC 14 50 506.6 8 3940 4.32
LMV324QD D SOIC 14 50 506.6 8 3940 4.32
LMV324QPW PW TSSOP 14 90 530 10.2 3600 3.5
LMV358ID D SOIC 8 75 506.6 8 3940 4.32
LMV358ID D SOIC 8 75 507 8 3940 4.32
LMV358IDG4 D SOIC 8 75 507 8 3940 4.32
LMV358IDG4 D SOIC 8 75 506.6 8 3940 4.32
LMV358IPW PW TSSOP 8 150 530 10.2 3600 3.5
LMV358IPWG4 PW TSSOP 8 150 530 10.2 3600 3.5
LMV358QD D SOIC 8 75 507 8 3940 4.32
LMV358QDG4 D SOIC 8 75 507 8 3940 4.32
PACKAGE OUTLINE
PW0008A SCALE 2.800
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE

SCALE:10X
SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS

NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1 5
2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)
4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
ALTERNATIVE PACKAGE SINGULATION VIEW
4214839/J 02/2024
NOTES:
per ASME Y14.5M.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/J 02/2024
NOTES: (continued)

www.ti.com
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/J 02/2024
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA
1 5
2X 0.65 NOTE 4
2.15
1.3 (0.15) 1.3
2 1.85
(0.1)
4
0.33 3
5X
0.15
0.1
0.1 C A B (0.9) TYP
0.0
NOTE 5
0.15
GAGE PLANE 0.22
TYP
0.08
8 0.46
TYP TYP
0 0.26
SEATING PLANE
4214834/D 07/2023
NOTES:
per ASME Y14.5M.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
www.ti.com
DCK0005A SOT - 1.1 max height
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X (0.65)
3 4
(R0.05) TYP (2.2)

EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/D 07/2023
NOTES: (continued)

www.ti.com
DCK0005A SOT - 1.1 max height
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X(0.65)
3 4
(R0.05) TYP
(2.2)

BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/D 07/2023
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)

www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
www.ti.com
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
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LMV358, LMV321, LMV324, LMV324S

SLOS263Y – AUGUST 1999 – REVISED AUGUST 2023

LMV3xx Low-Voltage Rail-to-Rail Output Operational Amplifier

• Desktop PCs Device Information

(1) For all available packages, see the orderable addendum at

Changes from Revision W (October 2014) to Revision X (May 2020) Page

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: LMV358 LMV321 LMV324 LMV324S

5 Pin Configuration and Functions

Table 5-1. Pin Functions: LMV358

(1) I = input, O = output

Table 5-2. Pin Functions: LMV321

(1) I = input, O = output

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Table 5-3. Pin Functions: LMV324

(1) I = input, O = output

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6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information: LMV321

6.5 Thermal Information: LMV324

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6.6 Thermal Information: LMV358

6.7 Electrical Characteristics: VCC+ = 2.7 V

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6.8 Electrical Characteristics: VCC+ = 5 V

Common-mode input 0 –0.2

Large-signal differential RL = 2 kΩ, TA = 25°C 15 100

Output short-circuit Sourcing, VO = 0 V, TA = 25°C 5(1) 40

ICC Supply current LMV358I (both amplifiers), TA = –40°C to μA

(1) Specified by characterization. Not production tested.

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6.9 Typical Characteristics

Phase Margin − Deg

Phase Margin − Deg

−10 −15 −10 −15

Phase Margin − Deg

0 Vs = 5.0 V −40 Vs = 5.0 V 0 0 pF −40

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6.9 Typical Characteristics (continued)

1000 2.5 V 1000

100 134 kΩ 1.21 MΩ

Slew Rate − V/ms

Output Voltage − V V CC − Supply Voltage − V

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6.9 Typical Characteristics (continued)

Output Voltage Referenced to GND − V Output Voltage Referenced to GND − V

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6.9 Typical Characteristics (continued)

Peak Output Voltage − V OPP

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6.9 Typical Characteristics (continued)

VCC = ±2.5 V VCC = ±2.5 V

VCC = ±2.5 V VCC = ±2.5 V