Manual MSE5010
Manual MSE5010
Manual MSE5010
HARDWARE DESCRIPTION
MSE 5010
HARDWARE DESCRIPTION
CONTENTS
1. EQUIPMENT ARCHITECTURE 8
2.3 SL16 13
2.4 SLQ4/SLD4/SL4 17
2.5 SLQ1/SL1 22
2.7 SPQ4/MU04 33
2.8 PD3/PL3/D34S/C34S 39
2.9 PQ1/PQM/PD1/D75S/D12S/D12B 45
2.10 EGS2 51
2.11 EFS4/EFS0/ETF8 56
2.12 CXL1/CXL4/CXL16 62
2.13 EOW 69
2.14 AUX 72
2.16 FAN 77
3. CABLES 79
3.1 75Ω
Ω E1 Cable 79
3.2 120Ω
Ω E1/T1 Cable 82
3.6 75Ω
Ω Clock Cable 89
3.7 120Ω
Ω Clock Cable 90
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3.12 Fiber 98
4. INDICATOR DESCRIPTION FOR EQUIPMENT AND BOARD 99
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MODIFICATIONS PAGE
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1. EQUIPMENT ARCHITECTURE
The MSE 5010 is composed of power supply unit, fan unit, boards and cables, as shown in Fig 1-1.
Boards and their corresponding slots of the MSE 5010 are shown in Table 1-1.
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2. BOARDS
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Caution:
Always wear an ESD wrist strap when holding the board, and make sure the
ESD wrist strap is well grounded, thus to prevent the static electricity from
damaging the board.
Warning:
It is strictly forbidden to stare into the optical interface board and the optical
interface, lest the laser beam inside the optical fiber would hurt your eyes.
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2.3 SL16
SL16 is the STM-16 optical interface board, responsible for STM-16 optical signal processing.
SL16 can be seated in Slot 11~ 13.
2.3.1.1 Functions
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2.3.1.2 Principles
Fig 2-2 shows the functional diagram of SL16.
Active cross-
Data and connect board
1 x STM-16 Interface SDH signal
clock
optical signal unit processing
recovery
unit Standby cross-
unit
connect board
SCC
Overhead bus
Cross-connect
Clock signal and timing unit
The STM-16 optical signal is accessed at the interface unit and sent to the SDH signal processing unit after data
and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements frame
search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the
incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are
re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to
the cross-connect and timing unit.
The timing unit extracts the clock signal at line side and receives system clock and frame header from the active
and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and
communication unit mainly functions control, communication and service configuration of the board. The power
module provides all modules of the board with DC power supply with required voltage.
The overhead processing unit extracts the overhead bytes from the one channel of overhead signal it receives, and
sends the extracted bytes to SCC and its paired board through the overhead bus according to related sequence
and clock requirements. In transmit direction, the overhead processing unit re-arranges the received overhead
signals from SCC or its paired board and then inserts them into the SOH.
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Color and
Indicator Description
status
On, green The board works normally.
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Color and
Indicator Description
status
On, green Service is normal, no service alarm occurs.
2.3.3 Interface
The optical interface of SL16 is LC.
Description
Parameter
SL16
Rate 2488320kbit/s
Connector LC
Power 20
consumption
(W)
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Description
Parameter
SL16
Transmission 0~2 2~15 15~40 40~80 80~10 80~14 140~1
distance (km) 0 0 70
2.4 SLQ4/SLD4/SL4
SLQ4 is the 4 × STM-4 optical interface board; SLD4 is the 2 × STM-4 optical interface board; SL4 is the 1 × STM-
4 optical interface board. All are responsible for STM-4 optical signal processing.
Table 2-3 shows the difference between these three optical interface boards.
2.4.1.1 Functions
SLQ4, SLD4 and SL4 can access and process 4, 2 and 1 × STM-4
optical signal respectively.
Support VC-4-4c concatenated services.
Support I-4, S-4.1, L-4.1, L-4.2 and Ve-4.2 optical interfaces for
different transmission distances.
Support various protection schemes such as two-fiber and four-fiber
bidirectional MSP, linear MSP, and SNCP.
Provide abundant alarm and performance events for convenient
equipment management and maintenance.
Support inloop and outloop at optical interfaces for fast fault location.
Support ALS function, avoiding laser injury to human body during
maintenance.
Support on-line query of the board information.
Support configuration of such bytes as D1-D3, D4-D12 (DCC), E1 and
E2 (ECC) to transparent transmission or into other unused overhead
bytes.
Support smooth software upgrade and expansion.
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2.4.1.2 Principles
Fig 2-4 shows the functional diagram of SLQ4/SLD4/SL4.
Active cross-
Data and connect board
4/2/1 x STM-4 Interface SDH signal
clock
optical signal unit processing
recovery
unit Standby cross-
unit
connect board
SCC
Overhead bus
Cross-connect
Clock signal and timing unit
The 4/2/1 × STM-4 optical signals are accessed at the interface unit and sent to the SDH signal processing unit
after data and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements
frame search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to
the incoming signals and then sends them to overhead processing unit for further processing. After that, the signals
are re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent
to the cross-connect and timing unit.
The timing unit extracts the clock signal at line side and receives system clock and frame header from the active
and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and
communication unit mainly functions control, communication and service configuration of the board. The power
module provides all modules of the board with DC power supply with required voltage.
The overhead processing unit extracts the overhead bytes from the two channels of overhead signals it receives,
and sends the extracted bytes to SCC and its paired board through the overhead bus according to related
sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received
overhead signals from SCC or its paired board and then inserts them into the SOH.
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2.4.3 Interface
SLQ4, SLD4 and SL4 provide LC optical interfaces.
Description
Parameter
SLQ4 SLD4 SL4
Rate 622080kbit/s
Connector LC
Power 16 15 14.5
consumption
(W)
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2.5 SLQ1/SL1
SLQ1 is the 4 × STM-1 optical interface board;
SL1 is the 1 × STM-1 optical interface board.
Both are responsible for STM-1 optical signal processing
Table 2-5 shows the difference between these two optical interface boards.
2.5.1.1 Functions
SLQ1 and SL1 access and process four and one channel of STM-1
optical signal respectively.
Support Ie-1, I-1, S-1.1, L-1.1, L-1.2 and V-1.2 optical interfaces for
different transmission distances.
Support various protection schemes such as two-fiber unidirectional
MSP, linear MSP and SNCP.
Provide abundant alarm and performance events for convenient
equipment management and maintenance.
Support inloop and outloop at optical interfaces for fast fault location.
Support ALS function, avoiding laser injury to human body during
maintenance.
Support on-line query of the board information.
Support configuration of such bytes as D1-D3, D4-D12 (DCC), E1 and
E2 (ECC) to transparent transmission or into other unused overhead
bytes.
Support smooth software upgrade and expansion.
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2.5.1.2 Principles
Fig 2-6 shows the functional diagram of SLQ1/SL1.
Active cross-
Data and connect board
4/1 x STM-1 Interface SDH signal
clock
optical signal unit processing
recovery
unit Standby cross-
unit
connect board
SCC
Overhead bus
Cross-connect
Clock signal and timing unit
The 4/1 × STM-1 optical signals are accessed at the interface unit and sent to the SDH signal processing unit after
data and clock signal extraction at data and clock recovery unit. The SDH signal processing unit implements frame
search, SOH termination and insertion, overhead byte extraction, pointer justification and POH monitoring to the
incoming signals and then sends them to overhead processing unit for further processing. After that, the signals are
re-timed with the system clock, and then multiplexed into 622M data signals after cross-connect and finally sent to
the cross-connect and timing unit.
The timing unit extracts the clock signal at line side and receives system clock and frame header from the active
and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and
communication unit mainly functions control, communication and service configuration of the board. The power
module provides all modules of the board with DC power supply with required voltage.
The overhead processing unit extracts the overhead bytes from the two channels of overhead signals it receives,
and sends the extracted bytes to SCC and its paired board through the overhead bus according to related
sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received
overhead signals from SCC or its paired board and then inserts them into the SOH.
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2.5.3 Interface
The interface of SLQ1 and SL1 is LC.
Description
Parameter
SLQ1 SL1
Rate 155520kbit/s
Connector LC
Power 15.5 14
consumption
(W)
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SEP1 is the 8 × STM-1 line processing board, with two STM-1 electrical interfaces on the front panel.
EU08 is the 8 × STM-1 electrical interface board;
EU04 is the 4 × STM-1 electrical interface board;
OU08 is the 8 × STM-1 optical interface board;
TSB8 is the 8 × PDH interface switching & bridging board; and
TSB4 is the 4 × PDH interface switching & bridging board.
Table 2-7 shows the differences between SEP1, EU04, EU08, OU08, TSB8 and TSB4.
EU08 and TSB8 Accessing and processing 8 x STM-1 electrical signal, realizing the 1:1
EPS to SEP1 board.
EU04 and TSB4 Accessing and processing 4 x STM-1 electrical signal, realizing the 1:1
EPS to SEP1 board.
Table 2-7 Comparison between SEP1, EU04, EU08, OU08, TSB8 and TSB4
2.6.1.1 Functions
2.6.1.2 Principles
The functional diagram of SEP1 and TSB8 is shown in Fig 2-8 and Fig 2-9 respectively.
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Active cross-
2/4/8 x STM-1 Data and connect board
SDH signal
optical/electrical Interface clock
unit recovery processing
signals
unit unit Standby cross-
connect board
SCC
Overhead bus
TSB8
Signal
selector
Working Protection
SEP1 SEP1
Allocation
drive 8¡ STM-1
Á
Electrical signal
The interface unit of SEP1 is EU04, EU08 and OU08, which accesses STM-1 signals and sends them to SDH
signal processing unit after data and clock signal extracting at data and clock recovery unit. The SDH signal
processing unit implements frame search, SOH termination and insertion, overhead byte extraction, pointer
justification and POH monitoring to the incoming signals and then sends them to overhead processing unit for
further processing. After that, the signals are re-timed with the system clock, and then multiplexed into 622M data
signals after cross-connect and finally sent to the cross-connect and timing unit.
The timing unit extracts the clock signal at line side and receives system clock and frame header from the active
and standby cross-connect boards. It also provides clock signal for other modules on the board. The control and
communication unit mainly functions control, communication and service configuration of the board. The power
module provides all modules of the board with DC power supply with required voltage.
The overhead processing unit extracts the overhead bytes from the two channels of overhead signals it receives,
and sends the extracted bytes to SCC and its paired board through the overhead bus according to related
sequence and clock requirements. In transmit direction, the overhead processing unit re-arranges the received
overhead signals from SCC or its paired board and then inserts them into the SOH.
TSB8 enables EPS of SEP1. The signal selector of the TSB8 selects one out of the three groups of received
signals from the working SEP1 and sends them to the protection SEP1. The allocation drive allocates the signals
from the protection SEP1 to the working SEP1.
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Fig 2-10 The front panel of SEP1, EU04, EU08, OU08, TSB8 and TSB4
Service On, green The service is activated. (In EPS protection mode, the
activation board is in working status.)
indicator-ACT
Off The service is not activated. (In EPS protection mode,
the board is in protection status.)
On for 100ms and off for Board software is being uploaded to FLASH or FGPA
100ms alternatively,
green
Board software
On for 300ms and off for The board software is initializing, and is in BIOS boot
indicator-PROG
300ms alternatively, stage.
green
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2.6.3 Interface
There are two pairs of 75Ω SMB interface on the panel of SEP1. The
board can access 2 x STM electrical signals when it is used
independently.
SEP1 board can also cooperate with EU08, EU04 or OU08 to realize
different functions.
Table 2-10 shows the comparison between EU08, EU04 and OU08.
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TSB8 and TSB4 enable EPS of SEP1. The specific protection principle
is shown in Fig 2-11.
SLOT 14 SLOT16
Signal
of
TSB8 EU04 Switch
Control
System
Control
Unit
SLOT 4/5
Protection Working
SEP1 SEP1
8 × STM-1(E4)
Failure
Service
SLOT12 SLOT13
When a working SEP1 failure is detected, the cross-connect and timing unit will ask EU04 to transfer the signal to
TSB8, and thus to bridging the signals of EU04 and protection SEP1.
Note:
EPS is a scheme at device level. When the working board fails, the accessed
signal will be protected by being bridged to the protection board. By this way,
triggering of more complex protection at network level such as MSP and
SNCP can be avoided, improving the equipment reliability.
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Description
Parameter
SEP1 EU08 EU04 OU08 TSB8 TSB4
Rate 155520kbit/s
Power 17 11 6 6 5 2.5
consumption
(W)
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2.7 SPQ4/MU04
SPQ4 is the 4 × E4/STM-1 processing board; and MU04 is the 4 x E4/STM-1 interface board.
SPQ4 can work with MU04 to access and process 4 × E4/STM-1 electrical signals; and SPQ4 and MU04 can work
with TSB4 to provide 1:1 EPS to SPQ4.
SPQ4 can be seated in Slot 12 ~ 13, MU04 in Slot 14, 16, and TSB4 in Slot 14, 16.
2.7.1.1 Functions
2.7.1.2 Principles
Fig 2-12 shows the functional diagram of SPQ4.
Mapping/
demapping Active cross-
4 x E4/STM-1 . Data and unit Bus connect board
Interface clock conversion
electrical . unit recovery unit
signals Overhead
. unit Standby cross-
processing
unit connect board
Control and
communication unit Other boards
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The interface unit for SPQ4 is MU04, at which the 4 × E4/STM-1 electrical signals are accessed. Then the data
signals extracted by the data and clock recovery unit are sent to the mapping/demapping unit and overhead
processing unit for signal processing, SOH byte termination and insertion, and overhead data extraction.
The control and communication unit communicates with the SCC and others boards through the Ethernet port to
collect and report alarm and performance events, and interpret and process the configuration command sent by
NM.
The power module provides all modules on the board with required DC power supply and monitors the power
supply status.
TSB4 enables EPS of SPQ4. The signal selector of the TSB4 selects one out of received signals from working
SPQ4 and sends them to the protection SEP1. The allocation drive allocates the signals from the protection SPQ4
to working SPQ4.
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2.7.3 Interface
SLOT 14 SLOT16
signal of
switching
TSB 4 MU04
control
System
Control
Unit
SLOT 4/5
protecting working
SPQ4 SPQ4
failure 4 x E 4 service
SLOT12 SLOT13
When a working SPQ4 failure is detected, the cross-connect and timing unit will ask MU04 to transfer the signals to
TSB4, thus to bridging the signals of MU04 and protection SPQ4.
The slot assignment of SPQ4, MU04 and TSB4 is shown in Table 2-11
TSB4 Slot 14
MU04 Slot 16
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Note:
EPS is a scheme at device level. When the working board fails, the accessed
signal will be protected by being bridged to the protection board. By this way,
triggering of more complex protection at network level such as MSP and
SNCP can be avoided, improving the equipment reliability.
Description
Parameter
SPQ4 MU04
Rate 139264kbit/s or 155520kbit/s
Power 24 2
consumption
(W)
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2.8 PD3/PL3/D34S/C34S
Board
PD3 PL3
Comparison
Processing capability 6 × E3/DS3 3 × E3/DS3
2.8.1.1 Functions
2.8.1.2 Principles
Fig 2-15 shows the functional diagram of PD3/PL3.
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Active cross-
Mapping/ connect board
3/6 x E3/DS3 Interface Bus
demapping
electrical unit conversion
unit
signals unit Standby cross-
connect board
Control and
Timing unit communication unit
Cross-connect
and timing unit
Clock signal
The interface unit accesses E3/DS3 electrical signals through D34S/C34S and recovers the data and clock signals.
Also, the interface unit performs decoding/encoding and jitter suppressing to the signals, generates and detects
pseudo-random binary sequence (PRBS), and detects and inserts part of the alarms. The mapping/demapping unit
maps/demaps the E3/DS3 signal, processes the lower order overhead, suppresses the jitter, and generates and
detects the PRBS. The bus conversion unit converts the low speed bus at board side into the high speed bus at
protection board side.
The timing unit receives the 38M clock signal and 2K frame header from the active and standby cross-connect and
timing units at the same time and performs the clock frequency conversion and drive of the board. Additionally, the
8K line reference clock signal is for board status checking. It is sent to the active and standby cross-connect boards
and indicates whether the board works normal and whether the board is in position.
The control and communication unit mainly functions control, communication and service configuration of the
board. The power module provides all modules of the board with DC power supply with required voltage.
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Fig 2-16 The front panel of PD3, PL3, D34S and C34S
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Color and
Indicator Description
status
On, green The board works normally.
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2.8.3 Interface
Interface description of D34S and C34S is shown in Table 2-14
PD3/PL3, D34S/C34S and TSB8/TSB4 can work together to provide 1:1 EPS. Fig 2-17 shows the 1:1 EPS of
PD3.The protection PD3 can be seated in Slot 12, and the working PD3 in Slot 13. D34S is in Slot 16, and TSB8 is
in Slot 14.
When a working PD3 failure is detected, the cross-connect and timing unit will ask the interface board to switch the
service from service bus to protection bus for protection.
SLOT 14 SLOT16
Signal of
TSB8 Switching
D34S
control
System
Control
unit
SLOT 4/5
protecting working
PD3 PD3
SLOT12 SLOT13
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Description
Parameter
PL3 PD3 D34S C34S
Rate 34368kbit/s or 44736kbit/s
Power 15 19 2 2
consumption
(W)
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2.9 PQ1/PQM/PD1/D75S/D12S/D12B
D75S, D12S and D12B can work as interfaces boards to receive/transmit E1/T1 service for PQ1/PQM/PD1. D75S
and D12S can also work as switching boards to implement EPS for PQ1/PQM/PD1.
Table 2-15 shows the difference between PQ1, PD1 and PQM.
Board name
PQ1 PQM PD1
Comparison
Processing capability 63 × E1 63 × E1/T1 32 × E1
2.9.1.1 Functions
2.9.1.2 Principles
0ig 2-18 shows the functional diagram of PQ1/PQM/PD1.
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Control and
Timing unit communication
unit
Cross-connect
Clock signal and timing unit
The interface unit accesses 63 × E1/T1 electrical signals through the interface board and recovers the data and
clock signals. Also, the interface unit performs decoding/encoding and jitter suppressing to the signals, generates
and detects PRBS, and detects and inserts part of the alarms. The frame header extraction & insertion unit extracts
and inserts the frame header of T1 signal, and pass through the E1 service in both the transmit and receive
directions. The mapping/demapping unit maps/demaps the E1/T1 signal, processes the lower order overhead,
suppresses the jitter, and generates and detects the PRBS. The bus conversion unit converts the low speed bus at
board side into the high speed bus at protection board side.
The timing unit receives the 38M clock signal and 2K frame header from the active and standby cross-connect and
timing units at the same time and performs the clock conversion and drive of the board. Additionally, the 8K line
reference clock signal is for board status checking. It is sent to the active and standby cross-connect boards and
indicates whether the board works normal and whether the board is in position.
The control and communication unit mainly functions control, communication and service configuration of the
board. The power module provides all modules of the board with DC power supply with required voltage.
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Fig 2-19 Front panel of PQ1, PQM, PD1, D75S, D12S and D12B
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Color and
Indicator Description
status
On, green The board works normally.
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2.9.3 Interface
Table 2-17 shows the difference between D75S, D12S and D12B.
Comparison
D75S D12S D12B
Board name
Service accessed 32×E1 32×E1/T1 32 × E1/T1
120Ω balanced
interface
PQ1/PQM/PD1 and D75S/D12S can be provided with 1:2 EPS. Fig 2-20 shows the EPS of PQ1.Slot 11 is for
protection PQ1, while Slot 12 - 13 is for working PQ1/PQM/PD1. Slot 14 ~ 15 and 15 ~ 17 is for interface board
D75S/D12S.
When a working PQ1 fails, the cross-connect unit will ask the interface board to switch the service to protection
PQ1 for protection.
SLOT 14 SLOT16
Signal
D75S of
D75S
Switch
Control
System
Control
Unit
SLOT 4/5
Protecting Working Working
PQ1 PQ1 PQ1
Failure E1 Service
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Description
Parameter
PQ1 PQM PD1 D75S D12S D12B
Rate 1544kbit/s or 2048kbit/s
Power 19 22 19 5.5 9 1
consumption
(W)
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2.10 EGS2
EGS2 is the 2-port Gigabit Ethernet (GE) optical interface board with Lanswitch.
EGS2 can transparently transmit and converge the GE service. When working together with EFS0 and EFS4, the
FE service can be converged into GE service and the Layer 2 switching can be performed.
EGS2 can be seated in Slot 11 - 13.
2.10.1.1 Functions
2.10.1.2 Principles
Fig 2-21 shows the functional diagram of EGS2.
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-48V
Control and Power module
communication module
In receive direction:
The interface processing module accesses the 1000BASE-SX/LX signals from external Ethernet equipments such
as Ethernet switch and router and performs decoding and serial/parallel conversion to the signals. Then, the
signals are sent to the service processing module for frame delimitation, preamble field code stripping, cyclic
redundancy code (CRC) termination and Ethernet performance statistics. And flow classification is performed
according to the service type and configuration requirement (message formats MPLS, L2 MPLS VPN and
Ethernet/VLAN are supported), and Tunnel and VC double labels are added according to the service for mapping
and transfer. At the encapsulation module, the HDLC, LAPS or GFP encapsulation is performed to the Ethernet
frame. After that, the services are mapped into VC-3 or VC-12 at the mapping module and then sent to the cross-
connect unit.
In transmit direction:
The VC-3 or VC-12 signals from the cross-connect unit are demapped and sent to the encapsulation module for
decapsulation. The service processing module determines the route according to the level of the equipment, and
performs flow classification according to the service type and configuration requirement. Also, frame delimitation,
adding preamble field code, CRC calculation and performance statistics are performed by the service processing
module. Finally, the signals are sent out from the Ethernet interface after serial/parallel conversion and encoding at
interface processing module.
Control and communication module
The control and communication unit mainly functions control, communication and service configuration of the
board.
Power module
The power module provides all modules of the board with DC power supply with required voltage.
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2.10.3 Interface
EGS2 supports the small-form pluggable (SEP) LC optical interface, and 1000Base-SX and 1000Base-LX
interfaces. The interface transmission distance reaches 500m (multimode) or 10km (single-mode). Table 2-18
shows the interface characteristics of EGS2.
Connector LC
Parameter Description
Board EGS2
Rate 1000Mbit/s
Connector LC (SFP)
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2.11 EFS4/EFS0/ETF8
EFS4 is the 4-ports fast Ethernet processing board with Lanswitch,
EFS0 is the fast Ethernet processing board with Lanswitch.
They are responsible for transparent transmission, convergence and Layer 2 switching of the Ethernet signal.
Board name
EFS4 EFS0
Comparison
Processing capability 4 × 10M/100M 8 × 10M/100M
Ports at panel 4 0
2.11.1.1 Functions
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2.11.1.2 Principles
Fig 2-23 shows the functional diagram of EFS0.
Interface Service
processing Encapsulation Mapping
processing
module (ETF8) module module
module
In receive direction:
The interface processing module accesses the 10/100BASE-TX signals from external Ethernet equipments such as
Ethernet switch and router and performs decoding and serial/parallel conversion to the signals. Then, the signals
are sent to the service processing module for frame delimitation, preamble field code stripping, cyclic redundancy
code (CRC) termination and Ethernet performance statistics. And flow classification is performed according to the
service type and configuration requirement (message formats MPLS, L2 MPLS VPN and Ethernet/VLAN are
supported), and Tunnel and VC double labels are added according to the service for mapping and transfer. At the
encapsulation module, the HDLC, LAPS or GFP encapsulation is performed to the Ethernet frame. After that, the
services are mapped into VC-3 or VC-12 at the mapping module and then sent to the cross-connect unit.
In transmit direction:
The VC-3 or VC-12 signals from the cross-connect and timing unit are demapped and sent to the encapsulation
module for decapsulation. The service processing module determines the route according to the level of the
equipment, and performs flow classification according to the service type and configuration requirement. Also,
frame delimitation, adding preamble field code, CRC calculation and performance statistics are performed by the
service processing module. Finally, the signals are sent out from the Ethernet interface after serial/parallel
conversion and encoding at interface processing module.
Control and communication module
The control and communication unit mainly functions control, communication and service configuration of the
board.
Power module
The power module provides all modules of the board with DC power supply with required voltage.
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2.11.3 Interface
EFS4 provides 4 Ethernet ports, and ETF8 provides the EFS0 with 8 ports. Table 2-21 shows the ports
characteristics.
Type RJ-45
Impedance 100Ω
Two indicators for each interface, their meanings shown in Table 2-22
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Description
Parameter
EFS4 EFS0 EFT8
Rate 10Mbit/s, 100Mbit/s
Accessing capability 4× 0 8×
10M/100M 10M/100M
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2.12 CXL1/CXL4/CXL16
CXL1, CXL4 and CXL16 are boards integrating the functions of the SDH processing unit, system control &
communication unit, cross-connect unit and timing unit at levels of STM-1, STM-4 and STM-16 respectively. Table
2-23 shows a comparison between CXL1, CXL4 and CXL16.
Ling processing
1×STM-1 1×STM-4 1×STM-16
capacity
Cross-connect
capacity (higher 40G/5G 40G/5G 40G/5G
order / lower order)
System control
Same
function
The CXL1, CXL4 and CXL16 boards are responsible for receiving and
transmitting one channel of optical signal at STM-1, STM-4 and STM-
16 level respectively. Their optical interfaces are compliant with ITU-T
Recommendation G.957. Frame structures are compliant with ITU-T
Recommendation G.707, and the jitter specifications compliant with
ITU-T Recommendation G.825 and G.958.
The CXL1 supports S-1.1, L-1.1, L-1.2, and Le-1.2 optical modules for
different transmission distances.
The CXL4 supports S-4.1, L-4.1, L-4.2, and Le-4.2 optical modules for
different transmission distances.
The CXL16 supports 1-16, S-16.1, L-16.1, and L-16.2 optical modules
for different transmission distances.
The CXL16 supports VC-4-4c, VC-4-8c and VC-4-16c concatenated
services.
The CXL16 can connect with the optical multiplex board of wavelength
division equipment without wavelength converter.
Support various protection schemes, such as 2-fiber or 4-fiber
bidirectional MSP ring, linear MSP and SNCP.
Provide abundant alarm and performance events for convenient
equipment management and maintenance.
Provide inloop and outloop at optical interfaces and VC-4 level for fast
fault locating.
Support ALS function, avoiding laser injury to human body during
maintenance.
Support the on-line query of board information and optical power.
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2.12.1.5 Principle
Take CXL16 as an example. Fig 2-27 shows the system diagram of CXL16.The CXL16 integrates SDH processing
unit, cross-connect unit SCC and timing unit at STM-16 level.
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F ro n t P a n e l S T M -1 6 S D H B a c k p la n e
p ro c e s s in g u n it
c ro s s -c o n n e c t u n it
SCC
tim in g u n it
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Indicator status:
Color and
Indicator Description
status
On, green The board works normally.
On for 100ms
Broad software is being uploaded to
and off for 100
FLASH or FGPA.
ms, green
Board software
indicator - On for 300 ms
The board software is initializing, and is
PROG and off for 300
in BIOS boot stage.
ms, green
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Indicator status:
Color and
Indicator Description
status
unit - SRVL Critical or major alarm occurs to the
On, red
service on the line unit.
2.12.3 Interfaces
The CXL1, CXL4 and CXL16 use LC connectors.
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Description
Parameter
CXL1 CXL4 CXL16
Rate 155520kbit/s 622080kbit/s 2488320kbit/s
Connector LC
Power 38 38 39
consumption
CXL1
Transmission 2 - 15 15 - 40 40 - 80 80 - 100
distance (km)
Launched -15 - -8 -5 - 0 -5 - 0 -3 - 2
Optical Power
(dBm)
CXL4
Transmission 2 - 15 15 - 40 40 - 80 80 - 100
distance (km)
Launched -15 - -8 -3 - 2 -3 - 2 -3 - 2
Optical Power
(dBm)
CXL16
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Description
Parameter
CXL1 CXL4 CXL16
Transmission 0-2 2 - 15 15 - 40 40 - 80
distance (km)
Launched -10 - -3 -5 - 0 -2 - 3 -2 - 3
Optical Power
(dBm)
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2.13 EOW
EOW offers order wire phone and data interfaces. EOW is seated in Slot 9.
2.13.1.1 Functions
It provides:
One orderwire phone
Four broadcast data interfaces S1~S4
2.13.1.2 Principles
Fig 2-27 shows the functional diagram of EOW.
Overhead
processing
unit
System control &
communication
Orderwire
unit
phone
Broadcast
data and
Ring orderwire ~ S1
generaating&reset phone unit
S4
, clock unit
Backplane
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Interface Description
PHONE Orderwire Phone Interface
S1 Serial 1
S2 Serial 2
S3 Serial 3
S4 Serial 4
Table 2-24 Description of the EOW interface on the front panel
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2.13.3 Interface
The orderwire phone interface of EOW is RJ-11, the interface of S1 – S4 is the type of RJ-45.
Parameter Description
Board name EOW
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2.14 AUX
AUX is the system auxiliary interface board, seated in slot 10.
2.14.1.1 Functions
2.14.1.2 Principles
Fig 2-29 shows the functional diagram of AUX.
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OAM Interface
F&f module
ETH
Communications 2 interfa ces of NM
COM module
Interface module
The interface module provides access of OAM and F&f. OAM and F&f use the same serial port, and are led out on
the front panel through RJ-45 interface.
External clock input/output module
The external clock input/output module performs access and processing of two building integrated timing supply
systems (BITS), and outputs two clock signals. The input and output share one RJ-45 interface with the impedance
of 120Ω.
Communication module
The module provides on the front panel one NT interface (ETH) and one debugging interface (COM), which pass
through RJ-45 interface.
Power monitoring module
The power monitoring module monitors two -48V power and 3.3V backup power, accomplishes the Boolean value
of three inputs and one output, and is led out on the front panel through RJ-45 interface.
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2.14.3 Interface
The interface provided by AUX is shown in Table 2.26
Interface Description
RJ-45
Parameter Description
Board name AUX
Power consumption 15
(W)
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2.15 PIU
PIU is the power interface board.
It functions power access, lightening protection and filtering, and can be seated in Slot 18 and 19.
2.15.1.1 Functions
2.15.1.2 Principles
Fig 2-31 shows the functional diagram of PIU.
NEG(-) NEG(-)
Protection Filtering
unit unit
RTN(+) RTN(+)
Power
detection
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2.15.3 Interface
The interfaces on PIU board is shown in
表 1-1 The interface description of PIU
Interface Description
PWR The interface of -48V power inputs.
Parameter Description
Board PIU
Power 1.5
consumption (W)
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2.16 FAN
The FAN board contains 6 fans and is used for heat dissipation of the equipment.
The FAN board can be installed in Slot 20.
2.16.1.1 Functions
2.16.1.2 Principle
Block diagram of the FAN unit is shown in Fig 2-33 , followed by the brief introduction of these units.
£ -4 8V 1
GND GND
£ -4 8V 2
P ow er
GND 1 S tart
input F ans
unit
GND 2 unit £ -4 8V £ -4 8V
GND
£ -48V
F ans status
alarm signal
S tatus
step dow n detection
unit £ -4 8V unit GND
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There are two indicators, one handle and one Electrostatic Discharge (ESD) jack on the FAN front panel. Handle
Used to draw out the air filter and FAN board.
Table 2-29 gives a description to the indicator of the FAN board.
2.16.3 Interface
ESD jack: Used to insert static wrist.
Item Description
Number of fans 6
Weight 1.010kg
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3. CABLES
This chapter introduces the architecture and pin assignments of cables of the MSE 5010.
The following cables are used for the MSE 5010:
75Ω E1 cable
3.1 75Ω
Ω E1 Cable
3.1.1 Structure
W1~W4
The pin assignments of the DB78 connector for 75Ω E1 cable are shown in Fig 3-2.
1 20
21 39
40 59
60 78
The 75Ω E1 cable comprises four coaxial cables, namely W1, W2, W3 and W4.
Each coaxial cable is composed of eight cores, numbered 1 through 8 on the sheath respectively. Fig 3-3 shows
the arrangement of these eight cores.
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2
8 3
1 4
7
6 5
The 75Ω E1 cable is terminated with a DB78 connector, for connecting the 75Ω E1 electrical interface board of the
MSE 5010.
Table 1-1shows the pin assignments of DB78 connector for 75Ω E1 cable.
31 Tip 33 Tip
2 T1 2 T5
12 Ring 14 Ring
41 Tip 43 Tip
3 R2 3 R6
61 Ring 63 Ring
70 Tip 72 Tip
4 T2 4 T6
W1 51 Ring W2 53 Ring
3 Tip 5 Tip
5 R3 5 R7
23 Ring 25 Ring
32 Tip 34 Tip
6 T3 6 T7
13 Ring 15 Ring
42 Tip 44 Tip
7 R4 7 R8
62 Ring 64 Ring
71 Tip 8 T4 73 Tip 8 T8
W1 52 Ring 8 T4 W2 54 Ring 8 T8
W3 6 Tip W4 8 Tip
1 R9 1 R13
26 Ring 28 Ring
35 Tip 37 Tip
2 T9 2 T13
16 Ring 18 Ring
45 Tip 47 Tip
3 R10 3 R14
65 Ring 67 Ring
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7 Tip 9 Tip
5 R11 5 R15
27 Ring 29 Ring
36 Tip 38 Tip
6 T11 6 T15
17 Ring 19 Ring
46 Tip 48 Tip
7 R12 7 R16
66 Ring 68 Ring
75 Tip 77 Tip
8 T12 8 T16
56 Ring 58 Ring
able 1-1 Pin assignments of the DB78 connector for 75Ω E1 cable
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3.2 120Ω
Ω E1/T1 Cable
3.2.1 Structure
W1~W4
The pin assignments of the DB78 connector for 120Ω E1/T1 cable are shown in Fig 3-5.
1 20
21 39
40 59
60 78
Fig 3-5 Pin assignments of DB78 connector for 120Ω E1/T1 cable
The 120Ω E1/T1 cable comprises four twisted pairs, namely W1, W2, W3 and W4.
Each twist-pair cable is composed of eight twisted pairs, numbered 1 through 8 on the sheath respectively.
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The 120Ω E1/T1 cable is terminated with a DB78 connector, for connecting the 120Ω E1/T1 electrical interface
board of the MSE 5010.
Table 3-2 shows the pin assignments of DB78 connector for the 120Ω E1/T1 cable.
41 Orange 45 Orange
Pair2 R2 Pair2 R10
61 White/Orange 65 White/Oran
ge
3 Green Pair 7 Green
R3 Pair 3 R11
3
23 White/Green 27 White/Gree
n
42 Brown Pair 46 Brown
R4 Pair 4 R12
4
62 White/Brown 66 White/Brow
W1 W2
n
4 Gray Pair 8 Gray Pair 5 R13
R5
24 White/Gray 5 28 White/Gray
43 Red Pair 47 Red
R6 Pair 6 R14
6
63 White/Red 67 White/Red
5 Black Pair 59 Black
R7 Pair 7 R15
7
25 White/Black 29 White/Black
44 Yellow Pair 48 Yellow
R8 Pair 8 R16
64 White/Yellow 8 68 White/Yello
w
31 Blue 35 Blue
Pair1 T1 Pair1 T9
12 White/Blue 16 White/Blue
70 Orange 74 Orange
W3 Pair2 T2 W4 Pair2 T10
51 White/Orange 55 White/Oran
ge
32 Green Pair 36 Green
T3 Pair 3 T11
13 White/Green 3 17 White/Gree
n
W3 71 Brown Pair W4 75 Brown
T4 Pair 4 T12
4
52 White/Brown 56 White/Brow
n
33 Gray Pair 37 Gray
T5 Pair 5 T13
5
14 White/Gray 18 White/Gray
72 Red Pair 76 Red
T6 Pair 6 T14
53 White/Red 6 57 White/Red
34 Black Pair 38 Black
T7 Pair 7 T15
7
15 White/Black 19 White/Black
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Core number 8
Connector DB78
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3.3.1 Structure
Connector SMB
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3.4.1 Structure
Structure of the power cable is shown in Fig 3-7.
A3
A2
A Main tag Tag 1
A1
X
Fig 3-7 Structure of the -48V/-60 DC power cable
W2 A3 (ground) Black
Table 3-3 Pin assignments of the 3-core connector for power cable
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3.5.1 Structure
Structure of the PGND Cable is shown in Fig 3-8
OT t ermi nal
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3.6 75Ω
Ω Clock Cable
3.6.1 Structure
The 75Ω clock cable is terminated with an SMB connector, for connecting the 75Ω clock interface board of the
MSE 5010.
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3.7 120Ω
Ω Clock Cable
3.7.1 Structure
The 120Ω clock cable is terminated with a DB9 connector, for connecting the 120Ω clock interface board of the
MSE 5010. Table 3-4 shows the pin assignments of the DB9 connector.
Table 3-4 Pin assignments of the DB9 connector for 120Ω clock cable
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3.8.1 Structure
Structure of the network cable is shown in Fig 3-11
Both ends of the network cable are terminated with RJ-45 connectors, for connecting the NM computer and the
MSE 5010 NM interface.
Fig 3-12 shows the RJ-45 connector.
PIN #8
PIN #1
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1 White/orange 1
2 Orange 2
3 White/green 3
4 Blue 4
5 White/blue 5
6 Green 6
7 White/brown 7
8 Brown 8
Table 3-5 Pin assignments of the X1 connector for straight through cable
2 Orange 6
3 White/ green 1
4 Blue 4
5 White/ blue 5
6 Green 2
7 White/ brown 7
8 Brown 8
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Connector RJ-45
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3.9.1 Structure
The structure of the Boolean input/output cable is shown in Fig 3-13
Twisted pair-120Ω-SEYVPV-0mm-24AWG-8
Model
cores-PANTONE 430U
Core number 8
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3.10.1 Structure
The structure of the OAM serial port cable is shown in Fig 3-14
1. Network port connector - RJ-45 2. Main tag 3. Cable connector - DB25 - male
Fig 3-14 OAM serial port cable
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X1.4
X2.7 pair GND
X1.5
Model
Twisted pair-120Ω-SEYVPV-0mm-24AWG-8 cores-
PANTONE 430U
Length 5000mm
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3.11.1.1 Structure
The structure of the S1 ~ S4/F&f cable is shown in Fig 3-15
1. Network port connector - RJ-45 2. Main tag 3. Cable connector - DB9 male
Fig 3-15 S1~S4/F&f cable
Model
Twisted pair-120Ω-SEYVPV-0mm-24AWG-8 cores-
PANTONE 430U
Length 15m
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3.12 Fiber
3.12.1 Structure
Structure of the fiber is shown in Fig 3-16
Connector LC/PC
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Status Description
On, green The board works normally.
Status Description
On, green The service is activated, and the board is in service.
Specifically, the board is in working status and the service is
active in EPS mode; and the indicator is normally on in the case
of no EPS provided.
Off The service is not activated, and the board can be swapped.
Status Description
On, green Upload of board software to FLASH or the FPGA
upload is normal, or the board software initialization is
normal.
On for 300ms and The board software is initializing, and is in BIOS boot
off for 300ms stage.
alternatively, green
Status Description
On, green Service is normal, no service alarm occurs.
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The flashing
The green indicator is on, The Ethernet cable is frequency of yellow
and the yellow indicator connected, and data is indicator depends on
flashes. transmitted. the transmission of
Ethernet data.
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PQ1 19 1.010
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FE Fast Ethernet
GE Gigabit Ethernet
IP Internet Protocol
L2 Layer 2
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NE Network Element
NM Network Management
P Provider
PE Provider Edge
TM Terminal Multiplexer
VC Virtual Container
VP Virtual Path
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