MODULE 1

Introduction to MTS-86C Microprocessor Training System

MODULE OUTLINE:
• Objectives
• Introduction to Microprocessor Systems
• Microprocessor Architecture (Sample)
• 8086 General Operation
• Introduction to MTS-86C
• Executing Demo Programs
Prepared By:
Engr. Cristine Jin DS. Estrada
 MODULE 1
Objectives
PRE-LAB DISCUSSION
• To give an overview of the microprocessor systems, its components and
architecture
• To introduce the general operation of the 8086 processor

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INTRODUCTION
Three Main Components of a
Basic Computer Organization

A. CPU or Microprocessor – performs

many operations and controls the
computer.

B. Memory Subsystem – used to store

programs being executed by the CPU,
along with the program’s data.

C. Input/Output Subsystem – allows

the CPU to interact with input and output
devices, such as the keyboard and GENERIC COMPUTER ORGANIZATION
monitor.
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INTRODUCTION
What is a System Bus?
A System Bus is a set of wires or a
physical group of signal lines that has a
related function within a microprocessor
system.
It is used to send information from one
component into another.
How is the system bus classified?
A. Address Bus – a unidirectional bus used to locate a
memory location or an I/O device connected to the
system.
B. Control Bus – a bus (collection of individual control
signals) used by the microprocessor to send its
generated control signals to any element of the
computer system
C. Data Bus – a bidirectional bus that carries data back GENERIC COMPUTER ORGANIZATION
and forth to a specified location with basis to the
address location provided by the address bus.
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INTRODUCTION
What is a Microprocessor?
A Microprocessor is considered to be the
Central Processing Unit (CPU) or the
brain of all computers and electronic
devices. It acts as a complete computation
engine that is fabricated on a single chip.

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MICROPROCESSOR ARCHITECTURE
BASIC MICROPROCESSOR
STRUCTURE ACCUMULATOR

A. Bus Unit – has the job of PROGRAM

establishing communication with COUNTER
the external unit ALU
MEMORY
B. Arithmetic Logic Unit (ALU) – GENERAL PURPOSE
STATUS
REGISTER ADDRESS
performs data processing REGISTER REGISTER
operations specified during the
execution phase of the
instruction being interpreted
INSTRUCTION
C. Control Unit – generates the REGISTER
set of timings and control signals MEMORY
DATA
necessary to activate different CONTROL REGISTER
parts of the circuit UNIT
D. Register Set – set of data
holding places
MICROPROCESSOR BLOCK DIAGRAM
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MICROPROCESSOR ARCHITECTURE
A. Bus Unit
Data Bus
• A bidirectional bus that
carries data back and forth to
a specified location with basis
to the address location
provided by the address bus.

NOTE:
The width of a data bus refers to the
number of bits (electrical wires) that
make up a bus.
e.g. 1-, 4-, 8-, 16-, 32-, and 64-bit BASIC STRUCTURE OF MICROPROCESSOR
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MICROPROCESSOR ARCHITECTURE
A. Bus Unit
Address Bus
• It is a group of wires or lines that
are used to transfer the addresses
of Memory or I/O devices. It is
bidirectional.

NOTE:
A 16-bit address bus can transfer
maximum address which means it can
address 65,536 different memory
locations.

The number of bits of address bus

determines the maximum size of memory
which the processor can access.
BASIC STRUCTURE OF MICROPROCESSOR
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Structure of Data LITTLE ENDIAN vs. BIG ENDIAN
Storage What is the difference between
• For multiple byte data these two storage structures?
items to be stored in the
memory, there is a need
to know how the order addr4 Byte 4
• LITTLE ENDIAN – the least
is done. significant 8 bits (byte) are to be
addr3 Byte 3
• Otherwise, problem may addr2 Byte 2
stored in a lower address.
occur when transferring addr1 Byte 1
data between machines.
• The order of storage of • BIG ENDIAN – the most addr4 Byte 1
data can be classified
into two: the Little
significant 8 bits (byte) are to be addr3 Byte 2

Endian and Big Endian stored in a lower address. addr2 Byte 3

addr1 Byte 4
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MICROPROCESSOR ARCHITECTURE
B. Arithmetic Logic Unit (ALU)
• It contains the microprocessor’s data
processing major logic.
• Performs arithmetic and logic
operations. ALU
• Composed of adders/subtracters,
comparators, and different
combinational circuits.

NOTE:
Example of arithmetic operations are:
1. addition/subtraction
2. increment/decrement
3. shift left/right, circular shift left/right

Example of logic operations are: AND, OR,

XOR, and NOT.
MICROPROCESSOR BLOCK DIAGRAM
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MICROPROCESSOR ARCHITECTURE
C. Control Unit
• Made up of instruction decoder,
timing circuits, and control logic
1. Instruction Decoder – the circuit
responsible for synthesizing and
decoding the instructions fed or
received by the microprocessor.
2. Timing Circuits – used to
synchronize the operation of the
different parts of the
microprocessor.
3. Control Logic – send the control CONTROL
signals flowing in the control bus UNIT
to enable the different parts of the
microprocessor unit. MICROPROCESSOR BLOCK DIAGRAM
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MICROPROCESSOR ARCHITECTURE
D. Register Set
• In the given structure, the ACCUMULATOR

register set is composed of PROGRAM

the following: COUNTER
1. General Purpose STATUS MEMORY
ADDRESS
Registers A and B GENERAL PURPOSE REGISTER
REGISTER REGISTER

2. Accumulator
3. Status Register
INSTRUCTION
4. Instruction Register REGISTER
MEMORY
5. Program Counter DATA
REGISTER
6. Memory Data Register
7. Memory Address Register
MICROPROCESSOR BLOCK DIAGRAM
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MICROPROCESSOR ARCHITECTURE
D. Register Set
2. Accumulator ACCUMULATOR

• The register that works very

closely with the ALU.
• All results of the processes
performed by the ALU is
stored in this register.
• This is the major register that
holds data for manipulation.
• It is considered as the most
versatile register because its
content always changes. MICROPROCESSOR BLOCK DIAGRAM
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MICROPROCESSOR ARCHITECTURE
D. Register Set
1. General Purpose
Registers (A and B)
• They are generally used as
data storage and are
GENERAL PURPOSE
REGISTER

directly connected to the

data bus.
NOTE:
The more the number of GPR,
the more powerful the
microprocessor is. MICROPROCESSOR BLOCK DIAGRAM
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MICROPROCESSOR ARCHITECTURE
D. Register Set
3. Status Register
• It is sometimes referred to as Flag
Register, Condition Code
Register, or the Indicator
Register.
• It is used to hold the status of the STATUS
REGISTER
microprocessor after performing an
operation.
Commonly Used Flags:
 CARRY – end carry of the parallel adder.
 ZERO – if the result of the ALU are all
zero
 SIGN – if the MSB in a signed operation
has a value of 1
 OVERFLOW – if the result of ALU
operation exceeds the defined range of
numbers
 PARITY – used for error detection MICROPROCESSOR BLOCK DIAGRAM
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D. Register Set
4. Instruction Register
• It is used to hold the
instruction code or
operation code (opcode).

NOTE: INSTRUCTION
REGISTER
The outputs of this register
are the inputs to the
instruction decoder.
MICROPROCESSOR BLOCK DIAGRAM
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D. Register Set
5. Program Counter
PROGRAM
• It contains the address of COUNTER
the next instruction to be
performed by the MPU.
• It automatically increments
as soon as it is finished
with the memory location.

MICROPROCESSOR BLOCK DIAGRAM

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MICROPROCESSOR ARCHITECTURE
D. Register Set
6. Memory Data Register
• This is where the data to be
stored to or retrieved from the
memory are placed.
MEMORY
• This register also loads the ADDRESS

fetched instruction from the REGISTER

memory going to instruction

register.

7. Memory Address Register MEMORY

DATA
• This is where the addresses REGISTER

of data and instructions can

be located.
MICROPROCESSOR BLOCK DIAGRAM
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MTS-86C
HARDWARE OVERVIEW
MTS-86C is an Intel 8086 based

MPU Chip Sets

microprocessor training system
designed for teaching purposes.
Memory
8086 I/Os
It is composed of 5 parts:

• MPU (8086)

External Interface
• Memory
• Chip Sets
• I/Os
MTS-86C FUNCTION BLOCKS
• External Interface
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MTS-86C
HARDWARE OVERVIEW
MPU
The MPU of the MTS-86C is an
MPU Chip Sets
Memory
Intel based 8086 microprocessor

8086 I/Os
which has the following elements:

 16-bit internal data bus



20-bit address bus
Control bus External Interface
 Execution Unit
 Bus Interface Unit MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
MEMORY
 ROM (Read Only Memory)

MPU Chip Sets

The memory has two 27,256 UV
EPROM (32Kb x 8), serving as the
storage of demo programs and
system monitoring program.
Memory
 RAM (Random Access Memory)
The memory also has two 62,256
SRAM (32Kb x 8), serving as the
8086 I/Os
storage of user programs/data and
interrupt vector table.

 USER MEMORY
External Interface
The user memory allows the user to
store programs in their own ROM or MTS-86C FUNCTION BLOCKS
RAM. (Optional)
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MTS-86C
HARDWARE OVERVIEW
CHIP SETS
 8255 – General purpose
programmable parallel
input/output interface (3 sets) MPU Chip Sets
Memory
 8251 – Serial data
communications interface (2
sets)
8086 I/Os
 8259 – Programmable Interrupt
Control Unit
External Interface
 8253 – Programmable MTS-86C FUNCTION BLOCKS
timer/counter
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MTS-86C
HARDWARE OVERVIEW
CHIP SETS

MPU
 8279 – Programmable
keypad/display interface Chip Sets
Memory
8086 I/Os
 74LS373 – Octal D-Type
latches

External Interface
 DAC0808 – 8-bit multiplying
digital to analog converter

 ADC0809 – 8 channels 8-bit

analog to digital converter MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
I/Os

MPU
 Switch – 8-bit logic TACT
switch Chip Sets
 LED – 8-BIT logic LED
Memory
8086 I/Os
 FND – 1 Flexible Numeric
Display
 Keypad – 4x6 keys

External Interface
 Display – 16x2 line LCD
 Speaker – 2 W Speaker
 ADC Input – microphone,
variable resistor, thermistor,
and phototransistor MTS-86C FUNCTION BLOCKS

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MTS-86C
HARDWARE OVERVIEW
External Interface
 PPI-1 – 1st Prototyping area for

MPU Chip Sets

8225 parallel port
 PPI-2 – 2nd Prototyping area for

Memory
8225 parallel port

8086 I/Os
 PIT/PIC/AD/DA – External
interface for 8259, AD/DA
Converter, and 8253,
respectively
 System Bus – connects to 8086
CPU
 RS232-1 – First serial port
interface for 8251
External Interface
 RS232-2 – Second serial port
interface for 8251 MTS-86C FUNCTION BLOCKS

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MTS-86C
FFFFFH
MEMORY MAP F8000H
Monitor Program 64KB EPROM
System Memory
• Monitor Program – allows user to Demo Program 27256 x 2
control and examine the F0000H

microprocessor from the keyboard User Memory ROM, RAM

E0000H (Optional)
• Demo Program – stores demo
Non-Use OPEN
programs 10000H

• User Memory – allows user to Program and Data 64KB SRAM

Program Memory
store/load programs in their own 00400H
62256 x 2
ROM or RAM (Optional)
Interrupt Vector Table
• Program and Data – user codes 00000H

and data are stored in this section

• Interrupt Vector Table – reserved MTS-86C MEMORY MAP
location for interrupt vector table
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MTS-86C
ADDRESSING MODE PHYSICAL vs. LOGICAL ADDRESS
Recall the elements of the What is the difference between these two
8086 processor: address?
The MPU of the MTS-86C is an Intel
based 8086 microprocessor which • LOGICAL ADDRESS – address generated
has the following elements:
by the CPU and can be also referred to as
virtual address.
 16-bit internal data bus
 20-bit address bus
 Control bus • PHYSICAL ADDRESS – address seen by
 Execution Unit the memory unit.
 Bus Interface Unit

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MTS-86C
ADDRESSING MODE Width = 16 bits
The physical address of the 8086 system is 20
bits in width. Hence, the generation of the
physical address requires the combination of
a 16-bit offset value and a 16-bit base value CODE SEGMENT (CS)
located in one of the four segment registers: DATA SEGMENT (DS)
• Code Segment (CS) – holds the program STACK SEGMENT (SS)
instruction codes
• Data Segment (DS) – stores data for the EXTRA SEGMENT (ES)
program
• Stack Segment (SS) – stores interrupt SEGMENT REGISTERS
subroutine return address
• Extra Segment (ES) – an extra data
segment often used for shared data
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How to generate a physical
address?
To generate a physical address, the value
in the segment register is shifted left by 4
bits with its
LSB filled with 0s

SEGMENT ADDRESS F 0 4 0 Width = 16 bits

0 0 0 0 Width = 16 bits
OFFSET ADDRESS

F 0 4 0 0 Width = 20 bits

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EXECUTING DEMO PROGRAMS
TABLE 4-1. DEMO PROGRAMS
EXPERIMENT
Fill out the remarks of
Table 4-1 Demo
Programs by exploring
MTS-86C.

OBJECTIVES
• To introduce the
hardware devices of
MTS-86C
• To introduce the memory
map of MTS-86C
• And to learn how to
execute the demo
programs in MTS-86C
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