1082 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO.

2, MARCH/APRIL 2014

Boost-Derived Hybrid Converter With

Simultaneous DC and AC Outputs
Olive Ray, Student Member, IEEE, and Santanu Mishra, Senior Member, IEEE

Abstract—This paper proposes a family of hybrid converter

topologies which can supply simultaneous dc and ac loads from
a single dc input. These topologies are realized by replacing
the controlled switch of single-switch boost converters with a
voltage-source-inverter bridge network. The resulting hybrid con-
verters require lesser number of switches to provide dc and ac
outputs with an increased reliability, resulting from its inherent
shoot-through protection in the inverter stage. Such multioutput
converters with better power processing density and reliability
can be well suited for systems with simultaneous dc and ac loads,
e.g., nanogrids in residential applications. The proposed converter,
studied in this paper, is called boost-derived hybrid converter
(BDHC) as it is obtained from the conventional boost topology. The
steady-state behavior of the BDHC has been studied in this paper,
and it is compared with conventional designs. A suitable pulse Fig. 1. Representative schematic of a nanogrid architecture with a single dc
width modulation (PWM) control strategy, based upon unipolar input and simultaneous dc and ac outputs. (a) Dedicated power converter-based
sine-PWM, is described. A DSP-based feedback controller is de- architecture. (b) Hybrid converter-based architecture.
signed to regulate the dc as well as ac outputs. A 600-W laboratory
prototype is used to validate the operation of the converter. The converter stage to perform both the conversions. The latter con-
proposed converter is able to supply dc and ac loads at 100 V and verter, referred to as a hybrid converter in this paper, has higher
110 V (rms), respectively, from a 48-V dc input. The performance power processing density and improved reliability (resulting
of the converter is demonstrated with inductive and nonlinear
loads. The converter exhibits superior cross-regulation properties from the inherent shoot-through protection capability). These
to dynamic load-change events. The proposed concept has been qualities make them suitable for use in compact systems with
extended to quadratic boost converters to achieve higher gains. both dc and ac loads. For example, an application of a hybrid
Index Terms—Boost-derived hybrid converter (BDHC), dc converter can be to power an ac fan and a LED lamp both at the
nanogrid, pulsewidth-modulated inverters. same time from a solitary dc input in a single stage.
Smart residential systems are often connected to nonconven-
I. I NTRODUCTION tional energy sources to provide cleaner energy. Due to space
constraints, these dedicated energy sources are highly localized

N ANOGRID architectures are being increasingly incorpo-

rated in modern smart residential electrical power systems
[1]. These systems involve different load types—dc as well as
and have low terminal voltage and power ratings (typically, on
the order of a hundred watts). Conventional designs involve
two separate converters, a dc–dc converter (e.g., boost) and a
ac—efficiently interfaced with different kinds of energy sources voltage source inverter (VSI), connected either in parallel [as
(conventional or nonconventional) using power electronic con- shown in Fig. 2(a)] or in cascade [Fig. 2(b)], supplying dc and
verters [2]. Fig. 1 shows the schematic of a system, where a ac outputs at vdcout and vacout , respectively. Depending upon
single dc source (vdcin ) (e.g., solar panel, battery, fuel cell, etc.) the requirements, topologies providing higher gains may be re-
supplies both dc (vdcout ) and ac (vacout ) loads. The architecture quired to achieve step-up operation [3]. This paper investigates
of Fig. 1(a) uses separate power converters for each conversion the use of single boost-stage architecture to supply hybrid loads.
type (dc–dc and dc–ac) while Fig. 1(b) utilizes a single power The operation of conventional VSIs in hybrid converters
would involve the use of deadtime circuitry to prevent shoot-
Manuscript received December 11, 2012; revised April 13, 2013; accepted through. In addition, due to electromagnetic interference (EMI)
May 8, 2013. Date of publication July 3, 2013; date of current version or other spurious noise, misgating turn-on of the inverter leg
March 17, 2014. Paper 2012-IPCC-719.R1, presented at the 2012 IEEE Energy switches may take place, resulting in damage to the switches. In
Conversion Congress and Exposition, Raleigh, NC, USA, September 15–20,
and approved for publication in the IEEE T RANSACTIONS ON I NDUSTRY A P - residential applications, due to the compactness of the overall
PLICATIONS by the Industrial Power Converter Committee of the IEEE Industry conversion system, the generation of spurious noise may be
Applications Society. This work was supported by the Department of Science commonplace. Thus, the VSIs in such applications need to be
and Technology, Government of India, under Grant SR/S3/EECE/0187/2012.
The authors are with the Department of Electrical Engineering, Indian In- highly reliable with appropriate measures against EMI-induced
stitute of Technology Kanpur, Kanpur 208 016, India (e-mail: olive@iitk.ac.in; misgating.
santanum@iitk.ac.in). The Z-source inverter (ZSI), proposed in [4], can mitigate the
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. problem of shoot-through due to the EMI in a VSI. The use of
Digital Object Identifier 10.1109/TIA.2013.2271874 a unique impedance network at the input of the ZSI allows a
0093-9994 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
RAY AND MISHRA: BOOST-DERIVED HYBRID CONVERTER WITH SIMULTANEOUS DC AND AC OUTPUTS 1083

Fig. 3. (a) Conventional boost converter. (b) Proposed BDHC obtained by

replacing Sa with a single-phase bridge network. The switch realization for the
Fig. 2. Schematic of power converter topologies with simultaneous dc and ac bridge can be done using bidirectional switches—either IGBTs with antiparallel
loads. A conventional boost converter and a VSI have been used to implement diodes or MOSFETs.
the system. System (a) when both are connected in parallel and (b) when
connected in cascade. by a comparative study of the BDHC in Section V. Section VI
extends the circuit modification principle to higher order boost
shoot-through state in which both the switches of an inverter converters. The converter and its control strategy have been
leg can be turned on simultaneously. Extended boost ZSI has validated using an experimental prototype in Section VII.
been proposed where a higher gain is achieved utilizing this
Z-source topology [5]. However, ZSI cannot supply both dc and II. BDHC
ac loads simultaneously. This is due to the fact that it has two
capacitors which have to be matched with equal loads across A. Proposed Circuit Modification
them. Unmatched loads on the capacitors might lead to dynamic Boost converters comprise complementary switch pairs, one
instability [6]. of which is the control switch (controls the duty cycle) and the
The switched boost inverter (SBI), proposed in [7], is a hy- other capable of being implemented using a diode. Hybrid con-
brid converter topology, which can achieve similar advantages verter topologies can be synthesized by replacing the controlled
as a ZSI with lesser number of passive components and supply switch with an inverter bridge network, either a single-phase or
simultaneous dc and ac loads. This inverse Watkins–Johnson three-phase one. The proposed circuit modification principle,
(IWJ) converter-derived topology [8] is a converter based upon applied to a boost converter, is illustrated in the next section.
the first-order four-switch converter cell [9]. The proposed The resulting converter, called BDHC, is the prime focus area
hybrid converter is derived from a two-switch converter cell- of this paper. Section VI extends this principle to higher order
based step-up converter, such as the boost converter. There- converters.
fore, it involves lesser component count compared to the IWJ
converter. The proposed converter is denoted as boost-derived
B. Derivation of BDHC Topology
hybrid converter (BDHC).
The objectives of this paper are the following: 1) to introduce The control switch Sa of a conventional boost converter
a family of hybrid converter topologies capable of simultane- [shown in Fig. 3(a)] has been replaced by the bidirectional
ously supplying ac and dc loads; 2) to characterize the steady- single-phase bridge network switches (Q1 –Q4 ) to obtain the
state behavior of the BDHC topology; 3) to develop a PWM BDHC topology [shown in Fig. 3(b)]. This proposed converter
control scheme for the BDHC; 4) to compare the performance provides simultaneous ac output (vacout ) in addition to the dc
of the BDHC with conventional designs; 5) to validate the static output (vdcout ) provided by the boost converter.
and dynamic performance of the BDHC using an experimental For the BDHC, the hybrid (dc as well as ac) outputs have
prototype; and 6) to extend the proposed philosophy to higher to be controlled using the same set of four controlled switches
order boost converters in order to achieve a higher conversion Q1 –Q4 . Thus, the challenges involved in the operation of
ratio. BDHC are the following: 1) defining the duty cycle (Dst ) for
This paper is organized as follows. The proposed circuit boost operation and the modulation index (Ma ) for inverter
modification principle is described next in Section II, and its operation; 2) determination of voltage stresses and currents
application to a boost converter is shown. The steady-state char- through different circuit components and their design; and
acterization of the converter is given in Section III. The PWM 3) control and channelization of total input power to both ac
control strategy and the closed-loop implementation to regulate and dc loads. In the subsequent sections, all the aforementioned
both ac and dc outputs are described in Section IV, followed challenges will be discussed.
1084 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014

III. O PERATION OF BDHC

The schematic of the BDHC with the reference current direc-
tions has been shown in Fig. 3(b). In this paper, the continuous
conduction mode of operation has been assumed (the boost
inductor current (iL ) never goes to zero). In this paper, lower
case letters represent instantaneous values, upper case letters
represent dc or rms values, lower case letters with tilde (∼ ) rep-
resent the ac component, and lower case letters with () repre-
sent the peak value of the variable.

A. Operating Principle
Each of the four bidirectional switches (Q1 –Q4 ) of BDHC
comprises the combination of a switch Si and an antiparallel
diode Di (i = 1 to 4). The boost operation of the proposed
converter can be realized by turning on both switches of any
particular leg (either S1 –S4 or S3 –S2 ) simultaneously. This is
equivalent to shoot-through switching condition as far as VSI
operation is concerned, and it is strictly forbidden in the case
of a conventional VSI. However, for the proposed modification,
this operation is equivalent to the switching “on” of the switch
“Sa ” of the conventional boost converter [see Fig. 3(a)].
The ac output of the BDHC is controlled using a modified Fig. 4. Switch node voltage (vsn ), inductor current (iL ), inverter output
version of unipolar sine-PWM switching scheme, described in voltage (vab ), diode current (iD ), and inverter input current (isn ) for a positive
Section IV. The BDHC, during inverter operation, has the same inverter output current. The reference directions for the voltages and currents
have been shown in Fig. 3(b). The figure shows that the inductor current has
circuit states as a conventional VSI. The reason for this is as a low-frequency component (at twice the power frequency) as described in
follows: For conventional VSIs (shown in Fig. 2), although the Section III.
input to the bridge is a voltage stiff dc bus, the input dc voltage
is required only during the power intervals, i.e., when there is a voltage drop). In this interval, either Q1 –Q2 or Q3 –Q4 is
power transfer with the source. In the other intervals, the current turned on.
freewheels among the inverter switches and these states do not 3) Interval III—Zero interval: The zero interval occurs when
require the input to be at a fixed dc value and hence can be zero. the inverter current circulates among the bridge network
In the BDHC, the switch node voltage (vsn ) acts as the input to switches and is not sourced or sunk. The diode “D” con-
the inverter; it switches between the voltage levels—vdcout and ducts during this interval. Fig. 5(c) shows the equivalent
zero. The switching scheme should ensure that the interval for circuit for this interval.
power transfer with the source occurs only when vsn is positive,
i.e., when vsn is clamped to the dc output voltage vdcout . Fig. 4 Table I shows the expressions for diode current (iD ), ca-
illustrates this concept. pacitor current (iC ), inverter output voltage (vab ), and boost
The BDHC has three distinct switching intervals as described switch node voltage (vsn ) for different operating modes. All
in the following. these expressions have been defined in Fig. 3(b).

1) Interval I—Shoot-through interval: The equivalent circuit B. Steady-State Analysis

schematic of the BDHC during the shoot-through interval
is shown in Fig. 5(a). The shoot-through interval occurs 1) Gain Expression for DC and AC Outputs: Similar to
when both the switches (either Q1 –Q4 or Q3 –Q2 ) of any conventional boost converters, the dc output of the BDHC can
particular leg are turned on at the same time. The duration be regulated using the duty cycle, denoted by Dst , and is defined
of the shoot-through interval decides the boost converter as the shoot-through time interval in a switching cycle, as
duty cycle (Dst ). The diode “D” is reverse biased during shown in Fig. 4. For the purpose of analysis, we assume that the
this period. The inverter output current circulates within output dc capacitor voltage and the input inductor current have
the bridge network switches. Thus, BDHC allows ad- small ripple compared to their dc values. Hence, the expression
ditional switching states which are strictly forbidden in for the voltage gain of the dc output is similar to that of a boost
a VSI. converter and can be derived as
2) Interval II—Power interval: The power interval, shown in Vdcout 1
Fig. 5(b), occurs when the inverter current enters or leaves = . (1)
Vdcin 1 − Dst
the bridge network at the switch node “s.” The diode “D”
conducts during this period, and the voltage at the switch The modulation index, denoted by Ma (0 ≤ Ma ≤ 1), regulates
node (vsn ) is equal to the vdcout (neglecting the diode the ac output voltage of the BDHC, and its definition is similar
RAY AND MISHRA: BOOST-DERIVED HYBRID CONVERTER WITH SIMULTANEOUS DC AND AC OUTPUTS 1085

The ac gain increases with the increase of modulation index

(Ma ) for any fixed value of duty cycle Dst . As the same set of
switches controls both the dc and ac outputs, there is limitation
to the maximum duty cycle or modulation index that can be
achieved for this topology. The switching strategy must satisfy
the following constraint:

Ma + Dst ≤ 1. (3)

Hence, the maximum value of ac gain is achieved at the equality

condition of relation (3). At this condition, the peak value of the
ac voltage is equal to the input voltage, and this is independent
of the values of the duty cycle and modulation index. This can
be obtained using (2) and (3). In order to achieve an ac voltage
with voltage levels higher than the input voltage, either a step-
up transformer needs to be interfaced to the BDHC or a higher
order boost converter needs to be used, as will be explained in
Section VI.
2) DC and AC Output Power Expressions: From (1) and (2),
the expressions for output dc (Pdc ) as well as ac power (Pac )
can be derived as follows:
2
Vdcin
Pdc = (4)
Rdc ∗ (1 − Dst )2

0.5 ∗ Vdcin
2
∗ Ma2
Pac = . (5)
Rac ∗ (1 − Dst )2

Rdc and Rac are the dc and ac output resistances, respectively.

Expressions (4) and (5) show that dc output power depends only
on duty cycle (Dst ), while ac output power depends upon both
Dst and Ma .
3) Design of Passive Components: The ac output wave-
forms of the BDHC are similar to those of a conventional VSI.
Therefore, the filter design principles associated with the design
of conventional VSIs can be used for Lac (= Lac1 + Lac2 )
Fig. 5. Equivalent circuits and current directions of the BDHC during
(a) shoot-through interval, (b) power interval, and (c) zero intervals. and Cac [see Fig. 3(b)]. As far as the dc–dc converter filters
are concerned, the selection of inductor (L) and capacitor (C)
TABLE I
S TEADY-S TATE E XPRESSIONS OF BDHC IN D IFFERENT M ODES OF
values depends mainly on the amount of allowable ripple in
O PERATION [R EFERENCE D IRECTIONS S HOWN IN F IG. 3(b)] the inductor current and capacitor voltage. One of the major
differences between the BDHC and a conventional boost con-
verter is that, in case of BDHC, since both dc and ac outputs
are achieved, the inductor current (iL ) and the capacitor voltage
(vdcout ) have both a high- and a low-frequency component (at
twice the output ac power frequency), in addition to their dc
values.
The ripple content due to the low-frequency component can
be evaluated as follows. The instantaneous power input into
the bridge network consists of a dc value (equal to Pac ) and
sinusoidal component varying at twice the power frequency.
In conventional VSIs, a dc-link capacitor is often used at the
to that associated with conventional VSIs. The peak output ac input, and this maintains the instantaneous power balance. This
voltage is related to the input as results in ripple content at the dc-link voltage at twice the
v̂acout Ma power frequency. For the proposed converter, this instantaneous
= . (2) power balance is maintained by both the reactive elements
Vdcin 1 − Dst
(capacitor C and inductor L). Neglecting switching frequency
The maximum dc output gain achieved using the BDHC is components, the equations related to the instantaneous power
similar to that of boost converters and is around four to five [15]. balance can be written as follows.
1086 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014

Let 4) Switch Stress and Current Expressions: The switches

Q1 –Q4 and Q3 –Q2 are complementary in operation except dur-
vab = van − vbn = v̂ab sin(ωt),
ing the shoot-through interval. The input to the inverter bridge
iab = îab sin(ωt − ϕ)
equals to vdcout (shown in Fig. 4) during both power and zero
where ϕ is the phase difference between the fundamental intervals. Thus, the maximum stress on each switch is equal
components of inverter output voltage (vab ) and current (iab ). to vdcout , the dc output voltage, neglecting the voltage drop
Therefore, the instantaneous inverter input power across the conducting diode D. The stress across the diode D
is equal to vdcout during the shoot-through interval. Thus, the
pab = vab iab selection of switch ratings is dependent upon the dc output
= 0.5 v̂ab îab cos ϕ − 0.5 v̂ab îab cos(2ωt − ϕ). (6) voltage rather than the input voltage, contrary to the case for
a conventional VSI.
The above expression has a dc as well as a sinusoidal compo-
As opposed to a conventional boost converter, the diode
nent. The dc component is equal to the real power demanded
current (iD ) of BDHC is dependent upon the boost inductor
by the ac output (Pac ). Thus, the average input current of the
current as well as the current drawn by the VSI bridge legs. This
inductor (L) can be calculated as shown in
is due to the fact that, apart from the shoot-through interval,
Pdc + Pac Vdcout Idcout + 0.5 v̂ab îab cos ϕ which is similar to the boost interval of a boost converter,
IL = = . (7)
Vdcin Vdcin there is an additional power interval. The current isn [shown
in Fig. 3(b)] is equal to iL during the shoot-through interval.
The sinusoidal component of instantaneous power pab is bal-
During the power interval, isn equals the inverter output current
anced by the variation of the inductor current and the capacitor
iab . Since iab is time varying, the value of isn and, hence, diode
voltage. This results in a low-frequency ripple (at twice the
current iD vary with time. This is shown in Fig. 4.
power frequency) in the inductor current as well as the capacitor
The expressions for the currents in different intervals are
voltage. This power balance equation is shown in
shown in Table I and in the Appendix (see Tables VI–VIII). The
 
d 12 Li2L (t) + 12 Cvdcout
2
(t) maximum current through the switches îsw can be expressed as
p̃ab = = 0.5 v̂ab îab cos(2ωt − ϕ) follows:
dt
(8)
îsw(i) = iL,max + |îab |, (i = 1 to 4). (11)
where p̃ab is the double frequency power component of input
power to the inverter bridge. The solution of (8) relates the max- |îab | represents the maximum value of the inverter output cur-
imum (iL,max , vdcout,max ) and minimum (iL,min , vdcout,min ) rent iab (t). Fig. 4 shows the nature of the switch node voltage
values of iL (t) and vdcout (t), as shown in (vsn ), inductor current (iL ), diode current (iD ), and inverter
1 2  1  2  p̃ab bridge input current (isn ) for a positive value of ac output
L iL,max − i2L,min + C vdcout,max − vdcout,min
2
= . current (iab ).
2 2 ω
(9)
Equation (9) can be simplified to obtain the following design IV. C ONTROL S TRATEGY
criterion:
A. Modified Unipolar PWM Strategy for BDHC

P ab
L.IL .ΔiL,pk−pk + C.Vdcout .Δvdcout,pk−pk = (10) The fundamental principle behind the operation of BDHC
ω is based upon the fact that the inverter bridge input must be
where ΔiL,pk−pk and Δvdcout,pk−pk represent the peak-to- connected to a positive voltage during the power interval only.
peak ripple contents in iL (t) and vdcout (t), respectively. This means that the inverter output has to be modulated when
Thus, from (10), it can be concluded that, with the increase vsn = 0 and boost operation occurs when vab = 0. The inverter
in ac output power, the ripple content (at twice the fundamen- output voltage assumes three different values, and hence, the
tal frequency) in both the inductor current iL and dc output PWM modulation strategy used is based upon unipolar sine-
capacitor voltage vdcout changes. Depending upon the active PWM scheme, which provides three voltage levels for output.
power level, the magnitude of this power frequency component The PWM control scheme for the BDHC is based upon the
can be greater than the ripple due to high frequency. The switching scheme proposed in [10]. In this scheme, shown
high-frequency ripple content has been illustrated in Fig. 4, in Fig. 6(a), the shoot-through is realized by gating-on both
where the inductor current does not reach its initial value after the switches of a single leg at the same time. The switching
each switching interval due to the presence of the sinusoidal strategy involves turning on only one leg at a time in order
component in capacitor voltage. This, in turn, results in a sinu- to achieve shoot-through. Another alternative is to turn on
soidal ripple in the inductor current at twice the fundamental all the switches during shoot-through. This scheme has been
frequency. This low-frequency ripple content should hence be proposed in [11] and [12], and the concept is illustrated using
considered during the component design. Fig. 6(b). As shown in the figure, turning on all the switches for
For the BDHC, the inductor current is drawn from a dc shoot-through involves more switching during each switching
source, and hence, the ripple content in the input current should period with their associated losses. The reliability of the circuit
be as low as possible. If the ripple in inductor current is fixed, also reduces since the time between two successive switching
the ripple in dc output can be calculated from (10). [switches S1 and S2 in Fig. 6(b)] is dependent on tz , which
RAY AND MISHRA: BOOST-DERIVED HYBRID CONVERTER WITH SIMULTANEOUS DC AND AC OUTPUTS 1087

Fig. 7. Implementation of the PWM scheme shown in Fig. 6(a).

Fig. 6. Generation of gate signals for a positive value of reference signal

(vm (t)). (a) Proposed PWM scheme used and (b) its variant where all switches
are turned on during shoot-through. Here, ST is the shoot-through interval, and
Z is the zero interval.

can be close to zero. This may be impractical considering

minimum switching times for the devices used. Thus, compared
to Fig. 6(b), additional switching at S1 and S2 is absent in the
proposed scheme of Fig. 6(a), and this scheme has been used
for the control of the BDHC.

Fig. 8. Closed-loop control architecture for the BDHC.

B. Implementation and Control of BDHC
The PWM control scheme of Fig. 6(a) is realized using the C. Closed-Loop Control of BDHC
schematic shown in Fig. 7. The reference signals to the PWM
Fig. 8 shows the closed-loop control architecture of the
generation circuit are vm (t) and vST (t). The signals S1–S4 are BDHC. The control scheme for the ac output uses DQ-reference
provided to the gates of the controlled switches. vST (t), a dc
frame control [3], [13]. The control design for dc and ac out-
signal, controls the shoot-through period, and hence, the duty puts of conventional converters can be extended to the BDHC
ratio (Dst ) for the dc output of the boost converter and vm (t) control. The controller generates control signals (S1–S4),
controls the modulation index (Ma ) for the inverter. The nature
which form the actual gate signals (GS1 –GS4 ) of the BDHC
of the gate signals for a positive value of reference signal vm (t) switches. The dc (vdcout ) and the ac voltages (vacout ) are
has been shown in Fig. 6(a). regulated by the controller to their references vdcout ∗
and
The control parameters vm (t) and vST (t) are generated by ∗ ∗
(vd , vq ), respectively. The controller has been implemented
the control system and must satisfy relation (3). This switching using TMS320F28335 DSP. The built-in 12-b analog-to-digital
strategy constraint is taken care of by the controller by sat- converter has been used for the purpose of digitization of
isfying the constraint given by the relation (12), with respect
feedback variables. There are two separate control loops for dc
to Fig. 7 as well as ac voltages. When the dynamics of the dc output
|vST | ≥ vm . (12) control is faster than that of the ac controller, both the dc and ac
1088 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014

TABLE II
C OMPARISON B ETWEEN BDHC AND C ONVENTIONAL A RCHITECTURES

Fig. 9. Higher gain can be achieved by using QBDHC.

5) The current during the boost interval of the boost con-

verter alternates between the two legs of the inverter.
This enables the use of higher switching frequency for
the boost converter, thus reducing the magnetic size and
improving the dynamics of the system.
6) The converter can supply both ac and dc loads from a
single dc input supply. The converter can also be adapted
outputs can be regulated separately using the control variables to generate ac outputs at frequencies other than line
Dst and Ma , respectively. The ac voltage control uses a cascade frequencies by a suitable choice of the reference carrier
control system with an inner current loop and an outer voltage waveform.
loop. The superior cross-regulation behavior of the converter The major limitation for the BDHC is that the degree of
has been demonstrated in the experimental section. freedom is reduced when the relation (3) reaches equality
condition. Another limitation for the converter is that, compared
to the circuit of Fig. 2(b), the peak value of the ac output is
V. C OMPARATIVE A NALYSIS OF BDHC
less than the input voltage. However, for the ac output voltage
W ITH C ONVENTIONAL D ESIGNS
realized using the configuration shown in Fig. 2(a), in practical
The BDHC can generate simultaneous dc and ac outputs situations, the maximum modulation index is around 0.85,
from a single dc input. Conventional solutions used to realize which makes the maximum peak ac voltage to be 0.85 times the
dc as well as ac outputs involve separate boost converter as well input. A similar peak ac voltage can be achieved by the BDHC
as VSI [see Fig. 2(a)] or a boost cascaded VSI [see Fig. 2(b)]. using a lower modulation index by having a suitable value of
Table II shows a comparison between the three solutions. the duty ratio.
The proposed BDHC has the following advantages.
1) Inherent shoot-through protection. The problems associ- VI. H IGHER O RDER B OOST-BASED H YBRID T OPOLOGIES
ated with the misgating-on of the two complementary The maximum output-to-input gain achieved by the boost
switches of each inverter leg due to EMI or other spurious converter is limited to approximately four due to resistive losses
noise have been eliminated by the proposed topology. The [15]. Higher order boost converters with a single controllable
shoot-through condition does not cause problems in the switch have been described in [16]–[18], which achieve higher
operation of the circuit and hence improves the reliability gains compared to a boost converter. Fig. 9 shows the schematic
of the system. On the contrary, having a shoot-through is of the quadratic BDHC (QBDHC), which has been derived
necessary for boost converter cascaded VSI operation. from the single-switch controlled quadratic boost converter.
2) The implementation of deadtime is not essential for this Thus, in general, the family of nth-order boost converters with
topology. This improves the nature of the inverter output single switch can be modified to form the corresponding family
with respect to its harmonic content [14]. In traditional of hybrid boost converters.
PWM inverters, deadtime compensation circuitry may be
needed to compensate the distortion in output voltage due
VII. E XPERIMENTAL V ERIFICATION
to deadtime circuit.
3) The number of controllable switches is reduced when The behavior of hybrid converters, described in this paper,
compared to a boost cascaded inverter topology [see has been validated using a laboratory prototype. A 600-W
Fig. 2(b)]; both the VSI and boost converter are controlled IGBT-based laboratory prototype has been used to demonstrate
using the same bridge configuration, thus reducing con- the characteristics of the BDHC. For the purpose of designing
trol circuit. the passive components, the ripple contents (both high- and
4) In this topology, the duty ratio and modulation index of low-frequency components) in the inductor current and the
the dc and ac structure can be independently controlled. capacitor voltage have been taken to be 25% and 3%, respec-
In contrast to a ZSI or SBI [6], the maximum duty cycle tively, at the rated power. Based on the equations described
for dc–dc conversion is not limited to 0.5. Thus, when the in Section III, the components for the BDHC have been de-
BDHC is not used for dc–ac operation, the converter can signed. The controller of the prototype is implemented using
be solely used for boost operation. the TMS320F28335 DSP kit. The SKYPER 32 Pro floating gate
RAY AND MISHRA: BOOST-DERIVED HYBRID CONVERTER WITH SIMULTANEOUS DC AND AC OUTPUTS 1089

TABLE III
D ESIGN E XAMPLE S PECIFICATIONS OF THE BDHC
(O PEN -L OOP O PERATION )

TABLE IV
PARAMETERS OF THE BDHC P ROTOTYPE

Fig. 11. Experimental validation of the proposed PWM control.

Fig. 10. Photograph of the IGBT-based laboratory prototype of the BDHC.

TABLE V
C OMPONENT L IST

Fig. 12. Steady-state behavior of the BDHC in open loop. The converter
produces a dc output (vdcout ) as well as an ac output (vacout ) from an input
voltage (vdcin ) of 48 V dc (Ch. 1). (a) DC output of 75.4 V (Ch. 4) and ac
output of 30 V (rms) (Ch. 2) for Dst = 0.4 and Ma = 0.6. (b) DC output of 108 V
dc (Ch. 4) and ac output of 30 V (rms) (Ch. 2) for Dst = 0.6 and Ma = 0.4.
drivers drive the IGBTs. A complete list of parameters and com-
ponent values for the prototype is given in Tables III and IV.
Fig. 12(a) and (b) shows the steady-state open-loop behavior
Fig. 10 shows the photograph of the experimental setup.
of the BDHC. For an input voltage of 48 V dc, the output dc
Table V lists the components used for building the BDHC
voltages achieved are 75.4 V and 108 V dc for duty cycles of
prototype.
0.4 and 0.6, respectively. The ac output is 30 V (rms) for mod-
ulation indices of 0.6 and 0.4, respectively. From these results,
A. Steady-State Behavior of BDHC
it is validated that, when the equality condition of relation (3)
Fig. 11 shows the gate control signals for the BDHC switches is maintained, for any value of duty (Dst ), the magnitude of the
and the resulting switch node voltage (vsn ) (referring to ac output voltage is always 0.707 times the input voltage. Here,
Figs. 3(b) and 8). The control schematic described in Section IV the dc and ac loads are 30 and 9 Ω, respectively. Hence, the
has been used for the generation of the gate signals. The prototype serves 390-W dc and 110-W ac loads approximately.
waveforms validate that, whenever the switches S1 and S4 or S2 From (4) and (5), the ratio of dc power to ac power is equal to
and S3 are “on” at the same time, vsn = 0. This interval refers 2Rac /M2a .Rdc , i.e., 3.75 (for Dst = 0.6 and Ma = 0.4). Thus,
to shoot-through, and it controls the dc output. The ac output is the theoretically calculated power relationship closely matches
modulated using the reference signal vm (t). the experimentally observed values.
1090 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014

Fig. 13. Steady-state input current and ripple variation of the BDHC state
variables. The converter produces a dc output (vdcout ) of 105 V (Ch. 2) as well
as an ac output (vacout ) of 27 V (rms) (Ch. 4) for an input voltage (vdcin ) of 48
V dc (Ch. 1). The variation of input inductor current is shown for Dst = 0.6
and Ma = 0.4. (a) C = 1 mF, iL (Ch. 3) having average of 12 A. (b) C =
3 mF, iL (Ch. 3) having average of 12 A is compared with the input current
obtained in Fig. 13(a) (Ch. A).

Fig. 15. Comparison of (a) dc gains as well as (b) ac gains achieved using (i)
separate boost converter and a VSI, (ii) boost cascaded VSI, (iii) BDHC, (iv)
QBDHC, and (v) experimental prototype. The modulation index for cases (i)
and (ii) has been taken as 0.8. For the remaining cases, Ma = 1 − Dst .

The steady-state waveform of the input inductor current [iL

in Fig 13(a)] for an input voltage of 48 V dc with Dst = 0.6 and
Ma = 0.4 is shown in Fig. 13(a). Fig. 13(b) shows the compar-
ison of the current waveforms when the output capacitance is
changed from 1 mF [Ch. A of Fig. 13(b)] to 3 mF [Ch. 3 of
Fig. 13(b)]. It can be seen that the increase in capacitance has
an effect on the ripple content of both the output voltage and
the input inductor current, as described in relation (10).
Fig. 14 shows the switching waveforms of the BDHC. This
figure validates that the power interval occurs only when the
switch node (vsn ) is positive. The diode current is dependent
Fig. 14. Switching waveforms of BDHC. The figure shows the input voltage upon the input inductor current as well as the current into the
(vdcin ), switch node voltage (vsn ), diode current (iD ), and inverter output
(vab ) voltages. (a) vab > 0. (b) vab < 0. Here, Dst = 0.55, and Ma = 0.35. inverter bridge legs, as described in Table I. These results are
The input voltage is 48 V. the same as the waveforms shown in Fig. 4.
RAY AND MISHRA: BOOST-DERIVED HYBRID CONVERTER WITH SIMULTANEOUS DC AND AC OUTPUTS 1091

Fig. 16. Cross-regulation behavior of the BDHC when subjected to step change in loads (dc as well as ac). (a) 50% step-down in ac load. (b) 50% step-up in ac
load. (c) 50% step-up in dc load. (d) 50% step-down in dc load. The load values are (a and b) Rdc = 32.8 Ω with Rac changing between 8.3 and 20.8 Ω and
(c and d) Rac = 8.5 Ω with Rdc changing between 75 and 31.8 Ω.

B. Variation of Gain With Duty Cycle outputs can be controlled independently using the two control
parameters “Dst ” and “Ma ”, respectively, so long as relation
The dc as well as ac voltage gains of the experimental proto-
(3) is satisfied. The cross-regulation behavior of the converter
type have been plotted against the duty cycle (Dst ) and shown
has been shown in Fig. 16. These results show that both the dc
in Fig. 15(a) and (b). A 48-V dc input is used to obtain the
and ac outputs are well regulated, even during a step change in
experimental data points. In order to achieve the highest ac gain,
loads in either outputs.
the modulation index satisfies the equality condition of relation
The converter efficiency has been measured to be 86.12% for
(3). The results have been compared with theoretical gains of
a total output of 370 W (dc power of 334 W and ac power of
conventional architectures such as separate boost converter and
36 W) and 88.1% at the total output power of 564 W (dc power
VSI, boost cascaded VSI, BDHC, and QBDHC. For the purpose
of 492 W and ac power of 72 W).
of analysis, it has been assumed that the modulation index for
traditional VSI is 0.8, in order to achieve a practical value of
high ac output. Clearly, a boost cascaded VSI achieves a higher
ac conversion ratio compared to the proposed converter at the D. Operation With Step-Up Transformer
cost of reduced EMI immunity. However, for a higher ac or dc When the BDHC is operated from a 48-V input voltage, the
conversion ratio, a QBDHC can be used. ac output voltage needs to be stepped up by using a transformer
to achieve practical voltage levels. Experimental results have
been shown when a 1:5 step-up transformer is connected to the
C. Cross-Regulation of BDHC
ac output of the BDHC. The transformer output is shown as
The closed-loop schematic, described in Section IV, has been Nvacout in Fig. 17. The figure shows results when connected to
used to regulate both dc and ac outputs. The dc as well as the ac different ac loads at 110 V ac (rms) and 100 V dc.
1092 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014

Fig. 17. Transformer (1 : 5) coupled BDHC with 110-V ac loads. Response of the prototype to (a) resistive ac load of 110 Ω, (b) inductive load of 0.75 (lag)
power factor load, and (c) nonlinear load.

A PPENDIX
The expressions for the switch currents of BDHC in different
intervals are shown in Tables VI–VIII.
TABLE VI
S WITCH C URRENTS OF BDHC FOR THE S HOOT-T HROUGH I NTERVAL

TABLE VII
S WITCH C URRENTS OF BDHC FOR THE P OWER I NTERVAL
Fig. 18. QBDHC behavior for an input voltage of 48 V dc with D = 0.4 and
Ma = 0.5.

E. Verification of High-Gain Boost Extensions

Hybrid converters with higher gains can be achieved when
TABLE VIII
the proposed circuit modification principle is extended to higher
S WITCH C URRENT OF BDHC FOR THE Z ERO I NTERVAL
order converters. Fig. 18 shows that, when a QBDHC is used
instead of the BDHC, for an input voltage of 48 V dc, output
voltages of 94 V dc as well as 34 V ac (rms) have been obtained
for a duty cycle of 0.4 and a modulation index of 0.5.

VIII. C ONCLUSION
ACKNOWLEDGMENT
This paper has proposed hybrid power converter topologies
which can supply simultaneous dc and ac loads from a single The authors would like to thank R. Adda and K. Jha, Re-
dc input. The various advantages of using this single converter search Scholars in the Power Management Laboratory, Indian
stage like shoot-through protection have been described and Institute of Technology Kanpur, for assisting in the develop-
compared to traditional VSIs. It has been shown that a class ment of the prototype and for providing useful suggestions for
of converters can be achieved by describing the BDHC and the improvement of the manuscript. O. Ray would like to thank
QBDHC. Experimental results verify the operation of the the Department of Science and Technology, Government of
BDHC in an open loop. The cross-regulation behavior of the India, for providing travel support for presenting a part of this
converter has been studied along with its behavior to different work at the 2012 Energy Conversion Congress and Exposition
load types. through its International Travel Support Scheme.
RAY AND MISHRA: BOOST-DERIVED HYBRID CONVERTER WITH SIMULTANEOUS DC AND AC OUTPUTS 1093

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pp. 1–10, Mar. 2010. and control.