This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2021.3084181, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

A Wide Range High Voltage Gain Bidirectional

DC-DC Converter for V2G and G2V Hybrid EV
Charger
Hamed Heydari-doostabad, Member, IEEE, Terence O’Donnell, Senior Member, IEEE

Abstract—This paper proposes a new wide range bidi-

rectional dc-dc converter that has an improved voltage
gain transfer ratio for use in electric vehicle (EV) appli-
cations. The converter preserves the common electrical
ground between input and output terminals, and presents
a low voltage stress of switches, high utilization factor and
high efficiency. The proposed EV charger performance is
evaluated for bidirectional power flow in grid connected
Vehicle to Grid (V2G) and Grid to Vehicle (G2V) modes.
The converter uses a dead-beat current controller in the
dc-dc and dc-ac stages which has a smooth, accurate and
fast response. Finally, experimental results for a 500 W, Fig. 1. Layout of an EV electrical system.
40 V to 200 V prototype are provided under bidirectional
power flow in a closed-loop system in the presence of
the proposed dead-beat controllers. The obtained results
longer term flexibility for peak shaving and valley filling of
substantiate the theoretical analysis and the applicability
of this structure. The converter exhibits the capability for load profiles curves is also a possibility [3].
EV battery charging/discharging and demonstrates a peak A key element of a V2G system is, as shown in Fig. 1,
efficiency of 97.2% and 96.8% in the step-down and the the bidirectional power converter which acts as an interface
step-up mode of operation, respectively. circuit stage between the battery pack and the grid side. Such
Index Terms—Bidirectional dc-dc converter, high voltage converters should be capable of enabling V2G and grid to
gain, non-isolated, semiconductor utilization factor, wide vehicle (G2V) operation modes with high efficiency, low cost,
range voltage gain. safe operation, and provide a fast and high quality performance
[4]–[9]. As the voltage level of the EV’s battery is relatively
low, to match the low voltage (LV) level of the battery and the
I. I NTRODUCTION high voltage (HV) level of the grid side, a wide range, high

E NERGY decarbonization policies around the world are voltage gain, bidirectional dc-dc converter is needed.
promoting the increased use of variable renewable gen- A wide range high voltage gain ratio can be obtained by
eration and the massive electrification of transport [1]. In this adjusting turns-ratio of the coupled-inductor based converters,
context the concept of using the considerable energy storage but they need to address the additional problems of leakage
of electric vehicles as a resource to aid renewable integration, inductance, such as high voltage spikes across power switches
so called vehicle to grid (V2G) has gained considerable especially if snubber circuits are not included [10], [11].
traction [2]. Ideally the electric vehicle (EV) battery would Due to the safety and electromagnetic interface (EMI)
be charged during periods of low demand (e.g. night time) effects, converter structures with a common ground between
or high renewable generation and the stored energy would be input and output terminals are more interesting for industrial
available to supply back to the grid as a form of reserve. This applications [12].
reserve can assist in system frequency support by providing The common ground, wide voltage range dc-dc converters
services such as fast frequency support and spinning reserve to presented in [13], [14] suffer from restricted voltage gain, and
mitigate sudden load changes [1]. The potential of providing their efficiencies and dynamic responses are limited by the
extreme duty cycles of the power switches. The interleaved
structures in [11], [15] also suffer from limitations in voltage
Manuscript received July 14, 2020; revised October 30, 2020, Febru- range and a high number of switches, which typically present
ary 11, 2021 and April 08, 2021; accepted May 16, 2021. high complexity for the circuit and control system, increase
This publication has emanated from research supported in part
by a Grant from Science Foundation Ireland under Grant number cost and limit power density.
SFI/16/IA/4496. (Corresponding author: Hamed Heydari-doostabad). Recently, a number of new high voltage gain bidirectional
Hamed Heydari-doostabad and Terence O’Donnell are with the dc-dc converters have been presented in [16]–[18]. Although
School of Electrical and Electronic Engineering, University College
Dublin (UCD), Dublin 4, Ireland. they have a high voltage gain, their voltage range are limited,
(e-mail: hamed.heydari-doostabad@ucd.ie; terence.odonnell@ucd.ie) and they do not have a common ground between input and

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output or they require more switches and capacitors as in [18].

Quadratic voltage gain bidirectional converters in [8], [9],
[19] suffer from high voltage across capacitors especially at
high voltage gains. Moreover, the total voltage stress across the
semiconductor devices of the converter in [9], [19] is relatively
high, which leads to costs and lower efficiency and reliability.
In terms of the voltage gain limitations of these existing
bidirectional converters, the voltage gain range of converters
in [6], [7], [16], [20]–[23] is from 0 to 0.5 in step down and Fig. 2. Proposed bidirectional converter structure.
from 2 to ∞ in step up. For the converters in [11], [17], [18]
the range is from 0 to 1/3 and from 3 to ∞ and converter
in [24] is from 0 to 1/4 and from 4 to ∞. Therefore, these respectively. The proposed dc-dc converter consists of two
converters are inactive for the voltage gain area between 0.5 inductors L1 and L2 , four capacitors C1 , C2 and Co(1,2)
to 2, 1/3 to 3 and 1/4 to 4, respectively. The practical voltage and five switches S1 , S2 , Q1 , Q2 and Q3 . The switches and
gain in the step-up and step-down modes of converters in [4]– body diodes conduct alternatively during a complete switching
[7], [10], [13], [14], [20]–[23] is relatively low. In addition period (Ts ). In order to interface the bidirectional dc-dc
the bidirectional topologies presented in [5], [6], [10], [15], converter to the ac grid, a conventional single-phase full-bridge
[17], [18], [22], [25] do not have a common ground between dc-ac converter using unipolar PWM modulation is used as
the input and output terminals, which produces an additional also depicted in Fig. 2. The basic PWM operation of the dc-
dvdt issue between the input and output grounds. Thus, its ac converter which consists of the four switches: SA , SB , SC
applications are limited. and SD , follows conventional, well known principles and so
Considering the above limitation of the existing converter is not described in detail here. The dc-ac has an inductive
topologies there is scope to provide an improved bidirectional filter, Lg , on the grid side. The step-down and the step-up
converter with a common ground, which has no voltage gain modes of the dc-dc converter in continuous conduction mode
restrictions, is simple and has an improved semiconductor (CCM) and discontinuous conduction mode (DCM) are shown
utilization. This paper proposes such a step-down/step-up bidi- in Figs. 3 and 4 and the detailed analysis of each mode are as
rectional converter suitable for use as the interface converter follows:
in V2G and G2V applications. The circuit has a wide and
high voltage gain range and so can provide the dynamic A. Step-down Mode
matching between the battery voltage and the constant dc link
A dc source and the load is connected to the VHV and VLV
voltage. The range of voltage gain is from 0 to ∞ and there
side, respectively. Two states for CCM (four states for DCM)
is no limitation, theoretically. The existence of a common
operation are defined as:
ground between the input and output terminals also avoids the
State 1 CCM and DCM [0 − t1 ]: In this interval and
additional dvdt issue, which is beneficial for the operation
according to Fig. 3(a), Q1 , Q2 and Q3 are turned on while S1
of the proposed converter. As well as a wide high voltage
and S2 are turned off. In this period, L2 is charged by the input
gain range and low power stress on semiconductor devices
dc source and the released energy from C1 . Thus, the current
(or high utilization factor), this converter also has a simple
through L2 increases, whereas the energy of L1 is increased
structure. The maximum total voltage stress of switches is
from C2 . According to the typical time-domain waveforms in
4VHV and the maximum semiconductors utilization factor
Fig. 5(a) the derived current and voltage equations are:
(SUF) is 0.71. As a result, the proposed converter can use 
power switches with low rated power, which can improve vL1 = L1 didtL1 = −VLV + vC1 = −VLV + vC2
(1)
efficiency. In summary, the converter proposed in this work vL2 = L2 didtL2 = +VHV − vC1 = +VHV − vC2
offers the highest-wide voltage gain ratio with higher SUF than
As shown in (1) the voltage across C1 and C2 are equal, that
all previously published bidirectional converters. Furthermore,
is, vC1 = vC2 .
a dead-beat current controller is adopted for the direct battery
State 2 CCM [t1 − Ts ] and DCM [t1 − t2 ]: Contrary to
current regulation which offers accurate, fast, and smooth
state 1, during this interval as shown in Fig. 3(b), Q1 , Q2
operation under different states of charge (SoC).
and Q3 are turned off whereas the body diodes of S1 and S2
The proposed structure is presented in section II. Section
are conducting. The inductor L2 releases its energy into the
III is devoted to the practical considerations and design of the
capacitors C1 and C2 . Similarly, the energy of L1 is released
proposed converter calculation. Comparisons to the previous
to the VLV side.
state of art converters are presented in section IV, the dead-
beat current controller implementation is given in section V 
vL1 = L1 didtL1 = −VLV
and the experimental verification is provided in section VI. (2)
vL2 = L2 didtL2 = −vC1 − vC2
Finally, section VII concludes the paper.
By applying volt-second balance on L1 and L2 , we have
II. P ROPOSED C ONVERTER O PERATION A NALYSIS
D(−VLV + VC1 ) + (1 − D)(−VLV ) = 0 (3)
Fig. 2 shows the proposed converter structure. VLV and
VHV denote the low voltage and the high voltage sides, D(VHV − VC1 ) + (1 − D)(−VC1 − VC2 ) = 0 (4)

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(a) (b) (c)

Fig. 3. Equivalent circuit of the proposed converter in the step-down mode: (a) state 1, (b) state 2 and (c) state 3.

(a) (b) (c)

Fig. 4. Equivalent circuit of the proposed converter in the step-up mode: (a) state 1, (b) state 2 and (c) state 3.

(a) (b)
Fig. 6. Time-domain waveforms in DCM: (a) step-down and (b) step-up.

current through L1 meets zero at time t3 , both before the end

of the switching period.
State 4 DCM [t3 − Ts ]: In this mode, all of the power
switches are turned off. The current through inductors meets
zero. At the end of this interval, a complete period Ts has
(a) (b) been passed.
Fig. 5. Time-domain waveforms in CCM: (a) step-down and (b) step-up. Considering these intervals, one can define D1 and D2
as duty cycles where the current of L1 and L2 becomes
zero, respectively. In this regard, according to a typical DCM
where D represents the duty cycle. By using (3), the average waveform in Fig. 6(a), the voltage across the inductors can
voltage across C1 and C2 can be determined as define

VC1 = VC1 = VLV D (5) −VLV + vC1orC2 0 ≤ t < DTs
From (4) and (5), the voltage conversion ratio of the VL1 = −VLV DTs ≤ t < (D + D1 )Ts (7)

proposed converter during CCM operation for step-down mode 0 (D + D1 )Ts ≤ t < Ts
can be calculated as follows 
VLV D2  VHV − vC1 0 ≤ t < DTs
Mstep−down(CCM ) = = (6) VL2 = −vC1 − vC2 DTs ≤ t < (D + D2 )Ts (8)
VHV 2−D 
0 (D + D2 )Ts ≤ t < Ts
State 3 DCM [t2 −t3 ]: According to Fig. 3(c), in this mode,
the current through inductor L2 meets zero at time t2 and the Now the volt-second balance is applied on both inductors.

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
So, the voltage of capacitors are  vC1 + vC2 0 ≤ t < DTs
VL2 = −VHV + vC1 DTs ≤ t < (D + D2 )Ts (18)
VC1 = VC2 = (D + D1 )VLV D (9) 
0 (D + D2 )Ts ≤ t < Ts
As a result, the DCM voltage gain transfer ratio during the Now the volt-second balance is applied on both inductors.
step-down mode can be obtained as: So, the voltage of the capacitors are
VLV D2
Mstep−down(DCM ) = = (10) VC1 = VC2 = (D + D1 )VLV D1 (19)
VHV (D + D1 )(D + 2D2 )

B. Step-up Mode As a result, the DCM voltage gain transfer ratio in the step-
up mode can be obtained as:
In this mode, the power flows from VLV side to VHV side.
Two states for CCM (four states for DCM) operation are VHV (D + D1 )(2D + D2 )
Mstep−up(DCM ) = = (20)
defined as: VLV D1 D2
State 1 CCM and DCM [0 − t1 ]: In this interval and
according to Fig. 4(a), S1 and S2 are both turned on while It must be mentioned that for CCM operation it is possible
Q1 , Q2 and Q3 are turned off. In this state, L1 is charged by to operate S1 and S2 as synchronous rectifiers during step-
the input dc source. Thus, the current through L2 increases, down mode and to operate Q1 , Q2 and Q3 as synchronous
whereas the energy of L2 is increased from C1 and C2 . rectifiers during step-up mode.
According to the typical time-domain waveforms in Fig. 5(b)
the derived current and voltage equation are: III. D ESIGN C ONSIDERATIONS

vL1 = L1 didtL1 = VLV A. Duty cycle calculation
(11)
vL2 = L2 didtL2 = vC1 + vC2
The duty cycle during the step-down and the step-up modes
State 2 CCM [t1 − Ts ] and DCM [t1 − t2 ]: Contrary to and CCM and DCM modes can be calculated according to
state 1, during this interval as shown in Fig. 4(b), S1 and S2 VLV and VHV side voltages.
are turned off whereas the body diodes of Q1 , Q2 and Q3 From (6) and (16), the duty cycles of the proposed con-
are conducting. The inductor L1 releases its energy into the verter in the step-down (Dstep−down ) and the step-up mode
capacitors C2 . Similarly, the energy of L2 is released to the (Dstep−up ) can be obtained:
VHV side. √

vL1 = L1 didtL1 = +VLV − vC1 = VLV − vC2 Dstep−down = 05(−VLV + VLV 2 + 8V
LV VHV )VHV (21)
(12)
vL2 = L2 didtL2 = −VHV + vC1 = −VHV + vC2
√
As shown in (12) the voltage across C1 and C2 are equal, Dstep−up = 05(2VHV + VLV − 2 + 8V
VLV LV VHV )VHV
that is, vC1 = vC2 . (22)
By applying volt-second balance on L1 and L2 , we have The current ripple of inductors L1 and L2 can be obtained
D(VLV ) + (1 − D)(VLV − VC1 ) = 0 (13) as follows

D(VC1 + VC2 ) + (1 − D)(−VHV + VC1 ) = 0 (14) 1−D 2(1 − D)

step-down:∆iL1 = VLV , ∆iL2 = VLV (23)
L1 fs L2 fs D
By using (13), voltage across C1 and C2 can be determined
as D 2D
VC1 = VC2 = VLV (1 − D) (15) step-up:∆iL1 = VLV , ∆iL2 = VLV (24)
L1 fs L2 fs (1 − D)
From (14) and (15), the voltage conversion ratio of the where fs is switching frequency.
proposed converter during CCM operation for step-up mode Under DCM operation, the average current of L1 and L2
can be calculated as follows and duty cycles can be obtained as
VHV 1+D
Mstep−up(CCM ) = = (16) IL1 = ILV = ∆iL1 (D + D1 )2
VLV (1 − D)2
D 1−D
State 3 DCM [t2 − t3 ]: According to Fig. 4(c), the current IL2 = ILV = ILV = ∆iL2 (D + D2 )2 (25)
2−D 1+D
through inductor L1 meets zero.      
step-down step-up
State 4 DCM [t3 − Ts ]: In this mode, all of the power
switches are turned off. The current through the inductors Therefore, D1 and D2 for the DCM modes can be calculated
meets zero. At the end of this interval, a complete switching as: {
period Ts has been completed. 2L1 fs ILV
D1 = (1−D)V −D
As shown in Fig. 6(b), the following equations can define step-down: LV
D 2 L2 fs ILV (26)
the voltage across the inductors D2 = (2−D)(1−D)V LV
−D

 VLV 0 ≤ t < DTs { 2L1 fs ILV
D1 = −D
VL1 = VLV − vC1orC2 DTs ≤ t < (D + D1 )Ts (17) step-up: DVLV
(27)
 (1−D)2 L2 fs ILV
0 (D + D1 )Ts ≤ t < Ts D2 = D(1+D)VLV −D

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B. Semiconductors rating TABLE I

C OMPARISON OF MAIN B IDIRECTIONAL DC-DC C ONVERTERS
The average on-current and average off-voltage across the
switches can be expressed as: Voltage

Number
Common Mstep−down Pout [W] Peak η[%]

Ref.
of Gain Step-down
 IS1 = 2ILV (2 − D) Elements†
ground? Mstep−up range f s [kHz] Step-up


I 4S yes D 1[kW]
S2,Q3 = DILV (2 − D) [4] 1L, 3C 0−∞ < 97%
step-down: , 1(1 − D) 50[kHz]

 IQ1 = 2ILV (2 − D) 3S D(2−D) 200[W] 967%

 [5] 2L, 2C no 0−∞
(1+D)(1−D) 50[kHz] 962%
IQ2 = (1 − D)ILV (2 − D) 4S D2 0−0.5 200[W] 948%
 (28) [6] 1L, 3C no
2(1 − D) 2−∞ 50[kHz]
I = 2I (1 − D) 2 941%

 S1 HV
4S D2 0−0.5 140[W]

I [7] 1L, 4C yes 963%
S2,Q3 = IHV (1 − D) 2(1 − D) 2−∞ 70[kHz] 975%
step-up: 4S D2 100[W] 937%
IQ1 = IHV (1 − D)2
 [8] 2L, 3C yes 0−∞
 1(1 − D)2 50[kHz] 955%

IQ2 = DIHV (1 − D)2 4S yes D2
0−∞
160[W] 950%
[9] 2L, 3C 1(1 − D)2 30[kHz]
 965%

VS1,Q1,Q2 = DVHV (2 − D) 3S 0.5D(1-D) 1.6[kW] 976%
[10] 2L, 4C no 0−∞
2D(1 − D) 100[kHz] 975%
step-down: VS2 = VHV , 8S D3 0−1/3 800[W] 959%

 [11] 3L, 6C yes
VQ3 = 2VHV (2 − D) 3(1 − D) 3−∞ 20[kHz] 958%
 (29) 3S yes D(2 − D)
0−∞
300[W] 9624%
 [13] 2L, 4C (1+D)(1−D) 20[kHz]
VS1,Q1,Q2 = (1 − D)VHV (1 + D) 9644%
3S yes D(2 − D) 500[W] 967%
step-up: VS2 = VHV [14] 2L, 4C (1+D)(1−D)
0−∞
30[kHz] 963%


VQ3 = 2VHV (1 + D) 5S yes D(3 − D) 0−0.5 400[W] 9441%
[16] 2L, 6C (2+D)(1−D) 2−∞ 20[kHz] 9409%
5S D(4 − D) 0−1/3 490[W] 935%
C. Passive components design [17] 2L, 3C no
(3+D)(1−D) 3−∞ 50[kHz] 940%
From (1) and (11), inductance values can be obtained as: 6S
no D 2 (2 + D) 0−1/3 2[kW] 974%
[18] 2L, 5C (3−D)(1−D)2 3−∞ 100[kHz] 972%
1−D 2(1 − D) 4S, 2D D2 200[W]
step-down:L1 ≥ VLV , L2 ≥ VLV (30) [19] 2L, 3C yes 0−∞
887%
∆iL1 fs ∆iL2 fs D 1/(1 − D)2 15[kHz] 832%
6S yes D4 0−1/4 500[W] 969%
DVLV 2DVLV [24] 2L, 5C 4−∞ 400[kHz]
step-up:L1 ≥ , L2 ≥ (31) 4(1 − D) 971%
∆iL1 fs ∆iL2 fs (1 − D) 5S
no
D2 0−0.5 1[kW] 9530%
[20] 2L, 4C 2(1 − D) 2−∞ 20[kHz] 9521%
Using (30), (31) and having the permissible range of current 4S D2 0−0.5 3[kW]
yes 976%
ripples ∆iL1 and ∆iL2 , the inductor values can be calculated. [21] 2L, 4C 2(1 − D) 2−∞ 50[kHz] 974%
Moreover, the minimum value of inductor currents must be 3S
no
D(1 + D) 0−0.5 120[W] 9762%
[22] 1L, 3C (2−D)(1−D) 2−∞ 30[kHz]
positive for CCM, the critical value of L1 and L2 can be 9780%
4S yes D2 0−0.5 300[W] 9445%
expressed as: [23] 1L, 4C 2(1 − D) 2−∞ 20[kHz] 9439%
(1 − D)VLV (2 − D)(1 − D) 3S D(2 − D) 2[kW] 986%
[25] 2L, 4C no 0−∞
step-down:L1 ≥ , L2 ≥ VLV (1+D)(1−D) 20[kHz] NA
2fs ILV D 2 fs ILV 5S D 2 (2 − D) 500[W] 972%
(32) Pro. yes 0−∞
2L, 4C (1+D)(1−D)2 50[kHz] 968%
DVLV D(1 + D)VLV
step-up:L1 ≥ , L2 ≥ (33) † S: switch, D: diode, L: inductor, C: capacitor.
2fs ILV (1 − D)2 fs ILV
Number of capacitors includes LV side and HV side capacitors.
The values of C1 , C2 and Co(1,2) can be obtained as:
D(1 − D)ILV (1 − D)VLV
step-down:C1,2 ≥ , Co1 ≥
∆vC1,2 fs (2 − D) 8∆vCo1 fs2 L1 IV. C OMPARISON OF P ROPOSED C ONVERTER TO THE
(34) S TATE OF A RT
D(1 − D)ILV D(1 − D)2 VLV
step-up:C1,2 ≥ , Co2 ≥ Some general information on the characteristics of the main
∆vC1,2 fs (1 + D) ∆vCo2 fs (1 + D)
(35) bidirectional dc-dc converters and the proposed converter are
Similarly, using (34), (35) and having the permissible range provided in Table I. Some of these structures suffer from a
of voltage ripples ∆vC1 , ∆vC2 , ∆vCo(1,2) , capacitor values lack of common ground between input and output terminals
can be selected. such as [5], [6], [10], [17], [18], [20], [22], [25].
Considering 50 kHz as the switching frequency, VLV = 40 A voltage gain comparison is made between the proposed
V, VHV = 200 V, maximum current ripple of L1 and L2 is 1 converter and the main bidirectional dc-dc structures in Fig. 7.
A and 2 A, respectively. The maximum voltage ripple of C1,2 The main point of Fig. 7(a) is that the converter in [18] has
is 4 V and the output voltage ripple is 1 V. The critical passive the lowest step-down voltage gain. However, due to it’s voltage
components are L1 = 368 µH, L2 = 681 µH, C1 = C2 = 10 gain relationship (D 2 (2 + D)), this converter suffers from a
µF and Co(1,2) = 23 µF. limited voltage gain range which only ranges between 0 and
It must be mentioned, the maximum critical inductor values 1/3. Hence, in the step-down mode, the proposed converter
for operating in DCM mode at both step-down and step-up has the lowest-wide range voltage gain in comparison to the
modes are L1 = 14.71 µH and L2 = 147.10 µH. other structures.

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(a)

(a) (b)
Fig. 7. Voltage gain comparison: (a) step-down and (b) step-up modes.

Similarly from Fig. 7(b), in step up mode due to voltage

gain relationship ((3 − D)(1 − D)2 ), the minimum voltage
gain of the converter in [18] is 3, whereas for the proposed (b)
converter it is 1, thus the proposed converter offers the highest-
wide range voltage gain in the step-up mode in comparison Fig. 8. (a) Comparison of total voltage of semiconductors and (b) the
total voltage of capacitors (step-down left and step-up right).
to the other structures. Furthermore, as shown in Fig. 7, the
quadratic voltage gain converters in [8], [9], [19] are the main
competitors for the proposed converter in regards to voltage
gain.
Another comparison can be made between the proposed
converter and its main competitors in [8], [9], [18], [19]
based on normalized total voltage of semiconductor devices
(Σj VSj VHV ) and normalized total voltage of capacitors
(Σj VCj VHV ) as shown in Fig. 8. Hence, the proposed con-
verter offers lower Σj VSj VHV than converters in [9], [18],
[19]. Also, Σj VCj VHV of the proposed converter is lower
than converters in [8], [9], [19] at the voltage gains higher than
6. It must be mentioned that, the Σj VSj VHV of converter
Fig. 9. Semiconductor utilization factor (step-down left and step-up
in [18], is lower than the proposed converter. However, the right).
converter in [18], is inactive in the voltage gain area between
1/3 to 3, which is demonstrated in Fig. 8 as the inactive area.
It is also useful to compare the semiconductor utilization the component count voltage gain range, semiconductor device
factor (SUF) of the proposed converter and the main competi- ratings, common ground between input and output terminals
tor approaches. The SUF of a converter should be as high as and efficiency which makes it a very practical solution for an
possible to reduce the cost of the semiconductor devices. As EV power converter unit.
was mentioned in [26], in a good converter design, the voltage
and current imposed on a semiconductor device is minimized, V. C ONTROL S YSTEM D ESIGN
while the output power (Po ) is maximized. The SUF can be
defined as The control of the proposed converter includes the current
∑n
SU F = Po  VSj ISj (36) control of LV side (or battery current) during constant current
j=1 (CC) loop and the voltage control of LV side (or battery volt-
where n is number of semiconductor devices, VSj and ISj is age) during constant voltage (CV) loop. The overall diagram
the peak voltage and the peak current of semiconductor device of the proposed control system is shown in Fig. 10.
j, respectively. In this converter, a simple fast yet efficient digital dead-beat
Fig. 9 shows the SUF curves of the main compared convert- current control concept is adopted for both directions.
ers and the proposed converter versus voltage gain. It is clear Based on [27], [28], the LV side voltage reference VLV ∗
(or
that the proposed converter has the highest SUF compared to Vbat ) is usually set as the full-charge voltage of the battery.
∗

the other bidirectional converters. When the battery is not fully charged, the LV side current
Furthermore, as will be shown later, the measured maximum reference ILV∗
(or Ibat
∗
) is determined.
efficiencies during the step-down and the step-up modes are When the battery is not fully charged, the output of the PI
97.2% and 96.8%, respectively for the proposed converters. compensator in the CC/CV control loop is saturated by the
Therefore, the proposed converter presents a good balance of limiter and the battery current reference Ibat
∗
is determined by

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Fig. 10. The overall control system of proposed EV charger.

OFF state (δQ,OF F ) can be express as

diL1 vC1 − VLV diL1 −VLV
δQ,ON = = , δQ,OF F = =
dt L1 dt L1
(39)
Similarly, in the step-up mode, when the switches S1,2 are
ON , the voltage across L1 can be expressed as

vL1 = L1 diL1 dt = VLV (40)

And when S1,2 are OFF , the inductor voltage is
(a)
vL1 = L1 diL1 dt = VLV − vC1 (41)

The current slope of L1 during S1,2 ON state (δS,ON ) and

OFF state (δS,OF F ) can be expressed as
diL1 VLV diL1 VLV − vC1
δS,ON = = , δS,OF F = = (42)
dt L1 dt L1
As shown in Fig. 11(a) and based on predictive control
(b)
theory [30], the inductor L1 current at the next sampling time
Fig. 11. (a) Battery current variations during CC and CV modes, (IL1 [k + 1]) can be calculated from its current value (IL1 [k]),
(b) Charging and discharging states of inverter (left) and grid current using the slopes in (39) and (42), i.e.,
variation (right).
IL1 [k + 1] = IL1 [k] + δQ/S,ON tON + δQ/S,OF F tOF F (43)

the upper limit value of the limiter. When VLV reaches the where tON and tOF F are the Q (or S) ON and OFF state dwell
full-charge voltage, the voltage control loop is activated by times, respectively.
the PI compensator to regulate the battery voltage [29]. The controller is intended to eliminate the error Ie between
The control of the inverter used to interface with the grid is the reference current (ILV∗
) and IL1 [k + 1] [31]–[34], which
set up to regulate its dc side voltage, VHV , with an outer PI translates to
based dc voltage control loop and an inner current control loop ∗
Ie = ILV − IL1 [k + 1] =
based on dead-beat control. The outer dc voltage controller is ∗ (44)
ILV − IL1 [k] − δQ/S,ON tON − δQ/S,OF F tOF F = 0
designed according to [28].
Then, tON and consequently, optimal D can be obtained as
The outputs of the PI compensator and limiter become the
reference for the dead-beat current control loop. As will be ∗
(ILV − IL1 [k]) − δQ/S,OF F Ts
shown, the proposed dead-beat current controller can also D= (45)
(δQ/S,ON − δQ/S,OF F )Ts
simply determine the optimal duty cycle, for the step-down and
the step-up modes from the measured VLV and C1 voltage, and The grid side inverter current controller is aims to shape
measured and reference current through the L1 inductance. the current through Lg , denoted as ig , as a pure sinusoid. As
In the step-down mode, when Q1,2,3 are ON, the voltage shown in Fig. 11(b) a simple dead-beat current controller is
across L1 can be determined as again developed for this goal. The simple equivalent circuit of
the inverter stage is shown in Fig. 11(b). In the equivalent cir-
vL1 = L1 diL1 dt = vC1 − VLV (37) cuit, when SA is ON, the voltage across Lg can be determined
as
When Q1,2,3 are OFF , the inductor voltage is vLg = Lg dig dt = VHV − vg (46)
where vg is grid voltage.
vL1 = L1 diL1 dt = −VLV (38)
When SA is OFF, the inductor voltage is
The slope of L1 current during Q1,2,3 ON state (δQ,ON ) and vLg = Lg dig dt = −vg (47)

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(a)
Fig. 12. Laboratory prototype of proposed converter.

TABLE II
E XPERIMENT PARAMETERS

Parameters Values
Rated power (Pout ): 500 [W]
Switching frequency (fs ): 50 [kHz]
LV and HV side voltages (VLV , VHV ): 40 [V] and 200 [V]
Grid side voltage (vg ): 110 [V], 50 [Hz]
Inductors L1 , L2 and Lg : 0.4 [mH], 1 [mH] and 4 [mH]
Capacitors C1 , C2 and Co(1,2) : 22 [µF], 22 [µF] and 680 [µF]
MOSFETs: IPW60R099CPA (b)
Microcontroller: STM32F407VGT
Fig. 13. Operation of CCM: (a) step-down and (b) step-up modes.

The slope of ig during SA ON-state (δinv,ON ) and OFF -state However for the sake of simplicity in the prototype, only
(δinv,OF F ) can be written as one type of switch is used and we try to find a high
dig VHV − vg dig −vg efficiency solution in terms of switch selection. The main
δinv,ON = = , δinv,OF F = = (48) features of the selected CoolMOS TM are very low values of
dt Lg dt Lg
on-state resistance (RDS,on ), drain-source output capacitance
Now one can predict the inductor current at the next (Coss ), rise time, fall time, gate-source charge (Qgs ), gate-
sampling period (ig [k + 1]) from its current value (ig [k]), by drain charge (Qgd ) and reverse recovery charge, which are
using the slopes already determined, i.e. relatively unique characteristics and results in improved energy
conversion efficiency. In this section, two operation modes are
ig [k +1] = ig [k]+δinv,ON tinv,ON +δinv,OF F tinv,OF F (49)
examined, i.e.: dc and grid connected modes.
where tinv,ON and tinv,OF F are the SA ON and OFF state
dwell times, respectively. A. Proposed DC-DC converter operation
The controller is intended to eliminate the error, ie , between
In this section the operation of the dc-dc converter alone is
the reference current (i∗g ) and ig [k + 1], which translates to
verified.
ie = i∗g − ig [k + 1] = Fig. 13(a) illustrates the performance of step-down mode
(50)
i∗g − ig [k] − δinv,ON tinv,ON − δinv,OF F tinv,OF F = 0 under steady state operation and under a step change in LV
side current reference from 6 A to 12.5 A. It can be seen that
Then, tinv,ON and consequently the optimal modulation
the input HV side voltage is 200 V and the voltage across the
index can be determined as
load changes from 18.2 V up to 40 V with the step change in
Lg (i∗g − ig [k]) + vg [k]Ts the reference LV side current.
minv = (51)
VHV Ts Subsequently, D varies stepwise from 0.38 to 0.54, as, the
LV side current varies from 6 A to 12.5 A. Fig. 14(a) shows
VI. E XPERIMENTAL V ERIFICATION the voltage and the current of switches in step-down mode
To confirm the feasibility of the proposed EV charger, a which validates the equations of Section III-B.
laboratory hardware setup shown in Fig. 12 is implemented. Similarly, Fig. 13(b) shows the performance of the converter
The specifications of the converter and component parameters in step-up mode under steady state operation and in response
are presented in Table II. to a step change in LV side current command from 6 A to
In theory, because not all switches in the converter re- 12.5 A. In this case, the input LV side voltage is 40 V and
quire the same voltage rating, a cost optimal design might since the inverter is not connected, the output voltage is not
use various different switches with different voltage ratings. regulated but steps from 140 V up to 200 V with the step

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(a) (b)
Fig. 16. Voltage and current of inductors during DCM mode: (a) step-
down and (b) step-up modes.

of LV side current which is essential for an appropriate

and smooth behavior of the proposed converter when grid
connected, which is examined in the next section. The voltage
and current of switches during step-up mode are shown in
Fig. 14(b).
The output of the converter in response to a step change in
current direction, i.e. from charging to discharging is shown
in Fig. 15. As shown in this figure, the battery side current
command changes from +5 A (charging) to -5 A (discharging),
as a consequence of which, the HV side current changes from
-1 A to +1 A.
The DCM operation of the proposed converter during step-
down and step-up modes are shown in Fig. 16(a) and (b),
respectively. The values of VLV and VHV with respect to D,
D1 and D2 confirm the DCM voltage gains.

B. Grid-connected results
The steady state experimental results of the proposed EV
charger for the grid connected mode in terms of G2V and
V2G performance is shown in Fig. 17. The LV side current (or
battery current Ib ) reference and the HV side voltage reference
(a) (b) is 12.5 A and 200 V, respectively. Note in Fig. 17(b), the step
Fig. 14. Voltage and current of switches and inductors: (a) step-down, change in VHV and VLV simply indicates the point at which
(b) step-up modes. the inverter side dc link voltage control is activated. Battery
voltage and grid voltage is 40 V and 110 V, respectively.
As shown in this figure, the battery is charged (G2V) and
discharged (V2G) with sinusoidal grid current.

C. Proposed converter evaluation

Fig. 18(a) shows the measured efficiency curves under dif-
ferent modes of operation. The maximum efficiency of the
proposed converter during charging (G2V) and discharging
(V2G) modes is 97.2% and 96.8%, respectively. The input
and output powers for the measurement of efficiency have
Fig. 15. Bidirectional charging and discharging operation. been obtained by using the math functions of the RIGOL
DS4024 digital oscilloscope on the measured voltage and
current waveforms.
increase in current. Also, D increases stepwise from 0.37 to A breakdown of the DC converter losses is presented in
0.45. These results demonstrate the proper performance of Fig. 18(b). It can be seen that a large portion of the losses is
the proposed current controller under the change of reference attributed to the conduction losses.

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(a)

(a) (b)
Fig. 18. Proposed converter (a) efciency curve, (b) calculated loss
breakdown for step-down (left) and step-up (right) modes.

smooth and accurate current control for both directions of

operation. The charge and discharge of the battery has been
successfully demonstrated under both directions using the de-
veloped prototype. The proposed EV charger has a maximum
efficiency of 97.2% at VLV = 40 V, VHV = 200 V, Pout = 500
W, and fs = 50 kHz. The measured waveforms from the proto-
type have validated the analysis and operation of the converter.
The advantages of the converter in terms of wider voltage
range and higher SUF make it a more practical and versatile
topology compared to previously published converters.

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for electric vehicles,” IEEE Trans. Veh. Technol., vol. 69, no. 1, pp. Hamed Heydari-doostabad (Member, IEEE)
194–206, Jan. 2020. received the Ph.D. (Hons.) degree in electri-
[19] V. F. Pires, D. Foito, and A. Cordeiro, “A dc-dc converter with quadratic cal engineering from the Ferdowsi University of
gain and bidirectional capability for batteries/supercapacitors,” IEEE Mashhad, Mashhad, Iran, in 2018. He is cur-
Trans. Ind. Appl., vol. 54, no. 1, pp. 274–285, Jan.-Feb. 2018. rently a Postdoctoral Senior Power System Re-
[20] Y. Zhang, Y. Gao, J. Li, and M. Sumner, “Interleaved switched-capacitor searcher with the School of Electrical and Elec-
bidirectional dc-dc converter with wide voltage-gain range for energy tronic Engineering, University College Dublin
storage systems,” IEEE Trans. Power Electron., vol. 33, no. 5, pp. 3852– (UCD), Dublin, Ireland.
3869, May. 2018. His research interests include power elec-
[21] H. Jeong, M. Kwon, and S. Choi, “Analysis, design, and implementation tronics, especially grid-feeding-forming invert-
of a high gain soft-switching bidirectional dc-dc converter with PPS ers, distributed energy resources, photovoltaic
control,” IEEE Trans. Power Electron., vol. 33, no. 6, pp. 4807–4816, inverters, dc converters, power quality, and control systems.
Jun. 2018.
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bidirectional dc-dc converter with low component counts,” IEEE Trans.
Ind. Appl., vol. 54, no. 2, pp. 1573–1582, March-April 2018. Terence O’Donnell (Senior Member, IEEE) re-
[23] Y. Zhang, Y. Gao, L. Zhou, and M. Sumner, “A switched-capacitor ceived the BE in Electrical Engineering from
bidirectional dc-dc converter with wide voltage gain range for electric University College Dublin in 1990 and the PhD
vehicles with hybrid energy sources,” IEEE Trans. Power Electron., degree, also in Electrical Engineering from Uni-
vol. 33, no. 11, pp. 9459–9469, Nov. 2018. versity College Dublin in 1996. He is currently an
[24] J. Chen, D. Sha, Y. Yan, B. Liu, and X. Liao, “Cascaded high voltage Associate Professor with the School of Electrical
conversion ratio bidirectional nonisolated dc-dc converter with variable and Electronic Engineering, University College
switching frequency,” IEEE Trans. Power Electron., vol. 33, no. 2, pp. Dublin (UCD), Dublin, Ireland.
1399–1409, Feb. 2018. He is a Principle Investigator within the UCD
[25] O. Cornea, G.-D. Andreescu, N. Muntean, and D. Hulea, “Bidirectional Energy Institute where his research interests
power flow control in a dc microgrid through a switched-capacitor cell are focused on the use of power electronics
[29] S. H. Hosseini, R. Ghazi, and H. Heydari-Doostabad, “An extendable converters in power systems and in particular on the interfacing of power
quadratic bidirectional dc-dc converter for V2G and G2V applications,” electronics to the grid. Specic interests include the grid applications of
IEEE Trans. Ind. Electron., vol. 68, DOI 10.1109/TIE.2020.2992967, solid state transformers, the control of converters for distributed energy
no. 6, pp. 4859–4869, Jun. 2021. resources and the use of power hardware in the loop testing methods.

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