Full/Low Speed 5 kV USB Digital Isolator

Data Sheet ADuM4160

FEATURES FUNCTIONAL BLOCK DIAGRAM
USB 2.0 compatible VBUS1 1 VBUS2
REG REG 16
Low and full speed data rate: 1.5 Mbps and 12 Mbps
GND1 2 15 GND2
Bidirectional communication
VDD1 3 14 VDD2
4.5 V to 5.5 V VBUS operation
7 mA maximum upstream supply current @ 1.5 Mbps PDEN 4 13 SPD
SPU 5 12 PIN
8 mA maximum upstream supply current @ 12 Mbps
2.3 mA maximum upstream idle current UD– 6 11 DD–

Upstream short-circuit protection UD+ 7 10 DD+

Class 3A contact ESD performance per ANSI/ESD STM5.1-2007

08171-001
GND1 8 9 GND2
PU LOGIC PD LOGIC
High temperature operation: 105°C
High common-mode transient immunity: >25 kV/μs Figure 1.
16-lead SOIC wide-body package version Many microcontrollers implement USB so that it presents only
16-lead SOIC wide body enhanced creepage version the D+ and D− lines to external pins. This is desirable in many
RoHS compliant cases because it minimizes external components and simplifies
Safety and regulatory approvals (RI-16 package) the design; however, this presents particular challenges when
UL recognition: 5000 V rms for 1 minute per isolation is required. USB lines must automatically switch between
UL 1577 actively driving D+/D−, receiving data, and allowing external
CSA Component Acceptance Notice #5A resistors to set the idle state of the bus. The ADuM4160 provides
IEC 60601-1: 250 V rms (reinforced) mechanisms for detecting the direction of data flow and control
IEC 60950-1: 400 V rms (reinforced) over the state of the output buffers. Data direction is determined
VDE Certificate of Conformity on a packet-by-packet basis.
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak The ADuM4160 uses the edge detection based iCoupler tech-
nology in conjunction with internal logic to implement a
APPLICATIONS transparent, easily configured, upstream facing port isolator.
USB peripheral isolation Isolating an upstream facing port provides several advantages
Isolated USB hub in simplicity, power management, and robust operation.
Medical applications The isolator has propagation delay comparable to that of a
GENERAL DESCRIPTION standard hub and cable. It operates with the bus voltage on
either side ranging from 4.5 V to 5.5 V, allowing connection
The ADuM41601 is a USB port isolator, based on Analog Devices,
directly to VBUS by internally regulating the voltage to the signaling
Inc., iCoupler® technology. Combining high speed CMOS and
level. The ADuM4160 provides isolated control of the pull-up
monolithic air core transformer technology, these isolation
resistor to allow the peripheral to control connection timing.
components provide outstanding performance characteristics
The device has a low idle current; so a suspend mode is not
and are easily integrated with low and full speed USB-compatible
required. A 2.5 kV version, the ADuM3160, is also available.
peripheral devices.

1
Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329.

Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.
ADuM4160 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1  Absolute Maximum Ratings ............................................................7 
Applications....................................................................................... 1  ESD Caution...................................................................................7 
General Description ......................................................................... 1  Pin Configuration and Function Descriptions..............................8 
Functional Block Diagram .............................................................. 1  Applications Information .............................................................. 10 
Revision History ............................................................................... 2  Functional Description.............................................................. 10 
Specifications..................................................................................... 3  Product Usage ............................................................................. 10 
Electrical Characteristics............................................................. 3  Compatibility of Upstream Applications ................................ 11 
Package Characteristics ............................................................... 4  Power Supply Options ............................................................... 11 
Regulatory Information............................................................... 4  Printed Circuit Board (PCB) Layout ....................................... 11 
Insulation and Safety-Related Specifications............................ 5  DC Correctness and Magnetic Field Immunity..................... 11 
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Insulation Lifetime ..................................................................... 12 
Characteristics .............................................................................. 5  Outline Dimensions ....................................................................... 14 
Recommended Operating Conditions ...................................... 6  Ordering Guide .......................................................................... 14 

REVISION HISTORY
2/12—Rev. C to Rev. D 8/10—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals Change to Data Sheet Title...............................................................1
Entry in Features Section................................................................. 1 Changes to Features Section ............................................................1
Changes to Table 3............................................................................ 4 Changes to Applications Section.....................................................1
Change to Table 4 ............................................................................. 5 Changes to General Description Section .......................................1
Updated Outline Dimensions ....................................................... 14 Changes to Table 3.............................................................................4
Changes to Ordering Guide .......................................................... 14 9/09—Rev. 0 to Rev. A
10/10—Rev. B to Rev. C Added USB Logo, Reformatted Page 1 ...........................................1
Changes to Features and General Description Section ............... 1 7/09—Revision 0: Initial Version
Changes to Endnote 3 in Table 1 and Table 3 ............................... 4
Changes to Table 4............................................................................ 5
Changes to Table 7 and Table 8....................................................... 7
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14

Rev. D | Page 2 of 16
Data Sheet ADuM4160

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V; 3.1 V ≤ VDD1 ≤ 3.6 V, 3.1 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over
the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Each
voltage is relative to its respective ground.

Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Total Supply Current1
1.5 Mbps
VDD1 or VBUS1 Supply Current IDD1 (L) 5 7 mA 750 kHz logic signal rate CL = 450 pF
VDD2 or VBUS2 Supply Current IDD2 (L) 5 7 mA 750 kHz logic signal rate CL = 450 pF
12 Mbps
VDD1 or VBUS1 Supply Current IDD1 (F) 6 8 mA 6 MHz logic signal rate CL = 50 pF
VDD2 or VBUS2 Supply Current IDD2 (F) 6 8 mA 6 MHz logic signal rate CL = 50 pF
Idle Current
VDD1 or VBUS1 Idle Current IDD1 (I) 1.7 2.3 mA
Input Currents IDD−, IDD+, −1 +0.1 +1 μA 0 V ≤ VDD−, VDD+, VUD+, VUD−, VSPD, VPIN,
IUD+, IUD−, VSPU, VPDEN ≤ 3.0
ISPD, IPIN,
ISPU, IPDEN
Single-Ended Logic High Input Threshold VIH 2.0 V
Single-Ended Logic Low Input Threshold VIL 0.8 V
Single-Ended Input Hysteresis VHST 0.4 V
Differential Input Sensitivity VDI 0.2 V |VXD+ − VXD−|
Logic High Output Voltages VOH 2.8 3.6 V RL = 15 kΩ, VL = 0 V
Logic Low Output Voltages VOL 0 0.3 V RL = 1.5 kΩ, VL = 3.6 V
VDD1 and VDD2 Supply Undervoltage Lockout VUVLO 2.4 3.1 V
VBUS1 Supply Undervoltage Lockout VUVLOB1 3.5 4.35 V
VBUS2 Supply Undervoltage Lockout VUVLOB2 3.5 4.4 V
Transceiver Capacitance CIN 10 pF UD+, UD−, DD+, DD− to ground
Capacitance Matching 10 %
Full Speed Driver Impedance ZOUTH 4 20 Ω
Impedance Matching 10 %
SWITCHING SPECIFICATIONS, I/O PINS LOW SPEED
Low Speed Data Rate 1.5 Mbps CL = 50 pF
Propagation Delay2 tPHLL, tPLHL 325 ns CL = 50 pF, SPD = SPU = low,
VDD1, VDD2 = 3.3 V
Side 1 Output Rise/Fall Time (10% to 90%) Low tRL/tFL 75 300 ns CL = 450 pF, SPD = SPU = low,
Speed VDD1, VDD2 = 3.3 V
Low Speed Differential Jitter, Next Transition |tLJN| 45 ns CL = 50 pF
Low Speed Differential Jitter, Paired Transition |tLJP| 15 ns CL = 50 pF
SWITCHING SPECIFICATIONS, I/O PINS FULL SPEED
Full Speed Data Rate 12 Mbps CL = 50 pF
Propagation Delay2 tPHLF, tPLHF 20 60 70 ns CL = 50 pF, SPD = SPU = high,
VDD1, VDD2 = 3.3 V
Output Rise/Fall Time (10% to 90%) Full Speed tRF/tFF 4 20 ns CL = 50 pF, SPD = SPU = high,
VDD1, VDD2 = 3.3 V
Full Speed Differential Jitter, Next Transition |tFJN| 3 ns CL = 50 pF
Full Speed Differential Jitter, Paired Transition |tFJP| 1 ns CL = 50 pF

Rev. D | Page 3 of 16
ADuM4160 Data Sheet
Parameter Symbol Min Typ Max Unit Test Conditions
For All Operating Modes
Common-Mode Transient Immunity
At Logic High Output 3 |CMH| 25 35 kV/μs VUD+, VUD−, VDD+, VDD− = VDD1 or VDD2,
VCM = 1000 V, transient magnitude =
800 V
At Logic Low Output3 |CML| 25 35 kV/μs VUD+, VUD−, VDD+, VDD− = 0 V, VCM =
1000 V, transient magnitude = 800 V
1
The supply current values for the device running at a fixed continuous data rate at 50% duty cycle alternating J and K states. Supply current values are specified with
USB-compliant load present.
2
Propagation delay of the low speed DD+ to UD+ or DD− to UD− in either signal direction is measured from the 50% level of the rising or falling edge to the 50% level
of the rising or falling edge of the corresponding output signal.
3
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDDx. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.

PACKAGE CHARACTERISTICS
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input to Output) 1 RI-O 1012 Ω
Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz
Input Capacitance 2 CI 4.0 pF
IC Junction-to-Ambient Thermal Resistance θJA 45 °C/W Thermocouple located at center
of package underside
1
Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14,
Pin 15, and Pin 16 are shorted together.
2
Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION
The ADuM4160 is approved by the organizations listed in Table 3. Refer to Table 8 and the Insulation Lifetime section for details
regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.

Table 3.
UL CSA VDE
Recognized under 1577 component Approved under CSA Component Certified according to DIN V VDE V
recognition program 1 Acceptance Notice #5A 0884-10 (VDE V 0884-10):2006-12 2
Single Protection Basic insulation per CSA 60950-1-07 and IEC 60950-1, Reinforced insulation, 846 V peak
5000 V rms Isolation Voltage 600 V rms (848 V peak) maximum working voltage.
Reinforced insulation per CSA 60950-1-07 and IEC
60950-1, 380 V rms (537 V peak) maximum working
voltage, RW-16 package.
Reinforced insulation per CSA 60950-1-07 and IEC
60950-1, 400 V rms (565 V peak) maximum working
voltage, RI-16 package.
Reinforced insulation per IEC 60601-1 125 V rms (176 V
peak) maximum working voltage, RW-16 package.
Reinforced insulation per IEC 60601-1 250 V rms (353 V
peak) maximum working voltage, RI-16 package.
File E214100 File 205078 File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM4160 is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec (current leakage detection limit = 10 μA).
2
In accordance with DIN V VDE V 0884-10, each ADuM4160 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.

Rev. D | Page 4 of 16
Data Sheet ADuM4160
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 5000 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 8.0 min mm Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) RW-16 Package L(I02) 7.7 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage) RI-16 Package L(I02) 8.3 min mm Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 5.
Description Conditions Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification 40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 846 V peak
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, VPR 1590 V peak
partial discharge < 5 pC
Input-to-Output Test Voltage, Method a VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VPR
After Environmental Tests Subgroup 1 1375 V peak
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC 1018 V peak
and Subgroup 3
Highest Allowable Overvoltage Transient overvoltage, tTR = 10 seconds VTR 6000 V peak
Safety-Limiting Values Maximum value allowed in the event of a failure
(see Figure 2)
Case Temperature TS 150 °C
Side 1 + Side 2 Current IS1 550 mA
Insulation Resistance at TS VIO = 500 V RS >109 Ω
600
SAFE OPERATING VDD1 CURRENT (mA)

500

400

300

200

100
08171-002

0
0 50 100 150 200
AMBIENT TEMPERATURE (°C)

Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10

Rev. D | Page 5 of 16
ADuM4160 Data Sheet
RECOMMENDED OPERATING CONDITIONS
Table 6.
Parameter Symbol Min Max Unit
Operating Temperature TA −40 +105 °C
Supply Voltages 1 VBUS1, VBUS2 3.1 5.5 V
Input Signal Rise and Fall Times 1.0 ms
1
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic
fields.

Rev. D | Page 6 of 16
Data Sheet ADuM4160

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
Table 7. may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational
Storage Temperature (TST) −65°C to +150°C
section of this specification is not implied. Exposure to absolute
Ambient Operating Temperature (TA) −40°C to +105°C
maximum rating conditions for extended periods may affect
Supply Voltages (VBUS1, VBUS2, VDD1, −0.5 V to +6.5 V
VDD2)1 device reliability.
Upstream Input Voltage −0.5 V to VDD1 + 0.5 V Table 8. Maximum Continuous Working Voltage1
(VUD+,VUD−, VSPU)1, 2
Parameter Max Unit Constraint
Downstream Input Voltage −0.5 V to VDD2 + 0.5 V
(VDD+, VDD−, VSPD, VPIN)1, 2 AC Voltage, Bipolar 565 V peak 50-year minimum
Average Output Current per Pin3 Waveform lifetime
Side 1 (IO1) −10 mA to +10 mA AC Voltage, Unipolar
Waveform
Side 2 (IO2) −10 mA to +10 mA
Basic Insulation 848 V peak Maximum approved
Common-Mode Transients4 −100 kV/μs to +100 kV/μs working voltage per
1
IEC 60950-1
All voltages are relative to their respective ground.
2
VDDI, VBUS1, and VDD2, VBUS2 refer to the supply voltages on the upstream and Reinforced Insulation 846 V peak Maximum approved
downstream sides of the coupler, respectively. working voltage per
3
See Figure 2 for maximum rated current values for various temperatures. VDE 0884-10
4
Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause latch-up DC Voltage
or permanent damage. Basic Insulation 848 V peak Maximum approved
working voltage per
IEC 60950-1
Reinforced Insulation 846 V peak Maximum approved
working voltage per
VDE 0884-10
1
Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more information.

ESD CAUTION

Rev. D | Page 7 of 16
ADuM4160 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VBUS1 1 16 VBUS2

GND1* 2 15 GND2*

VDD1 3 14 VDD2
ADuM4160
PDEN 4 TOP VIEW 13 SPD

SPU 5 (Not to Scale) 12 PIN

UD– 6 11 DD–

UD+ 7 10 DD+

GND1* 8 9 GND2*

NC = NO CONNECT

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING

08171-003
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.

Figure 3. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Direction Description
1 VBUS1 Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect VBUS1 to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
VBUS1 to VDD1 and to the external 3.3 V power supply. Bypass to GND1 is required.
2 GND1 Return Ground 1. Ground reference for Isolator Side 1.
3 VDD1 Power Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the VDDI pin
should be used for a bypass capacitor to GND1. Signal lines that may require pull up, such as PDEN and
SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS1 to
VDD1 and to the external 3.3 V power supply. Bypass to GND1 is required.
4 PDEN Input Pull-Down Enable. This pin is read when exiting reset. For standard operation, connect this pin to VDD1.
When connected to GND1 while exiting from reset, the downstream pull-down resistors are
disconnected, allowing buffer impedance measurements.
5 SPU Input Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied
low. This input must be set high via connection to VDD1 or set low via connection to GND1 and must
match Pin 13.
6 UD− I/O Upstream D−.
7 UD+ I/O Upstream D+.
8 GND1 Return Ground 1. Ground reference for Isolator Side 1.
9 GND2 Return Ground 2. Ground reference for Isolator Side 2.
10 DD+ I/O Downstream D+.
11 DD− I/O Downstream D−.
12 PIN Input Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can
be tied to VDD2 for operation on power-up, or tied to an external control signal for applications requiring
delayed enumeration.
13 SPD Input Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic
conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied
low. This input must be set high via connection to VDD2 or low via connection to GND2, and must match
Pin 5.
14 VDD2 Power Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the VDD2 pin
should be used for a bypass capacitor to GND2. Signal lines that may require pull-up, such as SPD, can be
tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2 and to the
external 3.3 V power supply. Bypass to GND2 is required.
15 GND2 Return Ground 2. Ground reference for Isolator Side 2.
16 VBUS2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,
connect VBUS2 to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect
VBUS2 to VDD2 and to the external 3.3 V power supply. Bypass to GND2 is required.

Rev. D | Page 8 of 16
Data Sheet ADuM4160

Table 10. Truth Table, Control Signals, and Power (Positive Logic) 1
VUD+, VDD+,
VSPU VBUS1, VDD1 VUD− VSPD VBUS2, VDD2 VDD− VPIN
Input State State Input State State Input Notes
H Powered Active H Powered Active H Input and output logic set for full speed logic convention
and timing.
L Powered Active L Powered Active H Input and output logic set for low speed logic convention
and timing.
L Powered Active H Powered Active H Not allowed: VSPU and VSPD must be set to the same value.
USB host detects communications error.
H Powered Active L Powered Active H Not allowed: VSPU and VSPD must be set to the same value.
USB host detects communications error.
X Powered Z X Powered Z L Upstream Side 1 presents a disconnected state to the USB
cable.
X Unpowered X X Powered Z X When power is not present on VDD1, the downstream data
output drivers revert to high-Z within 32 bit times. The
downstream side initializes in high-Z state.
X Powered Z X Unpowered X X When power is not present on VDD2, the upstream side
disconnects the pull-up and disables the upstream drivers
within 32 bit times.
1
H represents logic high input or output, L represents logic low input or output, X represents the don’t care logic input or output, and Z represents the high impedance
output state.

Rev. D | Page 9 of 16
ADuM4160 Data Sheet

APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION PRODUCT USAGE
USB isolation in the D+/D− lines is challenging for several The ADuM4160 is designed to be integrated into a USB
reasons. First, access to the output enable signals is normally peripheral with an upstream facing USB port as shown in
required to control a transceiver. Some level of intelligence must Figure 4. The key design points are:
be built into the isolator to interpret the data stream and 1. The USB host provides power for the upstream side of the
determine when to enable and disable its upstream and down- ADuM4160 through the cable.
stream output buffers. Second, the signal must be faithfully 2. The peripheral supply provides power to the downstream
reconstructed on the output side of the coupler while retaining side of the ADuM4160.
precise timing and not passing transient states such as invalid 3. The DD+/DD− lines of the isolator interface with the
SE0 and SE1 states. In addition, the part must meet the low peripheral controller, and the UD+/UD− lines of the
power requirements of the suspend mode. isolator connect to the cable or host.
The iCoupler technology is based on edge detection, and, 4. Peripheral devices have a fixed data rate that is set at design
therefore, lends itself well to the USB application. The flow of time. The ADuM4160 has configuration pins, SPU and
data through the device is accomplished by monitoring the SPD, that determine the buffer speed and logic convention
inputs for activity and setting the direction for data transfer for each side. These must be set identically and match the
based on a transition from the idle (J) state. When data desired peripheral speed.
direction is established, data is transferred until either an end- 5. USB enumeration begins when either the UD+ or UD−
of-packet (EOP) or a sufficiently long idle state is encountered. line is pulled high at the peripheral end of the USB cable,
At this point, the coupler disables its output buffers and which is the upstream side of the ADuM4160. Control of
monitors its inputs for the next activity the timing of this event is provided by the PIN input on the
During the data transfers, the input side of the coupler holds its downstream side of the coupler.
output buffers disabled. The output side enables its output buffers 6. Pull-up and pull-down resistors are implemented inside
and disables edge detection from the input buffers. This allows the coupler. Only external series resistors and bypass
the data to flow in one direction without wrapping back through capacitors are required for operation.
the coupler making the iCoupler latch. Logic is included to PERIPHERAL

eliminate any artifacts due to different input thresholds of the VDD2 3.3V

differential and single-ended buffers. The input state is transferred VBUS1 VBUS2
DD+ DD+
across the isolation barrier as one of three valid states, J, K, or USB DD– ADuM4160 DD– MICRO- POWER
SE0. The signal is reconstructed at the output side with a fixed HOST
GND1 PIN CONTROLLER SUPPLY
time delay from the input side differential input.

08171-004
The iCoupler does not have a special suspend mode, nor does it
need one because its power supply current is below the suspend Figure 4. Typical Application
current limit of 2.5 mA when the USB bus is idle.
Other than the delayed application of pull-up resistors, the
The ADuM4160 is designed to interface with an upstream ADuM4160 is transparent to USB traffic, and no modifications
facing low/full speed USB port by isolating the D+/D− lines. to the peripheral design are required to provide isolation. The
An upstream facing port supports only one speed of operation, isolator adds propagation delay to the signals comparable to a
thus, the speed related parameters, J/K logic levels, and D+/D− hub and cable. Isolated peripherals must be treated as if there
slew rate are set to match the speed of the upstream facing were a built-in hub when determining the maximum number of
peripheral port (see Table 10). hubs in a data chain.
A control line on the downstream side of the ADuM4160 activates Hubs can be isolated like any other peripheral. Isolated hubs
a pull-up resistor integrated into the upstream side. This allows can be created by placing an ADuM4160 on the upstream port
the downstream port to control when the upstream port attaches of a hub chip. This configuration can be made compliant if
to the USB bus. The pin can be tied to the peripheral pull-up, a counted as two hub delays. The hub chip allows the ADuM4160
control line, or the VDD2 pin, depending on when the initial bus to operate at full speed yet maintains compatibility with low
connect is to be performed. speed devices.

Rev. D | Page 10 of 16
Data Sheet ADuM4160
COMPATIBILITY OF UPSTREAM APPLICATIONS PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM4160 is designed specifically for isolating a USB The ADuM4160 digital isolator requires no external interface
peripheral. However, the chip does have two USB interfaces that circuitry for the logic interfaces. For full speed operation, the
meet the electrical requirements for driving USB cables. This D+ and D− line on each side of the device requires a 24 Ω ± 1%
opens the possibility of implementing isolation in downstream series termination resistor. These resistors are not required for
USB ports such as isolated cables, which have generic connections low speed applications. Power supply bypassing is required at
to both upstream and downstream devices, as well as isolating the input and output supply pins (see Figure 5). Install bypass
host ports. capacitors between VBUSx and VDDx on each side of the chip. The
capacitor value should have a value of 0.1 μF and be of a low
In a fully compliant application, a downstream facing port must ESR type. The total lead length between both ends of the
be able to detect whether a peripheral is low speed or full speed capacitor and the power supply pin should not exceed 10 mm.
based on the application of the upstream pull-up. The buffers and Bypassing between Pin 2 and Pin 8 and between Pin 9 and
logic conventions must adjust to match the requested speed. Pin 15 should also be considered, unless the ground pair on
Because the ADuM4160 sets its speed by hard wiring pins, the each package side is connected close to the package.
part cannot adjust to different peripherals on the fly. VBUS1 = 5.0V INPUT VBUS2 = 3.3V INPUT
VDD1 = 3.3V OUTPUT VDD2 = 3.3V INPUT
The practical result of using the ADuM4160 in a host port is VBUS1 VBUS2
that the port works at a single speed. This behavior is acceptable GND1 GND2
VDD1 VDD2
in embedded host applications; however, this type of interface is ADuM4160
PDEN SPD
not fully compliant as a general-purpose USB port. SPU PIN
UD– DD–
Isolated cable applications have a similar issue. The cable operates

08171-005
UD+ DD+
at the preset speed only; therefore, treat cable assemblies as GND1 GND2

custom applications, not general-purpose isolated cables. Figure 5. Recommended Printed Circuit Board Layout

POWER SUPPLY OPTIONS In applications involving high common-mode transients, it

In most USB transceivers, 3.3 V is derived from the 5 V USB bus is important to minimize board coupling across the isolation
through an LDO regulator. The ADuM4160 includes internal barrier. Furthermore, design the board layout such that any
LDO regulators on both the upstream and downstream sides. coupling that does occur equally affects all pins on a given
The output of the LDO is available on the VDD1 and VDD2 pins. component side. Failure to ensure this can cause voltage
In some cases, especially on the peripheral side of the isolation, differentials between pins exceeding the absolute maximum
there may not be a 5 V power supply available. The ADuM4160 ratings of the device, thereby leading to latch-up or permanent
has the ability to bypass the regulator and run on a 3.3 V supply damage.
directly. DC CORRECTNESS AND MAGNETIC FIELD
Two power pins are present on each side, VBUSx and VDDx. If 5 V IMMUNITY
is supplied to VBUSx, an internal regulator creates 3.3 V to power Positive and negative logic transitions at the isolator input
the xD+ and xD− drivers. VDDx provides external access to the cause narrow (~1 ns) pulses to be sent to the decoder via the
3.3 V supply to allow external bypass as well as bias for external transformer. The decoder is bistable and is, therefore, either set
pull-ups. If only 3.3 V is available, it can be supplied to both or reset by the pulses, indicating input logic transitions. In the
VBUSx and VDDx. This disables the regulator and powers the absence of logic transitions at the input for more than about
coupler directly from the 3.3 V supply. 12 USB bit times, a periodic set of refresh pulses indicative of
Figure 5 shows how to configure a typical application when the the correct input state are sent to ensure dc correctness at the
upstream side of the coupler receives power directly from the output. If the decoder receives no internal pulses for more than
USB bus and the downstream side is receiving 3.3 V from the about 36 USB bit times, the input side is assumed to be unpowered
peripheral power supply. The downstream side can run from a or nonfunctional, in which case the isolator output is forced to a
5 V VBUS2 power supply as well. It can be connected in the same default state (see Table 10) by the watchdog timer circuit.
manner as VBUS1 as shown in Figure 5, if needed.

Rev. D | Page 11 of 16
ADuM4160 Data Sheet
1000
The limitation on the magnetic field immunity of the ADuM4160
is set by the condition in which induced voltage in the receiving DISTANCE = 1m

MAXIMUM ALLOWABLE CURRENT (kA)

coil of the transformer is sufficiently large to either falsely set or 100

reset the decoder. The following analysis defines the conditions

under which this may occur. The 3 V operating condition of the
10
ADuM4160 is examined because it represents the most susceptible
DISTANCE = 100mm
mode of operation.
1
The pulses at the transformer output have an amplitude greater
DISTANCE = 5mm
than 1.0 V. The decoder has a sensing threshold of about 0.5 V, thus
0.1
establishing a 0.5 V margin in which induced voltages are tolerated.
The voltage induced across the receiving coil is given by
0.01
V = (−dβ/dt)∑∏rn2; n = 1, 2, … , N

08171-007
1k 10k 100k 1M 10M 100M

where: MAGNETIC FIELD FREQUENCY (Hz)

β is magnetic flux density (gauss). Figure 7. Maximum Allowable Current

for Various Current-to-ADuM4160 Spacings
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm). As shown, the ADuM4160 is extremely immune and can be
Given the geometry of the receiving coil in the ADuM4160 and affected only by extremely large currents operated at high
an imposed requirement that the induced voltage is, at most, frequency very close to the component. For the 1 MHz example
50% of the 0.5 V margin at the decoder, a maximum allowable noted, a 0.5 kA current would need to be placed 5 mm away
magnetic field is calculated, as shown in Figure 6. from the ADuM4160 to affect the operation of the component.
100 Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
MAXIMUM ALLOWABLE MAGNETIC FLUX

induce error voltages sufficiently large enough to trigger the

10
thresholds of succeeding circuitry. Take care in the layout of
such traces to avoid this possibility.
DENSITY (kguass)

1
INSULATION LIFETIME
All insulation structures eventually break down when subjected
0.1
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
0.01 voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
0.001 Devices carries out an extensive set of evaluations to determine
08171-006

1k 10k 100k 1M 10M 100M

MAGNETIC FIELD FREQUENCY (Hz)
the lifetime of the insulation structure within the ADuM4160.
Figure 6. Maximum Allowable External Magnetic Flux Density Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage. Accele-
For example, at a magnetic field frequency of 1 MHz, the max-
ration factors for several operating conditions are determined.
imum allowable magnetic field of 0.2 kgauss induces a voltage
These factors allow calculation of the time to failure at the actual
of 0.25 V at the receiving coil. This is about 50% of the sensing
working voltage. The values shown in Table 8 summarize the
threshold and does not cause a faulty output transition. Similarly,
peak voltage for 50 years of service life for a bipolar ac operating
if such an event occurs during a transmitted pulse (and is of the
condition, and the maximum CSA/VDE approved working
worst-case polarity), it reduces the received pulse from >1.0 V to
voltages. In many cases, the approved working voltage is higher
0.75 V—still well above the 0.5 V sensing threshold of the decoder.
than 50-year service life voltage. Operation at these high work-
The preceding magnetic flux density values correspond to specific ing voltages can lead to shortened insulation life in some cases.
current magnitudes at given distances from the ADuM4160
transformers. Figure 7 expresses these allowable current
magnitudes as a function of frequency for selected distances.

Rev. D | Page 12 of 16
Data Sheet ADuM4160
RATED PEAK VOLTAGE
The insulation lifetime of the ADuM4160 depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler

08171-008
0V
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8, Figure 8. Bipolar AC Waveform
Figure 9, and Figure 10 illustrate these different isolation voltage
waveforms. RATED PEAK VOLTAGE
Bipolar ac voltage is the most stringent environment. The goal

08171-009
of a 50-year operating lifetime under the ac bipolar condition
0V
determines the Analog Devices recommended maximum
Figure 9. Unipolar AC Waveform
working voltage.
In the case of unipolar ac or dc voltage, the stress on the insula-
RATED PEAK VOLTAGE
tion is significantly lower. This allows operation at higher working
voltages and still achieves a 50-year service life. The working

08171-010
voltages listed in Table 8 can be applied while maintaining the 0V
50-year minimum lifetime, provided that the voltage conforms Figure 10. DC Waveform
to either the unipolar ac or dc voltage cases. Treat any cross-
insulation voltage waveform that does not conform to Figure 9
or Figure 10 as a bipolar ac waveform and limit its peak voltage
to the 50-year lifetime voltage value listed in Table 8.
Note that the voltage presented in Figure 9 is shown as sinu-
soidal for illustration purposes only. It is meant to represent any
voltage waveform varying between 0 V and some limiting value.
The limiting value can be positive or negative, but the voltage
cannot cross 0 V.

Rev. D | Page 13 of 16
ADuM4160 Data Sheet

OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

1.27 (0.0500) 0.75 (0.0295)

BSC 45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013-AA

03-27-2007-B
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 11. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-16)
Dimensions shown in millimeters and (inches)

13.00 (0.5118)
12.60 (0.4961)

16 9
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
8
10.00 (0.3937)

0.75 (0.0295)
2.65 (0.1043) 45°
0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 SEATING
1.27 PLANE 0.33 (0.0130) 1.27 (0.0500)
(0.0500) 0.51 (0.0201)
BSC 0.31 (0.0122) 0.20 (0.0079) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013-AC

10-12-2010-A

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 12. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body (RI-16-1)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Number Number Maximum Maximum
of Inputs, of Inputs, Data Rate Propagation Maximum Package
Model 1 , 2 VDD1 Side VDD2 Side (Mbps) Delay, 5 V (ns) Jitter (ns) Temperature Range Package Description Option
ADuM4160BRWZ 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM4160BRWZ-RL 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_W RW-16
ADuM4160BRIZ 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
ADuM4160BRIZ-RL 2 2 12 70 3 −40°C to +105°C 16-Lead SOIC_IC RI-16-1
EVAL-ADUM4160EBZ Evaluation Board

1
Z = RoHS Compliant Part.
2
For all devices listed, specifications represent full speed buffer configuration.

Rev. D | Page 14 of 16
Data Sheet ADuM4160

NOTES

Rev. D | Page 15 of 16
ADuM4160 Data Sheet

NOTES

©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D08171-0-2/12(D)

Rev. D | Page 16 of 16