BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v.

2006] June 30, 2007 at 13:42 355 (1)

Sec. 7.6 Chapter Summary 355

 Biasing techniques establish the required gate voltage by means of a resistive path to the
supply rails or the output node (self-biasing).
 With a single transistor, only three amplifier topologies are possible: common-source and
common-gate stages and source followers.
 The CS stage provides a moderate voltage gain, a high input impedance, and a moderate
output impedance.
 Source degeneration improves the linearity but lowers the voltage gain.
 Source degeneration raises the output impedance of CS stages considerably.
 The CG stage provides a moderate voltage gain, a low input impedance, and a moderate
output impedance.
 The voltage gain expressions for CS and CG stages are similar but for a sign.
 The source follower provides a voltage gain less than unity, a high input impedance, and a
low output impedance, serving as a good voltage buffer.

Problems
In the following problems, unless otherwise stated, assume n Cox = 200 A=V2 ,
p Cox = 100 A=V2 ,  = 0, and VTH = 0:4 V for NMOS devices and ,0:4 V for
PMOS devices.

1. In the circuit of Fig. 7.39, determine the maximum allowable value of W=L if M1 must
VDD = 1.8 V

50 k Ω 1 kΩ

M1

Figure 7.39

remain in saturation. Assume  = 0.

2. We wish to design the circuit of Fig. 7.40 for a drain current of 1 mA. If W=L = 20=0:18,
compute R1 and R2 such that the input impedance is at least 20 k
.

VDD = 1.8 V

R1 500 Ω

M1
R2

Figure 7.40

3. Consider the circuit shown in Fig. 7.41. Calculate the maximum transconductance that M1
can provide (without going into the triode region.)
4. The circuit of Fig. 7.42 must be designed for a voltage drop of 200 mV across RS .
(a) Calculate the minimum allowable value of W=L if M1 must remain in saturation.
(b) What are the required values of R1 and R2 if the input impedance must be at least 30
k
.
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 356 (1)

356 Chap. 7 CMOS Amplifiers

VDD = 1.8 V

10 k Ω 1 kΩ

M1
100 Ω

Figure 7.41

VDD = 1.8 V

R1 500 Ω

M1
R2
RS 100 Ω

Figure 7.42

5. Consider the circuit depicted in Fig. 7.43, where W=L = 20=0:18. Assuming the current
flowing through R2 is one-tenth of ID1 , calculate the values of R1 and R2 so that ID1 = 0:5

VDD = 1.8 V

R1 500 Ω

M1
R2

RS 200 Ω

Figure 7.43

mA.
6. The self-biased stage of Fig. 7.44 must be designed for a drain current of 1 mA. If M1 is to
VDD = 1.8 V

RG RD

M1

Figure 7.44

provide a transconductance of 1=(100

), calculate the required value of RD .
7. We wish to design the stage in Fig. 7.45 for a drain current of 0.5 mA. If W=L = 50=0:18,
calculate the values of R1 and R2 such that these resistors carry a current equal to one-tenth
of ID1 .
8. Due to a manufacturing error, a parasitic resistor, RP has appeared in the circuit of Fig. 7.46.
We know that circuit samples free from this error exhibit VGS = VDS whereas defective
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 357 (1)

Sec. 7.6 Chapter Summary 357

VDD = 1.8 V

R1 2 kΩ

M1
R2

Figure 7.45

VDD = 1.8 V

10 k Ω 1 kΩ

M1 RP
20 k Ω
RS 200 Ω

Figure 7.46

samples exhibit VGS = VDS + VTH . Determine the values of W=L and RP .
9. Due to a manufacturing error, a parasitic resistor, RP has appeared in the circuit of Fig. 7.47.
We know that circuit samples free from this error exhibit VGS = VDS + 100 mV whereas

VDD = 1.8 V

30 k Ω RP 2 kΩ

M1

Figure 7.47

defective samples exhibit VGS = VDS + 50 mV. Determine the values of W=L and RP .
10. In the circuit of Fig. 7.48, M1 and M2 have lengths equal to 0.25 m and  = 0:1 V,1 .
IX IY

M1 M2
VB

Figure 7.48

Determine W1 and W2 such that IX = 2IY = 1 mA. Assume VDS 1 = VDS 2 = VB = 0:8
V. What is the output resistance of each current source?
11. An NMOS current source must be designed for an output resistance of 20 k
and an output
current of 0.5 mA. What is the maximum tolerable value of ?
12. The two current sources in Fig. 7.49 must be designed for IX = IY = 0:5 mA. If VB 1 = 1
V, VB 2 = 1:2 V,  = 0:1 V,1 , and L1 = L2 = 0:25 m, calculate W1 and W2 . Compare
the output resistances of the two current sources.
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 358 (1)

358 Chap. 7 CMOS Amplifiers

IX IY

M1 M2
V B1 V B2

Figure 7.49

13. A student mistakenly uses the circuit of Fig. 7.50 as a current source. If W=L = 10=0:25,
 = 0:1 V,1 , VB1 = 0:2 V, and VX has a dc level of 1.2 V, calculate the impedance seen at
the source of M1 .

VX
M1
V B1

Figure 7.50

14. In the circuit of Fig. 7.51, M1 and M2 serve as current sources. Calculate IX and IY if

VDD
W
2W
L L
M1 M2
IX VB IY

Figure 7.51

VB = 1 V and W=L = 20=0:25. How are the output resistances of M1 and M2 related?
15. Consider the circuit shown in Fig. 7.52, where (W=L)1 = 10=0:18 and (W=L)2 = 30=0:18.
if  = 0:1 V,1 , calculate VB such that VX = 0:9 V.

VDD = 1.8 V

M2

X
VB
M1

Figure 7.52

16. In the circuit of Fig. 7.53, (W=L)1 = 5=0:18, (W=L)2 = 10=0:18, 1 = 0:1 V,1 , and
2 = 0:15 V,1 .
(a) Determine VB such that ID1 = jID2 j = 0:5 mA for VX = 0:9 V.
(b) Now sketch IX as a function of VX as VX goes from 0 to VDD .
17. In the common-source stage of Fig. 7.54, W=L = 30=0:18 and  = 0.
(a) What gate voltage yields a drain current of 0.5 mA? (Verify that M1 operates in satura-
tion.)
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 359 (1)

Sec. 7.6 Chapter Summary 359

VDD = 1.8 V

M2
IX

VB
M1 VX

Figure 7.53

VDD = 1.8 V

RD 2 kΩ
Vout
V in M1

Figure 7.54

(b) With such a drain bias current, calculate the voltage gain of the stage.
18. The circuit of Fig. 7.54 is designed with W=L = 20=0:18,  = 0, and ID = 0:25 mA.
(a) Compute the required gate bias voltage.
(b) With such a gate voltage, how much can W=L be increased while M1 remains in satura-
tion? What is the maximum voltage gain that can be achieved as W=L increases?
19. We wish to design the stage of Fig. 7.55 for a voltage gain of 5 with W=L  20=0:18.

VDD = 1.8 V

RD
Vout
V in M1

Figure 7.55

Determine the required value of RD if the power dissipation must not exceed 1 mW.
20. The CS stage of Fig. 7.56 must provide a voltage gain of 10 with a bias current of 0.5 mA.
Assume 1 = 0:1 V,1 , and 2 = 0:15 V,1 .

VDD = 1.8 V

Vb M2
Vout
V in M1

Figure 7.56

(a) Compute the required value of (W=L)1 .

(b) if (W=L)2 = 20=0:18, calculate the required value of VB .
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 360 (1)

360 Chap. 7 CMOS Amplifiers

21. In the stage of Fig. 7.56, M2 has a long length so that 2  1 . Calculate the voltage gain
if 1 = 0:1 V,1 , (W=L)1 = 20=0:18, and ID = 1 mA.
22. The circuit of Fig. 7.56 is designed for a bias current of I1 with certain dimensions for M1
and M2 . If the width and the length of both transistors are doubled, how does the voltage gain
change? Consider two cases: (a) the bias current remains constant, or (b) the bias current is
doubled.
23. Explain which one of the topologies shown in Fig. 7.57 is preferred.
VDD VDD

Vb M2 V in M2
Vout Vout
V in M1 Vb M1

(a) (b)

Figure 7.57

24. The CS stage depicted in Fig. 7.58 must achieve a voltage gain of 15 at a bias current of 0.5

VDD = 1.8 V

V in M2
Vout
Vb M1

Figure 7.58

mA. If 1 = 0:15 V,1 and 2 = 0:05 V,1 , determine the required value of (W=L)2 .
25. We wish to design the circuit shown in Fig. 7.59 for a voltage gain of 3. If (W=L)1 =
VDD = 1.8 V

M2
Vout
V in M1

Figure 7.59

20=0:18, determine (W=L)2 . Assume  = 0.

26. In the circuit of Fig. 7.59, (W=L)1 = 10=0:18 and ID1 = 0:5 mA.
(a) If  = 0, determine (W=L)2 such that M1 operates at the edge of saturation.
(b) Now calculate the voltage gain.
(c) Explain why this choice of (W=L)2 yields the maximum gain.
27. The CS stage of Fig. 7.59 must achieve a voltage gain of 5.
(a) If (W=L)2 = 2=0:18, compute the required value of (W=L)1 .
(b) What is the maximum allowable bias current if M1 must operate in saturation?
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 361 (1)

Sec. 7.6 Chapter Summary 361

VDD VDD VDD

M2 Vb M2 M3 Vb M2
Vout Vout Vout
V in M1 V in M1 V in M1 M3

(a) (b) (c)

VDD VDD
VDD
V in M2 M2
V in M2
Vout RD
Vout
Vb M1 M3 Vout
Vb M1 M3
V in M1

(d) (e) (f)

Figure 7.60

28. If  6= 0, determine the voltage gain of the stages shown in Fig. 7.60.
29. In the circuit of Fig. 7.61, determine the gate voltage such that M1 operates at the edge of
saturation. Assume  = 0.
VDD = 1.8 V

RD
Vout
V in M1
RS

Figure 7.61

30. The degenerated CS stage of Fig. 7.61 must provide a voltage gain of 4 with a bias current
of 1 mA. Assume a drop of 200 mV across RS and  = 0.
(a) If RD = 1 k
, determine the required value of W=L. Does the transistor operate in
saturation for this choice of W=L?
(b) If W=L = 50=0:18, determine the required value of RD . Does the transistor operate in
saturation for this choice of RD ?
31. Consider a degenerated CS stage with  > 0. Assuming gm rO  1, calculate the voltage
gain of the circuit.
32. Calculate the voltage gain of the circuits depicted in Fig. 7.62. Assume  = 0.
33. Determine the output impedance of each circuit shown in Fig. 7.63. Assume  6= 0.
34. The CS stage of Fig. 7.64 carries a bias current of 1 mA. If RD = 1 k
and  = 0:1 V,1 ,
compute the required value of W=L for a gate voltage of 1 V. What is the voltage gain of the
circuit?
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 362 (1)

362 Chap. 7 CMOS Amplifiers

VDD VDD VDD

M2 M2 RD
Vout RD Vout
V in M1 Vout V in M1 M2 Vb
V in M1
M3 I1

M3

(a) (b) (c)

VDD VDD

RD Vb M2
Vout
V in M1
V in M1
Vout
M3
M2 Vb

(d) (e)
Figure 7.62

35. Repeat Problem 34 with  = 0 and compare the results.

36. An adventurous student decides to try a new circuit topology wherein the input is applied to
the drain and the output is sensed at the source (Fig. 7.65). Assume  6= 0, determine the
voltage gain of the circuit and discuss the result.
37. In the common-source stage depicted in Fig. 7.66, the drain current of M1 is defined by the
ideal current source I1 and remains independent of R1 and R2 (why?). Suppose I1 = 1 mA,
RD = 500
,  = 0, and C1 is very large.
(a) Compute the value of W=L to obtain a voltage gain of 5.
(b) Choose the values of R1 and R2 to place the transistor 200 mV away from the triode
region while R1 + R2 draws no more than 0.1 mA from the supply.
(c) With the values found in (b), what happens if W=L is twice that found in (a)? Consider
both the bias conditions (e.g., whether M1 comes closer to the triode region) and the voltage
gain.
38. Consider the CS stage shown in Fig. 7.67, where I1 defines the bias current of M1 and C1 is
very large.
(a) If  = 0 and I1 = 1 mA, what is the maximum allowable value of RD ?
(b) With the value found in (a), determine W=L to obtain a voltage gain of 5.
39. The common-gate stage shown in Fig. 7.68 must provide a voltage gain of 4 and an input
impedance of 50
. If ID = 0:5 mA, and  = 0, determine the values of RD and W=L.
40. Suppose in Fig. 7.68, ID = 0:5 mA,  = 0, and Vb = 1 V. Determine the values of W=L
and RD for an input impedance of 50
and maximum voltage gain (while M1 remains in
saturation).
41. A CG stage with a source resistance of RS employs a MOSFET with  > 0. Assuming
gm rO , calculate the voltage gain of the circuit.
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 363 (1)

Sec. 7.6 Chapter Summary 363

VDD
R out R out

V in M1 V in M1 M2 Vb

M2 Vb
I1

(a) (b)
VDD
R out
V in M2
Vb M2
Vb M1 M3
V in M1 M3
R out

(c) (d)

Figure 7.63

VDD = 1.8 V

RD
Vout
V in M1

Figure 7.64

V in M1
VB
Vout

RS

Figure 7.65

42. The CG stage depicted in Fig. 7.69 must provide an input impedance of 50
and an output
impedance of 500
. Assume  = 0.
(a) What is the maximum allowable value of ID ?
(b) With the value obtained in (a), calculate the required value of W=L.
(c) Compute the voltage gain.
43. The CG amplifier shown in Fig. 7.70 is biased by means of I1 = 1 mA. Assume  = 0 and
C1 is very large.
(a) What value of RD places the transistor M1 100 mV away from the triode region?
(b) What is the required W=L if the circuit must provide a voltage gain of 5 with the value
of RD obtained in (a)?
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 364 (1)

364 Chap. 7 CMOS Amplifiers

VDD = 1.8 V

R1 RD
C1 Vout
M1
V in R2
I1 C1

Figure 7.66

VDD = 1.8 V

R1 RD
C1 Vout
M1
V in
I1 C1

Figure 7.67

VDD = 1.8 V

RD
Vout

M1 Vb
V in

Figure 7.68

VDD = 1.8 V

RD
Vout

M1
V in

Figure 7.69

44. Determine the voltage gain of each stage depicted in Fig. 7.71. Assume  = 0.
45. Consider the circuit of Fig. 7.72, where a common-source stage (M1 and RD1 ) is followed
by a common-gate stage (M2 and RD2 ).
(a) Writing vout =vin = (vX =vin )(vout =vX ) and assuming  = 0, compute the overall
voltage gain.
(b) Simplify the result obtained in (a) if RD1 ! 1. Explain why this result is to be expected.
46. Repeat Problem 45 for the circuit shown in Fig. 7.73.
47. Assuming  = 0, calculate the voltage gain of the circuit shown in Fig. 7.74. Explain why
this stage is not a common-gate amplifier.
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 365 (1)

Sec. 7.6 Chapter Summary 365

VDD = 1.8 V

RD
Vout

M1
C1

I1
V in

Figure 7.70

VDD VDD VDD

M2 M2 M2
Vout RD Vout

M1 Vb Vout M1 Vb
V in V in
RS M1 Vb RS
V in R1

(a) (b) (c)

VDD V in VDD
Vb M3 M2 Vb M1 M2
RD Vout
RD
Vout

M1 Vb I1
V in

(d) (e)

Figure 7.71

48. Calculate the voltage gain of the stage depicted in Fig. 7.75. Assume  = 0 and the capaci-
tors are very large.
49. The source follower shown in Fig. 7.76 is biased through RG . Calculate the voltage gain if
W=L = 20=0:18 and  = 0:1 V,1 .
50. We wish to design the source follower shown in Fig. 7.77 for a voltage gain of 0.8. If W=L =
30=0:18 and  = 0, determine the required gate bias voltage.
51. The source follower of Fig. 7.77 is to be designed with a maximum bias gate voltage of 1.8
V. Compute the required value of W=L for a voltage gain of 0.8 if  = 0.
52. The source follower depicted in Fig. 7.78 employs a current source. Determine the values of
I1 and W=L if the circuit must provide an output impedance less than 100
with VGS = 0:9
V. Assume  = 0.
53. The circuit of Fig. 7.78 must exhibit an output impedance of less than 50
with a power
budget of 2 mW. Determine the required value of W=L. Assume  = 0.
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 366 (1)

366 Chap. 7 CMOS Amplifiers

VDD
R D2
R D1
Vout

M2 Vb
X
V in M1

Figure 7.72

VDD
R D2
V in M1 Vout

M2 Vb

X
R D1

Figure 7.73

VDD

I1

Vout

RG
M1
V in

Figure 7.74

54. We wish to design the source follower of Fig. 7.79 for a voltage gain of 0.8 with a power
budget of 3 mW. Compute the required value of W=L. Assume C1 is very large and  = 0.
55. Determine the voltage gain of the stages shown in Fig. 7.80. Assume  6= 0.
56. Consider the circuit shown in Fig. 7.81, where a source follower (M1 and I1 ) precedes a
common-gate stage (M2 and RD ).
(a) Writing vout =vin = (vX =vin )(vout =vX ), compute the overall voltage gain.
(b) Simplify the result obtained in (a) if gm1 = gm2 .
Design Problems
In the following problems, unless otherwise stated, assume  = 0.
57. Design the CS stage shown in Fig. 7.82 for a voltage gain of 5 and an output impedance of 1
k
. Bias the transistor so that it operates 100 mV away from the triode region. Assume the
capacitors are very large and RD = 10 k
.
58. The CS amplifier of Fig. 7.82 must be designed for a voltage gain of 5 with a power budget
of 2 mW. If RD ID = 1 V, determine the required value of W=L. Make the same assumptions
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 367 (1)

Sec. 7.6 Chapter Summary 367

VDD
RD
Vout
C1 R3
R2
R4 M1
V in
R1 CB

Figure 7.75

VDD = 1.8 V
RG 50 k Ω
V in M1
Vout
1 kΩ RS

Figure 7.76

VDD = 1.8 V

V in M1
Vout
500 Ω RS

Figure 7.77

VDD = 1.8 V

V in M1
Vout
I1

Figure 7.78

as those in Problem 57.

59. We wish to design the CS stage of Fig. 7.82 for maximum voltage gain but with W=L 
50=0:18 and a maximum output impedance of 500
. Determine the required current. Make
the same assumptions as those in Problem 57.
60. The degenerated stage depicted in Fig. 7.83 must provide a voltage gain of 4 with a power
budget of 2 mW while the voltage drop across RS is equal to 200 mV. If the overdrive voltage
of the transistor must not exceed 300 mV and R1 + R2 must consume less than than 5% of
the allocated power, design the circuit. Make the same assumptions as those in Problem 57.
61. Design the circuit of Fig. 7.83 for a voltage gain of 5 and a power budget of 6 mW. Assume
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 368 (1)

368 Chap. 7 CMOS Amplifiers

VDD = 1.8 V

V in M1
C1
Vout
I1 50 Ω RL

Figure 7.79

VDD VDD VDD

V in M1 V in M1 V in M1
Vout Vout Vout

RS Vb M2 M2
Vb M2 RS

(a) (b) (c)

VDD VDD
VDD
V in M1 V b2 M3
Vb M3 M1
Vout
R1 V b1 M2
Vout
Vout
M2 V in M2
R2 V in M1

(d) (e) (f)

Figure 7.80

VDD

RD
Vout
V in M1 X M2 Vb

I1

Figure 7.81

the voltage drop across RS is equal to the overdrive voltage of the transistor and RD =
200
.
62. The circuit shown in Fig. 7.84 must provide a voltage gain of 6, with CS serving as a low
impedance at the frequencies of interest. Assuming a power budget of 2 mW and an input
impedance of 20 k
, design the circuit such that M1 operates 200 mV away from the triode
region. Select the values of C1 and CS so that their impedance is negligible at 1 MHz.
63. In the circuit of Fig. 7.85, M2 serves as a current source. Design the stage for a voltage
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 369 (1)

Sec. 7.6 Chapter Summary 369

VDD = 1.8 V

RG RD
C2
C1 Vout
V in M1

Figure 7.82

VDD = 1.8 V

R1 RD
C1 Vout
M1
V in R2
RS

Figure 7.83

VDD = 1.8 V

R1 RD
C1 Vout
M1
V in
RS CS

Figure 7.84

VDD = 1.8 V

Vb M2
Vout
V in M1

Figure 7.85

gain of 20 and a power budget of 2 mW. Assume  = 0:1 V,1 for both transistors and
the maximum allowable level at the output is 1.5 V (i.e., M2 must remain in saturation if
Vout  1:5 V).
64. Consider the circuit shown in Fig. 7.86, where CB is very large and n = 0:5p = 0:1 V,1 .

(a) Calculate the voltage gain.

(b) Design the circuit for a voltage gain of 15 and a power budget of 3 mW. Assume RG 
10(rO1 jjrO2 ) and the dc level of the output must be equal to VDD =2.
65. The CS stage of Fig. 7.87 incorporates a degenerated PMOS current source. The degener-
ation must raise the output impedance of the current source to about 10rO1 such that the
voltage gain remains nearly equal to the intrinsic gain of M1 . Assume  = 0:1 V,1 for both
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 370 (1)

370 Chap. 7 CMOS Amplifiers

VDD = 1.8 V
CB
M2
RG
Vout

V in M1

Figure 7.86

VDD = 1.8 V

RS
Vb M2
Vout
V in M1

Figure 7.87

transistors and a power budget of 2 mW.

(a) If VB = 1 V, determine the values of (W=L)2 and RS so that the impedance seen looking
into the drain of M2 is equal to 10rO1 .
(b) Determine (W=L)1 to achieve a voltage gain of 30.
66. Assuming a power budget of 1 mW and an overdrive of 200 mV for M1 , design the circuit
shown in Fig. 7.88 for a voltage gain of 4.

VDD = 1.8 V

M2
Vout
V in M1

Figure 7.88

67. Design the common-gate stage depicted in Fig. 7.89 for an input impedance of 50
and a
voltage gain of 5. Assume a power budget of 3 mW.
VDD = 1.8 V

RD
Vout

M1
V in
I1

Figure 7.89
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 371 (1)

Sec. 7.6 Chapter Summary 371

68. Design the circuit of Fig. 7.90 such that M1 operates 100 mV away from the triode region
while providing a voltage gain of 4. Assume a power budget of 2 mW.
VDD = 1.8 V

RD
Vout

M1
V in
RS

Figure 7.90

69. Figure 7.91 shows a self-biased common-gate stage, where RG  10RD and CG serves as a
VDD = 1.8 V

RD
V out
RG
M1
V in CG
RS

Figure 7.91

low impedance so that the voltage gain is still given by gm RD . Design the circuit for a power
budget of 5 mW and a voltage gain of 5. Assume RS  10=gm so that the input impedance
remains approximately equal to 1=gm .
70. Design the CG stage shown in Fig. 7.92 such that it can accommodate an output swing of 500

VDD = 1.8 V

RD
V out R2

M1
V in R1
RS

Figure 7.92

mVpp , i.e., Vout can fall below its bias value by 250 mV without driving M1 into the triode
region. Assume a voltage gain of 4 and an input impedance of 50
. Select RS  10=gm
and R1 + R2 = 20 k
. (Hint: since M1 is biased 250 mV away from the triode region, we
have RS ID + VGS , VTH + 250 mV = VDD , ID RD .)
71. Design the source follower depicted in Fig. 7.93 for a voltage gain of 0.8 and a power budget
of 2 mW. Assume the output dc level is equal to VDD =2 and the input impedance exceeds
10 k
.
72. Consider the source follower shown in Fig. 7.94. The circuit must provide a voltage gain of
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 372 (1)

372 Chap. 7 CMOS Amplifiers

VDD = 1.8 V
RG
V in M1
Vout
RS

Figure 7.93

VDD = 1.8 V
RG
V in M1
C1
X Vout
RS 50 Ω RL

Figure 7.94

0.8 at 100 MHz while consuming 3 mW. Design the circuit such that the dc voltage at node
X is equal to VDD =2. Assume the input impedance exceeds 20 k
.
73. In the source follower of Fig. 7.95, M2 serves as a current source. The circuit must operate
VDD = 1.8 V

V in M1
Vout
Vb M2

Figure 7.95

with a power budget of 3 mW, a voltage gain of 0.9, and a minimum allowable output of 0.3
V (i.e., M2 must remain in saturation if VDS 2  0:3 V). Assuming  = 0:1 V,1 for both
transistors, design the circuit.
SPICE Problems
In the following problems, use the MOS models and source/drain dimensions given in Ap-
pendix A. Assume the substrates of NMOS and PMOS devices are tied to ground and VDD ,
respectively.
74. In the circuit of Fig. 7.96, I1 is an ideal current source equal to 1 mA.
VDD = 1.8 V

I1
10 k Ω
Vout
1 kΩ W
V in ( (1
C1 L
M1
Figure 7.96

(a) Using hand calculations, determine (W=L)1 such that gm1 = (100
),1 .
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 373 (1)

Sec. 7.6 Chapter Summary 373

(b) Select C1 for an impedance of  100

( 1 k
) at 50 MHz.
(c) Simulate the circuit and obtain the voltage gain and output impedance at 50 MHz..
(d) What is the change in the gain if I1 varies by 20%?
75. The source follower of Fig. 7.97 employs a bias current source, M2 .
VDD = 1.8 V
M1
V in 20
0.18
Vout
M2
10
0.8 V
0.18

Figure 7.97

(a) What value of Vin places M2 at the edge of saturation?

(b) What value of Vin places M1 at the edge of saturation?
(c) Determine the voltage gain if Vin has a dc value of 1.5 V.
(d) What is the change in the gain if Vb changes by 50 mV?
76. Figure 7.98 depicts a cascade of a source follower and a common-gate stage. Assume Vb =
1:2 V and (W=L)1 = (W=L)2 = 10 m=0:18 m.
VDD

1 kΩ

Vout

V in M1 M2 Vb

1 mA

Figure 7.98

(a) Determine the voltage gain if Vin has a dc value of 1.2 V.

(b) Verify that the gain drops if the dc value of Vin is higher or lower than 1.2 V.
(c) What dc value at the input reduces the gain by 10% with respect to that obtained in (a)?
77. Consider the CS stage shown in Fig. 7.99, where M2 operates as a resistor.

VDD = 1.8 V
M2
W2
0.18
Vout
V in 10
0.18
M1
Figure 7.99

(a) Determine W2 such that an input dc level of 0.8 V yields an output dc level of 1 V. What
is the voltage gain under these conditions?
(b) What is the change in the gain if the mobility of the NMOS device varies by 10%? Can
you explain this result using the expressions derived in Chapter 6 for the transconductance?
BR Wiley/Razavi/Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 374 (1)

374 Chap. 7 CMOS Amplifiers

78. Repeat Problem 77 for the circuit illustrated in Fig. 7.100 and compare the sensitivities to
the mobility.
VDD = 1.8 V
W2
0.18
M2
Vout
V in 10
0.18
M1
Figure 7.100