ULN2803A Darlington Transistor Arrays: 1 Features 3 Description
ULN2803A Darlington Transistor Arrays: 1 Features 3 Description
ULN2803A Darlington Transistor Arrays: 1 Features 3 Description
ULN2803A
SLRS049H – FEBRUARY 1997 – REVISED FEBRUARY 2017
Logic Diagram
1 18
1B 1C
2 17
2B 2C
3 16
3B 3C
4 15
4B 4C
5 14
5B 5C
6 13
6B 6C
7 12
7B 7C
8 11
8B 8C
10
COM
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ULN2803A
SLRS049H – FEBRUARY 1997 – REVISED FEBRUARY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................... 9
2 Applications ........................................................... 1 8.4 Device Functional Modes.......................................... 9
3 Description ............................................................. 1 9 Application and Implementation ........................ 10
4 Revision History..................................................... 2 9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 10 Power Supply Recommendations ..................... 12
6.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 12
6.2 ESD Ratings.............................................................. 4 11.1 Layout Guidelines ................................................. 12
6.3 Recommended Operating Conditions....................... 4 11.2 Layout Example .................................................... 12
6.4 Thermal Information .................................................. 4 12 Device and Documentation Support ................. 13
6.5 Electrical Characteristics........................................... 5 12.1 Receiving Notification of Documentation Updates 13
6.6 Switching Characteristics .......................................... 5 12.2 Community Resources.......................................... 13
6.7 Typical Characteristics .............................................. 5 12.3 Trademarks ........................................................... 13
7 Parameter Measurement Information .................. 6 12.4 Electrostatic Discharge Caution ............................ 13
12.5 Glossary ................................................................ 13
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ......................................... 9
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
DW Package
18-Pin SOIC
Top View
1B 1 18 1C
2B 2 17 2C
3B 3 16 3C
4B 4 15 4C
5B 5 14 5C
6B 6 13 6C
7B 7 12 7C
8B 8 11 8C
GND 9 10 COM
Not to scale
Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
1B 1
2B 2
3B 3
4B 4
I Channel 1 through 8 Darlington base input
5B 5
6B 6
7B 7
8B 8
1C 18
2C 17
3C 16
4C 15
O Channel 1 through 8 Darlington collector output
5C 14
6C 13
7C 12
8C 11
GND 9 — Common emitter shared by all channels (typically tied to ground)
COM 10 I/O Common cathode node for flyback diodes (required for inductive loads)
6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted) (1)
MIN MAX UNIT
VCE Collector-emitter voltage 50 V
(2)
VI Input voltage 30 V
Peak collector current 500 mA
I(clamp) Output clamp current 500 mA
Total substrate-terminal current –2.5 A
TJ Junction temperature –65 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the emitter/substrate terminal GND.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
μ μ
μ
μ
Figure 1. Collector-Emitter Saturation Voltage vs Collector Figure 2. Collector-Emitter Saturation Voltage vs Total
Current (One Darlington) Collector Current (Two Darlingtons in Parallel)
IC
ICEX II(off)
Open
II IC
VI Open VI
VCE
Open
VCE
IF
VF
Open
RL = 163 Ω
Pulse
Generator Output
(see Note A)
CL = 15 pF
(see Note B)
Test Circuit
<5 ns <10 ns
VIH
Input 90% 90% (see Note C)
50% 50%
10% 10% 0
0.5 µs
tPHL tPLH
VOH
50% 50%
Output
Voltage Waveforms
A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. VIH = 3 V
Input
2 mH
163 Ω
Pulse
Generator Output
(see Note A)
CL = 15 pF
(see Note B)
Test Circuit
<5 ns <10 ns
VIH
Input 90% 90% (see Note C)
1.5 V 1.5 V
10% 10% 0
40 µs
VOH
Output
Voltage Waveforms
A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. VIH = 3 V
8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to its
integration of 8 Darlington transistors that are capable of sinking up to 500 mA and wide GPIO range capability.
The ULN2803A is comprised of eight high voltage, high current NPN Darlington transistor pairs. All units feature
a common emitter and open collector outputs. To maximize their effectiveness, these units contain suppression
diodes for inductive loads. The ULN2803A has a series base resistor to each Darlington pair, thus allowing
operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The ULN2803A offers
solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and LEDs.
Applications requiring sink currents beyond the capability of a single output may be accommodated by paralleling
the outputs.
COM
2.7 kΩ Output C
Input B
7.2 kΩ 3 kΩ
E
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
ULN2803A
IN1 OUT1
IN2 OUT2
3.3 V Logic
IN3 OUT3
3.3 V Logic
IN4 OUT4
IN5 OUT5
IN6 OUT6
3.3 V Logic
IN7 OUT7
GND COM
where
• N is the number of channels active together.
• VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT) (2)
To ensure the reliability of ULN2803A and the system, the on-chip power dissipation must be lower that or equal
to the maximum allowable power dissipation (PD) dictated by Equation 3.
PD(MAX) =
(T J(MAX) - TA )
qJA
where
• TJ(MAX) is the target maximum junction temperature.
• TA is the operating ambient temperature.
• θJA is the package junction to ambient thermal resistance. (3)
TI recommends to limit ULN2803A IC’s die junction temperature to <125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
13 14
12
11 12
10
9 10
Output voltage - V
Output voltage - V
8
8
7
6
6
5
4 4
3
2 2
1
0 0
-0.004 0 0.004 0.008 0.012 0.016 -0.004 0 0.004 0.008 0.012 0.016
Time (s) D001
Time (s) D001
Figure 13. Output Response With Activation of Coil (Turn Figure 14. Output Response With De-Activation of Coil
On) (Turn Off)
11 Layout
1B 1 18 1C
2B 2 17 2C
3B 3 16 3C
4B 4 15 4C
5B 5 14 5C
6B 6 13 6C
7B 7 12 7C
8B 8 11 8C
GND 9 10 COM
GND
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ULN2803ADW ACTIVE SOIC DW 18 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A
& no Sb/Br)
ULN2803ADWG4 ACTIVE SOIC DW 18 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A
& no Sb/Br)
ULN2803ADWR ACTIVE SOIC DW 18 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A
& no Sb/Br)
ULN2803ADWRG4 ACTIVE SOIC DW 18 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2019
Pack Materials-Page 2
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