Control of a Modular Multi-level Converter

STATCOM for Low Voltage Ride-Through

Condition
O.J.K Oghorada Li Zhang
School of Electronic/Electrical Engineering
University of Leeds
Leeds, United Kingdom
el11oo@leeds.ac.uk, l.zhang@leeds.ac.uk

Abstract This paper presents a simulation study on the voltage level required without the use of step-up transformers
implementation of the Single Star Flying Capacitor Converter [6]. In addition it gives good waveform quality at low
Modular Multi-level Cascaded Converter (MMCC-SSFCC) as a
switching frequency. The switching and clamping devices in
STATCOM operating under voltage sag condition. This paper
proposes a cluster balancing control, using a zero sequence MMCC are rated at module power and voltage levels,
voltage injection technique for the SSFCC-STATCOM operating enabling the use of lower rated components operating under
either as a reactive compensator under Low Voltage Ride reduced voltage stress.
Through condition (LVRT) or unbalanced current compensator. It has been shown that the MMCC is capable of
This control strategy enables the STATCOM system to compensating reactive power under balanced conditions [7].
compensate for both positive sequence reactive and negative However, with the occurrence of a phase voltage sag, the
sequence currents. Not only does it compensate for the load
demands, but also keep the module DC-link and flying capacitor
voltages of the power network become asymmetrical, causing
voltages at their rated values. the MMCC module capacitor voltages drifting away from
their nominal values, if not properly monitored results to
Keywords voltage sag; flying capacitor converter; modular STATCOM failure [8]. It is of paramount importance that the
multilevel cascaded converter; Static synchronous compensator STATCOM is able to withstand the adverse effect of voltage
unbalance at the point of operation. Authors in [9] presented a
×ò INTRODUCTION control scheme for ensuring proper operation of STATCOM
In power distribution systems, voltage unbalance can take under condition of low voltage ride through (LVRT), but the
several forms including unequal magnitudes, presence of STATCOM topology used was a two-level PWM controlled
harmonics and unequal phase shift between voltages. This voltage source converter. Authors in [8] and [10] proposed a
occurs as a result of; uneven distribution of loads such as LVRT technique for an MMCC-SSBC based STATCOM
single phase traction drives and electric locomotives; open which can prevent module capacitor voltage drifts by
wye and delta transformer banks; asymmetric transmission injection of a zero sequence voltage to each phase limb.
impedances; and blown fuses in three phase capacitor banks This paper presents a new STATCOM with a different
[1]. These unbalanced voltages in power system result in sags, topology to the MMCC-SSBC, known as the Single Star
swells and interruptions [2]. This unbalance Voltage has an Flying Capacitor Converter-based MMCC (MMCC-SSFCC).
adverse effect on equipment, system stability and power Each of the three phase limbs of the MMCC-SSFCC
quality of power distribution system [3]. This in turn increases comprises a chained modules of three-level Full-bridge
losses, reduces efficiency and decrease life span of equipment. Flying Capacitor Converter (3L-FCC) synthesizing three
The Static Synchronous Compensator (STATCOM) plays a voltage levels (0, ±0.5VDC and ±VDC)[11]. Each 3L-FCC
paramount role in reactive power control and voltage consist of an outer dc-bus capacitor CDC1, two flying
regulation in power systems. This has also been applied to capacitors Ca, Cb and eight switch-diode pairs. The voltage on
overcome the problems of unbalance[4]. Recent development CDC1 defines the module voltage rating as VDC and this is twice
in the medium and high voltage power converters such as the the voltage rating of two flying capacitors, likewise their
Modular Multilevel Cascaded Converter using stacked H- capacitance. This configuration offers benefit of more
bridge cell configuration (MMCC-SSBC) [5] enables switching states and voltage levels per module. This MMCC-
STATCOM application in transmission network. With its SSFCC-based STATCOM has been investigated for balanced
modular nature the topology offers a number of benefits such voltage application [11], but, to the
as scalability by using its modular nature to extend to any work has been reported on its operation under voltage sag
conditions. This paper shows that this STATCOM is capable

978-1-5090-3474-1/16/$31.00 ©2016 IEEE 3691

of operating under grid voltage sag conditions, providing
LVRT and eliminating the effects of voltage sag on the load,
whilst maintaining the module capacitor voltage balance.
××ò DC VOLTAGE IMBALANCE IN MODULAR
MULTILEVEL CASCASED FLYING CAPACITOR
CONVERTER
Fig.1 shows the circuit configuration of a three phase
STATCOM using the MMCC-SSFCC.
Under balanced operation this MMCC-SSFCC-based
STATCOM is able to mitigate the reactive power, but when
voltage sag occurs it faces challenging issue. This is because
the average active power flowing through the converter is non-
Fig. 1. Circuit configuration of the three phase MMCC-SSFCC
zero during voltage unbalance, but the module capacitors for
STATCOM.
the chained modules do not allow circulating current flowing
within the converter phase limbs, resulting in module DC The first and second terms on the right-hand-side (RHS) of
voltage imbalance. the above three expressions contain positive and negative
The non-zero active power can be analyzed as follows; sequence terms solely. These terms contribute the zero
Under unbalanced operation, the PCC voltages and average active powers which are balanced. This implies that
compensation reference currents are written in phasor form as: the average three phase power flowing through the
va V p Vn STATCOM is zero. However the RHS third and last terms are
vp vn
cross products of positive sequence and negative sequence
2 2 (1) voltage and current respectively, they result in undesired non-
vb Vp ( vp ) Vn ( vn )
3 3 zero average active power flowing through individual phases.
2 2 This causes the DC link and flying capacitor voltages of each
vc Vp ( ) Vn ( )
vp
3
vn
3 module drifting away from their nominal values. Hence,
preventing the STATCOM to function properly as a reactive
i ra
*
IP In power compensator.
iP in
(2) An effective approach to overcome this problem involves
* 2 2
i rb I P ( iP ) I n ( in ) adding a common zero-sequence voltage to each of the three
3 3 converter-limb voltages. If accurately estimated and applied to
* 2 2 each phase limb, this zero-sequence voltage cancels out the
i rc I P ( iP ) I n ( in )
3 3 effect of the cross component terms of each phase active
Thus the total per phase active powers are expressed as: power. Thus the control strategy for the MMCC-SSFCC-based
pa [(V p vp Vn vn )( I P iP In in )] STATCOM include the following:
V P I P cos( vP iP ) V n I n cos( vn in ) 1) DC link/cluster voltage balancing control
V P I n cos(
2) Zero-sequence voltage estimation
vP in ) V n I P cos( vn iP )
3) Converter reference voltage estimation
2 2
(V P ( vP ) V n ( vn )) A. DC link/Cluster Voltage Balancing Control
3 3
pb [ ]
2 2 The active power flowing through each phase limb (Pa, Pb
(I P ( iP ) I n ( in )) and Pc) comprises two elements; the positive sequence active
3 3
power owing to converter loss and negative sequence active
V P I P cos( vP iP ) Vn I n cos( vn in ) VP I n
power due to unbalanced voltage. Both must be compensated
2 2 to prevent the phase limb voltages (module DC-link and flying
cos( vP in ) V n I p cos( vn ip )
3 3 capacitor voltages) deviating from their rated values. For the
2 2 converter losses, the DC-bus voltage feedback control is
(VP ( vP ) Vn ( vn ))
3 3 applied as illustrated in Fig. 2. For MMCC-SSFCC topology
pc [ ] obtaining the average value, VDC_avg, of the three phase-limb
2 2
(I P ( iP ) I n ( in )) DC-link voltages requires calculating per phase limb average
3 3 DC voltage. This can be done by averaging the measured
VP I P cos( vP iP ) Vn I n cos( vn in ) VP I n individual module voltages within the corresponding phase
2 2 chain, so the DC-link average voltage for each phase is given
cos( vP in ) Vn I p cos( vn ip ) as:
3 3
(3)

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 1
nmp pa [(V P VP Vn Vn V0 0 )( I P iP In in )]
V DC _(abc) V DC _ i ( abc) (4)
n mp V P I P cos( VP iP ) V P I n cos( VP in )
i 1
V n I P cos( ) Vn I n cos( )
where nmp denotes the number of modules per phase and the Vn iP Vn in

average voltage of the three phase-limb VDC_avg can be V0 I P cos( 0 iP ) V0 I n cos( 0 in )

evaluated as: 2 2
(VP ( ) Vn ( Vn ) V0 0 )
VDC _ a VDC _ b VDC _ c VP
3 3
VDC _ avg (5) pb [ ]
3 2 2
(I P ( iP ) I n ( in ))
Applying the average voltage value and the required 3 3
nominal voltage VDC_ref to the DC-bus voltage feedback P+I 2
VP I P cos( iP ) VP I n cos( VP )
controller (Fig. 2), the current Id_ref is evaluated for active VP in
3
power compensation. 2
For compensating the effect of the second element - the Vn I n cos( Vn in ) Vn I p cos( Vn ip )
3
negative sequence active power relies on implementing a 2 2
cluster voltage balancing control scheme since it is this power V0 I P cos( 0 iP ) V0 I n cos( 0 in )
3 3
flowing in and out of each converter phase limb that causes
2 2
the imbalance of the phase limb DC-link voltages. As shown (VP ( VP ) Vn ( Vn ) V0 0 )
in Fig. 3, this cluster voltage balancing control consists of 3 3
pc [ ]
three PI regulators respectively for each phase limb. The 2 2
(I P ( iP ) In ( in ))
average voltage VDC_avg evaluated in (5) and the individual 3 3
phase average voltages (i.e. VDC_a, VDC_b and VDC_c) as derived 2
V P I P cos( ) V P I n cos( )
in (4) are applied in generating the phase cluster powers. VP iP VP in
3
These cluster powers are further applied to determine the zero 2
sequence voltage to be injected. V n I n cos( Vn in ) V n I p cos( Vn ip )
3
B. Zero Sequence Voltage Estimation 2 2
V 0 I P cos( 0 iP ) V 0 I n cos( 0 in )
Having evaluated the active power, Pa, Pb and Pc flowing 3 3
through each phase limb, a zero sequence voltage vo can be (6)
derived. This follows the principle that the sum of active To determine the amplitude and phase angle of vo, any two
power caused by the injected zero sequence voltage and that of three power equations in (6) can be used. Assuming the first
of existing active power expressed by (3) should balance the two are selected they can be written as:
cluster powers. Thus, the equations for power across each V0 I P cos( 0 iP ) VP I P cos( VP iP ) VP I n cos( VP in )
pa
phase are written as: V0 I n cos( 0 in )
Vn In cos( Vn in ) Vn I p cos( Vn ip )
2 2
V0 I P cos( 0 iP ) [VP I P cos( VP iP ) VP I n cos( VP in )
3 3
pb
2 2
V0 I n cos( 0 in ) Vn In cos( Vn in ) Vn I p cos( Vn ip )]
3 3

Fig. 2. DC link controller

(7)
and their more compact forms are given as:
X a1V0 cos 0 X a 2V0 sin 0 pa X a3 (8)
X b1V0 cos 0 X b 2V0 sin 0 pb X b3
Where,
X a1 I p cos ip I n cos in

X a2 I p sin ip I n sin in

VP I P cos( VP iP ) VP I n cos( VP in )
X a3
Vn I n cos( Vn in ) Vn I p cos( Vn ip )
2 2
X b1 I p cos( ip ) I n cos( in )
3 3

Fig. 3. Diagram of cluster voltage balancing control

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 2 2
X b2 I p sin( ip ) I n sin( in )
3 3
2
VP I P cos( VP iP ) VP I n cos( VP in )
3
X b3
2
Vn I n cos( Vn in ) Vn I p cos( Vn ip )
3
From (7) the zero sequence voltage amplitude and phase angle
can be derived as:
( pa X a 3 ) (9)
V 0
X a1 cos 0 X a 2 sin 0

( pa X a3 ) X b1 ( pb X b3 ) X a1 (10)
0 arctan
( pb X b3 ) X a 2 ( pa X a3 ) X b 2
and its time domain instantaneous voltage is expressed as
v0 V0 sin( t 0)
(11) Fig. 4. Block diagram of MMCC-SSFCC STATCOM controller
where t is the synchronous rotating angle created by the
phase locked loop (PLL). ×××ò MODULAR MULTILEVEL CASCASED FLYING
With the calculated zero sequence voltage applied to each CAPACITOR CONVERTER STATCOM CONTROL
phase, the average active power in all three phases should SCHEME
ideally be zero. This zero sequence voltage will not affect the Fig. 4 shows the block diagram of the control system for the
values of voltage and current at the point of common coupling. SSFCC-MMCC based STATCOM. This comprises four parts
C. Converter Phase Reference Voltage Calculation based on their respective functions, namely: (a) reference
current determination block, (b) cluster voltage balancing
The reference voltage per phase limb of the converter
control, (c) current tracking control and (d) modulator
should enable the current flowing to the PCC to compensate
controller.
for reactive power under voltage sag condition. The current
Under the reference current determination and cluster
controller can be designed based on-
*
voltage balancing control block, the reference currents to be
dir ( abc) * (12) compensated are determined along with the cluster powers to
vc( abc) vs ( abc) Lc Rir ( abc)
dt estimate the zero sequence voltage to maintain the DC-link
Where Vs(abc) are the 3-phase line to neutral voltages at PCC, voltage at their nominal values. The current controller is used
Vc(abc) are the 3-phase converter output voltages, ir(abc)* are the in generating the converter phase reference voltages. The
3-phase reference compensated currents. This method uses current controller is actualized using the deadbeat predictive
three voltage source current control for each phase of the controller. The generated reference voltages are inputted into
converter. The voltage source current control is implemented the modulator to synthesize gate signals. The phase shifted
using a predictive deadbeat control expressed as:
PWM is applied for this operation as discussed in [11].
* L Lc (13)
v ( k 1) v (k ) i (k ) c i (k ) R
c ( abc) s _(abc) r ( abc)
Ts
c ( abc)
Ts ×Êò SIMULATION RESULTS
The three instantaneous converter line to neutral voltages The proposed STATCOM controller is verified through
including the zero sequence voltage (Vc_(abc) is expressed in simulation under voltage sag condition. The power system,
(14) as: STATCOM and control strategy are implemented via
vc _(abc) vc ( abc) vo (14) SIMULINK/MATLAB. All parameters are provided in table
Equation (14) ensures that with the addition of the 1. Two different scenarios are studied to highlight the
calculated zero sequence voltage, the module capacitor effectiveness of this STATCOM controller for MMCC-
voltages are maintained at their desired values. This scheme is SSFCC.
verified with the DC-link and flying capacitors maintaining A. STATCOM Low Voltage Ride Through Test Under Voltage
their desired values as discussed in section IV. Sag Condition
In this test, the controller performance when compensating
for reactive power is analyzed under voltage sag condition.
Fig. 5a shows the results for single phase voltage sag having a
voltage depth of 100% for a duration of 100ms.
The voltage sag occurs when STATCOM is carrying out a
reactive capacitive operation (reactive power Q=1.35KVAR).
The STATCOM output voltage and current are shown in
Fig.5b and 5c respectively.

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 TABLE 1
POWER SYSTEM CONFIGURATION PARAMETERS
parameters Rating
Rated network line to neutral voltage (peak) 230V
Distribution system resistance
Distribution system inductance 5mH
Filter resistance
Filter inductance 1600µH
Rated Power System capacity 10KVA
Number of connected cells in per phase Nmp 2
Rated DC voltage of each module 150V
Rated DC voltage of module flying capacitor 75V
DC module capacitance rating 260µF
Module flying capacitor capacitance rating 130µF
Switching frequency fs 750Hz

The phase current has a 900 phase lead over the phase
voltage. It can be observed that the compensated currents
generated by STATCOM controller are balanced as seen in
Fig. 5c, regardless of the voltage sag. With the injection of the
proposed zero sequence voltage (Fig. 5f), it can be observed
from Fig. 5d and 5e that the module and inner flying capacitor
voltages has a deviation of around ±2V and ±4V respectively Fig. 5. Simulated waveforms during single phase voltage sag with a
from their DC voltage reference. This is acceptable because it voltage depth of 100%. (a) Supply voltage. (b) Converter phase
lies within its tolerance limit of ±10% voltage rating. voltage. (c) STATCOM currents. (d) Module dc-link voltages. (e)
Module flying capacitor voltage. (f) Zero sequence voltage
The effectiveness of the proposed balancing algorithm
during asymmetric fault condition is compared with cluster
balancing control without zero sequence voltage injection. Fig.
6 shows that the DC bus and inner flying capacitor voltages
deviate from their desired values during fault ride through
operation. This arises from the cross coupled power terms
expressed in (3).
Fig. 7 shows the waveforms for three phase voltage sags
with a voltage depth of 50%. The SSFCC based STATCOM Fig. 6. Simulated waveforms during single phase voltage sag with a
continually inject three phase balanced sinusoidal currents for voltage depth of 100%. (a) Module dc-link voltages. (b) Module
reactive power compensation even when voltage sag occurs flying capacitor voltage.
(Fig. 7c). Fig. 7d and 7e show that the DC bus voltage and
inner flying capacitor voltages are maintained at their nominal
values. Under this symmetrical fault condition, all the dc bus
and inner flying capacitor voltages are also maintained at their
reference voltages even with the exclusion of the zero
sequence voltage as seen in Fig. 8a and 8b respectively.
Regardless of both methods maintaining the module and
inner flying capacitor voltages under symmetrical fault
conditions, their behavior under asymmetrical fault condition
differs. Therefore, the zero sequence voltage injection control
method has better performance for fault ride through
operations.

Fig. 7. Simulated waveforms during three phase voltage sag with a

voltage depth of 50%. (a) Supply voltage. (b) Converter phase
voltage. (c) STATCOM currents. (d) Module dc-link voltages.
(e) Module flying capacitor voltage.

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 Fig. 8. Simulated waveforms during three phase voltage sag with a
voltage depth of 50%. (a) Module dc-link voltages. (b) Module
flying capacitor voltage.

B. STATCOM Reactive and Unbalanced Current

Compensation Resulting From Unbalanced Voltage
Condition
In this scenario, the STATCOM operation under unbalanced
grid voltage is investigated. The system operates under
balanced condition until at time t= 1.5s, an asymmetric fault
(phase to ground fault) occurs at the supply side, resulting to a Fig. 9. Simulated waveforms during single phase voltage sag with a
voltage depth of 50%. (a) Supply voltage. (b) Supply currents.
voltage depth of 50% (see Fig. 9a). After t= 1.5s, unbalanced (c) Load currents. (d) Module dc-link voltages. (e) Reactive
current is absorbed by the balanced load as shown in Fig. 9c. current component: load reactive current iLq (red) and supply
This unbalanced condition created by the voltage sag is reactive current iSq (black). (f) Negative sequence current
component: load negative sequence current iLn (red) and supply
completely compensated by the STATCOM ensuring the negative sequence current iSn (black).
current at the point of common coupling to be balanced and
equal (see Fig. 9b). As a result of the voltage sag, a negative
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