2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)

An Overview Of Dynamic CMOS Comparators

A. Vidhyashri M. Reena
R. Sangeetha
Department of Electronics and Department of Electronics and
Department of Electronics and
Communication Engineering Communication Engineering
Communication Engineering
SNS College of Technology SNS College of Technology
SNS College of Technology
Coimbatore, India Coimbatore, India
Coimbatore, India
vidhyarajesh1999@gmail.com reenamahendran5@gmail.com
sangeetharajkumar10@gmail.com
Sangeetha govindan J. Ajayan
R. B. Sudharshan
Department of Electronics and Department of Electronics and
Department of Electronics and
Communication Engineering Communication Engineering
Communication Engineering
SNS College of Technology SNS College of Technology
SNS College of Technology
Coimbatore, India Coimbtore, India
Coimbatore, India
sangimenon6@gmail.com email2ajayan@gmail.com
sudharshanresh@gmail.com

Abstract—The circuit performance of dynamic CMOS potential is that the results of the gate. Source, drain and bulk
comparators has been reviewed in this work. CMOS dynamic / body potential, fidgeting with the latter 3 willeffectively
comparators contributes a major role on the implementation of alter the edge voltage. in theory, the effective threshold
mixed signal successive approximation register (SAR) type voltage may also be down by fidgeting with the drain
analog to digital converters (ADC). High precision, dynamic
voltage, as this terminal additionally has a sway on the
range, low voltage operation, high speed, low power
consumption, reliability and offset voltage are the critical potential within the channel. The comparator
factors to be considered while designing CMOS dynamic parameters like propagation delay, current consumption,
comparators. This paper reviewed the performance of some output stage kind, input offset voltage, hysteresis, output
popular dynamic CMOS comparators such as strong arm latch current capability, Fix and fall time, CMVR. The
comparator, dynamic latched comparator, resistive diode characteristics of the CMOS comparators are as follows:
comparator, double tail comparators, differential pair Response time: The interval time between time and step
comparator and Lewis-Grey comparator. input when the output attains the relevant logic level,
Hysteresis: It is the threshold voltage and it is different for
Keywords—Successive approximation register(SAR), Latch
comparator, Lewis-Grey comparator.
rising signal and falling signal, Sensitivity: In this input
voltage is minimum and gives an compatible output,
Latching compatibility: A command which is both latch and
I. INTRODUCTION unlatch which gives an logic state of an output, Input offset:
A device known as comparator, accustomed compare the In this voltage is given as an input and applied to the
2 voltages or current and outputs a digital signal transition between high and low state. The applications of
indicating that is larger. the comparator following: When a given value is as zero, it
it's accustomed sense once AN whimsical variable signal uses one of its functions Null Detector to identify.
reaches some threshold or reference level. Comparator Comparator may be a type of amplifier distinctively for null
is several circuits like Analog to digital comparison measurements, Zero crossing detectors detects
converters, change power regulator, dynamic each ac pulse changes polarity, Relaxation oscillator shows
logics, knowledge transmission etc. it's wide application negative feedback added to the trigger by the RC circuits
in distributed data processing communication, signals and biases the circuit to oscillator. The feedback may be
systems. The specifications of the comparator are power a Schmitt trigger, Level shifter circuit
consumption, immunity to noise mismatches and offset. provides nice flexibility in selecting the voltages to be
Dynamic comparators obtain a very low power dissipation translated by appropriate pull up voltage, The window
and at an inactive state they are turned off. The reduction detector is employed to check 2 voltages
technique of CMOS comparator square measure scaling, and confirm whether or not a given input voltage
threshold voltage. Scaling technology leads to reduction of is beneath voltage or over voltage, definite quantity detector
the lateral and vertical dimensions of transistors. detects two comparators and a digital logic gates and it is
There square measure 3 sorts of scaling like constant voltage, used to compare the absolute value of two voltages.
constant field and lateral scaling. In constant voltage scaling,
VDD is unbroken constant and therefore the method is II. ARCHITECTURE OF DYNAMIC COMPARATORS
scaled. For constant field scaling, the device
dimensions square measure scaled by the parameter ƛ. In A. STRONG ARM LATCH COMPARATOR
constant field scaling all dimensions of transistors, device
voltages and therefore the doping concentration densities J. Kim et al has demonstrated a strong ARM latch
by issue. In lateral scaling solely the gate length is comparator in 2009. A Clocked comparator is designed for
scaled. this is often additionally referred to as because low power and low cost. The schematic diagram for strong
the “Gate shrinking”. At circuit level, the edgevoltage will ARM latch comparator is shown in Fig. 1. It is the CMOS
be reduced by increasing the potential of the channel comparator consists of five NMOS and four PMOS. The
input pins are IN+ and IN-. The output pins are OUT+ and
for constant gate supply voltage. because thechannel

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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)
OUT-. It has enormous applications such as memory bit-line represented in Fig. 2. It comprises of three input pins VIN,
detectors, A/D converters and wireline receivers and used as VIP and LATCH and output pins are VOP and VON. The
a robust latch with high sensitivity. Thermal noise and dynamic latched comparator consists of six PMOS and five
flicker noise produce a random errors in the device it can be NMOS. In this latched comparator, regeneration can be done
overcome by using a sufficient magnitude for correct by using the cross coupled CMOS inverter. This type of
detection on each comparator. It is CMOS technologies, comparator has high speed performance without limitations
there will be a reduction of signal power due to the in Quiscent point. In power delay, the conventional logic
increased demand for low power consumption. In the strong 10.01μW and proposed logic 8.801μW. In delay, the
ARM latch comparator, for high performance 45nm strained conventional logic is 30.3ns and proposed logic is 22.1ns.
silicon technology, there will be 1.834ns delay and 7.19μW The most important parameter in dynamic latched
power. In the Low power 45nm technology, delay will be comparator. It shows that the performance of the comparator
1.8974ns and power will be 5.9894μW. The important has large effect. The major advantage of dynamic latched
features are it has small input referred offset and it won’t comparator is that the input impedance is high, output will be
consume any static power. Hence it produce the output as full swing and static power consumption is zero.
rail to rail.
C. RESISTIVE-DIVIDER-COMPARATOR

Fig. 3. Circuit Diagram of a Resistive-divider-comparator [7]

Fig. 1. Circuit Diagram of Strong ARM latch Comparator[4] P. E. Allen et al has reported a resistive divider
comparator in 2002. Resistive-divider-comparator is widely
used in pipeline Analog to Digital converter. Its work mainly
B. DYNAMIC-LATCHED-COMPARATOR
depends on a differential-sensing-amplifier. Moreover in
electronics, comparator will be used for comparing two
voltages or current which were given at two inputs of the
comparator. It gives a differential output voltage either high
level or low level signal. The schematic diagram shown in
the Fig. 3. In this VIN+ and VIN- are the inputs and
VOUT+ and VOUT- are output pins. CMOS comparator
have been considered as one of the most input circuit for
ADC. When VLATCH is set to zero, the control signal of the
two transistors where switched ON and another two
transistors are switched OFF, which in case causes to force
the output nodes of the differential to VDD and there is no
current supply at this phase. In high performance 45nm
strained silicon technology is used, when the delay is to be
maintained at 1.8757ns and power is to be at 4.8632μW.

D. CONVENTIONAL DOUBLE TAIL COMPARATOR

Shinkel et al has analysed a conventional-double-tail -
comparator in 2007. This type of comparator has been made
more efficient by modifying for low power and made to
operate at the high speed even in smaller supply voltage. It
Fig. 2. Circuit diagram of dynamic latched comparator [5 ] consists of an added transistor in its design without creating
any drawbacks in its function. It works at low voltage supply
P. M. Figueiredo et al proposed the Dynamic latched and has less stacking. Conventional double tail comparator is
comparator in 2006. This CMOS comparator was designed demonstrated in fig.4. During reset phase, the transistor are
to work with high speed and static low power consumption. in OFF condition when clock is zero. This pre changes to
Thus schematic diagram for dynamic-latched-comparator is VDD and in turn makes the transistors to put off change at

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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)
output nodes to ground. Hence the immediate stage formed is the efficient area and the need for low power, by pushing
transistor provides production among input and output stages ADC towards the dynamic regenerative comparator to
which produces kickback noise. In this delay for high increase the power efficiency and speed. The schematic
performance is 204.19ps and the power is 0.19152μW. For diagram shown in Fig. 5. The input pins are INN and INP
low performance, delay is 275.74ps and power is and output pins are OUTN and OUTP. For High
0.10886μW. performance 45nm, when the delay is 46.25ps and the power
is 0.21378μW. For Low performance 45nm, when the delay
is 173.3ps and the power is 0.11179μW.

F. CONVENTIONAL-DYNAMIC-COMPARATOR

Fig. 4. Circuit diagram of conventional double tail comparator [6 ] Fig. 6. Circuit diagram of conventional-dynamic- comparator [3]

B. Goll et al demonstrated that conventional comparator

E. LOW VOLTAGE LOW POWER DOUBLE- TAIL- in 2009.It consists of NMOS and PMOS transistors. There
COMPARATOR are four PMOS and five NMOS. Conventional dynamic
comparator is demonstrated in Fig. 6. Phases involved are
reset and comparison. INN and INPM are input nodes and
OUTN and OUTP are output nodes. Conventional dynamic
comparator has a delay of 1.832ns for high performance
45nm strained silicon technology. It consumes about
2.647μW of power at high performance. When compared at
low performance, this comparator has a delay of 1.892ns and
the power consumption of 1.9622μW. The advantages
features of conventional dynamic comparator is good
strength against mismatch and noise. It has wide application
in high speed ADC’s with high input impedance, rail to rail
output voltage swing and no static power consumption. It
compares the input voltage with reference voltages.

G. DIFFERENTIAL- PAIR- COMPARATOR

Fig. 5. Circuit diagram of Low voltage Low power Double-tail-

comparator[1]

S. B. Mashhadi et al has reported a low power low

voltage double-tail-comparator in 2013. A new dynamic
comparator is proposed based on the presented analysis. A
conventional double tail comparator is redesigned for fast Fig. 7. Schematic diagram of differential pair comparator [10]
operation and low power consumption where the supply
voltage is very small. A main application of this comparator

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 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS)
G. N. Balaji et al demonstrated a differential pair [2] Lauri Sumanen, Mikko Wattari, Kari Halonen “A Mismatch
comparator. It is a two stage CMOS amplifier with Insensitive CMOS Dynamic Comparators for Pipeline A/D
Conveters, ” pp. 32-35.
differential pair which are unbalanced. It consists of four
[3] “An Improved Dynamic Latch Based Comparator for 8-bit
PMOS and eight NMOS. The schematic diagram of Asynchronous SAR ADC” pp. 179-182 by Anush Bekal, Bahu. R.
Differential-pair-comparator is shown in Fig. 7. It comprises Singh, Ashok Srivatsava, Rohit Joshi and Manish Goswami.
of inverted output and input. Differential pair is unbalanced [4] Sarfraz Hussain, Rajesh kumar, Gaurav Trivedi, “Comparision and
by the second differential pair. Gates present in second Design of dynamic comparator in 180nm SCL technology for low
differential pair are attached to output signal. These gates power and high speed flash ADC” 2017 IEEE International
provide hystersis or positive feedback. The second Symposium on Nano electronic and Information Systems, pp. 140 -
144
differential pair provide hystersis bias current and forms the
current mirror of the transistor. There are two differential [5] “A Fast Convergent and Energy Efficient offset Calibration
Technique For Dynamic Comparators,” pp. 551-554 by Mohsen Judy
pairs, first differential pair is bigger than the latter one and it and Jeremy Holleman.
brings in parasitic capacitance to input amplifier. Hystersis [6] “A Multi-GHz Area-Efficient Comparator with Dynamic Offset
amount can be programmed by varying the Hystersis Cancellation” by Lingkai kong, Yue Lu, and Elad Alon.
current. [7] D. Osipov, “A 50ms/s low-power S-bit dynamic voltage comparator
in 0.18μm CMOS process,” PROC. 29TH International conference on
H. LEWIS- GRAY COMPARATOR Micro electronics (MEL2014),BELGRADE, SERBIA, 12-14 MAY,
2014, PP.439-442.
[8] Louis Luth, John choma, Jr. , Jeffrey Draper, “A High- Speed High –
Resoluted CMOS Current Comparator”
[9] Ricky Xiu- Kee Choi, chi-yingTsui, “A Novel Offset Cancellation
Technique for Dynamic Comparator Latch” 614-617
[10] G. N. Balaji, S. Karthikeyan, M. M. Asha, “o.18μm CMOS
comparator for High Speed Applications, International Journal of
Trend in Schematic Research and Development, Volume-1, pp.671-
674 , 2017 July-August.

Fig. 8. Schematic diagram of Lewis-Gray comparator [2]

L. Sumanen et al demonstrated a Lewis-Gray

comparator. In pipeline Analog to Digital converter, the
mostly used dynamic-comparator is depends on a
differential-sensing-amplifier. The benefit will be the
consumption of dc power is zero. The schematic diagram
shown in Fig. 8. There are four PMOS and eight NMOS. The
input pins are V+in, V-in and Vlatch . The ouput pins are
V+out and V-out. In triode region. when input and reference
transistors are present, it acts like voltage controlled
transistors.

III. CONCLUSION
In this review article, we presented an overview of
dynamic CMOS comparators which are the key components
in memory data receivers and Analog to Digital convertors
with high perfomance. Since the dynamic comparators have
the full-swing output, static power consumption is zero and
the input impedance is high, they are widely used in
consumer/industrial applications over static comparators.
Improving the speed without degrading the reliability and
performance is a critical challenge in the design of dynamic
comparators for future applications.

REFERENCES

[1] Sunwoo Kwon, Hoilee, “A 1.2v, 3.5μW, 20MS/S, 8-bit Comparator

with Dynamic- Biasing Preanmplifier, ”ISCAS 2006, pp. 4767-4770.

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