HW 5

Jun Li E.E.
457 HW#05
Problem 1 (25 points)

a) Using Electric, design a NMOS domino logic circuit for F=AB+CD + AC using 2-
input OR and AND gates. Do not simplify.
b) Layout in Electric. Run DRC check.
c) Make clock signal to cover the D input during the evaluate mode.
d) Do IRSim analysis of the layout. Put A=0, B=0, C=1 and D shown below.
0 5ns 10ns 20ns 25ns 35ns 40ns time
Timing Diagram for D Input
IRSIM:
LT-Spice:
Problem 2: (50 points)
Construct a dynamic NMOS gate for the function f =x⋅y + x⋅( z +w ). Do not simplify.
a) Draw a circuit schematic in Electric.
b) Provide a layout of the circuit using Electric. Use clock signal of 2GHz for LTSPICE.
c) Put Cload=5pF for the output capacitor and run LTSPICE with x=1, z=1 and w=1. The signal y
has clock pulse of 500MHz. Only print out 3 cycles.
When using 2GHz Clock:

When using 5 MHz Clock:
d) Now try Cload = 1fF and run the same LTSPICE as in part c). Did you observe any differences in
your output waveform? Only print out 3 cycles.
When using 2GHz Clock:
When using 5MHz Clock:
Observation: When output capacitance Cf = 5pF, a relatively large capacitance, the RC constant will be
large, therefore the charging and discharging time is longer. The 2GHz clock has such a short period that
the evaluation section is too small to complete charging and discharging, and the exponential growth and
decay characteristic of the charging and discharging sections causes gradual voltage drop as clock
continues. When output capacitance Cf=1fF, about the value of normal parasitic capacitance, the output
waveform shows clear charging and discharging sections. However, both charging and discharging is not
complete since the clock frequency is still high.
e) Use IRSIM and provide the output waveform by creating your own input signals.
Problem 3: (25 points)
Assume that you are a design engineer and at a leading semiconductor company. You are requested to
analyze high-speed signals on a newly developed chip on a silicon substrate. Assume that all fabrication is
done through a conventional CMOS batch process. You are to analyze a signal interconnect length of 750
um with width of 75 um and thickness of 10um. The interconnect is made of aluminum. Calculate the
following:
1) Find R, L and C if the oxide layer is 50 angstroms. Calculate characteristic impedance.

Resistance:
L ρ Al −6
L 2.7 ×10−8 Ω∙ m ( 750× 10 m )
R=R s × = × = × =0.027 Ω
W Thickness W 10× 10−6 m 75× 10−6 m
Capacitance:
0.222
t
[
C=c fringe L=ε ox 1.15
Inductace:
W
( ) (
t ox
+2.8 interconnect
t ox ) ] ( L ) =3.9× 8.854 ×
m [ (
10−12 F
1.15
75× 10−6 m
50 ×10−10 m) (
+2.8
10× 10−6 m
50 ×10−10 m
10−12 F 10−7 H
3.9 × 8.854 × ×4π ×
ε ox μ ox m m (
L=l ( length )= (length )= 750 × 10−6 m )=18.2 fH / m ( 750 ×10−6 m ) =
c fringe 0.596 uF
m
18.2 fH
Characteristic Impedance:
Z 0=
l
c fringe
=
√ m
0.596 uF /m √
=5.53 m Ω
2) Find time of flight delay on a silicon substrate.

Length Length 750 ×10−6 m
t flight = = = =5 ps
Time of flight: v c0 108 m
1.5 ×
√ε r μ r s
3) Assume a digital pulse goes through the 1000um long copper interconnect with 5GHz and rise
and fall time of 1ps. Determine if the transmission line effect should be considered. Provide
reasons.
1000 ×10−6 m
t flight = =6.67 ps
108 m
1.5 ×
s
t r=t f < 2.5t flight
Resistance:
L ρ Al −6
L 1.7 ×10−8 Ω ∙ m ( 1000× 10 m )
R=R s × = × = × =0.023 Ω
W Thickness W 10 × 10−6 m 75× 10−6 m
Fringe Capacitance per unit length:
0.222 0.22
t
c=ε ox
[ 1.15
W
( ) (
t ox
+2.8 interconnect
Inductance per unit length:

t ox ) ]
=3.9 ×8.854 ×
m [ (
10−12 F
1.15
75 ×10−6 m
) (
50 ×10−10 m
+2.8
10 ×10−6 m
50 ×10−10 m )
10−12 F 10−7 H
3.9 × 8.854 × × 4 π ×
ε μ m m
l= r r = =18.2 fH /m
c 0.596uF / m
18.2 fH
Characteristic Impedance: Z 0= l =
R<5 Z0
c
m
√
0.596 uF
m
Transmission line effect should be considered.

√
=5.53 m Ω
4) Using LTSPICE, provide simulation of a lossy distributed line (RLC) with 10 stages. Provide
output pulse waveforms with 50 Ohm load. Use input pulse waveform of 5GHz with 5 volts. Use
per unit values of 2ohms/um, 1pH/um and 5fF/um. Provide only 3 cycles of the waveform.
Load = 50 Ohm:
5) Now run the same simulation as in part 4) with 20 Ohm load and provide the output waveforms
for 3 cycles. What did you observe?
Load = 20 Ohm:
Observation: The 50 Ohm load case shows a output that is more like a square wave despite a little ripple at
the edge, whereas the 20 Ohm load case gives a output that has more obvious RC charging/discharging part
at the edge. In addition, 50 Ohm case preserves about 72% of input voltage, but 20 Ohm case has only
around 50%.

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Jun Li E.E.

Problem 1 (25 points)

When using 2GHz Clock:

Problem 3: (25 points)

1) Find R, L and C if the oxide layer is 50 angstroms. Calculate characteristic impedance.

2) Find time of flight delay on a silicon substrate.

Inductance per unit length:

Transmission line effect should be considered.

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