IJSRD - International Journal for Scientific Research & Development| Vol.

1, Issue 9, 2013 | ISSN (online): 2321-0613

Synthesis & FPGA Implementation of UART IP Soft Core

Sohini Chatterjee1 Sona Gava2 Shreya Sharan3 Sonam Sinha4 Subir Maity5
1,2,3,4
B. Tech Student 5Assistant Professor
1,2,3,4
Department of Electronics & Telecommunication 5School of Electronics Engg.
1,2,3,4,5
KIIT University, Bhubaneswar-751024, Odisha, India

Abstract—this paper presents synthesis and hardware UART is to sample the incoming serial data at the
implementation of fully functional Universal Asynchronous right time to precisely capture the binary stream. UART
Receiver Transmitter Intellectual Property core using serves as a medium to send information using a minimum
XILINX SPARTAN-3 XC3S400 series FPGA. The UART number of wires. The data is sent bitwise in a serial fashion,
soft core module consists of a transmitter along with baud without a clock signal [8]. The main function of a UART is
rate generator and a receiver module with false start bit the conversion of parallel-to-serial when transmitting and
detection features. This has been implemented using serial to-parallel when receiving. The fact that a clock signal
VERILOG hardware description language and synthesized is not sent with the data complicates the design of a UART.
using XILINX ISE development tools. All behavioral The following are the components required for this
simulation of UART module performed using MODELSIM serial to parallel and vice versa Communication:
simulator. After successful FPGA implementation
transmitter and receiver module was tested by connecting 1) BAUD RATE GENERATOR: A fast clock is used to
FPGA board with Hyper Terminal software via RS232 sample the binary stream multiple times for each data
interface at a data speed of 9.6 kbps. bit. It is basically a clock divider.
2) TRANSMITTER: When transmitting, the UART
Key words: VERILOG, UART, XILINX, MODELSIM, receives the data in parallel from the application, and
Baud rate, Soft core. sends it serially on the TxD pin.
3) RECEIVER: When receiving, the UART receives the
I. INTRODUCTION data serially on the RxD pin, and provides the parallel
An IP (intellectual property) core is a block of logic or data data to the application.
that is used in making a field programmable gate array
( FPGA ) or application-specific integrated circuit ( ASIC ) II. BAUD RATE GENERATOR
for a product. As essential elements of design reuse, IP cores Basically it is a clock divider. The main clock frequency is
are part of the growing electronic design automation (EDA) divided to generate specific data transfer rate. In this design-
industry trend towards repeated use of previously designed
components. Ideally, an IP core should be entirely portable - Main clock: 50 MHz, Required Baud rate: 9.6kbps
that is, must be easy to insert into any vendor technology or Divisor: (50,000/9.6) = 5208
design methodology. Universal Asynchronous Receiver It uses a counter & when count=5208, a pulse is
/Transmitter (UART s), central processing units generated at output. Verilog HDL is used to design Baud
(CPU s), Ethernet controllers, and PCI interfaces are all rate generator. MODELSIM [6] simulation result shown in
examples of IP cores. Fig.1.
IP cores fall into one of three categories: hard
cores, firm cores, or soft cores [4]. Hard cores are physical
manifestations of the IP design. These are best for plug-and-
play applications, and are less portable and flexible than the
other two types of cores. Like the hard cores, firm
(sometimes called semi-hard) cores also carry placement
data but are configurable to various applications. The most
flexible of the three, soft cores exist either as a net-list or
hardware description language (HDL) code.
A UART is a Universal Asynchronous Receiver-
Transmitter, which is used to communicate between two
devices [1, 2, 4]. Most computers and microcontrollers
include one or more serial data ports to communicate with
other serial I/O devices, such as keyboards and serial
printers. Serial ports are also used to communicate between Fig. 1: Simulation Result of Baud Rate Generator
two computers using a UART in each computer and a
crossover cable, which connects the transmitter (TxD) of III. UART TRANSMITTER
one UART to the receiver (RxD) of the other, and vice The transmitter was designed by five states. Those five
versa. A common ground (GND) wire connects both states are namely- IDLE, START, SEND, STOP1, and
computers to a common negative voltage source [8]. STOP2 as shown in Fig. 2.

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 Synthesis & FPGA Implementation of UART IP Soft Core
(IJSRD/Vol. 1/Issue 9/2013/0074)

HIGH to LOW transition in TX line receiver recognizes it as

beginning of a new transmission. But due to environmental
noise or man-made noise such as electric sparking etc., there
may be false short duration HIGH to LOW transition which
is detected by receiver which then treats the next data bits as
incoming data. To avoid this problem, one simple false start
bit detection scheme is introduced in this design. Detection
of START bit started with HIGH to LOW transition and it is
already sampled 16 times by UART receiver clock. At 5 th,
8th and 11th clock pulse, data sample of START bit are
collected and those bits are logically ‘AND’ed. If output is
Logic 1 then there was no false transition. If the result is
Logic 0, then receiver detects it as a false transition and
ignore it.

V. FPGA IMPLEMENTATION
Fig. 2: FSM for UART Transmitter After successful behavioral simulation of UART Module
using MODELSIM simulator, it was synthesized and
In this design 1-start bit, 2 stop bit and no parity mapped into XILINX SPARTAN-3 XC3S400 series FPGA
bits were used to transmit 8 bit data. Transmission started using XILINX ISE [5] design suite. Transmitter module is
with a START bit which is basically HIGH to LOW connected with computer’s serial port via RS232 interface
transition. Then 8 bit data are transmitted and after sending and incoming transmission was successfully tested using
8 bits two STOP bits were transmitted via TX line. STOP popular communication program named ‘HYPER
bits are HIGH. After completion of transmission, TX line TERMINAL’ with data transfer speed of 9600 bps, 2 stop
becomes HIGH which indicates Transmitter is in IDLE or bit, no parity, no flow control mechanism. To test receiver
REST condition. Transition from one state to another state module, ASCII character was transmitted from HYPER
occurs at rising edge of BAUD RATE clock pulse. TERMINAL and displayed on the LEDs connected at 8 bit
data output pin of UART receiver and data bits were
IV. UART RECEIVER received correctly.
In this design, Transmitted data bits were sampled 16 times
by using receiver side BAUD RATE clock which is 16 VI. RESULTS & DISCUSSION
times faster than Transmitter side clock pulse. Each data bit Fig. 4 shows MODELSIM simulation result of complete
is detected at its mid position and stored in a temporary UART transmitter and receiver for the transmission of 8bit
register. When all 8 bits are detected, then 8 bit parallel data digital data- ‘10110010’. In SPARTAN-3 XC3S400 series
is available at UART receiver output. FPGA. Total 63 slices and 113 LUTs were utilized to
The receiver was designed by five states. Receiver implement complete UART IP soft core.
side FSM diagram given in Fig. 3.

Fig. 4: Simulation of UART Transmitter with Receiver

Fig. 3: FSM for UART Receiver VII. CONCLUSION

False Start Bit Detection: When transmitter is in IDLE or One complete UART module was successfully implemented
REST condition TX line is HIGH which is connected with in XILINX SPARTAN-3 XC3S400 series FPGA and tested
RX line of UART receiver. In conventional UART design by connecting board with PC Hyper Terminal. Receiver
data bit detection in the receiver side starts with START bit module includes false start bit detection features. In future
which is HIGH to LOW transition. Whenever there is one FIFO can be introduced to enhance data processing

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 Synthesis & FPGA Implementation of UART IP Soft Core
(IJSRD/Vol. 1/Issue 9/2013/0074)

capability and to introduce parallel processing concept in

UART module. Also parity bit may be included to detect
error present in receiving bits.

REFERENCES
[1] Yu, Chen, “Implementation of a Multi-
channel UART Controller Based on FIFO Technique
and FPGA” Industrial Electronics and Applications,
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[2] Fang Yi-yuan , Chen Xue-jun ” Design and Simulation
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[3] M.Kaur, R.Mittal,” Fpga Implementation & Design of
Micro UART with Different Baud Rates” Journal of
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[4] 16750 UART core, http:// opencores.org/ project/ Uart
16750”
[5] XILINX ISE Tutorial “download.xilinx.com/ …ect/
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[6] Modelsim Tutorial, “www.mentor.com”
[7] PC16550D tutorial,” http://www.ti.com/general
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[8] Wikipedia, The Free Encyclopedia, Universal
asynchronous receiver/transmitter,
”http://en.wikipedia.org/wiki/Universal_asynchronous_
receiver/transmitter”

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