Datasheet

ENHANCED PIC16C5X
EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

Devices Included in this Data Sheet Pin Diagram
• PIC16C54A
PDIP, SOIC, Windowed CERDIP
• PIC16CR54A
• PIC16CR54B RA2 •1 18 RA1
RA3 2 17 RA0
• PIC16CR56
PIC16CR58B
PIC16CR58A
PIC16C58A
PIC16CR56
PIC16CR54A
PIC16C54A
PIC16CR54B
T0CKI 3 16 OSC1/CLKIN
• PIC16CR57A MCLR/VPP 4 15 OSC2/CLKOUT
VSS 5 14 VDD
• PIC16CR57B 6 13 RB7
RB0
• PIC16C58A RB1 7 12 RB6
RB2 8 11 RB5
• PIC16CR58A 10
RB3 9 RB4
• PIC16CR58B
High-Performance RISC CPU
PDIP, SOIC, CERDIP
• Only 33 single word instructions to learn
• All instructions are single cycle (200 ns) except T0CKI •1 28 MCLR
for program branches which are two-cycle VDD 2 27 OSC1/CLKIN
N/C 3 26 OSC2/CLKOUT
• Operating speed: DC - 20 MHz clock input VSS 4 25 RC7
PIC16CR57B
PIC16CR57A
DC - 200 ns instruction cycle N/C 5 24 RC6
RA0 6 23 RC5
EPROM/
Device Pins I/O RAM RA1 7 22 RC4
ROM RA2 8 21 RC3
RA3 9 20 RC2
PIC16C54A 18 12 512 25 RB0 10 19 RC1
PIC16CR54A 18 12 512 25 RB1 11 18 RC0
RB2 12 17 RB7
PIC16CR54B 18 12 512 25
RB3 13 16 RB6
PIC16CR56 18 12 1K 25 RB4 14 15 RB5
PIC16CR57A 28 20 2K 72
PIC16CR57B 28 20 2K 72
PIC16C58A 18 12 2K 73 • Selectable oscillator options:
PIC16CR58A 18 12 2K 73 - RC: Low-cost RC oscillator
PIC16CR58B 18 12 2K 73 - XT: Standard crystal/resonator
• 12-bit wide instructions - HS: High-speed crystal/resonator
• 8-bit wide data path - LP: Power saving, low frequency crystal
• Seven or eight special function hardware CMOS Technology
registers • Low-power, high-speed CMOS EPROM/ROM
• Two-level deep hardware stack technology
• Direct, indirect and relative addressing modes for • Fully static design
data and instructions • Wide-operating voltage range:
Peripheral Features - EPROM Commercial/Industrial 2.5V to 6.25V
• 8-bit real time clock/counter (TMR0) with 8-bit - ROM Commercial/Industrial 2.5V to 6.25V
programmable prescaler
- EPROM Automotive 2.5V to 6.0V
• Power-On Reset (POR)
• Low-power consumption
• Device Reset Timer (DRT)
- < 2 mA typical @ 5V, 4 MHz
• Watchdog Timer (WDT) with its own on-chip RC
- 15 µA typical @ 3V, 32 kHz
oscillator for reliable operation
- < 0.6 µA typical standby current (with WDT
• Programmable code-protection
disabled) @ 3V, 0°C to 70°C
• Power saving SLEEP mode
 1996 Microchip Technology Inc. DS30236B-page 1
This document was created with FrameMaker 4 0 4

Enhanced PIC16C5X
Pin Diagrams (con’t)
SSOP SSOP
RA2 •1 20 RA1 VSS •1 28 MCLR/VPP

RA3 2 19 RA0 T0CKI 2 27 OSC1/CLKIN
VDD 3 26 OSC2/CLKOUT
PIC16CR57B
PIC16CR57A
PIC16CR58B
PIC16CR58A
PIC16C58A
PIC16CR56
PIC16CR54B
PIC16CR54A
PIC16C54A
T0CKI 3 18 OSC1/CLKIN
VDD 4 25 RC7
MCLR/VPP 4 17 OSC2/CLKOUT RA0 5 24 RC6
VSS 5 16 VDD RA1 6 23 RC5
VSS 6 15 VDD RA2 7 22 RC4
RB0 7 14 RB7 RA3 8 21 RC3
RB0 9 20 RC2
RB1 8 13 RB6 10 19 RC1
RB1
RB2 9 12 RB5 RB2 11 18 RC0
RB3 10 11 RB4 RB3 12 17 RB7
RB4 13 16 RB6
VSS 14 15 RB5
Table of Contents
1.0 General Description .............................................................................................................................................3
2.0 Enhanced PIC16C5X Device Varieties................................................................................................................5
3.0 Architectural Overview.........................................................................................................................................7
4.0 Memory Organization ........................................................................................................................................13
5.0 I/O Ports.............................................................................................................................................................23
6.0 Timer0 Module and TMR0 Register...................................................................................................................25
7.0 Special Features of the CPU .............................................................................................................................29
8.0 Instruction Set Summary ...................................................................................................................................41
9.0 Development Support ........................................................................................................................................53
10.0 Electrical Characteristics - PIC16C54A .............................................................................................................59
11.0 Electrical Characteristics - PIC16CR54A...........................................................................................................71
12.0 Electrical Characteristics - PIC16CR54B/56/58B ..............................................................................................85
13.0 Electrical Characteristics - PIC16CR57A...........................................................................................................99
14.0 Electrical Characteristics - PIC16CR57B.........................................................................................................111
15.0 Electrical Characteristics - PIC16C58A ...........................................................................................................125
16.0 Electrical Characteristics - PIC16CR58A.........................................................................................................137
17.0 DC and AC Characteristics - All Enh. PIC16C5X, Except PIC16CR54A.........................................................151
18.0 DC and AC Characteristics - PIC16CR54A .....................................................................................................163
19.0 Packaging Information .....................................................................................................................................173
Appendix A: Compatibility................................................................................................................................185
Appendix B: What’s New .................................................................................................................................185
Appendix C: What’s Changed..........................................................................................................................186
Appendix D:PIC16/17 Microcontrollers............................................................................................................187
Index ................................................................................................................................................................195
Connecting to Microchip BBS ..........................................................................................................................199
Access to the Internet ......................................................................................................................................199
Reader Response............................................................................................................................................200
Enhanced PIC16C5X Product Identification System .......................................................................................201
To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
To assist you in the use of this document, Appendix B contains a list of new information in this data sheet, while
Appendix C contains information that has changed.
DS30236B-page 2  1996 Microchip Technology Inc.

Enhanced PIC16C5X
1.0 GENERAL DESCRIPTION 1.1 Applications
The Enhanced PIC16C5X from Microchip Technology The PIC16C5X series fits perfectly in applications
is a family of low-cost, high performance, 8-bit, fully ranging from high-speed automotive and appliance
static, EPROM/ROM-based CMOS microcontrollers. motor control to low-power remote transmitters/receiv-
This family is pin and software compatible with the ers, pointing devices and telecom processors. The
PIC16C5X family of devices in a new enhanced EPROM technology makes customizing application
process technology. It employs a RISC architecture programs (transmitter codes, motor speeds, receiver
with only 33 single word/single cycle instructions. All frequencies, etc.) extremely fast and convenient. The
instructions are single cycle (200 ns) except for small footprint packages, for through hole or surface
program branches which take two cycles. The mounting, make this microcontroller series perfect for
Enhanced PIC16C5X delivers performance an order of applications with space limitations. Low-cost,
magnitude higher than its competitors in the same low-power, high performance, ease of use and I/O flex-
price category. The 12-bit wide instructions are highly ibility make the PIC16C5X series very versatile even in
symmetrical resulting in 2:1 code compression over areas where no microcontroller use has been
other 8-bit microcontrollers in its class. The easy to use considered before (e.g., timer functions, replacement
and easy to remember instruction set reduces of “glue” logic in larger systems, coprocessor
development time significantly. applications).
The Enhanced PIC16C5X products are equipped with
special features that reduce system cost and power
requirements. The Power-On Reset (POR) and Device
Reset Timer (DRT) eliminate the need for external
reset circuitry. There are four oscillator configurations
to choose from, including the power-saving LP (Low
Power) oscillator and cost saving RC oscillator. Power
saving SLEEP mode, Watchdog Timer and code
protection features improve system cost, power and
reliability.
The UV erasable CERDIP packaged versions are ideal
for code development, while the cost-effective
One-Time-Programmable (OTP) versions are suitable
for production in any volume. The customer can take
full advantage of Microchip’s price leadership in OTP
microcontrollers while benefiting from the OTP’s
flexibility.
The PIC16C5X products are supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a ‘C’ compiler, fuzzy logic support
tools, a low-cost development programmer, and a full
featured programmer. All the tools are supported on
IBM PC and compatible machines.

Enhanced PIC16C5X
TABLE 1-1: ENHANCED PIC16C5X FAMILY OF DEVICES
Clock Memory Peripherals Features
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PIC16C54 20 512 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C54A 20 512 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR54(2) 20 — 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR54A 20 — 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR54B (1) 20 — 512 25 TMR0 12 2.5-5.5 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C55 20 512 — 24 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16C56 20 1K — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR56(1) 20 — 1K 25 TMR0 12 2.5-5.5 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C57 20 2K — 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16CR57A (2) 20 — 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16CR57B 20 — 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16C58A 20 2K — 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR58A 20 — 2K 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR58B(1) 20 — 2K 73 TMR0 12 2.5-5.5 33 18-pin DIP, SOIC; 20-pin SSOP
Legend: Grayed boxes: Devices NOT covered in this data sheet.

All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and
high I/O current capability.
Note 1: Please contact your local sales office for availability of these devices.
2: Not recommended for new designs.

Enhanced PIC16C5X
2.0 ENHANCED PIC16C5X DEVICE 2.3 Quick-Turnaround-Production (QTP)
VARIETIES Devices
A variety of frequency ranges and packaging options Microchip offers a QTP Programming Service for
are available. Depending on application and factory production orders. This service is made
production requirements, the proper device option can available for users who choose not to program a
be selected using the information in this section. When medium to high quantity of units and whose code
placing orders, please use the Enhanced PIC16C5X patterns have stabilized. The devices are identical to
Product Identification System at the back of this data the OTP devices but with all EPROM locations and
sheet to specify the correct part number. configuration bit options already programmed by the
For the Enhanced PIC16C5X family of devices, there factory. Certain code and prototype verification
are four device types, as indicated in the device procedures apply before production shipments are
number: available. Please contact your Microchip Technology
sales office for more details.
1. C, as in PIC16C54A. These devices have
EPROM program memory and operate over the 2.4 Serialized
standard voltage range. Quick-Turnaround-Production
2. LC, as in PIC16LC54A. These devices have (SQTP SM) Devices
EPROM program memory and operate over an
extended voltage range. Microchip offers the unique programming service
3. CR, as in PIC16CR54A. These devices have where a few user-defined locations in each device are
ROM program memory and operate over the programmed with different serial numbers. The serial
standard voltage range. numbers may be random, pseudo-random or
sequential.
4. LCR, as in PIC16LCR54A. These devices have
ROM program memory and operate over an Serial programming allows each device to have a
extended voltage range. unique number which can serve as an entry code,
password or ID number.
2.1 UV Erasable Devices
2.5 Read Only Memory (ROM) Devices
The UV erasable versions, offered in CERDIP
packages, are optimal for prototype development and Microchip offers masked ROM versions of several of
pilot programs the highest volume parts, giving the customer a low
cost option for high volume, mature products.
UV erasable devices can be programmed for any of
the four oscillator configurations. Microchip's
PICSTART and PRO MATE programmers both
support programming of the Enhanced PIC16C5X.
Third party programmers also are available; refer to
the Third Party Guide for a list of sources.
2.2 One-Time-Programmable (OTP)

Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages,
permit the user to program them once. In addition to
the program memory, the configuration bits must be
programmed.

Enhanced PIC16C5X
NOTES:

Enhanced PIC16C5X
3.0 ARCHITECTURAL OVERVIEW The PIC16C5X device contains an 8-bit ALU and
working register. The ALU is a general purpose
The high performance of the PIC16C5X family can be arithmetic unit. It performs arithmetic and Boolean
attributed to a number of architectural features functions between data in the working register and any
commonly found in RISC microprocessors. To begin register file.
with, the PIC16C5X uses a Harvard architecture in
which program and data are accessed on separate The ALU is 8-bits wide and capable of addition,
buses. This improves bandwidth over traditional von subtraction, shift and logical operations. Unless
Neumann architecture where program and data are otherwise mentioned, arithmetic operations are two's
fetched on the same bus. Separating program and complement in nature. In two-operand instructions,
data memory further allows instructions to be sized typically one operand is the W (working) register. The
differently than the 8-bit wide data word. Instruction other operand is either a file register or an immediate
opcodes are 12-bits wide making it possible to have all constant. In single operand instructions, the operand
single word instructions. A 12-bit wide program is either the W register or a file register.
memory access bus fetches a 12-bit instruction in a The W register is an 8-bit working register used for
single cycle. A two-stage pipeline overlaps fetch and ALU operations. It is not an addressable register.
execution of instructions. Consequently, all
Depending on the instruction executed, the ALU may
instructions (33) execute in a single cycle (200ns @
affect the values of the Carry (C), Digit Carry (DC),
20MHz) except for program branches.
and Zero (Z) bits in the STATUS register. The C and
The PIC16C54A/CR54A/CR54B address 512 x 12 of DC bits operate as a borrow and digit borrow out bit,
program memory, the PIC16CR56 addresses 1K x 12 respectively, in subtraction. See the SUBWF and ADDWF
of program memory and the PIC16CR57A/CR57B and instructions for examples.
PIC16C58A/CR58A/CR58B address 2K x 12 of
A simplified block diagram is shown in Figure 3-1, with
program memory. All program memory is internal.
the corresponding device pins described in Table 3-1
The PIC16C5X can directly or indirectly address its and Table 3-2.
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C5X has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC16C5X simple yet efficient.
In addition, the learning curve is reduced significantly.

Enhanced PIC16C5X
FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM
9-11 T0CKI OSC1 OSC2 MCLR

EPROM/ROM 9-11 STACK 1 CONFIGURATION WORD
PIN
512 X 12 TO STACK 2 “DISABLE” “OSC
2048 X 12 PC SELECT”
12 WATCHDOG 2
TIMER “CODE
PROTECT” OSCILLATOR/
INSTRUCTION TIMING &
REGISTER CONTROL
9 WDT TIME WDT/TMR0 CLKOUT
12 OUT PRESCALER
8 “SLEEP”
INSTRUCTION
6
DECODER
OPTION REG. “OPTION”
DIRECT ADDRESS DIRECT RAM
FROM W GENERAL
ADDRESS
PURPOSE
5 REGISTER
FILE
8 5-7
(SRAM)
24, 25, 72 or
LITERALS
STATUS 73 Bytes
TMR0 FSR
8
DATA BUS
W ALU
8
FROM W FROM W FROM W
4 8 8
4 8 8
“TRIS 5” “TRIS 6” “TRIS 7”
TRISA PORTA TRISB PORTB TRISC PORTC
4 8 8
RA3:RA0 RB7:RB0 RC7:RC0

(28-Pin
Devices Only)

Enhanced PIC16C5X
TABLE 3-1: PINOUT DESCRIPTION - PIC16C54A, PIC16CR54A, PIC16CR54B, PIC16CR56,
PIC16C58A, PIC16CR58A, PIC16CR58B
DIP, SOIC SSOP I/O/P Input

Name Description
No. No. Type Levels
RA0 17 19 I/O TTL Bi-directional I/O port
RA1 18 20 I/O TTL
RA2 1 1 I/O TTL
RA3 2 2 I/O TTL
RB0 6 7 I/O TTL Bi-directional I/O port
RB1 7 8 I/O TTL
RB2 8 9 I/O TTL
RB3 9 10 I/O TTL
RB4 10 11 I/O TTL
RB5 11 12 I/O TTL
RB6 12 13 I/O TTL
RB7 13 14 I/O TTL
T0CKI 3 3 I ST Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
MCLR/VPP 4 4 I ST Master clear (reset) input/programming voltage input. This
pin is an active low reset to the device. Voltage on the
MCLR/VPP pin must not exceed VDD to avoid unintended
entering of programming mode.
OSC1/CLKIN 16 18 I ST Oscillator crystal input/external clock source input.
OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
VDD 14 15,16 P — Positive supply for logic and I/O pins.
VSS 5 5,6 P — Ground reference for logic and I/O pins.
Legend: I = input, O = output, I/O = input/output,
P = power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input

Enhanced PIC16C5X
TABLE 3-2: PINOUT DESCRIPTION - PIC16CR57A, PIC16CR57B
DIP, SOIC SSOP I/O/P Input

Name Description
No. No. Type Levels
RA0 6 5 I/O TTL Bi-directional I/O port
RA1 7 6 I/O TTL
RA2 8 7 I/O TTL
RA3 9 8 I/O TTL
RB0 10 9 I/O TTL Bi-directional I/O port
RB1 11 10 I/O TTL
RB2 12 11 I/O TTL
RB3 13 12 I/O TTL
RB4 14 13 I/O TTL
RB5 15 15 I/O TTL
RB6 16 16 I/O TTL
RB7 17 17 I/O TTL
RC0 18 18 I/O TTL Bi-directional I/O port
RC1 19 19 I/O TTL
RC2 20 20 I/O TTL
RC3 21 21 I/O TTL
RC4 22 22 I/O TTL
RC5 23 23 I/O TTL
RC6 24 24 I/O TTL
RC7 25 25 I/O TTL
T0CKI 1 2 I ST Clock input to Timer0. Must be tied to VSS or VDD if not in use
to reduce current consumption.
MCLR 28 28 I ST Master clear (reset) input. This pin is an active low reset to
the device.
OSC1/CLKIN 27 27 I ST Oscillator crystal input/external clock source input.
OSC2/CLKOUT 26 26 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
VDD 2 3,4 P — Positive supply for logic and I/O pins.
VSS 4 1,14 P — Ground reference for logic and I/O pins.
N/C 3,5 — — — Unused, do not connect
Legend: I = input, O = output, I/O = input/output,
P = power, — = Not Used,
TTL = TTL input, ST = Schmitt Trigger input

Enhanced PIC16C5X
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided An Instruction Cycle consists of four Q cycles (Q1, Q2,
by four to generate four non-overlapping quadrature Q3 and Q4). The instruction fetch and execute are
clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle
program counter is incremented every Q1, and the while decode and execute takes another instruction
instruction is fetched from program memory and cycle. However, due to the pipelining, each instruction
latched into instruction register in Q4. It is decoded effectively executes in one cycle. If an instruction
and executed during the following Q1 through Q4. The causes the program counter to change (e.g., GOTO)
clocks and instruction execution flow is shown in then two cycles are required to complete the
Figure 3-2 and Example 3-1. instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55H Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

Enhanced PIC16C5X
NOTES:

Enhanced PIC16C5X
4.0 MEMORY ORGANIZATION FIGURE 4-2: PIC16CR56 PROGRAM
MEMORY MAP AND STACK
PIC16C5X memory is organized into program memory
and data memory. For devices with more than 512 PC<9:0>
bytes of program memory, a paging scheme is used. 10
Program memory pages are accessed using one or CALL, RETLW
two STATUS register bits. For devices with a data Stack Level 1
memory register file of more than 32 registers, a Stack Level 2
banking scheme is used. Data memory banks are
accessed using the File Selection Register (FSR). 000h
On-chip Program
User Memory
0FFh
4.1 Program Memory Organization Memory (Page 0) 100h
Space
The PIC16C54A, PIC16CR54A and PIC16CR54B 1FFh
200h
have a 9-bit Program Counter (PC) capable of
On-chip Program
addressing a 512 x 12 program memory space 2FFh
Memory (Page 1) 300h
(Figure 4-1). The PIC16CR56 has a 10-bit Program
Counter capable of addressing a 1K x 12 program Reset Vector 3FFh
memory space (Figure 4-2). The PIC16CR57A,
PIC16CR57B, PIC16C58A, PIC16CR58A, and
PIC16CR58B have an 11-bit Program Counter FIGURE 4-3: PIC16CR57A/CR57B/C58A/CR
capable of addressing a 2K x 12 program memory 58A/CR58B PROGRAM
space (Figure 4-3). Accessing a location above the MEMORY MAP AND STACK
physically implemented address will cause a
wraparound. PC<10:0>
11
The reset vector for the PIC16C54A, PIC16CR54A CALL, RETLW
and PIC16CR54B is at 1FFh, for the PIC16CR56, at Stack Level 1
3FFh and for the PIC16CR57A, PIC16CR57B, Stack Level 2
PIC16C58A, PIC16CR58A, and PIC16CR58B, at
7FFh. 000h
On-chip Program 0FFh
FIGURE 4-1: PIC16C54A/CR54A/CR54B Memory (Page 0) 100h
PROGRAM MEMORY MAP
1FFh
AND STACK 200h
On-chip Program
User Memory
PC<8:0> 2FFh
9
Space
CALL, RETLW
3FFh
Stack Level 1 400h
Stack Level 2 On-chip Program
4FFh
000h
5FFh
User Memory
On-chip 600h
Space
Program 0FFh On-chip Program

100h 6FFh
Memory Memory (Page 3) 700h
Reset Vector 7FFh
Reset Vector 1FFh

Enhanced PIC16C5X
4.2 Data Memory Organization FIGURE 4-4: PIC16C54A/CR54A/CR54B/CR
56 REGISTER FILE MAP
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified File Address
by its register file. The register file is divided into two
00h INDF(1)
functional groups: special function registers and
general purpose registers. 01h TMR0
The special function registers include the TMR0 02h PCL
register, the Program Counter (PC), the Status 03h STATUS
Register, the I/O registers (ports), and the File Select
04h FSR
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and 05h PORTA
prescaler options. 06h PORTB
The general purpose registers are used for data and 07h
control information under command of the instructions.
For the PIC16C54A, PIC16CR54A, PIC16CR54B and
PIC16CR56, the register file is composed of 7 special General
0Fh
function registers and 25 general purpose registers Purpose
10h Registers
(Figure 4-4).
For the PIC16CR57A and PIC16CR57B, the register
file is composed of 8 special function registers, 24
general purpose registers and up to 48 additional 1Fh
general purpose registers that may be addressed
using a banking scheme (Figure 4-5). Note 1: Not a physical register. See Section 4.7
For the PIC16C58A, PIC16CR58A and PIC16CR58B,
the register file is composed of 7 special function
registers, 25 general purpose registers and up to 48
additional general purpose registers that may be
addressed using a banking scheme (Figure 4-6).
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly or indirectly

through the file select register FSR (Section 4.7).

Enhanced PIC16C5X
FIGURE 4-5: PIC16CR57A/CR57B REGISTER FILE MAP
FSR<6:5> 00 01 10 11
File Address
00h INDF(1) 20h 40h 60h
01h TMR0
02h PCL
03h STATUS
04h FSR
Addresses map back to
05h PORTA addresses in Bank 0.
06h PORTB
07h PORTC
08h General
Purpose
0Fh Registers 2Fh 4Fh 6Fh
10h 30h 50h 70h
General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
1Fh 3Fh 5Fh 7Fh

Bank 0 Bank 1 Bank 2 Bank 3
Note 1: Not a physical register. See Section 4.7
FIGURE 4-6: PIC16C58A/CR58A/CR58B REGISTER FILE MAP

FSR<6:5> 00 01 10 11
File Address
00h INDF(1) 20h 40h 60h
01h TMR0
02h PCL
03h STATUS
04h FSR
Addresses map back to
05h PORTA addresses in Bank 0.
06h PORTB
07h
General
Purpose
Registers
0Fh 2Fh 4Fh 6Fh
10h 30h 50h 70h
General General General General
Purpose Purpose Purpose Purpose
Registers Registers Registers Registers
1Fh 3Fh 5Fh 7Fh

Note 1: Not a physical register. See Section 4.7

Enhanced PIC16C5X
4.2.2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets.
The special function registers associated with the
The Special Function Registers are registers used by “core” functions are described in this section. Those
the CPU and peripheral functions to control the related to the operation of the peripheral features are
operation of the device (Table 4-1). described in the section for each peripheral feature.
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Value on Value on
Power-On MCLR and
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset WDT Reset
N/A TRIS I/O control registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 --11 1111
00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu
02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111

03h STATUS PA2 PA1 PA0 TO PD Z DC C 0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer 1xxx xxxx 1uuu uuuu
05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h(2) PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)
x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5
for an explanation of how to access these bits.
2: File address 07h is a general purpose register on the PIC16C54A, PIC16CR54A, PIC16CR54B, PIC16CR56,
PIC16C58A, PIC16CR58A and PIC16CR58B.

Enhanced PIC16C5X
4.3 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
This register contains the arithmetic status of the ALU, as 000u u1uu (where u = unchanged).
the RESET status, and the page preselect bits for
It is recommended, therefore, that only BCF, BSF and
program memories larger than 512 words.
MOVWF instructions be used to alter the STATUS
The STATUS register can be the destination for any register because these instructions do not affect the Z,
instruction, as with any other register. If the STATUS DC or C bits from the STATUS register. For other
register is the destination for an instruction that affects instructions, which do affect STATUS bits, see
the Z, DC or C bits, then the write to these three bits is Table 8-2, Instruction Set Summary.
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
FIGURE 4-7: STATUS REGISTER (ADDRESS:03h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

PA2 PA1 PA0 TO PD Z DC C R = Readable bit
bit7 6 5 4 3 2 1 bit0 W = Writable bit
- n = Value at POR reset
bit 7: PA2: This bit unused at this time.
Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.
bit 6-5: PA1:PA0: Program page preselect bits (PIC16CR56/CR57A/CR57B/C58A/CR58A/CR58B)
00 = Page 0 (000h - 1FFh) - PIC16C56 and PIC16CR57A/CR57B/C58A/CR58A/CR58B
01 = Page 1 (200h - 3FFh) - PIC16C56 and PIC16CR57A/CR57B/C58A/CR58A/CR58B
10 = Page 2 (400h - 5FFh) - PIC16CR57A/CR57B/C58A/CR58A/CR58B
11 = Page 3 (600h - 7FFh) - PIC16CR57A/CR57B/C58A/CR58A/CR58B
Each page is 512 bytes.
Using the PA1:PA0 bits as general purpose read/write bits in devices which do not use them for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4: TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF SUBWF RRF or RLF
1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred

Enhanced PIC16C5X
4.4 OPTION Register
The OPTION register is a 6-bit wide, write-only
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<5:0> bits.
FIGURE 4-8: OPTION REGISTER
U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1

— — T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit
bit7 6 5 4 3 2 1 bit0 U = Unimplemented bit
- n = Value at POR reset
bit 7-6: Unimplemented.
bit 5: T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: Timer0 source edge select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3: PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0: PS2:PS0: Prescaler rate select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

Enhanced PIC16C5X
4.5 Program Counter FIGURE 4-9: LOADING OF PC
BRANCH INSTRUCTIONS -
As a program instruction is executed, the Program
PIC16C54A/CR54A/CR54B
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is GOTO Instruction
increased by one every instruction cycle, unless an 8 7 0
instruction changes the PC. PCL
PC
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0> (Figure 4-9, Figure 4-10 and Instruction Word
Figure 4-11).
For the PIC16CR56, PIC16CR57A, PIC16CR57B, CALL or Modify PCL Instruction
PIC16C58A, PIC16CR58A and PIC16CR58B, a page 8 7 0
number must be supplied as well. Bit5 of the STATUS PC PCL
register provides this to bit9 of the PC for the
PIC16CR56 (Figure 4-10). Bit5 and bit6 of the
STATUS register provide page information to bit9 and Reset to '0' Instruction Word
bit10 of the PC for the PIC16CR57A, PIC16CR57B,
PIC16C58A, PIC16CR58A and PIC16CR58B
(Figure 4-11). FIGURE 4-10: LOADING OF PC
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are PIC16CR56
provided by the instruction word. However, PC<8> GOTO Instruction
does not come from the instruction word, but is always
cleared (Figure 4-9, Figure 4-10 and Figure 4-11). 9 8 7 0
PC PCL
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5. Instruction Word
For the PIC16CR56, PIC16CR57A, PIC16CR57B,
PIC16C58A, PIC16CR58A and PIC16CR58B, a page 7 PA0 0
number again must be supplied. Bit5 of the STATUS
register provides this to bit9 of the PC for the STATUS
PIC16CR56 (Figure 4-10). Bit5 and bit6 of the
STATUS register provide page information to bit9 and
bit10 of the PC for the PIC16CR57A, PIC16CR57B, CALL or Modify PCL Instruction
PIC16C58A, PIC16CR58A and PIC16CR58B 9 8 7 0
(Figure 4-11). PC PCL
Note: Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
Instruction Word
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro- Reset to '0'
gram memory page (512 words long).
7 PA0 0
STATUS

Enhanced PIC16C5X
FIGURE 4-11: LOADING OF PC 4.5.2 EFFECTS OF RESET
The Program Counter is set upon a RESET, which
PIC16CR57A/CR54B/C58A/CR
means that the PC addresses the last location in the
58A/CR58B last page i.e., the reset vector.
GOTO Instruction The STATUS register page preselect bits are cleared
10 9 8 7 0 upon a RESET, which means that page 0 is
PC PCL pre-selected.
Therefore, upon a RESET, a GOTO instruction at the
reset vector location will automatically cause the
Instruction Word
program to jump to page 0.
2 PA1:PA0
7 0 4.6 Stack
STATUS
PIC16C5X devices have a 9-bit, 10-bit or 11-bit wide,
two-level hardware push/pop stack (Figure 4-1,
Figure 4-2 and Figure 4-3 respectively).
CALL or Modify PCL Instruction
A CALL instruction will push the current value of stack
10 9 8 7 0 1 into stack 2 and then push the current program
PC PCL counter value, incremented by one, into stack level 1.
If more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
Instruction Word
A RETLW instruction will pop the contents of stack level
Reset to ‘0’
1 into the program counter and then copy stack level 2
2 PA1:PA0 contents into level 1. If more than two sequential
7 0 RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
STATUS W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
For the RETLW instruction, the PC is loaded with the implementation of data look-up tables within the
Top Of Stack (TOS) contents. All of the devices program memory.
covered in this data sheet have a two-level stack. The
stack has the same bit width as the device PC.
4.5.1 PAGING CONSIDERATIONS –

PIC16CR56/CR57A/CR57B/C58A/CR58A/C
R58B
If the Program Counter is pointing to the last address

of a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS
register will not be updated. Therefore, the next GOTO,
CALL, or Modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0
or PA1:PA0).
For example, a NOP at location 1FFh (page 0)
increments the PC to 200h (page 1). A GOTO xxx at
200h will return the program to address xxxh on page
0 (assuming that PA1:PA0 are clear).
To prevent this, the page preselect bits must be
updated under program control.

Enhanced PIC16C5X
4.7 Indirect Data Addressing; INDF and EXAMPLE 4-2: HOW TO CLEAR RAM
FSR Registers USING INDIRECT
ADDRESSING
The INDF register is not a physical register. movlw 0x10 ;initialize pointer
Addressing INDF actually addresses the register movwf FSR ; to RAM
whose address is contained in the FSR register (FSR NEXT clrf INDF ;clear INDF register
is a pointer). This is indirect addressing. incf FSR,F ;inc pointer
btfsc FSR,4 ;all done?
EXAMPLE 4-1: INDIRECT ADDRESSING goto NEXT ;NO, clear next
CONTINUE
• Register file 05 contains the value 10h
: ;YES, continue
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register The FSR is either a 5-bit (PIC16C54A, PIC16CR54A,
• A read of the INDF register will return the value or PIC16CR54B) or 7-bit (PIC16CR56, PIC16CR57A,
of 10h PIC16CR57B, PIC16C58A, PIC16CR58A, or
• Increment the value of the FSR register by one PIC16CR58B) wide register. It is used in conjunction
(FSR = 06) with the INDF register to indirectly address the data
• A read of the INDR register now will return the memory area. The last 2 bits, FSR<6:5>, are also
value of 0Ah. used on the PIC16C57 for direct addressing
(Figure 4-12).
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a The FSR<4:0> bits are used to select data memory
no-operation (although STATUS bits may be affected). addresses 00h to 1Fh.
A simple program to clear RAM locations 10h-1Fh PIC16C54A/CR54A/CR54B/CR56: Do not use
using indirect addressing is shown in Example 4-2. banking. FSR<6:5> are unimplemented and read
as '1's.
PIC16CR57A/CR57B/C58A/CR58A/CR58B:
FSR<6:5> are the bank select bits and are used to
select the bank to be addressed (00 = bank 0,
01 = bank 1, 10 = bank 2, 11 = bank 3).
FIGURE 4-12: DIRECT/INDIRECT ADDRESSING

Direct Addressing Indirect Addressing
(FSR)
6 5 4 (opcode) 0 6 5 4 (FSR) 0
bank select location select bank location select

00 01 10 11
00h
Addresses map back

to addresses in Bank 0.
Data 0Fh
Memory(1) 10h
1Fh 3Fh 5Fh 7Fh

Note 1: For register map detail see Section 4.2.

Enhanced PIC16C5X
NOTES:

Enhanced PIC16C5X
5.0 I/O PORTS 5.5 I/O Interfacing
As with any other register, the I/O registers can be The equivalent circuit for an I/O port pin is shown in
written and read under program control. However, Figure 5-1. All ports may be used for both input and
read instructions (e.g., MOVF PORTB,W) always read output operations. For input operations these ports are
the I/O pins independent of the pin’s input/output non-latching. Any input must be present until read by
modes. On RESET, all I/O ports are defined as input an input instruction (e.g., MOVF PORTB, W). The
(inputs are at hi-impedance) since the I/O control outputs are latched and remain unchanged until the
registers (TRISA, TRISB, TRISC) are all set. output latch is rewritten. To use a port pin as output,
the corresponding direction control bit (in TRISA,
5.1 PORTA TRISB, TRISC) must be cleared (= 0). For use as an
PORTA is a 4-bit I/O register. Only the low order 4 bits input, the corresponding TRIS bit must be set. Any I/O
are used (RA3:RA0). Bits 7-4 are unimplemented and pin can be programmed individually as input or output.
read as '0's. FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
5.2 PORTB
Data
PORTB is an 8-bit I/O register (PORTB<7:0>). Bus
D Q
5.3 PORTC Data
VDD
WR Latch
Port
PIC16CR57A/CR57B: 8-bit I/O register. CK Q
P
PIC16C54A/CR54A/CR54B/CR55/CR56/C58A/CR58
A/CR58B: General purpose register.
W N I/O
5.4 TRIS Registers Reg pin(1)
D Q
The output driver control registers are loaded with the TRIS
VSS
Latch
contents of the W register by executing the TRIS f TRIS ‘f’
instruction. A '1' from a TRIS register bit puts the CK Q
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. Reset
Note: A read of the ports reads the pins, not the

output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a RD Port
read of the port will indicate that the pin is
low. Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS registers are “write-only” and are set (output

drivers disabled) upon RESET.
TABLE 5-1: SUMMARY OF PORT REGISTERS
Value on Value on
Power-On MCLR and
N/A TRIS I/O control registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h(1) PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
Legend: Shaded boxes = unimplemented, read as ‘0’,
– = unimplemented, read as '0', x = unknown, u = unchanged
Note 1: File address 07h is a general purpose register on the PIC16C54/CR54/C56.

Enhanced PIC16C5X
5.6 I/O Programming Considerations EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
5.6.1 BI-DIRECTIONAL I/O PORTS
I/O PORT
Some instructions operate internally as read followed ;Initial PORT Settings
; PORTB<7:4> Inputs
by write operations. The BCF and BSF instructions, for
; PORTB<3:0> Outputs
example, read the entire port into the CPU, execute ;PORTB<7:6> have external pull-ups and are
the bit operation and re-write the result. Caution must ;not connected to other circuitry
be used when these instructions are applied to a port ;
where one or more pins are used as input/outputs. For ; PORT latch PORT pins
example, a BSF operation on bit5 of PORTB will cause ; ---------- ----------
all eight bits of PORTB to be read into the CPU, bit5 to BCF PORTB, 7 ;01pp pppp 11pp pppp
be set and the PORTB value to be written to the output BCF PORTB, 6 ;10pp pppp 11pp pppp
latches. If another bit of PORTB is used as a MOVLW 03Fh ;
bi-directional I/O pin (say bit0) and it is defined as an TRIS PORTB ;10pp pppp 10pp pppp
;
input at this time, the input signal present on the pin
;Note that the user may have expected the pin
itself would be read into the CPU and rewritten to the ;values to be 00pp pppp. The 2nd BCF caused
data latch of this particular pin, overwriting the ;RB7 to be latched as the pin value (High).
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched 5.6.2 SUCCESSIVE OPERATIONS ON I/O
into output mode later on, the content of the data latch PORTS
may now be unknown.
The actual write to an I/O port happens at the end of
Example 5-1 shows the effect of two sequential an instruction cycle, whereas for reading, the data
read-modify-write instructions (e.g., BCF, BSF, etc.) on must be valid at the beginning of the instruction cycle
an I/O port. (Figure 5-2). Therefore, care must be exercised if a
A pin actively outputting a high or a low should not be write followed by a read operation is carried out on the
driven from external devices at the same time in order same I/O port. The sequence of instructions should
to change the level on this pin (“wired-or”, allow the pin voltage to stabilize (load dependent)
“wired-and”). The resulting high output currents may before the next instruction, which causes that file to be
damage the chip. read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC + 1 PC + 2 PC + 3 This example shows a write to PORTB

Instruction followed by a read from PORTB.
fetched MOVWF PORTB MOVF PORTB,W NOP NOP
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
RB7:RB0
TPD = propagation delay
Port pin Port pin Therefore, at higher clock frequencies, a
written here sampled here write followed by a read may be problematic.
Instruction
executed MOVWF PORTB MOVF PORTB,W NOP
(Write to (Read
PORTB) PORTB)

Enhanced PIC16C5X
6.0 TIMER0 MODULE AND Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
TMR0 REGISTER either on every rising or falling edge of pin T0CKI. The
The Timer0 module has the following features: incrementing edge is determined by the source edge
• 8-bit timer/counter register, TMR0 select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
- Readable and writable
clock input are discussed in detail in Section 6.1.
• 8-bit software programmable prescaler
The prescaler may be used by either the Timer0
• Internal or external clock select
module or the Watchdog Timer, but not both. The
- Edge select for external clock prescaler assignment is controlled in software by the
Figure 6-1 is a simplified block diagram of the Timer0 control bit PSA (OPTION<3>). Clearing the PSA bit
module, while Figure 6-2 shows the electrical structure will assign the prescaler to Timer0. The prescaler is
of the Timer0 input. not readable or writable. When the prescaler is
Timer mode is selected by clearing the T0CS bit assigned to the Timer0 module, prescale values of
(OPTION<5>). In timer mode, the Timer0 module will 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details
increment every instruction cycle (without prescaler). If the operation of the prescaler.
TMR0 register is written, the increment is inhibited for A summary of registers associated with the Timer0
the following two cycles (Figure 6-3 and Figure 6-4). module is found in Table 6-1.
The user can work around this by writing an adjusted
value to the TMR0 register.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0 reg
T0CKI Programmable Clocks
0 PSout
pin Prescaler(2)
T0SE(1) (2 cycle delay) Sync
3
PS2, PS1, PS0(1) PSA(1)
T0CS(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6).
FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN
RIN
T0CKI (1) Schmitt Trigger

pin (1) N Input Buffer
VSS VSS
Note 1: ESD protection circuits

Enhanced PIC16C5X
FIGURE 6-3: TIMER0 TIMING:
INTERNAL CLOCK/NO PRESCALE
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Timer0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
FIGURE 6-4: TIMER0 TIMING:

INTERNAL CLOCK/PRESCALE 1:2
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
Timer0 T0 T0+1 NT0 NT0+1 T0
Instruction
Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
Value on Value on
Power-On MCLR and
01 TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111
Legend: Shaded cells: Unimplemented bits,
- = unimplemented, x = unknown, u = unchanged,

Enhanced PIC16C5X
6.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
When an external clock input is used for Timer0, it prescaler so that the prescaler output is symmetrical.
must meet certain requirements. The external clock For the external clock to meet the sampling
requirement is due to internal phase clock (TOSC) requirement, the ripple counter must be taken into
synchronization. Also, there is a delay in the actual account. Therefore, it is necessary for T0CKI to have a
incrementing of Timer0 after synchronization. period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
6.1.1 EXTERNAL CLOCK SYNCHRONIZATION
requirement on T0CKI high and low time is that they
When no prescaler is used, the external clock input is do not violate the minimum pulse width requirement of
the same as the prescaler output. The synchronization 10 ns. Refer to parameters 40, 41 and 42 in the
of T0CKI with the internal phase clocks is electrical specification of the desired device.
accomplished by sampling the prescaler output on the
6.1.2 TIMER0 INCREMENT DELAY
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be Since the prescaler output is synchronized with the
high for at least 2TOSC (and a small RC delay of 20 ns) internal clocks, there is a small delay from the time the
and low for at least 2TOSC (and a small RC delay of external clock edge occurs to the time the Timer0
20 ns). Refer to the electrical specification of the module is actually incremented. Figure 6-5 shows the
desired device. delay from the external clock edge to the timer
incrementing.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
External Clock Input or Small pulse
Prescaler Output (2) misses sampling
(1)
External Clock/Prescaler (3)
Output After Sampling
Increment Timer0 (Q4)
Timer0 T0 T0 + 1 T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.

Enhanced PIC16C5X
6.2 Prescaler following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
An 8-bit counter is available as a prescaler for the Timer0 to the WDT.
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 6.1.2). For EXAMPLE 6-1: CHANGING PRESCALER
simplicity, this counter is being referred to as
(TIMER0→WDT)
“prescaler” throughout this data sheet. Note that the CLRF TMR0 ;Clear TMR0
prescaler may be used by either the Timer0 module or CLRWDT ;Clears WDT and
the WDT, but not both. Thus, a prescaler assignment ;prescaler
for the Timer0 module means that there is no MOVLW 'xxxx1xxx' ;Select new prescale
prescaler for the WDT, and vice-versa. OPTION ;value
The PSA and PS2:PS0 bits (OPTION<3:0>) To change prescaler from the WDT to the Timer0
determine prescaler assignment and prescale ratio. module, use the sequence shown in Example 6-2. This
When assigned to the Timer0 module, all instructions sequence must be used even if the WDT is disabled. A
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, CLRWDT instruction should be executed before switching
BSF 1,x, etc.) will clear the prescaler. When the prescaler.
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT. The prescaler is neither EXAMPLE 6-2: CHANGING PRESCALER
readable nor writable. On a RESET, the prescaler (WDT→TIMER0)
contains all '0's. CLRWDT ;Clear WDT and
;prescaler
6.2.1 SWITCHING PRESCALER ASSIGNMENT MOVLW 'xxxx0xxx' ;Select TMR0, new
;prescale value and
The prescaler assignment is fully under software control ;clock source
(i.e., it can be changed “on the fly” during program OPTION
execution). To avoid an unintended device RESET, the
FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
0 8
M 1
T0CKI U M
1 X Sync
pin U 2 TMR0 reg
0 X Cycles
T0SE
T0CS
PSA
0
8-bit Prescaler
M
U
1 X
Watchdog 8
Timer
8 - to - 1MUX PS2:PS0
PSA
0 1
WDT Enable bit
MUX PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

Enhanced PIC16C5X
7.0 SPECIAL FEATURES OF THE The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake up
CPU from SLEEP through external reset or through a
What sets a microcontroller apart from other Watchdog Timer time-out. Several oscillator options
processors are special circuits to deal with the needs are also made available to allow the part to fit the
of real-time applications. The PIC16C5X family of application. The RC oscillator option saves system
microcontrollers has a host of such features intended cost while the LP crystal option saves power. A set of
to maximize system reliability, minimize cost through configuration bits are used to select various options.
elimination of external components, provide power
saving operating modes and offer code protection. 7.1 Configuration Bits
These features are:
The PIC16C5X configuration word consists of 4 or 12
• Oscillator selection bits, depending on device configuration. Configuration
• Reset bits can be programmed to select various device
• Power-On Reset (POR) configurations. Two bits are for the selection of the
• Device Reset Timer (DRT) oscillator type and one bit is the Watchdog Timer
enable bit. One bit is the code protection bit
• Watchdog Timer (WDT)
(Figure 7-1) for the PIC16C54A, PIC16CR57A or
• SLEEP PIC16C58A devices. Nine bits are code protection
• Code protection bits (Figure 7-2) for the PIC16CR54A, PIC16CR54B,
• ID locations PIC16CR56, PIC16CR57B, PIC16CR58A or
The PIC16C5X has a Watchdog Timer which can be PIC16CR58B devices.
shut off only through configuration bit WDTE. It runs OTP, QTP or ROM devices have the oscillator
off of its own RC oscillator for added reliability. There configuration programmed at the factory and these
is an 18 ms delay provided by the Device Reset Timer parts are tested accordingly (see "Product
(DRT), intended to keep the chip in reset until the Identification System" on the inside back cover).
crystal oscillator is stable. With this timer on-chip, most
applications need no external reset circuitry.
FIGURE 7-1: CONFIGURATION WORD FOR PIC16C54A/CR57A/C58A
— — — — — — — — CP WDTE FOSC1 FOSC0 Register: CONFIG

bit11 10 9 8 7 6 5 4 3 2 1 bit0 Address(1): FFFh
bit 11-4: Unimplemented: Read as ’0’
bit 3: CP: Code protection bit.
1 = Code protection off
0 = Code protection on
bit 2: WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC16C5X Programming Specifications (literature number DS30190) to deter-
mine how to access the configuration word.

Enhanced PIC16C5X
FIGURE 7-2: CONFIGURATION WORD FOR PIC16CR54A/CR54B/CR56/CR57B/CR58A/CR58B
CP CP CP CP CP CP CP CP CP WDTE FOSC1 FOSC0 Register: CONFIG

bit11 10 9 8 7 6 5 4 3 2 1 bit0 Address(1): FFFh
bit 11-3: CP: Code protection bits
1 = Code protection off
0 = Code protection on
bit 2: WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Refer to the PIC16C5X Programming Specifications (literature number DS30190) to deter-
mine how to access the configuration word.
7.2 Oscillator Configurations FIGURE 7-3: CRYSTAL OPERATION (OR

CERAMIC RESONATOR) (HS,
7.2.1 OSCILLATOR TYPES
XT OR LP OSC
The PIC16C5X can be operated in four different CONFIGURATION)
oscillator modes. The user can program two C1(1) OSC1 PIC16C5X
configuration bits (FOSC1:FOSC0) to select one of
these four modes:
SLEEP
• LP: Low Power Crystal XTAL RF(3)
• XT: Crystal/Resonator To internal
logic
• HS: High Speed Crystal/Resonator OSC2
RS(2)
• RC: Resistor/Capacitor C2(1)
7.2.2 CRYSTAL OSCILLATOR / CERAMIC Note 1: See Capacitor Selection tables for
RESONATORS recommended values of C1 and C2.
2: A series resistor (RS) may be required for
In XT, LP or HS modes, a crystal or ceramic resonator AT strip cut crystals.
is connected to the OSC1/CLKIN and OSC2/CLKOUT 3: RF varies with the crystal chosen
pins to establish oscillation (Figure 7-3). The (approx. value = 10 MΩ).
PIC16C5X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers FIGURE 7-4: EXTERNAL CLOCK INPUT
specifications. When in XT, LP or HS modes, the OPERATION (HS, XT OR LP
device can have an external clock source drive the OSC CONFIGURATION)
OSC1/CLKIN pin (Figure 7-4).
Clock from OSC1

ext. system PIC16C5X
Open OSC2

Enhanced PIC16C5X
TABLE 7-1: CAPACITOR SELECTION TABLE 7-3: CAPACITOR SELECTION
FOR CERAMIC RESONATORS FOR CERAMIC RESONATORS
- ENH. PIC16C5X - ENH. PIC16CR5X
Osc Resonator Cap. Range Cap. Range Osc Resonator Cap. Range Cap. Range
Type Freq C1
R Y
C2 Type Freq C1 C2
XT 455 kHz
2.0 MHz IN A
68-100 pF
15-33 pF
68-100 pF
15-33 pF Data not available at this time.
4.0 MHz
L IM 10-22 pF 10-22 pF
HS
E
8.0 MHz 10-22 pF 10-22 pF
PR
16.0 MHz 10 pF 10 pF
TABLE 7-4: CAPACITOR SELECTION
These values are for design guidance only. Since FOR CRYSTAL OSCILLATOR
each resonator has its own characteristics, the user
should consult the resonator manufacturer for - ENH. PIC16CR5X
appropriate values of external components. Osc Resonator Cap.Range Cap. Range
TABLE 7-2: CAPACITOR SELECTION Type Freq C1 C2
FOR CRYSTAL OSCILLATOR LP 32 kHz(1) 15-33 pF 15-33 pF
- ENH. PIC16C5X 100 kHz 15-33 pF 15-33 pF
200 kHz 15-30 pF 15-30 pF
Osc Resonator Cap.Range Cap. Range
XT 100 kHz 68-100 pF
R Y 68-100 pF
Type
LP
Freq
32 kHz(1)
C1
15 pF
C2
15 pF
200 kHz
1 MHz
I
15-30 pF
N
15-47 pF
A 15-30 pF
15-47 pF
XT 100 kHz 15-30 pF 200-300 pF 2 MHz
L I M 15-47 pF 15-47 pF
200 kHz
455 kHz
15-30 pF
15-30 pF
100-200 pF
15-100 pF HS
R E 4 MHz
4 MHz
15-47 pF
15-47 pF
15-47 pF
15-47 pF
1 MHz
2 MHz
15-30 pF
15 pF
15-30 pF
15 pF
P 8 MHz
20 MHz
15-47 pF
15-47 pF
15-47 pF
15-47 pF
4 MHz 15 pF 15 pF Note 1: For VDD < 2.5V, C1 = C2 ≈ 15-33 pF is
HS 4 MHz 15 pF 15 pF recommended.
8 MHz 15 pF 15 pF These values are for design guidance only. Rs may
20 MHz 15 pF 15 pF be required in HS mode as well as XT mode to avoid
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is overdriving crystals with low drive level specification.
recommended. Since each crystal has its own characteristics, the
These values are for design guidance only. Rs may user should consult the crystal manufacturer for
be required in HS mode as well as XT mode to avoid appropriate values of external components.
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.

Enhanced PIC16C5X
7.2.3 EXTERNAL CRYSTAL OSCILLATOR 7.2.4 RC OSCILLATOR
CIRCUIT
For timing insensitive applications, the RC device
Either a prepackaged oscillator or a simple oscillator option offers additional cost savings. The RC oscillator
circuit with TTL gates can be used as an external frequency is a function of the supply voltage, the
crystal oscillator circuit. Prepackaged oscillators resistor (Rext) and capacitor (Cext) values, and the
provide a wide operating range and better stability. A operating temperature. In addition to this, the oscillator
well-designed crystal oscillator will provide good frequency will vary from unit to unit due to normal
performance with TTL gates. Two types of crystal process parameter variation. Furthermore, the
oscillator circuits can be used: one with parallel difference in lead frame capacitance between package
resonance, or one with series resonance. types will also affect the oscillation frequency,
Figure 7-5 shows implementation of a parallel especially for low Cext values. The user also needs to
resonant oscillator circuit. The circuit is designed to take into account variation due to tolerance of external
use the fundamental frequency of the crystal. The R and C components used.
74AS04 inverter performs the 180-degree phase shift Figure 7-7 shows how the R/C combination is
that a parallel oscillator requires. The 4.7 kΩ resistor connected to the PIC16C5X. For Rext values below
provides the negative feedback for stability. The 10 kΩ 2.2 kΩ, the oscillator operation may become unstable,
potentiometers bias the 74AS04 in the linear region. or stop completely. For very high Rext values
This circuit could be used for external oscillator (e.g., 1 MΩ) the oscillator becomes sensitive to noise,
designs. humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
FIGURE 7-5: EXTERNAL PARALLEL
RESONANT CRYSTAL Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
OSCILLATOR CIRCUIT
above 20 pF for noise and stability reasons. With no or
+5V small external capacitance, the oscillation frequency
To Other can vary dramatically due to changes in external
Devices
10k PIC16C5X capacitances, such as PCB trace capacitance or
4.7k 74AS04 package lead frame capacitance.
74AS04 CLKIN The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
10k (since leakage current variation will affect RC
XTAL frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
10k more).
Also, see the Electrical Specifications sections for
20 pF 20 pF
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
Figure 7-6 shows a series resonant oscillator circuit. operating temperature for given R, C, and VDD values.
This circuit is also designed to use the fundamental The oscillator frequency, divided by 4, is available on
frequency of the crystal. The inverter performs a the OSC2/CLKOUT pin, and can be used for test
180-degree phase shift in a series resonant oscillator purposes or to synchronize other logic.
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region. FIGURE 7-7: RC OSCILLATOR MODE
FIGURE 7-6: EXTERNAL SERIES VDD
RESONANT CRYSTAL
OSCILLATOR CIRCUIT Rext Internal
OSC1 clock
To Other
330 330 Devices
PIC16C5X
74AS04 74AS04 74AS04 N PIC16C5X
Cext
CLKIN
VSS
0.1 µF
Fosc/4
XTAL OSC2/CLKOUT

Enhanced PIC16C5X
7.3 Reset Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in
PIC16C5X devices may be reset in one of the any other reset. Most other registers are reset to a
following ways: “reset state” on Power-On Reset (POR), MCLR or
• Power-On Reset (POR) WDT reset. A MCLR or WDT wake-up from SLEEP
• MCLR reset (normal operation) also results in a device reset, and not a continuation of
operation before SLEEP.
• MCLR wake-up reset (from SLEEP)
• WDT reset (normal operation) The TO and PD bits (STATUS <4:3>) are set or
cleared depending on the different reset conditions
• WDT wake-up reset (from SLEEP)
(Section 7.7). These bits may be used to determine
Table 7-5 shows these reset conditions for the PCL the nature of the reset.
and STATUS registers.
Table 7-6 lists a full description of reset states of all
registers. Figure 7-8 shows a simplified block diagram
of the on-chip reset circuit.
TABLE 7-5: RESET CONDITIONS FOR SPECIAL REGISTERS
PCL STATUS
Condition
Addr: 02h Addr: 03h
Power-On Reset 1111 1111 0001 1xxx
MCLR reset (normal operation) 1111 1111 000u uuuu(1)
MCLR wake-up (from SLEEP) 1111 1111 0001 0uuu
WDT reset (normal operation) 1111 1111 0000 1uuu(2)
WDT wake-up (from SLEEP) 1111 1111 0000 0uuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.
Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.
2: The CLRWDT instruction will set the TO and PD bits.
TABLE 7-6: RESET CONDITIONS FOR ALL REGISTERS
Register Address Power-On Reset MCLR or WDT Reset
W N/A xxxx xxxx uuuu uuuu
TRIS N/A 1111 1111 1111 1111
OPTION N/A --11 1111 --11 1111
INDF 00h xxxx xxxx uuuu uuuu
TMR0 01h xxxx xxxx uuuu uuuu
PCL(1) 02h 1111 1111 1111 1111
STATUS(1) 03h 0001 1xxx 000q quuu

FSR 04h 1xxx xxxx 1uuu uuuu
PORTA 05h ---- xxxx ---- uuuu
PORTB 06h xxxx xxxx uuuu uuuu
PORTC(2) 07h xxxx xxxx uuuu uuuu
General Purpose 08-7Fh xxxx xxxx uuuu uuuu
register files
Legend: u = unchanged, x = unknown, - = unimplemented, read as '0',
q = see tables in Section 7.7 for possible values.
Note 1: See Table 7-5 for reset value for specific conditions.
2: General purpose register file on the PIC16C54/CR54/C56.

Enhanced PIC16C5X
FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
VDD POR (Power-On Reset)
MCLR/VPP pin WDT Time-out

RESET
8-bit Asynch S Q
On-Chip Ripple Counter
RC OSC (Start-Up Timer)
R Q
CHIP RESET

Enhanced PIC16C5X
7.4 Power-On Reset (POR) FIGURE 7-9: ELECTRICAL STRUCTURE OF
MCLR/VPP PIN
The PIC16C5X family incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip RIN
reset for most power-up situations. To use this feature,
the user merely ties the MCLR/VPP pin (Figure 7-9) to
VDD. A simplified block diagram of the on-chip (1)
MCLR/VPP Schmitt Trigger
Power-On Reset circuit is shown in Figure 7-8. (1) N
Pin Input Buffer
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR VSS VSS
to be high. After the time-out period, which is typically
Note 1: ESD protection circuits
18 ms, it will reset the reset latch and thus end the
on-chip reset signal.
FIGURE 7-10: EXTERNAL POWER-ON
A power-up example where MCLR is not tied to VDD is RESET CIRCUIT (FOR SLOW
shown in Figure 7-11. VDD is allowed to rise and VDD POWER-UP)
stabilize before bringing MCLR high. The chip will
VDD VDD
actually come out of reset TDRT msec after MCLR
goes high.
D R
In Figure 7-12, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together). The R1
VDD is stable before the start-up timer times out and MCLR
there is no problem in getting a proper reset. However, C PIC16C5X
Figure 7-13 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses a high on the MCLR/VPP pin, and when the • External Power-On Reset circuit is required
MCLR/VPP pin (and VDD) actually reach their full only if VDD power-up is too slow. The diode D
value, is too long. In this situation, when the start-up helps discharge the capacitor quickly when
timer times out, VDD has not reached the VDD (min) VDD powers down.
value and the chip is, therefore, not guaranteed to
• R < 40 kΩ is recommended to make sure that
function correctly. For such situations, we recommend
voltage drop across R does not violate the
that external RC circuits be used to achieve longer
device electrical specification.
POR delay times (Figure 7-10).
• R1 = 100Ω to 1 kΩ will limit any current
Note: When the device starts normal operation flowing into MCLR from external capacitor C
(exits the reset condition), device operat- in the event of MCLR pin breakdown due to
ing parameters (voltage, frequency, tem- Electrostatic Discharge (ESD) or Electrical
perature, etc.) must be meet to ensure Overstress (EOS).
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
For more information on PIC16C5X POR, see
Power-Up Considerations - AN522 in the Embedded
Control Handbook.
The POR circuit does not produce an internal reset
when VDD declines.

Enhanced PIC16C5X
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

Enhanced PIC16C5X
7.5 Device Reset Timer (DRT) 7.6 Watchdog Timer (WDT)
The Device Reset Timer (DRT) provides a fixed 18 ms The Watchdog Timer (WDT) is a free running on-chip
nominal time-out on reset. The DRT operates on an RC oscillator which does not require any external
internal RC oscillator. The processor is kept in RESET components. This RC oscillator is separate from the
as long as the DRT is active. The DRT delay allows RC oscillator of the OSC1/CLKIN pin. That means that
VDD to rise above VDD min., and for the oscillator to the WDT will run even if the clock on the OSC1/CLKIN
stabilize. and OSC2/CLKOUT pins have been stopped, for
Oscillator circuits based on crystals or ceramic example, by execution of a SLEEP instruction. During
resonators require a certain time after power-up to normal operation or SLEEP, a WDT reset or wake-up
establish a stable oscillation. The on-chip DRT keeps reset generates a device RESET.
the device in a RESET condition for approximately 18 The TO bit (STATUS<4>) will be cleared upon a
ms after the voltage on the MCLR/VPP pin has Watchdog Timer reset.
reached a logic high (VIHMC) level. Thus, external RC The WDT can be permanently disabled by
networks connected to the MCLR input are not programming the configuration bit WDTE as a '0'
required in most cases, allowing for savings in (Section 7.1). Refer to the PIC16C5X Programming
cost-sensitive and/or space restricted applications. Specifications (literature number DS30190) to
The Device Reset time delay will vary from chip to chip determine how to access the configuration word.
due to VDD, temperature, and process variation. See
AC parameters for details. 7.6.1 WDT PERIOD
The DRT will also be triggered upon a Watchdog The WDT has a nominal time-out period of 18 ms,
Timer time-out. This is particularly important for (with no prescaler). If a longer time-out period is
applications using the WDT to wake the PIC16C5X desired, a prescaler with a division ratio of up to 1:128
from SLEEP mode automatically. can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, time-out a
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and
part-to-part process variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2 WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.

Enhanced PIC16C5X
FIGURE 7-14: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
M Postscaler
Watchdog 1 Postscaler
U
Timer
X
8 - to - 1 MUX PS2:PS0
WDT Enable PSA

EPROM Bit
To Timer0 (Figure 6-5)
0 1
MUX PSA
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 7-7: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on Value on
Power-On MCLR and
N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111
Legend: Shaded boxes = Not used by Watchdog Timer,
– = unimplemented, read as '0', u = unchanged

Enhanced PIC16C5X
7.7 Time-Out Sequence and Power Down 7.8 Reset on Brown-Out
Status Bits (TO/PD)
A brown-out is a condition where device power (VDD)
The TO and PD bits in the STATUS register can be dips below its minimum value, but not to zero, and
tested to determine if a RESET condition has been then recovers. The device should be reset in the event
caused by a power-up condition, a MCLR or of a brown-out.
Watchdog Timer (WDT) reset, or a MCLR or WDT To reset PIC16C5X devices when a brown-out occurs,
wake-up reset. external brown-out protection circuits may be built, as
shown in Figure 7-15 and Figure 7-16.
TABLE 7-8: TO/PD STATUS AFTER
RESET FIGURE 7-15: BROWN-OUT PROTECTION
CIRCUIT 1
TO PD RESET was caused by
1 1 Power-up (POR) VDD
u u MCLR reset (normal operation)(1)
1 0 MCLR wake-up reset (from SLEEP) VDD
33k
0 1 WDT reset (normal operation)
0 0 WDT wake-up reset (from SLEEP) Q1
10k MCLR
Legend: u = unchanged
Note 1: The TO and PD bits maintain their status (u) until 40k
a reset occurs. A low-pulse on the MCLR input PIC16C5X
does not change the TO and PD status bits.
These STATUS bits are only affected by events listed

in Table 7-9. This circuit will activate reset when VDD goes below Vz +
0.7V (where Vz = Zener voltage).
TABLE 7-9: EVENTS AFFECTING TO/PD
STATUS BITS
Event TO PD Remarks
FIGURE 7-16: BROWN-OUT PROTECTION
Power-up 1 1
CIRCUIT 2
WDT Time-out 0 u No effect on PD
VDD
SLEEP instruction 1 0
CLRWDT instruction 1 1
VDD
Legend: u = unchanged
R1
A WDT time-out will occur regardless of the status of the TO
bit. A SLEEP instruction will be executed, regardless of the Q1
status of the PD bit. Table 7-8 reflects the status of TO and MCLR
PD after the corresponding event. R2 40k
PIC16C5X
Table 7-5 lists the reset conditions for the special
function registers, while Table 7-6 lists the reset
conditions for all the registers.
This brown-out circuit is less expensive, although

less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
R1
VDD • = 0.7V
R1 + R2

Enhanced PIC16C5X
7.9 Power-Down Mode (SLEEP) 7.10 Program Verification/Code Protection
A device may be powered down (SLEEP) and later If the code protection bit(s) have not been
powered up (Wake-up from SLEEP). programmed, the on-chip program memory can be
read out for verification purposes.
7.9.1 SLEEP
Note: Microchip does not recommend code pro-
The Power-Down mode is entered by executing a tecting windowed devices.
SLEEP instruction.
7.11 ID Locations
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD Four memory locations are designated as ID locations
bit (STATUS<3>) is cleared and the oscillator driver is where the user can store checksum or other
turned off. The I/O ports maintain the status they had code-identification numbers. These locations are not
before the SLEEP instruction was executed (driving accessible during normal execution but are readable
high, driving low, or hi-impedance). and writable during program/verify.
It should be noted that a RESET generated by a WDT Use only the lower 4 bits of the ID locations and
time-out does not drive the MCLR/VPP pin low. always program the upper 8 bits as '1's.
For lowest current consumption while powered down,
Note: Microchip will assign a unique pattern
the T0CKI input should be at VDD or VSS and the
number for QTP and SQTP requests and
MCLR/VPP pin must be at a logic high level (VIHMC).
for ROM devices. This pattern number will
7.9.2 WAKE-UP FROM SLEEP be unique and traceable to the submitted
code.
The device can wake up from SLEEP through one of
the following events:
1. An external reset input on MCLR/VPP pin.
2. A Watchdog Timer time-out reset (if WDT was
enabled).
Both of these events cause a device reset. The TO
and PD bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.

Enhanced PIC16C5X
8.0 INSTRUCTION SET SUMMARY All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
Each PIC16C5X instruction is a 12-bit word divided
program counter is changed as a result of an
into an OPCODE, which specifies the instruction type,
instruction. In this case, the execution takes two
and one or more operands which further specify the
instruction cycles. One instruction cycle consists of
operation of the instruction. The PIC16C5X instruction
four oscillator periods. Thus, for an oscillator
set summary in Table 8-2 groups the instructions into
frequency of 4 MHz, the normal instruction execution
byte-oriented, bit-oriented, and literal and control
time is 1 µs. If a conditional test is true or the program
operations. Table 8-1 shows the opcode field
counter is changed as a result of an instruction, the
descriptions.
instruction execution time is 2 µs.
For byte-oriented instructions, 'f' represents a file
Figure 8-1 shows the three general formats that the
register designator and 'd' represents a destination
instructions can have. All examples in the figure use the
designator. The file register designator is used to
following format to represent a hexadecimal number:
specify which one of the 32 file registers is to be used
by the instruction. 0xhhh
The destination designator specifies where the result where 'h' signifies a hexadecimal digit.
of the operation is to be placed. If 'd' is '0', the result is
FIGURE 8-1: GENERAL FORMAT FOR
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
INSTRUCTIONS
Byte-oriented file register operations
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected 11 6 5 4 0
by the operation, while 'f' represents the number of the OPCODE d f (FILE #)
file in which the bit is located. d = 0 for destination W
For literal and control operations, 'k' represents an d = 1 for destination f
f = 5-bit file register address
8 or 9-bit constant or literal value.
Bit-oriented file register operations
TABLE 8-1: OPCODE FIELD
11 8 7 5 4 0
DESCRIPTIONS
OPCODE b (BIT #) f (FILE #)
Field Description b = 3-bit bit address
f Register file address (0x00 to 0x7F) f = 5-bit file register address
W Working register (accumulator) Literal and control operations (except GOTO)

b Bit address within an 8-bit file register 11 8 7 0
k Literal field, constant data or label OPCODE k (literal)
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is k = 8-bit immediate value
x
the recommended form of use for compatibility
Literal and control operations - GOTO instruction
with all Microchip software tools.
Destination select; 11 9 8 0
d = 0 (store result in W) OPCODE k (literal)
d
d = 1 (store result in file register 'f')
Default is d = 1 k = 9-bit immediate value
label Label name
TOS Top of Stack
PC Program Counter
WDT Watchdog Timer Counter
TO Time-Out bit
PD Power-Down bit
Destination, either the W register or the specified
dest register file location
[ ] Options
( ) Contents
→ Assigned to
<> Register bit field
∈ In the set of
italics User defined term (font is courier)

Enhanced PIC16C5X
TABLE 8-2: INSTRUCTION SET SUMMARY
12-Bit Opcode
Mnemonic, Status
Operands Description Cycles MSb LSb Affected Notes
ADDWF f,d Add W and f 1 0001 11df ffff C,DC,Z 1,2,4
ANDWF f,d AND W with f 1 0001 01df ffff Z 2,4
CLRF f Clear f 1 0000 011f ffff Z 4
CLRW – Clear W 1 0000 0100 0000 Z
COMF f, d Complement f 1 0010 01df ffff Z
DECF f, d Decrement f 1 0000 11df ffff Z 2,4
DECFSZ f, d Decrement f, Skip if 0 1(2) 0010 11df ffff None 2,4
INCF f, d Increment f 1 0010 10df ffff Z 2,4
INCFSZ f, d Increment f, Skip if 0 1(2) 0011 11df ffff None 2,4
IORWF f, d Inclusive OR W with f 1 0001 00df ffff Z 2,4
MOVF f, d Move f 1 0010 00df ffff Z 2,4
MOVWF f Move W to f 1 0000 001f ffff None 1,4
NOP – No Operation 1 0000 0000 0000 None
RLF f, d Rotate left f through Carry 1 0011 01df ffff C 2,4
RRF f, d Rotate right f through Carry 1 0011 00df ffff C 2,4
SUBWF f, d Subtract W from f 1 0000 10df ffff C,DC,Z 1,2,4
SWAPF f, d Swap f 1 0011 10df ffff None 2,4
XORWF f, d Exclusive OR W with f 1 0001 10df ffff Z 2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 0100 bbbf ffff None 2,4
BSF f, b Bit Set f 1 0101 bbbf ffff None 2,4
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 0110 bbbf ffff None
BTFSS f, b Bit Test f, Skip if Set 1 (2) 0111 bbbf ffff None
LITERAL AND CONTROL OPERATIONS
ANDLW k AND literal with W 1 1110 kkkk kkkk Z
CALL k Call subroutine 2 1001 kkkk kkkk None 1
CLRWDT k Clear Watchdog Timer 1 0000 0000 0100 TO, PD
GOTO k Unconditional branch 2 101k kkkk kkkk None
IORLW k Inclusive OR Literal with W 1 1101 kkkk kkkk Z
MOVLW k Move Literal to W 1 1100 kkkk kkkk None
OPTION k Load OPTION register 1 0000 0000 0010 None
RETLW k Return, place Literal in W 2 1000 kkkk kkkk None
SLEEP – Go into standby mode 1 0000 0000 0011 TO, PD
TRIS f Load TRIS register 1 0000 0000 0fff None 3
XORLW k Exclusive OR Literal to W 1 1111 kkkk kkkk Z
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except forGOTO.
(Section 4.5)
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 5, 6, or 7 causes the contents of the W register to be written to the tristate
latches of PORTA, B or C, respectively. A '1' forces the pin to a hi-impedance state and disables the output buff-
ers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).

Enhanced PIC16C5X
ADDWF Add W and f ANDWF AND W with f

Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d
Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ f ≤ 31
d ∈ [0,1] d ∈ [0,1]
Operation: (W) + (f) → (dest) Operation: (W) .AND. (f) → (dest)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 0001 11df ffff Encoding: 0001 01df ffff
Description: Add the contents of the W register and Description: The contents of the W register are
register 'f'. If 'd' is 0 the result is stored AND’ed with register 'f'. If 'd' is 0 the
in the W register. If 'd' is '1' the result is result is stored in the W register. If 'd' is
stored back in register 'f'. '1' the result is stored back in register 'f'.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example: ADDWF FSR, 0 Example: ANDWF FSR, 1
Before Instruction Before Instruction
W = 0x17 W = 0x17
FSR = 0xC2 FSR = 0xC2
After Instruction After Instruction
W = 0xD9 W = 0x17
FSR = 0xC2 FSR = 0x02
ANDLW And literal with W BCF Bit Clear f

Syntax: [ label ] ANDLW k Syntax: [ label ] BCF f,b
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 31
Operation: (W).AND. (k) → (W) 0≤b≤7
Status Affected: Z Operation: 0 → (f<b>)
Encoding: 1110 kkkk kkkk Status Affected: None
Description: The contents of the W register are Encoding: 0100 bbbf ffff
AND’ed with the eight-bit literal 'k'. The Description: Bit 'b' in register 'f' is cleared.
result is placed in the W register.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Example: BCF FLAG_REG, 7
Example: ANDLW 0x5F
Before Instruction
Before Instruction FLAG_REG = 0xC7
W = 0xA3
After Instruction
After Instruction FLAG_REG = 0x47
W = 0x03

Enhanced PIC16C5X
BSF Bit Set f BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BSF f,b Syntax: [ label ] BTFSS f,b
0≤b≤7 0≤b<7
Operation: 1 → (f<b>) Operation: skip if (f<b>) = 1
Status Affected: None Status Affected: None
Encoding: 0101 bbbf ffff Encoding: 0111 bbbf ffff
Description: Bit 'b' in register 'f' is set. Description: If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
Words: 1
If bit 'b' is '1', then the next instruction
Cycles: 1 fetched during the current instruction
Example: BSF FLAG_REG, 7 execution, is discarded and an NOP is
executed instead, making this a 2 cycle
Before Instruction instruction.
FLAG_REG = 0x0A
Words: 1
After Instruction
FLAG_REG = 0x8A
Cycles: 1(2)
Example: HERE BTFSS FLAG,1
FALSE GOTO PROCESS_CODE
TRUE •
BTFSC Bit Test f, Skip if Clear
•
Syntax: [ label ] BTFSC f,b •
Operands: 0 ≤ f ≤ 31 Before Instruction
0≤b≤7 PC = address (HERE)
Operation: skip if (f<b>) = 0 After Instruction
If FLAG<1> = 0,
Status Affected: None PC = address (FALSE);
Encoding: 0110 bbbf ffff if FLAG<1> = 1,
PC = address (TRUE)
Description: If bit 'b' in register 'f' is 0 then the next
instruction is skipped.
If bit 'b' is 0 then the next instruction
fetched during the current instruction
execution is discarded, and an NOP is
executed instead, making this a 2 cycle
instruction.
Words: 1
Cycles: 1(2)
Example: HERE BTFSC FLAG,1
FALSE GOTO PROCESS_CODE
TRUE •
•
•
Before Instruction
PC = address (HERE)
After Instruction
if FLAG<1> = 0,
PC = address (TRUE);
if FLAG<1> = 1,
PC = address(FALSE)

Enhanced PIC16C5X
CALL Subroutine Call CLRW Clear W

Syntax: [ label ] CALL k Syntax: [ label ] CLRW
Operands: 0 ≤ k ≤ 255 Operands: None
Operation: (PC) + 1→ Top of Stack; Operation: 00h → (W);
k → PC<7:0>; 1→Z
(STATUS<6:5>) → PC<10:9>; Status Affected: Z
0 → PC<8>
Encoding: 0000 0100 0000
Status Affected: None
Description: The W register is cleared. Zero bit (Z)
Encoding: 1001 kkkk kkkk is set.
Description: Subroutine call. First, return address Words: 1
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded Cycles: 1
into PC bits <7:0>. The upper bits Example: CLRW
PC<10:9> are loaded from STA-
TUS<6:5>, PC<8> is cleared. CALL is Before Instruction
a two cycle instruction. W = 0x5A
Words: 1 After Instruction

W = 0x00
Cycles: 2 Z = 1
Example: HERE CALL THERE
Before Instruction
PC = address (HERE) CLRWDT Clear Watchdog Timer
After Instruction Syntax: [ label ] CLRWDT
PC = address (THERE) Operands: None
TOS = address (HERE + 1)
Operation: 00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
CLRF Clear f
1 → PD
Syntax: [ label ] CLRF f
Status Affected: TO, PD
Operands: 0 ≤ f ≤ 31
Encoding: 0000 0000 0100
Operation: 00h → (f);
Description: The CLRWDT instruction resets the
1→Z WDT. It also resets the prescaler, if the
Status Affected: Z prescaler is assigned to the WDT and
not Timer0. Status bits TO and PD are
Encoding: 0000 011f ffff
set.
Description: The contents of register 'f' are cleared
Words: 1
and the Z bit is set.
Cycles: 1
Words: 1
Example: CLRWDT
Cycles: 1
Before Instruction
Example: CLRF FLAG_REG
WDT counter = ?
Before Instruction
After Instruction
FLAG_REG = 0x5A
WDT counter = 0x00
After Instruction WDT prescale = 0
FLAG_REG = 0x00 TO = 1
Z = 1 PD = 1

Enhanced PIC16C5X
COMF Complement f DECFSZ Decrement f, Skip if 0

Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f) → (dest) Operation: (f) – 1 → d; skip if result = 0
Status Affected: Z Status Affected: None
Encoding: 0010 01df ffff Encoding: 0010 11df ffff
Description: The contents of register 'f' are comple- Description: The contents of register 'f' are decre-
mented. If 'd' is 0 the result is stored in mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is the W register. If 'd' is 1 the result is
stored back in register 'f'. placed back in register 'f'.
Words: 1 If the result is 0, the next instruction,
which is already fetched, is discarded
Cycles: 1 and an NOP is executed instead mak-
Example: COMF REG1,0 ing it a two cycle instruction.
Before Instruction Words: 1

REG1 = 0x13 Cycles: 1(2)
After Instruction Example: HERE DECFSZ CNT, 1
REG1 = 0x13 GOTO LOOP
W = 0xEC CONTINUE •
•
•
DECF Decrement f Before Instruction
Syntax: [ label ] DECF f,d PC = address (HERE)
Operands: 0 ≤ f ≤ 31 After Instruction

CNT = CNT - 1;
d ∈ [0,1]
if CNT = 0,
Operation: (f) – 1 → (dest) PC = address (CONTINUE);
if CNT ≠ 0,
Status Affected: Z
PC = address (HERE+1)
Encoding: 0000 11df ffff
Description: Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is GOTO Unconditional Branch
1 the result is stored back in register 'f'.
Syntax: [ label ] GOTO k
Words: 1
Operands: 0 ≤ k ≤ 511
Cycles: 1
Operation: k → PC<8:0>;
Example: DECF CNT, 1 STATUS<6:5> → PC<10:9>
Before Instruction Status Affected: None
CNT = 0x01
Z = 0 Encoding: 101k kkkk kkkk
After Instruction Description: GOTO is an unconditional branch. The

9-bit immediate value is loaded into PC
CNT = 0x00
bits <8:0>. The upper bits of PC are
Z = 1
loaded from STATUS<6:5>. GOTO is a
two cycle instruction.
Words: 1
Cycles: 2
Example: GOTO THERE
After Instruction
PC = address (THERE)

Enhanced PIC16C5X
INCF Increment f IORLW Inclusive OR literal with W

Syntax: [ label ] INCF f,d Syntax: [ label ] IORLW k
Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ k ≤ 255
d ∈ [0,1] Operation: (W) .OR. (k) → (W)
Operation: (f) + 1 → (dest) Status Affected: Z
Status Affected: Z Encoding: 1101 kkkk kkkk
Description: The contents of the W register are
Description: The contents of register 'f' are incre- OR’ed with the eight bit literal 'k'. The
mented. If 'd' is 0 the result is placed in result is placed in the W register.
the W register. If 'd' is 1 the result is Words: 1
placed back in register 'f'.
Cycles: 1
Words: 1
Example: IORLW 0x35
Cycles: 1
Before Instruction
Example: INCF CNT, 1 W = 0x9A
Before Instruction After Instruction
CNT = 0xFF W = 0xBF
Z = 0 Z = 0
After Instruction
CNT = 0x00
Z = 1 IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
INCFSZ Increment f, Skip if 0 Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Syntax: [ label ] INCFSZ f,d
Operation: (W).OR. (f) → (dest)
d ∈ [0,1] Status Affected: Z
Operation: (f) + 1 → (dest), skip if result = 0 Encoding: 0001 00df ffff
Status Affected: None Description: Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in
Encoding: 0011 11df ffff the W register. If 'd' is 1 the result is
Description: The contents of register 'f' are incre- placed back in register 'f'.
mented. If 'd' is 0 the result is placed in Words: 1
the W register. If 'd' is 1 the result is
placed back in register 'f'. Cycles: 1
If the result is 0, then the next instruc- Example: IORWF RESULT, 0
tion, which is already fetched, is dis-
carded and an NOP is executed Before Instruction
instead making it a two cycle instruc- RESULT = 0x13
tion. W = 0x91
Words: 1 After Instruction

RESULT = 0x13
Cycles: 1(2) W = 0x93
Example: HERE INCFSZ CNT, 1 Z = 0
GOTO LOOP
CONTINUE •
•
•
Before Instruction
PC = address (HERE)
After Instruction
CNT = CNT + 1;
if CNT = 0,
PC = address (CONTINUE);
if CNT ≠ 0,
PC = address (HERE +1)

Enhanced PIC16C5X
MOVF Move f MOVWF Move W to f

Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f
d ∈ [0,1] Operation: (W) → (f)
Operation: (f) → (dest) Status Affected: None
Status Affected: Z Encoding: 0000 001f ffff
Description: Move data from the W register to regis-
Description: The contents of register 'f' is moved to ter 'f'.
destination 'd'. If 'd' is 0, destination is
Words: 1
the W register. If 'd' is 1, the destination
is file register 'f'. 'd' is 1 is useful to test Cycles: 1
a file register since status flag Z is
Example: MOVWF TEMP_REG
affected.
Before Instruction
Words: 1
TEMP_REG = 0xFF
Cycles: 1 W = 0x4F
Example: MOVF FSR, 0 After Instruction
TEMP_REG = 0x4F
After Instruction
W = 0x4F
W = value in FSR register
NOP No Operation
MOVLW Move Literal to W Syntax: [ label ] NOP
Syntax: [ label ] MOVLW k Operands: None
Operands: 0 ≤ k ≤ 255 Operation: No operation
Operation: k → (W) Status Affected: None
Status Affected: None Encoding: 0000 0000 0000
Encoding: 1100 kkkk kkkk Description: No operation.
Description: The eight bit literal 'k' is loaded into the Words: 1
W register. The don’t cares will assem-
ble as 0s.
Cycles: 1
Words: 1 Example: NOP
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A

Enhanced PIC16C5X
OPTION Load OPTION Register RLF Rotate Left f through Carry

Syntax: [ label ] OPTION Syntax: [ label ] RLF f,d
Operands: None Operands: 0 ≤ f ≤ 31
Operation: (W) → OPTION d ∈ [0,1]
Status Affected: None Operation: See description below
Encoding: 0000 0000 0010 Status Affected: C
Description: The content of the W register is loaded Encoding: 0011 01df ffff
into the OPTION register.
Description: The contents of register 'f' are rotated
Words: 1 one bit to the left through the Carry
Cycles: 1 Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
Example OPTION
back in register 'f'.
Before Instruction
W = 0x07 C register 'f'
After Instruction Words: 1

OPTION = 0x07
Cycles: 1
Example: RLF REG1,0
RETLW Return with Literal in W
Before Instruction
Syntax: [ label ] RETLW k REG1 = 1110 0110
C = 0
Operands: 0 ≤ k ≤ 255
After Instruction
Operation: k → (W);
REG1 = 1110 0110
TOS → PC W = 1100 1100
Status Affected: None C = 1
Encoding: 1000 kkkk kkkk
Description: The W register is loaded with the eight
RRF Rotate Right f through Carry
bit literal 'k'. The program counter is
loaded from the top of the stack (the Syntax: [ label ] RRF f,d
return address). This is a two cycle
instruction.
d ∈ [0,1]
Words: 1
Operation: See description below
Cycles: 2
Status Affected: C
Example: CALL TABLE ;W contains
;table offset Encoding: 0011 00df ffff
;value. Description: The contents of register 'f' are rotated
• ;W now has table one bit to the right through the Carry
• ;value. Flag. If 'd' is 0 the result is placed in the
• W register. If 'd' is 1 the result is placed
TABLE ADDWF PC ;W = offset back in register 'f'.
RETLW k1 ;Begin table
RETLW k2 ; C register 'f'
•
• Words: 1
•
Cycles: 1
RETLW kn ; End of table
Before Instruction Example: RRF REG1,0
W = 0x07 Before Instruction
REG1 = 1110 0110
After Instruction
C = 0
W = value of k8
After Instruction
REG1 = 1110 0110
W = 0111 0011
C = 0

Enhanced PIC16C5X
SLEEP Enter SLEEP Mode SUBWF Subtract W from f

Syntax: [label] SLEEP Syntax: [label] SUBWF f,d
Operands: None Operands: 0 ≤ f ≤ 31
d ∈ [0,1]
Operation: 00h → WDT;
0 → WDT prescaler; Operation: (f) – (W) → (dest)
1 → TO; Status Affected: C, DC, Z
0 → PD
Status Affected: TO, PD
Description: Subtract (2’s complement method) the
Encoding: 0000 0000 0011 W register from register 'f'. If 'd' is 0 the
Description: Time-out status bit (TO) is set. The result is stored in the W register. If 'd' is
power down status bit (PD) is cleared. 1 the result is stored back in register 'f'.
The WDT and its prescaler are Words: 1
cleared.
Cycles: 1
The processor is put into SLEEP mode
with the oscillator stopped. See sec- Example 1: SUBWF REG1, 1
tion on SLEEP for more details.
Before Instruction
Words: 1 REG1 = 3
W = 2
Cycles: 1
C = ?
Example: SLEEP
After Instruction
REG1 = 1
W = 2
C = 1 ; result is positive
Example 2:
Before Instruction
REG1 = 2
W = 2
C = ?
After Instruction
REG1 = 0
W = 2
C = 1 ; result is zero
Example 3:
Before Instruction
REG1 = 1
W = 2
C = ?
After Instruction
REG1 = FF
W = 2
C = 0 ; result is negative

Enhanced PIC16C5X
SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W

Syntax: [ label ] SWAPF f,d Syntax: [label] XORLW k
Operands: 0 ≤ f ≤ 31 Operands: 0 ≤ k ≤ 255
d ∈ [0,1]
Operation: (W) .XOR. k → (W)
Operation: (f<3:0>) → (dest<7:4>);
Status Affected: Z
(f<7:4>) → (dest<3:0>)
Encoding: 1111 kkkk kkkk
Description: The contents of the W register are
XOR’ed with the eight bit literal 'k'. The
Description: The upper and lower nibbles of register result is placed in the W register.
'f' are exchanged. If 'd' is 0 the result is
Words: 1
placed in W register. If 'd' is 1 the result
is placed in register 'f'. Cycles: 1
Words: 1 Example: XORLW 0xAF
Cycles: 1 Before Instruction
W = 0xB5
Example SWAPF REG1, 0
After Instruction
Before Instruction
W = 0x1A
REG1 = 0xA5
After Instruction
REG1 = 0xA5
XORWF Exclusive OR W with f
W = 0X5A
Syntax: [ label ] XORWF f,d
TRIS Load TRIS Register d ∈ [0,1]
Syntax: [ label ] TRIS f Operation: (W) .XOR. (f) → (dest)
Operands: f = 5, 6 or 7 Status Affected: Z
Operation: (W) → TRIS register f Encoding: 0001 10df ffff
Description: Exclusive OR the contents of the W
Encoding: 0000 0000 0fff register with register 'f'. If 'd' is 0 the
Description: TRIS register 'f' (f = 5, 6, or 7) is loaded result is stored in the W register. If 'd' is
with the contents of the W register 1 the result is stored back in register 'f'.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example TRIS PORTA Example XORWF REG,1
Before Instruction Before Instruction
W = 0XA5 REG = 0xAF
After Instruction W = 0xB5
TRISA = 0XA5 After Instruction
REG = 0x1A
W = 0xB5

Enhanced PIC16C5X
NOTES:

Enhanced PIC16C5X
9.0 DEVELOPMENT SUPPORT The PICMASTER Emulator System has been
designed as a real-time emulation system with
9.1 Development Tools advanced features that are generally found on more
expensive development tools. The PC compatible 386
The PIC16/17 microcontrollers are supported with a full (and better) machine platform and
range of hardware and software development tools: Microsoft Windows 3.x environment was chosen to
• PICMASTER Real-Time In-Circuit Emulator best make these features available to you, the
• PRO MATE Universal Programmer end user.
• PICSTART Low-Cost Prototype Programmer The PICMASTER Universal Emulator System consists
• PICDEM-1 Low-Cost Demonstration Board primarily of four major components:
• PICDEM-2 Low-Cost Demonstration Board • Host-Interface Card
• MPASM Assembler • Emulator Control Pod
• MPSIM Software Simulator • Target-Specific Emulator Probe
• C Compiler (MP-C) • PC-Host Emulation Control Software
• Fuzzy logic development system The Windows operating system allows the developer to
(fuzzyTECH−MP) take full advantage of the many powerful features and
functions of the PICMASTER system.
9.2 PICMASTER High Performance
PICMASTER emulation can operate in one window,
Universal In-Circuit Emulator with
while a text editor is running in a second window.
MPLAB IDE
PC-Host Emulation Control software takes full advan-
The PICMASTER Universal In-Circuit Emulator is tage of Dynamic Data Exchange (DDE), a feature of
intended to provide the product development engineer Windows. DDE allows data to be dynamically trans-
with a complete microcontroller design tool set for all ferred between two or more Windows programs. With
microcontrollers in the PIC16C5X, PIC16CXX and this feature, data collected with PICMASTER can be
PIC17CXX families. PICMASTER is supplied with the automatically transferred to a spreadsheet or database
MPLAB Integrated Development Environment (IDE), program for further analysis.
which allows editing, "make" and download, and Under Windows, as many as four PICMASTER emula-
source debugging from a single environment. A tors can be run simultaneously from the same PC mak-
PICMASTER System configuration is shown ing development of multi-microcontroller systems
in Figure 9-1. possible (e.g., a system containing a PIC16CXX
Interchangeable target probes allow the system to be processor and a PIC17CXX processor).
easily reconfigured for emulation of different proces- The PICMASTER probes specifications are shown
sors. The universal architecture of the PICMASTER in Table 9-1.
allows expansion to support all new PIC16C5X,
PIC16CXX and PIC17CXX microcontrollers.
FIGURE 9-1: PICMASTER SYSTEM CONFIGURATION
In-Line
5 VDC
Power Supply 90 - 250 VAC
(Optional)
Windows 3.x
Power Switch
Interchangeable
Power Connector Emulator Probe
PC Bus
PC-Interface
PICMASTER Emulator Pod

Common Interface Card
PC Compatible Computer
Logic Probes

Enhanced PIC16C5X
TABLE 9-1: PICMASTER PROBE TABLE 9-1: PICMASTER PROBE
PROBE PROBE
PICMASTER PICMASTER
Devices Maximum Operating Devices Maximum Operating
PROBE PROBE
Frequency Voltage Frequency Voltage
PIC16C52 PROBE-16D 4 MHz 4.5V - 5.5V PIC16CR64 PROBE-16E(1) 10 MHz 4.5V - 5.5V
PIC16C54 PROBE-16D 20 MHz 4.5V - 5.5V PIC16C65 PROBE-16F 10 MHz 4.5V - 5.5V
PIC16C54A PROBE-16D 20 MHz 4.5V - 5.5V PIC16C65A PROBE-16F(1) 10 MHz 4.5V - 5.5V
PIC16CR54 PROBE-16D 20 MHz 4.5V - 5.5V PIC16C620 PROBE-16H 10 MHz 4.5V - 5.5V
PIC16CR54A PROBE-16D(1) 20 MHz 4.5V - 5.5V PIC16C621 PROBE-16H 10 MHz 4.5V - 5.5V
PIC16CR54B PROBE-16D(1) 20 MHz 4.5V - 5.5V PIC16C622 PROBE-16H 10 MHz 4.5V - 5.5V
PIC16C55 PROBE-16D 20 MHz 4.5V - 5.5V (1)
PIC16C70 PROBE-16B 10 MHz 4.5V - 5.5V
(1)
PIC16CR55 PROBE-16D 20 MHz 4.5V - 5.5V PIC16C71 PROBE-16B 10 MHz 4.5V - 5.5V
PIC16C56 PROBE-16D 20 MHz 4.5V - 5.5V (1)
PIC16C71A PROBE-16B 10 MHz 4.5V - 5.5V
PIC16CR56 PROBE-16D(1) 20 MHz 4.5V - 5.5V PIC16C72 PROBE-16F(1) 10 MHz 4.5V - 5.5V
PIC16C57 PROBE-16D 20 MHz 4.5V - 5.5V PIC16C73 PROBE-16F 10 MHz 4.5V - 5.5V
PIC16CR57A PROBE-16D 20 MHz 4.5V - 5.5V (1)
PIC16C73A PROBE-16F 10 MHz 4.5V - 5.5V
(1)
PIC16CR57B PROBE-16D 20 MHz 4.5V - 5.5V PIC16C74 PROBE-16F 10 MHz 4.5V - 5.5V
PIC16C58A PROBE-16D 20 MHz 4.5V - 5.5V PIC16C74A PROBE-16F(1) 10 MHz 4.5V - 5.5V
PIC16CR58A PROBE-16D 20 MHz 4.5V - 5.5V PIC16C83 PROBE-16C 10 MHz 4.5V - 5.5V
(1)
PIC16CR58B PROBE-16D 20 MHz 4.5V - 5.5V PIC16C84 PROBE-16C 10 MHz 4.5V - 5.5V
PIC16C61 PROBE-16G 10 MHz 4.5V - 5.5V PIC17C42 PROBE-17B 20 MHz 4.5V - 5.5V
PIC16C62 PROBE-16E 10 MHz 4.5V - 5.5V PIC17C43 PROBE-17B 20 MHz 4.5V - 5.5V
(1)
PIC16C62A PROBE-16E 10 MHz 4.5V - 5.5V PIC17C44 PROBE-17B 20 MHz 4.5V - 5.5V
(1)
PIC16CR62 PROBE-16E 10 MHz 4.5V - 5.5V Note 1: This PICMASTER probe can be used to
(1) functionally emulate the device listed in the
PIC16C63 PROBE-16F 10 MHz 4.5V - 5.5V
previous column. Contact your Microchip sales
PIC16C64 PROBE-16E 10 MHz 4.5V - 5.5V office for details.
PIC16C64A PROBE-16E(1) 10 MHz 4.5V - 5.5V

Enhanced PIC16C5X
9.3 PRO MATE Universal Programmer 9.5 PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PRO MATE Universal Programmer is a
full-featured programmer capable of operating in The PICDEM-1 is a simple board which demonstrates
stand-alone mode as well as PC-hosted mode. the capabilities of several of Microchip’s
The PRO MATE has programmable VDD and VPP microcontrollers. The microcontrollers supported are:
supplies which allows it to verify programmed memory PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61,
at VDD min and VDD max for maximum reliability. It has PIC16C62X, PIC16C71, PIC16C8X, PIC17C42,
an LCD display for displaying error messages, keys to PIC17C43 and PIC17C44. All necessary hardware and
enter commands and a modular detachable socket software is included to run basic demo programs. The
assembly to support various package types. In stand- users can program the sample microcontrollers
alone mode the PRO MATE can read, verify or program provided with the PICDEM-1 board, on a
PIC16C5X, PIC16CXX and PIC17CXX devices. It can PRO MATE or PICSTART-16B programmer, and
also set configuration and code-protect bits in easily test firmware. The user can also connect the
this mode. PICDEM-1 board to the PICMASTER emulator and
download the firmware to the emulator for testing.
In PC-hosted mode, the PRO MATE connects to the Additional prototype area is available for the user to
PC via one of the COM (RS-232) ports. PC based build some additional hardware and connect it to the
user-interface software makes using the programmer microcontroller socket(s). Some of the features include
simple and efficient. The user interface is full-screen an RS-232 interface, a potentiometer for simulated
and menu-based. Full screen display and editing of analog input, push-button switches and eight LEDs
data, easy selection of bit configuration and part type, connected to PORTB.
easy selection of VDD min, VDD max and VPP levels,
load and store to and from disk files (Intel hex format) 9.6 PICDEM-2 Low-Cost PIC16CXX
are some of the features of the software. Essential Demonstration Board
commands such as read, verify, program and blank
check can be issued from the screen. Additionally, The PICDEM-2 is a simple demonstration board that
serial programming support is possible where each supports the PIC16C64, PIC16C65, PIC16C73 and
part is programmed with a different serial number, PIC16C74 microcontrollers. All the necessary
sequential or random. hardware and software is included to run the basic
The PRO MATE has a modular “programming socket demonstration programs. The user can program
module”. Different socket modules are required for the sample microcontrollers provided with the
different processor types and/or package types. PICDEM-2 board, on a PRO MATE programmer or
PICSTART-16C, and easily test firmware. The
PRO MATE supports all PIC16C5X, PIC16CXX and PICMASTER emulator may also be used with the
PIC17CXX processors. PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding
9.4 PICSTART Low-Cost Development
additional hardware and connecting it to the
System microcontroller socket(s). Some of the features include
The PICSTART programmer is an easy to use, very a RS-232 interface, push-button switches, a
low-cost prototype programmer. It connects to the PC potentiometer for simulated analog input, a Serial
via one of the COM (RS-232) ports. A PC-based user EEPROM to demonstrate usage of the I2C bus and
interface software makes using the programmer simple separate headers for connection to an LCD module
and efficient. The user interface is full-screen and and a keypad.
menu-based. PICSTART is not recommended for
production programming.

Enhanced PIC16C5X
9.7 MPLAB Integrated Development 9.8 MPASM Assembler
Environment Software
The MPASM Cross Assembler is a PC-hosted symbolic
The MPLAB Software brings an ease of software assembler. It supports all microcontroller series
development previously unseen in the 8-bit including the PIC16C5X, PIC16CXX, and PIC17CXX
microcontroller market. MPLAB is a windows based families.
application which contains: MPASM offers full featured Macro capabilities,
• A full featured editor conditional assembly, and several source and listing
• Three operating modes formats. It generates various object code formats to
- editor support Microchip's development tools as well as third
- emulator party programmers.
- simulator (available soon) MPASM allows full symbolic debugging from
• A project manager the Microchip Universal Emulator System
• Customizable tool bar and key mapping (PICMASTER).
• A status bar with project information
MPASM has the following features to assist in
• Extensive on-line help
developing software for specific use applications.
MPLAB allows you to:
• Provides translation of Assembler source code to
• edit your source files (either assembly or "C") object code for all Microchip microcontrollers.
• one touch assemble (or compile) and download to • Macro assembly capability
PIC16/17 tools (automatically updates all project
• Produces all the files (Object, Listing, Symbol,
information)
and special) required for symbolic debug with
• debug using:
Microchip’s emulator systems.
- source files
- absolute listing file • Supports Hex (default), Decimal and Octal
• transfer data dynamically via DDE (soon to be source and listing formats.
replaced by OLE) MPASM provides a rich directive language to support
• run up to four emulators on the same PC programming of the PIC16/17. Directives are helpful in
The ability to use MPLAB with Microchip’s simulator making the development of your assemble source
(available soon) allows a consistent platform and the code shorter and more maintainable.
ability to easily switch from the low cost simulator to the • Data Directives are those that control the
full featured emulator with minimal retraining due to allocation of memory and provide a way to refer to
development tools. data items symbolically (i.e., by meaningful
names).
• Control Directives control the MPASM listing
display. They allow the specification of titles and
sub-titles, page ejects and other listing control.
This eases the readability of the printed
output file.
• Conditional Directives permit sections of
conditionally assembled code. This is most useful
where additional functionality may wished to be
added depending on the product (less
functionality for the low end product, then for the
high end product). Also this is very helpful in the
debugging of a program.
• Macro Directives control the execution and data
allocation within macro body definitions. This
makes very simple the re-use of functions in a
program as well as between programs.

Enhanced PIC16C5X
9.9 MPSIM Software Simulator 9.11 fuzzyTECH-MP Fuzzy Logic
Development System
The MPSIM Software Simulator allows code
development in a PC host environment. It allows the fuzzyTECH-MP fuzzy logic development tool is
user to simulate the PIC16/17 series microcontrollers available in two versions - a low cost introductory
on an instruction level. On any given instruction, the version, MP Explorer, for designers to gain a
user may examine or modify any of the data areas or comprehensive working knowledge of fuzzy logic
provide external stimulus to any of the pins. The system design; and a full-featured version,
input/output radix can be set by the user and the fuzzyTECH-MP, edition for implementing more
execution can be performed in; single step, execute complex systems.
until break, or in a trace mode. MPSIM fully supports
Both versions include Microchip’s fuzzyLAB
symbolic debugging using MP-C and MPASM. The
demonstration board for hands-on experience with
Software Simulator offers the low cost flexibility to
fuzzy logic systems implementation.
develop and debug code outside of the laboratory
environment making it an excellent multi-project 9.12 Development Systems
software development tool.
For convenience, the development tools are packaged
9.10 MP-C C Compiler into comprehensive systems as listed in Table 9-2.
The MP-C Code Development System is a complete 'C'
compiler and integrated development environment for
Microchip’s PIC16/17 family of microcontrollers. The
compiler provides powerful integration capabilities and
ease of use not found with other compilers.
For easier source level debugging, the compiler
provides symbol information that is compatible with the
PICMASTER Universal Emulator memory display
(PICMASTER emulator software versions 1.13
and later).
The MP-C Code Development System is supplied
directly by Byte Craft Limited of Waterloo, Ontario,
Canada. If you have any questions, please contact
your regional Microchip FAE or Microchip technical
support personnel at (602) 786-7627.
TABLE 9-2: DEVELOPMENT SYSTEM PACKAGES
Item Name System Description

1. PICMASTER System PICMASTER In-Circuit Emulator, PRO MATE Programmer, Assembler, Soft-
ware Simulator, Samples and your choice of Target Probe.
2. PICSTART System PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator
and Samples.
3. PRO MATE System PRO MATE Universal Programmer, full featured stand-alone or PC-hosted
programmer, Assembler, Simulator

Enhanced PIC16C5X
NOTES:

PIC16C54A Enh. PIC16C5X
10.0 ELECTRICAL CHARACTERISTICS - PIC16C54A
Absolute Maximum Ratings†
Ambient temperature under bias............................................................................................................ .-55˚C to +125˚C
Storage temperature ............................................................................................................................. - 65˚C to +150˚C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS(2) ............................................................................................................0 to +14V
Voltage on all other pins with respect to VSS .................................................................................. -0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin ...................................................................................................................................150 mA
Max. current into VDD pin ......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only) .....................................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD) ..............................................................................................................±20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin ............................................................................................................20 mA
Max. output current sourced by a single I/O port (PORTA or B) .............................................................................40 mA
Max. output current sunk by a single I/O port (PORTA or B) ..................................................................................50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

Enh. PIC16C5X PIC16C54A
TABLE 10-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC PIC16C54A-04 PIC16C54A-10 PIC16C54A-20 PIC16LC54A-04 PIC16C54A/JW

VDD: 3.0V to 6.25V VDD: 3.0V to 6.25V VDD: 3.0V to 6.25V VDD: 2.5V to 6.25V VDD: 3.0V to 6.25V
IDD: 2.4 mA max. at IDD: 1.7 mA typ. at IDD: 1.7 mA typ. at IDD: 0.5 mA typ. at IDD: 2.4 mA max. at
5.5V 5.5V 5.5V 5.5V 5.5V
RC
IPD: 4.0 µA max. at IPD: 0.25 µA typ. at IPD: 0.25 µA typ. at IPD: 0.25 µA typ. at IPD: 4.0 µA max. at
3.0V WDT dis 3.0V WDT dis 3.0V WDT dis 2.5V WDT dis 3.0V WDT dis
Freq: 4 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max.
IDD 2.4 mA max. at IDD: 1.7 mA typ. at IDD: 1.7 mA typ. at IDD: 0.5 mA typ. at IDD 2.4 mA max. at
5.5V 5.5V 5.5V 5.5V 5.5V
XT
Freq: 4 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max.
VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
IDD: 2.4 mA typ. at IDD: 8.0 mA max. at IDD: 16 mA max. at IDD: 8 mA max. at
5.5V 5.5V 5.5V Do not use in 5.5V
HS
IPD: 0.25 µA typ. at IPD: 4.0 µA max. at IPD: 4.0 µA max. at HS mode IPD: 4.0 µA max. at
3.0V WDT dis 3.0V WDT dis 3.0V WDT dis 3.0V WDT dis
Freq: 4.0 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 10 MHz max.
VDD: 3.0V to 6.25V VDD: 2.5V to 6.25V VDD: 2.5V to 6.25V
IDD: 14 µA typ. at IDD: 27 µA max. at IDD: 27 µA max. at
32kHz, 3.0V 32kHz, 2.5V 32kHz, 2.5V
Do not use in Do not use in
LP IPD: 0.25 µA typ. at WDT dis WDT dis
LP mode LP mode
3.0V WDT dis IPD: 4.0 µA max. at IPD: 4.0 µA max. at
Freq: 200 kHz max. 2.5V WDT dis 2.5V WDT dis
Freq: 200 kHz max. Freq: 200 kHz max.
The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended
that the user select the device type from information in unshaded sections.

10.1 DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)
PIC16C54A-04I, 10I, 20I (Industrial)
Standard Operating Conditions (unless otherwise specified)

DC Characteristics
Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)
Power Supply Pins
–40°C ≤ TA ≤ +85°C (industrial)
Characteristic Sym Min Typ(1) Max Units Conditions

Supply Voltage VDD
XT, RC and LP options 3.0 6.25 V
HS option 4.5 5.5 V
RAM Data Retention Voltage(2) VDR 1.5* V Device in SLEEP mode
VDD start voltage to ensure VPOR VSS V See section on Power-On Reset for details
Power-On Reset
VDD rise rate to ensure SVDD 0.05* V/ms See section on Power-On Reset for details
Power-On Reset
Supply Current(3) IDD
XT and RC(4) options 1.8 2.4 mA FOSC = 4.0 MHz, VDD = 5.5V
HS option 2.4 8.0 mA FOSC = 10 MHz, VDD = 5.5V
4.5 16 mA FOSC = 20 MHz, VDD = 5.5V
LP option, Commercial 14 µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP option, Industrial 17 µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled
Power Down Current(5) IPD
Commercial 4.0 12 µA VDD = 3.0V, WDT enabled
0.25 4.0 µA VDD = 3.0V, WDT disabled
Industrial 5.0 14 µA VDD = 3.0V, WDT enabled
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through Rext. The current through the resistor can be estimated by the
formula: IR = VDD/2Rext (mA) with Rext in kΩ.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

10.2 DC Characteristics: PIC16C54A-04E, 10E, 20E (Automotive)
DC Characteristics Standard Operating Conditions (unless otherwise specified)

Power Supply Pins Operating Temperature –40°C ≤ TA ≤ +125°C (automotive)

Supply Voltage VDD
XT and RC options 3.5 5.5 V
HS option 4.5 5.5 V
Power-On Reset
Power-On Reset
HS option 4.8 10 mA FOSC = 10 MHz, VDD = 5.5V
9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
XT and RC options 5.0 22 µA VDD = 3.5V, WDT enabled
0.8 18 µA VDD = 3.5V, WDT disabled
HS option 4.0 22 µA VDD = 3.5V, WDT enabled

10.3 DC Characteristics: PIC16LC54A-04 (Commercial)
PIC16LC54A-04I (Industrial)

DC Characteristics
Power Supply Pins

Supply Voltage VDD
(2)
RAM Data Retention Voltage VDR 1.5* V Device in SLEEP mode
Power-On Reset
Power-On Reset
XT and RC(4) options 0.5 mA FOSC = 4.0 MHz, VDD = 5.5V
LP option, Commercial 11 27 µA FOSC = 32 kHz, VDD = 2.5V WDT disabled
LP option, Industrial 14 35 µA FOSC = 32 kHz, VDD = 2.5V WDT disabled

10.4 DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04 (Commercial),

PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I (Industrial),
PIC16C54A-04E, 10E, 20E (Automotive)

DC Characteristics
All Pins Except
–40°C ≤ TA ≤ +125°C (automotive)
Power Supply Pins
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and
Section 10.3.
Input Low Voltage VIL
I/O ports VSS 0.2 VDD V Pin at hi-impedance
MCLR (Schmitt Trigger) VSS 0.15 VDD V
T0CKI (Schmitt Trigger) VSS 0.15 VDD V
OSC1 (Schmitt Trigger) VSS 0.15 VDD V RC option only(4)
OSC1 VSS 0.3 VDD V XT, HS and LP options
Input High Voltage VIH
I/O ports 0.2 VDD+1V VDD V For all VDD(5)
2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
MCLR (Schmitt Trigger) 0.85 VDD VDD V
T0CKI (Schmitt Trigger) 0.85 VDD VDD V
OSC1 (Schmitt Trigger) 0.85 VDD VDD V RC option only(4)
OSC1 0.7 VDD VDD V XT, HS and LP options
Hysteresis of Schmitt VHYS 0.15VDD* V
Trigger inputs
Input Leakage Current(3) IIL For VDD ≤ 5.5V
I/O ports -1.0 0.5 +1.0 µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
MCLR -5.0 +5.0 µA VPIN = VSS +0.25V(2)
0.5 +3.0 µA VPIN = VDD(2)
T0CKI -3.0 0.5 +3.0 µA VSS ≤ VPIN ≤ VDD
OSC1 -3.0 0.5 µA VSS ≤ VPIN ≤ VDD,
XT, HS and LP options
Output Low Voltage VOL
I/O ports 0.6 V IOL = 8.7 mA, VDD = 4.5V
OSC2/CLKOUT 0.6 V IOL = 1.6 mA, VDD = 4.5V,
RC option only
Output High Voltage VOH
I/O ports(3) VDD-0.7 V IOH = -5.4 mA, VDD = 4.5V
OSC2/CLKOUT VDD-0.7 V IOH = -1.0 mA, VDD = 4.5V,
RC option only
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
3: Negative current is defined as coming out of the pin.
4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
5: The user may use the better of the two specifications.

10.5 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
2 to mc MCLR
ck CLKOUT osc oscillator
cy cycle time os OSC1
drt device reset timer t0 T0CKI
io I/O port wdt watchdog timer
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
FIGURE 10-1: LOAD CONDITIONS - PIC16C54A
Pin CL = 50 pF for all pins except OSC2

CL 15 pF for OSC2 in XT, HS or LP
options when external clock
is used to drive OSC1
VSS

10.6 Timing Diagrams and Specifications
FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C54A
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3.
Parameter
No. Sym Characteristic Min Typ(1) Max Units Conditions
FOSC External CLKIN Frequency(2) DC — 4.0 MHz RC osc mode

DC — 4.0 MHz XT osc mode
DC — 4.0 MHz HS osc mode (04)
DC — 10 MHz HS osc mode (10)
DC — 200 kHz LP osc mode
Oscillator Frequency(2) DC — 4.0 MHz RC osc mode
0.1 — 4.0 MHz XT osc mode
4 — 4.0 MHz HS osc mode (04)
4 — 10 MHz HS osc mode (10)
4 — 20 MHz HS osc mode (20)
5 — 200 kHz LP osc mode
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating condi-
tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A (CON’T)

Parameter
1 TOSC External CLKIN Period(2) 250 — — ns RC osc mode

250 — — ns XT osc mode
250 — — ns HS osc mode (04)
5.0 — — µs LP osc mode
Oscillator Period(2) 250 — — ns RC osc mode
250 — 10,000 ns XT osc mode
250 — 250 ns HS osc mode (04)
100 — 250 ns HS osc mode (10)
50 — 250 ns HS osc mode (20)
5.0 — 200 µs LP osc mode
2 TCY Instruction Cycle Time(3) — 4/FOSC — —
3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator
20* — — ns HS oscillator
2.0* — — µs LP oscillator
4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator
— — 25* ns HS oscillator
— — 50* ns LP oscillator
and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating condi-
tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.

FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C54A
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
14 19 16
I/O Pin
(input)
17 15
I/O Pin Old Value New Value

(output)
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A

Section 10.3.
Parameter
No. Sym Characteristic Min Typ(1) Max Units
10 TosH2ckL OSC1↑ to CLKOUT↓(2) — 15 30** ns

11 TosH2ckH OSC1↑ to CLKOUT↑(2) — 15 30** ns
12 TckR CLKOUT rise time(2) — 5.0 15** ns
13 TckF CLKOUT fall time(2) — 5.0 15** ns
14 TckL2ioV CLKOUT↓ to Port out valid(2) — — 40** ns
15 TioV2ckH Port in valid before CLKOUT↑(2) 0.25 TCY+30* — — ns
16 TckH2ioI Port in hold after CLKOUT↑(2) 0* — — ns
17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(3) — — 100* ns
18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid (I/O in TBD — — ns
hold time)
19 TioV2osH Port input valid to OSC1↑ TBD — — ns
(I/O in setup time)
20 TioR Port output rise time(3) — 10 25** ns
21 TioF Port output fall time(3) — 10 25** ns
** These parameters are design targets and are not tested. No characterization data available at this time.
and are not tested.
2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
3: See Figure 10-1 for loading conditions.

FIGURE 10-4: RESET, WATCHDOG TIMER, AND
DEVICE RESET TIMER TIMING - PIC16C54A
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
TABLE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A

Parameter
30 TmcL MCLR Pulse Width (low) 100* — — ns VDD = 5.0V

31 Twdt Watchdog Timer Time-out Period 9.0* 18* 40* ms VDD = 5.0V (Commercial)
(No Prescaler)
32 TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Commercial)
34 TioZ I/O Hi-impedance from MCLR Low — — 100* ns
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.

FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C54A
T0CKI
40 41
42
TABLE 10-5: TIMER0 CLOCK REQUIREMENTS - PIC16C54A

Section 10.3.
Parameter
Sym Characteristic Min Typ(1) Max Units Conditions
No.
40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns
- With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns
42 Tt0P T0CKI Period 20 or TCY + 40* — — ns Whichever is greater.
N N = Prescale Value
(1, 2, 4,..., 256)
and are not tested.

PIC16CR54A Enh. PIC16C5X
11.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A
Ambient Temperature under bias ........................................................................................................... –55°C to +125°C
Storage Temperature ............................................................................................................................. –65°C to +150°C
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total Power Dissipation(1) ....................................................................................................................................800 mW
Max. Current out of VSS pin ..................................................................................................................................150 mA
Max. Current into VDD pin .......................................................................................................................................50 mA
Max. Current into an input pin (T0CKI only) ....................................................................................................................±500 µA
Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA
Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................±20 mA
Max. Output Current sunk by any I/O pin................................................................................................................25 mA
Max. Output Current sourced by any I/O pin...........................................................................................................20 mA
Max. Output Current sourced by a single I/O port (PORTA or B)............................................................................40 mA
Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................50 mA
Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus,
a series resistor of 50 to 100Ω should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to Vss.
†NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.

Enh. PIC16C5X PIC16CR54A

OSC PIC16CR54A-04 PIC16CR54A-10 PIC16CR54A-20 PIC16LCR54A-04

RC VDD: 2.5 V to 6.25 V
IDD: 3.6 mA max at 6.0 V
IPD: 6.0 µA max at 2.5 V, N/A N/A N/A
WDT dis
Freq: 4 MHz max
XT VDD: 2.5 V to 6.25 V
IDD: 3.6 mA max at 6.0 V
IPD: 6.0 µA max at 2.5 V, N/A N/A N/A
WDT dis
Freq: 4.0 MHz max
HS VDD: 4.5 V to 5.5 V VDD: 4.5 V to 5.5 V
IDD: 10 mA max at 5.5 V IDD: 10 mA max at 5.5 V
N/A IPD: 6.0 µA max at 2.5 V, IPD: 6.0 µA max at 2.5 V, N/A
WDT dis WDT dis
Freq: 10 MHz max Freq: 20 MHz max
LP VDD: 2.0 V to 6.25 V
IDD: 20 µA max at 32 kHz,
2.0 V
N/A N/A N/A
IPD: 6.0 µA max at 2.5 V,
WDT dis
Freq: 200 kHz max

11.1 DC Characteristics: PIC16CR54A-04, 10, 20 (Commercial)
PIC16CR54A-04I, 10I, 20I (Industrial)

DC Characteristics
Power Supply Pins

Supply Voltage VDD
RC and XT options 2.5 6.25 V
HS option 4.5 5.5 V
VDD Start Voltage to ensure VPOR VSS V See Section 7.4 for details on
Power-on Reset Power-on Reset
VDD Rise Rate to ensure SVDD 0.05* V/ms See Section 7.4 for details on
RC(4) and XT options 2.0 3.6 mA FOSC = 4.0 MHz, VDD = 6.0V
0.8 1.8 mA FOSC = 4.0 MHz, VDD = 3.0V
90 350 µA FOSC = 200 kHz, VDD = 2.5V
9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
Power-Down Current(5) IPD
Commercial
2.0 8.0* µA VDD = 4.0V, WDT disabled
5.0 25 µA VDD = 6.0V, WDT enabled
Industrial
2.0 10* µA VDD = 4.0V, WDT disabled
3.0 20* µA VDD = 4.0V, WDT enabled

11.2 DC Characteristics: PIC16CR54A-04E, 10E, 20E (Automotive)


Supply Voltage VDD
HS options 4.5 5.5 V
9.0 20 mA FOSC = 16 MHz, VDD = 5.5V
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.

11.3 DC Characteristics: PIC16LCR54A-04 (Commercial)
PIC16LCR54A-04I (Industrial)

DC Characteristics
Power Supply Pins

Supply Voltage VDD 2.0 6.25 V
10 20 µA FOSC = 32 kHz, VDD = 2.0V
70 µA FOSC = 32 kHz, VDD = 6.0V
Commercial
Industrial

11.4 DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)

PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)

DC Characteristics
All Pins Except
Power Supply Pins
Operating Voltage VDD range is described in Section 11.1 and Section 11.3.

I/O ports 2.0 VDD V VDD = 3.0V to 5.5V(5)
0.6 VDD VDD V Full VDD range(5)
Trigger inputs
I/O ports –1.0 +1.0 µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
MCLR –5.0 µA VPIN = VSS + 0.25V(2)
0.5 +5.0 µA VPIN = VDD(2)
T0CKI –3.0 0.5 +3.0 µA VSS ≤ VPIN ≤ VDD
OSC1 –3.0 0.5 +3.0 µA VSS ≤ VPIN ≤ VDD,
I/O ports 0.5 V IOL = 10 mA, VDD = 6.0V
RC option only
Output High Voltage(3) VOH
I/O ports VDD –0.5 V IOH = –4.0 mA, VDD = 6.0V
OSC2/CLKOUT VDD –0.5 V IOH = –0.8 mA, VDD = 6.0V,
RC option only
voltage.


All Pins Except Operating Temperature –40°C ≤ TA ≤ +125°C
Power Supply Pins Operating Voltage VDD range is described in Section 11.2.

I/O ports Vss 0.15 VDD V Pin at hi-impedance
MCLR (Schmitt Trigger) Vss 0.15 VDD V
T0CKI (Schmitt Trigger) Vss 0.15 VDD V
OSC1 (Schmitt Trigger) Vss 0.15 VDD V RC option only(4)
OSC1 Vss 0.3 VDD V XT, HS and LP options
I/O ports 0.45 VDD VDD V For all VDD(5)
2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
0.36 VDD VDD V VDD > 5.5V
Trigger inputs
I/O ports –1.0 0.5 +1.0 µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
0.5 +5.0 µA VPIN = VDD(2)
RC option only
Output High Voltage (3) VOH
RC option only
voltage.


1. TppS2ppS
2. TppS
T
F Frequency T Time
pp
2 to mc MCLR
S
F Fall P Period
H High R Rise
FIGURE 11-1: LOAD CONDITIONS

VSS

FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC16CR54A
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A

Parameter

4.0 — 4.0 MHz HS osc mode (04)
4.0 — 10 MHz HS osc mode (10)
5.0 — 200 kHz LP osc mode
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating
conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption.

TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A (CON’T)

Parameter

250 — 250 ns HS osc mode (04)
100 — 250 ns HS osc mode (10)
50 — 250 ns HS osc mode (20)

FIGURE 11-3: CLKOUT AND I/O TIMING - PIC16CR54A
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
19
14 16
I/O Pin
(input)
17 15

(output)
20, 21
TABLE 11-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A

Section 11.3.
Parameter

hold time)
(I/O in setup time)

FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)
TABLE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A

Parameter
30 TmcL MCLR Pulse Width (low) 1.0* — — µs VDD = 5.0V

(No Prescaler)
34 TioZ I/O Hi-impedance from MCLR Low — — 1.0* µs
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design

FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC16CR54A
T0CKI
40 41
42
TABLE 11-5: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A

Section 11.3.
Parameter
No.
(1, 2, 4,..., 256)

NOTES:

PIC16CR54B/56/58B Enh. PIC16C5X
12.0 ELECTRICAL CHARACTERISTICS - PIC16CR54B/56/58B
Max. Current into VDD pin .......................................................................................................................................50 mA
CE
N
Max. Output Current sourced by a single I/O port (PORTA or B)............................................................................40 mA
IO
Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................50 mA
RM N
AT
FO VA
†NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
IN AD

Enh. PIC16C5X PIC16CR54B/56/58B

PIC16CR54B-04 PIC16CR54B-10 PIC16CR54B-20 PIC16LCR54B-04

OSC PIC16CR56-04 PIC16CR56-10 PIC16CR56-20 PIC16LCR56-04
PIC16CR58B-04 PIC16CR58B-10 PIC16CR58B-20 PIC16LCR58B-04
RC VDD: 2.5 V to 5.5V
IDD: 3.6 mA max at 6.0V
IPD: 6.0 µA max at 2.5V, N/A N/A N/A
WDT dis
Freq: 4.0 MHz max
XT VDD: 2.5V to 5.5V
WDT dis
Freq: 4.0 MHz max
HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
IDD: 10 mA max at 5.5V IDD: 10 mA max at 5.5V
N/A IPD: 6.0 µA max at 2.5V, IPD: 6.0 µA max at 2.5V, N/A
CE
N
WDT dis WDT dis
LP VDD: 2.5V to 5.5V
IO
2.0V
N/A N/A N/A
IPD: 6.0 µA max at 2.5V,
RM N
WDT dis
Freq: 200 kHz max
AT
FO VA
IN AD

12.1 DC Characteristics: PIC16CR54B/56/58B-04, 10, 20 (Commercial)
PIC16CR54B/56/58B-04I, 10I, 20I (Industrial)

DC Characteristics
Power Supply Pins

Supply Voltage VDD
HS option 4.5 5.5 V
CE
N
0.8 1.8 mA FOSC = 4.0 MHz, VDD = 3.0V
90 350 µA FOSC = 200 kHz, VDD = 2.5V
IO
9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
Power-Down Current(5)
RM N IPD
Commercial
AT 1.0 6.0 µA
µA
VDD = 2.5V, WDT disabled
FO VA
2.0 8.0* VDD = 4.0V, WDT disabled
Industrial
IN AD


12.2 DC Characteristics: PIC16CR54B/56/58B-04E, 10E, 20E (Automotive)


Supply Voltage VDD
CE
N
9.0 20 mA FOSC = 16 MHz, VDD = 5.5V
µA
IO
5.0 22 VDD = 3.25V, WDT enabled
RM N
AT
FO VA
IN AD


12.3 DC Characteristics: PIC16LCR54B/56/58B-04 (Commercial)
PIC16LCR54B/56/58B-04I (Industrial)

DC Characteristics
Power Supply Pins

10 20 µA FOSC = 32 kHz, VDD = 2.0V
70 µA FOSC = 32 kHz, VDD = 5.5V
CE
N
Commercial
µA
IO
1.0 6.0 VDD = 2.5V, WDT disabled
RM N 5.0 25 µA VDD = 5.5V, WDT enabled
Industrial
AT
FO VA
IN AD


12.4 DC Characteristics: PIC16CR54B/56/58B-04, 10, 20 (Commercial)

PIC16LCR54B/56/58B-04 (Commercial)
PIC16CR54B/56/58B-04I, 10I, 20I (Industrial)
PIC16LCR54B/56/58B-04I (Industrial)

DC Characteristics
All Pins Except
Power Supply Pins

CE
N
I/O ports 2.0 VDD V VDD = 3.0V to 5.5V(5)
0.6 VDD VDD V Full VDD range(5)
IO
RM N
Trigger inputs AT
FO VA

Pin at hi-impedance
0.5 +5.0 µA VPIN = VDD(2)
IN AD

RC option only
RC option only
voltage.

12.5 DC Characteristics: PIC16CR54B/56/58B-04E, 10E, 20E (Automotive)


I/O ports Vss 0.15 VDD V Pin at hi-impedance
MCLR (Schmitt Trigger) Vss 0.15 VDD V
T0CKI (Schmitt Trigger) Vss 0.15 VDD V
OSC1 (Schmitt Trigger) Vss 0.15 VDD V RC option only(4)
OSC1 Vss 0.3 VDD V XT, HS and LP options
2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
CE
N
IO
Trigger inputs
RM N
µA VSS ≤ VPIN ≤ VDD,
I/O ports
AT –1.0 0.5 +1.0

Pin at hi-impedance
FO VA

0.5 +5.0 µA VPIN = VDD(2)
IN AD

RC option only
Output High Voltage (3) VOH
RC option only
voltage.


1. TppS2ppS
2. TppS
T
F Frequency T Time
pp
2 to mc MCLR
CE
N
S
F Fall P Period
IO
H High R Rise
RM N
AT
FO VA

IN AD

VSS

FIGURE 12-2: EXTERNAL CLOCK TIMING - PIC16CR54B/56/58B
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54B/56/58B

CE
N
IO
Parameter
RM N
AT DC — 4.0 MHz XT osc mode

FO VA

IN AD


TABLE 12-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54B/56/58B (CON’T)

Parameter

CE
N
250 — 250 ns HS osc mode (04)
IO
100 — 250 ns HS osc mode (10)
50 — 250 ns HS osc mode (20)
RM N
2 TCY AT Instruction Cycle Time(3) — 4/FOSC — —
FO VA
IN AD

FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16CR54B/56/58B
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
19
14 16
I/O Pin
(input)
17 15

(output)
CE
N
20, 21
IO
TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54B/56/58B

RM N
AT Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),

FO VA

Section 12.3.
Parameter
IN AD

12 TckR CLKOUT rise time(2) — 5 15** ns
13 TckF CLKOUT fall time(2) — 5 15** ns
hold time)
(I/O in setup time)

FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -
PIC16CR54B/56/58B
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
CE
N
Timer
RESET
31
IO
34 34
I/O pin
RM N
(Note 1)
AT
FO VA
TABLE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54B/56/58B

IN AD

Parameter

(No Prescaler)
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design

FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16CR54B/56/58B
T0CKI
40 41
42
TABLE 12-5: TIMER0 CLOCK REQUIREMENTS - PIC16CR54B/56/58B

CE
N
Section 12.3.
Parameter
No.
IO
RM N
AT - With Prescaler 10* — — ns

FO VA

(1, 2, 4,..., 256)
IN AD

NOTES:
CE
N
IO
RM N
AT
FO VA
IN AD

Max. Current into VDD pin .....................................................................................................................................100 mA
SI ED
NS
Max. Output Current sourced by a single I/O port
PORTA .........................................................................................................................................................50 mA
DE ND
PORTB or C ...............................................................................................................................................100 mA
G
Max. Output Current sunk by a single I/O port
NE MM T
PORTA .........................................................................................................................................................50 mA
R O NO
PORTB or C ...............................................................................................................................................100 mA
W E
†
NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
C
FO E
R



RC VDD: 3.0V to 6.25V
WDT dis
Freq: 4.0 MHz max
WDT dis
Freq: 4.0 MHz max
WDT dis WDT dis
SI ED
NS
2.5V
N/A N/A N/A
WDT dis
Freq: 200 kHz max
DE D
G
NE MM T
N
R O NO
W E
C
FO E
R


DC Characteristics
Power Supply Pins

Supply Voltage VDD
HS option 4.5 5.5 V
RC(4) and XT options 1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V
SI ED
NS
9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
DE ND
G
µA
NE MM T
Industrial 5.0 14 VDD = 3.0V, WDT enabled
R O NO

W E
C

FO E

R



DC Characteristics
Power Supply Pins

Commercial 15 32 µA FOSC = 32 kHz, VDD = 2.5V,
WDT disabled
Industrial 19 40 µA FOSC = 32 kHz, VDD = 2.5V,
SI ED
WDT disabled
NS
Industrial
DE D 5.0 14 µA VDD = 2.5V, WDT enabled
G
µA
NE MM T
0.8 12 VDD = 2.5V, WDT disabled
N
R O NO
W E
C
FO E
R


DC Characteristics
All Pins Except
Power Supply Pins

2.0 VDD V 4.0V < VDD ≤ 5.5(5)
SI ED
NS
DE ND
G
NE MM T
Trigger inputs
R O NO

W E
Pin at hi-impedance
0.5 +5.0 µA VPIN = VDD(2)
C
RC option only
FO E

RC option only
R

voltage.


1. TppS2ppS
2. TppS
T
F Frequency T Time
pp
2 to mc MCLR
SI ED
S
NS
F Fall P Period
H High R Rise
I
DE D
Invalid (Hi-impedance) V Valid
G
NE MM T
N
R O NO
W E

VSS
C
FO E
R

Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT

SI ED
NS
Parameter
Typ(1)
DE ND
No. Sym Characteristic Min Max Units Conditions
G
External CLKIN Frequency(2)
NE MM T
FOSC DC — 4.0 MHz RC osc mode
R O NO

W E
C

FO E

R



Parameter

SI ED
NS
250 — 250 ns HS osc mode (04)
100 — 250 ns HS osc mode (10)
DE D 50 — 250 ns HS osc mode (20)
G
µs
NE MM T
5.0 — 200 LP osc mode
2 TCY
N
Instruction Cycle Time(3) — 4/FOSC — —
R O NO

W E
C
FO E

R

Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
19
14 16
I/O Pin
(input)
17 15

(output)
SI ED
20, 21
NS
DE ND
G
NE MM T
R O NO

W E
Parameter

C

Port in valid before CLKOUT↑(2)
FO E
15 TioV2ckH 0.25 TCY+30* — — ns

R

hold time)
(I/O in setup time)

VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
SI ED
31
NS
34 34
I/O pin
(Note 1)
DE D
G
NE MM T
N
R O NO
W E
Parameter

C
FO E
(No Prescaler)
R


T0CKI
40 41
42

SI ED
Parameter
No.
NS
DE ND
G
NE MM T
R O NO

W E
(1, 2, 4,..., 256)
C
FO E
R

NOTES:
SI ED
NS
DE D
G
NE MM T
N
R O NO
W E
C
FO E
R

PIC16CR57B Enh. PIC16C5X
14.0 ELECTRICAL CHARACTERISTICS - PIC16CR57B
PORTA .........................................................................................................................................................50 mA
PORTB or C ...............................................................................................................................................100 mA
PORTA .........................................................................................................................................................50 mA
PORTB or C ...............................................................................................................................................100 mA
†

Enh. PIC16C5X PIC16CR57B

OSC PIC16CR57B-04 PIC16CR57B-10 PIC16CR57B-20 PIC16LCR57B-04

WDT dis
Freq: 4.0 MHz max
WDT dis
Freq: 4.0 MHz max
WDT dis WDT dis
2.5V
N/A N/A N/A
WDT dis
Freq: 200 kHz max

14.1 DC Characteristics: PIC16CR57B-04, 10, 20 (Commercial)
PIC16CR57B-04I, 10I, 20I (Industrial)

DC Characteristics
Power Supply Pins

Supply Voltage VDD
HS option 4.5 5.5 V
4.7 17 mA FOSC = 20 MHz, VDD = 5.5V

14.2 DC Characteristics: PIC16CR57B-04E, 10E, 20E (Automotive)


Supply Voltage VDD
9.0 20 mA FOSC = 16 MHz, VDD = 5.5V

14.3 DC Characteristics: PIC16LCR57B-04 (Commercial)
PIC16LCR57B-04I (Industrial)

DC Characteristics
Power Supply Pins

WDT disabled
WDT disabled

14.4 DC Characteristics: PIC16CR57B-04, 10, 20, PIC16LCR57B-04 (Commercial)

PIC16CR57B-04I, 10I, 20I, PIC16LCR57B-04I (Industrial)

DC Characteristics
All Pins Except
Power Supply Pins

2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
Trigger inputs
Pin at hi-impedance
0.5 +5.0 µA VPIN = VDD(2)
RC option only
RC option only
voltage.

14.5 DC Characteristics: PIC16CR57B-04E, 10E, 20E (Automotive)


2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
Trigger inputs
Pin at hi-impedance
MCLR –5.0 µA VPIN = VSS + 0.25 V(2)
0.5 +5.0 µA VPIN = VDD(2)
RC option only
RC option only
voltage.


1. TppS2ppS
2. TppS
T
F Frequency T Time
pp
2 to mc MCLR
S
F Fall P Period
H High R Rise

VSS

FIGURE 14-2: EXTERNAL CLOCK TIMING - PIC16CR57B
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
TABLE 14-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR57B

Parameter


TABLE 14-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR57B (CON’T)

Parameter

250 — 250 ns HS osc mode (04)
100 — 250 ns HS osc mode (10)
50 — 250 ns HS osc mode (20)

FIGURE 14-3: CLKOUT AND I/O TIMING - PIC16CR57B
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
19
14 16
I/O Pin
(input)
17 15

(output)
20, 21
TABLE 14-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR57B

Section 14.3.
Parameter

hold time)
(I/O in setup time)

FIGURE 14-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR57B
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)
TABLE 14-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR57B

Parameter

(No Prescaler)

FIGURE 14-5: TIMER0 CLOCK TIMINGS - PIC16CR57B
T0CKI
40 41
42
TABLE 14-5: TIMER0 CLOCK REQUIREMENTS - PIC16CR57B

Section 14.3.
Parameter
No.
(1, 2, 4,..., 256)

NOTES:

15.0 ELECTRICAL CHARACTERISTICS - PIC16C58A
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature ............................................................................................................................. - 65°C to +150°C
Voltage on all other pins with respect to VSS .................................................................................. -0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin ...................................................................................................................................150 mA
Max. current into VDD pin ......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only) .....................................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD) ..............................................................................................................±20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin ............................................................................................................20 mA
Max. output current sourced by a single I/O port
PORTA .........................................................................................................................................................50 mA
PORTB .......................................................................................................................................................100 mA
Max. output current sunk by a single I/O port
PORTA .........................................................................................................................................................50 mA
PORTB .......................................................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS
†


OSC PIC16C58A-04 PIC16C58A-10 PIC16C58A-20 PIC16LC58A-04 PIC16C58A/JW

IDD: 2.5 mA max. at IDD: 1.8 mA typ. at IDD: 1.8 mA typ. at IDD: 0.5 mA typ. at IDD: 2.5 mA max. at
5.5V 5.5V 5.5V 5.5V 5.5V
RC
Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max.
IDD 2.5 mA max. at IDD: 1.8 mA typ. at IDD: 1.8 mA typ. at IDD: 0.5 mA typ. at IDD 2.5 mA max. at
5.5V 5.5V 5.5V 5.5V 5.5V
XT
Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max. Freq: 4.0 MHz max.
VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V
IDD: 1.9 mA typ. at IDD: 8.0 mA max. at IDD: 17 mA max. at IDD: 17 mA max. at
5.5V 5.5V 5.5V Do not use in 5.5V
HS
IPD: 0.25 µA typ. at IPD: 4.0 µA max. at IPD: 4.0 µA max. at HS mode IPD: 4.0 µA max. at
3.0V WDT dis 3.0V WDT dis 3.0V WDT dis 3.0V WDT dis
Freq: 4.0 MHz max. Freq: 10 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.
VDD: 3.0V to 6.25V VDD: 2.5V to 6.25V VDD: 2.5V to 6.25V
IDD: 15 µA typ. at IDD: 28 µA max. at IDD: 28 µA max. at
32kHz, 3.0V 32kHz, 2.5V 32kHz, 2.5V
Do not use in Do not use in
LP IPD: 0.25 µA typ. at WDT dis WDT dis
LP mode LP mode
3.0V WDT dis IPD: 4.0 µA max. at IPD: 4.0 µA max. at
Freq: 200 kHz max. 2.5V WDT dis 2.5V WDT dis
Freq: 200 kHz max. Freq: 200 kHz max.

15.1 DC Characteristics: PIC16C58A-04, 10, 20 (Commercial)
PIC16C58A-04I, 10I, 20I (Industrial)

DC Characteristics
Power Supply Pins

Supply Voltage VDD
HS option 4.5 5.5 V
Power-On Reset
Power-On Reset
4.7 17 mA FOSC = 20 MHz, VDD = 5.5V
LP option, Commercial 15 µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP option, Industrial 18 µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled

15.2 DC Characteristics: PIC16C58A-04E, 10E, 20E (Automotive)


Supply Voltage VDD
XT and RC options 3.5 5.5 V
HS option 4.5 5.5 V
Power-On Reset
Power-On Reset
9.0 20 mA FOSC = 20 MHz, VDD = 5.5V
XT and RC options 5.0 22 µA VDD = 3.5V, WDT enabled
HS option 4.0 22 µA VDD = 3.5V, WDT enabled

15.3 DC Characteristics: PIC16LC58A-04 (Commercial)
PIC16LC58A-04I (Industrial)

DC Characteristics
Power Supply Pins

Supply Voltage VDD
(2)
RAM Data Retention Voltage VDR 1.5* V Device in SLEEP mode
Power-On Reset
Power-On Reset
XT and RC(4) options 0.5 mA FOSC = 4.0 MHz, VDD = 5.5V
LP option, Commercial 12 28 µA FOSC = 32 kHz, VDD = 2.5V WDT disabled
LP option, Industrial 15 37 µA FOSC = 32 kHz, VDD = 2.5V WDT disabled

15.4 DC Characteristics: PIC16C58A-04, 10, 20, PIC16LC58A-04 (Commercial),

PIC16C58A-04I, 10I, 20I, PIC16LC58A-04I (Industrial),
PIC16C58A-04E, 10E, 20E (Automotive)

DC Characteristics
All Pins Except
Power Supply Pins
Section 15.3.
I/O ports 0.2 VDD+1V VDD V For all VDD(5)
2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
Trigger inputs
I/O ports -1.0 0.5 +1.0 µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
MCLR -5.0 µA VPIN = VSS +0.25V(2)
0.5 +5.0 µA VPIN = VDD(2)
T0CKI -3.0 0.5 +3.0 µA VSS ≤ VPIN ≤ VDD
OSC1 -3.0 0.5 +3.0 µA VSS ≤ VPIN ≤ VDD,
RC option only
Output High Voltage VOH
I/O ports(3) VDD-0.7 V IOH = -5.4 mA, VDD = 4.5V
OSC2/CLKOUT VDD-0.7 V IOH = -1.0 mA, VDD = 4.5V,
RC option only
voltage.

1. TppS2ppS
2. TppS
T
F Frequency T Time
pp
2 to mc MCLR
S
F Fall P Period
H High R Rise
FIGURE 15-1: LOAD CONDITIONS - PIC16C58A

VSS

FIGURE 15-2: EXTERNAL CLOCK TIMING - PIC16C58A
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT
TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C58A

Parameter


TABLE 15-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C58A (CON’T)

Parameter

250 — 250 ns HS osc mode (04)
100 — 250 ns HS osc mode (10)
50 — 250 ns HS osc mode (20)

FIGURE 15-3: CLKOUT AND I/O TIMING - PIC16C58A
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
14 19 16
I/O Pin
(input)
17 15

(output)
20, 21
TABLE 15-3: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C58A

Section 15.3.
Parameter

hold time)
(I/O in setup time)

FIGURE 15-4: RESET, WATCHDOG TIMER, AND
DEVICE RESET TIMER TIMING - PIC16C58A
VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)
TABLE 15-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C58A

Parameter

(No Prescaler)

FIGURE 15-5: TIMER0 CLOCK TIMINGS - PIC16C58A
T0CKI
40 41
42
TABLE 15-5: TIMER0 CLOCK REQUIREMENTS - PIC16C58A

Section 15.3.
Parameter
No.
(1, 2, 4,..., 256)

PORTA .........................................................................................................................................................50 mA
PORTB .......................................................................................................................................................100 mA
PORTA .........................................................................................................................................................50 mA
PORTB .......................................................................................................................................................100 mA
†



WDT dis
Freq: 4.0 MHz max
WDT dis
Freq: 4.0 MHz max
IDD: 8.0 mA max at 5.5V IDD: 17 mA max at 5.5V
WDT dis WDT dis
2.5V
N/A N/A N/A
WDT dis
Freq: 200 kHz max


DC Characteristics
Power Supply Pins

Supply Voltage VDD
HS option 4.5 5.5 V
4.7 17 mA FOSC = 20 MHz, VDD = 5.5V



Supply Voltage VDD
9.0 20 mA FOSC = 16 MHz, VDD = 5.5V


DC Characteristics
Power Supply Pins

WDT disabled
WDT disabled



DC Characteristics
All Pins Except
Power Supply Pins

2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
Trigger inputs
Pin at hi-impedance
0.5 +5.0 µA VPIN = VDD(2)
RC option only
RC option only
voltage.



2.0 VDD V 4.0V < VDD ≤ 5.5V(5)
Trigger inputs
Pin at hi-impedance
0.5 +5.0 µA VPIN = VDD(2)
RC option only
RC option only
voltage.


1. TppS2ppS
2. TppS
T
F Frequency T Time
pp
2 to mc MCLR
S
F Fall P Period
H High R Rise

VSS

Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT

Parameter



Parameter

250 — 250 ns HS osc mode (04)
100 — 250 ns HS osc mode (10)
50 — 250 ns HS osc mode (20)

Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 18 12
19
14 16
I/O Pin
(input)
17 15

(output)
20, 21

Section 16.3.
Parameter

hold time)
(I/O in setup time)

VDD
MCLR
30
Internal
POR
32 32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O pin
(Note 1)

Parameter

(No Prescaler)

T0CKI
40 41
42

Section 16.3.
Parameter
No.
(1, 2, 4,..., 256)

NOTES:

All Enh. PIC16C5X, Except PIC16CR54A Enh. PIC16C5X
17.0 DC AND AC CHARACTERISTICS - ALL ENH. PIC16C5X,
EXCEPT PIC16CR54A
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some
graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is
for information only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 17-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC Frequency normalized to +25°C
FOSC (25°C)
1.10
Rext ≥ 10 kΩ
1.08
Cext = 100 pF
1.06
1.04
1.02
1.00
0.98
VDD = 5.5 V
0.96
0.94
VDD = 3.5 V
0.92
0.90
0.88
0 10 20 25 30 40 50 60 70
T(°C)
TABLE 17-1: RC OSCILLATOR FREQUENCIES

Average
Cext Rext
Fosc @ 5 V, 25°C
20 pF 3.3 k 4.973 MHz ± 27%
5k 3.82 MHz ± 21%
10 k 2.22 MHz ± 21%
100 k 262.15 kHz ± 31%
100 pF 3.3 k 1.63 MHz ± 13%
5k 1.19 MHz ± 13%
10 k 684.64 kHz ± 18%
100 k 71.56 kHz ± 25%
300 pF 3.3 k 660 kHz ± 10%
5.0 k 484.1 kHz ± 14%
10 k 267.63 kHz ± 15%
160 k 29.44 kHz ± 19%
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for VDD = 5 V.

Enh. PIC16C5X All Enh. PIC16C5X, Except PIC16CR54A
FIGURE 17-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20PF

6.00
R=3.3K
5.00
R=5.0K
4.00
Fosc(MHz)
3.00
R=10K
2.00
Cext=20pF, T=25C
1.00
R=100K
0.00
2.5 3 3.5 4 4.5 5 5.5 6
VDD(Volts)
TYPICAL RC
FIGURE 17-3: TYPICAL RC OSCILLATOR OSCILLATOR FREQUENCY
FREQUENCY vsEXT
vs. VDD, C VDD= 100 PF
1.80
R=3.3K
1.60
1.40
R=5.0K
1.20
1.00
Fosc(MHz)
0.80
R=10K
0.60
Cext=100pF, T=25C
0.40
0.20
R=100K
0.00
2.5 3 3.5 4 4.5 5 5.5 6
VDD(Volts)

FIGURE 17-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF
700.00
R=3.3K
600.00
500.00
R=5.0K
400.00
Fosc(KHz)
300.00
R=10K
200.00
Cext=300pF, T=25C
100.00
R=100K
0.00
2.5 3 3.5 4 4.5 5 5.5 6
VDD(Volts)

p
FIGURE 17-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)
2.5
1.5
Ipd(nA)
0.5
0
2.5 3 3.5 4 4.5 5 5.5 6
VDD(Volts)
p
FIGURE 17-6: MAXIMUM IPD vs. VDD, WATCHDOG DISABLED (-40°C TO +85°C)
60.00
50.00
85C
40.00
Ipd(nA)
30.00
20.00 70C
0C
10.00
-40C
0.00
2.5 3 3.5 4 4.5 5 5.5 6
VDD(Volts)

p
FIGURE 17-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25°C)
25.00
20.00
15.00
Ipd(uA)
10.00
5.00
0.00
2.5 3 3.5 4 4.5 5 5.5 6
VDD(Volts)
FIGURE 17-8: MAXIMUM IPD vs. VDD, WATCHDOG ENABLED (-40°C TO +85°C)
35.00
-40C
30.00 0C
70C
25.00
85C
20.00
Ipd(uA)
15.00
10.00
5.00
0.00
2.5 3 3.5 4 4.5 5 5.5 6
VDD(Volts)

FIGURE 17-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.00
+85°C
1.80 )
to
–40°C
1.60 Max (
VTH (Volts)
1.40 2 5°C)
Typ (+
1.20
1.00 + 85°C)
4 0°C to
Min (–
0.80
0.60
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 17-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
4.0
+8 5°C)
°C to
3.5 (–40
max
VIH °C
+25
typ C)
+85°
3.0
VIH
VIH, VIL (Volts)
° C t o
2.5 (–40
min
VIH
2.0
1.5 °C to +85°C)
VIL max (–40
1.0 VIH typ +25°C
0.5 5°C)
VIL min (–40°C to +8
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
Note: These input pins have Schmitt Trigger input buffers.
FIGURE 17-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT

(IN XT, HS, AND LP MODES) vs. VDD
3.4
3.2
3.0
2.8 °C)
o +85
2.6 °C t
(–40
2.4 Max °C)
( +25
VTH (Volts)
2.2 Typ
C)
2.0 o+ 85°
4 0°C t
(–
1.8 Min
1.6
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)

TYPICAL Idd vs(WDT
FIGURE 17-12: TYPICAL IDD vs. FREQUENCY FREQ(RC MODE
DIS, RC@MODE
20pF/25C)@ 20PF, 25°C)
10000
1000
Idd(uA)
6.0V
5.5V
5.0V
100 4.5V
4.0V
3.5V
3.0V
2.5V
10
100000 1000000 10000000
Freq(Hz)
MAXIMUM Idd vs
FIGURE 17-13: MAXIMUM IDD vs. FREQUENCY FREQ(RC
(WDT MODE
DIS, RC@ MODE
20pF) @ 20PF, -40°C TO +85°C)
10000
1000
Idd(uA)
6.0V
5.5V
5.0V
4.5V
100 4.0V
`3.5V
3.0V
2.5V
10
100000 1000000 10000000
Freq(Hz)

TYPICAL Idd vs
FIGURE 17-14: TYPICAL IDD vs. FREQUENCY FREQ(RC
(WDT MODE
DIS, RC@ 100pF/25C)
MODE @ 100PF, 25°C)
10000
1000
Idd(uA)
6.0V
100 5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
10000 100000 1000000 10000000
Freq(Hz)
FIGURE 17-15: MAXIMUM IDD vs. FREQUENCY (WDT (DIS, RC@MODE

p ) @ 100PF, -40°C TO +85°C)
10000
1000
Idd(uA)
6.0V
5.5V
5.0V
100 4.5V
4.0V
3.5V
3.0V
2.5V
10
10000 100000 1000000 10000000
Freq(Hz)

PC dd s(WDT
FIGURE 17-16: TYPICAL IDD vs. FREQUENCY R Q(RC O RC
DIS, @ 300p
MODE /25C)@ 300PF, 25°C)
10000
1000
Idd(uA)
6.0V
100 5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
10000 100000 1000000
Freq(Hz)
FIGURE 17-17: MAXIMUM IDD vs. FREQUENCY (WDT( DIS, RC

@ MODE
p ) @ 300PF, -40°C TO +85°C)
10000
1000
Idd(uA)
6.0V
5.5V
5.0V
100 4.5V
4.0V
3.5V
3.0V
2.5V
10
10000 100000 1000000
Freq(Hz)

FIGURE 17-18: WDT TIMER TIME-OUT TABLE 17-2: INPUT CAPACITANCE FOR
PERIOD vs. VDD PIC16C54A/C58A
50 Typical Capacitance (pF)
Pin
18L PDIP 18L SOIC
45
RA port 5.0 4.3
RB port 5.0 4.3
40
MCLR 17.0 17.0
35 OSC1 4.0 3.5

WDT period (ms)
OSC2/CLKOUT 4.3 3.5

30 T0CKI 3.2 2.8
Max +85°C
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
25
taken into account.
Max +70°C
20
Typ +25°C
15
MIn 0°C
10
MIn –40°C
5
2 3 4 5 6 7
VDD (Volts)

FIGURE 17-19: TRANSCONDUCTANCE (gm) FIGURE 17-20: TRANSCONDUCTANCE (gm)
OF HS OSCILLATOR vs. VDD OF LP OSCILLATOR vs. VDD
9000 45
8000 40
Max –40°C Max –40°C
7000 35
6000 30
5000 25
gm (µA/V)
gm (µA/V)
Typ +25°C
Typ +25°C
4000 20
3000 15
Min +85°C
2000 10
Min +85°C
100 5
0 0
2 3 4 5 6 7 2 3 4 5 6 7
VDD (Volts) VDD (Volts)
FIGURE 17-21: TRANSCONDUCTANCE (gm)

OF XT OSCILLATOR vs. VDD
2500
Max –40°C
2000
1500
gm (µA/V)
Typ +25°C
1000
Min +85°C
500
0
2 3 4 5 6 7
VDD (Volts)

FIGURE 17-22: IOH vs. VOH, VDD = 3 V FIGURE 17-24: IOL vs. VOL, VDD = 3 V
0 45
40 Max –40°C
–5
Min +85°C
35
30
–10
IOH (mA)
25
IOL (mA)
Typ +25°C
Typ +25°C
–15 20
Max –40°C
15
–20 Min +85°C

10
5
–25
0 0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts) 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
FIGURE 17-23: IOH vs. VOH, VDD = 5 V FIGURE 17-25: IOL vs. VOL, VDD = 5 V
0 90
80 Max –40°C
Min +85°C
–10 70
60
Typ +25°C
IOH (mA)
–20 50
IOL (mA)
Typ +25°C
40
Min +85°C
–30 30
Max –40°C
20
–40 10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts) 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)

18.0 DC AND AC CHARACTERISTICS - PIC16CR54A
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some
graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is
for information only and devices are will properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 18-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC Frequency normalized to +25°C
FOSC (25°C)
1.10
Rext ≥ 10 kΩ
1.08 Cext = 100 pF
1.06
1.04
1.02
1.00
0.98
VDD = 5.5V
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0 10 20 25 30 40 50 60 70
T(°C)
TABLE 18-1: RC OSCILLATOR FREQUENCIES
Average
Cext Rext Fosc @ 5V, 25°C
Part to Part Variation
20 pF 3.3 k 6.02 MHz ± 28%
5k 4.06 MHz ± 25%
10 k 2.47 MHz ± 24%
100 k 261 kHz ± 39%
100 pF 3.3 k 1.82 MHz ± 18%
5k 1.28 MHz ± 21%
10 k 715 kHz ± 18%
100 k 72.4 kHz ± 28%
300 pF 3.3 k 712.4 kHz ± 14%
5k 508 kHz ± 13%
10 k 278 kHz ± 13%
100 k 28 kHz ± 23%
Measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for full VDD range.

FIGURE 18-2: TYPICAL RC OSCILLATOR FIGURE 18-3: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD, FREQUENCY vs. VDD,
CEXT = 20 PF CEXT = 100 PF
6.5 2.0
R = 3.3k R = 3.3k
6.0 1.8
5.5 1.6
5.0 1.4
R = 5k
4.5 1.2
Fosc (MHz)
R = 5k
4.0 1.0
3.5 0.8
R = 10k
Fosc (MHz)
3.0 0.6
Measured on DIP Packages, T = 25˚C
R = 10k
2.5 0.4
2.0 0.2
R = 100k
1.5 0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
1.0
0.5
R = 100k
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)

FIGURE 18-4: TYPICAL RC OSCILLATOR FIGURE 18-5: TYPICAL IPD vs. VDD,
FREQUENCY vs. VDD, WATCHDOG ENABLED
CEXT = 300 PF
0.8
R = 3.3k 10
0.7
T = 25˚C
0.6
R = 5k 1.0
0.5
IPD (µA)
FOSC (MHz)
0.4
0.1
0.3 R = 10k
0.2
0.01
0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
R = 100k
VDD (Volts)
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 18-6: MAXIMUM IPD vs. VDD,

WATCHDOG ENABLED
35
30
–40°C
25
20
IPD (µA)
15
10 +85°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)

FIGURE 18-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.00
1.80
to + 85°C)
–40°C
1.60 Max (
VTH (Volts)
1.40 2 5°C)
Typ (+
to + 85°C)
1.20 40°C
Min (–
1.00
0.80
0.60
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
FIGURE 18-8: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
4.0
°C)
3.5 to + 85
(–40°C
max
3.0 VIH
VIH, VIL (Volts)
C)
25°C +85°
2.5 typ + °C to
VIH (–40
min
VIH
2.0
1.5
°C to +85°C)
VIL typ +25°C VIL max (–40
1.0
0.5 5°C)
VIL min (–40°C to +8
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Note: These input pins have Schmitt Trigger input buffers. VDD (Volts)
FIGURE 18-9: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT

(IN XT, HS, AND LP MODES) vs. VDD
3.4
3.2
3.0
2.8
2.6
C)
2.4 o+85° )
°C t 5°C
VTH (Volts)
– 4 0 (+2
2.2
Max
( Typ
)
2.0 5°C
Ct o +8
1.8 (– 40°
1.6 Min
1.4
1.2
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)

FIGURE 18-10: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C)
10
1.0
Idd (mA)
0.1
6.0
5.5
5.0
4.5
0.01 4.0
3.5
3.0
2.5
0.001
10k 100k 1M 10M
External Clock Frequency (Hz)

FIGURE 18-11: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –40°C TO +85°C)
10000
1000
IDD (µA)
100
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
10
10k 100k 1M 10M
External Clock Frequency (Hz)

FIGURE 18-12: WDT TIMER TIME-OUT FIGURE 18-13: TRANSCONDUCTANCE (gm)
PERIOD vs. VDD OF HS OSCILLATOR vs. VDD
50 9000
45 8000
40 7000
35 6000
Max –40°C
WDT period (ms)
30 Max +85°C 5000
gm (µA/V)
Typ +25°C Typ +25°C
25 4000
Max +70°C
Min +85°C
20 3000
15 2000
MIn 0°C
10 100
MIn –40°C
5 0
2 3 4 5 6 7 2 3 4 5 6 7
VDD (Volts) VDD (Volts)

FIGURE 18-14: TRANSCONDUCTANCE (gm) FIGURE 18-16: IOH vs. VOH, VDD = 3 V
OF LP OSCILLATOR vs. VDD
45 0
Max –40°C
40
–5
35 Min +85°C
30
–10
Typ +25°C Typ +25°C
IOH (mA)
25
gm (µA/V)
20 –15
15 Max –40°C
Min +85°C –20

10
5
–25
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0
2 3 4 5 6 7 VOH (Volts)
VDD (Volts)
FIGURE 18-15: TRANSCONDUCTANCE (gm) FIGURE 18-17: IOH vs. VOH, VDD = 5 V
OF XT OSCILLATOR vs. VDD
2500 0
–5
2000
Max –40°C
–10
Min +85°C
–15
1500
IOH (mA)
–20
gm (µA/V)
Typ +25°C
Typ +25°C
1000 –25
Min +85°C –30

500
Max –40°C
–35
–40
0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
2 3 4 5 6 7
VDD (Volts) VOH (Volts)

FIGURE 18-18: IOL vs. VOL, VDD = 3 V FIGURE 18-19: IOL vs. VOL, VDD = 5 V
45 90
40 Max –40°C 80 Max –40°C
35 70
30 60
Typ +25°C
25 Typ +25°C 50
IOL (mA)
IOL (mA)
20 40
15 30 Min +85°C
Min +85°C
10 20
5 10
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts) VOL (Volts)
TABLE 18-2: INPUT CAPACITANCE FOR

PIC16CR54A
Typical Capacitance (pF)
Pin 18L PDIP 18L SOIC

RA, RB port 5.0 4.3
MCLR 2.0 2.0
OSC1, OSC2/CLKOUT 4.0 3.5
T0CKI 3.2 2.8
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.

NOTES:

Enhanced PIC16C5X
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
18-Lead PDIP Example
MMMMMMMMMMMMXXX PIC16LCR56-
MMMMMMMMXXXXXXX 40I/P456
AABB CDE 9523 CBA
28-Lead Skinny PDIP (.300") Example
MMMMMMMMMMMMMMMMM PIC16CR58A-
XXXXXXXXXXXXXXXXX 04I/P456
AABB CDE 9523 CBA
28-Lead PDIP (.600") Example
MMMMMMMMMMMMXXX PIC16C58B-
MMMMMMMMXXXXXXX 10I/P126
XXXXXXXXXXXXXXX
AABB CDE 9542 CDA
Legend: MM...M Microchip part number information

XX...X Customer specific information*
AA Year code (last 2 digits of calendar year)
BB Week code (week of January 1 is week ‘01’)
C Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
D Mask revision number
E Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking
beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in
QTP price.

Enhanced PIC16C5X
18-Lead SOIC Example
MMMMMMMMM PIC16C54A-
XXXXXXXXX 10I/S0218
AABB CDE 9518 CDK
28-Lead SOIC Example
MMMMMMMMMMMMMMMMMMXX PIC16CR57A-20/SO301
XXXXXXXXXXXXXXXXXXXX
AABB CDE 9515 CBK
20-Lead SSOP Example
MMMMMMMM PIC16C54A
XXXXXXXX 10I/218
AABB CDE 9520 CBP
28-Lead SSOP Example

MMMMMMMMMMMM PIC16CR57B-
XXXXXXXXXXXX 20/SS123
AABB CDE 9525 CBK

part was assembled
QTP price.

Enhanced PIC16C5X
18-Lead CERDIP Windowed Example
MMMMMMMM PIC16C54A
MMMMMMMM /JW
AABB CDE 9501 CBA
28-Lead CERDIP Skinny Windowed Example
MMMMMMMMMMMMMM PIC16C58A
XXXXXXXXXXXXXX /JW
AABBCDE 9338 CCT
28-Lead CERDIP Windowed Example
MMMMMMMMMM PIC16C58A
MMMMMM /JW
AABB CDE 9538 CBA

part was assembled
QTP price.

Enhanced PIC16C5X
19.2 18-Lead Plastic Dual In-Line (PDIP) - 300 mil
N
α
C
E1 E
eA
Pin No. 1 eB
Indicator
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A2 A
B
D1
Package Group: Plastic Dual In-Line (PLA)

Millimeters Inches
Symbol Min Max Notes Min Max Notes
α 0° 10° 0° 10°
A – 4.064 – 0.160
A1 0.381 – 0.015 –
A2 3.048 3.810 0.120 0.150
B 0.355 0.559 0.014 0.022
B1 1.524 1.524 Reference 0.060 0.060 Reference
C 0.203 0.381 Typical 0.008 0.015 Typical
D 22.479 23.495 0.885 0.925
D1 20.320 20.320 Reference 0.800 0.800 Reference
E 7.620 8.255 0.300 0.325
E1 6.096 7.112 0.240 0.280
e1 2.489 2.591 Typical 0.098 0.102 Typical
eA 7.620 7.620 Reference 0.300 0.300 Reference
eB 7.874 9.906 0.310 0.390
L 3.048 3.556 0.120 0.140
N 18 18 18 18
S 0.889 – 0.035 –
S1 0.127 – 0.005 –

Enhanced PIC16C5X
E1 E α
C
Pin No. 1 eA
Indicator eB
Area
B2 B1
D
S
Base
Plane
Seating
Plane L
Detail A B3 B
e1 A1 A2 A
D1 Detail A

Millimeters Inches
α 0° 10° 0° 10°
A 3.632 4.572 0.143 0.180
A1 0.381 – 0.015 –
A2 3.175 3.556 0.125 0.140
B 0.406 0.559 0.016 0.022
B1 1.016 1.651 Typical 0.040 0.065 Typical
B2 0.762 1.016 4 places 0.030 0.040 4 places
B3 0.203 0.508 4 places 0.008 0.020 4 places
D 34.163 35.179 1.385 1.395
E 7.874 8.382 0.310 0.330
E1 7.112 7.493 0.280 0.295
eB 8.128 9.652 0.320 0.380
L 3.175 3.683 0.125 0.145
N 28 - 28 -
S 0.584 1.220 0.023 0.048

Enhanced PIC16C5X
α
E1 E C
Pin No. 1 eA
Indicator eB
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A2 A
B
D1

Millimeters Inches
α 0° 10° 0° 10°
A – 5.080 – 0.200
A1 0.508 – 0.020 –
A2 3.175 4.064 0.125 0.160
B 0.355 0.559 0.014 0.022
D 35.052 37.084 1.380 1.460
E 15.240 15.875 0.600 0.625
E1 12.827 13.970 0.505 0.550
eB 15.240 17.272 0.600 0.680
L 2.921 3.683 0.115 0.145
N 28 28 28 28
S 0.889 – 0.035 –
S1 0.508 – 0.020 –

Enhanced PIC16C5X
19.5 18-Lead Plastic Surface Mount (SOIC) - 300 mil
e
B
h x 45°
Index
Area
E H α C
Chamfer L
h x 45°
1 2 3
CP Base
Seating Plane
Plane
A1 A
Package Group: Plastic SOIC (SO)

Millimeters Inches
α 0° 8° 0° 8°
A 2.362 2.642 0.093 0.104
A1 0.101 0.300 0.004 0.012
B 0.355 0.483 0.014 0.019
C 0.241 0.318 0.009 0.013
D 11.353 11.735 0.447 0.462
E 7.416 7.595 0.292 0.299
e 1.270 1.270 Reference 0.050 0.050 Reference
H 10.007 10.643 0.394 0.419
h 0.381 0.762 0.015 0.030
L 0.406 1.143 0.016 0.045
N 18 18 18 18
CP – 0.102 – 0.004

Enhanced PIC16C5X
19.6 28-Lead Plastic Surface Mount (SOIC) - 300 mil
e
B
h x 45°
Index
Area
E H α C
Chamfer L
h x 45°
1 2 3
CP Base
Seating Plane
Plane
A1 A
Package Group: Plastic SOIC (SO)

Millimeters Inches
α 0° 8° 0° 8°
A 2.362 2.642 0.093 0.104
A1 0.101 0.300 0.004 0.012
B 0.355 0.483 0.014 0.019
C 0.241 0.318 0.009 0.013
D 17.703 18.085 0.697 0.712
E 7.416 7.595 0.292 0.299
e 1.270 1.270 Typical 0.050 0.050 Typical
H 10.007 10.643 0.394 0.419
h 0.381 0.762 0.015 0.030
L 0.406 1.143 0.016 0.045
N 28 28 28 28
CP – 0.102 – 0.004

Enhanced PIC16C5X
19.7 20-Lead Plastic Surface Mount (SSOP) - 209 mil
N
Index
area
E H
α
C
L
1 2 3
e B
A Base plane
CP
Seating plane
D A1
Package Group: Plastic SSOP

Millimeters Inches
α 0° 8° 0° 8°
A 1.730 1.990 0.068 0.078
A1 0.050 0.210 0.002 0.008
B 0.250 0.380 0.010 0.015
C 0.130 0.220 0.005 0.009
D 7.070 7.330 0.278 0.289
E 5.200 5.380 0.205 0.212
H 7.650 7.900 0.301 0.311
L 0.550 0.950 0.022 0.037
N 20 20 20 20
CP - 0.102 - 0.004

Enhanced PIC16C5X
19.8 28-Lead Plastic Surface Mount (SSOP) - 209 mil
N
Index
area
E H
α
C
L
1 2 3
e B
A Base plane
CP
Seating plane
D A1
Package Group: Plastic SSOP

Millimeters Inches
α 0° 8° 0° 8°
A 1.730 1.990 0.068 0.078
A1 0.050 0.210 0.002 0.008
B 0.250 0.380 0.010 0.015
C 0.130 0.220 0.005 0.009
D 10.070 10.330 0.396 0.407
E 5.200 5.380 0.205 0.212
H 7.650 7.900 0.301 0.311
L 0.550 0.950 0.022 0.037
N 28 28 28 28
CP - 0.102 - 0.004

Enhanced PIC16C5X
19.9 18-Lead Ceramic Dual In-Line (CERDIP) with Window - 300 mil
α C
E1 E
eA
Pin No. 1 eB
Indicator
Area
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A3 A A2
B
D1
Package Group: Ceramic Dual In-Line (CDP)

Millimeters Inches
α 0° 10° 0° 10°
A — 5.080 — 0.200
A1 0.381 1.7780 0.015 0.070
A2 3.810 4.699 0.150 0.185
A3 3.810 4.445 0.150 0.175
B 0.355 0.585 0.014 0.023
D 22.352 23.622 0.880 0.930
E 7.620 8.382 0.300 0.330
E1 5.588 7.874 0.220 0.310
e1 2.540 2.540 Reference 0.100 0.100 Reference
eA 7.366 8.128 Typical 0.290 0.320 Typical
eB 7.620 10.160 0.300 0.400
L 3.175 3.810 0.125 0.150
N 18 18 18 18
S 0.508 1.397 0.020 0.055
S1 0.381 1.270 0.015 0.050

Enhanced PIC16C5X
19.10 28-Lead Ceramic Dual In-Line (CERDIP) with Window - 600 mil
E1 E
α C
Pin No. 1
Indicator eA
Area eB
D
S S1
Base
Plane
Seating
Plane L
B1 e1 A1 A3 A A2
B
D1
Package Group: Ceramic Dual In-Line (CDP)

Millimeters Inches
α 0° 10° 0° 10°
A — 5.461 — 0.215
A1 0.381 1.524 0.015 0.060
A2 3.810 4.699 0.150 0.185
A3 3.810 4.445 0.150 0.175
B 0.355 0.585 0.014 0.023
D 36.195 37.465 1.425 1.475
E 15.240 15.875 0.600 0.625
E1 12.954 15.240 0.510 0.600
eB 15.240 18.034 0.600 0.710
L 3.175 3.810 0.125 0.150
N 28 28 28 28
S 1.016 2.286 0.040 0.090
S1 0.381 1.778 0.015 0.070

Enhanced PIC16C5X
APPENDIX A: COMPATIBILITY APPENDIX B: WHAT’S NEW
To convert code written for PIC16CXX to PIC16C5X,
B.1 Format
the user should take the following steps:
1. Check any CALL, GOTO or instructions that The format of this data sheet has been changed to be
modify the PC to determine if any program consistent with other product families. This ensures
memory page select operations (PA2, PA1, PA0 that important topics are covered across all PIC16/17
bits) need to be made. families. Here is an overview list of new features:
2. Revisit any computed jump operations (write to • Data Sheet Structure / Outline
PC or add to PC, etc.) to make sure page bits • Consistent Figures and Tables
are set properly under the new scheme.
3. Eliminate any special function register page B.2 Additions
switching. Redefine data variables to reallocate
Items that have been added to this data sheet are:
them.
4. Verify all writes to STATUS, OPTION, and FSR • PIC16CR54A, PIC16CR54B, PIC16CR55,
registers since these have changed. PIC16CR56, PIC16CR57B and PIC16CR58B
data
5. Change reset vector to proper value for
processor used. • PIC16C5X-10 data
6. Remove any use of the ADDLW and SUBLW • PIC16C5X/JW package information
instructions.
7. Rewrite any code segments that use interrupts.

Enhanced PIC16C5X
APPENDIX C: WHAT’S CHANGED
Changes to this version of the PIC16C5XA data sheet
are:
• Correction of the 28-lead SSOP package pin-out
• Inclusion of errata sheet information

TABLE D-1:
 1996 Microchip Technology Inc.

) y )
Hz or (s ls
(M e T)
n em ul R n ne g
io M od in
rat M SA ha m
pe am ,U )C ) m
O gr W
M 2C it ts ra
of ro s) t -b ol og
c y P y te e /P PI/I o r 1 6 s (V r t
n r ( e
PIC14XXX FAMILY OF DEVICES
(b s) S P rc lP se
q ue r y l e( pa s) ( v e t er u ge r ia e
e o u o m t( a r o a n e R
Fr od or Sl ve R tS ut s
M em M /C tS s
e ui -o ge
um O M r u re al P l l el C on rup i n g r c n k a
im R ta e pt ri ra r P lta i c
ax m D te -C ow
M EP Da Ti Ca Se Pa A/ In I/O Vo In Br Pa
APPENDIX D: PIC16/17 MICROCONTROLLERS
PIC14000 20 4K 192 TMR0 — SPI/I2C — 8 11 22 3.0-6.0 Yes — 28-pin SDIP, SOIC

DS30236B-page 187
Enhanced PIC16C5X
TABLE D-2:
DS30236B-page 188
ry
)
Hz
(M
n
s) o
io
rd em
)
at
o
r
ra
es
(w m M
pe
yt
og
O
)
(b
ns
Pr
ts
of
y
tio
ol
cy
or
(V
uc
s)
en
tr
u
em
le(
ge
M
ns
eq
n
I
du
Fr
ta
o
of
Ra
es
M
M
Da
um
ns
ag
O
ge
be
k
im
er
Pi
M
m
lta
AM
m
PR
ax
ac
E
RO
Enhanced PIC16C5X
M
I/O
P
Ti
Nu
Vo
PIC16C5X FAMILY OF DEVICES
PIC16C52 4 384 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC

PIC16C54 20 512 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C54A 20 512 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR54A 20 — 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C55 20 512 — 24 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16C56 20 1K — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C57 20 2K — 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16CR57B 20 — 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16C58A 20 2K — 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR58A 20 — 2K 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and
high I/O current capability.

TABLE D-3:

) y
Hz or
(M
n em
tio M ge
ra
pe r am l ta )
ofO og s) Vo lts
y Pr te c e s o
nc ( by s) ce (V et
ue e( ) en r ge
q y l (s fer u es
re or du t or So an R
F o Re R ut es
em
um M M M ra al pt ns -o ag
er pa rn rru Pi a ge n k
xim RO a e e lt ow c
a at m om Int Int Pa
M EP D Ti C I/O Vo Br
PIC16C620 20 512 80 TMR0 2 Yes 4 13 3.0-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
PIC16C621 20 1K 80 TMR0 2 Yes 4 13 3.0-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
PIC16C622 20 2K 128 TMR0 2 Yes 4 13 3.0-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC16C62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30236B-page 189
Enhanced PIC16C5X
TABLE D-4:
H z) y s)
(M or e(
e m ul T) g
t i on M ) od AR in
a s
DS30236B-page 190
r m d M S m
p e a r M , U m
O ) W 2C
) a
of
gr o ts gr
y ro (W t es e /P I /I r t V ol ro
nc
P y ) r P o e s ( l P et
(b (s pa S P rc
q ue r y le m s )( v e u n ge eria es
e o u o la a R
Fr od /C rt( So R tS ut es
M em M re Po e lS e ui -o
um O M r t u a l l l r u pt ins
a g i r c n k ag
i m R M t a e p r i r a r P l t C o w c
ax m te -
M EP RO Da Ti Ca Se Pa In I/O Vo In Br Pa
PIC16C62 20 2K — 128 TMR0, 1 SPI/I2C — 7 22 3.0-6.0 Yes — 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C62A(1) 20 2K — 128 TMR0, 1 SPI/I2C — 7 22 3.0-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16CR62(1) 20 — 2K 128 TMR0, 1 SPI/I2C — 7 22 3.0-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
Enhanced PIC16C5X
PIC16C63(1) 20 4K — 192 TMR0, 2 SPI/I2C, — 10 22 3.0-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16CR63(1) 20 — 4K 192 TMR0, 2 SPI/I2C, — 10 22 3.0-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C64 20 2K — 128 TMR0, 1 SPI/I2C Yes 8 33 3.0-6.0 Yes — 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP
PIC16C64A(1) 20 2K — 128 TMR0, 1 SPI/I2C Yes 8 33 3.0-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP, TQFP
PIC16CR64(1) 20 — 2K 128 TMR0, 1 SPI/I2C Yes 8 33 3.0-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP
PIC16C65 20 4K — 192 TMR0, 2 SPI/I2C, Yes 11 33 3.0-6.0 Yes — 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP
PIC16C65A(1) 20 4K — 192 TMR0, 2 SPI/I2C, Yes 11 33 3.0-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP, TQFP
PIC16CR65(1) 20 — 4K 192 TMR0, 2 SPI/I2C, Yes 11 33 3.0-6.0 Yes Yes 40-pin DIP;
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability.
All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7.

TABLE D-5:

) s )
Hz ord s) )
(M e( ls
n (W ul RT ne g
io y od A n in
r at or M m
pe em M US ha m
O M 2 C, C ) ra
it) lts

of m e s) / PW I /I t b o og
cy a yt or 8- r
o gr (b s) re SP P es (V lP et
en Pr e( pa )( r( rc ge
qu y l m s ve r te u e ria es
e or du rt( a So an t R s
Fr o /Co o Sl ve t R tS
M em re el on up ns ui ou ge
um O M rM u lP l C rr ge rc n- ka
xim R t a e t ria r al D e Pi tl a i w c
a EP im ap Se I nt -C o Pa
M Da T C Pa A/ I/O Vo In Br
PIC16C70(1) 20 512 36 TMR0 — — — 4 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC;
20-pin SSOP
PIC16C71 20 1K 36 TMR0 — — — 4 4 13 3.0-6.0 Yes — 18-pin DIP, SOIC
PIC16C71A(1) 20 1K 68 TMR0 — — — 4 4 13 3.0-6.0 Yes Yes 18-pin DIP, SOIC;
20-pin SSOP
PIC16C72(1) 20 2K 128 TMR0, 1 SPI/I2C — 5 8 22 3.0-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C73 20 4K 192 TMR0, 2 SPI/I2C, — 5 11 22 3.0-6.0 Yes — 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C73A(1) 20 4K 192 TMR0, 2 SPI/I2C, — 5 11 22 3.0-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C74 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 3.0-6.0 Yes — 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP
PIC16C74A(1) 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 3.0-6.0 Yes Yes 40-pin DIP;
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability.
All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30236B-page 191
Enhanced PIC16C5X
TABLE D-6:
DS30236B-page 192
)
Hz y
(M or
n em
io M
r at
pe r am s) )
O ) lts
of og tes y te o
cy Pr by (b s) s (V
en ( M ( ce
r ge
qu y O u le
e or Sou an s
Fr M em PR od R
um O M EE M pt ins ge a ge
R ru
Enhanced PIC16C5X
xim M a a er er P lta ck
EP at at m t
a E RO D D Ti In I/O Vo Pa
M
PIC16C83(1) 10 512 — 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16CR83(1) 10 — 512 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16C84 10 1K — 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16C84A(1) 10 1K — 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16CR84(1) 10 — 1K 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect,
and high I/O current capability.
All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7.

TABLE D-7:
)
ds

Hz
or
(M
(W
n
y
tio
or
s)
ra
te
em
pe
y
M
)
T)
O
(b
ns
R
lts
of
y
am
s
tio
r
o
y
ly
c
or
SA
pt
og
es
(V
nc
s)
tip
e
tru
(U
ru
rc
Pr
e
em
ul
e(
u
qu
er
ns
M
s)
e
ng
t(
nt
fI
du
So
Fr
s
o
re
lI
or
Ra
at
M
pt
a
a
M
ge
um
ns
er
lP
s
a
ru
rn
ge
M
b
RO
dw
im
er
Pi
ia
M
M s
r
er
ta
ck
r
m
p
l
m
xt
ax
RO
EP
a
In
Ha
E
RA
M
I/O
Pa
Se
Ti
Nu
C
PW tur
Vo
PIC17C42 25 2K — 232 TMR0,TMR1, 2 2 Yes — Yes 11 33 4.5-5.5 55 40-pin DIP;

PIC17CXX FAMILY OF DEVICES
TMR2,TMR3 44-pin PLCC, MQFP

PIC17C42A 25 2K — 232 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 4.5-5.5 58 40-pin DIP;
PIC17CR42 25 — 2K 232 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 4.5-5.5 58 40-pin DIP;
PIC17C43 25 4K — 454 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;
TMR2,TMR3 44-pin PLCC, TQFP, MQFP
PIC17CR43 25 — 4K 454 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;
PIC17C44 25 8K 454 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
DS30236B-page 193
Enhanced PIC16C5X
Enhanced PIC16C5X
D.1 Pin Compatibility
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE D-8: PIN COMPATIBLE DEVICES
Pin Compatible Devices Package
PIC16C54, PIC16C54A, 18 pin

PIC16CR54, PIC16CR54A, PIC16CR54B, (20 pin)
PIC16C56, PIC16CR56,
PIC16C58A, PIC16CR58A, PIC16CR58B,
PIC16C61,
PIC16C620, PIC16C621, PIC16C622,
PIC16C70, PIC16C71, PIC16C71A
PIC16C83, PIC16CR83,
PIC16C84, PIC16C84A, PIC16CR84
PIC16C55, PIC16CR55, 28 pin

PIC16C57, PIC16CR57A, PIC16CR57B
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63, 28 pin

PIC16C72, PIC16C73, PIC16C73A
PIC16C64, PIC16CR64, PIC16C64A, 40 pin

PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
PIC17C42, PIC17C43, PIC17C44 40 pin

Enhanced PIC16C5X
INDEX PIC16C8X ................................................................ 192
PIC17CXX ............................................................... 193
A Features ...............................................................................1
Absolute Maximum Ratings ..... 59, 71, 85, 99, 111, 125, 137 FSR ............................................................................. 21, 33
ALU ...................................................................................... 7 Fuzzy Logic Dev. System (fuzzyTECH-MP) ............. 53, 57
Applications .......................................................................... 3
Architectural Overview ......................................................... 7
I
Assembler .......................................................................... 56 I/O Interfacing .................................................................... 23
I/O Ports ............................................................................ 23
B I/O Programming Considerations ...................................... 24
Block Diagram ID Locations ................................................................. 29, 40
On-Chip Reset Circuit ................................................ 34 INDF ............................................................................ 21, 33
PIC16C5X Series ......................................................... 8 Indirect Data Addressing ................................................... 21
Timer0 ........................................................................ 25 Instruction Cycle ................................................................ 11
TMR0/WDT Prescaler ................................................ 28 Instruction Flow/Pipelining ................................................. 11
Watchdog Timer ......................................................... 38 Instruction Set Summary ................................................... 42
Brown-Out Protection Circuit ............................................. 39 Integrated .......................................................................... 56
C L
C Compiler (MP-C) ...................................................... 53, 57 Loading of PC .............................................................. 19, 20
Carry .................................................................................... 7
Characteristics - DC and AC .................................... 151, 163
M
Clocking Scheme ............................................................... 11 MCLR ................................................................................ 33
Code Protection ........................................................... 29, 40 Memory Map
Configuration Bits ............................................................... 29 PIC16C54A/CR54A/CR54B ...................................... 13
Configuration Word ............................................................ 30 PIC16CR56 ............................................................... 13
PIC16C54A/CR57A/C58A ......................................... 29 PIC16CR57A/CR57B/C58A/CR58A/CR58B ............. 13
PIC16CR54A/CR54B/Cr56/CR57B/CR58A/CR58B .. 30 Memory Organization ........................................................ 13
Data Memory ............................................................. 14
D Program Memory ....................................................... 13
Development Support ........................................................ 53 MPASM Assembler ..................................................... 53, 56
Development Systems ....................................................... 57 MP-C C Compiler .............................................................. 57
Development Tools ............................................................ 53 MPSIM Software Simulator ......................................... 53, 57
Device Drawings
18-Lead Ceramic Dual In-Line (CERDIP) with Window -
O
300 mil ..................................................................... 183 One-Time-Programmable (OTP) Devices ............................5
18-Lead Plastic Dual In-Line (PDIP) - 300 mil ......... 176 OPTION Register .............................................................. 18
18-Lead Plastic Surface Mount (SOIC) - 300 mil ..... 179 OSC selection .................................................................... 29
20-Lead Plastic Surface Mount (SSOP) - 209 mil .... 181 Oscillator Configurations ................................................... 30
28-Lead Ceramic Dual In-Line (CERDIP) Oscillator Types
with Window - 600 mil .............................................. 184 HS .............................................................................. 30
28-Lead Plastic Dual In-Line (PDIP) - 300 mil ......... 177 LP .............................................................................. 30
28-Lead Plastic Dual In-Line (PDIP) - 600 mil ......... 178 RC ............................................................................. 30
28-Lead Plastic Surface Mount (SOIC) - 300 mil ..... 180 XT .............................................................................. 30
28-Lead Plastic Surface Mount (SSOP) - 209 mil .... 182
P
Device Varieties ................................................................... 5
Digit Carry ............................................................................ 7 Package Marking Information .......................... 173, 174, 175
Dynamic Data Exchange (DDE) ........................................ 53 Packaging Information ..................................................... 173
PC ................................................................................ 19, 33
E PICDEM-1 Low-Cost PIC16/17 Demo Board .............. 53, 55
Electrical Characteristics PICDEM-2 Low-Cost PIC16CXX Demo Board ............ 53, 55
PIC16C54A ................................................................ 59 PICMASTER Probes ......................................................... 54
PIC16C58A .............................................................. 125 PICMASTER System Configuration .................................. 53
PIC16CR54A ............................................................. 71 PICMASTER RT In-Circuit Emulator ............................... 53
PIC16CR54B/56/58B ................................................. 85 PICSTART Low-Cost Development System ............. 53, 55
PIC16CR57A ............................................................. 99 Pin Compatible Devices .................................................. 194
PIC16CR57B ........................................................... 111 pin diagrams .................................................................... 1, 2
PIC16CR58A ........................................................... 137 Pinout Description - PIC16C54A,
External Power-On Reset Circuit ....................................... 35 PIC16CR54A, PIC16CR54B, PIC16CR56,
PIC16C58A, PIC16CR58A, PIC16CR58B ...........................9
F Pinout Description - PIC16CR57A, PIC16CR57B ............. 10
Family of Devices POR
PIC14XXX ................................................................ 187 Device Reset Timer (DRT) .................................. 29, 37
PIC16C5X ................................................................ 188 PD ........................................................................ 33, 39
PIC16C62X .............................................................. 189 Power-On Reset (POR) ................................. 29, 33, 35
PIC16C6X ................................................................ 190 TO ........................................................................ 33, 39
PIC16C7X ................................................................ 191 PORTA ........................................................................ 23, 33

Enhanced PIC16C5X
PORTB ......................................................................... 23, 33 LIST OF EXAMPLES
PORTC ......................................................................... 23, 33
Example 3-1: Instruction Pipeline Flow ............................ 11
Power-Down Mode ............................................................. 40
Example 4-1: Indirect Addressing..................................... 20
Prescaler ............................................................................ 28
Example 4-2: How To Clear RAM Using Indirect
PRO MATE Universal Programmer ........................... 53, 55
Addressing ................................................. 20
Product Identification System ........................................... 201
Example 5-1: Read-Modify-Write Instructions on an
Program Counter ................................................................ 19
I/O Port ....................................................... 22
Q Example 6-1: Changing Prescaler (Timer0→WDT).......... 26
Example 6-2: Changing Prescaler (WDT→Timer0).......... 26
Q cycles ............................................................................. 11
Quick-Turnaround-Production (QTP) Devices ..................... 5
LIST OF FIGURES
R Figure 3-1: PIC16C5X Series Block Diagram ................. 8
RC Oscillator ...................................................................... 32 Figure 3-2: Clock/Instruction Cycle ............................... 11
Read Modify Write .............................................................. 24 Figure 4-1: PIC16C54/CR54/C55 Program
Read Only Memory (ROM) Devices ..................................... 5 Memory Map and Stack ............................. 13
Register File Map Figure 4-2: PIC16C56 Program Memory Map
PIC16C54A/CR54A/CR54B/CR56 ............................. 14 and Stack ................................................... 13
PIC16C58A/CR58A/CR58B ....................................... 15 Figure 4-3: PIC16C57 Program Memory Map
PIC16CR57A/CR57B ................................................. 15 and Stack ................................................... 13
Registers Figure 4-4: PIC16C54/CR54/C56 Register File Map .... 14
Special Function ........................................................ 16 Figure 4-5: PIC16C55 Register File Map...................... 14
Reset ............................................................................ 29, 33 Figure 4-6: PIC16C57 Register File Map...................... 14
Reset on Brown-Out ........................................................... 39 Figure 4-7: STATUS Register (Address:03h) ............... 16
Figure 4-8: OPTION Register ....................................... 17
S Figure 4-9: Loading of PC
Serialized Quick-Turnaround-Production Branch Instructions -
(SQTPSM) Devices ............................................................... 5 PIC16C54/CR54/C55 ................................. 18
SLEEP .......................................................................... 29, 40 Figure 4-10: Loading of PC
Software Simulator (MPSIM) .............................................. 57 Branch Instructions -
Special Features of the CPU .............................................. 29 PIC16C56 ................................................... 18
Special Function Registers ................................................ 16 Figure 4-11: Loading of PC
Stack .................................................................................. 20 Branch Instructions -
STATUS ......................................................................... 7, 33 PIC16C57 ................................................... 18
STATUS Register ............................................................... 17 Figure 4-12: Direct/Indirect Addressing .......................... 20
Figure 5-1: Equivalent Circuit
T for a Single I/O Pin ..................................... 21
Timer0 Figure 5-2: Successive I/O Operation........................... 22
Switching Prescaler Assignment ................................ 28 Figure 6-1: Timer0 Block Diagram ................................ 23
Timer0 ........................................................................ 25 Figure 6-2: Electrical Structure of T0CKI Pin ................ 23
Timer0 (TMR0) Module .............................................. 25 Figure 6-3: Timer0 Timing:
TMR0 with External Clock .......................................... 27 Internal Clock/No Prescale ......................... 24
Timing Diagrams Figure 6-4: Timer0 Timing:
and Specifications .................. 66, 79, 93, 105, 119, 132, 145 Internal Clock/Prescale 1:2 ........................ 24
Timing Parameter Symbology Figure 6-5: Timer0 Timing With External Clock ............ 25
and Load Conditions .............. 65, 78, 92, 104, 118, 131, 144 Figure 6-6: Block Diagram of the Timer0/WDT
TRIS Registers ................................................................... 23 Prescaler .................................................... 26
Figure 7-1: Configuration Word for
U PIC16C54/CR54/C55/C56/C57 .................. 27
UV Erasable Devices ........................................................... 5 Figure 7-2: Crystal Operation or Ceramic Resonator
(HS, XT or LP OSC Configuration)............. 28
W Figure 7-3: External Clock Input Operation
W ........................................................................................ 33 (HS, XT or LP OSC Configuration)............. 28
Wake-up from SLEEP ........................................................ 40 Figure 7-4: External Parallel Resonant Crystal
Watchdog Timer (WDT) ............................................... 29, 37 Oscillator Circuit ......................................... 29
Period ......................................................................... 37 Figure 7-5: External Series Resonant Crystal
Programming Considerations .................................... 37 Oscillator Circuit ......................................... 29
Figure 7-6: RC Oscillator Mode .................................... 30
Z
Figure 7-7: Simplified Block Diagram of On-Chip
Zero bit ................................................................................. 7 Reset Circuit ............................................... 31
Figure 7-8: Electrical Structure of MCLR/VPP Pin......... 32
Figure 7-9: External Power-On Reset Circuit
(For Slow VDD Power-Up) .......................... 32
Figure 7-10: Time-Out Sequence on Power-Up
(MCLR Not Tied to VDD)............................. 33
Figure 7-11: Time-Out Sequence on Power-Up
(MCLR Tied to VDD): Fast VDD Rise Time.. 33

Enhanced PIC16C5X
Figure 7-12: Time-Out Sequence on Power-Up (MCLR Figure 13-1: Typical RC Oscillator Frequency
Tied to VDD): Slow VDD Rise Time ............. 33 vs. Temperature ......................................... 91
Figure 7-13: Watchdog Timer Block Diagram ................. 35 Figure 13-2: Typical RC Oscillator Frequency
Figure 7-14: Brown-Out Protection Circuit 1 ................... 36 vs. VDD,
Figure 7-15: Brown-Out Protection Circuit 2 ................... 36 CEXT = 20 PF .............................................. 92
Figure 8-1: General Format for Instructions .................. 39 Figure 13-3: Typical RC Oscillator Frequency
Figure 9-1: PICMASTER System Configuration ........... 51 vs. VDD,
Figure 10-1: Load Conditions - PIC16C54/55/56/57 ....... 64 CEXT = 100 PF ............................................ 92
Figure 10-2: External Clock Timing Figure 13-4: Typical RC Oscillator Frequency
- PIC16C54/55/56/57 .................................. 65 vs. VDD,
Figure 10-3: CLKOUT and I/O Timing - CEXT = 300 PF ............................................ 93
PIC16C54/55/56/57 .................................... 67 Figure 13-5: Typical IPD vs. VDD,
Figure 10-4: Reset, Watchdog Timer, and Watchdog Enabled ..................................... 93
Device Reset Timer Timing - Figure 13-6: Maximum IPD vs. VDD,
PIC16C54/55/56/57 .................................... 68 Watchdog Enabled ..................................... 93
Figure 10-5: Timer0 Clock Timings Figure 13-7: VTH (Input Threshold Voltage) of I/O Pins
- PIC16C54/55/56/57 .................................. 69 vs. VDD ....................................................... 94
Figure 11-1: Typical RC Oscillator Frequency Figure 13-8: VIH, VIL of MCLR, T0CKI and OSC1
vs. Temperature.......................................... 71 (in RC Mode) vs. VDD ................................. 94
Figure 11-2: Typical RC Oscillator Frequency Figure 13-9: VTH (Input Threshold Voltage)
vs. VDD, of OSC1 Input (in XT, HS, and LP modes)
CEXT = 20PF ............................................... 72 vs. VDD ....................................................... 94
Figure 11-3: Typical RC Oscillator Frequency Figure 13-10: Typical IDD vs. Frequency
vs. VDD, (External Clock 25°C)................................. 95
CEXT = 100 PF ............................................ 72 Figure 13-11: Maximum IDD vs. Frequency
Figure 11-4: Typical RC Oscillator Frequency (External Clock –40°C to +85°C)................ 96
vs. VDD, Figure 13-12: WDT Timer Time-out Period vs. VDD ......... 97
CEXT = 300 PF ............................................ 72 Figure 13-13: Transconductance (gm) OF HS Oscillator
Figure 11-5: Typical IPD vs. VDD, vs. VDD ....................................................... 97
Watchdog Disabled..................................... 73 Figure 13-14: Transconductance (gm) of LP Oscillator
Figure 11-6: Maximum IPD vs. VDD, vs. VDD ....................................................... 98
Watchdog Disabled..................................... 73 Figure 13-15: Transconductance (gm) of XT Oscillator
Figure 11-7: Typical IPD vs. VDD, vs. VDD ....................................................... 98
Watchdog Enabled ..................................... 73 Figure 13-16: IOH vs. VOH, VDD = 3 V............................... 98
Figure 11-8: Maximum IPD vs. VDD, Figure 13-17: IOH vs. VOH, VDD = 5 V............................... 98
Watchdog Enabled ..................................... 73 Figure 13-18: IOL vs. VOL, VDD = 3 V................................ 99
Figure 11-9: VTH (Input Threshold Voltage) of I/O Pins Figure 13-19: IOL vs. VOL, VDD = 5 V................................ 99
vs. VDD........................................................ 74
Figure 11-10: VIH, VIL of MCLR, T0CKI and OSC1
(in RC Mode) vs. VDD ................................. 74
Figure 11-11: VTH (Input Threshold Voltage)
of OSC1 Input (in XT, HS, and LP modes)
vs. VDD........................................................ 74
Figure 11-12: Typical IDD vs. Frequency
(External Clock, 25°C) ................................ 75
Figure 11-13: Maximum IDD vs. Frequency
(External Clock, –40°C to +85°C) ............... 75
Figure 11-14: Maximum IDD vs. Frequency
(External Clock –55°C to +125°C) .............. 76
Figure 11-15: WDT Timer Time-out Period vs. VDD.......... 76
Figure 11-16: Transconductance (gm) OF HS Oscillator
vs. VDD........................................................ 76
Figure 11-17: Transconductance (gm) of LP Oscillator
vs. VDD........................................................ 77
Figure 11-18: IOH vs. VOH, VDD = 3 V ............................... 77
Figure 11-19: Transconductance (gm) of XT Oscillator
vs. VDD........................................................ 77
Figure 11-20: IOH vs. VOH, VDD = 5 V ............................... 77
Figure 11-21: IOL vs. VOL, VDD = 3 V ................................ 78
Figure 11-22: IOL vs. VOL, VDD = 5 V ................................ 78
Figure 12-1: Load Conditions.......................................... 85
Figure 12-2: External Clock Timing - PIC16CR54 .......... 86
Figure 12-3: CLKOUT and I/O Timing - PIC16CR54 ...... 88
Figure 12-4: Reset, Watchdog Timer, and Device Reset
Timer Timing - PIC16CR54 ........................ 89
Figure 12-5: Timer0 Clock Timings - PIC16CR54........... 90

Enhanced PIC16C5X
LIST OF TABLES
Table 1-1: PIC16C5X Family of Devices ....................... 4
Table 3-1: PIC16C54/CR54/C56 Pinout Description ..... 9
Table 3-2: PIC16C55/C57 Pinout Description ............. 10
Table 4-1: Special Function Register Summary .......... 15
Table 5-1: Summary of Port Registers......................... 21
Table 6-1: Registers Associated With Timer0.............. 24
Table 7-1: Capacitor Selection
For Ceramic Resonators -
PIC16C54/55/56/57 .................................... 28
For Crystal Oscillator - PIC16C54/55/56/57 28
For Ceramic Resonators - PIC16CR54 ...... 29
For Crystal Oscillator - PIC16CR54 ............ 29
Table 7-5: Reset Conditions for Special Registers ...... 31
Table 7-6: Reset Conditions for All Registers .............. 31
Table 7-7: Summary of Registers Associated with the
Watchdog Timer ......................................... 35
Table 7-8: TO/PD Status After Reset........................... 36
Table 7-9: Events Affecting TO/PD Status Bits............ 36
Table 8-1: OPCODE Field Descriptions....................... 39
Table 8-2: Instruction Set Summary ............................ 40
Table 9-1: PICMASTER Probe Specification............... 52
Table 9-2: Development System Packages................. 55
Table 10-1: Cross Reference of Device Specs for
Oscillator Configurations (RC, XT & 10)
and Frequencies of Operation
(Commercial Devices) ................................ 58
Oscillator Configurations (HS, LP & JW)
and Frequencies of Operation
(Commercial Devices) ................................ 58
Table 10-3: External Clock Timing Requirements -
PIC16C54/55/56/57 .................................... 65
Table 10-4: CLKOUT and I/O Timing Requirements -
PIC16C54/55/56/57 .................................... 67
Table 10-5: Reset, Watchdog Timer, and Device Reset
Timer - PIC16C54/55/56/57........................ 68
Table 10-6: Timer0 Clock Requirements -
PIC16C54/55/56/57 .................................... 69
Table 11-1: RC Oscillator Frequencies.......................... 71
Table 11-2: Input Capacitance for PIC16C54/56 ........... 78
Table 11-3: Input Capacitance for PIC16C55/57 ........... 78
Oscillator Configurations and Frequencies
of Operation (Commercial Devices)............ 80
Table 12-2: External Clock Timing Requirements -
PIC16CR54................................................. 86
Table 12-3: CLKOUT and I/O Timing Requirements -
PIC16CR54................................................. 88
Table 12-4: Reset, Watchdog Timer, and Device Reset
Timer - PIC16CR54 .................................... 89
Table 12-5: Timer0 Clock Requirements - PIC16CR54. 90
Table 13-1: RC Oscillator Frequencies.......................... 91
Table 13-2: Input Capacitance for PIC16CR54 ............. 99
Table D-1: PIC16C5X Family of Devices ................... 117
Table D-2: PIC16C62X Family of Devices ................. 118
Table D-6: PIC17CXX Family of Devices ................... 122
Table D-7: Pin Compatible Devices............................ 123

Enhanced PIC16C5X
CONNECTING TO MICROCHIP BBS Trademarks:
Connect worldwide to the Microchip BBS using the PICMASTER, PICSTART, the Microchip logo and
CompuServe communications network. In most name are registered trademarks of Microchip
cases a local call is your only expense. The Microchip Technology Inc. PIC is a registered trademark of
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membership services, therefore, you do not need
PRO MATE, fuzzyLAB are trademarks of
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Microchip Technology Incorporated.
There is no charge for connecting to the BBS, except
SQTP is a service mark of Microchip
toll charge to CompuServe access number, where
Technology Inc.
applicable. You do not need to be a CompuServe
member to take advantage of this connection (you fuzzyTECH is a registered trademark of Inform
never actually log in to CompuServe). Software Corporation.
The procedure to connect will vary slightly from I 2C is a trademark of Philips Corporation.
country to country. Please check with your local
CompuServe agent for details if you have a problem. IBM, IBM PC-AT are registered trademarks of
CompuServe service allows multiple users at baud International Business Machines Corp.
rates up to 14,400 bps. Pentium is a trademark of Intel Corporation.
The following connect procedure applies in most MS-DOS, Microsoft Windows and Windows are
locations: registered trademarks of Microsoft Corporation.
1. Set your modem to 8-bit, No parity, and One CompuServe is a registered trademark of
stop (8N1). This is not the normal CompuServe CompuServe Incorporated.
setting which is 7E1.
2. Dial your local CompuServe access number. All other trademarks mentioned herein are the
property of their respective companies.
3. Depress <ENTER↵> and a garbage string will
appear because CompuServe is expecting a
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4. Type +, depress <ENTER↵> and Host Name:
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5. Type MCHIPBBS, depress < ENTER↵ > and
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In the United States, to find CompuServe's phone
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Type, NETWORK, depress < ENTER↵ > and follow
CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
number.
ACCESS TO THE INTERNET

Microchip’s current WWW address is listed on the
back page of this data sheet under Worldwide Sales &
Service - Americas - Corporate Office.

Enhanced PIC16C5X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can
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Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Device: Enhanced PIC16C5X Literature Number: DS30236B
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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Enhanced PIC16C5X
ENHANCED PIC16C5X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -XX X /XX XXX
Examples:
Device Frequency Temperature Package Pattern a) PIC16C54A -04/P 301 = Commercial
Range Range temp., PDIP package, 4MHz, normal VDD
limitis, QTP pattern #301.
Device PIC16C5X(2), PIC16C5XT(3)
b) PIC16LC58A - 04I/SO = Industrial temp.,
PIC16LC5X(2), PIC16LC5XT(3)
SOIC package, 4MHz, Extended VDD
PIC16CR5X(2), PIC16CR5XT(3)
limits.
PIC16LCR5X(2), PIC16LCR5XT(3)
c) PIC16CR57A - 10E/P355 = ROM pro-
Frequency 04 = 4 MHz gram memory, Automotive temp., PDIP
Range 10 = 10 MHz package, 10MHz, normal VDD limits.
20 = 20 MHz
b(1) = No type for JW(4) devices
Note 1: b = blank
Temperature b(1) = 0°C to +70°C (Commercial)
2: C = Standard VDD range
Range I = -40°C to +85°C (Industrial)
LC = Extended VDD range
E = -40°C to +125°C (Automotive)
CR = ROM Version, Standard VDD
Package JW = Windowed CERDIP range
P = PDIP LCR = ROM Version, Extended VDD
SO = SOIC (Gull Wing, 300 mil body) range
SP = Skinny PDIP (28 pin, 300 mil body) 3: T = in tape and reel - SOIC, SSOP
SS = SSOP (209 mil body) packages only.
4: UV erasable devices are tested to all
Pattern 3-digit Pattern Code for QTP, ROM (blank otherwise) available voltage/frequency options.
Erased devices are oscillator type
04. The user can select 04, 10 or 20
oscillators by programmng the appro-
priate configuration bits.
Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

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All rights reserved.  1996, Microchip Technology Incorporated, USA.
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reserved. All other trademarks mentioned herein are the property of their respective companies.

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ENHANCED PIC16C5X

EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

• PIC16CR57A MCLR/VPP 4 15 OSC2/CLKOUT

 1996 Microchip Technology Inc. DS30236B-page 1

This document was created with FrameMaker 4 0 4

RA2 •1 20 RA1 VSS •1 28 MCLR/VPP

To Our Valued Customers

DS30236B-page 2  1996 Microchip Technology Inc.

 1996 Microchip Technology Inc. DS30236B-page 3

This document was created with FrameMaker 4 0 4

Clock Memory Peripherals Features

PIC16C54 20 512 — 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR54(2) 20 — 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR54A 20 — 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C55 20 512 — 24 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16CR56(1) 20 — 1K 25 TMR0 12 2.5-5.5 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C57 20 2K — 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16CR57A (2) 20 — 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16CR57B 20 — 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16C58A 20 2K — 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16CR58B(1) 20 — 2K 73 TMR0 12 2.5-5.5 33 18-pin DIP, SOIC; 20-pin SSOP

Legend: Grayed boxes: Devices NOT covered in this data sheet.

DS30236B-page 4  1996 Microchip Technology Inc.

2.2 One-Time-Programmable (OTP)

 1996 Microchip Technology Inc. DS30236B-page 5

This document was created with FrameMaker 4 0 4

DS30236B-page 6  1996 Microchip Technology Inc.

 1996 Microchip Technology Inc. DS30236B-page 7

This document was created with FrameMaker 4 0 4

9-11 T0CKI OSC1 OSC2 MCLR

RA3:RA0 RB7:RB0 RC7:RC0

DS30236B-page 8  1996 Microchip Technology Inc.

DIP, SOIC SSOP I/O/P Input

 1996 Microchip Technology Inc. DS30236B-page 9

DIP, SOIC SSOP I/O/P Input

DS30236B-page 10  1996 Microchip Technology Inc.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55H Fetch 1 Execute 1

 1996 Microchip Technology Inc. DS30236B-page 11

DS30236B-page 12  1996 Microchip Technology Inc.

Program 0FFh On-chip Program

Reset Vector 7FFh

Reset Vector 1FFh

 1996 Microchip Technology Inc. DS30236B-page 13

This document was created with FrameMaker 4 0 4

4.2.1 GENERAL PURPOSE REGISTER FILE

The register file is accessed either directly or indirectly

DS30236B-page 14  1996 Microchip Technology Inc.

1Fh 3Fh 5Fh 7Fh

FIGURE 4-6: PIC16C58A/CR58A/CR58B REGISTER FILE MAP

1Fh 3Fh 5Fh 7Fh

Note 1: Not a physical register. See Section 4.7

 1996 Microchip Technology Inc. DS30236B-page 15

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111

DS30236B-page 16  1996 Microchip Technology Inc.

FIGURE 4-7: STATUS REGISTER (ADDRESS:03h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

 1996 Microchip Technology Inc. DS30236B-page 17