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Vlsi Syllabus

This document provides an overview of the ECE407B VLSI Design course offered at the B. Tech level. The course objectives are to understand IC fabrication steps, MOS and BIOS circuit properties, and VLSI design processes. The course covers MOS transistor theory, fabrication, MOS inverters, CMOS design techniques, MOS circuit design including layout rules, scaling of MOS circuits, circuit characterization, and design of subsystems like adders and multipliers. Students will learn to calculate electrical properties of MOS circuits and design various gates and circuits using stick diagrams and layouts. The course aims to provide ability to analyze and design digital VLSI circuits.

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rekhayadav
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60 views

Vlsi Syllabus

This document provides an overview of the ECE407B VLSI Design course offered at the B. Tech level. The course objectives are to understand IC fabrication steps, MOS and BIOS circuit properties, and VLSI design processes. The course covers MOS transistor theory, fabrication, MOS inverters, CMOS design techniques, MOS circuit design including layout rules, scaling of MOS circuits, circuit characterization, and design of subsystems like adders and multipliers. Students will learn to calculate electrical properties of MOS circuits and design various gates and circuits using stick diagrams and layouts. The course aims to provide ability to analyze and design digital VLSI circuits.

Uploaded by

rekhayadav
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE407B VLSI DESIGN

B. Tech Semester –VII (ECE, AEI, EEE)

L T P Credits Class Work : 25 Marks


3 1 - 4 Theory : 75 Marks
Total : 100 Marks
Duration of Exam. : 3 Hrs.
COURSE OBJECTIVES:
 To understand the steps involved in IC fabrication
 To study basic electrical properties of MOS &BIOS circuits.
 To understand VLSI circuit design processes representations of stick diagram &layout diagram.

UNIT I
INTRODUCTION:
Evolution of VLSI, Moore’s Law, MOS transistor theory – MOS structure, enhancement & depletion transistor, Threshold voltage, MOS device
design equations, Body Effect, Channel length modulation, Mos Transistor Trans conductance and output conductance.
MOS FABRICATION:
Crystal Growth, wafer preparation, epitaxy, oxidation, lithography, etching, diffusion, deposition, ion-implantation, metallization, Fabrication
Process: nMOS, CMOS (n-well, p-well, twin-tub, silicon on insulator, 3-D CMOS, MOS capacitance dynamic behavior, sub-micron MOS
transistors- related effects.
UNIT II
MOS INVERTER:
Introduction, nMOS inverter: resisive load, enhancement load, depletion load, determination of pull-up to pull-down ratio for an nMOS inverter
driven by another nMOS inverter. CMOS inverter: DC characteristics, circuit model, latch up.
CMOS DESIGN:
Gate Logic: inverter, nand gate, nor gate. Ratioed logic, pseudo NMOS logic, DCVSL Logic, Switch Logic: pass transistor and transmission
gate, dynamic logic, charge sharing logic, domino logic. Combination logic: Parity generator, multiplexer. Sequential logic: two phase clocking,
memory-latches and registers, setup and hold time violations, causes ,effects and remedies.

UNIT III
MOS circuit Design :
MOS layer, stick diagram: nMOS Design style, CMOS design style, design rules and layout: lambda based design rule, layer representation,
contact cuts, double metal MOS process rules, CMOS lambda based design rules.
SCALING OF MOS CIRCUITS:
Scaling models and scaling factors for device parameters, limitations of scaling: substrate doping, limits of miniaturization, limit of interconnect
and contact resistance.
UNIT IV

CIRCUIT CHARACTERIZATION AND PERFORMANCE ESTIMATION:


Sheet resistance, resistance estimation, capacitance estimation, inductance, switching characteristic, propagation delays, CMOS gate
transistor sizing, power dissipation: static and dynamics.
SUB-DESIGN PROCESS:
Design of an ALU subsystem: 4-bit shifter, barrel shifters, logarithmic shifters.Adders – ripple carry, Manchester carry, carry bypass, carry
select linear, carry select square root, carry look ahead, tree and domino adder .Multiplier – binary , array, carry save, Wallace
tree,Programmable logic array, random access memory, binary counter.
Text Books :
1. D.A.Pucknell and K. Eshraghian, “Basic VLSI Design”
2. Weste and Eshrighian, “Principle of CMOS VLSI Design” Pearson Education, 2001

Reference Books:
1. S. M. Kang, Y. Lebiebici, “CMOS digital integrated circuits analysis & design” TMH, 3rd Edition.
2. Rabaey, “Introduction of digital integration circuit”.

COURSE OUTCOMES:
 Ability to calculate electrical properties of MOS circuits
 Ability to design various gates, adders, Multipliers, Memories, using stick diagrams, layouts.

NOTE: In the Semester examination, the examiner will set 08 questions in all selecting two from each unit. The candidates will be required to
attempt five questions in all, atleast one from each unit. All questions carry equal marks.

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