Data Sheet: Integrated VIP and Teletext With Background Memory Controller (IVT1.1BMCX)

INTEGRATED CIRCUITS
DATA SHEET
SAA5249
Integrated VIP and Teletext with
Background Memory Controller
(IVT1.1BMCX)
Preliminary specification 1996 Nov 07
Supersedes data of December 1993
File under Integrated Circuits, IC02
Philips Semiconductors Preliminary specification

SAA5249
FEATURES
• Complete teletext decoder featuring a background
memory controller in a single 48-pin DIP package.
Capable of storing of up to 512 teletext pages in an
external DRAM, giving instant access to the teletext
data
• Automatic processing of extension packet 26 for widest
GENERAL DESCRIPTION
possible language decoding. All our standard language
options can be available, and the language option is The Integrated VIP and Teletext (IVT1.1BMCX) is a
readable via I2C-bus. teletext decoder (contained within a single chip package)
• 100% hardware compatible with the SAA5247 plug-in for decoding 625-line based World System Teletext
replacement and with the possibility of extra market in transmissions. With its built-in background memory
those countries with packet 26 transmissions. controller the device can store incoming teletext packets in
Still pin-aligned to SAA5254 and SAA5244A. the external 1M4 DRAM. With this large packet store
which can be rapidly scanned, we can achieve near
• 100% software compatible with the SAA5247, and instantaneous access to all the pages transmitted by the
SAA5244A, except if the special OSD symbols were broadcaster.
used. Also 100% software compatible to SAA5254. In all
events there is a change to the ROM ID number. This version of the decoder also contains some extra
hardware to process extension packet 26 automatically,
• The device is pin-aligned with the other members of the
extending the markets to which the TV chassis can be
new Philips teletext decoder family, i.e. SAA5281 and
shipped and offering many more language options for the
the SAA5254, making one hardware solution for the
set maker.
whole range
• Low software overhead for the microprocessor
• RGB interface to standard colour decoder ICs, push-pull
output drive.
QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VDD supply voltage 4.5 5.0 5.5 V
IDD supply current − 90 120 mA
Vsyn sync amplitude 0.1 0.3 0.6 V
Vvid video amplitude 0.7 1.0 1.4 V
fXTAL crystal frequency − 27 − MHz
Tamb operating ambient temperature −20 − +70 °C
ORDERING INFORMATION
TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
SAA5249P/E DIP48 plastic dual in-line package; 48 leads (600 mil) SOT240-1
SAA5249GP/E QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); SOT319-1
body 14 × 20 × 2.7 mm; high stand-off height
1996 Nov 07 2

SAA5249
BLOCK DIAGRAM
A0 to A9 D0 to D3 R/W CAS0 CAS1 RAS Y BLANK COR RGBREF R/G/B ODD/EVEN

handbook, full pagewidth
10 4 3
42 23 24 41 29 21 27 20 17 to 19 28
46
SEL1
45 DRAM INTERFACE DISPLAY
SEL2
HAMMING
3
VDD1 CHECKER
BACKGROUND AND
MEMORY PACKET 26
SAA5249 CONTROL PROCESSING
VDD2 12
ENGINE
VSSn 16, 22
38
MUX TELETEXT PAGE

ACQUISITION MEMORY
DATA SLICER AND
AND DECODING
CLOCK
REGENERATOR
31
SDA
DCVBS I 2C - BUS
INTERFACE
VSS1 7 30
ANALOG SCL
TO TIMING
8 DIGITAL CHAIN
REF+ CONVERTER
DISPLAY
CLOCK
4 INPUT CLAMP PHASE
OSCOUT LOCKED
CRYSTAL AND
SYNC LOOP
5 OSCILLATOR
OSCIN SEPARATOR
6 9 11 10 13 15 14 MLB304
GNDO BLACK IREF CVBS POL VCR/FFB STTV/LFB
Fig.1 Block diagram for SOT240-1 (DIP48) package.
1996 Nov 07 3

SAA5249
PINNING
PIN
SYMBOL DESCRIPTION
SOT240-1 SOT319-1(1)
n.c. 1 1 not connected
n.c. 2 2 not connected
VDD1 3 25 +5 V supply
OSCOUT 4 27 27 MHz crystal oscillator output
OSCIN 5 28 27 MHz crystal oscillator input
GNDO 6 29 0 V crystal oscillator ground
VSS1 7 12 0 V ground
REF+ 8 32 positive reference voltage; this pin should be connected to ground via a
100 nF capacitor
BLACK 9 35 video black level storage pin; this pin should be connected to ground via a
100 nF capacitor
CVBS 10 36 composite video input pin; a positive-going 1 V (p-p) input is required,
connected via a 100 nF capacitor
IREF 11 37 reference current input pin; connected to ground via a 27 kΩ resistor
VDD2 12 38 +5 V supply
POL 13 39 STTV/LFB/FFB polarity selection pin
STTV/LFB 14 40 sync to TV output pin/line flyback input pin; function controlled by an
internal register bit (scan sync mode)
VCR/FFB 15 42 PLL time constant switch/field input pin; function controlled by an internal
register bit (scan sync mode)
REF− − 31 negative reference voltage; this pin should be connected to REF+ via a
100 nF capacitor
R 17 49 dot rate character output of the RED colour information
G 18 50 dot rate character output of the GREEN colour information
B 19 51 dot rate character output of the BLUE colour information
RGBREF 20 52 input DC voltage to define the output high level on the RGB pins
BLANK 21 53 dot rate fast blanking output
VSS3 22 54, 55 0 V ground; internally connected for SOT319
CAS0 23 56 column address select to external DRAM for BMCX function
CAS1 24 57 column address select to external DRAM for BMCX function for second
DRAM where two 256 k × 4 devices are used
A4 25 58 address output to external DRAM for BMCX function
COR 27 60 programmable output to provide contrast reduction of the TV picture for
mixed text and picture displays or when viewing newsflash/subtitle pages;
open drain output
ODD/EVEN 28 61 25 Hz output synchronized with the CVBS input field sync pulses to
produce a non-interlaced display by adjustment of the vertical deflection
currents
1996 Nov 07 4

SAA5249
PIN
SYMBOL DESCRIPTION
SOT240-1 SOT319-1(1)
Y 29 62 dot rate character output of teletext foreground colour information; open
drain output
SCL 30 63 serial clock input for I2C-bus; it can still be driven HIGH during power-down
of the device
SDA 31 64 serial data port for the I2C-bus; open drain output. It can still be driven
HIGH during power-down of the device
RAS 41 15 row address select to external DRAM
R/W 42 18 read/write for external DRAM
D2 43 19 data input/output for external DRAM
SEL2 45 21 RAM select input to choose external DRAM size
SEL1 46 22 RAM select input to choose external DRAM size
Note
1. The remaining pins for SOT319 are not connected.
1996 Nov 07 5

SAA5249
n.c. 1 48 D1
n.c. 2 47 D3
VDD1 3 46 SEL1
OSCOUT 4 45 SEL2
OSCIN 5 44 D0
GNDO 6 43 D2
VSS1 7 42 R/W
REF 8 41 RAS
BLACK 9 40 A9
CVBS 10 39 A8
IREF 11 38 VSS4
VDD2 12 37 A0
SAA5249P
POL 13 36 A7
STTV/LFB 14 35 A1
VCR/FFB 15 34 A6
VSS2 16 33 A2
R 17 32 A5
G 18 31 SDA
B 19 30 SCL
RGBREF 20 29 Y
BLANK 21 28 ODD/EVEN
VSS3 22 27 COR
CAS0 23 26 A3
CAS1 24 25 A4
MLB305
Fig.2 Pin configuration; SOT240-1 (DIP48).
1996 Nov 07 6

SAA5249
61 ODD/EVEN
52 RGBREF
55 V SS3
54 V SS3
53 BLAN
57 CAS1
56 CAS0
60 COR
64 SDA
63 SCL
59 A3
58 A4
index
62 Y
corner
n.c. 1 51 B
n.c. 2 50 G
n.c. 3 49 R
A5 4 48
A2 5 47
A6 6 46 n.c.
n.c. 7 45
A1 8 44
A7 9 43 VSS4
n.c. 10 SAA5249GP 42 VCR/FFB
A0 11 41 n.c.
VSS1 12 40 STTV/LFB
A8 13 39 POL
A9 14 38 VDD2
RAS 15 37 IREF
n.c. 16 36 CVBS
n.c. 17 35 BLACK
R/W 18 34 n.c.
D2 19 33 n.c.
D0 20
SEL2 21
SEL1 22
D3 23
D1 24
VDD1 25
n.c. 26
OSCOUT 27
OSCIN 28
GNDO 29
V SS2 30
31
32
MLB306
REF
REF
Fig.3 Pin configuration; SOT319-1 (QFP64).
1996 Nov 07 7

SAA5249
LIMITING VALUES
In accordance with Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER MIN. MAX. UNIT
VDD supply voltage (all supplies) −0.3 +6.5 V
VI input voltage (any input) −0.3 VDD + 0.5 V
VO output voltage (any output) −0.3 VDD + 0.5 V
IO output current (each output) − ±10 mA
IIOK DC input or output diode current − ±20 mA
Tamb operating ambient temperature −20 +70 °C
QUALITY AND RELIABILITY

This device will meet Philips Semiconductors General Quality Specification for Business group “Consumer Integrated
Circuits SNW-FQ-611-Part E”. The principal requirements are shown in Tables 1 to 4.
1996 Nov 07 8

SAA5249
Group A
Table 1 Acceptance tests per lot
TEST REQUIREMENTS(1)
Mechanical cumulative target: <100 ppm
Electrical cumulative target: <100 ppm
Group B
Table 2 Processability tests (by package family)
TEST REQUIREMENTS(1)
Solderability <7% LTPD
Mechanical <15% LTPD
Solder heat resistance <15% LTPD
Group C
Table 3 Reliability tests (by process family)
TEST CONDITIONS REQUIREMENTS(1)

Operational life 168 hours at Tj = 150 °C <1500 FPM; equivalent to <100 FITS
at Tj = 70 °C
Humidity life temperature, humidity, bias <2000 FPM
(1000 hours, 85 °C, 85% RH or
equivalent test)
Temperature cycling performance Tstg(min) to Tstg(max) <2000 FPM
Table 4 Reliability tests (by device type)
TEST CONDITIONS REQUIREMENTS(1)

ESD and latch-up ESD Human body model <15% LTPD
2000 V, 100 pF, 1.5 kΩ
ESD Machine model <15% LTPD
200 V, 100 pF, 1.5 kΩ
latch-up 100 mA, 1.5 × VDD <15% LTPD
(absolute maximum)
Note to Tables 1 to 4
1. ppm = fraction of defective devices, in parts per million.
LTPD = Lot Tolerance Percent Defective.
FPM = fraction of devices failing at test condition, in Failures Per Million.
FITS = Failures In Time Standard.
1996 Nov 07 9

SAA5249
CHARACTERISTICS
VDD = 5 V ± 10%; Tamb = −20 to +70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies
VDD supply voltage 4.5 5.0 5.5 V
IDD(tot) total supply current − 90 120 mA
Inputs
CVBS
Vsync sync amplitude 0.1 0.3 0.6 V
td(sync) delay from CVBS to TCS output −150 0 +150 ns
from STTV buffer (nominal video,
average of leading/trailing edge)
∆td(sync) change in sync delay between all 0 − 25 ns
black and all white video input at
nominal levels
Vvid(p-p) video input amplitude 0.7 1.0 1.4 V
(peak-to-peak value)
display PLL catching range ±7 − − %
Zsource source impedance − − 250 Ω
Ci input capacitance − − 10 pF
IREF
Rgnd resistor to ground − 27 − kΩ
POL
VIL LOW level input voltage −0.3 − +0.8 V
VIH HIGH level input voltage 2.0 − VDD + 0.5 V
ILI input leakage current Vi = 0 to VDD −10 − +10 µA
LFB
Ii input current note 1 −1 − +1 mA
td(LFB) delay between LFB front edge − 250 − ns
and input video line sync
VCR/FFB
Ii input current note 1 −1 − +1 mA
1996 Nov 07 10

SAA5249

RGBREF note 2
VIL LOW level input voltage −0.3 − VDD + 0.5 V
IDC DC current − − 10 mA
SEL1 AND SEL2
SCL
fSCL clock frequency 0 − 100 kHz
tr input rise time 10% to 90% − − 2 µs
tf input fall time 90% to 10% − − 2 µs
Inputs/outputs
CRYSTAL OSCILLATOR (OSCIN; OSCOUT)
fXTAL crystal frequency − 27 − MHz
Gv small signal voltage gain 3.5 − −
Gm mutual conductance fi = 100 kHz 1.5 − − mA/V
CFB feedback capacitance − − 5 pF
BLACK
Cblk storage capacitor to ground − 100 − nF
SDA
tr input rise time 10% to 90% − − 2 µs
tf input fall time 90% to 10% − − 2 µs
VOL LOW level output voltage IOL = 3 mA 0 − 0.5 V
tf output fall time 3 V to 1 V − − 200 ns
CL load capacitance − − 400 pF
1996 Nov 07 11

SAA5249

D0 TO D3
ILI input leakage current −10 − +10 µA
VOL LOW level output voltage IOL = +1.6 mA 0 − 0.4 V
VOH HIGH level output voltage IOH = −0.2 mA 2.4 − VDD V
tr output rise time 0.6 to 2.2 V − − 20 ns
tf output fall time 2.2 to 0.6 V − − 20 ns
Outputs
STTV
Gstt gain of STTV relative to video 0.9 1.0 1.1
input
VTCS TCS amplitude 0.2 0.3 0.45 V
VDCs DC shift between TCS output and − − 0.15 V
nominal video output
IO output drive current − − 3.0 mA
A0 TO A9 ADDRESS OUTPUT TO MEMORY A0 TO A9
R/W, CASO AND CAS1
1996 Nov 07 12

SAA5249

R, G AND B
VOL LOW level output voltage IOL = 2 mA 0 − 0.2 V
VOH HIGH level output voltage IOH = −1.6 mA; RGBREF RGBREF RGBREF V
RGBREF ≤ VDD − 2 V −0.25 +0.25
|Zo| output impedance − − 200 Ω
IDC DC current − − −3.3 mA
tr output rise time 10% to 90% − − 20 ns
tf output fall time 90% to 10% − − 20 ns
BLANK
VOL LOW level output voltage IOL = 1.6 mA 0 − 0.4 V
VOH HIGH level output voltage IOH = −0.2 mA; 1.1 − − V
VDD = 4.5 V
VOH HIGH level output voltage IOH = 0 mA; − − 2.8 V
VDD = 5.5 V
VOH allowed voltage at pin with external pull-up − − VDD V
tr output rise time 10% to 90% − − 20 ns
tf output fall time 90% to 10% − − 20 ns
ODD/EVEN
COR AND Y (OPEN-DRAIN)
VOH pull-up voltage at pin − − VDD V
VOL output voltage LOW IOL = 5 mA 0 − 1.0 V
tf output fall time load resistor of 1.2 kΩ − − 50 ns
to VDD; measured
between VDD − 0.5 V
and 1.5 V
ILO output leakage current Vi = 0 to VDD −10 − +10 µA
tskew skew delay between display − − 20 ns
outputs R, G, B, COR, Y and
BLANK
1996 Nov 07 13

SAA5249

Timing
DRAM INTERFACE
tRC read or write cycle time 344 380 415 ns
tRP RAS precharge time 125 140 155 ns
tRAS RAS pulse width 194 210 230 ns
tCAS CAS pulse width 113 133 153 ns
tASR row address set-up time 30 60 80 ns
tRAH row address hold time 50 60 92 ns
tASC column address set-up time 50 60 75 ns
tCAH column address hold time 50 60 70 ns
tRCD RAS to CAS delay time 130 148 160 ns
tRAD RAS to column address delay 60 74 105 ns
time
tRSH RAS hold time 15 60 70 ns
tCSH CAS hold time 260 286 300 ns
tCRP CAS to RAS precharge time 60 70 80 ns
tDZO CAS set-up time from data input 200 225 280 ns
tr, tf rise and fall times 10 15 20 ns
tWCS write set-up time 193 212 235 ns
tWCH write command hold time 116 137 150 ns
tDS data input set-up time 193 212 235 ns
tDH data input hold time 42 62 80 ns
tRAC access time from RAS 165 183 220 ns
tCAC access time from CAS 0 35 40 ns
tAA access time from address 95 108 120 ns
tRCS read command set-up time 193 212 235 ns
tRCH read command hold time to CAS 0 10 20 ns
tRRH read command hold time to RAS 55 65 100 ns
tRAL column address to RAS lead time 90 133 150 ns
tOFF1 output buffer turn-off time 20 30 40 ns
tCDD CAS to data input delay time 25 35 45 ns
1996 Nov 07 14

SAA5249

I2C-BUS
tLOW clock LOW period 4 − − µs
tHIGH clock HIGH period 4 − − µs
tSU;DAT data set-up time 250 − − ns
tHD;DAT data hold time 170 − − ns
tSU;STO set-up time from clock HIGH to 4 − − µs
STOP
tBUF START set-up time following a 4 − − µs
STOP
tHD;STA START hold time 4 − − µs
tSU;STA START set-up time following 4 − − µs
clock LOW-to-HIGH transition
Notes
1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs.
Series current limiting resistors must be used to limit the input currents to ±1 mA.
2. RGBREF is the positive supply pin for the RGB output pins and it must be able to source the IOH current from the
R, G and B pins. The leakage specification on RGBREF only applies when there is no current load on the RGB pins.
1996 Nov 07 15
1996 Nov 07
0 4.66 64 µs
LSP
(Line Sync Pulse)
Philips Semiconductors
0 2.33 32 34.33 64 µs
EP
(Equalizing Pulse)
0 27.33 32 59.33 64 µs
BP
(Broad Pulse)
621 622 623 624 625

(308) (309) (310) (311) (312) 1 2 3 4 5 6 7
16
TCS interlaced
309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)
TCS interlaced
308 309 310 311 312 1 2 3 4 5 6 7
TCS non-interlaced
handbook, full pagewidth MLA037 - 2
Fig.4 Composite sync waveforms.

SAA5249
Preliminary specification

SAA5249
LSP
(TCS)
0 4.66 64 µs
40 µs
R, G, B, Y
display period
(1)
0 16.67 56.67 µs
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)
R, G, B, Y
(1) display period
0 41 291 312
line numbers
MLA662 - 1
(1) Also BLANK in character and box blanking.
Fig.5 Display output timing (a) line rate (b) field rate.
SDA
t BUF t LOW tf
SCL
t HD;STA t HIGH
tr
t HD;DAT
t SU;DAT
SDA
MBC764
t SU;STA
t SU;STO
Fig.6 I2C-bus timing.
1996 Nov 07 17

SAA5249
t RC
t RAS
RAS
t RSH t RP
tf t RCD t CAS t CRP
t CSH
CAS
t ASR t RAD t RAL

t RAH t ASC
ADDRESS ROW COLUMN
t CAH
t RCS t RCH
WE
t CAC t RRH
t AA
t OFF1
high impedance
DATA OUTPUT DATA VALID
t RAC
t DZO t CDD
high impedance
DATA INPUT
MBA732
Fig.7 DRAM interface timing; read cycle.
1996 Nov 07 18

SAA5249
t RC
t RAS
RAS
t RSH t RP
tf t RCD t CAS t CRP
t CSH
CAS
t ASR
t RAH tASC
ADDRESS ROW COLUMN
t CAH
t WCS t WCH
WE
t DS
t DH
DATA INPUT DATA VALID
high impedance
DATA OUTPUT
MBA731
Fig.8 DRAM interface timing; write cycle.
1996 Nov 07 19
FIRST FIELD START (EVEN)
621 622 623 624 625

(308) (309) (310) (311) (312) 1 2 3 4 5 6 7
1996 Nov 07
TCS interlaced
ODD/EVEN output
(normal sync mode) 2 µs
ODD/EVEN output
(normal sync mode 48 µs
when VCS to SCS
mode active)
ODD/EVEN output
(slave sync mode) 31 µs
SECOND FIELD START (ODD)
20
309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7)
TCS interlaced
ODD/EVEN output 2 µs
(normal sync mode)
ODD/EVEN output
(normal sync mode 16 µs
when VCS to SCS
mode active)
ODD/EVEN output 31 µs
(slave sync mode)
MBA073 - 4
Fig.9 ODD/EVEN timing.

SAA5249
1996 Nov 07
+5 V
GND R G B BLANKING ODD/EVEN
X3
IC1
1 2 3 4 5
KEY
6 SAA5249 C1 C2
X1 100 nF 33 µF
12
V DD2
1 +5 V 3
27 V DD1 IC2
COR
R1 28 47 4
ODD/EVEN D3 D3
KEY 10 kΩ 21 43 3 15
BLANK D2 D2 V CC
19 48
APPLICATION INFORMATION
B D1 7 D1
2 18 44 C13
VCR G D0 6 D0
5 100 nF
17 39 20
R A8 A8 V SS
29 36 19
Y A7 A7 1
+5 V 15 34 18
3 C3 VCR A6 A6 OE
CVBS 10 32 17
100 CVBS A5 A5
14 25 15
nF LK1 R2 STTV A4 A4
9 26 14
LINK 1 kΩ C8 100 nF BLACK A3 A3
20 33 13
RGBREF A2 A2
4 16 35 12
STTV VSS2 A1 A1
13 37 11
POL A0 A0 C11
4 40 10
OSCOUT A9 A9 100 nF
5 42 8
LK2 OSCIN R/W WE
C4 C9 8 41 9 C12
LINK C5 8.2 pF REF + RAS RAS
100 nF L1 100 nF 7 23 2 10 µF
X2 C7 1 nF 3.3 µH V SS1 CAS0 CAS
6 24
NOTE : GNDO CAS1
11 IC3
FOR +VE GOING IREF
1 R3 C7 R11 30 46 4
SYNC FIT LK1 G1 R9 SCL SEL1 D3
1 kΩ 15 pF 3.3 kΩ 31 45 3 15
21
FOR - VE 27 MHz 27 kΩ SDA SEL2 D2 V CC
22, 38 7 C14
GOING VSS3 , VSS4 D1
KEY 6 100
SYNC FIT LK2 D0 5 nF
10
2 A8 V SS
20
C10 100 nF A7 1
19
A6 OE
18
+5 V A5
17
+5 V A4
3 +5 V 16
A3
14
R5 R6 A2
4.7 kΩ 13 C13 and C14
4.7 kΩ R9 R10 A1
R7 220 Ω 4.7 kΩ 4.7 kΩ 12 are optional
A0
4 surface mounted
8 capacitors mounted
WE close to IC
LK3 LK4 9
RAS
R8 220 Ω LINK LINK 2
CAS
5 GND
n.c.
X4 LINK DRAM (120 nS)
KEY
1 2 3 3 4 IC2 IC3
SCL SDA IC2 and IC3 pin-outs are for
- - Dual In-Line Package (DIP)
D
256K x 4 -
256K x 4 256K x 4
MLB307 1M x 4 -
Fig.10 Application diagram; 1 or 4 Mbit DRAM.

SAA5249

SAA5249
IVT1.1BMCX page memory organization

The organization of the page memory is illustrated by Fig.11. The IVT1.1BMCX provides an additional row as compared
with first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the
teletext page; Row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt
information.
fixed character
written by IVT hardware
alphanumerics white for normal 8 characters
7 characters alphanumerics green when looking always rolling
for status for display page (time)
ROW
7 1 24 8 0
1
24 characters from page header 2
rolling when display page looked for 3
4
MAIN PAGE DISPLAY AREA

5
to
20
21
PACKET X / 22 22
PACKET X / 23 23
PACKET X / 24 STORED HERE IF R0D7 = 1 24
10 14 25
10 bytes for 14 bytes
received free for use
page information by microcontroller MBA274
Fig.11 Basic page memory organization.
REMARK TO Fig.11
Row 0
Row 0 is for the page header. The first seven columns
ROW (0 to 6) are free for status messages. The eighth is an
PACKET X / 24 if R0D7 = 0 0 alphanumeric white or green control character, written
PACKET X / 27 / 0 1
automatically by IVT1.1BMCX to give a green rolling
header when a page is being looked for. The last eight
PACKETS 8 / 30 / 0 to 15 2
characters are for rolling time.
MBA275 - 2
Row 25
The first 10 bytes of row 25 contain control data relating to
the received page as shown in Table 5. The remaining
Fig.12 Organization of the extension memory. 14-bytes are free for use by the microcomputer.
1996 Nov 07 22

SAA5249
Table 5 Row 25 received control data format

D0 PU0 PT0 MU0 MT0 HU0 HT0 C7 C11 MAG0 0
D1 PU1 PT1 MU1 MT1 HU1 HT1 C8 C12 MAG1 0
D2 PU2 PT2 MU2 MT2 HU2 C5 C9 C13 MAG2 0
D3 PU3 PT3 MU3 C4 HU3 C6 C10 C14 0 0
D4 HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND 0
D5 0 0 0 0 0 0 0 0 0 PBLF
D6 0 0 0 0 0 0 0 0 0 0
D7 0 0 0 0 0 0 0 0 0 0
Column 0 1 2 3 4 5 6 7 8 9
Table 6 Page number and sub-code for Table 5
Page number
MAG magazine
PU page units
PT page tens
PBLF page being looked for
FOUND LOW for page has been found
HAM.ER hamming error in corresponding byte
Page sub-code
MU minutes units
MT minutes tens
HU hours units
HT hours tens
C4 to C14 transmitted control bits
1996 Nov 07 23

SAA5249
Register maps
IVT1.1BMCX mode registers R0 to R11 are shown in Table 7. R0 to R10 are write only; R11 is read/write.
Register map (R3), for page requests, is shown in detail in Table 9.
Table 7 Register map (notes 1 to 5)

REGISTER D7 D6 D5 D4 D3 D2 D1 D0
Adv. control 0 X24 POS FREE AUTO DISABLE DISPLAY DISABLE − R11/R11B
RUN PLL ODD/ HDR SRATUS ODD/ SELECT
EVEN ROLL ROW EVEN
ONLY
Mode 1 VCS TO 7 + P/ ACQ DISABLE DEW/ TCS T1 T0
SCS 8-BIT ON/OFF PKT 26 FULL ON
FIELD
Page 2 − − − − TB START START START
request COLUMN COLUMN COLUMN
address SC2 SC1 SC0
Page 3 − − CLEAR PRD4 PRD3 PRD2 PRD1 PRD0
request B.M.
data
− − − − − − − −
Display 5 BKGND BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN
control OUT
(normal)
Display 6 BKGND BKGND IN COR OUT COR IN TEXT OUT TEXT IN PON OUT PON IN
control OUT
(newsflash
/subtitle)
Display 7 STATUS CURSOR CONCEA TOP/BTM SINGLE BOX ON BOX ON BOX ON 0
mode BTM ON L REVEAL HALF DOUBLE 24 1-23
TOP ON HEIGHT
− − − − − − − −
Cursor row 9 − CLEAR A0 R4 R3 R2 R1 R0
MEM.
Cursor 10 − − C5 C4 C3 C2 C1 C0
column
Cursor data 11 D7 D6 D5 D4 D3 D2 D1 D0
Device 11B 625/525 ROM VER ROM ROM VER ROM VER ROM TEXT VCS
status SYNC R4 VER R3 R2 R1 VER R0 SIGNAL SIGNAL
QUALITY QUALITY
1996 Nov 07 24

SAA5249
Notes
1. The dash (−) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. All bits in registers R0 to R10 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
which are set to logic 1.
3. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
(00000111) as the acquisition circuit is enabled but the page is on hold.
4. TB must be set to logic 0 for normal operation.
5. The I2C-bus slave address is 0010001.
Table 8 Register description
R0 ADVANCED CONTROL - auto increments to register 1

R11/R11B SELECT selects reading of R11 or R11B
DISABLE ODD/EVEN forces ODD/EVEN output LOW when logic 1
DISPLAY STATUS ROW when SET = 1 and R1D6 = 1 open (8-bit mode) then all the text display is blanked
out apart from the status row, this allows the page memory to be used for
non-textural data, such as in the German TOP system
DISABLE HDR ROLL disables green rolling header and time
AUTO ODD/EVEN when set forces ODD/EVEN LOW if any TV picture displayed, if DISABLE
ODD/EVEN = 0
FREE RUN PLL will force the PLL to free run in all conditions
X24 POS automatic display of FASTEXT prompt row when logic 1
R1 MODE - auto increments to register 2
T0, T1 interlace/non-interlace 312/313 line control (see Table 10)
TCS ON text composite sync or direct sync select (see Table 10 for FFB mode selection)
DEW/FULL FIELD field-flyback or full-channel mode
DISABLE PKT 26 disable automatic processing of packet 26
ACQ ON/OFF acquisition circuits turned off when logic 1
7 + P/8-BIT 7-bits with parity checking or 8-bit mode
VCS TO SCS when logic 1 enables display of messages with 60 Hz input signal
R2 PAGE REQUEST ADDRESS - auto increments to register 3
COL SCO - SC2 point to start column for page request data (see Table 9)
TB must be logic 0 for normal operation
R3 PAGE REQUEST DATA - does not auto increment (see Table 9)
CLEAR B.M. when set to logic 1. Useful when transmission channel changes
R5 NORMAL DISPLAY CONTROL - auto increments to register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto increments to register 7; (note 1)
PON picture on
TEXT text on
COR contrast reduction on
BKGND background colour on
1996 Nov 07 25

SAA5249
R7 DISPLAY MODE - does not auto increment

BOX ON 0 boxing function allowed on Row 0
BOX ON 1-23 boxing function allowed on Rows 1 to 23
BOX ON 24 boxing function allowed on Row 24
DOUBLE HEIGHT to display double height text
BOTTOM HALF to select bottom half of page when DOUBLE HEIGHT = 1
REVEAL ON to reveal concealed text
CURSOR ON to display cursor
STATUS TOP row 25 displayed above or below the main text
R9 CURSOR ROW - auto increments to register 10
R0 to R4 active row for data written to or read from memory via the I2C-bus
A0 selects display memory page (when = 0) or extension packet memory (when = 1)
CLEAR MEM. when set to 1, clears the display memory; this bit is automatically reset
R10 CURSOR COLUMN - auto increments to register 11 or 11B
C0 to C5 active column for data written to or read from memory via the I2C-bus
R11 CURSOR DATA - does not auto increment
D0 to D7 data read from/written to memory via I2C-bus, at location pointed to by R9 and
R10. This location automatically increments each time R11 is accessed
R11B DEVICE STATUS - does not auto increment
VCS SIGNAL QUALITY indicates that the video signal quality is good and PLL is phase locked to input
video when = 1
TEXT SIGNAL QUALITY if a good teletext signal is being received when logic 1
ROM VER R0 to R4 indicated language/ROM variant. For Western European = 11 000
625/525 SYNC if the input video is a 525 line signal when logic 1
Note
1. These functions have IN and OUT referring to inside and outside the boxing function respectively.
1996 Nov 07 26

SAA5249
Table 9 Register map for page requests (R3); notes 1 to 5

START COLUMN PRD4 PRD3 PRD2 PRD1 PRD0
0 DO CARE
magazine HOLD MAG2 MAG1 MAG0
1 DO CARE
page tens PT3 PT2 PT1 PT0
2 DO CARE
page units PU3 PU2 PU1 PU0
3 DO CARE
hours tens X X HT1 HT0
4 DO CARE
hours units HU3 HU2 HU1 HU0
5 DO CARE
minutes tens X MT2 MT1 MT0
6 DO CARE
minutes units MU3 MU2 MU1 MU0
Notes
1. Abbreviations are as for Table 5 except for DO CARE bits.
2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.
3. If HOLD is set LOW, the page is held and not updated.
4. Columns auto-increment on successive I2C-bus transmission bytes.
5. X = don't care.
Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option; notes 1 and 2
TCS ON
T1 T0 RESULT
FFB MODE
X 0 0 interlaced 312.5/312.5 lines
X 0 1 non-interlaced 312/313 lines (note 1)
X 1 0 non-interlaced 312/313 lines (note 1)
SCS (scan composite sync) mode: FFB leading edge in first broad
0 1 1
pulse of field
SCS (scan composite sync) mode: FFB leading edge in second
1 1 1
broad pulse of field
Notes
1. Reverts to interlaced mode if a newsflash or subtitle is being displayed.
2. X = Don't care.
1996 Nov 07 27

SAA5249
CLOCK SYSTEMS
Crystal oscillator
The crystal is a conventional 2-pin design operating at 27 MHz. It is capable of oscillating with both fundamental and third
overtone mode crystals. External components should be used to suppress the fundamental output of the third overtone
as illustrated in Fig.13.
VDD1
3 (25)
SAA5249
OSCOUT 4 (27)
15 pF 8.2 pF 100 nF
CRYSTAL
OSCILLATOR
1 nF 3.3 µH OSCIN 5 (28)
27 MHz
3.3 kΩ 3rd
overtone GNDO
6 (29)
MLB308
Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT319-1.
Table 11 Crystal characteristics (see Fig.13)

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
Crystal (27 MHz, 3rd overtone)
C1 series capacitance − 1.7 − pF
C0 parallel capacitance − 5.2 − pF
CL load capacitance − 20 − pF
Rr resonance resistance − − 50 Ω
R1 series resistance − 20 − Ω
Xa ageing − − ±5 10−6/year
Xj adjustment tolerance − − ±25 10−6
Xd drift − − ±25 10−6
1996 Nov 07 28

SAA5249
CHARACTER SETS
The WST specification allows the selection of national character sets via the page header transmission bits, C12 to C14.
The basic 96 character sets differ only in 13 national option characters as indicated in the Tables 16, 17 and 18 with
reference to their table position in the basic character matrix illustrated in Table 15. The IVT1.1BMCX automatically
decodes transmission bits C12 to C14. Tables 12, 13 and 14 illustrate the character matrixes.
Character bytes are listed as transmitted from b1 to b7.
MLA663
alphanumerics and alphanumerics alphanumerics or alphanumerics

graphics 'space' character blast-through character
character 1011010 alphanumerics 1111111
0000010 character
0001001
contiguous separated separated contiguous

graphics character graphics character graphics character graphics character
0110111 0110111 1111111 1111111
background display
= colour = colour
Fig.14 Character format.
1996 Nov 07 29

SAA5249
Table 12 SAA5249P/E character data input decoding, West European languages; notes 1 to 9
For character version number (11000) see Register 11B.
handbook, full
B pagewidth
b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1
b5 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1
b 4 b 3 b2 b 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
numerics graphics
0 0 0 0 0
black black
alpha -
graphics
0 0 0 1 1 numerics
red
red
alpha - graphics
0 0 1 0 2 numerics green
green
alpha - graphics
0 0 1 1 3 numerics yellow
yellow
alpha -
graphics
0 1 0 0 4 numerics
blue
blue
alpha -
graphics
0 1 0 1 5 numerics
magenta
magenta
alpha -
graphics
0 1 1 0 6 numerics
cyan cyan
(2)
alpha - graphics
0 1 1 1 7 numerics white
white
conceal
1 0 0 0 8 flash display
(2) (2)
contiguous
1 0 0 1 9 steady
graphics
(2)
separated
1 0 1 0 10 end box
graphics
(1)
1 0 1 1 11 start box ESC
(2) (2)
normal black
1 1 0 0 12 back -
height
ground
new
double back -
1 1 0 1 13 height ground
(1)
hold
1 1 1 0 14 SO graphics
(1) (2)
release
1 1 1 1 15 SI graphics
MBA429
1996 Nov 07 30

SAA5249
Table 13 SAA5249P/H character data input decoding, West European languages; notes 1 to 9
handbook, full
B pagewidth
b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1
1
b5 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
b b b b
4 3 2 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
numerics graphics
0 0 0 0 0 black
black
alpha -
numerics graphics
0 0 0 1 1 red
red
alpha - graphics
green
alpha - graphics
yellow
alpha -
numerics graphics
0 1 0 0 4 blue
blue
alpha - graphics
0 1 0 1 5 numerics magenta
magenta
alpha -
graphics
0 1 1 0 6 numerics
cyan cyan
(2)
alpha - graphics
white
conceal
(2) (2)
1 0 0 1 9 steady contiguous
graphics
(2)
separated
1 0 1 0 10 end box graphics
(1)
(2) (2)
normal black
1 1 0 0 12 back -
height
ground
new
double back -
1 1 0 1 13
height ground
(1)
hold
1 1 1 0 14 SO
graphics
(1) (2)
release
MLA961
1996 Nov 07 31

SAA5249
Table 14 SAA5249P/T character data input decoding, West European and Turkish languages; notes 1 to 9
handbook, full
B pagewidth
b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1
b5 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1
b 4 b 3 b2 b 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha -
numerics graphics
0 0 0 0 0
black black
alpha -
graphics
0 0 0 1 1 numerics
red
red
alpha - graphics
green
alpha - graphics
yellow
alpha -
graphics
0 1 0 0 4 numerics
blue
blue
alpha -
graphics
0 1 0 1 5 numerics
magenta
magenta
alpha -
graphics
0 1 1 0 6 numerics
cyan cyan
(2)
alpha - graphics
white
conceal
(2) (2)
contiguous
1 0 0 1 9 steady
graphics
(2)
separated
1 0 1 0 10 end box
graphics
(1)
(2) (2)
normal black
1 1 0 0 12 back -
height
ground
new
double back -
1 1 0 1 13 height ground
(1)
hold
(1) (2)
release
MBA431
1996 Nov 07 32

SAA5249
Table 15 SAA5249P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9
B b8 0 0 0 or 1 0 0 or 1 0 0 0 0 0 1 1 1 1 1 1
I
T b7 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1
S b6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1
b5 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1
b b b b
4 3 2 1
column
r 0 1 2 2a 3 3a 4 5 6 6a 7 7a 8 9 12 13 14 15
o
w alpha - graphics
0 0 0 0 0 numerics black
black
alpha -
graphics
0 0 0 1 1 numerics
red
red
alpha - graphics
green
alpha - graphics
yellow
alpha -
numerics graphics
0 1 0 0 4
blue blue
alpha - graphics
0 1 0 1 5 numerics magenta
magenta
alpha -
handbook, full pagewidth numerics graphics
0 1 1 0 6 cyan
cyan
(2)
alpha - graphics
white
conceal
(2) (2)
1 0 0 1 9 steady contiguous
graphics
(2)
separated
1 0 1 0 10 end box
graphics
1 0 1 1 11 start box TWIST
(2) (2)
black
1 1 0 0 12 normal
back -
height
ground
new
double back -
1 1 0 1 13
height ground
(1)
hold
(1) (2)
release
1 1 1 1 15 SI
graphics
MBA648 - 1
1996 Nov 07 33

SAA5249
Notes to Tables 12, 13, 14 and 15

1. These control characters are reserved for compatibility with other data codes.
2. These control characters are presumed before each row begins.
3. Control characters shown in Columns 0 and 1 are normally displayed as spaces.
4. Characters may be referred to by column and row (for example 2/5 refers to %).
5. Black represents displayed colour. White represents background.
6. The SAA5249 national option characters are illustrated in Tables 16, 17,18 and 19.
7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5
(E, H and T codes only).
8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped
into the basic code table into positions shown in Tables 16, 17, 18 and 19.
9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.
1996 Nov 07 34
Table 16 SAA5249 basic character matrix; note 1
1996 Nov 07
2/0 2/8 3/0 3/8 4/0 4/8 5/0 5/8 6/0 6/8 7/0 7/8
NC NC
2/1 2/9 3/1 3/9 4/1 4/9 5/1 5/9 6/1 6/9 7/1 7/9
2/2 2/10 3/2 3/10 4/2 4/10 5/2 5/10 6/2 6/10 7/2 7/10
2/3 2/11 3/3 3/11 4/3 4/11 5/3 5/11 6/3 6/11 7/3 7/11
NC NC NC
2/4 2/12 3/4 3/12 4/4 4/12 5/4 5/12 6/4 6/12 7/4 7/12
35
NC NC NC
2/5 2/13 3/5 3/13 4/5 4/13 5/5 5/13 6/5 6/13 7/5 7/13
NC NC
2/6 2/14 3/6 3/14 4/6 4/14 5/6 5/14 6/6 7/6 7/14
NC NC
2/7 2/15 3/7 3/15 4/7 4/15 5/7 5/15 6/7 6/15 7/7 7/15
NC
MLA630
full pagewidth
Note
SAA5249
1. Where: NC = national option character position.


SAA5249
Table 17 SAA5249P/E national option character set; note 1
handbook, full pagewidth (1)

PHCB CHARACTER POSITION (COLUMN / ROW)
LANGUAGE
C12 C13 C14 2 / 3 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14
ENGLISH 0 0 0
GERMAN 0 0 1
SWEDISH 0 1 0
ITALIAN 0 1 1
FRENCH 1 0 0
SPANISH 1 0 1
MLB458
Note
1. PHCB are the Page Header Control Bits. Other combinations default to English.
1996 Nov 07 36

SAA5249
Table 18 SAA5249P/H national option character set; note 1

LANGUAGE
C12 C13 C14 2 / 3 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14
POLISH 0 0 0
GERMAN 0 0 1
SWEDISH 0 1 0
SERBO-CROAT 1 0 1
CZECHOSLOVAKIA 1 1 0
RUMANIAN 1 1 1
MLA966
Note
1. PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change
with the PHCB. All other characters in the basic set are shown in Table 15.
1996 Nov 07 37

SAA5249
Table 19 SAA5249P/R national option character set; note 1

LANGUAGE
C12 C13 C14 2 / 3 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14
ESTONIAN 0 1 0
LETTISH /
LITHUANIAN 0 1 1
RUSSIAN 1 0 0
2 3 4 5 6 7
10
11
12
13
14
15
MEA597
Note
1. PHCB are the Page Header Control Bits. Other combinations default to Estonian.
1996 Nov 07 38

SAA5249
PACKAGE OUTLINES
DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1

seating plane
D ME
A2 A
L A1
c
Z e w M
b1
(e 1)
b
48 25 MH
pin 1 index
1 24
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.4 0.53 0.36 62.60 14.22 3.90 15.88 18.46
mm 4.9 0.36 4.06 2.54 15.24 0.254 2.1
1.14 0.38 0.23 61.60 13.56 3.05 15.24 15.24
0.055 0.021 0.014 2.46 0.56 0.15 0.63 0.73
inches 0.19 0.014 0.16 0.10 0.60 0.01 0.083
0.045 0.015 0.009 2.42 0.53 0.12 0.60 0.60
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
92-11-17
SOT240-1
95-01-25
1996 Nov 07 39

SAA5249
QFP64: plastic quad flat package;

64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height SOT319-1
c
y
X
51 33 A
52 32 ZE
e Q
A2
E HE A
A1 (A 3)
θ
wM
pin 1 index Lp
bp L
64 20 detail X
1 19
w M ZD v M A
e bp
D B
HD v M B
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y Z D (1) Z E (1) θ
o
0.36 2.87 0.50 0.25 20.1 14.1 24.2 18.2 1.0 1.43 1.2 1.2 7
mm 3.3 0.25 1 1.95 0.2 0.2 0.1
0.10 2.57 0.35 0.13 19.9 13.9 23.6 17.6 0.6 1.23 0.8 0.8 0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
92-11-17
SOT319-1
95-02-04
1996 Nov 07 40

SAA5249
SOLDERING Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied
Introduction
to the printed-circuit board by screen printing, stencilling or
There is no soldering method that is ideal for all IC pressure-syringe dispensing before package placement.
packages. Wave soldering is often preferred when
Several techniques exist for reflowing; for example,
through-hole and surface mounted components are mixed
thermal conduction by heated belt. Dwell times vary from
on one printed-circuit board. However, wave soldering is
50 to 300 seconds depending on heating method. Typical
not always suitable for surface mounted ICs, or for
reflow temperatures range from 215 to 250 °C.
printed-circuits with high population densities. In these
situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
WAVE SOLDERING
our “IC Package Databook” (order code 9398 652 90011).
Wave soldering is not recommended for QFP packages.
DIP This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
SOLDERING BY DIPPING OR BY WAVE solder penetration in multi-lead devices.
The maximum permissible temperature of the solder is If wave soldering cannot be avoided, the following
260 °C; solder at this temperature must not be in contact conditions must be observed:
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed • A double-wave (a turbulent wave with high upward
5 seconds. pressure followed by a smooth laminar wave)
soldering technique should be used.
The device may be mounted up to the seating plane, but
• The footprint must be at an angle of 45° to the board
the temperature of the plastic body must not exceed the
direction and must incorporate solder thieves
specified maximum storage temperature (Tstg max). If the
downstream and at the side corners.
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the Even with these conditions, do not consider wave
temperature within the permissible limit. soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
REPAIRING SOLDERED JOINTS QFP100 (SOT382-1) or QFP160 (SOT322-1).
Apply a low voltage soldering iron (less than 24 V) to the During placement and before soldering, the package must
lead(s) of the package, below the seating plane or not be fixed with a droplet of adhesive. The adhesive can be
more than 2 mm above it. If the temperature of the applied by screen printing, pin transfer or syringe
soldering iron bit is less than 300 °C it may remain in dispensing. The package can be soldered after the
contact for up to 10 seconds. If the bit temperature is adhesive is cured. Maximum permissible solder
between 300 and 400 °C, contact may be up to 5 seconds. temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
QFP 150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.
REFLOW SOLDERING
A mildly-activated flux will eliminate the need for removal
Reflow soldering techniques are suitable for all QFP of corrosive residues in most applications.
packages.
The choice of heating method may be influenced by larger REPAIRING SOLDERED JOINTS
plastic QFP packages (44 leads, or more). If infrared or Fix the component by first soldering two diagonally-
vapour phase heating is used and the large packages are opposite end leads. Use only a low voltage soldering iron
not absolutely dry (less than 0.1% moisture content by (less than 24 V) applied to the flat part of the lead. Contact
weight), vaporization of the small amount of moisture in time must be limited to 10 seconds at up to 300 °C. When
them can cause cracking of the plastic body. For more using a dedicated tool, all other leads can be soldered in
information, refer to the Drypack chapter in our “Quality one operation within 2 to 5 seconds between
Reference Handbook” (order code 9397 750 00192). 270 and 320 °C.
1996 Nov 07 41

SAA5249
DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 07 42

SAA5249
NOTES
1996 Nov 07 43
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Romania: see Italy
Tel. +1 800 234 7381 Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
China/Hong Kong: 501 Hong Kong Industrial Technology Centre, Tel. +7 095 247 9145, Fax. +7 095 247 9144
72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +852 2319 7888, Fax. +852 2319 7700 Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America Slovakia: see Austria
Czech Republic: see Austria Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
Tel. +45 32 88 2636, Fax. +45 31 57 1949 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +27 11 470 5911, Fax. +27 11 470 5494
Tel. +358 9 615800, Fax. +358 9 61580/xxx South America: Rua do Rocio 220, 5th floor, Suite 51,
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, 04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Tel. +55 11 821 2333, Fax. +55 11 829 1849
Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Spain: Balmes 22, 08007 BARCELONA,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Tel. +34 3 301 6312, Fax. +34 3 301 4107
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Tel. +46 8 632 2000, Fax. +46 8 632 2745
Hungary: see Austria Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
Indonesia: see Singapore TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444
Ireland: Newstead, Clonskeagh, DUBLIN 14, Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
Tel. +353 1 7640 000, Fax. +353 1 7640 200 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +66 2 745 4090, Fax. +66 2 398 0793
Tel. +972 3 645 0444, Fax. +972 3 649 1007 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, Tel. +90 212 279 2770, Fax. +90 212 282 6707
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Tel. +82 2 709 1412, Fax. +82 2 709 1415 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +1 800 234 7381
Tel. +60 3 750 5214, Fax. +60 3 757 4880 Uruguay: see South America
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Vietnam: see Singapore
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996 SCA52

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 537021/50/02/pp44 Date of release: 1996 Nov 07 Document order number: 9397 750 01014

Data Sheet: Integrated VIP and Teletext With Background Memory Controller (IVT1.1BMCX)

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Data Sheet: Integrated VIP and Teletext With Background Memory Controller (IVT1.1BMCX)

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INTEGRATED CIRCUITS

Integrated VIP and Teletext with

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Integrated VIP and Teletext with

A0 to A9 D0 to D3 R/W CAS0 CAS1 RAS Y BLANK COR RGBREF R/G/B ODD/EVEN

MUX TELETEXT PAGE

GNDO BLACK IREF CVBS POL VCR/FFB STTV/LFB

Fig.1 Block diagram for SOT240-1 (DIP48) package.

Integrated VIP and Teletext with

Integrated VIP and Teletext with

Integrated VIP and Teletext with

Fig.2 Pin configuration; SOT240-1 (DIP48).

Integrated VIP and Teletext with

n.c. 10 SAA5249GP 42 VCR/FFB

Fig.3 Pin configuration; SOT319-1 (QFP64).

Integrated VIP and Teletext with

QUALITY AND RELIABILITY

Integrated VIP and Teletext with

TEST CONDITIONS REQUIREMENTS(1)

Table 4 Reliability tests (by device type)

TEST CONDITIONS REQUIREMENTS(1)

Integrated VIP and Teletext with

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Integrated VIP and Teletext with

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Integrated VIP and Teletext with

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Integrated VIP and Teletext with

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Integrated VIP and Teletext with

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Integrated VIP and Teletext with

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

621 622 623 624 625

308 309 310 311 312 1 2 3 4 5 6 7

Fig.4 Composite sync waveforms.

Integrated VIP and Teletext with

lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced)

(1) Also BLANK in character and box blanking.

handbook, full pagewidth

Fig.6 I2C-bus timing.

Integrated VIP and Teletext with

t ASR t RAD t RAL

ADDRESS ROW COLUMN

Fig.7 DRAM interface timing; read cycle.

Integrated VIP and Teletext with

ADDRESS ROW COLUMN

DATA INPUT DATA VALID

Fig.8 DRAM interface timing; write cycle.

621 622 623 624 625

(slave sync mode) 31 µs

SECOND FIELD START (ODD)

Fig.9 ODD/EVEN timing.

Fig.10 Application diagram; 1 or 4 Mbit DRAM.

Integrated VIP and Teletext with

IVT1.1BMCX page memory organization

MAIN PAGE DISPLAY AREA

Fig.11 Basic page memory organization.