Data Sheet: SAA4977H

INTEGRATED CIRCUITS
DATA SHEET
SAA4977H
Besic
Preliminary specification 1998 Jul 23
File under Integrated Circuits, IC02
Philips Semiconductors Preliminary specification
Besic SAA4977H
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 QUICK REFERENCE DATA
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING INFORMATION
6.1 Pinning
6.2 Pin description
7 FUNCTIONAL DESCRIPTION
7.1 Analog-to-digital conversion
7.2 Digital processing at 1fH level
7.4 Digital-to-analog conversion
7.5 Microprocessor
7.6 Memory controller
7.7 Line locked clock generation
7.8 Clock and sync interfacing
7.9 4 : 1 : 1 I/O interfacing
7.10 Test mode operation
7.11 I2C-bus control registers
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 CHARACTERISTICS
11 APPLICATION
12 PACKAGE OUTLINE
13 SOLDERING
13.1 Introduction
13.2 Reflow soldering
13.3 Wave soldering
13.4 Repairing soldered joints
14 DEFINITIONS
15 LIFE SUPPORT APPLICATIONS
16 PURCHASE OF PHILIPS I2C COMPONENTS
1998 Jul 23 2
Besic SAA4977H
1 FEATURES
• Internal prefilter
• Clamp circuit
• Analog AGC
• Line locked PLL
• Synchronous No parity Eight bit Reception and
• Triple YUV 8-bit Analog-to-Digital Converter (ADC) Transmission (SNERT) interface.
• Horizontal compression
• Field rate up-conversion (50 to 100 Hz or 60 to 120 Hz) 2 GENERAL DESCRIPTION
• 4 : 1 : 1 digital I/O interface The SAA4977H is a video processing IC providing analog
• Digital CTI (DCTI) YUV interfacing, video enhancing features, memory
controlling and an embedded 80C51 microprocessor core.
• Digital luminance peaking
It is applicable especially for field rate up-conversion
• Triple 10-bit Digital-to-Analog Converter (DAC) (50 to 100 Hz or 60 to 120 Hz) in cooperation with a
• Memory controller 2.9 Mbit field memory. It is designed for applications
together with:
• Embedded microprocessor
SAA4955/56TJ, TMS4C2972/73 (serial field memories)
• 16 kbyte ROM SAA4990H (PROZONIC)
• 256 byte RAM SAA4991WP (MELZONIC).
• I2C-bus interface
3 QUICK REFERENCE DATA
SYMBOL PARAMETER MIN. TYP. MAX. UNIT

VDDA(1,2,3) analog supply voltage front-end 4.75 5.0 5.25 V
VDDD(1,2,3) digital supply voltage front-end 4.75 5.0 5.25 V
VDDA(4,5) analog supply voltage back-end 3.15 3.3 3.45 V
VDDD(4,5,6) digital supply voltage back-end 3.15 3.3 3.45 V
VDDIO I/O supply voltage back-end 4.75 5.0 5.25 V
IDDA(1,2,3) analog supply current front-end − 85 100 mA
IDDD(1,2,3) digital supply current front-end − 65 80 mA
IDDA(4,5) analog supply current back-end − 25 35 mA
IDDD(4,5,6) digital supply current back-end − 40 55 mA
IDDIO I/O supply current back-end − 1 10 mA
Ptot total power dissipation − − 1.3 W
Tamb operating ambient temperature −20 − +60 °C
4 ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
SAA4977H QFP80 plastic quad flat package; 80 leads (lead length 1.95 mm); SOT318-2
body 14 × 20 × 2.8 mm
1998 Jul 23 3
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1998 Jul 23
Philips Semiconductors
Besic
BLOCK DIAGRAM
UVO7 to UVO4 UVI7 to UVI4
YO7 to YO0 YI7 to YI0

8 4 4 8
45 to 38 37 59 51 to 58
to to
34 62
VARIABLE
26 VARIABLE Y-DELAY Y-PEAKING 79
Y-DELAY
YIN YOUT
HORIZONTAL BLANKING
CLAMP TRIPLE COMPRESSION
TRIPLE
28 ADC REFORMATTER DCTI DAC
DOWN 76
UIN AGC UOUT
UV SAMPLING UP UP
ANALOG 8 BIT CLAMP SAMPLING SAMPLING 10 BIT
CORRECTION 4:4:4 FORMATTER SIDE-
30 PREFILTER 74
VIN TO 4:1:1 4:2:2 PANELS VOUT
4:1:1 TO TO
4:2:2 4:4:4
SAA4977H
4
ROM RAM
CONTROL CONTROL
MICROPROCESSOR
INTERFACE INTERFACE
TEST
ACQUISITION
CONTROL MEMORY CONTROL MEMORY CONTROL I/O SNERT- I2C-
PLL
BLOCK (ACQUISITION) (DISPLAY) PORT BUS BUS
63, 71, 12,

15 49 47 33 22 17 20 32 24 70 64 66 72 68 9 3 to 7 13, 10 1, 2
MGM592
2 2 5 3 2
TMS SWC HA LLD BLND HRD
VA WE RSTW P1.5 SNDA, SDA,
TRST LLA SELCLK RE HDFL RST to SNCL, SCL
IE2 VDFL P1.1 SNRST
Preliminary specification
SAA4977H
Fig.1 Block diagram.
Besic SAA4977H
6 PINNING INFORMATION
6.1 Pinning
69 VDDD4
75 VDDA4
80 VDDA5
77 VSSA5
73 VSSA4
78 VSSA6
67 VDDIO
handbook, full pagewidth
65 VSSIO
76 UOUT
74 VOUT
79 YOUT
66 BLND
71 HDFL
72 VDFL
68 HRD
70 LLD
SDA 1 64 IE2
SCL 2 63 RE
P1.5 3 62 UVI4
P1.4 4 61 UVI5
P1.3 5 60 UVI6
P1.2 6 59 UVI7
P1.1 7 58 YI0
VDDD5 8 57 YI1
RST 9 56 YI2
SNRST 10 55 YI3
VDDD6 11 54 YI4
SNDA 12 53 YI5
SAA4977H
SNCL 13 52 YI6
VSSD4 14 51 YI7
TMS 15 50 VSSD3
VSSD1 16 49 TRST
SELCLK 17 48 VSSD2
VDDD1 18 47 SWC
VDDD2 19 46 VDDD3
VA 20 45 YO7
VSSA1 21 44 YO6
HA 22 43 YO5
VDDA1 23 42 YO4
RSTW 24 41 YO3
VDDA2 25
YIN 26
VSSA2 27
UIN 28
VDDA3 29
VIN 30
VSSA3 31
WE 32
LLA 33
UVO4 34
UVO5 35
UVO6 36
UVO7 37
YO0 38
YO1 39
YO2 40
MGM593
Fig.2 Pin configuration.
1998 Jul 23 5
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6.2 Pin description

Table 1 QFP80 package
SYMBOL PIN DESCRIPTION
SDA 1 I2C-bus serial data (P1.7)
SCL 2 I2C-bus serial clock (P1.6)
P1.5 3 Port 1 data input/output signal 5
VDDD5 8 digital supply voltage 5 (3.3 V)
RST 9 microprocessor reset input
SNRST 10 SNERT restart (port 1.0)
SNDA 12 SNERT data
SNCL 13 SNERT clock
VSSD4 14 digital ground 4
TMS 15 test mode select
SELCLK 17 select acquisition clock input; internal PLL if HIGH, external clock if LOW
VDDD1 18 digital supply voltage 1 (5 V)
VA 20 vertical synchronization input, acquisition part
VSSA1 21 analog ground 1
HA 22 analog/digital horizontal reference input
VDDA1 23 analog supply voltage 1 (5 V)
RSTW 24 reset write signal output, memory 1
YIN 26 Y analog input
UIN 28 U analog input
VIN 30 V analog input
WE 32 write enable signal output, memory 1
LLA 33 acquisition clock input
UVO4 34 V digital output bit 0
UVO5 35 V digital output bit 1
UVO6 36 U digital output bit 0
UVO7 37 U digital output bit 1
YO0 38 Y digital output bit 0
1998 Jul 23 6
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YO7 45 Y digital output bit 7 (MSB)
SWC 47 serial write clock output
TRST 49 test reset, active LOW
YI7 51 Y digital input bit 7 (MSB)
YI6 52 Y digital input bit 6
UVI7 59 U digital input bit 1
UVI6 60 U digital input bit 0
UVI5 61 V digital input bit 1
UVI4 62 V digital input bit 0
RE 63 read enable signal output, memory 1
IE2 64 input enable signal output, memory 2
VSSIO 65 I/O ground
BLND 66 horizontal blanking signal output, display part
VDDIO 67 I/O supply voltage (5 V)
HRD 68 horizontal reference signal output, deflection part
LLD 70 display clock input
HDFL 71 horizontal synchronization signal output, deflection part
VDFL 72 vertical synchronization signal output, deflection part
VOUT 74 V analog output
VDDA4 75 analog supply voltage 4 (3.3 V)
UOUT 76 U analog output
1998 Jul 23 7
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YOUT 79 Y analog output
VDDA5 80 analog supply voltage 5 (3.3 V)
7 FUNCTIONAL DESCRIPTION 7.1.4 TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERSION

7.1 Analog-to-digital conversion Three identical ADCs are used to convert Y, U and V with
16 MHz data rate. A multi-step type ADC is applied here.
7.1.1 CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 16
AND UV TO 0 (2’S COMPLEMENT)
A clamp circuit is applied for each input channel, to map
7.2.1 OVERLOAD DETECTION
the colourless black level in each video line (on the sync
back porch) to level 16 for Y and to the centre level of the The overload detection provides information to make
converters for U and V. During the clamp period, an efficient use of the AGC. The number of overflows per
internally generated clamp pulse is used to switch on the video field in the luminance channel is accumulated by a
clamp action. An operational transconductance amplifier 14-bit counter. The 8 MSBs of this counter can be read out
like construction, which references to voltage reference by the microprocessor respectively via the I2C-bus.
points in the ladders of the ADCs, will provide a current on Overflow levels can be programmed as 216, 224,
the input of the YUV signals, in order to bring the signals 232 and 240.
to the correct DC value. This current is proportional to the
DC error, but is limited to ±100 µA. When the clamping 7.2.2 DIGITAL CLAMP CORRECTION FOR UV
action is off, the residual clamp current should be very low
During 32 samples within the clamp position the clamp
in order not to drift away within a video line.
error is measured and accumulated to make a low-pass
filtered value of the clamp error. Then a vertical recursive
7.1.2 GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL
filter is used to further low-pass this error value. This value
A variable amplifier is used to map the possible YUV input can be read by the microprocessor or directly be used to
range to the ADC range. A rise of 6 dB up to a drop fall of correct the clamp error. It is also possible to give a fixed
6 dB w.r.t. the nominal values can be achieved. The gain correction value by the microprocessor.
setting within this range is done digitally via control
registers. For this purpose a gain setting DAC is 7.2.3 4 : 4 : 4 TO 4 : 1 : 1 DOWN-SAMPLING AND UV
incorporated. The smallest step in the gain setting should CORING
be hardly visible on the picture, which can be met with
smallest steps of 0.4%/step. The U and V samples from the ADC are low-pass filtered,
before being subsampled with a factor of 2. Coring is
Luminance and chrominance gain settings can be applied to the subsampled signal to obtain no gain for low
separately controlled. The reason for this split is that amplitudes which is considered to be noise. Coring levels
U and V may be gain adjusted already, whereas can be programmed as 0 (off), ±1⁄2, ±1 and ±2 LSB.
luminance is to be adjusted by the SAA4977H AGC. On
the other hand, for RGB originated sources, Y, U and V The U and V samples from the 4 : 2 : 2 data are low-pass
should be adjusted with the same AGC gain. filtered again, before being subsampled a second time
with a factor of 2 and formatted to 4 : 1 : 1 format.
7.1.3 ANALOG ANTI-ALIASING PREFILTERING
7.2.4 Y-DELAY
A third order linear phase filter is applied on each of the Y,
U and V channels. It provides a notch on fCLK (16 MHz) to The Y samples can be shifted onto 8 positions w.r.t. the
strongly prevent aliasing to low frequencies, which would UV samples. This shift is meant to account for a possible
be the most disturbing. The bandwidth of the filters is difference in delay previous to the SAA4977H. The zero
designed for −3 dB at 5.6 MHz. The filters can be delay setting is suitable for the nominal case of aligned
bypassed if external filtering with other characteristics is input data according to the interface format standard.
desired. The other settings provide four samples less delay to three
sample more delay in Y.
1998 Jul 23 8
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7.2.5 HORIZONTAL COMPRESSION • The original signal band-passed with centre frequency
of 2.38 MHz.
For displaying 4 : 3 sources on 16 : 9 screens a horizontal
signal compression can be done by data interpolation. The band-passed and high-passed signals are weighted
Therefore two horizontal compression factors of either with factors 0, 1⁄16, 2⁄16, 3⁄16, 4⁄16, 5⁄16, 6⁄16, and 8⁄16, resulting
4⁄ or 7⁄ are possible. Via the I2C-bus the compression can in a maximum gain difference of 2 dB at the centre
3 6
be switched on or off and the compression mode 16 : 9 or frequencies.
14 : 9 can be selected. When the compression mode is
Coring is added to obtain no gain for low amplitudes in the
active, a reduced number of the interpolated data is stored
high-pass and band-pass filtered signal, which is
in the field memory. To achieve sufficiently high accuracy
considered to be noise. Coring levels can be programmed
in interpolation Variable Phase Delay filters are used
as 0 (off), ±8, ±16, ±24 to ±120 LSB w.r.t. the (signed)
(VPD10 for luminance, a multiplexed VPD06 for UV).
11-bit filtered signal.
7.3 Digital processing at 2fH level In addition the peaking gain can be reduced depending on
the signal amplitude, programming range 0 (no
7.3.1 4 : 1 : 1 TO 4 : 2 : 2 UP-CONVERSION attenuation), 1⁄4, 2⁄4, and 4⁄4. It is also possible to make
An up-converter to 4 : 2 : 2 is applied with a linear larger undershoots than overshoots, programming range 0
interpolation filter for creation of the extra samples. These (no attenuation of undershoots), 1⁄4, 2⁄4, and 4⁄4.
are combined with the original samples from the 4 : 1 : 1
stream. 7.3.4 Y-DELAY
The Y samples can be shifted onto 8 positions w.r.t. the
7.3.2 DCTI UV samples. This shift is meant to account for a possible
The Digital Colour Transient Improvement (DCTI) is difference in delay previous to the SAA4977H. The zero
intended for U and V signals originating from a 4 : 1 : 1 delay setting is suitable for the nominal case of aligned
source. Horizontal transients are detected and enhanced input data. The other settings provide one to seven
without overshoots by differentiating, make absolute and samples less delay in Y.
again differentiating the U and V signals separately.
7.3.5 SIDEPANELS AND BLANKING
This results in a 4 : 4 : 4 U and V bandwidth. To prevent
third harmonic distortion, typical for this processing, a so Sidepanels are generated by switching Y and the 4 MSBs
called over the hill protection prevents peak signals of U and V to certain programmable values. The start and
becoming distorted. Via the I2C-bus it is possible to stop values for the sidepanels w.r.t. the rising edge of the
control: gain width (see Fig.4), threshold (i.e. immunity HRD signal are programmable in a resolution of 4 LLD
against noise), selection of simple or improved first clock cycles. In addition, a fine shift of 0 to 3 LLD clock
differentiating filter (see Fig.3), limit for pixel shift range cycles of both values can be achieved.
(see Fig.5), common or separate processing of U and V Blanking is done by switching Y to value 64 at 10-bit word
signals, hill protection mode (i.e. no discolourations in and UV to value 0 (in 2’s complement). Blanking is
narrow colour gaps), low-pass filtering for U and V signals controlled by a composite signal HVBDA, consisting of a
(see Fig.6) and a so called super hill mode, which avoids horizontal part HBDA and a vertical part VBDA. Set and
discolourations in transients within a colour component. reset value of the horizontal control signal HBDA are
programmable w.r.t. the rising edge of the HRD signal, set
7.3.3 Y-PEAKING and reset value of the vertical control signal VBDA are
A linear peaking is applied, which amplifies the luminance programmable w.r.t. the rising edge of the VA signal.
signal in the middle and the upper ranges of the The range of the Y output signal can be selected between
bandwidth. 9 and 10 bits. In the case of 9 bits for the nominal signal
The filtering is an addition of: there is room left for undershoot and overshoot (adding up
to a total of 10 bits). In the case of selecting all 10 bits of
• The original signal
the luminance DAC for the nominal signal any under or
• The original signal high-passed with maximum gain at overshoot will be clipped (see Fig.11).
frequency = 1⁄2fs (8 MHz)
• The original signal band-passed with centre
frequency = 1⁄4fs (4 MHz)
1998 Jul 23 9
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MGM689
1
handbook, halfpage
signal
amplitude
0.8
(1) (2)
0.6
0.4
0.2
0
0 0.05 0.1 0.15 0.2 0.25
f/fs
(1) dcti_ddx_sel = 1.
(2) dcti_ddx_sel = 0.
Fig.3 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel.
handbook, full pagewidth MGM690

500
digital
signal 400
amplitude
(1)
300
(2)
(4)
(3)
200 (5)
100
0
samples
−100
−200
−300
(1) input signal. −400

(2) gain = 1.
(3) gain = 3. −500
(4) gain = 5.
(5) gain = 7.
Fig.4 DCTI with variation of gain setting (limit = 1).
1998 Jul 23 10
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handbook, full pagewidth MGM691

500
digital (4)
signal 400 (3)
amplitude
(2)
300
(1)
200
100
0
samples
−100
−200
−300
−400
(1) input signal.
(2) limit = 1. −500
(3) limit = 2.
(4) limit = 3.
Fig.5 DCTI with variation of limit setting (gain = 7).
MGM692
1.2
handbook, halfpage
signal
amplitude
0.8
0.4
0
0 0.1 0.2 0.3 0.4 0.5
f/fs
Fig.6 DCTI post-filter transfer function.
1998 Jul 23 11
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MGM594
10
signal (7)
amplitude
(dB)
8
(6)
(5)
6
(4)
(3)
(2)
2
(1)
0
0 0.1 0.2 0.3 0.4 f/fs 0.5
(1) β = 1⁄16.
(2) β = 2⁄16.
(3) β = 3⁄16.
(4) β = 4⁄16.
(5) β = 5⁄16.
(6) β = 6⁄16.
(7) β = 8⁄16.
Fig.7 Transfer function of the peaking high-pass filter with variation of β (α = 0; τ = 0).
1998 Jul 23 12
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MGM595
10
signal (7)
amplitude
(dB)
8
(6)
(5)
6
(4)
(3)
4
(2)
2
(1)
0
0 0.1 0.2 0.3 0.4 f/fs 0.5
(1) α = 1⁄16.
(2) α = 2⁄16.
(3) α = 3⁄16.
(4) α = 4⁄16.
(5) α = 5⁄16.
(6) α = 6⁄16.
(7) α = 8⁄16.
Fig.8 Transfer function of the peaking band-pass with variation of α (β = 0; τ = 0).
1998 Jul 23 13
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MGM596
10
signal
amplitude
(dB)
8 (7)
(6)
6
(5)
(4)
4
(3)
(2)
2
(1)
0
0 0.1 0.2 0.3 0.4 0.5
f/fs
(1) τ = 1⁄16.
(2) τ = 2⁄16.
(3) τ = 3⁄16.
(4) τ = 4⁄16.
(5) τ = 5⁄16.
(6) τ = 6⁄16.
(7) τ = 8⁄16.
Fig.9 Transfer function of peaking low band-pass with variation of τ (α = 0; β = 0).
1998 Jul 23 14
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7.4 Digital-to-analog conversion When reading from the bus, one byte is loaded by the
microprocessor for the address, the received byte is the
Three identical 10-bit DACs are used to map the 4 : 4 : 4
data from the addressed SNERT location.
data to analog levels.
7.5.3 I/O PORTS
7.5 Microprocessor
A parallel 8-bit I/O port (P1) is available, where P1.0 is
The SAA4977H contains an embedded 80C51
used as the SNERT reset signal (SNRST), P1.1 to P1.5
microprocessor core including a 256 byte RAM and
can be used for application specific control signals, and
16 kbyte ROM. The microprocessor runs on a 16 MHz
P1.6 and P1.7 are used as I2C-bus signals (SCL and
clock, generated by dividing the 32 MHz display clock by a
SDA).
factor of 2. For controlling internal registers a host
interface, consisting of a parallel address and data bus, is
7.5.4 WATCHDOG TIMER
built-in, that can be addressed as internal AUX RAM via
MOVX type of instructions. The microprocessor contains an internal Watchdog Timer,
which can be activated by setting the bit 4 in SFR PCON.
7.5.1 I2C-BUS Only a synchronous reset will clear this bit. To prevent a
system reset the Watchdog Timer must be reloaded in
The I2C-bus interface in the SAA4977H is used in a slave time. The Watchdog Timer is incremented every 0.75 ms.
receive and transmit mode for communication with a The time interval between the timer’s reloading and the
central system microprocessor. The standardized bus occurrence of a reset depends on the reloaded 8-bit value.
frequencies of both 100 kHz and 400 kHz can be dealt
with.
7.6 Memory controller
The I2C-bus slave address of the SAA4977H is
The memory controller provides all necessary acquisition
0110100 R/W.
clock related write signals (WE and RSTW) and display
For a detailed description of the transmission protocol clock related read signals (RE and IE2) to control one or
refer to brochure “The I2C-bus and how to use it” (order two-field memory concepts. Furthermore the drive signals
number 9398 393 40011) and to Application note “I2C-bus (HDFL and VDFL) for the horizontal and vertical deflection
register specification of the SAA4977H” (AN98054). power stages are generated. Also a horizontal blanking
pulse BLND is generated which can be used for peripheral
7.5.2 SNERT-BUS circuits as SAA4990H. The memory controller is
connected to the microprocessor via the host interface.
A SNERT interface is built-in, which operates in a master Start and stop values for all pulses, referring to the
receive and transmit mode for communication with corresponding horizontal or vertical reference signal, are
peripheral circuits such as the SAA4990H or programmable under control of the internal software.
SAA4991WP. The SNERT interface replaces the standard To allow user access to these control signals via the
UART interface. In contrast to the 80C51 UART interface I2C-bus a range of subaddresses is reserved; for a
there are additional special function registers and there is detailed description of this user interface refer to
no byte separation time between address and data. Application Note “I2C-bus register specification of the
The SNERT interface transforms the parallel data from the SAA4977H” (AN98054).
microprocessor into 1 Mbaud SNERT data. The
SNERT-bus consists of three signals: SNCL used as the 7.6.1 WE
serial clock signal and is generated by the SNERT
The write enable signal for field memory 1 is a composite
interface; SNDA used as the bidirectional data line, and
signal consisting of a horizontal and a vertical part.
SNRST used as the reset signal and is generated by the
The horizontal position w.r.t the rising edge of the HA
microprocessor to indicate the start of a transmission.
signal and the vertical position w.r.t the rising edge of the
The read or write operation must be set by the VA signal are programmable.
microprocessor. When writing to the bus, 2 bytes are
loaded by the microprocessor: one for the address, the
other for the data.
1998 Jul 23 15
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7.6.2 RSTW 7.7.2 PLL CLOCK GENERATOR RUNNING AT 32 MHZ

(2048 CLOCK CYCLES PER LINE)
Reset write signal for field memory 1; this signal is derived
from the positive edge of the VA input signal and has a The basic frequency of the clock generator is 32 MHz.
pulse width of 64 µs. The type of PLL is known as ‘Petra PLL’. This is a purely
analog clock generator, with analog frequency control via
7.6.3 RE a loop filter on the measured phase error.
The read enable signal for field memory 1 is a composite
7.7.3 DIVIDE-BY-2 FOR MASTER CLOCK 16 MHZ
signal consisting of a horizontal and a vertical part.
The horizontal position w.r.t the rising edge of the HA A simple clock divider is used to generate 16 MHz out of
signal and the vertical position w.r.t the rising edge of the 32 MHz. The advantage of this construction is the inherent
VA signal are programmable. 50% duty cycle on the acquisition clock.
7.6.4 IE2 7.7.4 DIVIDE BY ANOTHER 1024 TO GENERATE LINE

FREQUENT, CLOCK SYNCHRONOUS Href SIGNAL
Input enable signal for field memory 2, can be directly set
or reset by the microprocessor. The video lines contain 1024 clock cycles of 16 MHz.
Therefore, frequency division by 1024 creates a 50% duty
7.6.5 HDFL cycle line frequent signal Href.
Horizontal deflection signal for driving a deflection circuit;
this signal has a cycle time of 32 µs and a pulse width of 7.8 Clock and sync interfacing
76 LLD clock cycles. Typically the circuit operates as a two clock system, i.e.
LLA is supplied with a 16 MHz clock and LLD with a
7.6.6 VDFL 32 MHz clock.
Vertical deflection signal for driving a deflection circuit; this The line locked display clock LLD must be provided by the
signal has a cycle time of 10 ms; the start and stop value application. Also a line frequent signal must be provided by
w.r.t the rising edge of the VA signal is programmable in the application at pin HA. A vertical 50 or 60 Hz
steps of 16 µs. synchronization signal has to be applied on pin VA.
It is also possible to use an external line locked acquisition
7.6.7 BLND
clock, which must be provided at pin LLA. This operation
Horizontal blanking signal for peripheral circuits e.g. mode can be selected by the SELCLK pin. When using the
SAA4990H, start and stop values w.r.t. the rising edge of external acquisition clock the HA signal must be
HRD are programmable. synchronous to the acquisition clock.
A display clock synchronous line frequent signal is put out
7.7 Line locked clock generation
at pin HRD providing a duty factor of 50%. The rising edge
7.7.1 PHASE COMPARISON OF HA RISING EDGE WITH of HRD is also the reference for display related control
GENERATED Href SIGNAL signals as BLND, RE, HDAV and HBDA.
The HA signal, which has a nominal period of 64 µs, is The acquisition clock is buffered internally and put out as
used as a timing reference for the line locked acquisition serial write clock (SWC) for supplying the field memory.
clock system. This HA signal may vary in position from
application to application, related to the active video part.
The phase comparator measures the delay between the
HA and the internally generated, clock synchronous Href
signal.
1998 Jul 23 16
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7.9 4 : 1 : 1 I/O interfacing

Table 2 Digital input and output bus format
OUTPUT INPUT
4 : 1 : 1 FORMAT
PIN PIN
YO7 Y07 Y17 Y27 Y37 YI7
YO6 Y06 Y16 Y26 Y36 YI6
YO5 Y05 Y15 Y25 Y35 YI5
YO4 Y04 Y14 Y24 Y34 YI4
YO3 Y03 Y13 Y23 Y33 YI3
YO2 Y02 Y12 Y22 Y32 YI2
Y01 Y01 Y11 Y21 Y31 YI1
YO0 Y00 Y10 Y20 Y30 YI0
UVO7 U07 U05 U03 U01 UVI7
UVO6 U06 U04 U02 U00 UVI6
UVO5 V07 V05 V03 V01 UVI5
UVO4 V06 V04 V02 V00 UVI4
The first phase of the 4 : 1 : 1 YUV dataword is available

on the output bus one SWC clock cycle after the rising
edge of the WE signal. The start position, when the first
phase of the 4 : 1 : 1 YUV data word is expected on the
input bus, can be defined by the internal control signal
HDAV.
The luminance output signal is in 8-bit straight binary
format, whereas U and V input signals are in
2’s complement format. Also the luminance input signal is
expected in 8-bit straight binary format, whereas U and V
input signals are expected in 2’s complement format. The
U and V input signals are inverted if the corresponding
control bit uv_inv is set via the I2C-bus.
7.10 Test mode operation

The SAA4977H provides a test mode function which
should not be entered by the customer. If the TRST input
is driven HIGH, different test modes can be selected by
applying a HIGH to the TMS input for a defined number of
LLD clock cycles. To exit the test mode TMS and TRST
must be driven LOW.
1998 Jul 23 17
Besic SAA4977H
7.11 I2C-bus control registers
ADDRESS BIT NAME DESCRIPTION

Subaddress 00H to 2FH: reserved; note 1
Subaddress 30H to 32H (AGC)
30H 0 to 7 AGC_Y AGC gain for Y channel (2’s complement relative to 0 dB): upper 8 bits
31H 0 to 7 AGC_UV AGC gain for U and V channel (2’s complement relative to 0 dB): upper 8 bits
32H 0 AGC_Y AGC gain for Y channel LSB
1 AGC_UV AGC gain for UV channel LSB
2 standby_f front-end in standby mode if HIGH
3 aaf_bypass bypass for prefilter if HIGH
4 to 7 − reserved
Subaddress 33H (UV clamp correction)
33H 0 and 1 UVclcor_mode clamp correction mode = auto, fixed, keep, reserved
2 to 4 Uclcor_fval fixed value for clamp correction U channel
5 to 7 Vclcor_fval fixed value for clamp correction V channel
Subaddress 34H (UV coring)
34H 0 and 1 UVcoring coring level = 0, ±0.5, ±1 and ±2 LSB
2 and 3 − reserved
4 and 5 UVcl_tau vertical filtering of measured clamp
Subaddress 35H (Y delay)
35H 0 to 2 ydelay_f variable Y-delay in LLA clock cycles: −4, −3, −2, −1, 0, 1, 2 and 3
3 and 4 overl_thr overload threshold: (216, 224, 232, 240)
5 fill_mem fill memory with constant value if HIGH
Subaddress 36H and 37H (DCTI)
36H 0 to 2 dcti_gain DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7
3 to 6 dcti_threshold DCTI threshold: 0, 1 to 15
7 dcti_ddx_sel DCTI selection of first differentiating filter; see Fig.3
37H 0 and 1 dcti_limit DCTI limit for pixel shift range: 0, 1, 2 and 3
2 dcti_separate DCTI separate processing of U and V signals; 0 = off, 1 = on
3 dcti_protection DCTI over the hill protection; 0 = off, 1 = on
4 dcti_filteron DCTI post-filter; 0 = off, 1 = on
5 dcti_superhill DCTI super hill mode; 0 = off, 1 = on
Subaddress 38H and 3AH (peaking)
38H 0 to 2 pk_alpha peaking alpha: 1⁄16 (0, 1, 2, 3, 4, 5, 6, 8)
3 to 5 pk_beta peaking beta: 1⁄16 (0, 1, 2, 3, 4, 5, 6, 8)
1998 Jul 23 18
Besic SAA4977H
ADDRESS BIT NAME DESCRIPTION

39H 0 to 2 pk_tau peaking tau: 1⁄ (0, 1, 2, 3, 4, 5, 6, 8)
16
3 and 4 pk_delta peaking amplitude dependent attenuation: 1⁄4 (0, 1, 2, 4)
5 and 6 pk_neggain peaking attenuation of undershoots: 1⁄4 (0, 1, 2, 4)
7 − reserved
3AH 0 to 3 pk_corthr peaking coring threshold 0, ±8, ±16 to ±120 LSB
4 to 7 − reserved
Subaddress 3BH and 3CH (sidepanels overlay)
3BH 0 to 3 overlay_u sidepanels overlay U (4 MSB)
4 to 7 overlay_v sidepanels overlay V (4 MSB)
3CH 0 to 7 overlay_y sidepanels overlay Y (8 MSB)
Subaddress 3DH to 3FH (sidepanel position)
3DH 0 to 7 sidepanel_start sidepanel start position (8 MSB) w.r.t. the rising edge of HRD signal
3EH 0 to 7 sidepanel_stop sidepanel stop position (8 MSB) w.r.t. the rising edge of HRD signal
3FH 0 and 1 sidepanel_fdel fine delay of sidepanel signal in LLD clock cycles: 0, 1, 2 and 3
2 output_range output range (output range = 0: 9 bit for the nominal output signal,
black level: 288 and white level: 767; output range = 1: 10 bit for the nominal
output signal, black level 64 and white level 1023)
3 uv_inv inverts UV input signals: 0 = no inversion, 1 = inversion
4 to 6 ydelay_out variable Y-delay in LLD clock cycles: −7, −6, −5, −4, −3, −2, −1 and 0
7 − reserved
Note
1. Detailed information about the software dependent I2C-bus registers can be found in Application Note “I2C-bus
register specification of the SAA4977H” (AN98054).
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER MIN. MAX. UNIT
VDDA(1,2,3) analog supply voltage front-end −0.5 +5.25 V
VDDD(1,2,3) digital supply voltage front-end −0.5 +5.25 V
VDDA(4,5) analog supply voltage back-end −0.5 +3.45 V
VDDD(4,5,6) digital supply voltage back-end −0.5 +3.45 V
VDDIO digital I/O supply voltage back-end −0.5 +5.25 V
Vi input voltage for all I/O pins −0.5 +5.25 V
Tstg storage temperature −20 +150 °C
Tamb operating ambient temperature −20 +60 °C
9 THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 50 K/W
1998 Jul 23 19
Besic SAA4977H
10 CHARACTERISTICS
VDDD(1,2,3) = 4.75 to 5.25 V; VDDA(1,2,3) = 4.75 to 5.25 V; VDDD(4,5,6) = 3.15 to 3.45 V; VDDA(4,5) = 3.15 to 3.45 V;
Tamb = 0 to 60 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply
VDDA(1,2,3) analog supply voltage front-end 4.75 5.0 5.25 V
VDDD(1,2,3) digital supply voltage front-end 4.75 5.0 5.25 V
IDDA(1,2,3) analog supply current front-end − 85 100 mA
IDDD(1,2,3) digital supply current front-end − 65 80 mA
VDDA(4,5) analog supply voltage back-end 3.15 3.3 3.45 V
VDDD(4,5,6) digital supply voltage back-end 3.15 3.3 3.45 V
VDDIO I/O supply voltage back-end 4.75 5.0 5.25 V
IDDA(4,5) analog supply current back-end − 25 35 mA
IDDD(4,5,6) digital supply current back-end − 40 55 mA
IDDIO I/O supply current back-end − 1 10 mA
Dissipation
Ptot total power dissipation − − 1.3 W
Luminance input signal (Y clamp level digital 16)
Vi(p-p) Y input level AGC fixed at 0 dB; note 1 0.95 1.00 1.05 V
(peak-to-peak value)
Ci input capacitance − 7 15 pF
ILI input leakage current clamp not active − − 100 nA
II input current during clamping − − ±150 µA
αAGC(max) maximum AGC attenuation 5.75 6 − dB
GAGC(max) maximum AGC gain 5.75 6 − dB
αAGC(acc) AGC attenuation accuracy − 8 − bits
digital
GAGC(acc) AGC gain accuracy digital − 8 − bits
Colour difference input signals (U and V clamp level digital 128)
Vi(p-p) U input level AGC fixed at 0 dB; note 1 1.29 1.34 1.39 V
V input level AGC fixed at 0 dB; note 1 1.00 1.05 1.10 V
Ci input capacitance − − 15 pF
ILI input leakage current clamp not active − − 100 nA
II input current during clamping − − ±150 µA
αAGC(max) maximum AGC attenuation 5.75 6 − dB
GAGC(max) maximum AGC gain 5.75 6 − dB
αAGC(acc) AGC attenuation accuracy − 8 − bits
digital
GAGC(acc) AGC gain accuracy digital − 8 − bits
1998 Jul 23 20
Besic SAA4977H

Analog input transfer function (sample rate 16 MHz/8 bits)
fCLK maximum sample clock 18 − − MHz
INL integral non linearity ramp input signal −1 − +1 LSB
DNL differential non linearity ramp input signal −0.75 − +0.75 LSB
S/N signal-to-noise ratio nominal amplitude; 43 − − dB
0 to 8 MHz
HD harmonic distortion (2nd to 5th 95% amplitude; − −50 −37 dB
harmonic) Y at 4.3 MHz; UV at 1 MHz
Gdif differential gain fCLK = 4.4 MHz; ADC only; − 1 2 %
at nominal AGC setting
SVR supply voltage rejection note 2 34 − − dB
Analog Y, U and V input filter (third order linear phase filter with notch at fCLK)
f(−3dB) 3 dB down frequency fCLK = 16 MHz 5.4 5.6 5.8 MHz
α(0.5) attenuation at 1⁄ f
2 CLK (8 MHz) 7 8 − dB
αsb stop band attenuation 30 − − dB
fnotch notch frequency 15.5 16 16.5 MHz
td(g) group delay fCLK = 4 MHz − 55 65 ns
td(g)(dif) differential group delay within − 20 30 ns
1 to 6 MHz
Luminance output signal (output_range = 0: Y black level digital 288, white level digital 767, output_range = 1:
Y black level digital 64, white level digital 1023); see Fig.11
Vo(p-p) Y output level ZL = 2 kΩ 1.28 1.34 1.40 V
Ro output resistance − 50 100 Ω
RL resistive load 1 2 − kΩ
CL capacitive load − − 25 pF
αct crosstalk attenuation between 0 to 10 MHz 40 − − dB
outputs
0 to 10 MHz
Colour difference output signals (U and V digital range 0 to 1023)
Vo(p-p) U output level ZL = 2 kΩ 1.28 1.34 1.40 V
V output level ZL = 2 kΩ 1.28 1.34 1.40 V
Gm(U-V) gain matching U to V − 1 3 %
Ro output resistance − 50 100 Ω
RL resistive load 1 2 − kΩ
CL capacitive load − − 25 pF
1998 Jul 23 21
Besic SAA4977H

αct crosstalk attenuation between 0 to 10 MHz 40 − − dB
outputs
0 to 10 MHz
Output transfer function (sample rate 32 MHz/10 bits)
INL integral non linearity −2 − +2 LSB
DNL differential non linearity −1 − +1 LSB
Digital output signals: YO, UVO, WE and RSTW (CL = 15 pF); timing referred to SWC clock
VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V
VOL LOW-level output voltage IOL = 1.6 mA − − 0.4 V
td(o) output delay time see Fig.10 − − 20 ns
th(o) output hold time see Fig.10 4 − − ns
Digital output signal: SWC (CL = 15 pF); timing referred to LLA clock
td(o) output delay time see Fig.10 3 − 12 ns
Digital output signal: HRD
Digital output signals: IE2, BLND, RE, HDFL and VDFL (CL = 15 pF); timing referred to LLD clock
td(o) output delay time see Fig.10 − − 20 ns
th(o) output hold time see Fig.10 4 − − ns
Digital input/output signals: P1.1 to P1.5 and SNRST
VOL LOW-level output voltage IOL = 1.6 mA 0 − 0.4 V
VIH HIGH-level input voltage 2.0 − 5.5 V
VIL LOW-level input voltage 0 − 0.8 V
Digital input signals: YI and UVI; timing referred to LLD clock
VIL LOW-level input voltage − − 0.8 V
tsu(i) input set-up time see Fig.10 4 − − ns
th(i) input hold time see Fig.10 3 − − ns
1998 Jul 23 22
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Digital input signal: HA; timing referred to LLA clock (only when SELCLK = 0, HA used as digital horizontal
reference)
tsu(i) input set-up time see Fig.10 7 − − ns
th(i) input hold time see Fig.10 4 − − ns
Digital input signals: TRST, TMS, RST and VA
Digital input clock signal: LLA
fLLA sample clock frequency 14 16 34 MHz
δclk clock duty factor 40 50 60 %
VIH HIGH-level input voltage 2.4 − − V
tr clock rise time see Fig.10 − − 5 ns
tf clock fall time see Fig.10 − − 5 ns
Digital input clock signal: LLD
fLLD sample clock frequency 30 32 34 MHz
δclk clock duty factor 40 50 60 %
VIH HIGH-level input voltage 2.4 − − V
tr clock rise time see Fig.10 − − 5 ns
tf clock fall time see Fig.10 − − 5 ns
I2C-bus signal: SDA and SCL; note 3
VIH HIGH-level input voltage 0.7VDDIO − − V
VIL LOW-level input voltage − − 0.3VDDIO V
fSCL SCL clock frequency − − 400 kHz
tHD;STA hold time START condition 0.6 − − µs
tLOW SCL LOW time 1.3 − − µs
tHIGH SCL HIGH time 0.6 − − µs
tSU;DAT data set-up time 100 − − ns
tSU;DAT1 data set-up time (before 0.6 − − µs
repeated START condition)
tSU;DAT2 data set-up time (before STOP 0.6 − − µs
condition)
tSU;STA set-up time repeated START 0.6 − − µs
tSU;STO set-up time STOP condition 0.6 − − µs
1998 Jul 23 23
Besic SAA4977H

SNERT-bus: SNDA and SNCL; note 4
tsu(i) input set-up time 700 − − ns
th(i) input hold time 0 − − ns
tcycle SNCL cycle time − 1 − µs
th(o) output hold time 50 − − ns
Notes
1. With AGC at −3 dB, U full ADC range is obtained at Vi = 1.89 V; with AGC at +6 dB, U full ADC range is obtained at
Vi = 0.67 V; with AGC at −3 dB, V full ADC range is obtained at Vi = 1.48 V; with AGC at +6 dB, V full ADC range is
obtained at Vi = 0.52 V.
2. Supply voltage ripple rejection, measured over a frequency range from 20 Hz to 50 kHz. This includes 1⁄2fV, fV, 2fV,
fH and 2fH which are major load frequencies: SVR is relative variation of the full scale analog input for a supply
variation of 0.25 V.
3. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum
400 kHz). Information about the I2C-bus can be found in the brochure “I2C-bus and how to use it” (order number
9398 393 40011).
4. More information about the SNERT-bus protocol can be found in Application Note “The SNERT-bus specification”
(AN95127).
handbook, full pagewidth tr tf
2.4 V
CLOCK 1.5 V
0.6 V
th(i)
tsu(i)
2.0 V
INPUT
DATA
0.8 V
td(o)
th(o)
2.4 V
OUTPUT
DATA
0.4 V
MGM597
Fig.10 Timing diagram.
1998 Jul 23 24
Besic SAA4977H
handbook, full pagewidth INPUT 8 bit OUTPUT 10 bit

output_range = 1 output_range = 0
white 255 1023 1023
767
1.00 V 1.34 V
288
256
black 16 64
0 0 0
MGM598
Fig.11 Luminance levels.
11 APPLICATION
The SAA4977H supports two different up-converter concepts. The simple one is shown in Fig.12. In this application only
one field memory SAA4955TJ is needed for a 100 Hz conversion based on a field repetition algorithm (AABB mode).
The concept can be upgraded by a noise reduction based on a motion adaptive field recursive filter if the SAA4956TJ is
used instead of the SAA4955TJ.
The SAA4977H supports a dual-clock system. The acquisition clock is taken from the digital front-end. The display
control is based on a clock generated by an external H-PLL. By this structure the stability of the display is enhanced
compared to a one-clock system if an unstable source like a VCR is used as an input.
The second system supported by the SAA4977H is shown in Fig.13. This concept needs two field memories
(SAA4955TJ) and the signal processing IC MELZONIC (SAA4991WP). The SAA4991WP allows a vector based motion
estimation and compensation for a display of 100 Hz pictures in high-end TV sets which is free of motion artefacts.
It additionally provides a variable vertical zoom function, noise and cross colour reduction. Furthermore a multi-PIP
feature is supported making use of the field memories.
1998 Jul 23 25
Besic SAA4977H
+5 V
+3.3 V
8, 11, 69, 17, 18, 19, 10 µF

YIN 26 75, 80 23, 25, 29,
46, 67 9
UIN 28
VIN 30 8.2 kΩ
+3.3 V +5 V
19, 22 20, 21, 23

SWC D11
15 47 45
D11 RSTW D10
3 16 24 44
D10 WE D9
4 17, 18 32 43
D9 D8
5 38 51 42
D8 D7
6 37 52 41
D7 D6
7 36 53 40
D6 D5
8 35 54 39
D5 D4
9 34 55 38
D4 SAA4955TJ(1) SAA4977H D3
10 33 56 37
D3 D2
11 32 57 36
D2 D1
12 31 58 35
D1 D0
13 30 59 34
D0
14 29 60
79 YOUT
28 61
76 UOUT
25 27 62
RE 74 VOUT
26 24 63
1, 2, 39, 40 1 SDA
2 SCL
20
22 14 to 16, 71 HDFL
21, 27, 31, 72 VDFL
HRD 48 to 50, 3 to 7,
68 33, 65, 73, 10, 12, 70
77, 78 13, 64, 66
n.c.
VA SRC
DISPLAY
HA PLL
MGM599
(1) Alternatively SAA4956TJ.
Fig.12 Application diagram 1.
1998 Jul 23 26
Besic SAA4977H
handbook,
YIN full pagewidth
UIN +5 V
VIN +3.3 V
SWC
+3.3 V +5 V 8, 11, 69, 17, 18, 19, 10 µF
RSTW
26 75, 80 23, 25, 29, 9
WE 46, 67
19, 22 20, 21, 23 28
15 8.2 kΩ
D11 +5 V 30
3 16
D10 47
4 17, 18 1, 4, 20, 42,
D9 24
5 38 41 46, 65, 78
32 D11
D8 45
6 37 40 D10
D7 48 51
44
7 36 38 D9
D6 49 52
43
8 35 37 D8
D5 50 53
42
9 SAA4955TJ 34 36
51 54 D7
D4 41
10 FM1 33 35 D6
D3 52 55
40
11 32 34 D5
D2 53 56
39
12 31 33 D4
D1 54 57
38
13 30 32 SAA4977H D3
D0 55 58
37
14 29 31 D2
56 59
36
28 30 D1
57 60
35
25 27 29 D0
RE1 58 61
34
26 24 28
59 62
1, 2, 39, 40 RE 79 YOUT
61 63
76 UOUT
+3.3 V +5 V SNDA 74 VOUT
44 12
SAA4991WP SNCL
19, 22 20, 21, 23 43 13 1 SDA
15 2 SCL
D11 20
3 16
D10 WE2 22 14 to 16, 71 HDFL
4 17, 18 11 8 to 10 n.c.
D9 21, 27, 31, 72 VDFL
5 38 64 48 to 50,
D8 D11 HRD
68 33, 65, 73, 3 to 7, 70
6 37 66 25
D7 D10 77, 78 10, 64, 66
7 36 67 24
D6 D9
8 35 68 23 n.c.
D5 D8
9 SAA4955TJ 34 69 21
D4 D7
10 FM2 33 70 19
DISPLAY SRC
D3 D6
11 32 71 18 PLL
D2 D5
12 31 72 17
D1 D4
13 30 73 16
D0 D3
14 29 74 15
D2
28 75 14
2, 3, 5, 6, 7, D1
25 27 76 13
RE2 22, 26, 27, D0
26 24 77 47, 60, 63, 12
1, 2, 39, 40 79 to 84 62 45
MGM600
VA
HA
Fig.13 Application diagram 2.
1998 Jul 23 27
Besic SAA4977H
12 PACKAGE OUTLINE
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2
c
y
X
64 41 A
65 40
ZE
e
A2
E HE A
A1 (A 3)
wM θ
pin 1 index Lp
bp
L
80 25 detail X
1 24
wM ZD v M A
e bp
D B
HD v M B
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y Z D (1) Z E (1) θ
o
0.25 2.90 0.45 0.25 20.1 14.1 24.2 18.2 1.0 1.0 1.2 7
mm 3.2 0.25 0.8 1.95 0.2 0.2 0.1
0.05 2.65 0.30 0.14 19.9 13.9 23.6 17.6 0.6 0.6 0.8 0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
95-02-04
SOT318-2
97-08-01
1998 Jul 23 28
Besic SAA4977H
13 SOLDERING If wave soldering cannot be avoided, for QFP

packages with a pitch (e) larger than 0.5 mm, the
13.1 Introduction
following conditions must be observed:
There is no soldering method that is ideal for all IC • A double-wave (a turbulent wave with high upward
packages. Wave soldering is often preferred when pressure followed by a smooth laminar wave)
through-hole and surface mounted components are mixed soldering technique should be used.
on one printed-circuit board. However, wave soldering is
• The footprint must be at an angle of 45° to the board
not always suitable for surface mounted ICs, or for
direction and must incorporate solder thieves
printed-circuits with high population densities. In these
downstream and at the side corners.
situations reflow soldering is often used.
During placement and before soldering, the package must
This text gives a very brief insight to a complex technology.
be fixed with a droplet of adhesive. The adhesive can be
A more in-depth account of soldering ICs can be found in
applied by screen printing, pin transfer or syringe
our “Data Handbook IC26; Integrated Circuit Packages”
dispensing. The package can be soldered after the
(order code 9398 652 90011).
adhesive is cured.
13.2 Reflow soldering Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
Reflow soldering techniques are suitable for all QFP
10 seconds, if cooled to less than 150 °C within
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
A mildly-activated flux will eliminate the need for removal
plastic QFP packages (44 leads, or more). If infrared or
of corrosive residues in most applications.
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
13.4 Repairing soldered joints
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details, Fix the component by first soldering two diagonally-
refer to the Drypack information in the “Data Handbook opposite end leads. Use only a low voltage soldering iron
IC26; Integrated Circuit Packages; Section: Packing (less than 24 V) applied to the flat part of the lead. Contact
Methods”. time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
Reflow soldering requires solder paste (a suspension of
one operation within 2 to 5 seconds between
fine solder particles, flux and binding agent) to be applied
270 and 320 °C.
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
13.3 Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Jul 23 29
Besic SAA4977H
14 DEFINITIONS
Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
15 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
16 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1998 Jul 23 30
Besic SAA4977H
NOTES
1998 Jul 23 31
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220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belgium: see The Netherlands Pakistan: see Singapore
Brazil: see South America Philippines: Philips Semiconductors Philippines Inc.,
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
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Tel. +1 800 234 7381 Portugal: see Spain
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Tel. +852 2319 7888, Fax. +852 2319 7700 Tel. +7 095 755 6918, Fax. +7 095 755 6919
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Czech Republic: see Austria Tel. +65 350 2538, Fax. +65 251 6500
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Slovakia: see Austria
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Hungary: see Austria Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
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Tel. +91 22 493 8541, Fax. +91 22 493 0966 Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division, Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
Ireland: Newstead, Clonskeagh, DUBLIN 14, 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +353 1 7640 000, Fax. +353 1 7640 200 Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415 Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Uruguay: see South America
Tel. +60 3 750 5214, Fax. +60 3 757 4880 Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +9-5 800 234 7381 Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998 SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 545104/00/01/pp32 Date of release: 1998 Jul 23 Document order number: 9397 750 03258

Data Sheet: SAA4977H

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INTEGRATED CIRCUITS

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

YO7 to YO0 YI7 to YI0

63, 71, 12,

Fig.2 Pin configuration.

6.2 Pin description

SYMBOL PIN DESCRIPTION

SYMBOL PIN DESCRIPTION

7 FUNCTIONAL DESCRIPTION 7.1.4 TRIPLE 8-BIT ANALOG-TO-DIGITAL CONVERSION

handbook, full pagewidth MGM690

(1) input signal. −400

Fig.4 DCTI with variation of gain setting (limit = 1).

handbook, full pagewidth MGM691

Fig.5 DCTI with variation of limit setting (gain = 7).

Fig.6 DCTI post-filter transfer function.

Fig.8 Transfer function of the peaking band-pass with variation of α (β = 0; τ = 0).

Fig.9 Transfer function of peaking low band-pass with variation of τ (α = 0; β = 0).

7.6.2 RSTW 7.7.2 PLL CLOCK GENERATOR RUNNING AT 32 MHZ

7.6.4 IE2 7.7.4 DIVIDE BY ANOTHER 1024 TO GENERATE LINE

7.9 4 : 1 : 1 I/O interfacing

The first phase of the 4 : 1 : 1 YUV dataword is available

7.10 Test mode operation

7.11 I2C-bus control registers

ADDRESS BIT NAME DESCRIPTION

ADDRESS BIT NAME DESCRIPTION

SYMBOL PARAMETER CONDITIONS VALUE UNIT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

handbook, full pagewidth tr tf

Fig.10 Timing diagram.

handbook, full pagewidth INPUT 8 bit OUTPUT 10 bit

white 255 1023 1023

Fig.11 Luminance levels.

handbook, full pagewidth

8, 11, 69, 17, 18, 19, 10 µF

19, 22 20, 21, 23

(1) Alternatively SAA4956TJ.

Fig.12 Application diagram 1.

Fig.13 Application diagram 2.

DIMENSIONS (mm are the original dimensions)

OUTLINE REFERENCES EUROPEAN

13 SOLDERING If wave soldering cannot be avoided, for QFP

13.3 Wave soldering

Data sheet status

15 LIFE SUPPORT APPLICATIONS

16 PURCHASE OF PHILIPS I2C COMPONENTS

© Philips Electronics N.V. 1998 SCA60

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