International Journal of Scientific and Research Publications, Volume 3, Issue 4, April 2013 1

ISSN 2250-3153

An Overview of Advance Microcontroller Bus Architec-

ture Relate on APB Bridge
Ms. Radhika Koti, Ms. Divya Meshram

Student (M. Tech - VLSI), Priyadarshini College of Engineering, Nagpur - India

Lecturer, Priyadarshini College of Engineering, Nagpur – India

Abstract — The Advanced Microcontroller Bus Architeture be used without royalties AMBA’s target is to help designer of
(AMBA) is a widely used interconnection standard for System embedded system to meet challenges like design for low pow-
on Chip (SoC) design. An AMBA-based microcontroller typi- er consumption, to facilitate the right-first-time development
cally consists of a high-performance system backbone bus of Embedded Microcontroller Products with one or more
(AMBA AHB or AMBA ASB), able to sustain the external CPUs or signal processors, to be technology-independent and
memory bandwidth, on which the CPU, on-chip memory and to encourage modular system [4]. To minimize the silicon in-
other Direct Memory Access (DMA) devices reside. This bus frastructure required supporting efficient on-chip and off-chip
provides a high-bandwidth interface between the elements that communication for both operation and manufacturing test [1].
are involved in the majority of transfers. This paper present
three distinct buses and their comparison. By considering mer- This paper discusses the architecture of AMBA in the section
its of APB , AMBA can be design by using HDL. II, section III deals with the various bus methods and their
comparison is discuss in section IV. Finally section V and VI
Index Terms — AMBA, AHB, ASB, APB, Difference of bus- gives proposed work and conclude the paper.
es
II. ARCHITECTURE OF AMBA BASED SIMPLE
I. INTRODUCTION
MICROCONTROLLER
Today in the era of modern technology micro-electronics play
a very vital role in every aspects of life of an individual, in- An AMBA-based microcontroller typically consists of a
creasing use for micro-electronics equipment increases the high-performance system backbone bus (AMBA AHB or
demand for manufacturing its components and its availability AMBA ASB), able to sustain the external memory band-
[4].Embedded system designers have a choice of using a share width, on which the CPU, on-chip memory and other Direct
or point-to-point bus in their designs [2]. Typically, an embed- Memory Access (DMA) devices reside. This bus provides a
ded design will have a general purpose processor, cache, high-bandwidth interface between the elements that are in-
SDRAM, DMA port, and Bridge port to a slower I/O bus, such volved in the majority of transfers[3]. Fig1 shows AMBA
as the Advanced Micro controller Bus Architecture (AMBA) based Simple Microcontroller. Also located on the high per-
Advanced Peripheral Bus (APB). In addition, there might be a formance bus is a bridge to the lower bandwidth APB, where
port to a DSP processor, or hardware accelerator, common most of the peripheral devices in the system are located.
with the increased use of video in many applications. As chip- AMBA APB provides the basic peripheral macro cell com-
level device geometries become smaller and smaller, more and munications infrastructure as a secondary bus from the higher
more functionality can be added without the concomitant [2] bandwidth pipelined main system bus [1]. Such peripherals
increase in power and cost per die as seen in prior generations. typically:

The Advanced Microcontroller Bus Architecture (AMBA) was (i) Have interfaces which are memory-mapped registers
introduced by ARM Ltd 1996 and is widely used as the on- (ii) Have no high-bandwidth interfaces
chip bus in system on chip (SoC) designs. AMBA is a regis- (iii) Are accessed under programmed control.
tered trademark of ARM Ltd. The first AMBA buses were Ad-
vanced System Bus (ASB) and Advanced Peripheral Bus The AMBA specification [2] has become a de-facto standard
(APB). In its 2nd version, AMBA 2, ARM added AMBA for the semiconductor industry, it has been adopted by more
High-performance Bus (AHB) that is a single clock-edge pro- than 95% of ARM’s partners and a number of IP providers.
tocol. In 2003, ARM introduced [2,4] the 3rd generation, The specification has been successfully implemented in sever-
AMBA 3, including AXI to reach even higher performance in- al ASIC designs. Since the AMBA interface is processor and
terconnect and the Advanced Trace Bus (ATB) as part of the technology independent, it enhances the reusability of periph-
Core Sight on-chip debug and trace solution. eral and system components across a wide range of applica-
These protocols are today the de-facto standard for 32-bit em- tions.
bedded processors because they are well documented and can
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International Journal of Scientific and Research Publications, Volume 3, Issue 4, April 2013 2
ISSN 2250-3153

The AMBA specification [1,3] has been derived to satisfy the Memory Access (DMA) or Digital Signal Processor (DSP)
following four key requirements. to be included as bus masters.

(i) To facilitate the right-first-time development of Embedded The external memory interface, APB bridge and any inter-
Microcontroller Products with one or more CPUs or signal nal memory are the most common AHB slaves. Any other
processors. peripheral in the system could also be included as an AHB
(ii) To be technology-independent and ensure that highly reus- slave. However, low-bandwidth peripherals typically reside
able peripheral and system macro cells can be migrated across on the APB.
a diverse range of IC processes and be appropriate for full-
custom, standard cell and gate array technologies. (B) The Advanced System Bus (ASB): ASB is the first
(iii) To encourage modular system design to improve proces- generation of AMBA system bus. A typical AMBA ASB
sor independence, providing a development road-map for ad- system may contain one or more bus masters. For example,
vanced cached CPU cores and the development of peripheral at least the processor and test interface. However, it would
libraries. also be common for a Direct Memory Access (DMA) or
(iv)To minimize the silicon infrastructure required supporting Digital Signal Processor (DSP) to be included as bus mas-
efficient on-chip and off-chip communication for both opera- ters.
tion and manufacturing test.
The external memory interface, APB bridge and any inter-
nal memory are the most common ASB slaves. Any other
peripheral in the system could also be included as an ASB
slave. However, low-bandwidth peripherals typically reside
on the APB.

(C) The Advanced Peripheral Bus (APB): The APB is part

of the AMBA hierarchy of buses and is optimized for min-
imal power consumption and reduced interface complexity.
The AMBA APB appears as a local secondary bus that is
encapsulated as a single AHB or ASB slave device. APB
provides a low-power extension to the system bus which
builds on AHB or ASB signals directly. The APB bridge
appears as a slave module which handles the bus handshake
and control signal retiming on behalf of the local peripheral
bus. By defining the APB interface from the starting point
of the system bus, the benefits of the system diagnostics
Fig. 1. AMBA based Simple Microcontroller and test methodology can be exploited.

The AMBA APB should be used to interface to any periph-

III. DIFFERENT AMBA BUSES
erals which are low bandwidth and do not require the high
The Advanced Microcontroller Bus Architecture (AMBA) performance of a pipelined bus interface. The latest revi-
is ARM’s no-cost, open specification[1,3,4], which defines sion of the APB[6,7] is specified so that all signal transi-
an on-chip communications standard for designing high tions are only related to the rising edge of the clock. This
performance Embedded Microcontrollers. Three distinct improvement ensures the APB peripherals can be integrated
buses are defined within the AMBA specification: easily into any design flow. These changes to the APB also
make it simpler to interface it to the new AHB. An AMBA
(A) The Advanced High-performance Bus (AHB) APB implementation typically contains a single APB
(B) The Advanced System Bus (ASB) bridge which is required to convert AHB or ASB transfers
(C) The Advanced Peripheral Bus (APB). into a suitable format for the slave devices on the APB. The
bridge provides latching of all address, data and control
(A) The Advanced High-performance Bus (AHB): AHB is signals, as well as providing a second level of decoding to
a new generation of AMBA bus which is intended to ad- generate slave select signals for the APB peripherals.
dress the requirements of high-performance synthesizable
designs. It is a high-performance system bus that supports
multiple bus masters and provides high-bandwidth opera- IV. COMPARISON OF BUSES
tion. Bridging between this higher level of bus and the cur- Following table shows the comparison among the AMBA
rent ASB/APB can be done efficiently to ensure that any buses:
existing designs can be easily integrated. An AMBA AHB
design may contain one or more bus masters, typically a
system would contain at least the processor and test inter-
face. However, it would also be common for a Direct

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International Journal of Scientific and Research Publications, Volume 3, Issue 4, April 2013 3
ISSN 2250-3153

[6] Jaehoon Song, Student member, IEEE, Hyunbean Yi, Member,IEEE,

AHB ASB APB Juhee Han, and Sungju Park, Member, IEEE,”An Efficient SOC Test
Technique by Reusing On/Off-Chip Bus Bridge”IEEE Transcactions
High perfor- High perfor- Low power on Circuits and Systems-I: Regular Papers, Vol,56,No.3,March2009.
mance mance
[7] Sangik Choi and Shinwook Kang, Mobile SamsungElectronics
Co.,Ltd, “Implementation of an On-Chip Bus Bridge between Hetero-
Latched ad-
Pipelined opera- Pipelined opera- geneous Buses with Different Clock Frequencies”.IEEE, IDE-
dress and
tion tion AS’05,1098-8068/2005.
control

Multiple bus Multiple bus Simple inter- AUTHORS

masters masters face 1 First Author: Ms. Radhika Koti
Student M.Tech (VLSI)
Priyadarshini College of Engineering
It consists of It consists of It consist of
Nagpur – India
master, slave, master, slave, APB bridge
Email ID: kotiradhika10@rediffmail.com
arbiter decoder arbiter decoder and slave
2 Second Author: Ms. Divya Meshram
Table 1: Comparison of buses Lecturer, M.Tech
Priyadarshini College of Engineering
Nagpur – India
V. PROPOSED WORK Email ID: divyameshram@gmail.com

As discuss above, APB is good choice for implementing

Advanced Microcontroller Bus Architecture by using HDL.

VI. CONCLUSION

Implementation of proposed work i.e. AMBA APB prvides

the basic peripheral macro cell communications infrastruc-
ture as a secondary bus from the higher bandwidth pipe-
lined main system bus .Such peripherals typically:

(i) Have interfaces which are memory-mapped registers

(ii) Have no high-bandwidth interfaces
(iii) Are accessed under programmed control.

REFERENCES
[1] AMBA specification, version 2.0.

[2] Akhilesh kumar and Richa Sinha, “design and verification analysis of
ABP3 protocol with coverage ”Inaternational journal of advance in
engineering and Technology vol. 1 issue 5 pp.310-317,Nov 2011.

[3] Priyanka Gandhani, Charu Patel “ Moving from AMBA AHB to AXI
Bus in SoC Designs: A Comparative Study” Int. J Comp Sci. Emerging
Tech Vol-2 No 4 ,pp.476-479 August, 2011.

[4] Vani. R. M. and Roopa. M “Design of AHB2APB Bridge for different

phase and Frequency” International Journal of Computer and Electri-
cal Engineering, Vol. 3, No. 2,pp. April, 2011.

[5] Wang Zhonghai,Ye Yizheng,Wang Jinxing, and Yu Mingyan, “Design-

ing AHB/PCI Bridge,”in Proceedings of 4th International Conference
on ASIC, Oct 2001,pp.578-580.

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