FABRICATION OF MICROELECTRONIC DEVICES

UNIT 5 : FABRICATION OF MICROELECTRONIC

DEVICES
5.1 INTRODUCTION

Miniaturized microelectronic circuits are in common use today in

wristwatches, portable CD players, cellular phones, home entertainment
system, fax machine, artificial hearts, military satellites, automotive fuel
injection and others. Over the past decades, the number of components per
integrated circuits has increased from 2,300 in 1971 to 42 million in 2001,
while the number of calculations per second has increased 100,000 times,
from 10,000 to over a billion. The key to this progress has been development
of large-batch-size, semi-conductor processing methods coupled with
miniaturization of electrical components and connectors.

Although semiconducting materials have been used in electronics since the

early decades of this century, it was the invention of the transistor in 1948 that
set would become one of the greatest technological advancements of all
history.

Microelectronics have played an ever-increasing role in our lives since

integrated circuit (IC) technology became the foundation for calculators,
wrist watches, home appliances control, information systems,
telecommunications, automotive controls, robotics, space travel, military
weaponry, and personal computers.

Definition of IC
An integrated circuit (IC) is a collection of electronic devices such as
transistors, diodes, and resistors that have been fabricated and electrically
intra-connected onto a small flat chip of semiconductor material.

The major advantages of today's lCs are their

- Small size : as fabrication technology becomes more advanced, the size
of devices decreases; consequently, more components can be put onto a
chip (a small piece of semiconducting material on which the circuit is
fabricated).
- Cost : mass processing and process automation have helped to reduce
the cost of each completed circuit. The components fabricated diodes,
resistors, and capacitors.

Typical chips produced today have sizes that range from 3 mm X 3 mm to

more than 50mm X 50 mm. In the past, no more than 100 devices could be
lubricated on a single chip; new technology, however, allows densities the
range of 10 million devices per chip. This magnitude of integration has been
termed very large scale integration (VLSI). Some of the most advanced ICs
may contain more than 100 million devices.

Because of the minute scale of microelectronic devices, all fabrication must

take place in an extremely clean environment. Clean rooms are used for this
purpose and are allowed to have a maximum number of 0.5-µm particles per

BPLK 1 DMV 4242

cubic foot. Most modem clean rooms are class 1 (one particle per cubic foot)
to class 10 (ten particles per cubic foot) facilities. In comparison, the
contamination level in modern hospitals is on the order of 10,000 particles per
cubic foot.

The current processes used in the fabrication of microelectronic devices and

integrated circuits can be outlined by Figure 5.1.

FIGURE 5.1 General fabrication sequences for integrated circuits.

5.2 LEARNING OUTCOMES
After completing the unit, students should be able to:
1. Define IC.
2. Arrange the fabrication sequence of IC.
3. Explain silicon, wafer preparation and film deposition process
4. Discuss oxidation, lithography, etching, diffusion and ion implantation,
metallization and testing, bonding and packaging and theirs purpose.
5. Explain yield and reliability
5.3 SEMICONDUCTORS AND SILICON
As the name suggests, semiconductor materials have electrical properties
that lie between those of conductors and insulators, and exhibit resistivities
between 10-3Ω-cm and 108Ω-cm. Semiconductors have become the
foundation for electronic devices because their electrical properties can be
altered when controlled amounts of selected impurity atoms are added to their
crystal structures. These impurity atoms, also known as dopants, have either
one more valence electron (n-type or negative dopant) or one less valence
electron (p-type or positive dopant) than the atoms in the semiconductor
lattice.

n – type - donor (extra one valence electron) / group V

(phosphorous)
p – type - acceptor (less one valence electron) / group III (boron)

For silicon, which is a group IV element, typical n-type and p-type dopants
include phosphorus (group V) and boron (group III), respectively. The
electrical operation of semiconductor devices can be controlled through the
creation of regions of different doping types and concentrations.

Although the earliest electronic devices were fabricated on germanium,

silicon has become the industry standard. The abundance of alternative
forms of silicon is second only to that of oxygen, making it economically
attractive. Silicon's main advantage over germanium is its large energy gap
(1.1 eV) compared to that of germanium (0.66 eV). This energy gap allows
silicon-based devices to operate at temperatures about 150°C higher than
devices fabricated on germanium (about 100°C).

Silicon's important processing advantage is that its oxide (silicon dioxide) is

an excellent insulator and can be used for both isolation and passivation
purposes. Conversely, germanium oxide is water soluble and unsuitable for
electronic devices.

However, silicon has some limitations, which have encouraged the

developments compound semiconductors, specifically gallium arsenide. Its
major advantage over silicon is its ability to emit light, allowing fabrication of
devices such as lasers and light-emitting diodes (LEDs). It also has a larger
energy gap (1.43 eV) and therefore a higher maximum operating temperature
(about 200 °C).

Devices fabricated on gallium arsenide also have much higher operating

speeds than those fabricated on silicon. Some of gallium arsenide's
disadvantages include its considerably higher cost, greater processing
complications, and the difficulty of growing high-quality oxide layers (the need
for which is emphasized throughout this chapter).
5.4 CRYSTAL GROWING AND WAFER PREPARATION
Silicon occurs naturally in the forms of silicon dioxide and various silicates. It
must undergo a series of purification steps in order to become the high-
quality, defect-free, single-crystal material that is required for semiconductor
device fabrication. The process begins by heating silica and carbon together
in an electric furnace, which results in a 95% to 98% pure polycrystalline
silicon. This material is converted to an alternative form, commonly
trichlorosilane, which in turn is purified and decomposed in a high-
temperature hydrogen atmosphere. The result is extremely high-quality
electronic-grade silicon (EGS).

The most widely used crystal-growing method in the semiconductor industry

is the Czochralski process, illustrated in Figure 5.2, in which a single crystal
ingot, called a boule, is pulled upward from a pool of molten silicon.
 The setup includes a furnace, a mechanical apparatus for pulling the
boule, a vacuum system, and supporting controls.
 The furnace consists of a crucible and heating system contained in a
vacuum chamber. The crucible is supported by a mechanism that
permits rotation during the crystal-pulling procedure.
 Chunks of EGS are placed in the crucible and heated to a temperature
slightly above the melting point of silicon: 1410CC.
 Heating is by induction or resistance, the latter being used for large
melt sizes.
 The molten silicon is doped (Table 5.1) prior to boule pulling to make
the crystal either p-type or n-type.
 To initiate crystal growing, a seed crystal of silicon is dipped into the
molten pool and then withdrawn upward under carefully controlled
conditions.
 At first the pulling rate (vertical velocity of the pulling apparatus) is
relatively rapid; this causes a single crystal of silicon to solidify against
the seed, forming a thin neck.
 The velocity is then reduced, causing the neck to grow into the desired
larger diameter of the boule while maintaining its single crystal
structure.
 In addition to pulling rate, rotation of the crucible and other process
parameters are used to control boule size.
 Single-crystal ingots of diameter = 200 mm or greater and up to 3 m
long are commonly produced for subsequent fabrication of
microelectronic chips.

It is important to avoid contamination of the silicon during crystal growing,

since contaminants, even in small amounts, can dramatically alter the
electrical properties of Si. To minimize unwanted reactions with silicon and
the introduction of contaminants at the elevated temperatures of crystal
growing, the procedure is carried out either in an inert gas (argon or helium)
or a vacuum. Choice of crucible material is also important; fused silica (SiO 2),
although not perfect for the application, represents the best available material
and is used almost exclusively. Gradual dissolution of the crucible introduces
oxygen as an unintentional impurity in the silicon boule. Unfortunately, the
level of oxygen in the melt increases during the process, leading to a variation
 in concentration of the impurity throughout the length and diameter of the
ingot.

FIGURE 5.2 The Czochralski process for growing single-crystal ingots of silicon: (a)
initial setup prior to start of crystal pulling, and (b) during crystal pulling to form the
boule.

Next, the crystal is sliced into individual wafers by using an inner diameter
blade.In this method a rotating blade with its cutting edge on the inner ring is
utilized. While the substrate depth needed for most electronic devices is no
more than several microns, wafers are typically cut to a thickness of about 0.5
mm. This thickness provides the necessary physical support for the
absorption of temperature variations, and the mechanical support needed
during subsequent fabrication. Finally, the waters must be polished and
cleaned to remove surface damage caused by the sawing process.

FIGURE 5.3 Grinding operations used in shaping the silicon ingot: (a) a
form of cylindrical grinding provides diameter and roundness control, and
(b) a flat ground on the cylinder.
Fabrication takes place over the entire wafer surface, and many identical
circuits are generated at the same time. Because of decreasing device sizes
and larger wafer diameters, thousands of individual circuits can be put on one
wafer. Once processing is finished, the wafer is sliced into individual chips,
each containing one complete integrated circuit.

FIGURE 5.4 Wafer slicing using a diamond abrasive cut-off saw.

FIGURE 5.5 Two of the steps in wafer preparation: (a)

contour grinding to round the wafer rim, and (b) surface
polishing
 Summarizing the preceding discussion, the production of silicon-based
integrated circuits consists of the following stages, portrayed in Figure 5.6:
(1) Silicon processing, in which sand is reduced to very pure silicon and
then shaped into wafers;
(2) IC fabrication, consisting of multiple processing steps that add, alter,
and remove thin layers in selected regions to form the electronic
devices; lithography is used to define the regions to be processed on
the surface of the wafer; and
(3) IC packaging, in which the wafer is tested, cut into individual dies (IC
chips), and the dies are encapsulated in an appropriate package.

FIGURE 5.6 Sequence of processing steps in the production of integrated circuits:

(1) pure silicon is formed from the molten state into an ingot and then sliced into
wafers; (2) fabrication of integrated circuits on the wafer surface; and (3) wafer is cut
into chips and packaged
5.5 FILM DEPOSITION
Films of many different types, particularly insulating and conducting films, are
used extensively in microelectronic device processing. Common depositing
films include polysilicon, silicon nitride, silicon dioxide, tungsten, titanium, and
aluminum. In some instances, the wafers serve merely as a mechanical
support on which custom epitaxial layers are grown. Epitaxy is defined as the
growth of a vapor deposit or electrodeposit in which the crystal orientation of
the deposit is directly related to the crystal orientation in the underlying
crystalline substrate. The advantages of processing on these deposited films,
instead of on the actual wafer surface, include fewer impurities (notably
carbon and oxygen), improved device performance, and the tailoring of
material properties, which cannot be done on the wafers themselves.

Some of the major functions of deposited films are masking, for diffusion or
implants, and protection of the semiconductor surface. In masking
applications, the film must effectively inhibit the passage of dopants and
concurrently display an ability to be etched into patterns of high resolution.
Upon completion of device fabrication, films are applied to protect the
underlying circuitry. Films used for masking and protection include silicon
dioxide, phosphosilicate glass (PSG), and silicon nitride. Each of these
materials has distinct advantages, and they are often used in combination.

Other films contain dopant impurities and are used as doping sources for the
underlying substrate. Conductive films are used primarily for device
interconnection. These films must have a low resistivity, be capable of
carrying large currents, and be suitable for connection to terminal packaging
leads with wire bonds. Generally, aluminum and copper are used for this
purpose. Increasing circuit complexity has required up to six levels of
conductive layers, which must all be separated by insulating films.

Films may be deposited using a number of techniques, which involve a

variety of pressures, temperatures, and vacuum systems, as described here:

a. One of the simplest and oldest methods is evaporation, which is used

primarily for depositing metal films. In this process the metal is heated
to its point of vaporization in a vacuum. Upon evaporation, the metal
forms a thin layer on the substrate surface. The heat for evaporation is
usually generated by a heating filament or electron beam.

b. Another method of metal deposition is sputtering and entails

bombarding a target with high-energy ions, usually argon (Ar +), in a
vacuum. Sputtering systems usually include a dc power source to
obtain the energized ions. As the ions impinge on the target, atoms
are knocked off and subsequently deposited on wafers mounted within
the system. Although some argon may be trapped within the film, this
technique results in very uniform coverage. Advances in this field
include using a radio-frequency power source (RF sputtering) and
introducing magnetic fields (magnetron sputtering).
 c. In one of the most common techniques, chemical vapor deposition
(CVD), film depositing is achieved by way of the reaction and/or
decomposition of gaseous compounds. Using this technique, silicon
dioxide is routinely deposited by the oxidation of silane or a
chlorosilane. Figure 5.7a shows a continuous CVD reactor that
operates at atmospheric pressure.

FIGURE 5.7 Schematic diagrams of (a) continuous, atmospheric-pressure CVD

reactor and (b) low-pressure CVD. Source: S. M. Sze.

A similar method that operates at lower pressures, referred to as low-

pressure chemical vapor deposition (LPCVD), is shown in Figure 5.7b.
Capable of coating hundreds of wafers at a time, this method results in a
much higher production rate than that of atmospheric-pressure CVD, and
provides superior film uniformity with less consumption of carrier gases. This
technique is commonly used for depositing polysilicon, silicon nitride, and
silicon dioxide.

d. Plasma-enhanced chemical vapor deposition (PECVD) involves

the process of wafers in an RF plasma containing the source gases.
This method has the advantage of maintaining low wafer temperature
during deposition.

Silicon epitaxy layers, in which the crystalline layer is formed using the
substrate as a seed crystal can be grown using a variety of methods. If the
silicon is deposited from the gaseous phase, the process is known as vapor-
phase epitaxy (VPE). In another variation, the heated substrate is brought
into contact with a liquid solution containing the material to be deposited
(liquid-phase epitaxy, or LPE).

Another high-vacuum process utilizes evaporation to produce a thermal beam

of molecules that are deposited on the heated substrate. This process, called
molecular beam epitaxy (MBE), results in a very high degree of purity. In
addition, since the films are grown one atomic layer at a time, it is possible to
have excellent control over doping profiles. This level of control is especially
important in gallium arsenide technology. Unfortunately, MBE suffers from
relatively low growth rates compared to other conventional film-deposition
techniques.
5.6 OXIDATION
Recall that the term oxidation refers to the growth of an oxide layer as a result
of the reaction of oxygen with the substrate material. Oxide films can also be
formed using the previously described deposition techniques. The thermally
grown oxides described in this section display a higher level of purity than
deposited oxides because they are grown directly from the high-quality
substrate. However, deposition methods must be used if the composition of
the desired film is different from that of the substrate material.

Silicon dioxide is the most widely used oxide in IC technology today, and its
excellent characteristics are one of the major reasons for the widespread use
of silicon. Aside from its effectiveness in dopant masking and device isolation,
silicon dioxide's most critical role is that of the "gate oxide" material.

Silicon surfaces have an extremely high affinity for oxygen, and a freshly
sawed slice of silicon will quickly grow a native oxide of 30 Å- 40 Å. Modern
IC technologies requires oxide thicknesses from the tens to the thousands of
angstroms.

a. Dry oxidation is a relatively simple process and is accomplished by

elevating the substrate temperature typically to 750 °C-1100 °C, in an
oxygen-rich environment.

As a layer of oxide forms, the oxidizing agents must be able to pass through
the oxide and reach the silicon surface where the actual reaction takes place.
Thus, an oxide layer does not continue to grow on top of itself, but rather it
grows from the silicon surface outward. Some of the silicon substrate is
consumed in the oxidation process (Figure 5.8).

FIGURE 5.8 Growth of silicon dioxide, showing consumption of

silicon. Source: S. M. Sze.

The ratio of oxide thickness to amount of silicon consumed is found to be

1:0.44. Therefore, to obtain an oxide layer 1000 A thick, roughly 440 A of
silicon will be consumed. This does not present a problem, as substrates are
always grown sufficiently thick.

One important effect of this consumption of silicon is the rearrangement of

dopants in the substrate near the interface. As different impurities have
 different segregation coefficients in silicon dioxide, some dopants deplete
away from the oxide interface while others pile up. Hence, processing
parameters must be adjusted to compensate for this effect.

b. Another oxidizing technique utilizes a water-vapor atmosphere as the

agent and is called, appropriately, wet oxidation. This method affects
a considerably higher growth rate than that of dry oxidation, but it
suffers from a lower oxide density and therefore a lower dielectric
strength. Common practice is to combine both dry and wet oxidation
methods, growing an oxide in a three-part layer: dry, wet, dry. This
approach combines the advantages of wet oxidation's much higher
growth rate and dry oxidation's high quality.

c. These oxidation methods are useful primarily for coating the entire
silicon surface with oxide, but it can also be necessary to oxidize only
certain portions of the substrate surface. The procedure of oxidizing
only certain areas is termed selective oxidation and uses silicon
nitride, which inhibits the passage of oxygen and water vapor. Thus,
through the masking of certain areas with silicon nitride, the silicon
under these areas remains unaffected but the uncovered areas are
oxidized.

5.7 LITHOGRAPHY
Lithography is the process by which the geometric patterns that define
devices are transferred from a reticle to the substrate surface. In current
practice, the lithographic process is applied to each microelectronic circuit
many times, each time using a different reticle to define the different areas of
the working devices. Typically designed at several thousand times their final
size, reticle patterns go through a series of reductions before being applied
permanently to a defect-free quartz plate.

Computer-aided design (CAD) has had a major impact on reticle design and
generation. Cleanliness is especially important in lithography, and many
manufacturers are now using robotics and specialized wafer-handling
apparatus in order to minimize dust and dirt contamination.

Once the film deposition process is completed and the desired reticle patterns
have been generated, the wafer is cleaned and coated with an organic
photoresist (PR), which is sensitive to ultraviolet (UV) light. Photoresist
layers of 0.5 µm-2.5 µm thick are obtained by applying the PR to the
substrate in liquid form and then spinning it at several thousand rpm for 30 or
60 seconds to give uniform coverage.

The next step in lithography is prebaking the wafer to remove the solvent
from the PR and harden it. This step is carried out on a hot plate that has
been heated to around 100 °C. The wafer is then aligned under the desired
reticle in a "stepper". In this crucial step, called registration, the reticle must
be aligned correctly with the previous layer on the wafer. Once the reticle is
aligned, it is stepped across the wafer and subjected to UV radiation. Upon
development and removal of the exposed PR, a duplicate of the reticle
pattern will appear in the PR layer.

As can be seen in Figure 5.9, the reticle can be a negative or a positive

image of the desired pattern. A positive reticle uses the UV radiation to break
down the chains in the organic film, so that these films are preferentially
removed by the developer. Positive masking has become dominant because
it complements dry etching.

FIGURE 5.9 Pattern transfer by lithography. Note that the mask in step
three can be a positive or negative image of the pattern. Source: After W. C.
Till and J. T. Luxon.

Following the exposure and development sequence, the wafer is post baked
to toughen and improve the adhesion of the remaining resist. In addition, a
deep UV treatment (baking the wafer to 150°C-200°C in ultraviolet light) can
be used to further strengthen the resist against high-energy implants and dry
etches. The underlying film not covered by the PR is then etched away or
implanted. Finally, the PR is stripped, by exposure to oxygen plasma (Figure
5.9). The lithography process is sometimes repeated as many as 25 times in
the fabrication of the most advanced ICs.

One of the major issues in the area of lithography is linewidth, which refers
to the width of the smallest feature unprintable on the silicon surface. As
circuit densities have escalated over the years, device sizes and features
have become smaller and smaller. Today, minimum commercially feasible
linewidths are between 0.15 µm and 0.25 µm, with considerable research
being done in regard to smaller linewidths of 0.12 µm.

As pattern resolution and device miniaturization have been limited by the

wavelength of the radiation source used, the need has arisen to move to
wavelengths shorter than those in the ultraviolet range, such as "deep" UV
wavelengths, electron beams, and x-rays. In these technologies, the
photoresist is replaced by a similar resist that is sensitive to a specific range
of shorter wavelengths.
5.8 ETCHING
Etching is the process by which entire films or particular sections of films are
removed and it plays an important role in the fabrication sequence. One of the
most important criteria in this process is selectivity, which refers to the ability
to etch one material without etching another.

In silicon technology, an etching process must effectively etch the silicon

dioxide layer with minimal removal of the underlying silicon or the resist
material. In addition, polysilicon and metals must be etched into high-
resolution lines with vertical wall profile and with minimal removal of the
underlying insulating film or photoresist. Typical etch rates range from
hundreds to several thousands of angstroms per minute, and selectivities
(defined as the ratio of the etch rates of the two films) can range from 1:1 to
100:1.

An older etching method requires the wafers to be immersed in a liquid

solution (wet etching). If silicon dioxide is to be etched, this solution usually
contains hydrofluoric acid, which etches silicon very slowly. The main
drawback of this etching technique is that it is isotropic, meaning that the
etch occurs equally in all directions. This condition leads to undercutting
(Figure 5.10a), which in turn prohibits the transfer of very high resolution
patterns.

FIGURE 5.10 Etching profiles resulting from (a) isotropic wet etching and
(b) anisotropic dry etching. Source: R. C. Jaeger.

Modern ICs are processed using, exclusively, dry etching which involves the
use of chemical reactants in a low-pressure system. In contrast to the wet
process, dry etching allows for a high degree of directionality, resulting in
highly anisotropic etch profiles (Figure 5.10b). Also, the dry process requires
only small amounts of reactant gases, whereas the aqueous solutions used in
the wet process need to be refreshed periodically.

The most widely used dry-etching techniques include

(a) sputter etching, which removes material by bombarding it with noble
gas ions, usually Ar+, and
(b) plasma etching, which utilizes a gaseous plasma of chlorine or
fluorine ions generated by RF excitation.
(c) Reactive ion etching combines these two processes, using both
momentum transfer and chemical reaction to remove material.
5.9 DIFFUSION AND ION IMPLANTATION
We should mention again that the electrical operation of microelectronic
devices depends on regions that have different doping types and
concentrations. The electrical character of these regions is altered through
the introduction of dopants into the substrate, which is accomplished by the
diffusion and ion implantation processes. This step in the fabrication se-
quence is repeated several times, since many different regions of
microelectronic devices must be defined.

In the diffusion process, the movement of atoms is a result of thermal

excitation. Dopants can be introduced to the substrate surface in the form of
a deposited film, or the substrate can be placed in a vapor containing the
dopant source. The process takes place at elevated temperature, usually
800°C - 1200°C. Dopant movement within the substrate is strictly a function
of temperature, time, and the diffusion coefficient (or diffusivity) of the dopant
species, as well as the type and quality of the substrate material.

Because of the nature of diffusion, the dopant concentration is very high at

the substrate surface and away from the surface, drops off sharply. To obtain
a more uniform concentration within the substrate, the wafer is heated further
to drive in the dopants in a process called drive-in diffusion. Diffusion,
desired or undesired will always occur at high temperatures; this fact is
always taken into account during subsequent processing steps. Although the
diffusion process is relatively inexpensive, it is highly isotropic.

FIGURE 5.11 Apparatus for ion implantation.

Ion implantation is a much more extensive process and requires specialized

equipment (Figure 5.11). Implantation is accomplished by accelerating the
ions through a high-voltage field of as much as one million electron-volts and
then choosing the desired dopant by means of a mass separator. In a manner
similar to that of cathode-ray tubes, the beam is swept across the wafer by
sets of deflection plates, thus ensuring uniform coverage of the substrate. The
complete implantation system must be operated in a vacuum.

The high-velocity impact of ions on the silicon surface damages the lattice
structure and results in lower electron mobilities. This condition is
undesirable, but the damage can be repaired by an annealing step, which
involves heating the substrate to relatively low temperatures, usually 400°C-
800°C for 15-30 minutes. This provides the energy that the silicon lattice
needs to rearrange and mend itself.

Another important function of annealing is driving in the implanted dopants.

Implantation alone imbeds the dopants less than half a micron below the
silicon surface; the annealing step enables the dopants to diffuse to a more
desirable depth of a few microns.
5.10 METALLIZATION AND TESTING
The preceding sections focused only on device fabrication. However,
generating a complete and functional integrated circuit requires these devices
to be interconnected. Interconnections are made by metals that exhibit low
electrical resistance and good adhesion to dielectric insulator surfaces.
Aluminum and aluminum-copper alloys remain the most commonly used
materials for this purpose in VLSI technology today.

However, as device dimensions continue to shrink, electromigration has

become more of a concern with aluminum interconnects. Electromigration is
the process by which aluminum atoms are physically moved by the impact of
drifting electrons under high current conditions. In extreme cases, this can
lead to severed and/or shorted metal lines. Solutions to the electromigration
problem include

(a) the addition of sandwiched metal layers such as tungsten and

titanium, and more recently,
(b) the usage of pure copper, which displays lower resistivity and
significantly better electromigration performance than
aluminum.

Metals are deposited using standard deposition techniques, and

interconnection patterns are generated through lithographic and etching
processes as previously described. Modern ICs typically have one to six
layers of metallization, in which case each layer of metal is insulated by a
dielectric.

Planarization (producing a planar surface) of these inter-layer dielectrics is

critical in the reduction of metal shorts and of the linewidth variation of the
interconnect. A common method used to achieve a planar surface is a
uniform oxide etches process that smoothens out the "peaks" and "valleys" of
the dielectric layer.
Example 5.1 : Processing of a p-Type Region in n-Type Silicon.

Assume that we wish to create a p-type region within a sample of n-type silicon.
Draw cross-sections of the sample at each processing step in order to accomplish
this. (See Figure 5.12)

Solution: This simple device is known as a pn junction diode, and the physics of its
operation are the foundation for most semiconductor devices.

FIGURE 5.12 Processing of a p-Type Region in n-Type Silicon

However, today's standard for planarizing high density interconnects and has
quickly become chemical mechanical polishing (CMP). This process entails
physically polishing the wafer surface in as manner similar to that by which a
disc or belt sander flattens the ridges in a piece of wood. A typical CMP
process combines an abrasive medium with a polishing compound, or slurry,
and can polish a wafer to within 300 angstroms of being perfectly flat.

Layers of metal are connected together by vias; access to the devices on the
substrate is achieved through contacts (Figure 5.13).

(a) (b)

FIGURE 5.13 (a) Scanning electron microscope photograph of a two-level

metal interconnect. Note the varying surface topography. Source: National
Semiconductor Corporation, (b) Schematic drawing of a two-level metal
interconnect structure. Source: R. C. Jaeger.

In recent years, as devices have become smaller and faster, the size and
speed of some chips have become limited by the metallization itself.

Wafer processing is complete upon application of a passivation layer, usually

silicon nitride (Si3N4). The silicon nitride acts as an ion barrier for sodium ions
and also provides excellent scratch resistance.

The next step is to test each of the individual circuits on the wafer. Each chip,
also known as a die, is tested by a computer-controlled probe platform that
contains needlelike probes which access the bonding pads on the die. The
platform steps across the wafer, and tests whether each circuit functions
properly with computer-generated timing waveforms. If a defective chip is
encountered, it is marked with a drop of ink.

After this wafer-level testing is complete, each die is separated from the
wafer. Diamond sawing is a commonly-used separation technique and results
in very straight edges, with minimal chipping and cracking damage. The chips
are then sorted; the functional dies are sent on for packaging, and the inked
dies are discarded.
5.11 BONDING AND PACKAGING

The working dice must be attached to a more rugged foundation to ensure

reliability. One simple method is to fasten a die to its packaging material with
an epoxy cement. Another method makes use of a eutectic bond, which is
made by heating metal-alloy systems. One widely used mixture is 96.4% gold
and 3.6% silicon, and has a eutectic point at 370 °C.

Once the chip has been attached to its substrate, it must be electrically
connected to the package leads. This is accomplished by wire-bonding very
thin (25 µm diameter) gold wires from the package leads to bonding pads
located around the perimeter or down the center of the die (Figure 5.14 a).

FIGURE 5.14 (a) SEM photograph of wire bonds connecting package leads (left-
hand side) to die bonding pads, (b) and (c) Detailed views of (a). Source: Courtesy
of Micron Technology, Inc.

The bonding pads on the die are typically drawn at 75 µm -100 µm per side,
and the bond wires are attached using thermocompression, ultrasonic, or
thermosonic techniques (Figures 5.14 b and c).

The connected circuit is now ready for final packaging. The packaging
process largely determines the overall cost of each completed IC, since the
circuits are mass produced on the wafer but then packaged individually.
Packages are available in a variety of styles; the appropriate one must reflect
operating requirements.

Consideration of a circuit's package includes chip size, number of external

leads, operating environment, heat dissipation, and power requirements. For
example, ICs that are used for military and industrial applications require
packages of particularly high strength, toughness, and temperature
resistance.

An older style of packaging is the dual-in-line package (DIP), shown

schematically in Figure 5.15a. Characterized by low cost and ease of
handling, DIP packages are made of thermoplastic, epoxy, or ceramic and
can have from 2 to 500 external leads. Ceramic packages are designed for
use over a broader temperature range and in high-reliability and military
applications, thus costing considerably more than plastic packages.
Figure 5.15b shows a flat ceramic package in which the package and all the
leads are in the same plane. This package style does not offer the ease of
handling or the modular design of the DIP package. For this reason, it is
usually permanently affixed to a multiple-level circuit board in which the low
profile of the flat pack is necessary.

FIGURE 5.15 Schematic illustrations of different IC packages: (a) dual-in-

line (DIP), and (b) ceramic flat pack, and (c) common surface mount
configuration. Sources: R. C. Jaeger and A. B. Glaser; G. E. Subak-Sharpe.

Surface mount packages have become the standard for today's integrated
circuits. As can be seen in Figure 5.15, the main difference in the designs is
in the shape of the connectors.

The DIP connection to the surface board is via prongs which are inserted into
corresponding holes, while a surface mount is soldered onto specially
fabricated pad or land designs. A land is a raised solder platform for
component interconnections in a printed circuit board. Package size and
layouts are selected from standard patterns, and usually require adhesive
bonding of the package to the board, followed by wave soldering of the
connections.

After the chip has been sealed in the package, it undergoes final testing.
Because one of the main purposes of packaging is isolation from the
environment, testing at this stage usually involves heat, humidity, mechanical
shock, corrosion, and vibration. Destructive tests are also performed to
investigate the effectiveness of sealing.
5.12 SUMMARY
In this unit we have studied that
1. The microelectronics industry is developing rapidly. The possibilities
for new deviceconcepts and circuit designs appear to be endless. The
fabrication of microelectronic devices and integrated circuits involves
many different types of processes, most of which have been adapted
from those of other fields of manufacturing.
2. After bare wafer have been prepared, they undergo repeated
oxidation or film deposition, lithographic, and etching step to open
windows in the oxide layer in order to access the silicon substrate.
3. After each of these processing cycles is complete, dopants are
introduced into various regions of the silicon structure through
diffusion and ion implantation.
4. After all doping regions have been established, devices are
interconnected by multiple metal layers, and the completed circuit is
packaged and made accessible through electrical connections.
5. Finally, the packaged circuit and other discrete devices are soldered
to a printed circuit board for final installation.

5.13 SELF TEST

1. Define IC
2. What are dopants?
3. Arrange the fabrication sequence of IC
4. Explain the three main stages in production of silicon-based integrated
circuits.
5. State three types of oxidation.
6. What is lithography?
7. What is etching?
8. Distinguish diffusion and ion implantation.
9. Compare silicon, germanium and gallium arsenide.
10. Define electromigration.

5.14 KEY TERM

Integrated Circuit
Planarization
Metallization
5.15 REFERENCES

Serope Kalpakjian, Steven R. Schmidt (2001). Manufacturing

Engineering and Technology, (4th Edition), state: Prentice Hall.
Mikell P. Groover (2002). Fundamentals of Modern Manufacturing
Materials, Processes, and Systems, (2nd Edition), state: John Wiley &
Son, Inc.
John A. Schey, (year). Introduction to Manufacturing Processes, (3rd Edition),
state: Mc Graw Hill.
E. Paul Degarmo, J T. Black, Ronald A. Kohser (2003). Materials and
Processes in Manufacturing, (9th Edition), state: John Wiley & Son, Inc.
5.16 ANSWER

1. Define IC
An integrated circuit (IC) is a collection of electronic devices
such as transistors, diodes, and resistors that have been
fabricated and electrically intra-connected onto a small flat chip
of semiconductor material.

2. What are dopants?

Dopants are impurity atoms, have either one more valence
electron (n-type or negative dopant) or one less valence electron
(p-type or positive dopant) than the atoms in the semiconductor
lattice.
n – type - donor (extra one valence electron) / group V
(phosphorous)
p – type - acceptor (less one valence electron) / group III
(boron)

3. Arrange the fabrication sequence of IC

4. Explain the three main stages in production of silicon-based integrated
circuits.
The production of silicon-based integrated circuits consists of
the following stages:
(1) Silicon processing, in which sand is reduced to very pure
silicon and then shaped into wafers;
(2) IC fabrication, consisting of multiple processing steps that
add, alter, and remove thin layers in selected regions to
form the electronic devices; lithography is used to define
the regions to be processed on the surface of the wafer;
and
(3) IC packaging, in which the wafer is tested, cut into
individual dies (IC chips), and the dies are encapsulated in
an appropriate package.

2. State three types of oxidation.

 Dry oxidation
 Wet oxidation
 Selective oxidation

3. What is lithography?
Lithography is the process by which the geometric patterns that
define devices are transferred from a reticle to the substrate
surface.

4. What is etching?
Etching is the process by which entire films or particular
sections of films are removed and it plays an important role in
the fabrication sequence.

5. Distinguish diffusion and ion implantation.

In the diffusion process, the movement of atoms is a result of
thermal excitation. Dopants can be introduced to the substrate
surface in the form of a deposited film, or the substrate can be
placed in a vapor containing the dopant source. The process
takes place at elevated temperature, usually 800°C - 1200°C.
Dopant movement within the substrate is strictly a function of
temperature, time, and the diffusion coefficient (or diffusivity) of
the dopant species, as well as the type and quality of the
substrate material.

Ion implantation is a much more extensive process and requires

specialized equipment. Implantation is accomplished by
accelerating the ions through a high-voltage field of as much as
one million electron-volts and then choosing the desired dopant
by means of a mass separator. In a manner similar to that of
cathode-ray tubes, the beam is swept across the wafer by sets of
deflection plates, thus ensuring uniform coverage of the
substrate. The complete implantation system must be operated
in a vacuum.
 The high-velocity impact of ions on the silicon surface damages
the lattice structure and results in lower electron mobilities. This
condition is undesirable, but the damage can be repaired by an
annealing step, which involves heating the substrate to relatively
low temperatures, usually 400°C-800°C for 15-30 minutes. This
provides the energy that the silicon lattice needs to rearrange
and mend itself.

9. Compare silicon, germanium and gallium arsenide.

Although the earliest electronic devices were fabricated on
germanium, silicon has become the industry standard. The
abundance of alternative forms of silicon is second only to that
of oxygen, making it economically attractive. Silicon's main
advantage over germanium is its large energy gap (1.1 eV)
compared to that of germanium (0.66 eV). This energy gap allows
silicon-based devices to operate at temperatures about 150 °C
higher than devices fabricated on germanium (about 100 °C).

Silicon's important processing advantage is that its oxide (silicon

dioxide) is an excellent insulator and can be used for both
isolation and passivation purposes. Conversely, germanium
oxide is water soluble and unsuitable for electronic devices.

However, silicon has some limitations, which have encouraged

the developments compound semiconductors, specifically
gallium arsenide. Its major advantage over silicon is its ability to
emit light, allowing fabrication of devices such as lasers and
light-emitting diodes (LEDs). It also has a larger energy gap (1.43
eV) and therefore a higher maximum operating temperature
(about 200 °C).

Devices fabricated on gallium arsenide also have much higher

operating speeds than those fabricated on silicon. Some of
gallium arsenide's disadvantages include its considerably higher
cost, greater processing complications, and the difficulty of
growing high-quality oxide layers.

10. Define electromigration.

Electromigration is the process by which aluminum atoms are
physically moved by the impact of drifting electrons under high
current conditions.