ACPL-351J: Data Sheet

Data Sheet
ACPL-351J
5.0 Amp Output Current IGBT and SiC/GaN
MOSFET Gate Drive Optocoupler with
Overcurrent Sensing and FAULT Signal
Description Features
The Broadcom® ACPL-351J is a 5A intelligent gate drive  ACPL-351J – 5.0 A maximum peak output current
optocoupler. The high peak output current and wide  150-ns maximum propagation delay
operating voltage range make it ideal for driving IGBT or  Dual output drive to control turning on and off time
SiC/GaN MOSFET directly in motor control and inverter  Overcurrent detection with configurable "soft" shutdown
applications.  FAULT signal for external isolated feedback
The device features fast propagation delay with excellent  Under voltage lockout (UVLO) with hysteresis
timing skew performance. It provides IGBT/MOSFET with  100 kV/µs minimum common mode rejection (CMR) at
overcurrent protection and FAULT signal for external VCM = 1500V
isolated feedback. This gate drive optocoupler comes in a  15V to 30V wide operating VDD2 range
compact, surface-mountable SO-16 package. It provides  –40°C to 105°C industrial temperature range
reinforced insulation certified for safety regulatory IEC/EN/  8.3-mm creepage and clearance
DIN, UL, and CSA.  Safety approval:
– UL Recognized 5000 VRMS for 1 minute
CAUTION! Take normal static precautions in handling and
– CSA
assembly of this component to prevent
– IEC/EN/DIN EN 60747-5-5 VIORM = 1414 VPEAK
damage, degradation, or both that may be
induced by ESD. The components featured in Applications
this data sheet are not to be used in military or
aerospace applications or environments.  IGBT and SiC/GaN MOSFET gate drives
 Industrial drives and inverters
 Renewable energy inverters
 Switching power supplies
Broadcom ACPL-351J-DS100
October 22, 2019
5.0 Amp Output Current IGBT and SiC/GaN MOSFET Gate Drive Optocoupler with Over-
ACPL-351J Data Sheet current Sensing and FAULT Signal
Functional Diagram
12
VDD2
UVLO
7 D
ANODE R
VOUTP/CLAMP
I Drive Logic 11
6, 8 Clamp
CATHODE V & Overlap
Logic
LED1 Protection
E 9
R VS
VOUTN
10
SHIELD
15
FAULT
16
VSS2
14
OC
DESAT
13
SS
2
Pin Description
1 NC VSS2 16
2 NC FAULT 15
3 NC OC 14
4 NC SS 13
5 NC VDD2 12
6 CATHODE VOUTP/CLAMP 11
7 ANODE VOUTN 10
8 CATHODE VS 9
Pin Symbol Description

1 NC No connection
2 NC No connection
3 NC No connection
4 NC No connection
5 NC No connection
6 CATHODE Input LED cathode
7 ANODE Input LED anode
8 CATHODE Input LED Cathode
9 VS Common (IGBT emitter or MOSFET source) output supply voltage.
10 VOUTN Driver output to turn off IGBT or MOSFET gate
11 VOUTP/CLAMP Driver output to turn on IGBT or MOSFET gate/Miller clamp
12 VDD2 Positive output power supply
13 SS Soft shutdown
14 OC Overcurrent (OC) input pin. When the voltage on the OC pin exceeds an internal reference voltage
of 9V while the IGBT/MOSFET is on, the FAULT output is changed from logic high to low state.
15 FAULT OC fault signal for external isolated feedback
16 VSS2 Negative output power supply
3
Ordering Information
ACPL-351J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Option
IEC/EN/DIN
Part Number RoHS Compliant Package Surface Mount Tape and Reel EN 60747-5-5 Quantity
ACPL-351J -000E SO-16 X X 45 per tube
-500E X X X 850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option column
to form an order entry.
Example:
ACPL-351J-500E to order a product of SO-16 surface mount package in tape and reel packaging with IEC/EN/DIN
EN 60747-5-5 Safety Approval in RoHS compliant.
Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information.
ACPL-351J 16-Lead Surface Mount Package
·
A 351J
YYWW
EEE
Lot ID
NOTE:
1. Dimensions are in inches (millimeters).
2. Floating lead protrusion is 0.25 mm (10 mils) maximum.
3. Initial and continued variation in the color of the ACPL-351J's white mold compound is normal and does not
affect device performance or reliability.
4
Recommended Pb-Free IR Profile

Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Use non-halide flux.
Regulatory Information
The ACPL-351J is approved by the following organizations.
IEC/EN/DIN EN 60747-5-5 Maximum working insulation voltage VIORM = 1414 VPEAK.

UL Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361.
CSA Approval under CSA Component Acceptance Notice #5, File CA 88324.
Table 1: IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa
Description Symbol Characteristic Units

Installation Classification per DIN VDE 0110/39, Table 1
For rated mains voltage ≤ 150 Vrms I - IV
For rated mains voltage ≤ 1000 Vrms I - III
Climatic Classification 40/105/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 1414 VPEAK
Input to Output Test Voltage, Method bb VPR 2652 VPEAK

VIORM × 1.875 = VPR, 100% Production Test with tm = 1 second, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*D VPR 2262 VPEAK
VIORM × 1.6 = VPR, Type and Sample Test, tm = 10 seconds, Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 seconds) VIOTM 8000 VPEAK
Safety-Limiting Values – maximum values allowed in the event of a failure
Case Temperature TS 175 °C
Input Current IS, INPUT 400 mA
Output Power PS, OUTPUT 1200 mW
Insulation Resistance at TS, VIO = 500V RS >109 Ω
a. Isolation characteristics are guaranteed only within the safety maximum ratings that must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
b. Refer to IEC/EN/DIN EN 60747-5-5 Optoisolator Safety Standard section of the Broadcom Regulatory Guide to Isolation Circuits,
AV02-2041EN for a detailed description of Method a and Method b partial discharge test profiles.
5
Table 2: Insulation and Safety Related Specifications
Parameter Symbol ACPL-351J Units Conditions

Minimum External Air Gap L(101) 8.3 mm Measured from input terminals to output terminals,
(Clearance) shortest distance through air.
Minimum External Tracking L(102) 8.3 mm Measured from input terminals to output terminals,
(Creepage) shortest distance path along body.
Minimum Internal Plastic Gap 0.5 mm Through insulation distance conductor to conductor,
(Internal Clearance) usually the straight line distance thickness between the
emitter and the detector.
Tracking Resistance CTI >175 V DIN IEC 112/VDE 0303 Part 1.
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1).
NOTE: All Broadcom data sheets report the creepage and clearance inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equipment designer when determining the circuit insulation
requirements. However, when mounted on a printed circuit board, minimum creepage and clearance requirements
must be met as specified for individual equipment standards. For creepage, the shortest distance path along the
surface of a printed circuit board between the solder fillets of the input and output leads must be considered (the
recommended land pattern does not necessarily meet the minimum creepage of the device). There are
recommended techniques, such as grooves and ribs, that may be used on a printed circuit board to achieve the
desired creepage and clearances. The creepage and clearance distances will also change depending on factors.
such as pollution degree and insulation level.
6
Table 3: Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Notes

Storage Temperature TS –55 125 °C
Operating Temperature TA –40 105 °C
Output IC Junction Temperature TJ — 125 °C
Average Input Current IF(AVG) — 25 mA a
Peak Transient Input Current IF(TRAN) — 1.0 A

(<1 µs pulse width, 300 pps)
Reverse Input Voltage VR — 5 V
"High" Peak Output Current IOH(PEAK) — 5 A b
"Low" Peak Output Current IOL(PEAK) — 5 A b
Total Output Supply Voltage (VDD2 – VSS2) –0.5 35 V

Negative Output Supply Voltage (VS – VSS2) –0.5 17 V
Positive Output Supply Voltage (VDD2 – VS) –0.5 35 – (VS – VSS2) V
Input Current (Rise/Fall Time) tr(IN)/tf(IN) — 500 ns
High Side Pull Up Voltage VOUTP VSS2 – 0.5 VDD2 + 0.5 V
Low Side Pull Down Voltage VOUTN VSS2 – 0.5 VDD2 + 0.5 V
Overcurrent Pin Voltage VOC VS – 0.5 VDD2 + 0.5 V
Peak Clamp Sinking Current ICLAMP — 3 A
Miller Clamp Pin Voltage VCLAMP VSS2 – 0.5 VDD2 + 0.5 V
FAULT Pin Voltage VFAULT — VDD2 + 0.5 V
Output IC Power Dissipation PO — 600 mW c
Input LED Power Dissipation PI — 110 mW d
a. Derate linearly above 70°C free-air temperature at a rate of 0.3 mA/ °C.
b. Maximum pulse width = 10 µs.The output must be limited to –5.0A/5.0A of the peak current by external resistors. See Supply and Ground
Planes Layout and Loading Conditions to prevent output noise at 5A rated current.
c. Derate linearly above 95°C free-air temperature at a rate of 20 mW/ °C.
d. Derate linearly above 95°C free-air temperature at a rate of 3.7 mW/ °C. The maximum LED junction temperature should not exceed 125°C.
Table 4: Recommended Operating Conditions
Parameter Symbol Min. Max. Units Notes

Operating Temperature TA –40 105 °C
Total Output Supply Voltage (VDD2 – VSS2) 15 30 V
Negative Output Supply Voltage (VS – VSS2) 0 15 V
Positive Output Supply Voltage (VDD2 – VS) 15 30 – (VS – VSS2) V
Input Current (ON) IF(ON) 8 12 mA
Input Voltage (OFF) VF(OFF) –3.6 0.8 V
FAULT Pin Voltage VFAULT — 30 V
7
In Table 5, all typical values at TA = 25°C, VDD2 – VS = 15V, VS – VSS2 = 15V; all minimum and maximum specifications are
at recommended operating conditions, unless otherwise noted.
Table 5: Electrical Specifications (DC)
Parameter Symbol Min. Typ. Max. Units Test Conditions Figure Notes
VOUTP High Level Peak IOH –4.5 9.0 — A VDD2 – VOUTP = 15V 3 a
Output Current
VOUTN Low Level Peak IOL 4.5 7.0 — A VOUTN – VSS2 = 15V 4 a
Output Current
VOUTP Output PMOS ROUTP 0.4 0.7 1.5 Ω IOP = –4.5A, 5 a
RDS(ON) IF = 8 mA
VOUTN Output NMOS ROUTN 0.3 0.6 1.2 Ω ION = 4.5A, VF = 0V 6 a
RDS(ON)
VOUTP Output Voltage VOH VDD2 – 0.60 VDD2 – 0.06 — V IOP = –100 mA, 1 b, c
IF = 8 mA
VOUTN Output Voltage VOL — VSS2 + 0.04 VSS2 + 0.60 V ION = 100 mA, 2
VF = 0V
Clamp Threshold Voltage VTH_CLAMP — 2 3 V
Clamp Low Level Sinking ICLAMP 2 2.5 — A VCLAMP = 7
Current VSS2 + 2.5V
Clamp Output Transistor RDS,CLAMP — 0.9 2 Ω ICLAMP = 2.5A
RDS(ON)
SS Pull Down Current IOSS 70 140 — mA SS – VSS2 ≥15V, 8
IF = 8 mA, OC = Open
SS RDSON ROUTSS — 16 40 Ω ISS = 70 mA,
IF =8 mA, OC = Open
High Level Output Supply IDD2H — 4.6 7.5 mA IF = 8 mA, No Load 9
Current (VDD2)
Low Level Output Supply IDD2L — 3.7 6.5 mA VF = 0V, No Load, 9
Current (VDD2)
High Level Output Supply ISS2H –2.2 –1.7 — mA IF = 8 mA, No Load, 10
Current (VSS2)
Low Level Output Supply ISS2L –1.2 –0.8 — mA VF = 0V, No Load, 10
Current (VSS2)
Input Threshold Current IFLH 0.5 2 6.5 mA 11, 12
Low to High
Input Threshold Voltage VFHL 0.8 — — V
High to Low
Input Forward Voltage VF 1.2 1.55 1.95 V IF = 8 mA
Temperature Coefficient of VF/TA — –1.7 — mV/°C IF = 8 mA
Input Forward Voltage
Input Reverse Breakdown BVR 5 — — V IR = 100 µA
Voltage
Input Capacitance CIN — 70 — pF f = 1 MHz, VF = 0V
8
Table 5: Electrical Specifications (DC) (Continued)
UVLO Threshold, VUVLO+ 12 12.9 13.5 V IF = 8 mA, b, c, d
VDD2 – VS VOUTP – VE > 5V
VUVLO- 11 11.8 12.5 V IF = 8 mA, b, c, e
VOUTP – VE < 5V
UVLO Hysteresis, VUVLO+ – VUVLO- 0.5 1 — V
VDD2 – VS
OC Sensing Voltage VOC 8.5 9 9.5 V VDD2 – VS > VUVLO+ 13 c
Threshold
Blanking Capacitor ICHG 0.85 1 1.15 mA VOC = 2V 14 c, f
Charging Current
OC Low Voltage when VDSCHG — 1.1 2 V IDSCHG = 20 mA c, f
Blanking Capacitor
Discharge
Low Level FAULT Output VFAULTL — 0.7 1.5 V IFAULT = 10 mA
Voltage
High Level FAULT IFAULTH — 2 20 µA VFAULT = 30V
Leakage Current
a. Output is sourced at –4.5A /4.5A with a maximum pulse width = 10 µs.
b. 15V is the recommended minimum operating positive supply voltage (VDD2 – VS) to ensure adequate margin in excess of the maximum
VUVLO+ threshold of 13.5V. For high level output voltage testing, VOUTP is measured with a 50-µs pulse load current. When driving capacitive
loads, VOUTP will approach VDD2 as IOUTP approaches zero units.
c. When the system is out of UVLO (VDD2 – VS > VUVLO+), the OC detection feature of the ACPL-351J will be the primary source of IGBT/
MOSFET protection. UVLO must be unlocked to ensure that OC is functional. When VDD2 exceeds VUVLO+ threshold, OC will remain
functional until VDD2 is below the VUVLO- threshold. The OC detection and UVLO features of the ACPL-351J work in conjunction to ensure
constant IGBT / MOSFET protection.
d. This is the "increasing" (that is, turn-on or "positive going" direction) of VDD2 – VS.
e. This is the "decreasing" (that is, turn-off or "negative going" direction) of VDD2 – VS.
f. See OC Fault Detection Blanking Time for further details.
In Table 6, all typical values at TA = 25°C, VDD2 – VS = 15V, VS – VSS2 = 15V; all minimum and maximum specifications are
at recommended operating conditions, unless otherwise noted.
Table 6: Switching Specifications (AC)
Propagation Delay Time to High VOUTP tPLH 40 100 150 ns RGP = 5Ω, 15, 16, a
Output Level RGN = 5Ω , 21
Propagation Delay Time to Low VOUTN tPHL 40 90 150 ns CG = 5 nF, f = 20 kHz, b
Output Level Duty Cycle = 50%,
Pulse Width Distortion PWD –50 10 50 ns IF = 8 mA c
Propagation Delay Difference Between PDD –75 — 75 ns d

Any Two Parts (tPLH – tPHL)
Propagation Delay Skew tPSK — — 60 ns e
9
Table 6: Switching Specifications (AC) (Continued)
10% to 90% Rise Time on VOUTP tR — 37 — ns RGP = 5Ω,
90% to 10% Fall Time on VOUTN tF — 30 — ns RGN = 5Ω,
CG = 2 nF, f = 20 kHz,
Duty Cycle = 50%,
IF = 8 mA
OC Blanking Time tOC(BLANKING) — 0.75 1 µs RGP = 5Ω, 20 f
OC Detection to 90% VGATE Delay tOC(90%) — 0.13 — µs RGN = 5Ω, 20 g

CG = 5 nF, f = 100 Hz,
OC Detection to VGATE = 2V Delay tOC(2V) — 2.5 — µs 20 h
Duty Cycle = 50%,
OC Detection to OC Pull Low tOC(LOW) — 0.25 — µs IF = 8 mA, 20 i
Propagation Delay RSS = 133Ω,
OC Detection to SS Pull Low tSS(LOW) — 0.15 0.8 µs RFS = 1 kΩ, 17, 20 j
Propagation Delay CFS = 470 pF
OC Detection to Low Level FAULT tOC(FAULT) — 180 200 ns 20 k
Signal Delay
Output Mute Time Due to Overcurrent tOC(MUTE) 2 3 4 ms 18, 20 l
Time Input Kept Low Before Fault Reset tOC(RESET) 2 3 4 ms 18, 20 m

to High
VDD2 UVLO to VOUTP High Delay tUVLO_ON — 3 — µs 22 n
VDD2 UVLO to VOUTN Low Delay tUVLO_OFF — 1.5 — µs 22 o
Output High Level Common Mode |CMH| 100 — — kV/µs TA = 25°C, IF = 8 mA, p, q
Transient Immunity VCM = 1500 V,
Output Low Level Common Mode |CML| 100 — — kV/µs TA = 25°C, VF = 0V, q, r
Transient Immunity VCM = 1500 V
a. tPLH is defined as propagation delay from 50% of LED input IF, to 50% of VOUTP high level output.
b. tPHL is defined as propagation delay from 50% of LED input IF, to 50% of VOUTN low level output.
c. Pulse width distortion (PWD) is defined as |tPHL – tPLH| for any given unit.
d. Propagation delay difference (PDD) is the difference between tPHL and tPLH between any two units under the same test condition.
e. Propagation delay skew (tPSK) is the difference in tPHL or tPLH between any two units under the same test condition.
f. The internal delay time to respond to an OC fault condition without any external blanking capacitor.
g. The amount of time from when the OC threshold is exceeded to 90% of VGATE at the mentioned test conditions.
h. The amount of time from when the OC threshold is exceeded to VGATE at 2V at the mentioned test conditions.
i. The amount of time from when the OC threshold is exceeded to 10% of OC low voltage.
j. The amount of time from when the OC threshold is exceeded to 10% of SS (Soft Shut) low voltage.
k. The amount of time from when the OC threshold is exceeded to FAULT output low.
l. The amount of time when the OC threshold is exceeded, output is muted to LED input.
m. The amount of time when the OC mute time is expired, the LED input must be kept low for FAULT status to return to high.
n. The delay time when VDD2 exceeds the UVLO+ threshold to 50% of the VOUTP high level output.
o. The delay time when VDD2 exceeds the UVLO- threshold to 50% of the VOUTN low level output.
p. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (that is, VDD2 – VOUTP < 1.0V or FAULT > 2V). VDD2 must be higher than VUVLO+.
q. Split resistor network in the ratio 3:1 with 324Ω at the anode and 107Ω at the cathode.
r. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (that is, VOUTN – VSS2 < 1.0V or FAULT > 2 V). VDD2 must be higher than VUVLO+.
10
Table 7: Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary Withstand VISO 5000 — VRMS RH < 50%, t = 1 min.ute, a, b, c
Voltage TA = 25°C
Input-Output Resistance RI-O — > 109 — Ω VI-O = 500V c
Input-Output Capacitance CI-O — 1.3 — pF freq = 1 MHz

Thermal Coefficient Between: — °C/W d
LED and Output IC AEO 33.1 — —

LED and Ambient AEA 176.1 — —
Output IC and Ambient AOA 76.7 — —
a. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is
performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic
Table, if applicable.
b. The input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or the IEC/EN/DIN EN 60747-5-5 Insulation
Characteristics Table.
c. The device is considered a two-terminal device: Pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
d. For further details, see Thermal Calculation.
11
Figure 1: VOH vs. Temperature Figure 2: VOL vs. Temperature
29.96 0.06
VOH HIGH OUTPUT VOLTAGE DROP
VOL - LOW OUTPUT VOLTAGE - V

29.955 I F = 8 mA 0.05
I OUTP = -100 mA
V DD2 - V S = 15 V
29.95 0.04
V S - V SS2 = 15 V
29.945 0.03
-V
VF = 0 V
29.94 0.02 IOUTN= 100 mA
VDD2 - VS = 15 V
29.935 0.01 VS - VSS2 = 15 V
29.93 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
TA - TEMPERATURE - OC TA - TEMPERATURE - OC
Figure 3: IOH vs. VOH Figure 4: IOL vs. VOL
0 2 4 6 8 10 12 14 8
0 IOL - OUTPUT LOW CURRENT - A
7
IOH - OUTPUT HIGH CURRENT - A
-2 IF = 8 mA 6
TA = 25ºC
VDD2 - VS = 15 V 5
-4 VS - VSS2 = 15 V
4
-6 3 VF = 0 V
TA = 25ºC
2 VDD2 - VS = 15 V
-8 VS - VSS2 = 15 V
1
-10
0
0 2 4 6 8 10 12 14
-12
VOH - OUTPUT HIGH VOLTAGE - V VOL - OUTPUT LOW VOLTAGE - V
Figure 5: ROUTP vs. Temperature Figure 6: ROUTN vs. Temperature
0.9 0.8
ROUTN - OUTPUT NMOS RDS(ON)-
ROUTP - OUTPUT PMOS RDS(ON)-
0.8 0.7
0.7 0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3 IF = 8 mA VF = 0 V
IOUTP = -4.5 A 0.2 IOUTN = -4.5 A
0.2 VDD2 - VS = 15 V VDD2 - VS = 15 V
VS - VSS2 = 15 V 0.1 VS - VSS2 = 15 V
0.1
0 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
12
Figure 7: ICLAMP vs. Temperature Figure 8: IOSS vs. VOSS
3.5 0.3
ICLAMP - CLAMP SINKING CURRENT-
IOSS - SS PULL DOWN CURRENT - A

3
0.25
2.5
0.2
2
0.15
A
1.5 VF = 0 V IF = 8 mA
VCLAMP = VSS + 2.5 V TA = 25ºC
VDD2 - VS = 15 V 0.1
1 VDD2 - VS = 15 V
VS - VSS2 = 15 V VS - VSS2 = 15 V
0.5 0.05
0
0
-40 -20 0 20 40 60 80 100
0 2 4 6 8 10 12 14
TA - TEMPERATURE - OC
VOSS - SS OUTPUT LOW VOLTAGE - V
Figure 9: IDD2H/IDD2L vs. Temperature Figure 10: ISS2H/ISS2L vs. Temperature
7 -40 -20 0 20 40 60 80 100

IDD2H/IDD2L - VDD2 OUTPUT SUPPLY
0
6
ISS2H/ISS2L - VSS2 OUTPUT SUPPLY
-0.2
5 -0.4
CURRENT - mA
-0.6
CURRENT - mA
4
-0.8
3 IDD2L
-1 IF = 8 mA IDD2H ISS2L
IDD2H VF = 0 V IDD2L
2 IF = 8 mA IDD2H -1.2 ISS2H
VDD2 - VS = 15 V
VF = 0 V IDD2L -1.4 VS - VSS2 = 15 V
1 VDD2 - VS = 15 V
VS - VSS2 = 15 V -1.6
0 -1.8
-40 -20 0 20 40 60 80 100
-2
Figure 11: VOUTP/VOUTN vs. IFLH Figure 12: IFLH vs. Temperature
35 3
VOUTP/VOUTN - OUTPUT VOLTAGE - V
IFLH - INPUT THRESHOLD CURRENT
30
2.5
25
2
20
- mA
1.5
15
TA = 25ºC
VDD2 - VS = 15 V VDD2 - VS = 15 V
1
10 VS - VSS2 = 15 V VS - VSS2 = 15 V
5 0.5
0
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
-40 -20 0 20 40 60 80 100
IFLH – INPUT THRESHOLD CURRENT - mA
TA - TEMPERATURE - OC
13
Figure 13: VOC vs. Temperature Figure 14: ICHG vs. Temperature
9.11 -40 -20 0 20 40 60 80 100

VOC - OC SENSING VOLTAGE THRESHOLD -
9.1
-0.1
9.09
ICHG - BLANKING CAPACITOR

CHARGING CURRENT - mA
9.08 -0.3 IF = 8 mA
VDD2 - VS = 15 V
9.07
-0.5 VS - VSS2 = 15 V
9.06
V
-0.7
9.05
IF = 8 mA
9.04 VDD2 - VS = 15 V -0.9
VS - VSS2 = 15 V
9.03
-1.1
9.02
9.01 -1.3
-40 -20 0 20 40 60 80 100
-1.5
Figure 15: tPLH/tPHL vs. Temperature Figure 16: tPLH/tPHL vs. IF
140 140
tPLH/tPHL - PROPAGATION DELAY- ns
tPLH/tPHL - PROPAGATION DELAY- ns

120 120
100 100
80 80
IF = 8 mA VDD2 - VS = 15 V
tPLH tPLH
60 VDD2 - VS = 15 V 60 VS - VSS2 = 15 V
VS - VSS2 = 15 V
30_15
tPHL RGN = RGP = 5
40 RGN = RGP = 5Ω CG = 5nF tPHL
40
CG = 5nF f = 20kHz 30_15
20 f = 20kHz DC = 50%
20
DC = 50% TA = 25ºC
0 0
-40 -20 0 20 40 60 80 100 8 8.5 9 9.5 10 10.5 11 11.5 12
TA - TEMPERATURE - OC IF - FORWARD LED CURRENT- mA
Figure 17: tPLH/tPHL vs. Temperature Figure 18: tOC(RESET)/tOC(MUTE) vs. Temperature
0.3 3.07
3.065
tSS(LOW) - PROPAGATION DELAY- μs
0.25
3.06
tOC(RESET)/tOC(MUTE) - mS
0.2 3.055 tOC(RESET)

3.05 tOC(MUTE)
0.15 IF = 8 mA
IF = 8 mA
VDD2 - VS = 15 V 3.045
VDD2 - VS = 15 V
VS - VSS2 = 15 V
0.1 3.04 VS - VSS2 = 15 V
RSS = 133
RSS = 133
RGN = RGP = 5 3.035 RGN = RGP = 5
CG = 5nF
0.05 CG = 5nF
f = 20kHz 3.03 DC = 50%
DC = 50%
0 3.025
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
14
Applications Information
Recommended Application Circuit
Figure 19: Recommended Application Circuit for the ACPL-351J
1 VSS2 16
ϭʅ& 1μF VSS2=-5V

2 FAULT 15
RBLOCK = 1kё DBLOCK
3 OC 14
RSS = 133ё
4 SS 13
CBLANK = 220pF
5 VDD2 12 VDD2=20V
RGP = 5ё IGBT/
VGATE
6 CATHODE VOUTP/CLAMP 11 MOSFET
R 1μF DP
7 ANODE VOUTN 10
R RGN = 5ё
8 CATHODE VS 9
RFSш4.ϳŬɏ
VCC1
RL =2.ϴŬɏ 6 1
FAULT
5 2
(to MCU)
CL = 330pF 4 3
CFS = 470pF
ACPL-W50L
VSS2=-5V
The ACPL-351J has an LED input control and overcurrent fault reporting mechanisms through the external feedback
optocoupler. The supply VDD2 is connected to four 1-µF bypass decoupling capacitors to provide the large transient currents
necessary during a switching transition.
The two resistors (R) connected to the input LED's anode and cathode are recommended to be split in the ratio of 3:1. They
help to balance the common mode impedances at the LED's anode and cathode, which equalizes the common mode voltage
changes at the anode and cathode to give high CMR performance.
The HV blocking diode, DBLOCK, RBLOCK, and 220-pF blanking capacitors are used to protect the OC pin and prevent false
fault detection. During overcurrent fault conditions, the IGBT/MOSFET is soft shut down through the SS pin and the rate of
shut down can be adjusted by RSS.
The gate resistor (RGP and RGN) serves to limit the gate current and indirectly control the IGBT/MOSFET switching times.
The Schottky diode, DP, is used together with the CLAMP function to shunt parasitic IGBT/MOSFET Miller current during the
off cycle.
15
CFS filters noise from turning on the external feedback LED during normal operation. During an overcurrent fault condition,
the FAULT pin pulls to VSS2 to turn on the external LED to feedback to the MCU.
Output Control
The secondary output stage (VOUT, CLAMP, OC, and SS) is controlled by the combination of VDD2, LED current (IF) and
overcurrent (OC) conditions. The following table shows the logic truth table for these outputs. The logic level is defined by
the respective threshold of each function pin.
Fault Reporting
Inputs Secondary Outputs Output
Condition VDD2 IF OC VOUTN VOUTP/CLAMP SS FAULT

VDD2 UVLO Low X Not Active Low Low(CLAMP) High-Z High
Overcurrent High Low Not Active Low Low(CLAMP) High-Z High
High High Active(OC) High-Z Low(CLAMP) Low Low
Normal High Low Not Active Low Low(CLAMP) High-Z High
Switching High High Active(no OC) High-Z High(VOUTP) High-Z High
Introduction to Overcurrent (or DESAT) Detection and Protection

The power stage of a typical three-phase inverter is susceptible to several types of failures, most of which are potentially
destructive to the power IGBT/MOSFET. These failure modes can be grouped into four basic categories: phase, rail supply
short circuits, or both due to user misconnect or bad wiring; control signal failures due to noise or computational errors;
overload conditions induced by the load; and component failures in the gate drive circuitry. Under any of these fault
conditions, the current through the IGBT/MOSFET can increase rapidly, causing excessive power dissipation and heating.
The IGBT/MOSFET becomes damaged when the current load approaches the saturation current of the device, and the
collector/drain to emitter/source voltage rises above the saturation voltage level. The drastically increased power dissipation
quickly overheats the power device and destroys it. To prevent damage to the drive, fault protection must be implemented
to reduce or turn off the IGBT/MOSFET during a fault condition.
The ACPL-351J OC pin monitors the drain/source voltages of the MOSFET or the collector/emitter voltages of the IGBT.
When the MOSFET goes into overcurrent or IGBT into desaturation, these voltages exceed the predetermined threshold,
VOC. The ACPL-351J triggers a local fault shutdown sequence and slowly reduces the high overcurrent to prevent damaging
voltage spikes. The fault is reported to the controller through the external feedback optocoupler.
During the off state (no LED input) of the IGBT, the fault detect circuitry is disabled to prevent false “fault” signals.
16
Description of Operation During an Overcurrent Condition

1. The OC terminal monitors IGBT’s VCE or MOSFET VDS voltage.
2. When the voltage on the OC terminal exceeds 9V, the output voltages (VOUTP and VOUTN) go to Hi-Z state, and the SS
pulls down the VGATE at a slow rate adjustable using resistor RSS.
3. The FAULT pin pulls to VSS2 to turn on the external feedback optocoupler and notifies the microcontroller of the fault
condition.
4. The microcontroller takes the appropriate action.
5. When tOC(MUTES) expires, the LED input must be kept low for tOC(RESET) before the fault condition is cleared. FAULT
status will return to high, and SS output will return to Hi-Z state.
6. In the event that the LED goes high during tOC(RESET), the tOC(RESET) timing will reset, and the LED input will need to be
kept low for another tOC(RESET) before the fault condition is cleared.
7. VGATE starts to respond to the LED input after the fault condition is cleared.
Figure 20: Circuit Behaviors During an Overcurrent Event
tOC(MUTE) )
IF
tOC(90%)
90%
VGATE tOC(2V) 2V
Hi-Z Hi-Z
VOUTN
Hi-Z Miller Clamp Miller Clamp

VOUTP/CLAMP 10% 10%
tSS(LOW )
Hi-Z Hi-Z
SS (Soft Shut) 10%
9V
OC tOC(BLANKING )
1V 10%
tOC(BLANKING )
10%
tOC(LOW )
FAULT
tOC(FAULT) tOC(RESET)
17
OC Fault Detection Blanking Time

The OC fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the
collector voltage to fall below the OC threshold. This time period, called the total OC blanking time, is controlled by the both
internal OC blanking time tOC(BLANKING) (Figure 20) and external blanking time, determined by internal charge current, the
OC voltage threshold, and the external blanking capacitor.
The total blanking time is calculated in terms of internal blanking time (tOC(BLANKING)), external capacitance (CBLANK), FAULT
threshold voltage (VOC), and blanking capacitor charge current (ICHG) as follows.
tBLANK = tOC(BLANKING) + CBLANK × (VOC / ICHG)
Description of Gate Driver and Miller Clamping

The gate driver is directly controlled by the LED current. When LED current is driven high, the output of the ACPL-351J is
capable of delivering 5A maximum sourcing current to drive the IGBT's/MOSFET's gate. While the LED is switched off, the
gate driver can provide 5A maximum sinking current to switch the gate off fast. An additional Miller clamping pull-down
transistor is activated when the output voltage reaches about 2V with respect to VSS2 to provide low impedance path to the
Miller current as shown in Figure 21.
Figure 21: Gate Drive Signal Behavior
IF
tPLH
Miller Clamp turns on at

VOUTP Miller Clamp HI-Z VGATE = VSS2 +2V
HI-Z
VOUTN
tPHL
VGATE
Description of Under Voltage Lockout

Insufficient gate voltage to IGBT/MOSFET can increase turn-on resistance of IGBT/MOSFET, resulting a large power loss
and IGBT/MOSFET damage due to high heat dissipation. The ACPL-351J monitors the output power supply, VDD2,
constantly. When the output power supply is lower than the under voltage lockout (UVLO) threshold, the gate driver output
shuts off to protect IGBT/MOSFET from low voltage bias. During power up, the UVLO feature locks the gate driver output
low to prevent unwanted turn on at the lower supply voltage.
18
Figure 22: Circuit Behaviors at Power Up and Power Down
VUVLO-
VUVLO+ VUVLO- VUVLO+
VDD2
IF
VOUTP Miller Clamp Miller Clamp tUVLO_ON
HI-Z
VOUTN HI-Z
tUVLO_OFF
Selecting the Gate Resistor (Rg)

Step 1: Calculate RG minimum from the IO(PEAK) specification. The IGBT/MOSFET and RG in Figure 19 can be analyzed as
a simple RC circuit with a voltage supplied by the ACPL-351J.
RG ≥ VDD 2–VSS 2 – ROUTP ( MIN ) RG ≥ VDD 2–VSS 2 – ROUTN ( MIN )

I OPEAK I OPEAK
20 – (– 5)V or 20 – (– 5)V
= – 0.4Ω = = 0.3Ω
5A 5A
= 4.6Ω = 4.7Ω
The external gate resistor, RG, and internal minimum turn-on resistance, RDSON, ensure that the output current does not
exceed the device absolute maximum rating of 5A. In this case, use as the worst case, RG ≥ 4.8Ω.
Step 2: Check the ACPL-351J power dissipation and increase RG if necessary. The ACPL-351J total power dissipation (PT)
is equal to the sum of the LED power (PE) and the output IC power (PO).
PT = PE + PO
Assuming operation conditions of IF = 8 mA, RG = 4.8Ω, maximum duty cycle = 80%, QG = 0.5 µC, f = 100 kHz, and
TA = 80°C.
Calculation of LED Power Dissipation

PE = IF × VF × Duty Cycle
= 8 mA × 1.95V × 0.8 = 12.5 mW
Calculation of Output IC Power Dissipation

PO = PO(BIAS) + PO(SWITCHING)
= IDD2 × (VDD2 – VSS2) + PHS + PLS
PHS = (VDD2 × QG × f) × ROUTP(MAX) / (ROUTP(MAX) + RG) / 2
PLS = (VDD2 × QG × f) × ROUTN(MAX) / (ROUTN(MAX) + RG) / 2
19
PHS = (25V × 0.5 µC × 100 kHz) × 1.5Ω / (1.5Ω + 4.8Ω) / 2 = 148.81 mW

PLS = (25V × 0.5 µC × 100 kHz) × 1.2Ω / (1.2Ω + 4.8Ω) / 2 = 125.0 mW
PO = 7.5 mA × 25V + 148.81 mW + 125.0 mW
= 461.3 mW < 600 mW (PO(MAX) at 95°C)
The value of 7.5 mA for IDD2 in the previous equation is the maximum ICC2 over the entire operating temperature range.
Because PO is less than PO(MAX), Rg = 4.8Ω is correct for the power dissipation.
Thermal Calculation
The application and environmental design for the ACPL-351J must ensure that the junction temperature of the internal IC
and LED within the gate driver optocoupler does not exceed 125°C. The following equations calculate the maximum power
dissipation effect on junction temperatures.
LED Junction Temperature, TE = (AEA × PE) + (AEO × PO) + TA

= (176.1°C/W × 12.5 mW) + (33.1°C/W × 461.3 mW) + 80°C
= 97.5°C
Output IC Junction Temperature, TO = (AEO × PE) + (AOA × PO) + TA

= (33.1°C/W × 12.5 mW) + (76.7°C/W × 461.3 mW) + 80°C
= 115.8°C
Overcurrent Blocking Diodes and Threshold

The DBLOCK diode's function is to conduct forward current, allowing sensing of the IGBT's VCE or MOSFET's VDS when it is
"on" and to block high voltages when it is "off".
During IGBT/MOSFET switching off and towards the end of the forward conduction of the DBLOCK diode, a reverse current
flows for a short time. This reverse recovery effect causes the diode to not be able to achieve its blocking capability until the
mobile charge in the junction is depleted. During this time, there is commonly a very high dV/dt voltage ramp rate across the
IGBT/MOSFET. This results in ICHARGE = CD-BLOCK × dV/dt charging current, which will charge the blanking capacitor,
CBLANK. To minimize this charging current and avoid false overcurrent triggering, it is best to use fast response diodes.
In the recommended application circuit shown in Figure 23, the voltage on pin 14 (OC) is VOC = VF + VCE (where VF is the
forward ON voltage of DBLOCK, and VCE is for example, the IGBT collector-to-emitter voltage). The value of VOC,FAULT(TH),
which triggers OC to signal a FAULT condition, is nominally 9V – VF. If desired, this threshold voltage can be decreased by
using multiple DBLOCK diodes or low voltage Zener diode in series. If n is the number of DBLOCK diodes, the nominal
threshold value becomes VOC,FAULT(TH) = 9V – n × VF. If a Zener diode is used, the nominal threshold value becomes
VOC,FAULT(TH) = 7V – VF – VZ. In the case of using two diodes instead of one, diodes with half of the total required maximum
reverse-voltage rating may be chosen.
20
Figure 23: OC Blocking Diodes and Threshold
VSS2 16
FAULT 15
1kΩ DZENER DBLOCK
OC 14
CBLANK
+
VCE
Q1 -
VS 9
OC Pin Protection Resistor

The freewheeling of flyback diodes connected across the IGBT/MOSFET can have large instantaneous forward voltage
transients that greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on
the OC pin, which will draw substantial current out of the driver if protection is not used. To limit this current to levels that will
not damage the driver IC, insert a 1-kΩ resistor in series with the DBLOCK diode.
False Fault Prevention Diodes

One of the situations that may cause the driver to generate a false fault signal is if the substrate diode of the driver becomes
forward biased. This can happen if the reverse recovery spikes coming from the IGBT/MOSFET freewheeling diodes bring
the OC pin below ground. Hence, the OC pin voltage will be “brought” above the threshold voltage. This negative going
voltage spikes are typically generated by inductive loads or reverse recovery spikes of the IGBT/MOSFETs free-wheeling
diodes. To prevent a false fault signal, connect a Zener diode and Schottky diode across the OC pin and VS pin
This circuit solution is shown in Figure 24. The Schottky diode prevents the substrate diode of the gate driver optocoupler
from being forward biased while the Zener diode (value around 10V) is used to prevent any positive high transient voltage
to affect the OC pin.
Figure 24: False Fault Prevention Diodes
VSS2 16
FAULT 15
10V Zener
1N5925A ϭŬΩ DBLOCK
OC 14
CBLANK
+
VCE
Q1 -
VS 9
SchoƩŬy
Diode
MBR0540
21
Supply and Ground Planes Layout and Loading Conditions

At 5A rated high current switching, the decoupling capacitor must be close to the VDD and VSS pins. Due to the fast switching,
large VDD and VSS planes are recommended to prevent noise by lowering the parasitic inductance. Without the VDD and
VSS planes, it is recommended to connect total load bigger than 2 nF during all applications or board testing to prevent output
noise.
Figure 25: Recommended VDD2 and VSS2, Supply and Ground Planes Layout.
VSS2 16
Decoupling capacitor is connected

between VDD2 and VEE2 planes
VDD2 12
VDD2 plane
VSS2 plane
Output Noise Prevention Diodes

Figure 26: Recommended Schottky Diodes to Prevent Output Noise
VDD2 12 VDD2=20V
RGP = 5ё
VGATE IGBT/MOSFET
VOUTP/CLAMP 11
1μF DP
VOUTN 10
RGN = 5ё
DSCHOTTKY_VS
VS 9 DSCHOTTKY_VOUTN
VSS2=-5V
DSCHOTTKY_VOUTP
VSS2=-5V
The output, VGATE can be disturbed due to negative transient caused by parasitic inductance. This might cause noise at the
VGATE if voltage at VOUT or VS goes below the most negative potential of VSS. Schottky diodes, DSCHOTTKY_VOUTP,
DSCHOTTKY_VOUTN, or DSCHOTTKY_VS can be used to prevent the noise if any of these nodes experience negative transient
caused by parasitic inductance.
22
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ACPL-351J: Data Sheet

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Data Sheet

Pin Symbol Description

ACPL-351J 16-Lead Surface Mount Package

Recommended Pb-Free IR Profile

IEC/EN/DIN EN 60747-5-5 Maximum working insulation voltage VIORM = 1414 VPEAK.

Table 1: IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa

Description Symbol Characteristic Units

Input to Output Test Voltage, Method bb VPR 2652 VPEAK

Table 2: Insulation and Safety Related Specifications

Parameter Symbol ACPL-351J Units Conditions

Table 3: Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Notes

Peak Transient Input Current IF(TRAN) — 1.0 A

"Low" Peak Output Current IOL(PEAK) — 5 A b

Total Output Supply Voltage (VDD2 – VSS2) –0.5 35 V

Input LED Power Dissipation PI — 110 mW d

Table 4: Recommended Operating Conditions

Parameter Symbol Min. Max. Units Notes

Total Output Supply Voltage (VDD2 – VSS2) 15 30 V

Negative Output Supply Voltage (VS – VSS2) 0 15 V

Positive Output Supply Voltage (VDD2 – VS) 15 30 – (VS – VSS2) V

Input Current (ON) IF(ON) 8 12 mA

Input Voltage (OFF) VF(OFF) –3.6 0.8 V

FAULT Pin Voltage VFAULT — 30 V

Table 5: Electrical Specifications (DC)

Table 5: Electrical Specifications (DC) (Continued)

Table 6: Switching Specifications (AC)

Propagation Delay Difference Between PDD –75 — 75 ns d

Table 6: Switching Specifications (AC) (Continued)

OC Detection to 90% VGATE Delay tOC(90%) — 0.13 — µs RGN = 5Ω, 20 g

Time Input Kept Low Before Fault Reset tOC(RESET) 2 3 4 ms 18, 20 m

VDD2 UVLO to VOUTN Low Delay tUVLO_OFF — 1.5 — µs 22 o

Table 7: Package Characteristics

Input-Output Capacitance CI-O — 1.3 — pF freq = 1 MHz

LED and Output IC AEO 33.1 — —

Figure 1: VOH vs. Temperature Figure 2: VOL vs. Temperature

VOL - LOW OUTPUT VOLTAGE - V

Figure 3: IOH vs. VOH Figure 4: IOL vs. VOL

Figure 5: ROUTP vs. Temperature Figure 6: ROUTN vs. Temperature

Figure 7: ICLAMP vs. Temperature Figure 8: IOSS vs. VOSS

IOSS - SS PULL DOWN CURRENT - A

Figure 9: IDD2H/IDD2L vs. Temperature Figure 10: ISS2H/ISS2L vs. Temperature

7 -40 -20 0 20 40 60 80 100

IFLH - INPUT THRESHOLD CURRENT

9.11 -40 -20 0 20 40 60 80 100

ICHG - BLANKING CAPACITOR

Figure 15: tPLH/tPHL vs. Temperature Figure 16: tPLH/tPHL vs. IF

tPLH/tPHL - PROPAGATION DELAY- ns

0.2 3.055 tOC(RESET)

ϭʅ& 1μF VSS2=-5V

Condition VDD2 IF OC VOUTN VOUTP/CLAMP SS FAULT

Introduction to Overcurrent (or DESAT) Detection and Protection

Description of Operation During an Overcurrent Condition

Figure 20: Circuit Behaviors During an Overcurrent Event

Hi-Z Miller Clamp Miller Clamp

OC Fault Detection Blanking Time

tBLANK = tOC(BLANKING) + CBLANK × (VOC / ICHG)

Description of Gate Driver and Miller Clamping

Figure 21: Gate Drive Signal Behavior