FEATURES DESCRIPTION • Compatible with Voltage or Current Mode The UC1825 family of PWM control ICs is optimized for high fre- Topologies quency switched mode power supply applications. Particular care was given to minimizing propagation delays through the comparators • Practical Operation Switching Frequencies to 1MHz and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. This controller is designed for use in either current- • 50ns Propagation Delay to Output mode or voltage mode systems with the capability for input voltage • High Current Dual Totem Pole Outputs feed-forward. (1.5A Peak) Protection circuitry includes a current limit comparator with a 1V threshold, a TTL compatible shutdown port, and a soft start pin which • Wide Bandwidth Error Amplifier will double as a maximum duty cycle clamp. The logic is fully latched • Fully Latched Logic with Double Pulse to provide jitter free operation and prohibit multiple pulses at an out- Suppression put. An under-voltage lockout section with 800mV of hysteresis as- sures low start up current. During under-voltage lockout, the outputs • Pulse-by-Pulse Current Limiting are high impedance. • Soft Start / Max. Duty Cycle Control These devices feature totem pole outputs designed to source and • Under-Voltage Lockout with Hysteresis sink high peak currents from capacitive loads, such as the gate of a
Datasheet.Live power MOSFET. The on state is designed as a high level. • Low Start Up Current (1.1mA) • Trimmed Bandgap Reference (5.1V ±1%)
ELECTRICAL CHARACTERISTICS: Unless otherwise stated,these specifications apply for , RT = 3.65k, CT = 1nF, VCC = 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ. UC1825 UC3825 PARAMETERS TEST CONDITIONS UC2825 MIN TYP MAX MIN TYP MAX UNITS Reference Section Output Voltage TJ = 25°C, IO = 1mA 5.05 5.10 5.15 5.00 5.10 5.20 V Line Regulation 10V < VCC < 30V 2 20 2 20 mV Load Regulation 1mA < IO < 10mA 5 20 5 20 mV Temperature Stability* TMIN < TA < TMAX 0.2 0.4 0.2 0.4 mV/°C Total Output Variation* Line, Load, Temperature 5.00 5.20 4.95 5.25 V Output Noise Voltage* 10Hz < f < 10kHz 50 50 µV Long Term Stability* TJ = 125°C, 1000hrs. 5 25 5 25 mV Short Circuit Current VREF = 0V -15 -50 -100 -15 -50 -100 mA Oscillator Section Initial Accuracy* TJ = 25°C 360 400 440 360 400 440 kHz Voltage Stability* 10V < VCC < 30V 0.2 2 0.2 2 % Temperature Stability* TMIN < TA < TMAX 5 5 % Total Variation* Line, Temperature 340 460 340 460 kHz
2 UC1825 UC2825 UC3825 ELECTRICAL CHARACTERISTICS Unless otherwise stated,these specifications apply for , RT = 3.65k, CT (cont.) = 1nF, VCC = 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ. UC1825 UC3825 PARAMETERS TEST CONDITIONS UC2825 MIN TYP MAX MIN TYP MAX UNITS Oscillator Section (cont.) Clock Out High 3.9 4.5 3.9 4.5 V Clock Out Low 2.3 2.9 2.3 2.9 V Ramp Peak* 2.6 2.8 3.0 2.6 2.8 3.0 V Ramp Valley* 0.7 1.0 1.25 0.7 1.0 1.25 V Ramp Valley to Peak* 1.6 1.8 2.0 1.6 1.8 2.0 V Error Amplifier Section Input Offset Voltage 10 15 mV Input Bias Current 0.6 3 0.6 3 µA Input Offset Current 0.1 1 0.1 1 µA Open Loop Gain 1V < VO < 4V 60 95 60 95 dB CMRR 1.5V < VCM < 5.5V 75 95 75 95 dB PSRR 10V < VCC < 30V 85 110 85 110 dB Output Sink Current VPIN 3 = 1V 1 2.5 1 2.5 mA Output Source Current VPIN 3 = 4V -0.5 -1.3 -0.5 -1.3 mA Output High Voltage IPIN 3 = -0.5mA 4.0 4.7 5.0 4.0 4.7 5.0 V Output Low Voltage IPIN 3 = 1mA 0 0 .5 1.0 0 0.5 1.0 V Unity Gain Bandwidth* 3 5.5 3 5.5 MHz Slew Rate* 6 12 6 12 V/µs PWM Comparator Section Pin 7 Bias Current VPIN 7 = 0V -1 -5 -1 -5 µA Duty Cycle Range 0 80 0 85 % Pin 3 Zero DC Threshold VPIN 7 = 0V 1.1 1.25 1.1 1.25 V Delay to Output* 50 80 50 80 ns Soft-Start Section Charge Current VPIN 8 = 0.5V 3 9 20 3 9 20 µA Discharge Current VPIN 8 = 1V 1 1 mA Current Limit / Shutdown Section Pin 9 Bias Current 0 < VPIN 9 < 4V 15 10 µA Current Limit Threshold 0.9 1.0 1.1 0.9 1.0 1.1 V Shutdown Threshold 1.25 1.40 1.55 1.25 1.40 1.55 V Delay to Output 50 80 50 80 ns Output Section Output Low Level IOUT = 20mA 0.25 0.40 0.25 0.40 V IOUT = 200mA 1.2 2.2 1.2 2.2 V Output High Level IOUT = -20mA 13.0 13.5 13.0 13.5 V IOUT = -200mA 12.0 13.0 12.0 13.0 V Collector Leakage VC = 30V 100 500 10 500 µA Rise/Fall Time* CL = 1nF 30 60 30 60 ns Under-Voltage Lockout Section Start Threshold 8.8 9.2 9.6 8.8 9.2 9.6 V UVLO Hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V Supply Current Section Start Up Current VCC = 8V 1.1 2.5 1.1 2.5 mA ICC VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V 22 33 22 33 mA * This parameter not 100% tested in production but guaranteed by design.
3 UC1825 UC2825 Printed Circuit Board Layout Considerations UC3825 High speed circuits demand careful attention to layout Schottky diode at the output pin will serve this purpose. 3) and component placement. To assure proper performance Bypass VCC, VC, and VREF. Use 0.1µF monolithic ceramic of the UC1825 follow these rules: 1) Use a ground plane. capacitors with low equivalent series inductance. Allow 2) Damp or clamp parasitic inductive kick energy from the less than 1 cm of total lead length for each capacitor be- gate of driven MOSFETs. Do not allow the output pins to tween the bypassed pin and the ground plane. 4) Treat ring below ground. A series gate resistor or a shunt 1 Amp the timing capacitor, CT, like a bypass capacitor.
µ Timing Resistance vs Frequency Deadtime vs Frequency 160
1.0nF 140
TD (ns) 120
100 470pF 80 10k 100k 1M FREQ (Hz)
Synchronized Operation
Two Units in Close Proximity Generalized Synchronization
5 UC1825 UC2825 Forward Technique for Off-Line Voltage Mode Application UC3825
Constant Volt-Second Clamp Circuit
The circuit shown here will achieve a constant volt-sec-
ond product clamp over varying input voltages. The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be com- pletely discharged during the minimum deadtime.
Output Section Simplified Schematic Rise/Fall Time (CL=1nF)
Rise/Fall Time (CL=10nF) Saturation Curves
6 UC1825 UC2825 Open Loop Laboratory Test Fixture UC3825
UDG-92032-2
This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and by- UC1825’s functions and measuring their specifications. pass procedures should be followed. The use of a ground plane is highly recommended.
Design Example: 50W, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency
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