application UC1825

INFO
available
UC2825
UC3825

High Speed PWM Controller

FEATURES DESCRIPTION
• Compatible with Voltage or Current Mode The UC1825 family of PWM control ICs is optimized for high fre-
Topologies quency switched mode power supply applications. Particular care
was given to minimizing propagation delays through the comparators
• Practical Operation Switching Frequencies
to 1MHz and logic circuitry while maximizing bandwidth and slew rate of the
error amplifier. This controller is designed for use in either cur-
• 50ns Propagation Delay to Output rent-mode or voltage mode systems with the capability for input volt-
age feed-forward.
• High Current Dual Totem Pole Outputs
(1.5A Peak) Protection circuitry includes a current limit comparator with a 1V
threshold, a TTL compatible shutdown port, and a soft start pin
• Wide Bandwidth Error Amplifier
which will double as a maximum duty cycle clamp. The logic is fully
• Fully Latched Logic with Double Pulse latched to provide jitter free operation and prohibit multiple pulses at
Suppression an output. An under-voltage lockout section with 800mV of hysteresis
assures low start up current. During under-voltage lockout, the out-
• Pulse-by-Pulse Current Limiting
puts are high impedance.
• Soft Start / Max. Duty Cycle Control
These devices feature totem pole outputs designed to source and
• Under-Voltage Lockout with Hysteresis sink high peak currents from capacitive loads, such as the gate of a
power MOSFET. The on state is designed as a high level.
• Low Start Up Current (1.1mA)

BLOCK DIAGRAM

UDG-92030-2

SLUS235A - MARCH 1997 - REVISED MARCH 2004

 UC1825
UC2825
UC3825
ABSOLUTE MAXIMUM RATINGS (Note 1) CONNECTION DIAGRAMS
Supply Voltage (Pins 13, 15) . . . . . . . . . . . . . . . . . . . . . . . . 30V
Output Current, Source or Sink (Pins 11, 14) DIL-16 (Top View)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A J or N Package
Pulse (0.5 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0A
Analog Inputs
(Pins 1, 2, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
(Pin 8, 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Clock Output Current (Pin 4) . . . . . . . . . . . . . . . . . . . . . . . -5mA
Error Amplifier Output Current (Pin 3) . . . . . . . . . . . . . . . . 5mA
Soft Start Sink Current (Pin 8) . . . . . . . . . . . . . . . . . . . . . 20mA
Oscillator Charging Current (Pin 5) . . . . . . . . . . . . . . . . . . -5mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range . . . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . 300°C

PACKAGE PIN FUNCTION

PLCC-20 & LCC-20 FUNCTION PIN
(Top View) N/C 1
INV 2
SOIC-16 (Top View) Q & L Packages
NI 3
DW Package E/A Out 4
Clock 5
N/C 6
RT 7
CT 8
Ramp 9
Soft Start 10
N/C 11
ILIM/SD 12
Gnd 13
Out A 14
Pwr Gnd 15
N/C 16
VC 17
Out B 18
VCC 19
VREF 5.1V 20

THERMAL RATINGS TABLE

Package QJA QJC
DIL-16J 80-120 28(2)
DIL-16N 90(1) 45
PLCC-20 43-75(1) 34
LCC-20 70-80 20(2)
SOIC-16 50-120(1) 35
Q

2
 UC1825
UC2825
UC3825

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC
= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TO.

UC1825
UC3825
PARAMETERS TEST CONDITIONS UC2825
MIN TOP MAX MIN TOP MAX UNITS
Reference Section
Output Voltage TO = 25°C, IO = 1mA 5.05 5.10 5.15 5.00 5.10 5.20 V
Line Regulation 10V < VCC < 30V 2 20 2 20 mV
Load Regulation 1mA < IO < 10mA 5 20 5 20 mV
Temperature Stability* TMIN < TA < TMAX 0.2 0.4 0.2 0.4 mV/°C
Total Output Variation* Line, Load, Temperature 5.00 5.20 4.95 5.25 V
Output Noise Voltage* 10Hz < f < 10kHz 50 50 µV
Long Term Stability* TJ = 125°C, 1000hrs. 5 25 5 25 mV
Short Circuit Current VREF = 0V -15 -50 -100 -15 -50 -100 mA
Oscillator Section
Initial Accuracy* TJ = 2°C 360 400 440 360 400 440 kHz
Voltage Stability* 10V < VCC < 30V 0.2 2 0.2 2 %
Temperature Stability* TMIN < TA < TMAX 5 5 %
Total Variation* Line, Temperature 340 460 340 460 kHz
Oscillator Section (cont.)
Clock Out High 3.9 4.5 3.9 4.5 V
Clock Out Low 2.3 2.9 2.3 2.9 V
Ramp Peak* 2.6 2.8 3.0 2.6 2.8 3.0 V
Ramp Valley* 0.7 1.0 1.25 0.7 1.0 1.25 V
Ramp Valley to Peak* 1.6 1.8 2.0 1.6 1.8 2.0 V
Error Amplifier Section
Input Offset Voltage 10 15 mV
Input Bias Current 0.6 3 0.6 3 µA
Input Offset Current 0.1 1 0.1 1 µA
Open Loop Gain 1V < VO < 4V 60 95 60 95 dB
CMRR 1.5V < VCM < 5.5V 75 95 75 95 dB
PSRR 10V < VCC < 30V 85 110 85 110 dB
Output Sink Current VPIN 3 = 1V 1 2.5 1 2.5 mA
Output Source Current VPIN 3 = 4V -0.5 -1.3 -0.5 -1.3 mA
Output High Voltage IPIN 3 = -0.5mA 4.0 4.7 5.0 4.0 4.7 5.0 V
Output Low Voltage IPIN 3 = 1mA 0 0 .5 1.0 0 0.5 1.0 V
Unity Gain Bandwidth* 3 5.5 3 5.5 MHz
Slew Rate* 6 12 6 12 V/µs

3
 UC1825
UC2825
UC3825

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for , RT = 3.65k, CT = 1nF, VCC
= 15V, -55°C<TA<125°C for the UC1825, –40°C<TA<85°C for the UC2825, and 0°C<TA<70°C for the UC3825, TA=TJ.

UC1825
UC3825
PARAMETERS TEST CONDITIONS UC2825
MIN TOP MAX MIN TOP MAX UNITS
PWM Comparator Section
Pin 7 Bias Current VPIN 7 = 0V -1 -5 -1 -5 µA
Duty Cycle Range 0 80 0 85 %
Pin 3 Zero DC Threshold VPIN 7 = 0V 1.1 1.25 1.1 1.25 V
Delay to Output* 50 80 50 80 ns
Soft-Start Section
Charge Current VPIN 8 = 0.5V 3 9 20 3 9 20 µA
Discharge Current VPIN 8 = 1V 1 1 mA
Current Limit / Shutdown Section
Pin 9 Bias Current 0 < VPIN 9 < 4V 15 10 µA
Current Limit Threshold 0.9 1.0 1.1 0.9 1.0 1.1 V
Shutdown Threshold 1.25 1.40 1.55 1.25 1.40 1.55 V
Delay to Output 50 80 50 80 ns
Output Section
Output Low Level IOUT = 20mA 0.25 0.40 0.25 0.40 V
IOUT = 200mA 1.2 2.2 1.2 2.2 V
Output High Level IOUT = -20mA 13.0 13.5 13.0 13.5 V
IOUT = -200mA 12.0 13.0 12.0 13.0 V
Collector Leakage VC = 30V 100 500 10 500 µA
Rise/Fall Time* CL = 1nF 30 60 30 60 ns
Under-Voltage Lockout Section
Start Threshold 8.8 9.2 9.6 8.8 9.2 9.6 V
UVLO Hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V
Supply Current Section
Start Up Current VCC = 8V 1.1 2.5 1.1 2.5 mA
ICC VPIN 1, VPIN 7, VPIN 9 = 0V; VPIN 2 = 1V 22 33 22 33 mA

4
 UC1825
UC2825
Printed Circuit Board Layout Considerations UC3825
High speed circuits demand careful attention to layout this purpose. 3) Bypass VCC, VC, and VREF. Use 0.1µF
and component placement. To assure proper perfor- monolithic ceramic capacitors with low equivalent series
mance of the UC1825 follow these rules: 1) Use a ground inductance. Allow less than 1 cm of total lead length for
plane. 2) Damp or clamp parasitic inductive kick energy each capacitor between the bypassed pin and the ground
from the gate of driven MOSFETs. Do not allow the out- plane. 4) Treat the timing capacitor, CT, like a bypass ca-
put pins to ring below ground. A series gate resistor or a pacitor.
shunt 1 Amp Schottky diode at the output pin will serve

Error Amplifier Circuit

Simplified Schematic

Open Loop Frequency Response Unity Gain Slew Rate

PWM Applications
Current-Mode
Conventional (Voltage Mode)

5
 UC1825
UC2825
Oscillator Circuit UC3825
Deadtime vs CT (3k RT 100k)

µ
Timing Resistance vs Frequency Deadtime vs Frequency
160

1.0nF
140

TD (ns) 120

100
470pF
80
10k 100k 1M
FREQ (Hz)

Synchronized Operation

Two Units in Close Proximity Generalized Synchronization

6
 UC1825
UC2825
Forward Technique for Off-Line Voltage Mode Application UC3825

Constant Volt-Second Clamp Circuit

The circuit shown here will achieve a constant

volt-second product clamp over varying input voltages.
The ramp generator components, RT and CR are cho-
sen so that the ramp at Pin 9 crosses the 1V threshold
at the same time the desired maximum volt-second
product is reached. The delay through the functional
nor block must be such that the ramp capacitor can be
completely discharged during the minimum deadtime.

Output Section

Simplified Schematic Rise/Fall Time (CL=1nF)

Rise/Fall Time (CL=10nF) Saturation Curves

7
 UC1825
UC2825
Open Loop Laboratory Test Fixture UC3825

UDG-92032-2

This test fixture is useful for exercising many of the As with any wideband circuit, careful grounding and by-
UC1825’s functions and measuring their specifications. pass procedures should be followed. The use of a
ground plane is highly recommended.

Design Example: 50W, 48V to 5V DC to DC Converter - 1.5MHz Clock Frequency

UDG-92033-3

8
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

5962-87681012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87681012A
UC1825L/
883B
5962-8768101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101EA
UC1825J/883B
5962-8768101QFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101QF
A
UC1825W/883B
UC1825J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 UC1825J

UC1825J883B ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101EA
UC1825J/883B
UC1825L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UC1825L

UC1825L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87681012A
UC1825L/
883B
UC1825W883B ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8768101QF
A
UC1825W/883B
UC2825DW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825DW
& no Sb/Br)
UC2825DWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825DW
& no Sb/Br)
UC2825DWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825DW
& no Sb/Br)
UC2825DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2825DW
& no Sb/Br)
UC2825J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -40 to 85 UC2825J

UC2825N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2825N
& no Sb/Br)
UC2825NG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UC2825N
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UC2825Q ACTIVE PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 85 UC2825Q

& no Sb/Br)
UC3825DW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW
& no Sb/Br)
UC3825DWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW
& no Sb/Br)
UC3825DWTR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW
& no Sb/Br)
UC3825DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3825DW
& no Sb/Br)
UC3825N ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3825N
& no Sb/Br)
UC3825NG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UC3825N
& no Sb/Br)
UC3825Q ACTIVE PLCC FN 20 46 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 UC3825Q
& no Sb/Br)
UC3825QTR ACTIVE PLCC FN 20 1000 Green (RoHS CU SN Level-2-260C-1 YEAR 0 to 70 UC3825Q
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1825, UC2825, UC2825M, UC3825 :

• Catalog: UC3825, UC2825

• Military: UC2825M, UC1825
• Space: UC1825-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE OUTLINE
FN0020A SCALE 1.300
PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER

.180 MAX
B .350-.356 [4.57]
[8.89-9.04] .020 MIN
NOTE 3 [0.51]
A (.008)
3 1 20 [0.2]

4 18

PIN 1 ID
.350-.356
(OPTIONAL) .283-.339
[8.89-9.04]
[7.19-8.61]
NOTE 3

8 14

9 13
.090-.120 TYP
20X .026-.032 [2.29-3.04]
[0.66-0.81]

SEATING PLANE
20X .013-.021
[0.33-0.53] .004 [0.1] C
16X .050
.007 [0.18] C A B
[1.27]

.385-.395
[9.78-10.03]
TYP

4215152/B 04/2017
NOTES:

1. All linear dimensions are in inches. Any dimensions in brackets are in millimeters. Any dimensions in parenthesis are for reference only.
Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension does not include mold protrusion. Maximum allowable mold protrusion .01 in [0.25 mm] per side.
4. Reference JEDEC registration MS-018.

www.ti.com
 EXAMPLE BOARD LAYOUT
FN0020A PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER

SYMM
(R.002 ) TYP
20X (.096 ) 3 1 20 [0.05]
[2.45]

20X (.025 )
[0.64] 4
18

SYMM
(.327)
[8.3]

16X (.050 )
[1.27]
14
8

9 13
(.327)
[8.3]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X

.002 MAX EXPOSED METAL .002 MIN EXPOSED METAL

[0.05] [0.05]
ALL AROUND ALL AROUND

SOLDER MASK SOLDER MASK METAL UNDER

METAL
OPENING OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4215152/B 04/2017
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
FN0020A PLCC - 4.57 mm max height
PLASTIC CHIP CARRIER

SYMM

20X (.096 ) (R.002 ) TYP

3 1 20 [0.05]
[2.45]

20X (.025 )
[0.64] 4
18

SYMM
(.327)
[8.3]

16X (.050 )
[1.27]
14
8

9 13
(.327)
[8.3]

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4215152/B 04/2017
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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