USOO80446.

04B2

(12) United States Patent (10) Patent No.: US 8,044,604 B2

Hagino et al. (45) Date of Patent: Oct. 25, 2011
(54) INVERTER (56) References Cited
(75) Inventors: Junichi Hagino, Kyoto (JP); Kenichi U.S. PATENT DOCUMENTS
Fukumoto, Kyoto (JP) 7,236,377 B2 * 6/2007 Fukumoto .................. 363.21.09
7,944,652 B2 * 5/2011 Fukumoto ....................... 361.23
2004/O130921 A1* 7/2004 Fukumoto ....................... 363.98
(73) Assignee: Rohm Co., Ltd. (JP)
FOREIGN PATENT DOCUMENTS
(*) Notice: Subject to any disclaimer, the term of this JP 2003-323994 A 11, 2003
patent is extended or adjusted under 35 * cited by examiner
U.S.C. 154(b) by 422 days.
Primary Examiner — ShawkiS Ismail
(21) Appl. No.: 12/420,274 Assistant Examiner — Crystal L Hammond
(74) Attorney, Agent, or Firm — Cantor Colburn LLP
(22) Filed: Apr. 8, 2009 (57) ABSTRACT
(65) Prior Publication Data A soft start circuit generates a soft start Voltage which
changes over time when light emission of an EEFL is started.
US 2009/O251062 A1 Oct. 8, 2009 A pulse modulator receives a feedback Voltage that corre
sponds to the output Voltage of an inverter and the soft start
(30) Foreign Application Priority Data voltage, and adjusts the duty ratio of a pulse signal PWM such
that these two Voltages match one another using a feedback
Apr. 8, 2008 (JP) ................................. 2008-100740 operation. A striking control circuit monitors an error signal
which is asserted when an abnormal state occurs. In a case in
(51) Int. Cl. which the error signal has been asserted at a detection timing
H05B 4/26 (2006.01) after the Soft start Voltage has reached a target Voltage, the
H02M 3/24 (2006.01) striking control circuit resets and restarts the Soft start circuit.
GO2F L/335 (2006.01) A driver controls the switching of the voltage at the primary
(52) U.S. Cl. ............................. 315/276,363/95; 349/70 coil of a transformer according to the pulse signal received
(58) Field of Classification Search ........................ None from the pulse modulator.
See application file for complete search history. 7 Claims, 8 Drawing Sheets
CTSYNC out
CTSYNCInouy sc; Brit DUTYout
U.S. Patent Oct. 25, 2011 Sheet 1 of 8 US 8,044,604 B2
U.S. Patent Oct. 25, 2011 Sheet 2 of 8 US 8,044,604 B2

FIG.2
U.S. Patent Oct. 25, 2011 Sheet 4 of 8 US 8,044,604 B2

CT SYNCOUT
R CT SYNC IN DUTY BCT BRT DUTY OUT
- - - - -
72
REFAW 3.
U.S. Patent Oct. 25, 2011 Sheet 5 of 8 US 8,044,604 B2

- - - - - - -
U.S. Patent Oct. 25, 2011 Sheet 6 of 8 US 8,044,604 B2

VREF SS

t31st NG Count tA
NG court finish atch threshold
CP

TSSW

FAll
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OPEN
LED ON Ter
reset
-1
Error delect
Low
U.S. Patent Oct. 25, 2011 Sheet 7 of 8 US 8,044,604 B2

FIG.7

SSW

TLED ON
FA OPEN
U.S. Patent Oct. 25, 2011 Sheet 8 of 8 US 8,044,604 B2

FIG.8

STB
UWO

FA OW
 US 8,044,604 B2
1. 2
INVERTER restarts the soft start circuit when the error signal has been
asserted at a detection timing after the Soft start Voltage has
BACKGROUND OF THE INVENTION reached a threshold Voltage.
With such an embodiment, the striking operation for the
1. Field of the Invention EEFL is performed using the soft start circuit. Thus, there is
The present invention relates to an inverter which supplies no need to provide an external circuit for the striking opera
driving Voltage to an external electrode fluorescent lamp. tion. Such an embodiment allows the EEFL to emit light in a
2. Description of the Related Art Sure manner using a simple configuration. Furthermore, only
In recent years, liquid crystal display TVs, which provide a in a case in which an error signal has been asserted after the
TV having a thin shape and a large size, are becoming popular 10 completion of the soft start period in which the soft start
as replacements for CRT-based TVs. Liquid crystal display Voltage is raised, the Soft start circuit is reset and the striking
TVs include multiple cold cathode fluorescent lamps (which operation is performed. Thus, such an embodiment prevents
the striking operation when the EEFL is emitting light.
will be referred to as “CCFLs”hereafter) or external electrode Also, the Striking control circuit may include a counter
fluorescent lamps (which will be referred to as “EEFLS” 15 which counts the number of times the soft start circuit has
hereafter) arranged on the back face of a liquid crystal panel been reset. Also, in a case in which the count value has
on which video images are to be displayed, which are used as reached a predetermined value, the soft start circuit may be
light-emitting backlights. prevented from being reset. Such an arrangement is capable
The CCFL or EEFL is driven using an inverter (DC/AC of limiting the number of times the striking operation is
converter) which boosts DC voltage of around 12 V. and performed.
which outputs the voltage thus boosted in the form of AC Such an arrangement may allow the predetermined value to
voltage, for example. The inverter converts the current flow be selected from among multiple values. In this case, by
ing through the CCFL into Voltage, and returns the Voltage setting the number of times the Striking operation can be
thus converted to a control circuit as a feedback Voltage, performed according to the probability that the EEFL will
thereby controlling the ON/OFF operation of a switching 25 emit light, Such an arrangement allows the EEFL to emit light
element based upon this feedback Voltage. For example, a in a Sure manner.
CCFL driving technique using Such an inverter is disclosed in Also, the soft start circuit may include: a capacitor, one
Patent document 1. terminal of which is set to a fixed electric potential; a current
Patent Document 1 Source which charges the capacitor, and a first comparator
Japanese Patent Application Laid Open No. 2003-323994 30 which compares the soft start Voltage, which occurs at the
EEFLs have a problem in that it is difficult to turn on an other terminal of the capacitor, with a predetermined first
EEFL as compared with other fluorescent lamps such as threshold voltage. Also, when the soft start circuit is reset, the
CCFLs. Whether or not the EEFL is switched to a light striking control circuit may switch an initializing Switch,
emission state is a matter of probability. Accordingly, in order provided between the one terminal of the capacitor and a fixed
to ensure that the EEFL emits light, conventional inverters 35 voltage terminal, to the ON state, and when the soft start
repeatedly perform a start-up operation several times, thereby Voltage is reduced to a predetermined threshold Voltage, the
raising the probability of light emission. Specifically, in order striking control circuit may switch the initializing Switch to
to perform EEFL striking, conventional inverters repeatedly the OFF state.
perform an operation in which high Voltage is applied to the Another embodiment of the present invention relates to an
inverter and the inverter is shut down. 40 inverter. The inverter includes: a transformer; any one of the
Such conventional techniques require an external circuit above-described control circuits which control the switching
which repeatedly performs the shut down operation and the of the Voltage at the primary coil of the transformer, and a
start-up operation of a control circuit for the inverter, in addi voltage detection unit which detects the output voltage of the
tion to the control circuit. This leads to a large circuit area and inverter, which is generated at the secondary coil of the trans
high costs. 45 former, and which outputs a voltage that corresponds to the
output Voltage to the control circuit.
SUMMARY OF THE INVENTION Yet another embodiment of the present invention relates to
a light emitting apparatus. The light emitting apparatus
The present invention has been made in order to solve the includes an EEFL and the above-described inverter which
aforementioned problem. Accordingly, it is a general purpose 50 supplies the output voltage thereof to the EEFL.
of the present invention to provide a low-cost or Small-area Yet another embodiment of the present invention relates to
control circuit for an inverter which allows an EEFL to emit a liquid crystal display apparatus. The liquid crystal display
light in a Sure manner. apparatus includes: a liquid crystal panel; an EEFL provided
An embodiment of the present invention relates to a control as a backlight for the liquid crystal panel; and the above
circuit for an inverter which drives an external electrode fluo 55 described inverter, the output voltage of which is supplied to
rescent lamp (EEFL) connected to a secondary line of a the EEFL.
transformer. The control circuit includes: a soft start circuit Yet another embodiment of the present invention relates to
which generates a soft start Voltage which changes over time a control method for an inverter which drives an EEFL. The
when igniting the EEFL; a pulse modulator which receives a control method includes: generating a soft start Voltage which
feedback Voltage that corresponds to the output Voltage of the 60 changes overtime when igniting the EEFL, adjusting the duty
inverter and the soft start Voltage, and which adjusts the duty ratio of a pulse signal Such that a feedback Voltage that cor
ratio of a pulse signal Such that the feedback Voltage matches responds to the output voltage of the inverter matches the soft
the soft start voltage; a driver which controls the switching of start Voltage; controlling the Switching of the Voltage at a
the Voltage at a primary coil of the transformer according to primary coil of a transformer according to the pulse signal;
the pulse signal output from the pulse modulator, and a strik 65 and monitoring an error signal which is asserted when an
ing control circuit which monitors an error signal which is abnormal state occurs, and striking the EEFL by initializing
asserted when an abnormal state occurs, and which resets and the soft start Voltage and by changing the Soft start Voltage
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over time when the error signal has been asserted at a detec crystal display TV 300 is connected to an antenna 310. The
tion timing after the Soft start Voltage has reached a threshold antenna 310 receives broadcast waves, and outputs a received
Voltage. signal to a reception unit 304. The reception unit 304 detects
It is to be noted that any arbitrary combination or rear and amplifies the received signal, and outputs the received
rangement of the above-described structural components and signal thus detected and amplified to a signal processing unit
So forth is effective as and encompassed by the present 306. The signal processing unit 306 demodulates the modu
embodiments. lated data, and outputs the image data obtained by the
Moreover, this Summary of the invention does not neces demodulation to a liquid crystal panel driver 308. The liquid
sarily describe all necessary features so that the invention crystal panel driver 308 outputs the image data to a liquid
may also be a sub-combination of these described features. 10 crystal panel 302 in increments of scanning lines, thereby
displaying video images and still images. Multiple light emit
BRIEF DESCRIPTION OF THE DRAWINGS ting apparatuses 200 are arranged as a backlight on the back
face of the liquid crystal panel 302. The light emitting appa
Embodiments will now be described, by way of example ratus 200 according to the present embodiment is suitably
only, with reference to the accompanying drawings which are 15 employed as a backlight for Such a liquid crystal panel 302.
meant to be exemplary, not limiting, and wherein like ele Returning to FIG.1, detailed description will be made below
ments are numbered alike in several Figures, in which: regarding the configuration and the operation of the light
FIG. 1 is a circuit diagram which shows a configuration of emitting apparatus 200.
a light emitting apparatus according to an embodiment of the The light emitting apparatus 200 according to the present
present invention; embodiment includes an EEFL 210, a first inverter 100a, and
FIG. 2 is a block diagram which shows a configuration of a a second inverter 100b. The EEFL210 is arranged on the back
liquid crystal display TV mounting the light emitting appa face of the liquid crystal panel 302. The first inverter 100a and
ratus shown in FIG. 1; the second inverter 100bare DC/AC converters which convert
FIG. 3 is a circuit diagram which shows a configuration of the input voltage Vin, which is output from a DC power
a pin layout of a control circuit and a configuration of a 25 Supply and is input to an input terminal 102, into AC Voltages,
peripheral circuit; boost the AC voltages thus converted, and supply the AC
FIG. 4 is a circuit diagram which shows a part of the Voltages thus boosted to a first terminal 212 and a second
configuration of the control circuit; terminal 214 as a first driving voltage VdrV1 and a second
FIG. 5 is a circuit diagram which shows a part of the driving voltage VdrV2, respectively. The first driving voltage
configuration of the control circuit; 30 VdrV1 and the second driving voltage V drv2 are AC voltages
FIG. 6 is a first time chart which shows the operation of the having opposite phases.
control circuit; In FIG. 1, a single EEFL 210 is shown. Also, multiple
FIG. 7 is a second time chart which shows the operation of EEFLs 210 may be arranged in parallel. Description will be
the control circuit; and made below regarding the configuration of the first inverter
FIG. 8 is a third time chart which shows the operation of the 35 100a and the second inverter 100b according to the present
control circuit. embodiment. The first inverter 100a and the second inverter
100b have the same configuration. Accordingly, description
DETAILED DESCRIPTION OF THE INVENTION will be made below with these inverters collectively referred
to as the “inverter 100' without distinguishing the one from
The invention will now be described based on preferred 40 the other.
embodiments which do not intend to limit the scope of the The inverter 100 includes an H-bridge circuit 10, a trans
present invention but exemplify the invention. All of the fea former 12, a current/voltage conversion unit 14, a driving
tures and the combinations thereof described in the embodi voltage detection unit 20, a control circuit 30, and a capacitor
ment are not necessarily essential to the invention. C10.
In the present specification, the state represented by the 45 The H-bridge circuit 10 includes four power transistors,
phrase “the member A is connected to the member B' i.e., a first high-side transistor MH1, a first low-side transistor
includes a state in which the member A is indirectly con ML1, a second high-side transistor MH2, and a second low
nected to the member B via another member that does not side transistor ML2.
affect the electric connection therebetween, in addition to a One terminal of the first high-side transistor MH1 is con
state in which the member A is physically and directly con 50 nected to the input terminal 102 to which the input voltage Vin
nected to the member B. In the same way, the state repre is applied, and the other terminal thereof is connected to the
sented by the phrase “the member C is provided between the first terminal of a primary coil 12a of the transformer 12. One
member A and the member B' includes a state in which the terminal of the first low-side transistor ML1 is connected to
member A is indirectly connected to the member C, or the the ground terminal at which the electric potential is set to a
member B is indirectly connected to the member C via 55 fixed electric potential, and the other terminal thereof is con
another member that does not affect the electric connection nected to the first terminal of the primary coil 12a. One
therebetween, in addition to a state in which the member A is terminal of the second high-side transistor MH2 is connected
directly connected to the member C, or the member B is to the input terminal 102, and the other terminal thereof is
directly connected to the member C. connected to the second terminal of the primary coil via the
Also, each symbol which denotes the corresponding ter 60 DC-current blocking capacitor C10. One terminal of the sec
minal (pin) is also used as a symbol which indicates the signal ond low-side transistor ML2 is connected to the ground ter
output from the terminal. minal, and the other terminal thereof is connected to the
FIG. 1 is a circuit diagram which shows a configuration of second terminal of the primary coil 12a via the DC-current
a light emitting apparatus 200 according to an embodiment of blocking capacitor C10.
the present invention. FIG. 2 is a block diagram which shows 65 The current/voltage conversion unit 14 is provided on a
a configuration of a liquid crystal display TV 300 mounting current path of a secondary coil 12b of the transformer 12.
the light emitting apparatus 200 shown in FIG.1. The liquid The current/voltage conversion unit 14 converts the current
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5 6
flowing through the secondary coil 12b, i.e., the current flow First, referring to FIG. 4, a power supply voltage VCC is
ing through the EEFL 210, into voltage, and outputs the applied to a power Supply terminal VCC. A ground terminal
Voltage thus converted as a current detection signal IS. The GND is connected to an external terminal at the ground elec
current/voltage conversion unit 14 includes a rectification tric potential. A UVLO signal, which is asserted when the
circuit 16 and a filter 18. power Supply Voltage VCC is low, is input to a low-voltage
The rectification circuit 16 includes diodes D1 and D2 and lockout terminal UVLO. A standby signal is input to a
a resistor R1. The anode of the diode D1 is grounded, and the standby terminal STB. The ON/OFF operation of a reference
cathode thereof is connected to one terminal of the secondary Voltage source 32 is controlled according to the standby Sig
coil 12b. The anode of the diode D2 is connected to the nal STB. The reference voltage source 32 generates a refer
cathode of the diode D1. The resistor R1 is provided between 10 ence voltage REF4V of 4V, and supplies the reference voltage
the cathode of the diode D2 and the ground. The AC current REF4V to each block of the control circuit 30 and an external
that flows through the secondary coil 12b is half-wave recti circuit via a terminal REF4V.
fied by the diodes D1 and D2, and the current thus half-wave A Soft start circuit 40 generates a Soft start Voltage
rectified flows through the resistor R1. A voltage drop occurs VREF SS which changes over time when the EEFL performs
at the resistor R1 in proportion with the current that flows 15 light emission. A soft start terminal SS is connected to a soft
through the secondary coil 12b. The rectification circuit 16 start capacitor Css. A current source 42 charges the Soft start
outputs the Voltage drop that occurs at the resistor R1. capacitor CSS, thereby generating the Soft start Voltage
The filter 18 is a low-pass filter including a resistor R2 and VREF SS which gradually rises over time. A discharge
a capacitor C1. The filter 18 feeds back the current detection switch 44 is provided between the SS terminal and the
signal IS, which is obtained by removing a high-frequency ground, and discharges the charge stored in the soft start
component from the output Voltage of the rectification circuit capacitor Css when the discharge switch 44 is in the ON state,
16, to a current feedback terminal IS of the control circuit 30. thereby initializing the soft start voltage VREF SS. When a
The driving Voltage detection unit 20 has a configuration latch signal SL is asserted (i.e., set to the high-level state) or
including a rectification circuit 22 and a filter 24, and is a reset signal SR is negated (i.e., set to the low-level state), the
provided between an output terminal 104 of the inverter 100 25 discharge switch 44 is switched to the ON state.
and the ground. The driving Voltage detection unit 20 gener A first comparator 46 compares the soft start Voltage
ates, in the form of a DC voltage, a Voltage detection signal VREF SS with a predetermined first threshold voltage Vth 1.
VS that corresponds to the driving voltage VdrV output from When VREF SS is greater than Vth 1, the first comparator 46
the inverter 100, and feeds back the voltage detection signal outputs a soft start end signal SS end at the high level. That is
VS to a voltage feedback terminal VS of the control circuit 30. 30 to say, the Soft startend signal SS end is asserted at the timing
The rectification circuit 22 includes capacitors C2 and C3. at which the soft start operation is completed.
diodes D3 and D4, and resistors R3 and R4. The capacitors C2 The current detection signal IS fed back to the feedback
and C3 are connected in series between the output terminal terminal IS is input to the non-inverting input terminal of a
104 and the ground. The anode of the diode D3 is grounded, first error amplifier 50. The first error amplifier 50 includes
and the cathode thereof is connected to a connection node that 35 two inverting input terminals, one of which receives a refer
connects the capacitor C2 and the capacitor C3. Furthermore, ence Voltage of 1.25 V as an input Voltage. A computation
the anode of the diode D4 is connected to the cathode of the amplifier 52 is a buffer which receives a voltage VREF input
diode D3. The resistors R3 and R4 are connected in series from an external circuit via a reference terminal VREF. The
between the cathode of the diode D4 and the ground. The computation amplifier 52 outputs the reference voltage VREF
driving voltage VdrV, which is output from the output termi 40 thus received to the other inverting input terminal of the first
nal 104, is AC voltage, and is divided by the capacitors C2 and error amplifier 50.
C3. The driving voltage V drv thus divided is half-wave rec The first error amplifier 50 selects the lower of the two
tified by the diodes D3 and D4, and is further divided by the Voltages input to the two inverting input terminals, and ampli
resistors R3 and R4. The driving voltage thus divided by the fies the difference between the lower voltage thus selected
resistors R3 and R4 is output to the filter 24. 45 and the current detection signal IS input to the non-inverting
The filter 24 feeds back the voltage detection signal VS, input terminal. That is to say, when the reference Voltage
which is obtained by removing a high-frequency component VREF thus supplied is greater than 1.25 V, the reference
from a signal output from the rectification circuit 22, to the voltage VREF is not used, and the feedback operation is
control circuit 30. The filter 24 may be configured employing performed such that the current detection signal IS matches
a resistor and a capacitor as with the filter 18. 50 the reference voltage of 1.25 V. When the reference voltage
The control circuit 30 controls the ON/OFF operations of VREF is set to a voltage smaller than 1.25 V, the feedback
the first high-side transistor MH1, the first low-side transistor operation is performed Such that the current detection signal
ML1, the second high-side transistor MH2, and the second IS matches the reference voltage VREF. That is to say, the
low-side transistor ML2 of the H-bridge circuit 10 according lamp dimming operation (current dimming) can be per
to the current detection signal IS and the Voltage detection 55 formed by changing the reference voltage VREF in a range
signal VS thus fed back. By controlling the H-bridge circuit Smaller than 1.25 V according to an external instruction.
10, a Switching Voltage is Supplied to the primary coil 12a of The control circuit 30 provides a burst dimming function.
the transformer 12. As a result, energy conversion is per A current source 74 generates a constant current, which flows
formed at the transformer 12, and the first driving voltage into the IS terminal via a diode 75. A switch 76 is provided
VdrV1 is supplied to the EEFL 210 connected to the second 60 between the anode of the diode and the ground terminal.
ary coil 12b. When the signal obtained by inverting the burst signal SB is at
Description will be made below regarding the configura the high level, or when a protection detection signal ST is at
tion of the control circuit 30. FIG.3 is a circuit diagram which the high level, the switch 76 is set to the ON state. That is to
shows a pin layout of the control circuit 30 and a configura say, the switch 76 is switched between the ON state and the
tion of peripheral circuits. FIG. 4 and FIG. 5 are circuit 65 OFF state according to the level of the burst signal SB.
diagrams which show the configuration of the control circuit When the Switch 76 is switched to the ON state, the current
30 according to the present embodiment. generated by the current source 74 flows into the ground via
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7 8
the switch 76. Accordingly, the electric potential at the IS old used to detect whether or not the lamp is in the low current
terminal is set to the current detection signal IS that corre state can be changed according to the target value of the lamp
sponds to the lamp current, and the feedback operation is Current.
performed such that the current detection signal IS matches The voltage detection signal VS fed back to the feedback
the reference Voltage. When the switch 76 is switched to the terminal VS is input to the non-inverting input terminal of a
OFF state, the current generated by the current source 74 second error amplifier 56. A predetermined reference voltage
flows into the IS terminal, which raises the electric potential Vref1 is input to the inverting input terminal of the second
at the IS terminal up to around the power supply voltage. This error amplifier 56. The second error amplifier 56 amplifies the
disables the feedback operation. As a result, the lamp stops difference between the voltage detection signal VS and the
light emission. 10 reference voltage Vref1. The error Voltage Verr2 output from
Thus, the lamp repeatedly Switches the light emission state the second error amplifier 56 is input to the base of a second
between the ON state and the OFF state according to the burst transistor Q2 having a grounded emitter. The second transis
signal SB. Thus, the luminance thereof is controlled accord tor Q2 includes two collector terminals.
A pulse modulator 60 includes a PWM comparator 61, an
ing to the duty ratio of the burst signal SB. 15 oscillator 70, and a hysteresis comparator 72. The pulse
The burst signal SB is generated by a burst signal generat modulator 60 receives a feedback voltage FB that corre
ing circuit 94. A burst dimming oscillator 95 generates a sponds to the output voltage of the inverter 100 and the soft
sawtooth wave signal having a frequency that corresponds to start voltage VREF SS, and generates a pulse signal PWM
the capacitor connected to a BCT terminal and a resistor having a duty ratio fed back such that the feedback voltage FB
connected to a BRT terminal. matches the soft start voltage VREF SS.
A duty terminal DUTY receives eitheran analog voltage or The collector of the first transistor Q1 and one of the
a cyclic signal (pulse signal) as an input signal. In a case in collectors of the second transistor Q2 are connected to each
which the analog Voltage is input, a burst dimming compara other so as to form a common terminal which is connected to
tor 96 makes a comparison between the sawtooth wave signal the non-inverting input terminal of the PWN comparator 61.
generated at the BCT terminal and the voltage level of the 25 Furthermore, the common terminal thus formed is connected
duty terminal DUTY, and generates the burst signal SB. In a to the feedback terminal FB.
case in which a frequency signal is input, the burst dimming The third transistor Q3 is a PNP bipolar transistor, the
comparator 97 compares the cyclic signal with a reference collector of which is grounded, and the base of which receives
Voltage, and generates the burst signal SB. A selector terminal a reference voltage. The third transistor Q3 is provided in
DSEL receives a logical signal as an input signal which indi 30 parallel with the first transistor Q1 and the second transistor
cates which of the analog signal or the cyclic signal is input to Q2. The emitter of the third transistor Q3 is connected to the
the DUTY terminal. A selector 98 selects the output from the collectors of the first transistor Q1 and the second transistor
burst dimming comparator 96 or from the burst dimming Q2. A current Source 62 supplies a constant current to the
comparator 97 according to the level of the selector terminal three transistors Q1 through Q3.
35 The first transistor Q1 and the second transistor Q2 form a
DSEL. The burst signal SB thus selected by the selector 98 is so-called minimum value circuit, which selects the lower of
supplied to the aforementioned switch 76. Furthermore, the the two error voltages Verr1 and Verr2, and outputs the lower
burst signal SB is output to an external circuit via a duty Voltage thus selected to the non-inverting input terminal of the
output terminal DUTY OUT. The duty ratio of the burst duty PWM comparator 61. The aforementioned soft start voltage
signal SB changes according to the signal Supplied to the 40 VREF SS is input to the other non-inverting terminal of the
DUTY terminal, thereby allowing the luminance of the lamp PWM comparator 61.
to be adjusted. A current source 64 Supplies a constant current to one
An error voltage Verr1 output from the first error amplifier collector of the second transistor Q2. The voltage that corre
50 is input to the base of a first transistor Q1. sponds to the Voltage detection signal VS occurs at this col
The current detection signal IS is input to the non-inverting 45 lector. An overVoltage detection comparator 58 compares a
terminal of a current comparator 54. The current comparator predetermined threshold voltage Vth 10 with the collector
54 includes two inverting terminals, one of which receives a Voltage of the second transistor Q2, and outputs the compari
threshold voltage of 0.625 V as an input voltage. Further son result as an overvoltage detection signal VS High. When
more, the reference voltage VREF output from the computa the Voltage applied to the lamp is greater than the threshold
tion amplifier 52 is divided by the resistors, and the reference 50 Voltage, the overvoltage detection signal VS High is
voltage VREF thus divided is input to the other inverting input asserted.
terminal of the computation amplifier 52. An error signal, which is asserted when an overvoltage is
The current comparator 54 compares the current detection applied, is input to a comparison terminal COMP. A hyster
signal IS input to the non-inverting terminal thereof with the esis comparator 66 makes a comparison between an error
lower of the two Voltages input to the two inverting input 55 signal COMP and a threshold voltage Vth 12 of 4V, and out
terminals. The output of the current comparator 54 is inverted puts a comparison signal COMPH which is asserted (set to the
by an inverter 55, and is output as a low current detection high-level state) when an overvoltage is applied.
signal IS Low. When the current detection signal IS becomes The oscillator 70 generates a sawtooth wave signal Vsaw,
smaller than the threshold voltage, i.e., when the current that having a frequency that corresponds to a resistor connected to
flows through the lamp becomes smaller than the threshold 60 an RT terminal, by repeatedly performing a charge/discharge
value, the low current detection signal IS Low is asserted. operation, and outputs the Sawtooth wave signal V saw to the
When VREF is greater than 1.25 V, the current detection inverting input terminal of the PWM comparator 61.
signal IS is compared with the fixed threshold voltage of The oscillator 70 is configured such that it can operate in a
0.625 V. When VREF is smaller than 1.25 V, the current master mode and in a slave mode. In the slave mode, a pulse
detection signal IS is compared with a threshold value which 65 signal is input to a synchronous input terminal CT SYN
is proportional to the reference voltage VREF. That is to say, C IN. The hysteresis comparator 72 performs wave-shaping
in the aforementioned current dimming operation, the thresh on the pulse signal, and outputs the pulse signal thus wave
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9 10
shaped to the oscillator 70. The oscillator 70 generates a generates the logical AND of the output signal of the OR gate
sawtooth wave signal V saw synchronously with the output 510 and the burst signal SB. The AND gate 512 has a function
signal (pulse signal) of the hysteresis comparator 72. of masking the result of the low-level detection using the burst
In the master mode, the oscillator 70 performs self-oscil signal SB. That it to say, the low-level detection is disabled
lation so as to generate a sawtooth wave signal Vsaw, and 5 during a period in which the lamp stops light emission accord
outputs, via a synchronous output terminal CT SYNC OUT. ing to the burst signal SB. An OR gate 514 receives the
a synchronous signal that corresponds to the cycle of the IS Low signal, the VS High signal, the COMPH signal, and
sawtooth wave signal Vsaw. the output of the AND gate 512 as input signals, and outputs
The PWM comparator 61 compares the lower of the volt the logical AND of these signals as an error signal. That is to
ages input to the two non-inverting input terminals with the 10 say, in a case in which an abnormal state has occurred, the
sawtooth wave signal Vsaw so as to generate a pulse width error signal ERROR is asserted.
modulation signal (PWM signal). When the state in which the error signal ERROR has been
A driver 80 drives the high-side transistors MH1 and MH2 negated, i.e., the state in which an error State has not occurred,
and the low-side transistors ML1 and ML2, which are pro continues for a predetermined period, the error cancel detec
vided in the form of external components, according to the 15 tion timer 520 asserts the latch signal SL.
PWM signal. An AND gate 82 generates the logical AND of An AND gate 522 masks the error signal ERROR using the
the PWM signal and the output signal of the hysteresis com striking end signal STRC end and the soft-start end signal
parator 72. The output of the AND gate 82 is inverted by the SS end, and outputs the error signal ERROR thus masked as
inverter 83, and is input to a first driver 86. The first driver 86 a protection detection signal ST. A transistor M51 is con
drives the first high-side transistor MH1. A second driver 88 nected to a Fail terminal in an open-drain fashion. The pro
drives the first low-side transistor ML1 according to the out tection detection signal ST is input to the gate of the transistor
put signal of the AND gate. M51. That is to say, when the protection detection signal ST
A second driver 90 and a second driver 92 drive the second is asserted, the FAIL terminal is set to the low-level state.
high-side transistor MH2 and the second low-side transistor When the protection detection signal ST is negated, the Fail
ML2, respectively. 25 terminal is set to the high-impedance state.
The above-described configuration provides the soft-start A capacitor Cop is connected to a CP terminal. A current
operation, the current dimming operation, and the burst dim Source 530 generates a constant current, and charges the
ming operation. capacitor Cep. ACP-terminal comparator 532 compares the
An LED driving circuit 400 drives a light-emitting diode electric potential at the CP terminal with a second threshold
(LED) connected to an SSW terminal. The emitter of a fourth 30 voltage V th2 of 4V. The output of the comparator 532 is input
transistor Q4 is grounded via a ground terminal SSGND, and to the set terminal of an RS flip-flop 534. Furthermore, the
the collector thereof is connected to the cathode of the LED reset signal SR is input to the resetterminal of the RS flip-flop
via the SSW terminal. A current source 402 charges a capaci 534. That is to say, when the electric potential at the CP
tor Cssw connected to a TSSW terminal. A timer comparator terminal exceeds 4 V, the RS flip-flop is set. When the reset
404 compares the electric potential at the TSSW terminal 35 signal SR is asserted, the RS flip-flop 534 is reset. The latch
with a threshold voltage V th5 (e.g., 4V). A timer comparator signal SL is output from the output terminal Q of the RS
404 sets the fourth transistor Q4 to the ON state so as to flip-flop 534.
instruct the LED to emit light during a period in which the An initializing switch 536 is provided between the CP
electric potential at the TSSW terminal is smaller than the terminal and the ground terminal. When the protection detec
threshold voltage V th5. The LED is provided in order to raise 40 tion signal ST is asserted, the initializing switch 536 is
the probability that the EEFL will emit light. switched to the ON state, which discharges the charge stored
An SRT terminal is connected to the RT terminal via an in the capacitor Cep, thereby initializing the electric potential
external resistor R50. A transistor M50 is provided between at the CP terminal. During a period in which the protection
the SRT terminal and the ground terminal. When at least one detection signal ST has been negated (a period in which an
of the IS Low signal or the COMPH signal is asserted, the 45 abnormal state has not occurred), the initializing switch 536 is
transistor M50 is Switched to the ON State. maintained in the OFF state, which charges the capacitor Cep,
Next, description will be made with reference to FIG.5. An thereby raising the electric potential at the CP terminal over
error detection circuit 500 includes an error signal generating time. When the electric potential at the CP terminal reaches
unit 501 and an error cancel detection timer 520. the second threshold voltage V th2, the latch signal SL is
The error signal generating unit 501 detects whether or not 50 asserted.
an abnormal state has occurred in the inverter 100, and gen The above-described is the configuration of the error detec
erates an error signal ERROR which is asserted when an tion circuit 500.
abnormal state occurs. When the light-emission operation of the EEFL is started,
A low-level detection circuit 502 detects whether or not the control circuit 30 performs a striking operation, i.e.,
voltages LCP1 and LCP2 supplied from an external circuit 55 repeatedly performs several times an operation in which high
are smaller than predetermined threshold voltages voltage is applied to the EEFL. A striking control circuit 550
LCP1 REF1 and LCP2. REF2, respectively. A low-level is provided in order to control the striking operation.
detection comparator 504 compares the reference voltage The striking control circuit 550 monitors the error signal
LCP1 REF with the electric potential at an LCP1 terminal, ERROR which is asserted in a case in which an abnormal state
and generates a low-level detection signal which is Switched 60 has occurred. In a case in which the error signal ERROR has
to the high-level state when LCP1 is smaller than LCP1 REF. been asserted at a detection timing after the soft start Voltage
Similarly, the same applies to the operation performed by the VREF SS has reached the threshold voltage Vth 1, the strik
low-level detection comparator 506. Such an arrangement ing control circuit 550 resets and restarts the soft start circuit
allows the user of the control circuit 30 to supply desired 40.
voltages to the LCP1 terminal and the LCP2 terminal. 65 The striking control circuit 550 generates a discharge sig
The outputs of the low-level detection comparators 504 nal dis which is asserted at the resettiming. A first initializing
and 506 are input to an OR gate 510. An AND gate 512 switch SW1 is provided between an SS terminal and the
 US 8,044,604 B2
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ground terminal. When the first initializing switch SW1 is counts the number of times the output Q is switched to the
Switched to the ON state according to the discharge signal dis. high-level state. When the counted number reaches a prede
the soft start circuit 40 is initialized, thereby restarting the termined number n (-2), the counter 580 asserts the judgment
generation of the soft start voltage VREF SS (restart opera end signal judge stop. The count value counted by the
tion). counter 580 is reset to Zero according to the standby signal
A timing setting circuit 552 sets the aforementioned detec STB and the UVLO signal.
tion timing, and detects the timing at which the striking opera The above-described is the configuration of the control
tion has ended. circuit 30. Next, description will be made regarding the
A striking capacitor Cstrc is connected to a capacitor ter operation thereof. FIG. 6 is a first time chart which shows the
minal TSTRC. A current source 554 generates a constant 10 operation of the control circuit 30. FIG. 6 shows the standby/
current, and charges the capacitor Cstrc. A comparator 556 UVLO signals, the lamp voltage waveform, the soft start
compares the electric potential at the TSTRC terminal with a voltage VREF SS, the electric potential at the STRC termi
predetermined third threshold voltage V th;3, and generates a nal, the electric potential at the CP terminal, the error signal
judgment signal STRC judge which is asserted at the detec ERROR, the electric potential at the TSSW terminal, and the
tion timing. The detection timing is adjusted according to a 15 state of the Fail terminal, in this order from the top.
period in which the electric potential at the TSTRC terminal At the point in time t0, the standby/UVLO signals are
reaches the threshold voltage V th;3. The detection timing is asserted, which starts up the soft start circuit 40, and the soft
set to a timing after the timing at which the Soft-start end start voltage VREF SS thereby starts to rise over time. At the
signal SS end is asserted. point in time t2 after the passage of the soft start period Tss,
A comparator 558 compares the electric potential at the the soft start end signal SS end is asserted. The timing setting
TSTRC terminal with a predetermined fourth threshold volt circuit 552 in the striking control circuit 550 starts to charge
age Vitha, and generates a striking end signal STRC end the TSTRC terminal from the point in time to, thereby raising
which indicates whether or not the striking operation has the electric potential at this terminal over time. At the point in
ended. time t3 after the passage of a predetermined period of time
Comparators 560, 562, and 564 detect whether or not the 25 Tstrc (Tstrc-Tss) after the point in time to, the judgment
electric potentials at the SS terminal, the TSSW terminal, and signal STRC judge is asserted. The point in time t3 corre
the TSTRC terminal, respectively, have been reduced to a sponds to the aforementioned detection timing.
predetermined threshold voltage (0.2 V), i.e., whether or not In a situation in which an abnormal circuit state of some
the capacitors connected to these terminals have been dis kind occurs at the point in time t1, the error signal ERROR is
charged in a sure manner. An AND gate 566 outputs the 30 asserted. The time chart shown in FIG. 6 shows the operation
logical AND of the outputs of the three comparators 560,562, in a case in which a circuit abnormal state has continued to
and 564, as a discharge end signal discharge OK. occur. At the detection timing t3, the error signal ERROR is
In the basic operation, in a case in which the error signal asserted. Accordingly, the initializing circuit 570 asserts the
ERROR has been asserted when the judgment signal discharge signal dis, which Switches the states of the initial
STRC judge is asserted, an initializing circuit 570 asserts the 35 izing switches SW1 through SW3 in the computation ampli
discharge signal dis So as to initialize and the restart the soft fier 52, thereby initializing the soft start circuit 40. When the
start circuit 40. electric potentials at the SS terminal, the STRC terminal, and
An AND gate 572 generates the logical AND of the error the TSSW terminal are sufficiently reduced, the discharge end
signal ERROR and the soft-startend signal SS end. That is to signal discharge OK is asserted.
say, the AND gate 572 masks the error signal ERROR in a 40 When the soft start circuit 40 is reset at the point in time t2.
case in which it has been asserted before the completion of the the count value counted by the counter 580 is incremented.
Soft start operation. When the discharge end signal discharge OK is asserted,
An AND gate 574 generates the logical AND of the judg the initializing circuit 570 negates the discharge signal dis.
ment signal STRC judge and a judgment end signal After the discharge signal dis is negated, the initializing
judge stop. When the number of times the soft start circuit 40 45 switches SW1 through SW3 in the timing setting circuit 552
has been initialized (the number of times the striking opera are switched to the OFF state. Accordingly, the soft start
tion has been performed) reaches a predetermined number, circuit 40 is restarted, thereby raising the soft start voltage
the judgment end signal judge stop is asserted. That is to say, VREF SS over time.
the judgment signal STRC judge is masked using the judg The operation from the point in time t3 up to the point in
ment end signal judge stop, thereby preventing the number 50 time ta is the same as that from the point in time to up to the
of times the striking operation is performed from becoming point in time t3. That is to say, after the passage of the
equal to or greater than the predetermined number. predetermined period of time Tstrc after the point in time t3.
An AND gate 576 generates the logical AND of the outputs the judgment signal STRC judge is asserted again. Also, at
of the AND gates 572 and 574, and outputs the logical AND the detection timing of the point in time ta, the error signal
thus generated to the set terminal of an RS flip-flop 578. The 55 ERROR has been asserted. Accordingly, the discharge signal
discharge end signal discharge OK is input to the resetter dis is asserted again, thereby initializing the Soft start circuit
minal of the RS flip-flop 578. 40. Furthermore, the count value counted by the counter 580
ANAND gate 582 generates the NAND of the soft startend is incremented. When the count value reaches an upper limit
signal SS end and the striking end signal STRC end. An value n=2, the judgment end signal judge stop is asserted. An
AND gate 584 masks the output signal Q of the RS flip-flop 60 arrangement may be made which allows the value of n to be
578 using the mask signal (NAND) generated by the NAND selected from among multiple values. The selection operation
gate 582. That is to say, when both the soft-start end signal may be performed by writing data to a register which sets the
SS end and the striking end signal STRC end have been in value.
negated, the discharge signal dis is fixed at the low level. At the next detection timing t5, the error signal ERROR is
Furthermore, the output signal Q of the RS flip-flop 578 is 65 masked, and accordingly, the discharge signal dis is not
switched to the high-level state every time an instruction is asserted, and the electric potential at the STRC terminal
given to initialize the soft start circuit 40. A counter 580 thereby continues to be raised. When the electric potential at
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the STRC terminal exceeds the fourth threshold voltage Vitha low-level state of the signals, have been described for exem
at the point in time té, the error cancel detection timer 520 plary purposes only. The settings can be freely modified by
asserts the striking end signal STRC end. Upon reception of inverting the signals using inverters or the like.
the striking end signal STRC end thus asserted, the protec Description has been made in the embodiment regarding
tion detection signal ST is asserted, which switches the tran an arrangement in which two inverters 100 are connected to
sistor M51 to the ON state, thereby switching the fail terminal both terminals of the EEFL 210, and the EEFL 210 is driven
FAIL to the low-level state. Furthermore, when the protection with driving Voltages having opposite phases. However, the
detection signal ST is asserted at the point in time té, the present invention is not restricted to Such an arrangement.
charge operation for the CP terminal is started. This asserts Also, an arrangement may be made in which one terminal of
the latch signal SL at the point in time t7 after the passage of 10 the EEFL 210 is set to a fixed voltage, and the EEFL 210 is
a predetermined period of time Tcp, thereby shutting down driven by a single inverter 100.
the control circuit 30. In the embodiment, the soft start circuit 40 is configured as
As described above, with the inverter 100 according to the an analog circuit using the soft start capacitor CSS. However,
embodiment, in a case in which the error signal ERROR has the present invention is not restricted to Such an arrangement.
been asserted at a predetermined timing after the start of the 15 Also, the soft start circuit 40 may have a configuration includ
soft start operation, the soft start circuit 40 can be reset and ing a signal generator which generates a digital signal having
restarted. a signal value which changes according to the soft start Volt
Furthermore, by counting the number of times the striking age Vss shown in FIG. 4 and a D/A converter which performs
operation is repeatedly performed using the counter 580 thus digital/analog conversion of the output of the signal genera
provided, such an arrangement allows an upper limit of the tor. Also, the several timer circuits, each of which performs a
number of times the Striking operation is performed to be set. timing operation by charging a capacitor, may be replaced by
FIG. 7 is a second time chart which shows the operation of a counter which counts a clock signal.
the control circuit 30. The operation from the point in time to While the preferred embodiments of the present invention
up to the point in time t3 shown in FIG. 7 is the same as that have been described using specific terms, such description is
shown in FIG. 6. At the point in time t3, the circuit abnormal 25 for illustrative purposes only, and it is to be understood that
state is eliminated, and the error signal ERROR is negated. At changes and variations may be made without departing from
the Subsequent detection timing ta, the discharge signal dis is the spirit or Scope of the appended claims.
not asserted. Accordingly, the electric potential at the STRC
terminal continues to rise, and reaches the fourth threshold What is claimed is:
voltage Vitha at the point in time t9, at which the striking end 30 1. A control circuit for an inverter which drives an external
signal STRC end is asserted. At this time, the error signal electrode fluorescent lamp connected to a secondary line of a
ERROR has been negated, and accordingly, the protection transformer, the control circuit comprising:
detection signal ST is not asserted, thereby maintaining the a soft start circuit structured to generate a soft start Voltage
fail signal FAIL in the open state. This is a point of difference which changes over time when the external electrode
from the operation shown in the time chart in FIG. 6. At the 35 fluorescent lamp is ignited;
point in time t10 after the passage of the LED light-emission a pulse modulator structured to receive a feedback Voltage
period TLED ON set by the timer comparator 404 after the that corresponds to the output Voltage of the inverter and
point in time t3, the fourth transistor Q4 is switched to the the soft start Voltage, and structured to adjust the duty
OFF state, which turns off the LED connected to the SSW ratio of a pulse signal Such that the feedback Voltage
terminal. 40 matches the Soft start Voltage;
FIG. 8 is a third time chart which shows the operation of the a driver structured to control the switching of the voltage at
control circuit 30. The time chart shown in FIG. 8 shows the a primary coil of the transformer according to the pulse
operation in a case in which the striking operation is not signal output from the pulse modulator, and
executed. In a case in which the STRC terminal is pulled up to a striking control circuit structured to monitor an error
the high-level state (e.g., REF4V) using an external resistor or 45 signal which is asserted when an abnormal state occurs,
wiring, the striking operation is disabled. and structured to reset and restart the soft start circuit
As the circuit is started up, the electric potential at the when the error signal has been asserted at a detection
STRC terminal thus pulled up exceeds the third threshold timing after the Soft start Voltage has reached a threshold
voltage Vitha, and the striking end signal STRC end is Voltage.
asserted. At the point in time t1, the error signal ERROR is 50 2. A control circuit according to claim 1, wherein the strik
asserted. When the soft start voltage VREF SS exceeds the ing control circuit comprises a counter structured to count the
first threshold voltage Vth 1 at the point in time t3, the soft start number of times the soft start circuit has been reset,
end signal SS end is asserted, thereby switching the FAIL and wherein, in a case in which the count value has reached
terminal to the low-level state. When the electric potential at a predetermined value, the soft start circuit is prevented
the CP terminal reaches the second threshold voltage after the 55 from being reset.
passage of a predetermined period of time Tcp after the point 3. A control circuit according to claim 1, wherein the soft
in time t3, the latch signal SL is asserted, and the control start circuit further comprises:
circuit 30 is thereby shut down (point in time t11). a capacitor, one terminal of which is set to a fixed electric
The above-described embodiment has been described for potential;
exemplary purposes only, and is by no means intended to be 60 a current source structured to charge the capacitor; and
interpreted restrictively. Rather, it can be readily conceived a first comparator structured to compare the Soft start Volt
by those skilled in this art that various modifications may be age, which occurs at the other terminal of the capacitor,
made by making various combinations of the aforementioned with a predetermined first threshold voltage,
components or processes, which are also encompassed in the and wherein, when the Soft start circuit is reset, the striking
technical scope of the present invention. 65 control circuit Switches an initializing Switch, provided
In the present embodiment, the settings of the logical val between the one terminal of the capacitor and a fixed
ues in the logic circuit, Such as the high-level state and the voltage terminal, to the ON state, and when the soft start
 US 8,044,604 B2
15 16
Voltage is reduced to a predetermined threshold Voltage, generating a soft start Voltage which changes over time
the striking control circuit Switches the initializing when the external electrode fluorescent lamp is ignited;
Switch to the OFF state. adjusting a duty ratio of a pulse signal Such that a feedback
4. An inverter comprising: Voltage that corresponds to output Voltage of the inverter
a transformer, 5 matches the Soft start Voltage;
control circuit according to claim 1, which is structured to controlling Switching of the Voltage at a primary coil of a
control the Switching of the Voltage at the primary coil of transformer according to the pulse signal; and
the transformer, and monitoring an error signal which is asserted when an
a Voltage detection unit structured to detect the output abnormal state occurs, and striking the external elec
Voltage of the inverter, which is generated at the second- 10 trode fluorescent lamp by initializing the soft start volt
ary coil of the transformer, and which structured to out age and by changing the soft start Voltage over time
put a Voltage that corresponds to the output Voltage to the when the error signal has been asserted at a detection
control circuit. timing after the Soft start Voltage has reached a threshold
5. A liquid crystal display apparatus including: Voltage.
a liquid crystal panel; 15 7. A control method according to claim 6, further compris
an external electrode fluorescent lamp provided as a back ing counting the number of times the Soft start Voltage has
light for the liquid crystal panel; and been initialized,
an inverter according to claim 4, the output Voltage of wherein, in a case in which the count value has reached a
which is supplied to the external electrode fluorescent predetermined value, the soft start circuit is prevented
lamp. 2O from being reset.
6. A control method for an inverter which drives an external
electrode fluorescent lamp, the method comprising: