Window Discriminator TCA 965 B

Preliminary Bipolar IC

Features
● Two window settings
– direct setting of lower and upper edge
voltage (window edges)
– indirect setting by window center
voltage and half window width
● Adjustable hysteresis
● Digital outputs with open collectors
P-DIP-14-1
for currents up to 50 mA
● Adjustable reference voltage VStab

Type Ordering Code Package

■ TCA 965 B Q67000-A8338 P-DIP-14-1

■ Not for new design

The window discriminator compares an input voltage to a defined voltage window. The
digital outputs show whether the input voltage is below, within or above this window.
The TCA 965 B window discriminator is especially suitable as a tracking or
compensating controller with a dead band in control engineering and for the selection of
DC voltages within a certain tolerance of the required setpoint value in measurement
engineering. When it is used as a Schmitt trigger, switching frequencies up to a typical
value of 50 kHz are possible.

Semiconductor Group 1 1998-02-10

 TCA 965 B

Functional Description
Amplifier Amp 3 increases the voltage of the reference source R to VStab = 2 x VREF. The
amplification factor can be altered by external wiring. With direct setting of the window,
the input voltage appears on amplifier Amp 1 (V8), the upper edge voltage on
comparator K2 (V6) and the lower edge voltage on comparator K1 (V7).
With indirect setting of the window, the input voltage appears on inputs V6 and V7, while
the center voltage is connected to amplifier A1 (V8).
The voltage applied to the input (V9) of amplifier Amp 2 is subtracted symmetrically from
the output voltage of amplifier Amp 1 and added. The comparators switch with
hysteresis. The logic gates have open-collector outputs.
If the inhibit input A or B is connected to ground, output A or B will always be high.

+ VS VREF

11 1 5
20 k Ω 20 k Ω

_
10
+Amp 3 VStab
R

7 1
V7 + 2
_ A
_ K1
+
4
Inhibit A

<_ 1
Amp 1 13
C
8
V8
1 3
V=1 D

12
Inhibit B
Amp 2
+
9 1
V9 _ + 14
_ K2
B
V=1
6
V6

IEB00091

Outputs A, B, C, D are open-collector

Block Diagram

Semiconductor Group 2 1998-02-10

 TCA 965 B

Pin Configuration
(top view)

TCA 965 B

GND 1 14 B

A 2 13 C

D 3 12 Inhibit B

Inhibit A 4 11 +V S

V REF 5 10 V Stab

V6 6 9 V9

V7 7 8 V8

IEP00292

Pin Definitions and Functions

Pin Symbol Pin Function in

Direct Setting Indirect Setting

of Window

1 GND GND
2 A Logic output A
3 D Logic output D = A @ B (AND)
4 Inhibit A Connected to GND: logic output A = HIGH
5 VREF Internal VREF = 3 V

6 V6 Upper edge voltage Input voltage V6/7

7 V7 Lower edge voltage Input voltage V6/7
8 V8 Input voltage Center voltage
9 V9 GND Half window width

10 VStab Internal VStab = 6 V

11 + VS Supply voltage
12 Inhibit B Connected to GND: logic output B = HIGH
13 C Logic output C = A @ B (NAND)
14 B Logic output B

Semiconductor Group 3 1998-02-10

 TCA 965 B

Absolute Maximum Ratings

Maximum ratings for ambient temperature TA = – 25 to 85 °C

Parameter Symbol Limit Values Unit

min. max.

Supply voltage (pin 11) VS – 30 V

Difference in input voltage between pins 6, 7, 8 VI – 15 V
Input voltage (pins 6, 7, 8, 9) VI – 30 V

Output current (pins 2, 3, 13, 14) IQ – 50 mA

Output voltage (pins 2, 3, 13, 14) –

independent of VS VQ – 30 V
Voltage on VREF (pin 5) VR – 8 V

Output current of stabilized voltage (pin 10) I10 – 10 mA

Inhibit input voltage (pins 4, 12) VIH – 7 V

Junction temperature Tj 150 °C

Storage temperature Tstg – 55 125 °C

Thermal resistance system - air P-DIP-14-1 Rth SA – 80 K/W

Operating Range

Supply voltage VS 4.5 30 V

Ambient temperature TA – 25 85 °C

Semiconductor Group 4 1998-02-10

 TCA 965 B

Characteristics
VS = 10 V; TA = 25 °C
Parameter Symbol Limit Values Unit Test Test
Condition Circuit
min. typ. max.

Current consumption IS – 5 7 mA V2, V13 = VQH 1

Input current
(pins 6, 7, 8) II – 20 50 nA 1
Input current, pin 9 – II – 400 3000 nA 1

Input offset voltage in

direct setting of window VIO – 20 20 mV 1
Input offset voltage in
indirect setting of window VIO – 50 50 mV 2
Input-voltage range on
pins 6, 7, 8 VI 1.5 VS – 1 V ∆VI < 13 V 1
Input-voltage range on
pin 9 VI 50 VS/2 mV 2
Differential input voltage V6 – (V8 – V9) 13 V
(V8 + V9) – V7 13 V

Reference voltage V5 2.8 3 3.2 V IREF = 0

Stabilized voltage on
pin 10 V10 5.5 6 6.5 V VS > 7.9 V
TC of reference voltage αV5 0.4 mV/K
Sensitivity of reference
voltage to supply-voltage
variation ∆V5/∆VS 2 mV/V

Output reverse current IQH – – 10 µA – –

Output saturation voltage VQL 100 200 mV IQ = 10 mA 1

500 800 mV IQ = 50 mA
Hysteresis of window
edges VU – VL 18 22 35 mV
Inhibit threshold V4, 12 1 1.8 V

Inhibit current I4, 12 – – 100 – µA – –

Switching frequency fdir – 20 – kHz – 1

find – 50 – kHz – 2

Semiconductor Group 5 1998-02-10

 TCA 965 B

VS
Ι S11
11 RL RL RL RL

Ι Ι6 Ι QH2
6 2

Ι QH3
3

Ι QH13
13
Ι Ι7
7
TCA 965B Ι QH14
14

10

Ι Ι8
8 5

9 1 4 12
= V6 = V7 = V8 V5 V10 VQL14 VQL13 VQL3 VQL2
Ι Ι9

IES00086

= V4 = V12

Test Circuit 1
Direct Setting of Window

Semiconductor Group 6 1998-02-10

 TCA 965 B

VS
Ι S11
11 RL RL RL RL

Ι QH2
6 2

Ι QH3
3
7 Ι QH13
13

TCA 965B Ι QH14

14
8
10

9 5

1 4 12
= = V8 = V9 V5 V10 VQL14 VQL13 VQL3 VQL2
V6/7

IES00087

= V4 = V12

Test Circuit 2
Indirect Setting of Window by Center Voltage and Half Window Width

Semiconductor Group 7 1998-02-10

 TCA 965 B

Inhibit Inputs 4,12

VS
V4,12 Outputs A, B

100 Ω 1 kΩ
V4,12 GND High

>7V Not permitted

open Normal function

> 1.8 V Low

Inputs 6, 7, 8 Input 9

1 kΩ
V6,7,8
V9

Outputs VREF , VStab

Outputs 2, 3, 13, 14

VStab
R

VREF
Q

IES00088

Schematic Circuit Diagrams

Semiconductor Group 8 1998-02-10

 TCA 965 B

VS
C1

R1 10 11

R4 6 V 2
6 A

R2 3
D

TCA 965 B
R5 7 V 13
7 C

C2

R6
VΙ 8 V 14
8 B

C3 R3

V9
9 1 4 12

R7

IES00294

To increase the switching frequency, pin 9 may be grounded

via R 7 ( V9 approx. 30...40 mV).

Application Circuit 1
Direct Setting of Lower and Upper Edge Voltages

V6 – V9 = Upper edge voltage

V7 + V9 = Lower edge voltage
V8 = Input voltage

Semiconductor Group 9 1998-02-10

 TCA 965 B

V10

A
VL VU
t
V7 IES00296

Definition of the Offset Voltage VIO

VL + VU
V 10 = --------------------- – V7
2

Semiconductor Group 10 1998-02-10

 TCA 965 B

V8

Upper V6
Edge

Lower V7
Edge

t L t U t

A
B

Inhibit A
Pin 4 on GND 1.8 V < Pin 4<7V
A 1 1
0 A 0
B B

C 1
C 0
D 1
D 0

Inhibit B
Pin 12 on GND 1.8 V < Pin 12 < 7 V

A A
B 1 1
0 B 0
C C 1
0
1
D D 0
IES00295
t L t U t L t U

Application Circuit 1
Direct Setting of Lower and Upper Edge Voltages

Semiconductor Group 11 1998-02-10

 TCA 965 B

VS
C1

10 11
R1 R3

C2 R5 8 V 2
8 A

R6 9 V 3
9 D

TCA 965 B
R7
VΙ 6 V 13
6 C

C3

7 V 14
7 B

1 4 12

R2 R4

IES00297

Application Circuit 2
Indirect Setting of Window by Center Voltage and Half-Window Width V

V6 = V7 = Input voltage
V8 = Center voltage
V9 = Half window width

Semiconductor Group 12 1998-02-10

 TCA 965 B

V10

B
VL VU
t
V8 - V9
VL - VU
V10 = - (V 8 - V 9 ) IES00299
2

Definition of the Offset Voltage VIO

VL + VU
V 10 = --------------------- – (V 8 – V 9 )
2

Semiconductor Group 13 1998-02-10

 TCA 965 B

V8

Upper V6
Edge

Lower V7
Edge

t L t U t
A

B
C

Inhibit A
Pin 4 on GND 1.8 V < Pin 4<7V
A 1 1
0 A 0
B
B
C 1
C 0
D 1
D 0

Inhibit B
Pin 12 on GND 1.8 V < Pin 12 < 7 V
A A

B 1 1
0 B 0
C 1
C 0
D 1
D 0

t L t U t L t U IED00298

Application Circuit 2
Indirect Setting of Window by Center Voltage and Half-Window Width V

Semiconductor Group 14 1998-02-10

 TCA 965 B

VS

RL RL RL
10 11
R1 13

6 14

VΙ 8 2
TCA 965B
R2 R4
7 3
9
R3 P = R5
1

V3

VH VH
V8
0 V7 V6 IES00089

Application Circuit 3
Symmetrically Enlarged Edge Hysteresis in Direct Setting of Window

Calculation of Hysteresis VH

R5
V H = V 10 ------------------
-
R4 + R5

V 10 V 10
------------------- + -------------------------------- ≤ 10 mA
R4 + R5 R1 + R2 + R3

Semiconductor Group 15 1998-02-10

 TCA 965 B

VS

RL RL RL
10 11
R1 2

14
8
13
VΙ 6
TCA 965B 3
7
R5 R3
9

R2 1 R4

V3

V9/1 VH =
V9/2 - V9/1
V9/2
V6/7
V8
0 IES00090

Application Circuit 4
Symmetrically Enlarged Edge Hysteresis in Indirect Setting of Window

Calculation of Hysteresis VH
VH = V9/2 – V9/1
R 4 || R 5
V 9/1 = V 10 -------------------------------
R 3 + R 4 || R 5

R4
V 9/2 = V 10 ------------------
-
R3 + R4

Semiconductor Group 16 1998-02-10

 TCA 965 B

P-DIP-14-1
(Plastic Dual In-line Package)

GPD05005

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm

Semiconductor Group 17 1998-02-10

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