Nalla Malla Reddy Engineering College: I-Mid Examination Objective Set-A Branch: EEE Subject: DE Year /sem: II/II Date

NALLA MALLA REDDY ENGINEERING COLLEGE
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

I-MID EXAMINATION OBJECTIVE
SET-A
Branch: EEE Subject: DE
Year /Sem: II/II Date:
1. What is the addition of the binary numbers 11011011010 and 010100101?

a. 11101111111
b. 0111001000
c. 10011010011
d. 1100110110
2. Perform binary addition: 101101 + 011011
a. 1001000
b. 101110
c. 011010
d. 1010100
3. Binary subtraction of 100101 – 011110 is
a. 101010
b. 111000
c. 000111
d. 010101
4. Which of these gates are universal gates?
a. AND, OR
b. EX-OR, EX-NOR
c. NAND, EX-OR
d. NAND, NOR
5. A universal logic gate is one which can be used to generate any logic function. Which
of the following is a universal logic gate?
a. XOR
b. OR
c. AND
d. NAND
6. Perform binary subtraction: 101111 – 010101 = __________
7. Perform multiplication of the binary numbers: 01001 × 01011 = ______________
8. 2’s complement of 11001011 is ___________
9. All input of NOR as low produces the result as _______
10. On subtracting (010110)2 from (1011001)2 using 2’s complement, we get ________
11. The expression Y=AB+BC+AC shows the POS operation. (True/ False)
12. The canonical sum of product form of the function y(A,B) = A + B is AB + AB’ +
A’B. (True/ False)
13. A(A + B) = A (True/ False)
14. The Boolean function A + BC is a reduced form of (A + C) B (True/ False)
15. A multiplexer is a device which converts many signals into one (True/ False)
16. Assertion: A 64 input MUX can be built by using eight 8 input multiplexers
Reason: Any six variable function can always be implemented by a multiplexer with
six address lines.
a) Both A and R are true and R is a correct explanation of A
b) Both A and R are true and R is not a correct explanation of A
c) A is true but R is false
d) A is false but R is true
17. A:When all inputs of a NAND gate are shorted to get a one input, one output gate, it
becomes an inverter.
R: When all inputs of a NAND gate are at logic ‘0’ level, the output is at logic’1’
level.
e) Both A and R are true and R is a correct explanation of A
f) Both A and R are true and R is not a correct explanation of A
g) A is true but R is false
h) A is false but R is true
18. A. Counting 1. ROM
B. Decoding 2. Multiplexer
C. Data selection 3. De multiplexer
D. Code Conversion 4. Register
Codes A B C D
a. 3 4 2 1
b. 3 4 1 2
c. 4 3 1 2
d. 4 3 2 1
19. The enable input is also known as ___________
a) Select input
b) Decoded input
c) Strobe
d) Sink
20. 4 to 1 MUX would have ____________
a) 2 inputs
b) 3 inputs
c) 4 inputs
d) 5 inputs
NALLA MALLA REDDY ENGINEERING COLLEGE

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
I-MID EXAMINATION OBJECTIVE
SET-B
Branch: EEE Subject: DE
Year /Sem: II/II Date:
1. 100101 × 0110 =
a. 1011001111
b. 0110100101
c. 0100110011
d. 101111110
2. On multiplication of (10.10) and (01.01), we get
a. 101.0010
b. 0010.101
c. 110.0011
d. 011.0010
3. Divide the binary numbers: 111101 ÷ 1001 and find the remainder.
a. 1100
b. 0111
c. 0010
d. 1010
4. Divide the binary number (011010000) by (0101) and find the quotient.
a. 110010
b. 101001
c. 100011
d. 010001
5. Binary subtraction of 101101 – 001011 =
a. 010110
b. 101100
c. 110101
d. 100010
6. The representation of octal number (532.2)8 in decimal is ________
7. The octal equivalent of the decimal number (417)10 is ________
8. A logic gate gave output 1, when all inputs are 1. The gate is _______
9. A logic gate gave output 1, when all inputs same. The gate is _______
10. The NOR gate output will be high if the two inputs are ___ and ________
11. The K-map based Boolean reduction is based on the following Unifying Theorem: A
+ A’ = 1. (True/ False)
12. The prime implicant which has at least one element that is not present in any other
implicant is known as Implicant. (True/ False)
13. Product-of-Sums expressions can be implemented using Both 2-level OR-AND and
NOR logic circuits. (True/ False)
14. Don’t care conditions can be used for simplifying Boolean expressions in K-maps.
(True/ False)
15. Using the transformation method, you can realize any POS realization of OR-AND
with only. (True/ False)
16. Assertion: A 64 input MUX can be built by using eight 8 input multiplexers
Reason: Any six variable function can always be implemented by a multiplexer with
six address lines.
i) Both A and R are true and R is a correct explanation of A
j) Both A and R are true and R is not a correct explanation of A
k) A is true but R is false
l) A is false but R is true
17. A:When all inputs of a NAND gate are shorted to get a one input, one output gate, it
becomes an inverter.
R: When all inputs of a NAND gate are at logic ‘0’ level, the output is at logic’1’
level.
a. Both A and R are true and R is a correct explanation of A
b. Both A and R are true and R is not a correct explanation of A
c. A is true but R is false
d. A is false but R is true
18. A. Counting 1. ROM
B. Decoding 2. Multiplexer
C. Data selection 3. De multiplexer
D. Code Conversion 4. Register
Codes A B C D
a. 3 4 2 1
b. 3 4 1 2
c. 4 3 1 2
d. 4 3 2 1
19. Which combinational circuit is renowned for selecting a single input from
multiple inputs & directing the binary information to output line?
a) Data Selector
b) Data distributor
c) Both data selector and data distributor
d) DeMultiplexer
20. A digital multiplexer is a combinational circuit that selects ___________
a) One digital information from several sources and transmits the selected one
b) Many digital information and convert them into one
c) Many decimal inputs and transmits the selected information
d) Many decimal outputs and accepts the selected information

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NALLA MALLA REDDY ENGINEERING COLLEGE

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

1. What is the addition of the binary numbers 11011011010 and 010100101?

NALLA MALLA REDDY ENGINEERING COLLEGE

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