Chapter # 3: Multi-Level Combinational Logic

Contemporary Logic Design

Randy H. Katz
University of California, Berkeley

June 1993

No. 3-1

Chapter Overview

• Multi-Level Logic
Conversion to NAND-NAND and NOR-NOR Networks

DeMorgan's Law and Pushing Bubbles

AND-OR-Invert Building Blocks

CAD Tools for Multi-Level Optimization

• Time Response in Combinational Networks

Gate Delays and Timing Waveforms

Hazards/Glitches and How To Avoid Them

No. 3-2
 Boolean Algebra

Commutative Laws:

a+b=b+a a •b = b •a

Associative Laws:

(a+b)+c = a+(b+c) (ab)c = a(bc)

Identities:
a+0=a a •0 = 0
a•1=a a+1=1

Distributive Laws:
a + (b •c) = (a+b) •(b+c) a •(b+c) = (a •b) + (a •c)

No. 3-3

Boolean Algebra

Complement:

a+a=1 a •a = 0

a+a=a a •a = a

Theorems:

a + ab = a ab + ab = b

DeMorgan’s Theorem:

a •b = a + b a + b = a •b

No. 3-4
 Multi-Level Logic: Advantages
Reduced sum of products form:

x=ADF + AEF + BDF + BEF + CDF + CEF + G

6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)
25 wires (19 literals plus 6 internal wires)

A
D 1
F
A
E 2
F
A
B B 1
D 3
C
F
B D
E 4 7 x E
2 3
4 x
F F
C G
D 5
F Factored form:
C
E 6 x = (A + B + C) (D + E) F + G
F
G 1 x 3-input OR gate, 2 x 2-input OR gates,
1 x 3-input AND gate
10 wires (7 literals plus 3 internal wires)
No. 3-5

Multi-Level Logic: Conversion of Forms

NAND-NAND and NOR-NOR Networks

DeMorgan's Law: (A + B)' = A' • B'; (A • B)' = A' + B'

A + B = (A' • B')'; (A • B) = (A' + B')'
In other words,
OR is the same as NAND with complemented inputs
AND is the same as NOR with complemented inputs
NAND is the same as OR with complemented inputs
NOR is the same as AND with complemented inputs

OR/NAND
Equivalence

≡
A A B B A +B A• B A +B A •B A A
OR OR
0 1 0 1 0 0 1 1 B B
0 1 1 0 1 1 1 1
1 0 0 1 1 1 1 1

≡
1 0 1 0 1 1 0 0 A A
B Nand Nand
B

No. 3-6
 Mult-Level Logic: Conversion Between Forms

AND/NOR
Equivalence

≡
A A B B A•B A+ B A•B A+B A A
AND AND
0 1 0 1 0 0 1 1 B B
0 1 1 0 0 0 0 0
1 0 0 1 0 0 0 0

≡
1 0 1 0 1 1 0 0 A A
B NOR NOR
B

ItIt isis possible

possible to
to convert
convert from
from networks
networks with
with ANDs
ANDs and
and ORs
ORs
to
to networks with NANDs and NORs by introducing the
networks with NANDs and NORs by introducing the
appropriate
appropriate inversions
inversions ("bubbles")
("bubbles")
To
To preserve
preserve logic
logic levels,
levels, each
each introduced
introduced "bubble"
"bubble" must
must be
be
matched with a corresponding "bubble"
matched with a corresponding "bubble"

No. 3-7

Multi-Level Logic: Conversion of Forms

Example: Map AND/OR network to NAND/NAND network

(A) A (B) A
B B AND
OR
C C
D D AND

(C) A (D) B
A
B

C C
D NAND D NAND
NAND NAND

No. 3-8
 Example: Map AND/OR network to NAND/NAND network

NAND
A A

B B
Z Z
NAND
C C
NAND
D D

Z = [(A•B)' (C•D)' ]'

= [(A' + B') (C' + D')]'

= [(A' + B')' • (C' + D')']

= (A • B) + (C • D) ¦
This is the easy conversion!
No. 3-9

Example: Map AND/OR network to NOR/NOR network

A \A

\B NOR
B
Z Z
C NOR NOR
\C
D
\D

Conserve Conserve
"Bubbles" Step 1 Step 2 "Bubbles"

Z=

No. 3-10
 Example: Map AND/OR network to NOR/NOR network

A \A

\B
B NOR
Z Z
C
NOR NOR
\C
D
\D

Step 1 Step 2
Conserve Conserve
"Bubbles" "Bubbles"
Z = {[(A' + B')' + (C' + D')']'}'

= {(A' + B') • (C' + D')}'

= (A' + B')' + (C' + D')'

= (A • B) + (C • D)

This is the hard conversion! AND/OR

AND/ORto
toNAND/NAND
NAND/NANDmore
morenatural
natural
No. 3-11

Example: Map OR/AND network to NOR/NOR network

NOR

NOR

NOR

Conserve
Bubbles

Verify equivalence
of the two forms Z=

No. 3-12
 Example: Map OR/AND network to NOR/NOR network

NOR

NOR

NOR

Conserve
Bubbles

Z = [(A + B)' + (C + D)']'

= {(A + B)'}' • {(C + D)'}'

= (A + B) • (C + D)

This is the easy conversion!

No. 3-13

Example: Map OR/AND network to NAND/NAND network

Nand Nand

Nand

Conserve
Step 1 Step 2 Conserve
Bubbles! Bubbles!

No. 3-14
 Example: Map OR/AND network to NAND/NAND network

Nand Nand

Nand

Step 1 Step 2
Conserve Conserve
Bubbles! Bubbles!
Z = {[(A' • B')' • (C' • D')']'}'

= {(A' • B') + (C' • D')}'

= (A' • B')' • (C' • D')'

= (A + B) • (C + D)

This is the hard conversion! OR/AND

OR/ANDto
toNOR/NOR
NOR/NORmore
morenatural
natural
No. 3-15

Multi-Level Logic: More than Two Levels

ƒ = A (B + C D) + B C'
Level 1 Level 2 Level 3 Level 4

C G1
D G3
Original B
AND-OR Network A G4 G5 F
B G2
\C

C
Introduction and D
G1
G3
G4
Conservation of Bubbles G5 F
B
A
B G2
\C

Redrawn in terms
C
of conventional D
G1 G3
NAND Gates G4 G5 F
\B
A
B
\C G2

No. 3-16
 Multi-Level Logic: More than Two Levels

Level 1 Level 2 Level 3 Level 4

C
G1
G3
D G4 G5 F
B
A
Same beginning network
after introduction of
\B
bubbles
G2
C

\C
G1
\D G3 G4
G5
B F
\A
B G2
\C Final network, redrawn
in NOR-only form

No. 3-17

Conversion Example

A A
B F B F
C C
X X
D D
(a) Original circuit (b) Add double bubbles at inputs

A
X
A
B B
C F C F
\X \X
\D \D
(c) (d) Insert inverters to fix mismatches
Distribute bubbles
some mismatches

No. 3-18
 Multi- Level Logic: AND-OR-Invert Block (AOI)

AOI Function: Three stage logic — AND, OR, Invert

Multiple gates "packaged" as a single circuit block

logical concept
A C
True
A
B B D Z
Z
C A B
D
False
C D

AND OR Invert

two-input two-stack

No. 3-19

Multi-Level Logic: AND-OR-Invert Block (AOI)

&
2x2 AOI Schematic
+
Symbol &

&
3x2 AOI Schematic +
Symbol &

No. 3-20
 Example: XOR implementation

A xor B = A' B + A B'

AOI form = ( ? )'

(A' B + A B')'

(A + B') (A' + B)

(A B + A' B')

General procedure to place in AOI form:

Compute the complement in Sum of Products form by
circling the 0's in the K-map!

ƒ = (A' B' + A B)'

No. 3-21

Example:

AB A F = B C' + A C' + A B
C 00 01 11 10
0 1 0 0 0 F' = A' B' + A' C + B' C
1 1 1 0 1
2-input 3-stack AOI gate
B

F K-map
F = (A + B) (A + C') (B + C')
F' = (B' + C) (A' + C) (A' + B')
2-input 3-stack OAI gate

No. 3-22
 Example: 4-bit Equality Function

Z = (A0 B0 + A0' B0') (A1 B1 + A1' B1')

(A2 B2 + A2' B2') (A3 B3 + A3' B3')

Each implemented in single 2x2 AOI gate

No. 3-23

Example: AOI Implementation of a 4-Bit Equality Tester

High if A0 ° B0, Low if A0 = B0

A = B active low

Conservation of bubbles

If all inputs are low

(asserted in negative logic)
NOR
then Ai = Bi, i=0,...,3
Output Z asserted

No. 3-24
 Multi-Level Logic: CAD Tools for Simplification
Multi-Level Optimization:
1. Factor out common sublogic (reduce fan-in, increase gate levels),
subject to timing constraints

2. Map factored form onto library of gates

3. Minimize number of literals (correlates with number of wires)

Factored Form:
sum of products of sum of products . . .

A
•
B F1 X = (A B + B' C) (C + D (E + A C')) + (D + E)(F G)
+
B
•
•
C C
+F
D 2
• + X
E F5
+ F F4
A •
• G
D •
C +
E F3

No. 3-25

Multi-Level Logic: CAD Tools for Simplification

Operations on Factored Forms:
• Decompostion

• Extraction
Manipulate network by interactively
issuing the appropriate instructions
• Factoring
There exists no algorithm that guarantees
"optimal" multi-level network will be
• Substitution obtained

• Collapsing

No. 3-26
 Time Response in Combinational Networks
• emphasis on timing behavior of circuits

• waveforms to visualize what is happening

• simulation to create these waveforms

• momentary change of signals at the outputs: hazards

- can be useful— pulse shaping circuits
- can be a problem — glitches: incorrect circuit operation

Terms:
gate delay - time for change at input to cause change at output
minimum delay vs. typical/nominal delay vs. maximum delay
careful designers design for the worst case!

rise time - time for output to transition from low to high voltage
fall time - time for output to transition from high to low voltage
No. 3-27

Pulse Shaping Circuit

A' • A = 0

3 gate delays

D remains high for

three gate delays after F is not always 0!
A changes from low to high

No. 3-28
 Another Pulse Shaping Circuit

+
Resistor
A B
Open C D
Switch

Close Switch Open Switch

Initially undefined

No. 3-29

Hazards/Glitches and How to Avoid Them

Unwanting switching at the outputs
Occur because delay paths through the circuit experience
different propagation delays
Danger if logic "makes a decision" while output is unstable
OR hazard output controls an asynchronous input (these
respond immediately to changes rather than waiting for a
synchronizing signal called a clock)
Usual solutions:
- wait until signals are stable (by using a clock)
- never, never, never use circuits with asynchronous inputs
- design hazard-free circuits
Suggest that first two approaches be used, but we'll tell you
about hazard-free design anyway!
No. 3-30
 Hazards/Glitches and How to Avoid Them

1 1
Static Input change causes output to
0 1-hazard go from 1 to 0 to 1
1
Static
0 0
0-hazard Input change causes output to
go from 0 to 1 to 0
1 1

0 0
Dynamic
Input change causes a double change
1 1 hazards from 0 to 1 to 0 to 1 OR
from 1 to 0 to 1 to 0
0 0

Kinds of Hazards

No. 3-31

Glitch Example A
AB
00 01 11 10
1 1 CD
A 1 A 1
G1 G1
\C
1
\C 1 00 0 0 1 1
1 G3 F 1 G3 F
\A 0 \A 0
G2 G2 01 1 1 1 1
D 0 D 0
0 0
D
ABCD = 1100 ABCD = 1101 11 1 1 0 0
C
input change within product term 10 0 0 0 0

F = A' D + A C'

1 0 0
A 1 A 0 A 0
G1 G1 G1
\C \C 0 \C 1
1 1 1 1
G3 F G3 F G3 F
\A 0 \A 0 \A 1
G2 G2 G2
D 0 D 0 D 1
1 1 1

ABCD = 1101 ABCD = 0101 (A is still 0) ABCD = 0101 (A is 1)

input change that spans product terms

output changes from 1 to 0 to 1
No. 3-32
 Glitch Example

General Strategy: add redundant terms

F = A' D + A C' becomes A' D + A C' + C' D

This eliminates 1-hazard? How about 0-hazard?

A
AB
Re-express F in PoS form: CD
00 01 11 10
00 0 0 1 1
F = (A' + C')(A + D)
01 1 1 1 1
D
Glitch present! 11 1 1 0 0
C
Add term: (C' + D) 10 0 0 0 0

B
This expression is equivalent
to the hazard-free SoP form of F
No. 3-33

Glitch Example

Start with expression that is free of static 1-hazards

F = A C' + A' D + C' D

Work with complement:

F' = (A C' + A' D + C' D)'

= (A' + D) (A + D') (C + D')

= A C + A C D' + C D' + A' C D' + A' D'

= A C + C D' + A' D’

covers all the adjacent 0's in the K-map

free of static-1 and static-0 hazards!
No. 3-34
 Detecting Static Hazards in Multi-Level Circuits
Calculate transient output function

variables and complements are treated as independent variables

cannot use X + X' = 1 or X •X' = 0 for simplifications

Example:
F = A B C + (A + D) (A' + C')
F1 = A B C + A A' + A C' + A' D + C' D 2-level form
A
AB
00 01 11 10
CD ABCD: 1111 to 1110, covered by term
00 0 0 1 1 ABC, so no 1-hazard present
01 1 1 1 1 ABCD: 1110 to 1100, term ABC goes low
D while term AC' goes high
11 1 1 1 0
C some static hazards are present!
10 0 0 1 0

B
No. 3-35

Static 1-hazards

Solution:
Add redundant terms to insure all adjacent
transitions are covered by terms

F2 = A C' + A' D + C' D + A B + B D

100
A
B
C
D
F
F2
1's hazards in F
corrected in F2
No. 3-36
 Static 0-Hazards
Similar to previous case, but work with the complement of F

If terms of the transient output function cover all 0 transitions, then

no 0-hazards are present
A
AB
F = [A B C + (A + D) (A' + C')]' CD
00 01 11 10
00 0 0 1 1
= (A' + B' + C') (A' D' + A C)
01 1 1 1 1
= A' D' + A' B D' + A' C D' + A B' C D
11 1 1 1 0
= A' D' + A B' C C
+ B' C D' 10 0 0 1 0

F = (A + D) (A' + B + C') (B + C' + D) 0-hazard on transition from

1010 to 0010
0-hazard free
equivalent to F2 on last slide

No. 3-37

Static 0-Hazards

100
A
B
C
D
F
F3

0-Hazard
Corrected in F3

No. 3-38
 Designing Networks for Hazard-free operation

Simply place transient output function in a form that

guarantees that all adjacent ones are covered by a term

no term of the transient output function contains

both a variable and its complement

A F(A,B,C,D) = •m(1,3,5,7,8,9,12,13,14,15)
AB
00 01 11 10
CD
F = A B + A' D + B D + A C' + C' D
00 0 0 1 1

01 1 1 1 1
= (A' + B + C') D + A (B + C')
D
(factored by distributive law, which does not
11 1 1 1 0
introduce hazards since it does not depend on
C the complementarity laws for its validity)
10 0 0 1 0

No. 3-39

Dynamic Hazards
1 01
\A
G1
B
01
Slow G3
10 1 01
\B
G2 1 01 0
\C 10
1 G5 F
0
A 10
G4
\B
10
V ery slow

Three different paths from B or B' to output

ABC = 000, F = 1 to ABC = 010, F = 0
different delays along the paths:
G1 slow, G4 very slow

Handling dynamic hazards very complex

Beyond our scope
No. 3-40
 Elements of a Data Sheet

A data sheet contains all the relevant documentation that

you need to use the component:

1. Description of Function
2. A function/truth table
3. A logic schematic with labeled I/Os
4. Boolean expression of function in terms of I/Os
5. Alternative package pint-outs
6. Internal transistor shcematics
7. Operating specifications
8. Recommended operating conditions
9. Electrical characteristics.
10. Switching characteristics.

No. 3-41

Operating Specifications: the absolute worst-case conditions

under which the component can operate or be stored. Max
input volt: 7v, Temp: 0 to 70 C.

Recommended Operating Conditions: the normal operating

conditions for the supply voltage, input voltages, output
currents, and temperature.

V HI : min input volt recognized as a logic 1 (2v)

V IL: max input volt recognized as a logic 0 (0.8v)

I OH : max current gate can supply to maintain volt of logic 1 (-0.4 mA)
I OL: min current gate can supply to maintain volt of logic 0 (8 mA)

No. 3-42
Electrical Characteristics: voltages and currents that can
be observed at the inputs and outputs.
V OH : min output high volt (2.7v min, 3.4v typical)
V OL: max output low volt (0.4v max, 0.25v typical)

IIH : max current into input when high (20uA)

IIL: max current into input when low (-0.4 mA)

The voltages determine the noise margin: 0.7v margin

on logic 1, and 0.4v on logic 0.

Switching Characteristics: the typical and maximum

gatdelays under specified test conditions.
tPLH : delay from low to high (9ns typical, 15ns worst)
tPHL : delay from high to low (10ns typical, 15ns worst)
No. 3-43

Fan-Out: a given output can drive only a finite number of

inputs before the output signal levels become degraded
and are no longer recognized as good logic 1/0s.

To determine the fan-out examine the I OH of the driving

gate. This value must exceed the sum of the I IH values of
the inputs that the gate is driving.
Similarly, the I OL of the gate must exceed the sum of the
I IL values of the inputs to which it is connected.

Example: IIH: 20uA, IOH: -0.4mA

IIL: -0.4mA, IOL: 8mA

It can drive 20 gates to logic 1 and to logic 0.

No. 3-44
 Technology Metrics

There are differences in the underlying technologies that

may make one technology more attractive than another.
The main technology metrics are:

1. Gate Delay: the time delay between the changes. Om

general, bipolar techs are faster than MOS (ECL the
fastest).

2. Degree of Integration: the area required to implement a

given function in the underlying tech. MOS pack much more
densely than bipolar.

SSI: up to 10 gates
MSI: up to 100 gates (not important)
LSI / VLSI: up to 1000 gates (MOS has advantage)

No. 3-45

3. Power Dissipation: the power consumption and heat

generated that must be dissipated.
- Bipolar generate more heat and consume more power
- ECL consume the most power
- MOS, especially CMOS, consume very little power

4. Noise Margin: the max volt that can be added to or

subtracted from the login voltages and still have the ckt
interpret the voltage as the correct logic value.

- Modern TTL / CMOS have good noise margins

- ECL has tighter noise margin

5. Component Cost: TTL, MOS, ECL

No. 3-46