ECE 545—Digital System Design with VHDL

Lecture 1

Digital Logic Refresher

Part A – Combinational Logic Building Blocks

1
Lecture Roadmap – Combinational Logic
•  Basic Logic Review
•  Basic Gates
•  De Morgan’s Law

•  Combinational Logic Building Blocks

•  Multiplexers
•  Decoders, Demultiplexers
•  Encoders, Priority Encoders
•  Arithmetic circuits
•  ROM. Implementing combinational logic using ROM.
•  Tri-state buffers.

2
Textbook References

•  Combinational Logic Review

•  Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design, 2nd or 3rd Edition
§  Chapter 2 Introduction to Logic Circuits (2.1-2.8 only)
§  Chapter 6 Combinational-Circuit Building Blocks (6.1-6.5 only)
•  OR your undergraduate digital logic textbook (chapters on
combinational logic)

3
 Basic Logic Review

some slides modified from:

S. Dandamudi, “Fundamentals of Computer Organization and Design”

4
Basic Logic Gates (2-input versions)

5
Basic Logic Gates Generalized
•  Simple logic gates
•  AND à 0 if one or more inputs is 0
•  OR à 1 if one or more inputs is 1
•  NAND = AND + NOT
•  1 if one or more inputs is 0
•  NOR = OR + NOT
•  0 if one or more input is 1
•  XOR à 1 if an odd number of inputs is 1
•  XNOR à 1 if an even number of inputs is 1
•  NAND and NOR gates require fewer transistors than AND and
OR in standard CMOS
•  Functionality can be expressed by a truth table
•  A truth table lists output for each possible input combination

6
Number of Functions

•  Number of functions
•  With N logical variables, we can define
N
2 functions
2

•  Some of them are useful

•  AND, NAND, NOR, XOR, …
•  Some are not useful:
•  Output is always 1
•  Output is always 0
•  “Number of functions” definition is useful in proving
completeness property

7
Complete Set of Gates
•  Complete sets
•  A set of gates is complete
•  if we can implement any logic function using only the type of
gates in the set
•  Some example complete sets
•  {AND, OR, NOT} Not a minimal complete set
•  {AND, NOT}
•  {OR, NOT}
•  {NAND}
•  {NOR}
•  Minimal complete set
•  A complete set with no redundant elements.

8
NAND as a Complete Set
•  Proving NAND gate is universal

9
Logic Functions

•  Logic functions can be expressed in several ways:

•  Truth table
•  Logical expressions
•  Graphical schematic form
•  HDL code
•  Example:
•  Majority function
•  Output is one whenever majority of inputs is 1
•  We use 3-input majority function

10
Alternative Representations of Logic Function
Truth table Logical expression form
A B C F F=AB+BC+AC

0 0 0 0 Graphical schematic form

0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
HDL code: F <= (A AND B) OR (B AND C) OR (A AND C) ; 11
Boolean Algebra

Boolean identities
Name AND version OR version
Identity x .1 = x x+0=x
Complement x. x’ = 0 x + x’ = 1
Commutative x .y = y .x x+y=y+x
Distribution x. (y+z) = xy+xz x + (y. z) =
(x+y) (x+z)
Idempotent x .x = x x+x=x
Null x .0 = 0 x+1=1
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Boolean Algebra (cont’d)

•  Boolean identities (cont’d)

Name AND version OR version

Involution x = (x’)’ ---

Absorption x. (x+y) = x x + (x.y) = x
Associative x.(y. z) = (x. y).z x + (y + z) =
(x + y) + z
de Morgan (x. y)’ = x’ + y’ (x + y)’ = x’ . y’
(de Morgan’s law in particular is very useful)

13
Alternative symbols for NAND and NOR

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Majority Function Using Other Gates

•  Using NAND gates

•  Get an equivalent expression
A B + C D = (A B + C D)’’
•  Using de Morgan’s law

A B + C D = ( (A B)’ . (C D)’)’
•  Can be generalized
•  Example: Majority function

A B + B C + AC = ((A B)’ . (B C)’ . (AC)’)’

15
Majority Function Using Other Gates (cont'd)
•  Majority function

16
Combinational Logic Building Blocks

Some slides modified from:

S. Dandamudi, “Fundamentals of Computer Organization and Design”
S. Brown and Z. Vranesic, "Fundamentals of Digital Logic"

17
Multiplexers

log2n selection inputs

n inputs 1 output

•  multiplexer
•  n binary inputs (binary input = 1-bit input)
•  log2n binary selection inputs
•  1 binary output
•  Function: one of n inputs is placed onto output
•  Called n-to-1 multiplexer

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 2-to-1 Multiplexer
s
s f
w0 0 w0
f 0
w1 1 1 w1

(a) Graphical symbol (b) Truth table

w0 w0

s f s

w1 w1 f

(c) Sum-of-products circuit (d) Circuit with transmission gates

Source: Brown and Vranesic

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 4-to-1 Multiplexer
s0
s1 s 1 s0 f
w0 00 0 0 w0
w1 01 w1
f 0 1
w2 10 w2
1 0
w3 11
1 1 w3

(a) Graphic symbol (b) Truth table

s0
w0
s1

w1

w2

w3

Source: Brown and Vranesic (c) Circuit 20

Multi-bit 4-to-1 Multiplexer
s0
s1 s 1 s0 f
w0 00 0 0 w0
w1 01 w1
f 0 1
w2 10 w2
1 0
w3 11 8
1 1 w3
8

(a) Graphic symbol (b) Truth table

•  When drawing schematics, can draw multi-bit multiplexers

•  Example: 8-bit 4-to-1 multiplexer
•  4 inputs (each 8 bits)
•  1 output (8 bits)
•  2 selection bits
•  Can also have multi-bit 2-to-1 muxes, 16-to-1 muxes, etc.
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8-bit 4-to-1 Multiplexer
s0
s
1
w0(7)
00
w1(7)
01
f(7)
w2(7)
10
11
w3(7)

s0
s0 s1
s1 An 8-bit 4-to-1 multiplexer is composed
w0(6)

w0 00 w1(6)

00
01
of eight [1-bit] 4-to-1 multiplexers
f(6)
=
w1 01 10
f w2(6)

w2 10 11
w3 8
w3(6)

11
8

s0
s1
w0(0)
00
w1(0)
01
f(0)
w2(0)
10
11
w3(0)

22
Decoders
wn-1 y2n – 1
n
inputs 2n
w0 outputs

Enable y0
En

•  Decoder
•  n binary inputs
•  2n binary outputs
•  Function: decode encoded information
•  If enable=1, one output is asserted high, the other outputs are asserted low
•  If enable=0, all outputs asserted low
•  Often, enable pin is not needed (i.e. the decoder is always enabled)
•  Called n-to-2n decoder
•  Can consider n binary inputs as a single n-bit input
•  Can consider 2n binary outputs as a single 2n-bit output
•  Decoders are often used for RAM/ROM addressing
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 2-to-4 Decoder
En w1 w0 y3 y2 y1 y0
w1 y3
1 0 0 0 0 0 1
w0 y2
1 0 1 0 0 1 0
y1
1 1 0 0 1 0 0
En y0
1 1 1 1 0 0 0
0 - - 0 0 0 0
(a) Truth table (b) Graphical symbol

w0
y0
w1

y1

y2

y3

En
Source: Brown and Vranesic
(c) Logic circuit 24
Demultiplexers

log2n selection inputs

1 input n outputs

•  Demultiplexer
•  1 binary input
•  n binary outputs
•  log2n binary selection inputs
•  Function: places input onto one of n outputs, with the remaining outputs asserted low
•  Called 1-to-n demultiplexer
•  Closely related to decoder
•  Can build 1-to-n demultiplexer from log2n-to-n decoder by using the decoder's enable
signal as the demultiplexer's input signal, and using decoder's input signals as the
demultiplexer's selection input signals.

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1-to-4 Demultiplexer

26
Encoders

w2n – 1
yn – 1

2n n
inputs outputs
y0
w0

•  Encoder
•  2n binary inputs
•  n binary outputs
•  Function: encodes information into an n-bit code
•  Called 2n-to-n encoder
•  Can consider 2n binary inputs as a single 2n-bit input
•  Can consider n binary output as a single n-bit output
•  Encoders only work when exactly one binary input is equal to 1
27
4-to-2 Encoder
w3 w2 w1 w0 y1 y0

0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

(a) Truth table

w0

w1
y0

w2

y1
w3

(b) Circuit
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Priority Encoders

w2n – 1
yn – 1

2n n
inputs outputs
y0
w0 z "valid" output

•  Priority Encoder
•  2n binary inputs
•  n binary outputs
•  1 binary "valid" output
•  Function: encodes information into an n-bit code based on priority of inputs
•  Called 2n-to-n priority encoder
•  Priority encoder allows for multiple inputs to have a value of '1', as it encodes the input with the
highest priority (MSB = highest priority, LSB = lowest priority)
•  "valid" output indicates when priority encoder output is valid
•  Priority encoder is more common than an encoder

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4-to-2 MSB Priority Encoder

w3 w 2 w 1 w0 y 1 y0 z

0 0 0 0 - - 0
0 0 0 1 0 0 1
0 0 1 - 0 1 1
0 1 - - 1 0 1
1 - - - 1 1 1

30
Single-Bit Adders
•  Half-adder
•  Adds two binary (i.e. 1-bit) inputs A and B
•  Produces a sum and carryout
•  Problem: Cannot use it alone to build larger adders
•  Full-adder
•  Adds three binary (i.e. 1-bit) inputs A, B, and carryin
•  Like half-adder, produces a sum and carryout
•  Allows building M-bit adders (M > 1)
•  Simple technique
•  Connect Cout of one adder to Cin of the next
•  These are called ripple-carry adders

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Half-Adder

c x 2 1
HA x + y = ( c s )2
s y

x y c s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

32
Full-Adder
cout x
2 1
FA y x + y + cin = ( cout s )2
s
cin

x y cin cout s
x s
0 0 0 0 0 y
0 0 1 0 1
cin
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1 cout
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
33
16-bit Unsigned Adder

16 16

X Y
Cout + Cin
S
16

34
Multi-Bit Ripple-Carry Adder
A 16-bit ripple-carry adder is composed of 16 (1-bit) full adders
Inputs: 16-bit A, 16-bit B, 1-bit carry in (set to zero in the figure below)
Outputs: 16-bit sum S, 1-bit carry out
Other multi-bit adder structures can be studied in ECE 645—Computer Arithmetic

Called a ripple-carry adder because carry ripples from one full-adder to the next.
Critical path is 16 full-adders. 35
Comparator
•  Used two compare two M-bit numbers and produce a flag (M >1)
•  Inputs: M-bit input A, M-bit input B
•  Output: 1-bit output flag
•  1 indicates condition is met
•  0 indicates condition is not met
•  Can compare: >, >=, <, <=, =, etc.

A
M 1 if A > B
A > B?
B 0 if A <= B
M

36
Example: 4-bit comparator (A = B)

A
4 1 if A = B
A = B?
B 0 if A != B
4

37
4x4-bit Unsigned Multiplier

4 4

a b
*
c U
8

38
4x4-bit Signed Multiplier

4 4

a b
*
c S
8

39
 Unsigned vs. Signed Multiplication

Unsigned Signed

1111 15 1111 -1
x 1111 x 15 x 1111 x -1

11100001 225 00000001 1

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 Quotient and remainder
Given integers a and n, n>0

∃! q, r ∈ Z such that

a = q⋅ n + r and 0≤r<n

a
q – quotient q= = a div n
n
a
r – remainder r = a - q⋅ n = a – ⋅n =
n
(of a divided by n) = a mod n
41
Rules of addition, subtraction and multiplication
modulo n

a + b mod n = ((a mod n) + (b mod n)) mod n

a - b mod n = ((a mod n) - (b mod n)) mod n

a ⋅ b mod n = ((a mod n) ⋅ (b mod n)) mod n

42
Logical Shift Right

4
A(3) A(2) A(1) A(0)

A
A
>>1
C L
4 C
‘0’ A(3) A(2) A(1)

43
Arithmetic Shift Right

4
A(3) A(2) A(1) A(0)

A
A
>>1
C A
4 C
A(3) A(3) A(2) A(1)

44
Fixed Rotation

4
A(3) A(2) A(1) A(0)
A
A
<<< 1
C
4 C
A(2) A(1) A(0) A(3)

45
8-bit Variable Rotator Left

A
3
B A <<< B

C
8

46
Read Only Memory (ROM)

ADDR DOUT
m n

ROM

47
Implementing Arbitrary Combinational Logic
Using ROM
X5 X4 X3 X2 X1 Y
0 0 0 0 0 0
0 0 0 0 1 1
0 0 0 1 0 0
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 1
0 0 1 1 0 0
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 1 0
0 1 0 1 1
0
1
ADDR DOUT
0 1 1 0 0 1
5 1
0 1 1 0 1 1

ROM
0 1 1 1 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 0 1 1 0
1 0 1 0 0 0
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 1 1
1 1 0 1 0 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 1
1 1 1 1 0 0
1 1 1 1 1 0

48
Tri-state Buffer
e

x f
e= 0
(a) A tri-state buffer x f

e x f e= 1
x f
0 0 Z
0 1 Z
1 0 0 (b) Equivalent circuit
1 1 1

(c) Truth table

49
Four types of Tri-state Buffers

e e

x f x f

(a) (b)

e e

x f x f

(c) (d)

50