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    EE331L Experiment #3 Adders and Subtractors: Written By: Shehab Alaa Ramadan Group: C University ID Number: 022180589

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    Shehab Ramadan
    This document describes an experiment to design and implement half adders, full adders, half subtractors, and full subtractors using logic gates. The objectives are to realize these circuits using basic and universal gates. The introduction defines half adders, full adders, half subtractors, and full subtractors. The experimental procedure explains how to construct each circuit using 7486, 7408, 7432, and 7404 ICs on a breadboard. The results section provides the outputs of the built circuits. References for the lab manual and Quartus tutorial are also provided.

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    © All Rights Reserved
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    EE331L Experiment #3 Adders and Subtractors: Written By: Shehab Alaa Ramadan Group: C University ID Number: 022180589

    Uploaded by

    Shehab Ramadan
    25 views6 pages
    This document describes an experiment to design and implement half adders, full adders, half subtractors, and full subtractors using logic gates. The objectives are to realize these circuits using basic and universal gates. The introduction defines half adders, full adders, half subtractors, and full subtractors. The experimental procedure explains how to construct each circuit using 7486, 7408, 7432, and 7404 ICs on a breadboard. The results section provides the outputs of the built circuits. References for the lab manual and Quartus tutorial are also provided.

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    This document describes an experiment to design and implement half adders, full adders, half subtractors, and full subtractors using logic gates. The objectives are to realize these circuits using basic and universal gates. The introduction defines half adders, full adders, half subtractors, and full subtractors. The experimental procedure explains how to construct each circuit using 7486, 7408, 7432, and 7404 ICs on a breadboard. The results section provides the outputs of the built circuits. References for the lab manual and Quartus tutorial are also provided.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    25 views6 pages

    EE331L Experiment #3 Adders and Subtractors: Written By: Shehab Alaa Ramadan Group: C University ID Number: 022180589

    Uploaded by

    Shehab Ramadan
    This document describes an experiment to design and implement half adders, full adders, half subtractors, and full subtractors using logic gates. The objectives are to realize these circuits using basic and universal gates. The introduction defines half adders, full adders, half subtractors, and full subtractors. The experimental procedure explains how to construct each circuit using 7486, 7408, 7432, and 7404 ICs on a breadboard. The results section provides the outputs of the built circuits. References for the lab manual and Quartus tutorial are also provided.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    EE331L

    Experiment #3
    Adders and Subtractors

    Written by: Shehab alaa ramadan Group: C


    University ID Number: 022180589

    Instructor: Eng. Nadia Alhamdi

    1
    1-Objectives:

     To design, realize and verify the adder and subtractor circuits using basic gates
    and universal gates.

    2-Introduction:

    Half-Adder: A combinational logic circuit that performs the addition of two data
    bits, A and B, is called a half-adder. Addition will result in two output bits; one of
    which is the sum bit, S, and the other is the carry bit, C. The Boolean functions
    describing the half-adder are: S =A ⊕ B C = A B

    Full-Adder: The half-adder does not take the carry bit from its previous stage into
    account. This carry bit from its previous stage is called carry-in bit. A
    combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin,
    is called a full-adder. The Boolean functions describing the full-adder are: S = (x ⊕
    y) ⊕ Cin C = xy + Cin (x ⊕ y)

    Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A -B)
    produces a difference bit D and a borrow out bit B-out. This operation is called
    half subtraction and the circuit to realize it is called a half subtractor. The Boolean
    functions describing the halfSubtractor are: S =A ⊕ B C = A’ B

    Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit
    value A produces a difference bit D and a borrow out Br bit. This is called full
    subtraction. The Boolean functions describing the full-subtracter are: D = (x ⊕ y)
    ⊕ Cin Br= A’B + A’ (Cin) + B (Cin)

    2
    3-Equipments:
    -ICs 7486 7408 7432 7404
    -a surface mount dip switch
    -D C Power Supply.
    -Red Green LEDs
    -Connecting Wires
    -BreadBoard

    4-Experimental procedure:

    Half-Adder: we need one xor gate and one and gate to construct the half adder
    on the breadboard then we take the wires and put them to the pins first we take
    the vcc and put it in the where the data sheet tells us and put the two inputs and
    the outputs and if it turn green then the output is 0

    Full-Adder: we need two xor gates and two and gates and one or gate in order to
    implement them in the breadboard the outputs will be named sum and carry the
    sum is the output from the xor gate that the inputs of the xor gates will be a and b
    attached inte another xor gate and the other input will be connected directly to
    the iinputs of the breadboard and acts like carry in and then the other output will
    named carry like we said

    3
    Half Subtractor: we need to invert the second input which is called b into the and
    gate in order to do that will need to bring the not gate and then take a wire and
    put it in the not gate the from the same pin we take another wire and put it into
    the and gate and only the and gate and everything else will be the same as the
    half adder

    Full Subtractor: we need to invert the output of the first xor gate and put it as an
    input in the second and gate then we also take an inverter and invert the a input
    and put it to the first and gate and everything else stays the same as we did in full
    adder

    5-

    4
    5-Results:

    5
    8-Refrence:

    [1] Manual: Parallel Adders, Subtractors,. Laboratory, METU. (Used until 2015)

    [2] G.L. Moss, “Quartus Tutorial 3–Hierarchical Designs, A step-by-step tutorial


    using Quartus II v9.x.” May 2010.

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