Microprocessor & Microcontroller
Microprocessor & Microcontroller
Microprocessor & Microcontroller
Macro Subroutine
Macro can be called only in the program it is Subroutine can be called from other programs
defined. also.
Macro can have maximum 9 parameters. Can have any number of parameters.
Macro can be called only after its definition. This is not true for Subroutine.
A macro is defined inside: Subroutine is defined inside:
DEFINE … FORM …..
…. …..
END-OF-DEFINITION. ENDFORM.
Macro is used when same thing is to be done
Subroutine is used for modularization.
in a program a number of times.
The different types of interrupts present in 8086 microprocessor are given by:
1. Hardware Interrupts –
Hardware interrupts are those interrupts which are caused by any peripheral device by
sending a signal through a specified pin to the microprocessor. There are two
hardware interrupts in 8086 microprocessor. They are:
o (A) NMI (Non Maskable Interrupt) – It is a single pin non maskable hardware
interrupt which cannot be disabled. It is the highest priority interrupt in 8086
microprocessor. After its execution, this interrupt generates a TYPE 2
interrupt. IP is loaded from word location 00008 H and CS is loaded from the
word location 0000A H.
o (B) INTR (Interrupt Request) – It provides a single interrupt request and is
activated by I/O port. This interrupt can be masked or delayed. It is a level
triggered interrupt. It can receive any interrupt type, so the value of IP and CS
will change on the interrupt type received.
2. Software Interrupts – These are instructions that are inserted within the program to
generate interrupts. There are 256 software interrupts in 8086 microprocessor. The
instructions are of the format INT type where type ranges from 00 to FF. The starting
address ranges from 00000 H to 003FF H. These are 2 byte instructions. IP is loaded
from type * 04 H and CS is loaded from the next address give by (type * 04) + 02 H.
Some important software interrupts are:
o (A) TYPE 0 corresponds to division by zero(0).
o (B) TYPE 1 is used for single step execution for debugging of program.
o (C) TYPE 2 represents NMI and is used in power failure conditions.
o (D) TYPE 3 represents a break-point interrupt.
o (E) TYPE 4 is the overflow interrupt.
Machines before the late 1960s—such as the PDP-8 and HP 2100—did not have compilers
which supported recursion. Their subroutine instructions typically would save the current
location in the jump address, and then set the program counter to the next address.[1] While
this is simpler than maintaining a stack, since there is only one return location per subroutine
code section, there cannot be recursion without considerable effort on the part of the
programmer.
A stack machine has 2 or more stack registers — one of them keeps track of a call stack, the
other(s) keep track of other stack
Declaration examples:
Byte1 DB 10h
Declaration examples:
Word DW 1234h
Declaration examples:
Dword1 DW 12345678h
(1) The STRUCT directive tells the assembler that a user defined uninitialized data structure
follows. The uninitialized data structure consists of a combination of the three supported data
types. DB, DW, and DD. The labels serve as zero-based offsets into the structure. The first
element’s offset for any structure is 0. A structure element is referenced with the base “+”
operator before the element’s name.
1. Register mode – In this type of addressing mode both the operands are registers.
Example:
2. MOV AX, BX
3. XOR AX, DX
ADD AL, BL
4. Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16
bit data. Destination operand can never be immediate data.
Example:
5. MOV AX, 2000
6. MOV CL, 0A
7. ADD AL, 45
AND AX, 0000
The logical address also goes by the name of effective address or offset address (also known
as offset), is contained in the 16-bit IP, BP, SP, BX, SI or DI.
The 16-bit content of one of the four-segment registers (CS, DS, ES, SS) is known as the
base segment address.
Offset and base segment addresses are combined to form a 20-bit physical address (also
called real address) that is used to access the memory. This 20-bit physical address is put on
the address bus (AD19 – AD0) by the BIU.
The 20-bit physical (real) address is generated by combining the offset (residing in IP, BP,
SP, BX, SI or DI) and the content of one of the segment registers CS, DS, ES or SS.
The process of combination is as follows: The content of the segment register is internally appended
with 0 H (0000 H) on its rightmost end to form a 20-bit memory address—this 20-bit address points
to the start of the segment. The offset is then added to the above to get the physical address.
8 State in your own words the 8086 instructions used for BCD arithmetic.
In unpacked BCD representation, each digit is stored in a byte, while two digits are packed into a
byte in the packed representation. Since this representation is similar to the ASCII representation,
the four instructions—aaa, aas, aam, and aad—can be used with ASCII as well as unpacked BCD
representations. Arithmetic Instructions are the instructions which perform basic arithmetic
operations such as addition, subtraction and a few more. Unlike in 8085 microprocessor, in 8086
microprocessor the destination operand need not be the accumulator
REP/REPE/REPZ/REPNE/REPNZ
MOVS/MOVSB/MOVSN
CMPS/CMPSB/CMPSW
REP/REPE/REPZ/REPNE/REPNZ Instruction :
REP is a prefix which is written before one of the String Instruction in 8086. These
instructions repeat until specified condition exists
MOVS/MOVSB/MOVSW Instruction :
This instruction copies a byte or word from a location in the data segment to a location in the
extra segment. The offset of the source byte or word in the data segment must be in the SI
register. The offset of the destination in the extra segment must be contained in the DI
register. For multiple byte or multiple word moves the number of elements to be moved is put
in the CX register so that it can function as a counter. After the byte or word is moved SI and
DI are automatically adjusted to point to the next source and the next destination. If the
direction flag is 0, then SI and DI will be incremented by 1 after a byte move and they will
incremented by 2 after a word move. If the DF is a 1, then SI and DI will be decremented by
1 after a byte move and they will be decremented by 2 after a word move. MOVS affects no
flags.
CMPS/CMPSB/CMPSW Instruction :
A String Instruction in 8086 is a series of the same type of data items in sequential memory
locations. The CMPS instruction can be used to compare a byte in one string with a byte in
another string or to compare a word in one string with a word in another string. SI is used to
hold the offset of a byte or word in the source string and DI is used to hold the offset of a byte
or a word in the other string. The comparison is done by subtracting the byte or word pointed
to by DI from the byte or word pointed to by SI. The AF, CF, OF, PF, SF, and ZF flags are
affected by the comparison, but neither operand is affected
Macros in Microprocessor:
Macro is a group of instructions. The Macros in Microprocessor assembler generates the code
in the program each time where the macro is ‘called’. Macros can be defined by MACRO and
ENDM assembler directives. Creating macro is very similar to creating a new opcode that
can be used in the program.
It is important to note that macro sequences execute faster than procedures because there are
no CALL and RET instructions to execute. The assembler places the macro instructions in
the program each time when it is invoked. This procedure is known as Macro expansion
A module interface expresses the elements that are provided and required by the module. The
elements defined in the interface are detectable by other modules. The implementation
contains the working code that corresponds to the elements declared in the interface. Modular
programming is closely related to structured programming and object-oriented programming,
all having the same goal of facilitating construction of large software programs and systems
by decomposition into smaller pieces, and all originating around the 1960s. While the
historical usage of these terms has been inconsistent, "modular programming" now refers to
the high-level decomposition of the code of an entire program into pieces: structured
programming to the low-level code use of structured control flow, and object-oriented
programming to the data use of objects, a kind of data structure.
String is a group of bytes/words and their memory is always allocated in a sequential order.
String is either referred as byte string or word string. Here we will see some instructions
which are used to manipulate the string related operations.
1 Define Bus.
In computer architecture, a bus[1] (shortened form of the Latin omnibus, and historically also
called data highway[2]) is a communication system that transfers data between components
inside a computer, or between computers. This expression covers all related hardware
components (wire, optical fiber, etc.) and software, including communication protocols.[3]
Early computer buses were parallel electrical wires with multiple hardware connections, but
the term is now used for any physical arrangement that provides the same logical function as
a parallel electrical bus. Modern computer buses can use both parallel and bit serial
connections, and can be wired in either a multidrop (electrical parallel) or daisy chain
topology, or connected by switched hubs, as in the case of USB.
Internal buses
The internal bus, also known as internal data bus, memory bus, system bus or front-side bus,
connects all the internal components of a computer, such as CPU and memory, to the
motherboard. Internal data buses are also referred to as local buses, because they are intended
to connect to local devices. This bus is typically rather quick and is independent of the rest of
the computer operations.
External buses
The external bus, or expansion bus, is made up of the electronic pathways that connect the
different external devices, such as printer etc., to the computer.
1.minimum mode (minimum mode can be selected by strapping its MN/MX pin to logic 1.&
it acts like a single microprocessor . in this mode all the control signals are given out by the
microprocessor chip itself).
2.maximum mode(this operation can be selected by strapping its MN/MX pin to logic 0.&
microprocessor acts like a multiprocessor. it provides the signals for implementing a
multiprocessor/co processor system environment.and in this each processor is executing its
own program.usually in this type of system environment,there are some system resources that
are common to all processors.they are called global resources.& there are also other resources
,that are assigned to specific purpose ,called as local or private resources. co processor means
there is a second processor in the system,but this two processors can not access the system
bus at the same time.one processor processor passes the control of the system bus to the other
& then may suspend its operation)
5 Compose the term ‘ Multiprogramming’
The THE system apparently introduced the first forms of software-based paged virtual
memory (the Electrologica X8 did not support hardware-based memory management),[3]
freeing programmers from being forced to use actual physical locations on the drum memory.
It did this by using a modified ALGOL compiler (the only programming language supported
by Dijkstra's system) to "automatically generate calls to system routines, which made sure the
requested information was in memory, swapping if necessary".[3] Paged virtual memory was
also used for buffering I/O device data, and for a significant portion of the operating system
code as well as nearly all the ALGOL 60 compiler. In this system itself, semaphores were
used as a programming construct for the first time.
Semaphores are a useful tool in the prevention of race conditions; however, their use is by no
means a guarantee that a program is free from these problems. Semaphores which allow an
arbitrary resource count are called counting semaphores, while semaphores which are
restricted to the values 0 and 1 (or locked/unlocked, unavailable/available) are called binary
semaphores and are used to implement locks.
The semaphore concept was invented by Dutch computer scientist Edsger Dijkstra in 1962 or
1963,[2] when Dijkstra and his team were developing an operating system for the
Electrologica X8. That system eventually became known as THE multiprogramming system.
Before moving forward with pipelining, check these topics out to understand the concept
better :
Memory Organization
Memory Mapping and Virtual Memory
Parallel Processing
ipeline system is like the modern day assembly line setup in factories. For example in a car
manufacturing industry, huge assembly lines are setup and at each point, there are robotic
arms to perform a certain task, and then the car moves on ahead to the next arm.
Types of Pipeline
1. Arithmetic Pipeline
2. Instruction Pipeline
Arithmetic Pipeline
Arithmetic pipelines are usually found in most of the computers. They are used for floating
point operations, multiplication of fixed point numbers etc. For example: The input to the
Floating Point Adder pipeline is:
X = A*2^a
Y = B*2^b
Here A and B are mantissas (significant digit of floating point numbers), while a and b are
exponents.
Registers are used for storing the intermediate results between the above operations.
Instruction Pipeline
In this a stream of instructions can be executed by overlapping fetch, decode and execute
phases of an instruction cycle. This type of technique is used to increase the throughput of the
computer system.
An instruction pipeline reads instruction from the memory while previous instructions are
being executed in other segments of the pipeline. Thus we can execute multiple instructions
simultaneously. The pipeline will be more efficient if the instruction cycle is divided into
segments of equal duration.
Pipeline Conflicts
There are some factors that cause the pipeline to deviate its normal performance. Some of
these factors are given below:
1. Timing Variations
All stages cannot take same amount of time. This problem generally occurs in instruction
processing where different instructions have different operand requirements and thus
different processing time.
2. Data Hazards
When several instructions are in partial execution, and if they reference same data then the
problem arises. We must ensure that next instruction does not attempt to access data before
the current instruction, because this will lead to incorrect results.
3. Branching
In order to fetch and execute the next instruction, we must know what that instruction is. If
the present instruction is a conditional branch, and its result will lead us to the next
instruction, then the next instruction may not be known until the current one is processed.
4. Interrupts
Interrupts set unwanted instruction into the instruction stream. Interrupts effect the execution
of instruction.
5. Data Dependency
It arises when an instruction depends upon the result of a previous instruction but this result is
not yet available.
List of microprocessors
Altera.
AMD.
Apollo.
ARM.
Atmel.
Altera
AMD
Main article: List of AMD microprocessors
Apollo
PRISM
ARM
ARM
Atmel
AVR32
AVR
14 List the advantages of multiprocessor configurations.
In a multiprocessor system, even if one processor fails, the system will not halt. This ability
to continue working despite hardware failure is known as graceful degradation. For example:
If there are 5 processors in a multiprocessor system and one of them fails, then also 4
processors are still working. So the system only becomes slower and does not ground to a
halt.
Enhanced Throughput
If multiple processors are working in tandem, then the throughput of the system increases i.e.
number of processes getting executed per unit of time increase. If there are N processors then
the throughput increases by an amount just under N.
Multiprocessor systems are cheaper than single processor systems in the long run because
they share the data storage, peripheral devices, power supplies etc. If there are multiple
processes that share data, it is better to schedule them on multiprocessor systems with shared
data than have different computer systems with multiple copies of the data.
A coprocessor is a computer processor used to supplement the functions of the primary processor
(the CPU). Operations performed by the coprocessor may be floating point arithmetic, graphics,
signal processing, string processing, cryptography or I/O interfacing with peripheral devices. By
offloading processor-intensive tasks from the main processor, coprocessors can accelerate system
performance. Coprocessors allow a line of computers to be customized, so that customers who do
not need the extra performance do not need to pay for it.
A coprocessor is a computer processor used to supplement the functions of the primary processor
(the CPU). ... Coprocessors allow a line of computers to be customized, so that customers who do
not need the extra performance do not need to pay for it.
PART III
1 State the advantage and disadvantage of parallel communication over serial communication.
There is a misconception that the serial ports/buses are slower than parallel ports/buses as the
transmission of data is only a bit per unit of time. Even serial ports/buses may be clocked
considerably at quicker rate than the parallel ports/buses and can accomplish a higher speed
of data flow. The factors which makes Serial Communication better than Parallel
Communication are:
No Clock Required: In case of unclocked and asynchronous type Serial Communication, the
problem of clock skew between the lanes/ channels does not exist.
Requires Less Space: The Serial Communication configuration requires less space because
the requirement of cable is less in serial connection. The availability of this additional space
gives good isolation of the data lanes from the neighboring communication components.
Low Cost: The cost of serial link is less in comparison to parallel links.
➨It uses less number of lines for transmission between devices. Hence it supports slower speed of
transmission.
➨It occupies overhead of about 20% other than useful information. This leads to wastage of
bandwidth meant for data trasmission for useless stuff.
D/A Converters
Digital Data:
A/D Converters
An A/D converter is a device that converts analog signals (usually voltage) obtained from
environmental (physical) phenomena into digital format
8254 is a device designed to solve the timing control problems in a microprocessor. It has 3
independent counters, each capable of handling clock inputs up to 10 MHz and size of each
counter is 16 bit. It operates in +5V regulated power supply and has 24 pin signals. All modes
are software programmable. The 8254 is an advanced version of 8253 which did not offered
the feature of read back command.
It has 3 counters each with two inputs (Clock and Gate) and one output. Gate is used to
enable or disable counting. When any value of count is loaded and value of gate is set(1),
after every step value of count is decremented by 1 until it becomes zero.
Depending upon the value of CS, A1 and A0 we can determine addresses of selected counter.
CS A1 A0 SELECETION
0 0 0 C0
0 0 1 C1
0 1 0 C2
0 1 1 Control Register
Applications
Output Mode
8279 provides two output modes for selecting the display options. In this mode,
8279 provides 8 or 16 character-multiplexed displays those can be organized
as dual 4-bit or single 8-bit display units. 8279 allows options for data entry on
the displays.
This mode deals with display-related operations. This mode is further classified into two
output modes.
Display Entry − This mode allows the data to be entered for display either from the
right side/left side.
10 What is meant by key bouncing?
When a key is pressed the contact bounce back and forth and settle down only after a small
time delay (about 20ms). Even though a key is actuated once, it will appear to have been
actuated several times. This problem is called Key Bouncing.
When you press a key down and it triggers the switch, sometimes the key can bounce. Since
computers run so quickly, this bouncing can register as multiple keystrokes as it triggers the switch
multiple times. Debouncing mechanisms detect these bounces and register them as only one
keystroke so you have more reliable key input. Debounce mechanisms are usually invisible to the
user and you (usually) won’t be able to trigger them by trying to press the key repeatedly. If you can
trigger the debounce mechanism by pressing a key multiple times in quick succession, you have what
I call a Shitty Keyboard
The 8255, primarily, can be programmed in two basic modes : Bit Set/Reset (BSR) mode and
I/O mode. The BSR mode is used to set or reset the bits in port C.
Two groups – group A and group B are available for strobed data transfer.
1. Each group contains one 8-bit data I/O port and one 4-bit control/data port. 2. The 8-bit data port
can be either used as input or output port. The inputs and outputs both are latched. 3. Out of 8-bit
port C, PC0-PC2 is used to generate control signals for port B and PC3=PC5 are used to generate
control signals for port A. The lines PC6, PC7 may be used as independent data lines.
The two basic modes are selected by D7 bit of control register. When D7=1 it is an I/O
mode and when D7=0; it is a BSR mode.
BSR mode-
1. The pin of port C is selected using bit select bits [b b b] and set or reset is decided by
bit S/R ̅.
2. The BSR mode affects only one bit of port C at a time. 6.0The bit set using BSR
mode remains set unless and until you change the bit. So to set any bit of port C, bit
pattern is loaded in control register.
3. If a BSR mode is selected it will not affect I/O mode.
I/O modes-
17 State your idea on the different types of command words used in 8259?
a. The edge sense circuit is reset, which means that following initialization, an
interrupt request (IR) input must make a low-to-high transition to generate an
interrupt.
b. The Interrupt Mask Register is cleared.
In an MCS 80/85 system, the 8 request levels will generate CALLs to 8 locations
equally spaced in memory.
These can be programmed to be spaced at intervals of 4 or 8 memory locations, thus
the 8 routines will occupy a page of 32 or 64 bytes, respectively.
The address format is 2 bytes long (A0-A15).
When the routine interval is 4, A0±A4 are automatically inserted by the 8259A, while
A5-A15 are programmed externally.
When the routine interval is 8, A0±A5 are automatically inserted by the 8259A, while
A6±A15 are programmed externally.
The 8-byte interval will maintain compatibility with current software, while the 4-byte
interval is best for a compact jump table. In an 8086 system A15-A11 are inserted in
the five most significant bits of the vectoring byte and the 8259A sets the three least
significant bits according to the interrupt level. A10±A5 are ignored and ADI
(Address interval) has no effect.
LTIM: If LTIM e 1, then the 8259A will operate in the level interrupt mode. Edge detect
logic on the interrupt inputs will be disabled.
ADI: CALL address interval. ADI =1 then interval= 4; ADI =0 then interval =8.
SNGL: Single. Means that this is the only 8259A in the system. If SNGL = 1 no ICW3 will
be issued.
IC4: If this bit is setÐICW4 has to be read. If ICW4 is not needed, set IC4= 0
After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is
ready to accept interrupt requests at its input lines. However, during the 8259A operation, a
selection of algorithms can command the 8259A to operate in various modes through the
Operation Command Words (OCWs).
The control words written to control register state an I/O function for every I.O port. The bit D7 of
the control word verifies either the I/O function of the BSR function A port can be programmed to
act as an input port or an output port. To tell about that we generate a bit pattern or we may
say a word which is called control word. A control word is, therefore, to be formed for
programming the ports of 8255A.
The format for the control word format for 8255A is shown in figure bellow. As per the
requirement of the programmer the control word is written into the control word register of
8255A. No read operation of the control word is allowed.
So from above control word format for 8255A diagram we can see the bit wise
function of control word generation. Now we go for further description of the control
bits. We know in control word format it has 8 bits. In addition,every bit responsible
for respective work. Now see what are the work those bits do?
Bit D0 :
Bit D1:
Bit D2:
Bit D4:
PART IV
The 8051 Microcontroller Memory is separated in Program Memory (ROM) and Data
Memory (RAM). The Program Memory of the 8051 Microcontroller is used for storing the
program to be executed i.e., instructions. The Data Memory on the other hand, is used for
storing temporary variable data and intermediate results.
8051 Microcontroller has both Internal ROM and Internal RAM. If the internal memory is
inadequate, you can add external memory using suitable circuits.
In 8051 Microcontroller, the code or instructions to be executed are stored in the Program
Memory, which is also called as the ROM of the Microcontroller. The original 8051
Microcontroller by Intel has 4KB of internal ROM.
Some variants of 8051 like the 8031 and 8032 series doesn’t have any internal ROM
(Program Memory) and must be interfaced with external Program Memory with instructions
loaded in it.
Almost all modern 8051 Microcontrollers, like 8052 Series, have 8KB of Internal Program
Memory (ROM) in the form of Flash Memory (ROM) and provide the option of
reprogramming the memory.
In case of 4KB of Internal ROM, the address space is 0000H to 0FFFH. If the address space
i.e., the program addresses exceed this value, then the CPU will automatically fetch the code
from the external Program Memory.
For this, the External Access Pin (EA Pin) must be pulled HIGH i.e., when the EA Pin is
high, the CPU first fetches instructions from the Internal Program Memory in the address
range of 0000H to 0FFFFH and if the memory addresses exceed the limit, then the
instructions are fetched from the external ROM in the address range of 1000H to FFFFH.
There is another way to fetch the instructions: ignore the Internal ROM and fetch all the
instructions only from the External Program Memory (External ROM). For this scenario, the
EA Pin must be connected to GND. In this case, the memory addresses of the external ROM
will be from 0000H to FFFFH
The Data Memory or RAM of the 8051 Microcontroller stores temporary data and
intermediate results that are generated and used during the normal operation of the
microcontroller. Original Intel’s 8051 Microcontroller had 128B of internal RAM.
But almost all modern variants of 8051 Microcontroller have 256B of RAM. In this 256B, the
first 128B i.e., memory addresses from 00H to 7FH is divided in to Working Registers
(organized as Register Banks), Bit – Addressable Area and General Purpose RAM (also
known as Scratchpad area).
In the first 128B of RAM (from 00H to 7FH), the first 32B i.e., memory from addresses 00H
to 1FH consists of 32 Working Registers that are organized as four banks with 8 Registers in
each Bank.
The 4 banks are named as Bank0, Bank1, Bank2 and Bank3. Each Bank consists of 8
registers named as R0 – R7. Each Register can be addressed in two ways: either by name or
by address.
To address the register by name, first the corresponding Bank must be selected. In order to
select the bank, we have to use the RS0 and RS1 bits of the Program Status Word (PSW)
Register (RS0 and RS1 are 3rd and 4th bits in the PSW Register).
When addressing the Register using its address i.e., 12H for example, the corresponding
Bank may or may not be selected. (12H corresponds to R2 in Bank2).
The next 16B of the RAM i.e., from 20H to 2FH are Bit – Addressable memory locations.
There are totally 128 bits that can be addressed individually using 00H to 7FH or the entire
byte can be addressed as 20H to 2FH.
For example 32H is the bit 2 of the internal RAM location 26H.
The final 80B of the internal RAM i.e., addresses from 30H to 7FH, is the general purpose
RAM area which are byte addressable.
The 8051 has two timers: timer0 and timer1. They can be used either as timers or as counters. Both
timers are 16 bits wide. Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two
separate registers of low byte and high byte. First we shall discuss about Timer0 registers.
Timer0 registers is a 16 bits register and accessed as low byte and high byte. The low byte is referred
as a TL0 and the high byte is referred as TH0. These registers can be accessed like any other
registers.
Timer1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and TH1.
TMOD (timer mode) Register: This is an 8-bit register which is used by both timers 0 and 1 to set
the various timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the upper 4
bits are set aside for timer1. In each case, the lower 2 bits are used to set the timer mode and upper
2 bits to specify the operation.
In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting and stopping.
Some timers do this by software, some by hardware, and some have both software and hardware
controls. The hardware way of starting and stopping the timer by an external source is achieved by
making GATE=1 in the TMOD register. And if we change to GATE=0 then we do no need external
hardware to start and stop the timers.
The second bit is C/T bit and is used to decide whether a timer is used as a time delay generator
or an event counter. If this bit is 0 then it is used as a timer and if it is 1 then it is used as a counter.
By default, the 8051 microcontroller is powered up with register bank 0; and, by using the
Program Status Word (PSW), we can switch to other banks. The two bits of PSW are used for
switching between the register banks. These two bits are accessed by the bit-addressable
instructions SETB and CLR.
Based on the possible combinations of RS1 and RS0 of PSW, the register bank is changed
accordingly, i.e., if RS1 and RS0 are 0, then the Bank 0 is selected. Similarly, Bank1, 2&3
are selected as per the values of RS1 and RS0.
1. Idle mode
2. Power down mode
In this mode, clock supply is cut from the whole system. In this power saving mode
maximum amount of power is saved.
1. Restart
In this method, the system is restarted, and the previous data is lost.
Idle mode is equivalent to sleep mode and power down mode is equivalent to hibernate in this
generation of computers.
This is all about the power saving mode of 8051. For more information about 8051 visit the
section of 8051
There is a SFR ( last SFR in our list ) for power control mode in 8051. Only two bits in the
register are related to power saving mode in 8051 ( PD, IDL )
8051 addressing modes. If you’re familiar with 8051 already, you may know an addressing
mode is a way to address an operand. If you are new, don’t worry – we’ve covered every
aspect about 8051 addressing modes in detail. Let’s begin the journey.
Lets begin this article with a simple question. “What is an addressing mode ?“. A simple
question always has a simple answer too. Addressing mode is a way to address an operand.
Operand means the data we are operating upon (in most cases source data). It can be a direct
address of memory, it can be register names, it can be any numerical data etc. I will explain
this with a simple data move instruction of 8051.
Here the data 6A is the operand, often known as source data. When this instruction is
executed, the data 6AH is moved to accumulator A. There are 5 different ways to execute this
instruction and hence we say, we have got 5 addressing modes for 8051. They are
This addressing mode is named as “immediate” because it transfers an 8-bit data immediately to the
accumulator
The opcode for MOV A, # data is 74H. The opcode is saved in program memory at 0202 address. The
data 6AH is saved in program memory 0203. (See, any part of the program memory can be used, this
is just an example) When the opcode 74H is read, the next step taken would be to transfer whatever
data at the next program memory address (here at 0203) to accumulator A (E0H is the address of
accumulator). This instruction is of two bytes and is executed in one cycle. So after the execution of
this instruction, program counter will add 2 and move to o204 of program memory.
This is another way of addressing an operand. Here the address of the data (source data ) is
given as operand. Lets take an example.
Here 04H is the address of register 4 of register bank#0. When this instruction is executed, what ever
data is stored in register 04H is moved to accumulator. In the picture below we can see, register 04H
holds the data 1FH. So the data 1FH is moved to accumulator.
2 byte instruction which requires 1 cycle to complete. Program counter will increment by 2
and stand in 0204. The opcode for instruction MOV A, address is E5H. When the instruction
at 0202 is executed (E5H), accumulator is made active and ready to receive data. Then
program control goes to next address that is 0203 and look up the address of the location
(04H) where the source data (to be transferred to accumulator) is located. At 04H the control
finds the data 1F and transfers it to accumulator and hence the execution is completed.
In this addressing mode we use the register name directly At a time registers can take value
from R0,R1…to R7. You may already know there are 32 such registers. So how you access
32 registers with just 8 variables to address registers? Here comes the use of register banks.
There are 4 register banks named 0,1,2 and 3. Each bank has 8 registers named from R0 to
R7. At a time only one register bank can be selected. Selection of register bank is made
possible through a Special Function Register (SFR) named Processor Status Word (PSW).
PSW is an 8 bit SFR where each bit can be programmed. Bits are designated from PSW.0 to
PSW.7 Register banks are selected using PSW.3 and PSW.4 These two bits are known as
register bank select bits as they are used to select register banks. A picture below shows the
PSW register and the Register Bank Select bits with status
So we see that opcode for MOV A, R4 is EC. The opcode is stored in program memory
address 0202 and when it is executed the control goes directly to R4 of the respected register
bank (that is selected in PSW). If register bank #0 is selected then the data from R4 of
register bank #0 will be moved to accumulator. (Here it is 2F stored at 04 H). 04 H is the
address of R4 of register bank #0. Movement of data (2F) in this case is shown as bold line.
Now please take a look at the dotted line. Here 2F is getting transferred to accumulator from
data memory location 0C H. Now understand that 0C H is the address location of Register 4
(R4) of register bank #1. Programmers usually get confused with register bank selection.
Also keep in mind that data at R4 of register bank #0 and register bank #1 (or even other
banks) will not be same. So wrong selection of register banks will result in undesired output.
Also note that the instruction above is 1 byte and requires 1 cycle for complete execution.
This means using register direct addressing mode can save program memory.
Register Indirect Addressing Mode
So in this addressing mode, address of the data (source data to transfer) is given in the
register operand.
The source operand is @A+DPTR and we know we will get the source data (to
transfer) from this location. It is nothing but adding contents of DPTR with
present content of accumulator. This addition will result a new data which is
taken as the address of source data (to transfer). The data at this address is
then transferred to accumulator
The opcode for the instruction is 93H. DPTR holds the value 01FE, where 01
is located in DPH (higher 8 bits) and FE is located in DPL (lower 8 bits).
Accumulator now has the value 02H. A 16 bit addition is performed and now
01FE H+02 H results in 0200 H. What ever data is in 0200 H will
get transferred to accumulator. The previous value inside accumulator (02H)
will get replaced with new data from 0200H. New data in the accumulator is
shown in dotted line box.
his is a 1 byte instruction with 2 cycles needed for execution. What you infer from that? The
execution time required for this instruction is high compared to previous instructions (which
all were 1 cycle).
The other example MOVC A, @A+PC works the same way as above example. The only
difference is, instead of adding DPTR with accumulator, here data inside program counter
(PC) is added with accumulator to obtain the target address.
I hope you now have a clear cut understanding of 8051 addressing modes. If you have any
doubts or need any additional clarifications, please post your comments below. I will answer
them
The register PSW (Program Status Word) or the program status word contains
information on the status of the CPU. Contains indicators or flags to use conditional
statements to make decisions. These indicators are changed automatically when any of the
instructions shown in the following table is executed, can also be modified by the user. The
PSW is in direct address 0D0H (SFRs area) and the address bit support bit by bit.
Indicators or flags
C: Carry Flag.
AC: Auxiliary Carry Flag indicates the carry from bit 3, is used for BCD operations.
F0: User Indicator or general purpose.
Ov: overflow indicator, when a drift in the 6 th and 7 th bit at a time.
P: parity indicator indicates 1 when the number is odd about the Acc.
Rs 0 and Rs 1: Selection of bank records.
Rs
RS0 Bank Address
1
0 0 0 00H to 07H
0 1 1 08H to 0FH
1 0 2 10H 17H
1 1 3 18H to 1FH
The CJNE instruction compares the first two operands and branches to the specified destination if
their values are not equal. If the values are the same, execution continues with the next instruction
CJNE compares the value of operand1 and operand2 and branches to the indicated relative address
if operand1 and operand2 are not equal. If the two operands are equal program flow continues with
the instruction following the CJNE instruction.
The Carry bit (C) is set if operand1 is less than operand2, otherwise it is cleared
The DJNZ instruction decrements the byte indicated by the first operand and, if the resulting
value is not zero, branches to the address specified in the second operand.
The relative address range for DJNZ instruction The 2-byte target address is to allow a jump
to any memory location from 0000 to FFFFH. SJMP (short jump) − It is a 2-byte instruction
where the first byte is the opcode and the second byte is the relative address of the target
location.
Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set
architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is
to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and
operate only on general-purpose registers.
There are two sets published by Intel: BMI (here referred to as BMI1) and BMI2; they were
both introduced with the Haswell microarchitecture. Another two sets were published by
AMD: ABM (Advanced Bit Manipulation, which is also a subset of SSE4a implemented by
Intel as part of SSE4.2 and BMI1), and TBM (Trailing Bit Manipulation, an extension
introduced with Piledriver-based processors as an extension to BMI1, but dropped again in
Zen-based processors)
14 Distinguish between microprocessor & micro controller.
A microprocessor is an IC which has only the CPU inside them, i.e. only the processing
powers such as Intel’s Pentium 1,2,3,4, core 2 duo, i3, i5 etc. These microprocessors don’t
have RAM, ROM, and other peripherals on the chip. A system designer has to add them
externally to make them functional. Applications of microprocessor include Desktop PC’s,
Laptops, notepads etc.
But this is not the case with Microcontrollers. A microcontroller has a CPU, in addition with
a fixed amount of RAM, ROM and other peripherals all embedded on a single chip. At times
it is also termed as a mini computer or a computer on a single chip. Today different
manufacturers produce microcontrollers with a wide range of features available in different
versions. Some manufacturers are ATMEL, Microchip, TI, Freescale, Philips, Motorola etc.
Microcontrollers are designed to perform specific tasks. Specific means applications where
the relationship of input and output is defined. Depending on the input, some processing
needs to be done and output is delivered. For example, keyboards, mouse, washing machine,
digicam, pendrive, remote, microwave, cars, bikes, telephone, mobiles, watches, etc. Since
the applications are very specific, they need small resources like RAM, ROM, I/O ports etc
and hence can be embedded on a single chip. This in turn reduces the size and the cost.
Microprocessors find applications where tasks are unspecific like developing software,
games, websites, photo editing, creating documents etc. In such cases the relationship
between input and output is not defined. They need high amount of resources like RAM,
ROM, I/O ports etc.
The clock speed of the Microprocessor is quite high as compared to the microcontroller.
Whereas the microcontrollers operate from a few MHz to 30 to 50 MHz, today’s
microprocessors operate above 1GHz as they perform complex tasks. Read more about what
is microcontroller.
8 – Bit ALU: ALU or Arithmetic Logic Unit is the heart of a microcontroller. It performs
arithmetic and bitwise operation on binary numbers. The ALU in 8051 is an 8 – Bit ALU i.e. it
can perform operations on 8 – bit data.
8 – Bit Accumulator:The Accumulator is an important register associated with the ALU. The
accumulator in 8051 is an 8 – bit register.
RAM: 8051 Microcontroller has 128 Bytes of RAM which includes SFRs and Input / Output
Port Registers.
ROM: 8051 has 4 KB of on-chip ROM (Program Memory).
I/O Ports: 8051 has four 8 – bit Input / Output Ports which are bit addressable and
bidirectional.
Timers / Counters: 8051 has two 16 – bit Timers / Counters.
Serial Port: 8051 supports full duplex UART Communication.
External Memory: 8051Microcontroller can access two 16 – bit address line at once: one
each for RAM and ROM. The total external memory that an 8051 Microcontroller can access
for RAM and ROM is 64KB (2 16 for each type).
Additional Features: Interrupts, on-chip oscillator, Boolean Processor, Power Down Mode,
etc.
A Special Function Register (or Special Purpose Register, or simply Special Register) is a
register within a microprocessor that controls or monitors the various functions of a
microprocessor. As the special registers are closely tied to some special function or status of
the processor, they might not be directly writable by normal instructions (like add, move,
etc.). Instead, some special registers in some processor architectures require special
instructions to modify them.
In the 8051, register A, B, DPTR, and PSW are a part of the group of registers commonly
referred to as SFR (special function registers). An SFR can be accessed by its name or by its
address.
Byte
Bit Address
Address
FF
F0 F7 F6 F5 F4 F3 F2 F1 F0 B
E0 E7 E6 E5 E4 E3 E2 E1 E0 ACC
D0 D7 D6 D5 D4 D3 D2 - D0 PSW
B8 - - - BC BB BA B9 B8 IP
B0 B7 B6 B5 B4 B3 B2 B1 B0 P3
A2 AF - - AC AB AA A9 A8 IE
A0 A7 A6 A5 A4 A3 A2 A1 A0 P2
99 Not bit Addressable SBUF
98 9F 9E 9D 9C 9B 9A 99 98 SCON
90 97 96 95 94 93 92 91 90 P1
8D Not bit Addressable TH1
8C Not bit Addressable TH0
8B Not bit Addressable TL1
8A Not bit Addressable TL0
89 Not bit Addressable TMOD
88 8F 8E 8D 8C 8B 8A 89 88 TCON
87 Not bit Addressable PCON
83 Not bit Addressable DPH
82 Not bit Addressable DPL
81 Not bit Addressable SP
80 87 87 85 84 83 82 81 80 P0
A special function register can have an address between 80H to FFH. These addresses
are above 80H, as the addresses from 00 to 7FH are the addresses of RAM memory
inside the 8051.
Not all the address space of 80 to FF are used by the SFR. Unused locations, 80H to
FFH, are reserved and must not be used by the 8051 programmer.
PART V
Light dependent resistor LDR Phototransistor Photo sensors are used in much the same way as
pressure sensors. If we hook one up to a microcontroller via a voltage divider (or RC time) circuit,
the microcontroller can sense how much light is falling on the device
Embedded systems are increasingly using multiple sensors to sample their environment. A large
number of these sensors use simple serial interfaces that produce digital output, which can be
directly processed by the microcontroller. Some of these systems use traditional serial interfaces
that are multiplexed among the sensors to provide the controllers with the structure to handle just
one input at a time (GPIO, I²C, SPI, RS232, RS422, etc.). Other serial sensor devices incorporate full
protocol management of the USB interface and that interface's methods for multi-device
management.
While communication with sensors is digital, most sensors are analog. Analog sensors include light
and IR detectors, thermocouples, touch controllers, sound and external-area motion sensors, device
position and movement sensors, and temperature and pressure sensors. The resolution and
accuracy levels of analog sensors dictate not only the size of the data stores and word size but also
the speed and math processing capabilities of the MCU.
Since there many different types of sensors, the primary method for system development involves
selecting a core controller and then programming in software an application that calls an interface
software routine for the specific sensor being used. Using this approach, the designer can create a
common design platform and GUI while leaving the final optimization step for a particular sensor
and application until the very end of the design cycle. Most of the MCU software development kits
(SDKs) are designed to support this methodology and include development boards that are
optimized for this approach.
Advantages
Microprocessor is that these are general purpose electronic processing devices which can
be programmed to execute a number of tasks.
Microprocessor is its speed, which is measured in hertz
Microprocessor is that it can quickly move data between the various memory
locations
1. Permanent Magnet Stepper. PM steppers have rotors that are constructed with permanent
magnets, which interact with the electromagnets of the stator to create rotation and torque.
PM steppers usually have comparatively low power requirements and can produce more
torque per unit of input power.
2. Variable Reluctance Stepper. VR stepper rotors are not built with permanent magnets.
Rather, they are constructed with plain iron and resemble a gear, with protrusions or
“teeth” around the circumference of the rotor. The teeth lead to VR steppers that have a
very high degree of angular resolution; however, this accuracy usually comes at the expense
of torque.
3. Hybrid Syncronous Stepper. HS stepper rotors use the best features of both PM and VR
steppers. The rotor in an HS motor has a permanent magnet core, while the circumference is
built from plain iron and has teeth. A hybrid synchronous motor, therefore, has both high
angular resolution and high torque.
To change direction you need to reverse the current in one set of coils only. At the moment the two
motors are connected in parallel and turn in the same direction. Swap ONE of the coil pairs over and
you should be able to get the two motors turn in the opposite direction with the same drive signal
Current through 1a, 1b coils will turn the rotor so it is aligned as shown above. Turn on the current
(in the appropriate direction) the rotor turns clockwise (half step) between 1a, 2a. Turn off the
current to 1a, 1b and the rotor turns clockwise (another half step) to align with 2a, 2b. Reversing the
direction of the current in the coils produces motion in the same direction. To change direction you
need to reverse the current in one set of coils only. At the moment the two motors are connected in
parallel and turn in the same direction. Swap ONE of the coil pairs over and you should be able to get
the two motors turn in the opposite direction with the same drive signal.
While interfaces such as Ethernet, FireWire, and USB also send data as a serial stream, the
term serial port usually denotes hardware compliant with RS-232 or a related standard, such
as RS-485 or RS-422.
Modern consumer PCs have largely replaced serial ports with higher-speed standards,
primarily USB. However, serial ports are still frequently used in applications demanding
simple, low-speed interfaces, such as industrial automation systems, scientific instruments,
point of sale systems and some industrial and consumer products.
Server computers may use a serial port as a control console for diagnostics, while networking
hardware (such as routers and switches) commonly use serial console ports for configuration,
diagnostics, and emergency maintenance access. To interface with these and other devices,
USB-to-serial converters can quickly and easily add a serial port to a modern PC.
7 State in your own words how is stepper motor interfaced with 8051?
Stepper Motor Interfacing with 8051 Microcontroller. Stepper motor is brushless DC motor, which
can be rotated in small angles, these angles are called steps. Generally stepper motor use 200 steps
to complete 360 degree rotation, means its rotate 1.8 degree per step
Stepper motor used in many devices which needs precise rotational movement like robots,
antennas, hard drives etc. We can rotate stepper motor to any particular angle by giving it
proper instructions.
Stepper motors are basically two types: Unipolar and Bipolar. Unipolar stepper motor
generally has five or six wire, in which four wires are one end of four stator coils, and other
end of the all four coils is tied together which represents fifth wire, this is called common
wire (common point). Generally there are two common wire, formed by connecting one end
of the two-two coils as shown in below figure. Unipolar stepper motor is very common and
popular because of its ease of use.
Stands for "Interrupt Service Routine." An ISR (also called an interrupt handler) is a software
process invoked by an interrupt request from a hardware device. It handles the request and
sends it to the CPU, interrupting the active process. When the ISR is complete, the process is
resumed.
A basic example of an ISR is a routine that handles keyboard events, such as pressing or
releasing a key. Each time a key is pressed, the the ISR processes the input. For example, if
you press and hold the right arrow key in a text file, the ISR will signal to the CPU that the
right arrow key is depressed. The CPU sends this information to the active word processor or
text editing program, which will move the cursor to the right. When you let go of the key, the
ISR handles the "key up" event. This interrupts the previous "key down" state, which signals
to the program to stop moving the cursor.
SBUF register
Its an 8 bit register used solely for serial communication in 8051. For a byte of data to be
transferred via TxD line, it muse be placed in SBUF register. Similarly SBUF register holds
the serially inputed data received by TxD line of 8051
The 8051 Microcontroller Special Function Registers are used to program and control different
hardware peripherals like Timers, Serial Port, I/O Ports etc. In fact, by manipulating the 8051
Microcontroller Special Function Registers (SFRs), you can assess or change the operating mode of
the 8051 Microcontroller.
The 8051 Microcontroller Special Function Registers act as a control table that monitor and
control the operation of the 8051 Microcontroller. If you observe in Internal RAM Structure,
the Address Space from 80H to FFH is allocated to SFRs.
Out of these 128 Memory Locations (80H to FFH), there are only 21 locations that are
actually assigned to SFRs. Each SFR has one Byte Address and also a unique name which
specifies its purpose.
Since the SFRs are a part of the Internal RAM Structure, you can access SFRs as if you
access the Internal RAM. The main difference is the address space: first 128 Bytes (00H to
7FH) is for regular Internal RAM and next 128 Bytes (80H to FFH) is for SFRs.
TIP: As only 21 of the possible 128 SFR memory locations are assigned, it is recommended
that the remaining registers or memory locations are not accessed during programming.
A or ACC
B
DPL
DPH
IE
Types of memory
There are two basic kinds of memory used in microprocessor systems - commonly called
Read Only Memory and Read / Write Memory, but more usually called ROM and RAM -
"Read Only Memory" and "Random Access Memory". The program may be stored in ROM
or RAM - the program does n ot normally change while it executes - while data is stored in
the registers and RAM. Of course, if you turn off the chip and turn it on again, you have lost
all the contents of the registers, and RAM.
In a typical computer , as much as possible (including most of the program instructions and
all the data) is in RAM, to give the maximum possible flexibility; you have basic
programmes allowing you to interact with discs, keyboards and the display in ROM, and load
in as much of the software as possible when you run the programs. Storing these in ROM
means they always available, even when the computer has only just been switched on.
RAM
Random Access Memory (RAM) is usually used for storing programs and data in a computer.
Most computers also use some Read Only Memory (ROM) or Erasable-Programmable Read
Only Memory (EPROM). This stores programs (or libraries of procedures) which do not need
to be changed. (This usuallly includes the program that is executed when the computer is first
turned on, and the procedures required to access permanently connected peripherals - such as
the keyboard, display, disk drive, ...).
Static RAM is composed of D-Type Flip-Flops, and is extremely fast, however it is also
expensive. It is therefore usually reserved for applications requiring a high speed (such as
graphics display memory or cache memory).The main computer memory is usually formed
from Dynamic RAM (DRAM), which uses an array of "capacitor" storage elements.
Although slower than SRAM, it is also much cheaper, and therefore it usually possible to buy
many MB of Dyanmic RAM per computer.
ROM
There are a number of different types of ROM; the cheapest, when produced in very large
quantities, is "Masked ROM", often just called ROM. Here the individual voltages (bits) are
fixed high or low when the chip is made, and cannot be altered; they are determined by the
pattern of connections in the mask used to make the chip.
The diagram below gives an idea of the implementation of a ROM. The outputs of the open-
drain transistors are logic '0' (when selected by a logic '1' on the 'word line') only if their
source terminals are grounded when the ROM is program is created in silicon other wise
logic '1' is maintained by a pull-up resistor.
Producing a mask for ROM is quite expensive; it is justifiable if you have a large production
run, say of many 10,000s.
PROM/EPROM
Another type of ROM is programmable (PROM). The pattern of 0 and 1 values of bits can be
determined after production, usually by selectively applying high voltages to some of the
memory locations. The contents of program memory area is only fixed after manufacture (it
can be done by sending voltages in through two of the pins in the correct sequence)
Some devices are made with EPROM - this stands for "Erasable Programmable Read Only
Memory" This means that there is a quartz window which allows you to illuminated the chip
with UV radiation, which puts the chip back into its original state, and allows fresh
programming. PROMs and EPROMs are very similar inside, but only some of them have a
window to allow you to erase the pattern. So some are OTP - "One Time Programmable" -
and these are cheaper.
EEPROM/FLASH
In some applications, it is desirable to store data for long periods of time, but to allow the
data to be erased as and when required. Examples include the configuration of the disks
conencted to a computer, the network name, operating system password. This could be done
by using RAM, and providing a back-up battery which kept the RAM powered when the
main computer power supply is turned off. Some RAM chips require very little power when
the data is not being accessed and this is sometimes the chosen approach. Two other types of
memory may also be used which require no power supply to retain their data. They have the
advantage that the memory chip may actually be removed from the computer without loss of
data.
The first type of memory is Electrically Erasable EPROM, EEPROM. Standard EPROM can
be thought of as series of 'potential wells' into which electrons can be forced (over the SiO2
barrier) by applying bias (see the left hand diagram below); electrons can only be ejected
from the wells by strong UV light applied through the EPROM chip's erasure window. In
EEPROM, the SiO2 barrier is thin, and electrons can 'tunnel' through it.
FLASH memory is often used to store programs and data, it too can be re-programmed and is
often packaged for computers in PCMCIA cards (about the size of a credit card). Smaller
FLASH memory cards are frequently used in such items as digital cameras.
Mico-Controller Memory
Micro-controllers are usually used for a single application, and in contrast to general purpose
computers usually execute only a single program for the entire life. In this case, the program
is usually also stored in ROM. Most microcontrollers contain an in-built EPROM or ROM.
The latter allows them to be programmed and re-programmed. This type of microcontoller is
often to be found in laboratories were software is being developed. The contents of the
memory is "erased" by exposing the "window" on top of the chip to strong ultra-violet light.
This erases all data in the chip (it can not be used to erase a single byte), but allows the entire
chip to re-programmed.
A timer is a specialized type of clock which is used to measure time intervals. A timer that
counts from zero upwards for measuring time elapsed is often called a stopwatch. It is a
device that counts down from a specified time interval and used to generate a time delay, for
example, an hourglass is a timer.
A counter is a device that stores (and sometimes displays) the number of times a particular
event or process occurred, with respect to a clock signal. It is used to count the events
happening outside the microcontroller. In electronics, counters can be implemented quite
easily using register-type circuits such as a flip-flop.
Timer Counter
The register incremented for every The register is incremented considering 1 to 0 transition at
machine cycle. its corresponding to an external input pin (T0, T1).