ASSIGNMENT

ON
MICROPROCESSOR
AND
MICROCONTROLLER

JOYAL JOSE AUGUSTINE

1 Identify the difference between Macro and subroutine.

Subroutines (FORM) can be called from both the program the are defined in and other
programs. A MACRO is more or less an abbreviation for some lines of code that are used more
than once or twice. A FORM is a local subroutine (which can be called external).

2 Name the different types of interrupts supported by8086.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt
and INTR is a maskable interrupt having lower priority.

Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes

3 List the flag register in 8086.

Flag register of 8086 microprocessor

Sign Flag (S)

Zero Flag (Z)

Auxiliary Cary Flag (AC)

Parity Flag (P)

Carry Flag (CY) ...

Overflow Flag (O) – This flag will be set (1) if the result of a signed operation is too large to fit in
the number of bits available to represent it, otherwise reset (0).

4 Define stack segment register.

The stack segment register (SS) is usually used to store information about the memory segment
that stores the call stack of currently executed program. SP points to current stack top. By
default, the stack grows downward in memory, so newer values are placed at lower memory
addresses.

5 What are the assembler directives there in 8086?

An assembler supports directives to define data, to organise segments to control procedure, to

define macros. It consists of two types of statements: instructions and directives. The
instructions are translated to the machine code by the assembler whereas directives are not
translated to the machine codes.
Assembler Directives of the 8086 Microprocessor

(a) The DB directive

(b) The DW directive

(c) The DD directive

(d) The STRUCT (or STRUC) and ENDS directives (counted as one)

(e)The EQU Directive

(f)The COMMENT directive

(g)ASSUME

(h) EXTERN

(i) GLOBAL

(j) SEGMENT

(k)OFFSET

(l) PROC
 (m)GROUP

(n) INCLUDE

6 Outline the different type of addressing modes of8086

The addressing modes provided by the 8086 family include displacement-only, base,
displacement plus base, base plus indexed, and displacement plus base plus indexed. Variations
on these five forms provide the 17 different addressing modes on the 8086.

7 Express physical address generated in 8086?

The 8086 addresses a segmented memory. The complete physical address which is 20-bits long
is generated using segment and offset registers each of the size 16-bit. The content of a segment
register also called as segment address, and content of an offset register also called as offset
address.

8 State in your own words the 8086 instructions used for BCD arithmetic.

For BCD arithmetic the following instructions are used,

Signed 8-bit or 16-bit division. Increment Register or memory by 1. Decrement register or

memory by 1. Decimal Adjust after BCD Addition: When two BCD numbers are added, the DAA is
used after ADD or ADC instruction to get correct answer in BCD.

9 Classify the program control instructions available in 8086

Instructions to transfer the instruction during an execution without any condition −

CALL − Used to call a procedure and save their return address to the stack.

RET − Used to return from the procedure to the main program.

JMP − Used to jump to the provided address to proceed to the next instruction.

Instructions to transfer the instruction during an execution with some conditions −

JA/JNBE − Used to jump if above/not below/equal instruction satisfies.

JAE/JNB − Used to jump if above/not below instruction satisfies.

JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.

JC − Used to jump if carry flag CF = 1

JE/JZ − Used to jump if equal/zero flag ZF = 1

JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.

JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.

JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.

JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.

JNC − Used to jump if no carry flag (CF = 0)

JNE/JNZ − Used to jump if not equal/zero flag ZF = 0

JNO − Used to jump if no overflow flag OF = 0

JNP/JPO − Used to jump if not parity/parity odd PF = 0

 JNS − Used to jump if not sign SF = 0

JO − Used to jump if overflow flag OF = 1

JP/JPE − Used to jump if parity/parity even PF = 1

JS − Used to jump if sign flag SF = 1

10 Describe about program counter and stack pointer register in 8086.

The program counter (PC) is a register that manages the memory address of the instruction to
be executed next. The address specified by the PC will be + n (+1 for a 1-word instruction and +2
for a 2-word instruction) each time one instruction is executed.

In 8086, the main stack register is called stack pointer - SP. The stack segment register (SS) is
usually used to store information about the memory segment that stores the call stack of
currently executed program. SP points to current stack top.

1 (i) Identify the use of the following assembler directives: DD, ASSUME, EQU.

(ii) Explain about the Interrupt handling process in 8086.

(i) DD – The DD directive is used to declare a DWORD – A DWORD double word is made up of 32
bits =2 Word’s or 4 BYTE.

The EQU directive is used to give name to some value or symbol. Each time the assembler finds
the given names in the program, it will replace the name with the value or a symbol. The value
can be in the range 0 through 65535 and it can be another Equate declared anywhere above or
below.

ASSUME: Shows the segment name to the assembler. It provides information to the assembler
regarding the name of the program or data segment for that particular segment.

The job of the interrupt handler is to service the device and stop it from interrupting. Once the
handler returns, the CPU resumes what it was doing before the interrupt occurred.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt
and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is
INTA called interrupt acknowledge.
 NMI

It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt
request pin (INTR)and it is of type 2 interrupt.

When this interrupt is activated, these actions take place −

Completes the current instruction that is in progress.

Pushes the Flag register values on to the stack.

Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on
to the stack.

IP is loaded from the contents of the word location 00008H.

CS is loaded from the contents of the next word location 0000AH.

Interrupt flag and trap flag are reset to 0.

INTR

The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt
Flag instruction.

The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled,
then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first
‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor
receives the 8 bit, say X, from the programmable interrupt controller.
 These actions are taken by the microprocessor −

First completes the current instruction.

Activates INTA output and receives the interrupt type, say X.

Flag register value, CS value of the return address and IP value of the return address are pushed
on to the stack.

IP value is loaded from the contents of word location X × 4

CS is loaded from the contents of the next word location.

Interrupt flag and trap flag is reset to 0

Software Interrupts

Some instructions are inserted at the desired position into the program to create interrupts.
These interrupt instructions can be used to test the working of various interrupt handlers. It
includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte provides the
interrupt type number. There are 256 interrupt types under this group.

2 (i) Write an 8086 ALP to convert BCD data to Binary data.

(ii) Identify the conditions which cause the 8086 to perform type 0 and type 1 interrupt.

DATA SEGMENT

NO1 DB "9036"

D2 DB ?
D1 DB 16 DUP(?)

DATA ENDS

CODE SEGMENT

ASSUME CS:CODE, DS:DATA

START:

MOV AX, DATA

MOV DS, AX

LEA SI, NO1

LEA DI, D1

MOV CX, 04H

TOP:

MOV AL, [SI]

MOV DX, 0CH

UP1:

ROL AX,1

DEC DX

JNZ UP1

AND AX, 1111000000000000B

MOV DX, 04H

UP2:

ROL AX, 1

JNC DN

MOV BX, 1

MOV [DI], BX

JMP DN2
 DN:

MOV BX, 0

MOV [DI], BX

DN2:

INC DI

DEC DX

JNZ UP2

INC SI

DEC CX

JNZ TOP

INT 3

CODE ENDS

END START

(ii). The 8086 will automatically do a type 0 interrupt if the result of a DIV operation or an IDIV
operation is too large to fit in the destination register. For a type 0 interrupt, the 8086 pushes
the flag register on the stack, resets IF and TF and pushes the return addresses on the stack.

3 (i) Describe the internal architecture of 8086 microprocessor with neat diagrams.

(ii) List some of the assembler directives with examples

8086 does not have a RAM or ROM inside it. However, it has internal registers for storing
intermediate and final results and interfaces with memory located outside it through the System
Bus.

In case of 8086, it is a 16-bit Integer processor in a 40 pin, Dual Inline Packaged IC.

The size of the internal registers(present within the chip) indicate how much information the
processor can operate on at a time (in this case 16-bit registers) and how it moves data around
internally within the chip, sometimes also referred to as the internal data bus.

8086 provides the programmer with 14 internal registers, each 16 bits or 2 Bytes wide.

Memory segmentation:

To increase execution speed and fetching speed, 8086 segments the memory.

It’s 20 bit address bus can address 1MB of memory, it segments it into 16 64kB segments.

8086 works only with four 64KB segments within the whole 1MB memory.

The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU), and
The Execution Unit (EU).

(ii) ASSUME

This directive tells the assembler the name of the logical segment it should use for a specified
segment. For example ASSUME CS:CODE, tells the assembler that the instructions for a program
are in a logical segment named CODE. The 8086 works directly with only 4 physical segments: a
Code segment, a data segment, a stack segment, and an extra segment.
 DB – Define Byte

This directive is used to declare a byte type variable or to store a byte in memory location. For
example

NAME DB ‘THOMAS’;

VALUES DB ‘0’,’1’,’2’,’3’;

DD – Define Doubleword

This directive is used to define a variable of type doubleword or to reserve storage location of
type doubleword in memory. For example

POINTER DD 12341234H

DQ – Define Quadword

This directive is used to define a variable of type quadword or to reserve storage location of
type quadword in memory. For example

POINTER DQ 1234123412341234H

DT – Define Ten Bytes

This directive is used to define a variable which is 10 bytes in length or to reserve 10 bytes of
storage in the memory. For example

POINTER DT 11223344556677889900

DW – Define Word

This directive is used to define a variable of type word or to reserve storage location of type
word in memory.

4 Examine the various addressing modes available in 8086. Explain each mode with an example.

Types of addressing modes:

Register mode – In this type of addressing mode both the operands are registers.

Example:

MOV AX, BX

XOR AX, DX

ADD AL, BL
Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16 bit data.
Destination operand can never be immediate data.

Example:

MOV AX, 2000

MOV CL, 0A

ADD AL, 45

AND AX, 0000

Note that to initialize the value of segment register an register is required.

MOV AX, 2000

MOV CS, AX

Displacement or direct mode – In this type of addressing mode the effective address is directly
given in the instruction as displacement.

Example:

MOV AX, [DISP]

MOV AX, [0500]

Register indirect mode – In this addressing mode the effective address is in SI, DI or BX.

Example: Physical Address = Segment Address + Effective Address

MOV AX, [DI]

ADD AL, [BX]

MOV AX, [SI]

Based indexed mode – In this the effective address is sum of base register and index register.

Base register: BX, BP

Index register: SI, DI

The physical memory address is calculated according to the base register.

Example:
MOV AL, [BP+SI]

MOV AX, [BX+DI]

Indexed mode – In this type of addressing mode the effective address is sum of index register
and displacement.

Example:

MOV AX, [SI+2000]

MOV AL, [DI+3000]

Based mode – In this the effective address is the sum of base register and displacement.

Example:

MOV AL, [BP+ 0100]

Based indexed displacement mode – In this type of addressing mode the effective address is the
sum of index register, base register and displacement.

Example:

MOV AL, [SI+BP+2000]

String mode – This addressing mode is related to string instructions. In this the value of SI and DI
are auto incremented and decremented depending upon the value of directional flag.

Example:

MOVS B

MOVS W

Input/Output mode – This addressing mode is related with input output operations.

Example:

IN A, 45

OUT A, 50

Relative mode –

In this the effective address is calculated with reference to instruction pointer.

Example:
 JNZ 8 bit address

IP=IP+8 bit address

5 (i) explain the data transfer, arithmetic and branch instructions of 8086 microprocessor with examples.

(ii) Analyze an 8086 ALP to find the sum of numbers in an array of 10 elements.

(i). Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group −

Instruction to transfer a word

MOV − Used to copy the byte or word from the provided source to the provided destination.

PPUSH − Used to put a word at the top of the stack.

POP − Used to get a word from the top of the stack to the provided location.

PUSHA − Used to put all the registers into the stack.

POPA − Used to get words from the stack to all registers.

XCHG − Used to exchange the data from two locations.

XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

IN − Used to read a byte or word from the provided port to the accumulator.
OUT − Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

LEA − Used to load the address of operand into the provided register.

LDS − Used to load DS register and other provided register from the memory

LES − Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

LAHF − Used to load AH with the low byte of the flag register.

SAHF − Used to store AH register to low byte of the flag register.

PUSHF − Used to copy the flag register at the top of the stack.

POPF − Used to copy a word at the top of the stack to the flag register.

Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.

Following is the list of instructions under this group −

Instructions to perform addition

ADD − Used to add the provided byte to byte/word to word.

ADC − Used to add with carry.

INC − Used to increment the provided byte/word by 1.

AAA − Used to adjust ASCII after addition.

DAA − Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

SUB − Used to subtract the byte from byte/word from word.

SBB − Used to perform subtraction with borrow.

DEC − Used to decrement the provided byte/word by 1.

NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.

CMP − Used to compare 2 provided byte/word.

AAS − Used to adjust ASCII codes after subtraction.

DAS − Used to adjust decimal after subtraction.

Instruction to perform multiplication

MUL − Used to multiply unsigned byte by byte/word by word.

IMUL − Used to multiply signed byte by byte/word by word.

AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division

DIV − Used to divide the unsigned word by byte or unsigned double word by word.

IDIV − Used to divide the signed word by byte or signed double word by word.

AAD − Used to adjust ASCII codes after division.

CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.

CWD − Used to fill the upper word of the double word with the sign bit of the lower word.

Branch Instructions

It is also called program execution transfer instruction. Instructions of this group transfer
program execution from the normal sequence of instructions to the specified destination or
target. The following instructions come under this category:

JA or JNBE, Jump if above, not below, or equal i.e. when CF and ZF = 0

JAE/JNB/JNC ,Jump if above, not below, equal or no carry i.e. when CF = 0

JB/JNAE/JC ,Jump if below, not above, equal or carry i.e. when CF = 0

JBE/JNA ,Jump if below, not above, or equal i.e. when CF and ZF = 1

JCXZ ,Jump if CX register = 0

JE/JZ ,Jump if zero or equal i.e. when ZF = 1

JG/JNLE ,Jump if greater, not less or equal i.e. when ZF = 0 and CF = OF

JGE/JNL ,Jump if greater, not less or equal i.e. when SF = OF

JL/JNGE ,Jump if less, not greater than or equal i.e. when SF ≠ OF

JLE/JNG ,Jump if less, equal or not greater i.e. when ZF = 1 and SF ≠ OF

JMP ,Causes the program execution to jump unconditionally to the memory address or label
given in the instruction.

CALL ,Calls a procedure whose address is given in the instruction and saves their return
address to the stack.

RET ,Returns program execution from a procedure (subroutine) to the next instruction or
main program.

IRET ,Returns program execution from an interrupt service procedure (subroutine) to the
main program.

INT, Used to generate software interrupt at the desired point in a program.

INTO ,Software interrupts to indicate overflow after arithmetic operation.

LOOP ,Jump to defined label until CX = 0.

LOOPZ/LOOPE ,Decrement CX register and jump if CX ≠ 0 and ZF = 1.

LOOPNZ/LOOPNE , Decrement CX register and jump if CX ≠ 0 and ZF = 0.

Joyal: (ii).

DATA SEGMENT

ARR DB 5,3,7,1,9,2,6,8,4,10

LEN DW $-ARR

SUM DW ?

DATA ENDS

CODE SEGMENT

ASSUME DS:DATA CS:CODE

START:

MOV AX,DATA

MOV DS,AX
 LEA SI,ARR

MOV AX,0

MOV CX,LEN

REPEAT:

MOV BL,ARR[SI]

MOV BH,0

ADD AX,BX

INC SI

LOOP REPEAT

MOV SUM,AX

MOV AH,4CH

INT 21H

CODE ENDS

END START

1 Define Bus.

A bus is a network topology or circuit arrangement in which all devices are attached to a line
directly and all signals pass through each of the devices. Each device has a unique identity and
can recognize those signals intended for it.

2 State about External & Internal Bus.

An internal bus enables the communication between internal components, such as a video card
and memory. An external bus is capable of communicating with external peripherals, such as a
USB or SCSI device.

3 How would you explain two modes of operation in8086?

There are two operating modes of operation for Intel 8086, namely the minimum mode and the
maximum mode. When only one 8086 CPU is to be used in a microprocessor system, the 8086 is
used in the Minimum mode of operation. In a multiprocessor system 8086 operates in the
Maximum mode.

4 Distinguish the LOCK and TEST signal?

 The LOCK signal will be active until the completion of the next instruction. TEST' : This examined
by a 'WAIT' instruction. If the TEST pin goes low(0), execution will continue, else the processor
remains in an idle state. The input is internally synchronized during each of the clock cycle on
leading edge of the clock.

5 Compose the term ‘ Multiprogramming’

Multiprogramming means interleaved execution of several tasks on the same computer system.
One of the major aims of multiprogramming is to manage the various resources of the entire
system. Examples of multiprogramming operating systems are Windows, IOS, Excel, Firefox, etc.

6 Analyse the queue status of QS1 and QS0.

QS0, QS1 provide status to allow external tracking of the internal 8086 instruction queue. The
condition of queue status is shown in table 4. Queue status allows external devices like In-circuit
Emulators or special instruction set extension co-processors to track the CPU instruction
execution

7 Illustrate the timing diagram of Interrupt acknowledgement on a minimum mode system.

The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.

In minimum mode,8086 is the only processor in the system which provides all the control signals
which are needed for memory operations and I/O interfacing.

Here the circuit is simple but it does not support multiprocessing.

The other components which are transceivers, latches, 8284 clock generator, 74138 decoder,
memory and i/o devices are also present in the system.

The address bus of 8086 is 20 bits long. By this we can access 220 byte memory i.e. 1MB . Out of
20 bits, 16 bits A0 to A15(or 16 lines) are multiplexed with a data bus. By multiplexing, it means
they will act as address lines during the first T state of the machine cycle and in the rest, they act
as data lines. A16 to A19 are multiplexed S3 to S6 and BHE’ is multiplexed with S7.
8 Classify the I/O programming.

I/O operations can be divided into three groups: sensory input, control output, and data
transfer. Once the nature of each type of I/O operation is understood, the hardware design and
software for these operations can be understood easily.

9 Discuss about Semaphore.

A semaphore is an integer variable, shared among multiple processes. The main aim of using a
semaphore is process synchronization and access control for a common resource in a
concurrent environment. The initial value of a semaphore depends on the problem at hand.

10 Discriminate the minimum mode and maximum mode of operation.

1 Examine all the pin functions of 8086 processor configured in the maximum mode.

When MN/ MX’ = 0 , 8086 works in max mode.

Clock is provided by 8284 clock generator.

8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three such
latches are required because address bus is 20 bit. The ALE(Address latch enable) is connected
to STB(Strobe) of the latch. The ALE for latch is given by 8288 bus controller.

The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
because data bus is 16-bit. The transceivers are enabled the DEN signal, while the direction of
data is controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected to T. Both
DEN and DT/ R’ are given by 8288 bus controller.

Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288 bus
controller.

controller.
 Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0/GT0 has more priority than
RQ1/GT1.

INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.

In max mode, the advanced write signals get enabled one T-state in advance as compared to
normal write signals. This gives slower devices more time to get ready to accept the data,
therefore it reduces the number of cycles.

2 Discuss about the signals involved in minimum mode operation of 8086 with a microprocessor based

system with the timing diagram.

The 8086 microprocessor operates in minimum mode when MN/MX’ = 1.

In minimum mode,8086 is the only processor in the system which provides all the control signals
which are needed for memory operations and I/O interfacing.

Here the circuit is simple but it does not support multiprocessing.

The other components which are transceivers, latches, 8284 clock generator, 74138 decoder,
memory and i/o devices are also present in the system.
The address bus of 8086 is 20 bits long. By this we can access 220 byte memory i.e. 1MB . Out of
20 bits, 16 bits A0 to A15(or 16 lines) are multiplexed with a data bus. By multiplexing, it means
they will act as address lines during the first T state of the machine cycle and in the rest, they act
as data lines. A16 to A19 are multiplexed S3 to S6 and BHE’ is multiplexed with S7.

Control signals provided by 8086 for memory operations and i/o interfacing :

They are used to identifying whether the bus is carrying a valid address or not , in which
direction data is needed to be transferred over the bus, when there is valid write data on the
data bus and when to put read data on the system bus. Therefore, their sequence pattern
makes all the operations successful in a particular machine cycle.

The working of min mode can be easily understood by timing diagrams.

All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is given by processor in
the T1 state. It is available on the bus for one T-state.

In T2, the bus is tristated for changing the direction of the bus( in the case of a data read cycle.)

The data transfer takes place between T3 and T4.

If the addressed device is slower, then the wait state is inserted between T3 and T4.
At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus and also M /
IO’= 1, which indicates the memory operation is in progress.

In T2, the address is removed from the local bus and is sent to the addressed device. Then the
bus is tristated.

When RD’ = 0 , the valid data is present on the data bus.

During T2 DEN’ =0, which enables transceivers and DT/R’ = 0 ,which indicates that the data is
received.

During T3, data is put on the data bus and the processor reads it.

The output device makes the READY line high. This means the output device has performed the
data transfer process. When the processor makes the read signal to 1, then the output device
will again tristate its bus drivers.

At T1 state ALE =1 ,this indicates that a valid address is latched on the address bus and also M /
IO’= 1, which indicates the memory operation is in progress.
 In T2, the processor sends the data to be written to the addressed location.

The data is buffered on the bus until the middle of T4 state.

The WR’=0 becomes at the beginning of T2.

The BHE’ and A0 signals are used to select the byte or bytes of memory or I/O word.

During T2 DEN’ =0, which enables, transceivers and DT/R’ = 1 ,which indicates that the data is
transferred by the processor to the addressed device.

3 Classify the system bus timing of 8086 in minimum and maximum mode?

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX* pin to logic1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system. The
remaining components in the system are latches, transreceivers, clock generator, memory and
I/O devices.

The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in
two parts, the first is the timing diagram for read cycle and the second is the timing diagram for
write cycle.

Fig shows the read cycle timing diagram. The read cycle begins in T1 with the assertion of the
address latch enable (ALE) signal and also M/IO* signal. During the negative going edge of this
signal, the valid address is latched on the local bus. The BHE* and A0 signals address low, high or
both bytes. From Tl to T4, the M/IO* signal indicates a memory or I/O operation. At T2 the
address is removed from the local bus and is sent to the output. The bus is then tristated. The
read (RD*) control signal is also activated in T2 .The read (RD) signal causes the addressed
device to enable its data bus drivers. After RD* goes low, the valid data is available on the data
bus. The addressed device will drive the READY line high, when the processor returns the read
signal to high level, the addressed device will again tristate its bus drivers.
 A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO*
signal is again asserted to indicate a memory or I/O operation. In T2 after sending the address in
Tl the processor sends the data to be written to the addressed location. The data remains on the
bus until middle of T4 state. The WR* becomes active at the beginning ofT2 (unlike RD* is
somewhat delayed in T2 to provide time for floating). The BHE* and A0 signals are used to select
the proper byte or bytes of memory or I/O word to be read or written. The M/IO*, RD* and WR*
signals indicate the types of data transfer

4 Describe the maximum mode configuration of 8086 by with a neat diagram. Mention the functions of

various signals

In this we can connect more processors to 8086 (8087/8089).

8086 max mode is basically for implementation of allocation of global resources and passing bus
control to other coprocessor(i.e. second processor in the system), because two processors can
not access system bus at same instant.

All processors execute their own program.

The resources which are common to all processors are known as global resources.

The resources which are allocated to a particular processor are known as local or private
resources.
Circuit explanation:

When MN/ MX’ = 0 , 8086 works in max mode.

Clock is provided by 8284 clock generator.

8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three such
latches are required because address bus is 20 bit. The ALE(Address latch enable) is connected
to STB(Strobe) of the latch. The ALE for latch is given by 8288 bus controller.

The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
because data bus is 16-bit. The transceivers are enabled the DEN signal, while the direction of
data is controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected to T. Both
DEN and DT/ R’ are given by 8288 bus controller.

Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288 bus
controller.

Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0/GT0 has more priority than
RQ1/GT1.

INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.

 In max mode, the advanced write signals get enabled one T-state in advance as compared to
normal write signals. This gives slower devices more time to get ready to accept the data,
therefore it reduces the number of cycles.

5 Write the operations of I/O programming in detail.

Input-output (I/O) systems transfer information between computer main memory and the
outside world. An I/O system is composed of I/O devices (peripherals), I/O control units, and
software to carry out the I/O transaction(s) through a sequence of I/O operations. I/O devices
can be classified as serial, i.e. able to transfer bit streams one bit at a time, or parallel. Parallel
devices have a wider data bus and can therefore transfer data in words of one or more bytes.
Like any other activity in a computer system, I/O is a concerted work of both hardware and
software. The software which is executed to carry out an I/O transaction for a specific I/O device
is called a device driver. An example of such an I/O transaction is reading a block of data from
disk to memory. The software to do this is simply a sequence of I/O operations (instructions) to
transfer data between the peripheral devices and main memory (q.v.), and to enable the central
processing unit (CPU) to control the peripheral devices connected to it. Thus, I/O operations are
of two classes: control operations and data transfer operations.

1 State the advantage and disadvantage of parallel communication over serial communication.

Serial transmission requires a single line to send data. Parallel transmission requires multiple
lines to send data.

There are fewer errors and less noise in serial transmission, since the transmission is done one
bit at a time. There are more errors and noise in parallel transmission, since the transmission is
done multiple bits at a time.

Serial transmission is slower since data flows through a single line; conversely, parallel
transmission is faster since data flows through multiple lines.

Serial transmission is ‘full duplex’ since the sender can send and receive data at the same time.
Parallel transmission is ‘half duplex’ since the data can be sent or received at any given time.

The cables used in serial transmission are thinner, longer, and more economical compared to
the cables used in parallel transmission.

Serial transmission is reliable and straightforward. Parallel transmission is unreliable and

complicated.

Both serial and parallel transmissions have advantages and disadvantages. Parallel transmission
is used for shorter distances and provides greater speed, while serial transmission is reliable for
transferring data over longer distances. Both serial and parallel transmissions are individually
essential for transferring data.
2 Define the terms A/D & D/A convertor.

An A/D converter is a device that converts analog signals (usually voltage) obtained from
environmental (physical) phenomena into digital format. Conversion involves a series of steps,
including sampling, quantization, and coding.

In electronics, a digital-to-analog converter (DAC, D/A, D2A, or D-to-A) is a system that converts
a digital signal into an analog signal. An analog-to-digital converter (ADC) performs the reverse
function.

3 List the four display modes of 8279 keyboard and display controller

4 Name the applications of programmable interval timer.

Applications –

To generate an accurate time delay.

As an event counter.

Square wave generator.

Rate generator.

Digital one shot.

5 Outline the different peripheral interfacing used with 8086.

Memory device-RAM and ROM.

Input and Output devices.

8255- Programmable Peripheral Device.

DAC-Digital to Analog Converter.

ADC-Analog to Digital Converter.

8257-DMA Controller.

8259- Interrupt Controller.

6 Write the various modes of 8254 timer.

Operating Modes of 8254:

Mode 0 (Interrupt on Terminal Count) – Mode 0 is typically used for event counting. After the
Control Word is written, OUT is initially low, and will remain low until the counter reaches zero it
is decremented by 1 after every clock cycle. OUT then goes high and remains high until a new
count or a new Mode 0 Control Word is written into the counter. GATE = 1 enables counting,
GATE = 0 disables counting.

Mode 1 (Hardware Retriggreable One Shot) – OUT will be initially high. OUT will go low on the
CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the counter
reaches zero.

Mode 2 (Rate Generator) – Initially value of OUT is low. When counting is enabled, it becomes
high and this process repeats periodically. Value of count = Input Frequency / Output Frequency.
This mode works as a frequency divider.

Mode 3 (Square Wave Generator) – Counting is enabled when GATE = 1 and disabled when
GATE = 0. This mode is used to generate square waveform and time period (equal to count) is
generated.

If N is count and is even then ontime of wave = N/2 and offtime = N/2

If N is odd the ontime = (N + 1) / 2 and offtime = (N – 1) / 2

Mode 4 (Software Triggered Strobe) – In this mode counting is enabled by using GATE = 1 and
disabled by GATE = 0. Initially value of OUT is high and becomes low when value of count is at
last stage. Count is reloaded again for subsequent clock pulse.

Mode 5 (Hardware Triggered Strobe) – OUT will initially be high. Counting is triggered by a rising
edge of GATE. When the initial count has expired, OUT will go low for one clock pulse and then
go high again. After writing the Control Word and initial count, the counter will not be loaded
until the clock pulse after a trigger.

7 Classify the output modes used in 8279.

Output Mode

This mode is further classified into two output modes. Display Scan − This mode allows 8/16
character multiplexed displays to be organized as dual 4-bit/single 8-bit display units. Display
Entry − This mode allows the data to be entered for display either from the right side/left side.

8 What frequency transmit clock (TxC) is required by an 8251 in order for it to transmit data at 4800

Baud with a Baud rate factor of 16?

 Baud rate factor = (TXC) / (Desired Baud Rate) (TXC)= Baud rate factor X Desired Baud Rate = 16
X 4800= 76,800 Hz

9 Summarize the modes used by the DMA processor to transfer data.

Mode-1 :

Burst Mode –

In this mode Burst of data (entire data or burst of block containing data) is transferred before
CPU takes control of the buses back from DMAC.

Mode-2 :

Cycle Stealing Mode –

Slow IO device will take some time to prepare data (or word) and within that time CPU keeps
the control of the buses.

Mode-3 :

Interleaving Mode –

Whenever CPU does not require the system buses then only control of buses will be given to
DMAC.

10 What is meant by key bouncing?

Mechanical switches are used as keys in most of the keyboards. When a key is pressed the
contact bounce back and forth and settle down only after a small time delay (about 20ms). Even
though a key is actuated once, it will appear to have been actuated several times. This problem
is called Key Bouncing.

1 Explain the Functional diagram of Programmable Interrupt Controller in detail.

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade
Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.

Data bus buffer –

This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a
buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it to the
control logic of 8259 microprocessor. Also, after selection of Interrupt by 8259 microprocessor,
it transfer the opcode of the selected Interrupt and address of the Interrupt service sub routine
to the other connected microprocessor. The data bus buffer consists of 8 bits represented as
D0-D7 in the block diagram. Thus, shows that a maximum of 8 bits data can be transferred at a
time.

Read/Write logic –

This block works only when the value of pin CS is low (as this pin is active low). This block is
responsible for the flow of data depending upon the inputs of RD and WR. These two pins are
active low pins used for read and write operations.

Control logic –

It is the centre of the microprocessor and controls the functioning of every block. It has pin INTR
which is connected with other microprocessor for taking interrupt request and pin INT for giving
the output. If 8259 is enabled, and the other microprocessor Interrupt flag is high then this
causes the value of the output INT pin high and in this way 8259 responds to the request made
by other microprocessor.

Interrupt request register (IRR) –

It stores all the interrupt level which are requesting for Interrupt services.

Interrupt service register (ISR) –

It stores the interrupt level which are currently being executed.

Interrupt mask register (IMR) –

It stores the interrupt level which have to be masked by storing the masking bits of the interrupt
level.

Priority resolver –

It examines all the three registers and set the priority of interrupts and according to the priority
of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the interrupt
level which is already been serviced in IRR.

Cascade buffer –
 To increase the Interrupt handling capability, we can further cascade more number of pins by
using cascade buffer. So, during increment of interrupt capability, CSA lines are used to control
multiple interrupt structure. SP/EN (Slave program/Enable buffer) pin is when set to high, works
in master mode else in slave mode. In Non Buffered mode, SP/EN pin is used to specify whether
8259 work as master or slave and in Buffered mode, SP/EN pin is used as an output to enable
data bus.

2 Elaborate the 8255 programmable peripheral interface and its operating modes.

PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard etc. We can program it according to the given
condition. It can be used with almost any microprocessor.

It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We can assign
different ports as input or output functions.

Operating modes –

Bit set reset (BSR) mode –

If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are used
for set or reset.

Input-Output mode –

If MSB of control word (D7) is 1, PPI works in input-output mode. This is further divided into
three modes:

Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input function or
simple output function. In this mode there is no interrupt handling capacity.
 Mode 1 – Handshake I/O mode or strobed I/O mode. In this mode either port A or port B can
work as simple input port or simple output port, and port C bits are used for handshake signals
before actual data transmission. It has interrupt handling capacity and input and output are
latched.

Example: A CPU wants to transfer data to a printer. In this case since speed of processor is very
fast as compared to relatively slow printer, so before actual data transfer it will send handshake
signals to the printer for synchronization of the speed of the CPU and the peripherals.

Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can work
either in mode 0 or mode 1. 6 bits port C are used as handshake signals. It also has interrupt
handling capacity.

4 With neat diagram, outline the internal structure of key board and display controller.

Let us understand the operation of this architecture by considering its 4 separate sections.

1. Keyboard Section: This section is composed of Return Buffer and Keyboard Debounce and
Control. It holds the 8 return lines denoted by RL0 to RL7 that forms the column of the keyboard
matrix. Shift and Control/Strobe are the two additional inputs provided to this unit.

The two operating modes are 2-key lockout and N-key rollover. In the 2-key lockout mode of
operation, if two keys are pressed at the same time then the first recognized key will be
considered by the system. While N-key rollover mode, whenever it is found that two keys are
pressed at the same time then key codes of both of them get stored with the FIFO and are
further serviced.

It has 8*8 FIFO RAM that works on the First–In–First–Out approach and can store 8 keycodes
(code of pressed key) at a time in a sequential manner. The status of two additional input keys
i.e., shift and control are also stored within FIFO RAM.
 In scan keyboard mode, 8 keycodes are stored and anytime whenever an entry is made in the
FIFO RAM then 8279 generates an interrupt signal that tells the processor to perform FIFO read
operation till the time everything within FIFO is serviced. While in sensor matrix mode, the FIFO
RAM holds the condition of 64 switches within it regarding whether these are open or closed.
Whenever the condition of any switch is changed then 8279 generates an interrupt request for
the processor.

2. Display Section: This section is constituted by display address registers and display RAM. This
section contains 8 output lines i.e., A0-A3 and B0-B3 and these are connected to the 7-segment
LEDs. There is a 16*8 display RAM and the processor simply performs read and write operations
within this RAM.

3. Scan Section: The scan counter and four scan lines (SL0 to SL3) are part of this section. There
are two modes of scan counter namely, encode and decode. In encode mode, a binary count will
be obtained as the output of scan lines and this requires external decoding to give rise to
decoded output. These output scan lines are the same for the keyboard and display and 4 scan
lines can drive up to 16 displays.

4. CPU Interface Section: This section is composed of I/O control and Data Buffers along with
Timing and Control Registers. The timing and control unit is also a part of this unit. This section is
responsible for data transfer between 8279 and the CPU and hence consists of bidirectional data
lines DB0 to DB7.

There are two internal addresses whose specified value i.e., either 0 or 1 makes the selection for
either data buffer or control register. Here we have pins A0, CS, RD, and WR that are used for
command, status, read and write operations. The IRQ is an interrupt request line that is
specified for data transfer that is associated with generated interrupt requests.

It operates on an internal clock frequency of 100 kHz. The RESET signal provided to the 8279 is
responsible for setting its 16-character display. The control and timing register holds the modes
and operating conditions which program the CPU.

5 Explain memory interfacing and I/O interfacing in detail?

Memory and I/O Interfacing

Several memory chips and I/O devices are connected to a microprocessor.

The following figure shows a schematic diagram to interface memory chips and I/O devices to a
microprocessor.
 Memory Interfacing

When we are executing any instruction, the address of memory location or an I/O device is sent
out by the microprocessor. The corresponding memory chip or I/O device is selected by a
decoding circuit.

Memory requires some signals to read from and write to registers and microprocessor transmits
some signals for reading or writing data.

The interfacing process includes matching the memory requirements with the microprocessor
signals. Therefore, the interfacing circuit should be designed in such a way that it matches the
memory signal requirements with the microprocessor's signals.

I/O interfacing

As we know, keyboard and displays are used as communication channel with outside world.
Therefore, it is necessary that we interface keyboard and displays with the microprocessor. This
is called I/O interfacing. For this type of interfacing, we use latches and buffers for interfacing
the keyboards and displays with the microprocessor.

But the main drawback of this interfacing is that the microprocessor can perform only one
function.

9 Describe the internal architectural diagram of the 8237 and explain how it functions as a DMA

controller.
 Intel 8237 is a direct memory access (DMA) controller, a part of the MCS 85 microprocessor
family. It enables data transfer between memory and the I/O with reduced load on the system's
main processor by providing the memory with control signals and memory address information
during the DMA transfer.

The 8237 is a four-channel device that can be expanded to include any number of DMA channel
inputs. The 8237 is capable of DMA transfers at rates of up to 1.6 megabyte per second. Each
channel is capable of addressing a full 64k-byte section of memory and can transfer up to 64k
bytes with a single programming.

A single 8237 was used as the DMA controller in the original IBM PC and IBM XT. The IBM PC AT
added another 8237 in master-slave configuration, increasing the number of DMA channels
from four to seven.Later IBM-compatible personal computers may have chip sets that emulate
the functions of the 8237 for backward compatibility. The Intel 8237 was actually designed by
AMD (called Am9517). It was part of a cross licensing agreement, allowing AMD to manufacture
Intel processors, that made the design available for Intel as well. This is why the Intel package
has "(C) AMD 1980" printed on it.

1 Write the size of memory systems used in 8051 microcontroller?

While, internal data RAM is 128 bytes in size; it can have external memory upto 64K in size.
Thus, total Data Memory available on 8051 Microcontroller is 64K + 128 bytes in size.

2 Identify the different operand types used in 8051

In 8051 There are six types of addressing modes.

Immediate AddressingMode.

Register AddressingMode.

Direct AddressingMode.

Register IndirectAddressing Mode.

 Indexed AddressingMode.

Implied AddressingMode.

3 List the counters available in 8051

The 8051 has two counters/timers which can be used either as timer to generate a time delay or
as counter to count events happening outside the microcontroller. The 8051 has two timers:
timer0 and timer1. They can be used either as timers or as counters. Both timers are 16 bits
wide.

4 Label the register bank of 8051.

The 8051 microcontroller consists of four register banks, such as Bank0, Bank1, Bank2, Bank3
which are selected by the PSW (Program Status Word) register. These register banks are present
in the internal RAM memory of the 8051 microcontroller, and are used to process the data
when the microcontroller is programmed.

5 Name the number of ports are bit addressable in 8051.

8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or
output. Hence, total 32 input/output pins allow the microcontroller to be connected with the
peripheral devices.

6 Describe hardware and software interrupts in 8051. Mention Its vector addresses.

8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled or
disabled by setting bits of the IE register and the whole interrupt system can be disabled by
clearing the EA bit of the same register.

7 Outline the words the power down mode of 8051.

In Power Down mode, the oscillator clock provided to the system is OFF i.e. CPU and peripherals
clock remains inactive in this mode. In Idle Mode, only the clock provided to the CPU gets
deactivated, whereas the peripherals clock will remain active in this mode.

8 Classify operand addressing mode in 8051.

 There are 5 different ways to execute this instruction and hence we say, we have got 5
addressing modes for 8051. They are 1) Immediate addressing mode 2) Direct addressing mode
3) Register direct addressing mode 4) Register indirect addressing mode 5) Indexed addressing
mode.

9 Summarize the place a specific value in the DPTRregister.

DPTR is meant for pointing to data. It is used by the 8051 to access external memory using the
address indicated by DPTR. DPTR is the only 16-bit register available and is often used to store 2-
byte values.

10 What is meant by PSW in 8051?

The Program Status Word (PSW) contains status bits that reflect the current CPU state. The 8051
variants provide one special function register called PSW with this status information.

1 Pointout the various instruction sets of 8051 microcontroller and describe any two in detail.

In 8051 Microcontroller there are 24 different instructions under the Arithmetic Group. In total
there are 64 opcodes. The Carry Flag (CY), Auxiliary Carry (AC)and Overflow flag (OV) are
affected based on the result of ADD, ADDC, SUBB etc. instructions. The multiple and divide
instructions clear the Carry flag, and also does not affect the AC flag. After execution of
multiplication, the OV flag will be 1 when the result is greater than FFH. Otherwise, it is 0.
Similarly, after division OV flag is 1 when the content of B is 00H before division, otherwise it is
0. The DA A (Decimal Adjust Accumulator) affects the Carry Flag only.

In the following table, we will see the Mnemonics, Lengths, Execution Time in terms of the
machine cycle, Number of Opcodes etc.

ADD A, 32H

This is an instruction of type ADD A, #d8. The immediate data 32H is added to register A. The
result is also stored in A.

2 ADDC A, @R1
This is an instruction of type ADDC A, @Ri. It means the content on internal RAM location which
is pointed by register R1 is added to A.

3 SUBB A, R5

This is SUBB A, Rn type instruction. The SUBBstands for Subtract with borrow. So the content of
R5 will be subtracted from A.

4 INC 40H

This is a type of INC a8. Here the content in local RAM whose address is 40H, it is increased by 1.

5 INC DPTR

It can increase the content of DPTR by 1. This instruction takes two machine cycle to execute.

6 MUL AB

This instruction is used to multiply the content of register A and B. The 16-bit address will be
stored at B and A registers. The B will hold the MS byte, and A will hold the LSByte.

7 DIV AB

This instruction is used to divide the content of A register by B register. The 8-bit quotient is
stored into the register A, and the 8-bit remainder is stored into the register B.

Logical operations in 8051 perform bitwise operations between the accumulator and data
stored in a memory location, register, or data given by the programmer. The result of a logical
operation is stored in the accumulator itself. The table given below lists the logical operations
which can be performed by the 8051. [A]=Accumulator; [Rn]= register in register bank of RAM
space.

AND operation

The AND instructions compare the bits in the source and the destination operand and then store
the result in the accumulator after performing the AND operation.

OR Operation

The OR instructions compare the bits in the source and the destination operand and then store
the result in the accumulator after performing the OR operation.

XOR Operation

These instructions compare the bits in the source and the destination operand and then store
the result in the accumulator after performing the XOR operation.

Clear operation
 The CLR instruction is used to clear the data stored in the accumulator.

Compliment operation

The CPL instruction inverts all the bits stored in the accumulator.

Swap operation

Swaps the data in the upper nibble with the lower nibble of the accumulator.

Rotate right operation

The RR instruction shifts the data stored in the accumulator to the right in a bit by bit fashion.
The data in the LSB is shifted to the MSB.

Rotate right with carry operation

The RRC command performs the same operation but includes the carry bit in the operation as
well. It is used for serial transmission of data to any external port.

Rotate left operation

The RL instruction shifts the data stored in the accumulator to the left in a bit by bit fashion. The
data in the MSB is shifted to the LSB.

Rotate left with carry operation

The RLC command performs the same operation but includes the carry bit in the operation as
well. It is used for serial transmission of data to any external port.

2 Write an ALP using 8051 instructions to receive bytes of data serially and put them in P1. Set the baud

rate at 4800, 8-bit data, and 1 stop bit.

3 (i) Give PSW of 8051 and describe the uses of each bit.

(ii) Summarize the functions of the following signals in 8051: RST, EA, PSEN and ALE.
The Program Status Word (PSW) contains status bits that reflect the current CPU state. The 8051
variants provide one special function register called PSW with this status information. The 251
provides two additional status flags, Z and N, that are available in a second special function
register called PSW1.

RST

(ii) Pin 9 is the RESET pin. It is an input and is active high (normally low). Upon applying a high
pulse to this pin, the microcontroller will reset and terminate all activities. This is often referred
to as a power-on reset. Activating a power-on reset will cause all values in the registers to be
lost. It will set program counter to all Os.

EA

The 8051 family members, such as the 8751/52, 89C51/52, or DS89C4xO, all come with on-chip
ROM to store programs. In such cases, the EA pin is connected to Vcc. For family members such
as the 8031 and 8032 in which there is no on-chip ROM. code is stored on an external ROM and
 is fetched by the 8031/32. Therefore, for the 8031 the EA pin must be connected to GND to
indicate that the code is stored externally. EA. which stands for “external access,” is pin number
31 in the DIP packages. It is an input pin and must be connected to either Vcc or GND. In other
words, it cannot be left unconnected.

PSEN

This is an output pin. PSEN stands for “program store enable.” In an 8031-based system in which
an external ROM holds the program code, this pin is connected to the OE pin of the ROM.

ALE

ALE (address latch enable) is an output pin and is active high. When connecting an 8031 to
external memory, port 0 provides both address and data. In other words, the 8031 multiplexes
address and data through port 0 to save pins. The ALE pin is used for demultiplexing the address
and data by connecting to the G pin of the 74LS373 chip.

6 Outline the I/O ports of 8051 microcontroller in detail.

8051 microcontrollers have 4 I/O ports each of 8-bit, which can be configured as input or
output. Hence, total 32 input/output pins allow the microcontroller to be connected with the
peripheral devices.

Pin configuration, i.e. the pin can be configured as 1 for input and 0 for output as per the logic
state.

Input/Output (I/O) pin − All the circuits within the microcontroller must be connected to one of
its pins except P0 port because it does not have pull-up resistors built-in.

Input pin − Logic 1 is applied to a bit of the P register. The output FE transistor is turned off and
the other pin remains connected to the power supply voltage over a pull-up resistor of high
resistance.

Port 0 − The P0 (zero) port is characterized by two functions −

When the external memory is used then the lower address byte (addresses A0A7) is applied on
it, else all bits of this port are configured as input/output.

When P0 port is configured as an output then other ports consisting of pins with built-in pull-up
resistor connected by its end to 5V power supply, the pins of this port have this resistor left out.

Output Configuration

When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0 to a
port bit, the appropriate pin will be connected to ground (0V), and applying logic 1, the external
output will keep on “floating”.
 In order to apply logic 1 (5V) on this output pin, it is necessary to build an external pullup
resistor.

Port 1

P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this port can be
configured as general I/O only. It has a built-in pull-up resistor and is completely compatible
with TTL circuits.

Port 2

P2 is similar to P0 when the external memory is used. Pins of this port occupy addresses
intended for the external memory chip. This port can be used for higher address byte with
addresses A8-A15. When no memory is added then this port can be used as a general
input/output port similar to Port 1.

Port 3

In this port, functions are similar to other ports except that the logic 1 must be applied to
appropriate bit of the P3 register.

8 Recognize the different addressing modes in 8051 microcontroller with an example.

In 8051 There are six types of addressing modes.

Immediate AddressingMode

Register AddressingMode

Direct AddressingMode

Register IndirectAddressing Mode

Indexed AddressingMode

Implied AddressingMode

Immediate addressing mode

In this Immediate Addressing Mode, the data is provided in the instruction itself. The data is
provided immediately after the opcode. These are some examples of Immediate Addressing
Mode.

MOVA, #0AFH;

MOVR3, #45H;
MOVDPTR, #FE00H;

In these instructions, the # symbol is used for immediate data. In the last instruction, there is
DPTR. The DPTR stands for Data Pointer. Using this, it points the external data memory location.
In the first instruction, the immediate data is AFH, but one 0 is added at the beginning. So when
the data is starting with A to F, the data should be preceded by 0.

Register addressing mode

In the register addressing mode the source or destination data should be present in a register
(R0 to R7). These are some examples of RegisterAddressing Mode.

MOVA, R5;

MOVR2, #45H;

MOVR0, A;

In 8051, there is no instruction like MOVR5, R7. But we can get the same result by using this
instruction MOV R5, 07H, or by using MOV 05H, R7. But this two instruction will work when the
selected register bank is RB0. To use another register bank and to get the same effect, we have
to add the starting address of that register bank with the register number. For an example, if the
RB2 is selected, and we want to access R5, then the address will be (10H + 05H = 15H), so the
instruction will look like this MOV 15H, R7. Here 10H is the starting address of Register Bank 2.

Direct Addressing Mode

In the Direct Addressing Mode, the source or destination address is specified by using 8-bit data
in the instruction. Only the internal data memory can be used in this mode. Here some of the
examples of direct Addressing Mode.

MOV80H, R6;

MOVR2, 45H;

MOVR0, 05H;

The first instruction will send the content of registerR6 to port P0 (Address of Port 0 is 80H). The
second one is forgetting content from 45H to R2. The third one is used to get data from Register
R5 (When register bank RB0 is selected) to register R5.

Register indirect addressing Mode

In this mode, the source or destination address is given in the register. By using register indirect
addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used
for 8-bit addresses, and DPTR is used for 16-bit addresses, no other registers can be used for
addressing purposes. Let us see some examples of this mode.
MOV0E5H, @R0;

MOV@R1, 80H

In the instructions, the @ symbol is used for register indirect addressing. In the first instruction,
it is showing that theR0 register is used. If the content of R0 is 40H, then that instruction will
take the data which is located at location 40H of the internal RAM. In the second one, if the
content of R1 is 30H, then it indicates that the content of port P0 will be stored at location 30H
in the internal RAM.

MOVXA, @R1;

MOV@DPTR, A;

In these two instructions, the X in MOVX indicates the external data memory. The external data
memory can only be accessed in register indirect mode. In the first instruction if the R0 is
holding 40H, then A will get the content of external RAM location40H. And in the second one,
the content of A is overwritten in the location pointed by DPTR.

Indexed addressing mode

In the indexed addressing mode, the source memory can only be accessed from program
memory only. The destination operand is always the register A. These are some examples of
Indexed addressing mode.

MOVCA, @A+PC;

MOVCA, @A+DPTR;

The C in MOVC instruction refers to code byte. For the first instruction, let us consider A holds
30H. And the PC value is1125H. The contents of program memory location 1155H (30H + 1125H)
are moved to register A.

Implied Addressing Mode

In the implied addressing mode, there will be a single operand. These types of instruction can
work on specific registers only. These types of instructions are also known as register specific
instruction. Here are some examples of Implied Addressing Mode.

RLA;

SWAPA;

These are 1- byte instruction. The first one is used to rotate the A register content to the Left.
The second one is used to swap the nibbles in A.
1 What are the types of sensors used for interfacing?

there are a lot of different ways of interfacing with sensors. They can be grouped into three
different categories: direct digital, direct analog, and protocol-based communications. With
direct digital and direct analog, the MCU will be reading the sensor value directly.

2 Mention the advantages of microprocessor based systemdesign?

The microprocessor is that these are general purpose electronics processing devices which can
be programmed to execute a number of tasks

Compact size

High speed

Low power consumption

It is portable

It is very reliable

Less heat generation

The microprocessor is very versatile

The microprocessor is its speed, which is measured in basically Hertz. For instance, a
microprocessor with a measured speed 3 GHz, shortly GHz is capable of performing 3 billion
tasks per second

The microprocessor is that it can quickly move data between the various memory location

3 List out the classifications of stepper motor.

There are three main types of stepper motors:

Permanent Magnet Stepper. PM steppers have rotors that are constructed with permanent
magnets, which interact with the electromagnets of the stator to create rotation and torque.
PM steppers usually have comparatively low power requirements and can produce more torque
per unit of input power.

Variable Reluctance Stepper. VR stepper rotors are not built with permanent magnets. Rather,
they are constructed with plain iron and resemble a gear, with protrusions or “teeth” around
the circumference of the rotor. The teeth lead to VR steppers that have a very high degree of
angular resolution; however, this accuracy usually comes at the expense of torque.

Hybrid Syncronous Stepper. HS stepper rotors use the best features of both PM and VR
steppers. The rotor in an HS motor has a permanent magnet core, while the circumference is
 built from plain iron and has teeth. A hybrid synchronous motor, therefore, has both high
angular resolution and high torque.

4 How to change the stepper motor direction?

To change direction you need to reverse the current in one set of coils only. At the moment the
two motors are connected in parallel and turn in the same direction. Swap ONE of the coil pairs
over and you should be able to get the two motors turn in the opposite direction with the same
drive signal.

5 Identify the features of serial port in Mode-0.

Mode 0 is a synchronous communication system. Through the RxD pin is transmit data, while
the sync pulses are located at TxD. For this mode, the transmission speed is fixed to the
oscillator frequency ÷ 12. This communication system is typically used to expand the number of
points of entry and exit by shift registers.

6. Show the difference in microprocessor and microcontroller.

7 State in your own words how is stepper motor interfaced with 8051?
 Interfacing Stepper Motor with 8051 Microcontroller

Each ULN2003 has seven NPN Darlington pairs. It can provide high voltage output with common
cathode clamp diodes for switching inductive loads. The Unipolar stepper motor works in three
modes. Wave Drive Mode − In this mode, one coil is energized at a time.

Full Drive Mode − In this mode, two coils are energized at the same time. This mode produces
more torque. Here the power consumption is also high.

Half Drive Mode − In this mode, one and two coils are energized alternately. At first, one coil is
energized then two coils are energized. This is basically a combination of wave and full drive
mode. It increases the angular rotation of the motor.

8 What is the main idea of PWM in motor controlusing microcontroller?

Pulse Width Modulation (PWM) technique was used to control the amount of power delivered
to the load (the DC motor) without dissipating any wasted power. The components and
assembly of this microcontroller circuit are highlighted in this paper, and the constructed circuit
tested.

9 Describe the special functions registers that controls the serial communication 0f 8051?

List of 8051 Microcontroller Special Function Registers

A or ACC

DPL

DPH

IE

IP

P0

P1

P2

P3

PCON

PSW
 SCON

SBUF

SP

TMOD

TCON

TL0

TH0

TL1

TH1

The 8051 Microcontroller Special Function Registers act as a control table that monitor and
control the operation of the 8051 Microcontroller. If you observe in Internal RAM Structure, the
Address Space from 80H to FFH is allocated to SFRs.

Out of these 128 Memory Locations (80H to FFH), there are only 21 locations that are actually
assigned to SFRs. Each SFR has one Byte Address and also a unique name which specifies its
purpose.

10 Summarize the interrupt service routine.

An ISR (also called an interrupt handler) is a software process invoked by an interrupt request
from a hardware device. It handles the request and sends it to the CPU, interrupting the active
process. When the ISR is complete, the process is resumed.

1 (i) Discuss about serial port interface of 8051.

(ii) Explain the various operating modes for serial port of 8051 microcontroller.
Microcontrollers need to communicate with external devices such as sensors, computers and so
on to collect data for processing. Data communication is generally done by means of two
methods – Parallel and Serial mode. In parallel mode data bits are transferred faster using more
data pins. But when comes to a Microcontroller, we cannot afford to dedicate many pins for
data transfer. UART or Serial communication in 8051 microcontroller will allow the controller to
send and receive data’s just by using two pins

Serial Communication uses only two data pins to establish communication between
Microcontroller and external devices. In this mode of communication data is transferred one bit
at a time. This article describes Interfacing of 8051 with PC to establish communication through
its serial port RS232.

RS232 AND MAX232:

To establish communication between a controller and PC, we must use serial I/O protocol RS-
232 which was widely used in PC and several devices. PC works on RS-232 standards which
operates at a logic level of -25V to +25V. But Microcontrollers use TTL logic which works on 0-5V
is not compatible with the RS-232 voltage levels.

MAX232 is a specialized IC which offers intermediate link between the Microcontroller and PC.
The transmitter of this IC will convert the TTL input level to RS-232 Voltage standards.
Meanwhile the receiver of this IC will convert RS-232 input to 5V TTL logic levels.

(ii). Mode 0: 8-Bit Shift Register Mode. Terms RXD & TXD are

misleading in this mode. RXD line is used for both input

and output. TXD line serves as the clock.

• Eight bits are transmitted and received with the LSB first.

Baud Rate is fixed at 1/12 of on-chip oscillator frequency.

• Transmission is initiated by any instruction that writes data

to SBUF. Data are shifted out on RXD line with clock

pulses sent out by the TXD line. Each transmitted bit is

valid on the RXD pin for one machine cycle.

E.g., MOV SBUF, A

• Reception is initiated when the REN is 1 and the RI is 0.

REN is set at the beginning of the program, and then clear

RI to begin a data input operation. The clocking of data

into serial port occurs on the positive edge of TXD.

Mode 1: Serial port operates as an 8-bit UART with a

variable baud rate.10-bits are transmitted on TXD or

received on RXD. Start bit (always 0), 8 data bits (LSB

first), and a stop bit (always 1). For a receive operation,

the stop bit goes into RB8 in SCON. Baud Rate Clock is

variable using Timer 1 overflow or external count input.

• Transmission is initiated by writing data to SBUF.

Shifted data are outputted on the TXD line beginning

with the start bit. The transmit interrupt flag (TI) is set

as soon as the stop bit appears on TXD.

• Reception is initiated by a 1-to-0 transition on RXD.

Mode 2: Serial port operates as a 9-bit UART with a

fixed baud rate. 11-bits are transmitted or received.

Start bit (always 0), 8 data bits (LSB first), a

 programmable 9th bit, and a stop bit (always 1).

• On transmission, the 9th bit whatever has been put in

TB8 in SCON (may be a parity bit).

• On reception, the 9th bit is placed in RB8 in SCON.

• Baud Rate is programmable to either 1/32 or 1/64 of

the on-chip oscillator frequency.

Mode 3: Serial port operates as a 9-bit UART

with a variable baud rate. 11-bits are transmitted

or received. Baud Rate is programmable and

provided by the Timer 1 overflow or external

input.

2 (i) Show how to interface an LCD display with µC.

(ii) Demonstrate a program to display a character using LCD display.

(i) Circuit diagram for LCD interfacing with 8051 microcontroller is shown in the above figure. If
you have basic understanding of 8051 then you must know about EA(PIN 31), XTAL1 & XTAL2,
RST pin(PIN 9), Vcc and Ground Pin of 8051 microcontroller. I have used these Pins in above
circuit. If you don’t have any idea about that then I recommend you to read this Article LED
Interfacing with 8051 Microcontroller before going through LCD interfacing.

So besides these above pins we have connected the data pins (D0-D7) of LCD to the Port 2 (P2_0
– P2_7) microcontroller. And control pins RS, RW and E to the pin 12,13,14 (pin 2,3,4 of port 3)
of microcontroller respectively.

PIN 2(VDD) and PIN 15(Backlight supply) of LCD are connected to voltage (5v), and PIN 1 (VSS)
and PIN 16(Backlight ground) are connected to ground.

Pin 3(V0) is connected to voltage (Vcc) through a variable resistor of 10k to adjust the contrast
of LCD. Middle leg of the variable resistor is connected to PIN 3 and other two legs are
connected to voltage supply and Ground

(ii). the program to display the "javaTpoint" on LCD display is:-

#include<reg51.h>

#define kam P0

void lcd_initi();

void lcd_dat(unsigned char );

void lcd_cmd(unsigned char );

void delay();

void display(unsigned char *s, unsigned char r)

sbit rs=P2^0;

sbit rw=P2^1;

sbit en=P2^2;

void main()

lcd_initi();

lcd_cmd(0x80);

delay(100);

lcd_cmd(0xc0);
display("javaTpoint",10);

while(1);

void display(unsigned char *s, unsigned char r)

unsignedint w;

for(w=0;w<r;w++)

lcd_data(s[w]);

voidlcd_initi()

lcd_cmd(0?01);

delay(100);

lcd_cmd(0?38);

delay(100);

lcd_cmd(0?06);

delay(100);

lcd_cmd(0x0c);

delay(100);

voidlcd_dat(unsigned char dat)

kam = dat;
 rs=1;

rw=0;

en=1;

delay(100);

en=0;

voidlcd_cmd(unsigned char cmd)

kam=cmd;

rs=0;

rw=0;

en=1;

delay(100);

en=0;

void delay( unsigned int n)

unsignedint a;

for(a=0;a<n;a++);

7. Describe the basic operation of a stepper motor and also discuss how to interface a stepper motor to

8051.

Stepper Motor

Stepper motors are used to translate electrical pulses into mechanical movements. In some disk
drives, dot matrix printers, and some other different places the stepper motors are used. The
 main advantage of using the stepper motor is the position control. Stepper motors generally
have a permanent magnet shaft (rotor), and it is surrounded by a stator. Normal motor shafts
can move freely but the stepper motor shafts move in fixed repeatable increments.

Interfacing Stepper Motor with 8051 Microcontroller

Weare using Port P0 of 8051 for connecting the stepper motor. HereULN2003 is used. This is
basically a high voltage, high current Darlington transistor array. Each ULN2003 has seven NPN
Darlington pairs. It can provide high voltage output with common cathode clamp diodes for
switching inductive loads.

The Unipolar stepper motor works in three modes.

Wave Drive Mode − In this mode, one coil is energized at a time. So all four coils are energized
one after another. This mode produces less torque than full step drive mode.

Full Drive Mode − In this mode, two coils are energized at the same time. This mode produces
more torque. Here the power consumption is also high

Half Drive Mode − In this mode, one and two coils are energized alternately. At first, one coil is
energized then two coils are energized. This is basically a combination of wave and full drive
mode. It increases the angular rotation of the motor

The circuit diagram is like below: We are using the full drive mode.

9. Discuss how a DAC is interfaced with 8051 µC.

The Digital to Analog converter (DAC) is a device, that is widely used for converting digital pulses
to analog signals.
The MC1408 DAC (or DAC0808)

In this chip the digital inputs are converted to current. The output current is known as Iout by
connecting a resistor to the output to convert into voltage. The total current provided by the
Iout pin is basically a function of the binary numbers at the input pins D0 - D7 (D0 is the LSB and
D7 is the MSB) of DAC0808 and the reference current Iref. The following formula is showing the
function of Iout

IOut=Iref⟮D7/2+D6/4+D5/8+D4/16+D3/32+D2/64+D1/128+D0/256⟯

The Iref is the input current. This must be provided into the pin 14. Generally 2.0mA is used as
Iref

We connect the Iout pin to the resistor to convert the current to voltage. But in real life it may
cause inaccuracy since the input resistance of the load will also affect the output voltage. So
practically Iref current input is isolated by connecting it to an Op-Amp with Rf = 5KΩ as feedback
resistor. The feedback resistor value can be changed as per requirement.

Generating Sinewave using DAC and 8051 Microcontroller

For generating sinewave, at first we need a look-up table to represent the magnitude of the sine
value of angles between 0° to 360°. The sine function varies from -1 to +1. In the table only
integer values are applicable for DAC input. In this example we will consider 30° increments and
calculate the values from degree to DAC input. We are assuming full-scale voltage of 10V for
DAC output. We can follow this formula to get the voltage ranges.

Vout = 5V + (5 ×sinθ)
10. With diagram, describe the operation of R-2R method of D/A converter

To overcome huge range of resistor used in weighted resistor D/A converter, R-2R ladder D/A
converter is introduced. In my previous post I discussed about weighted resistor D/A converter.
Now question is why we use R-2R ladder D/A converter?

As we know the vital problem in weighted register D/A converter is use of huge range of
different resistance. Suppose we have to design 8-bit weighted register D/A converter then we
need the resistance value 20R+21R+….+27R. So the largest resistor corresponding to bit b8 is
128 times the value of the smallest resistor correspond to b1. But in case of R-2R ladder D/A
converter, Resistors of only two value (R and 2R) are used. Now in bellow see the simple ladder
network.

In ladder circuit the output voltage is also weighted sum of the corresponding digital input. Let
take an example to understand how it works? As we can see the above network is a 4-bit ladder
network so we take an example to convert analog signal correspond of 1000 digital bit. For 1000
bit we can see only MSB got 1 and rest all bits got 0. See the bellow picture to understand how it
work if it got 1000.

Firstly, at node1 (N1) resistor 2R connecting in b4 parallel with resistor 2R. And those 2R parallel
2R resistors make equivalent register of R shown in bellow diagram.
Secondly, for N2 same thing happen B3 series with 2R and parallel with R + R resistors. It will
also make equivalent resistor R at N3.

Thirdly, repeating the same process we got equivalent of R resistor at N4.

Fourthly, at N4, if we calculate the output analog equivalent voltage then we will get

VA = VR*2R/(R+R+2R)

= VR/2

Thus when bit 1000 the output is VR/2. Similarly it can be found that using above process for bit
0100 the output will be VR/4, for bit 0010 output will be VR/8 and for bit 0001 output will be
VR/16.

By using superposition theorem we can find in any n-bit ladder network the output voltage will
be

VA = VR/21 + VR/22 + VR/23 + ……. + VR/2n

Where n is the total number of bits at the input.

Finally, the practical circuit arrangement of 4-bit R-2R ladder D/A converter using op amp.
The inverting input terminal of the op amp work as a summing amplifier for the ladder inputs.
So we can get out put voltage by bellow equation.

V0 = VR*(RF/R)[b1/21 + b2/22 + b3/23 + b4/24]