Module IV

1.6 Introduction to Stack

The stack in the 8086/8088 microprocessor, like that in many microprocessors, is

a region of memory that can store information for later retrieval. It is called a stack,
because you "stack" things on it. The philosophy is that you retrieve (pop) things in the
opposite order of storing (push) them.
In the 8086/8088, the stack pointer is SS:SP, which is a 16 bit pointer into a 20
bit address space. It, at any point of time, points to the last item pushed on the stack. If
the stack is empty, it points to the highest address of the stack plus one.
In a push operation, the SP register is decremented by two, and the data to be
pushed is stored at that address, low order byte first. In a pop operation, the data to be
popped is retrieved from that address, again low order byte first, and then the SP
register is incremented by two.
Some instructions, such as a FAR CALL, or FAR RETURN push or pop more
than two bytes on the stack.
It is also possible to allocate temporary storage on the stack. You simply
decrement the SP register by some amount, use that memory, and then increment the
SP register to release the memory. This is known as a stack frame. In fact, the BP
register makes is very easy to do so. You use BP to separate arguments from local data
- arguments will be above BP, and local
data will be below BP. Memory reference instructions that are relative to BP, i.e.
[BP+6] or [BP-48] will automatically use the SS segment register.

1.6.1 Stack Structure of 8086

The stack contains a set of sequentially arranged data bytes, with the last item
appearing on the top of the stack. This item will be popped off the stack first for use by
the CPU. The stack pointer (SP) register is a 16-bit register that contains the offset of
the address that lies in the stack segment. The stack segment, like any other segment,
may have a memory block of a maximum of 64Kbyte locations, and thus may overlap
with any other segments. The stack Segment register (SS) and Stack Pointer register
(SP) together address the stack-top.
Let the content of SS be 5000 H and the content of the stack pointer register be
2050 H. To find out the current stack-top address, the stack segment register content is
shifted left by four bit positions (multiplied by 10 H) and the resulting 20-bit content is
added with the 16-bit offset value, stored in the stack pointer register. In the above
case, the stack top address can be calculated as shown in the Fig.5.11.

Fig.5.11 Stack-top Address Calculation

If the stack top points to a memory location 52050 H, it means that the location
52050 H is already occupied, i.e. previously pushed data is available at 52050 H. The
next 16-bit push operation will decrement the stack pointer by two, so that it will point to
the new stack-top 5204EH, and the decremented contents of SP will be 204E H. this
location will now be occupied by the recently pushed data. Thus, if a 16-bit data is
pushed onto the stack, the push operation will decrement the SP by two because two
locations will be required for a 2-byte (16- bit) data. Hus it may be noted here that the
stack grows down.
Thus for a selected value of SS, the maximum value of SP = FFFF H and the
segment can have maximum of 64K locations. Thus after starting with an initial value of
FFFFH, the Stack Pointer (SP) is decremented by two, whenever a 16-bit data is
pushed onto the stack. After successive push operations, when the Stack Pointer
contains 0000 H, any attempt to further push the data to the stack will result in stack
overflow.

Each PUSH operation decrements the SP as explained above, while each POP
operation increments the SP. The POP operation is used to retrieve the data stored on
to the stack. Fig.5.12 shows the stack overflow conditions, while Fig.5.13 shows the
effect of PUSH and POP operations on the stack memory block.

Fig.5.12 The execution of bracketed PUSH AX Instruction Results in Stack

Overflow
 Fig5.13 Effect of PUSH and POP on SP

1.7 Interrupts and Interrupts Service Routine

Interrupt ‘ means to break the operation. While the CPU is executing a

programme, an―interrupt‖ breaks the normal sequence of execution of instructions,
diverts its execution to some other programme called Interrupt Service Routine (ISR).
After executing ISR, the control is transferred back again to the main programme which
was being executed at the time of interruption. Some of the interrupts are Maskable and
Non maskable Interrupts.

Fig.4.6 ISR
 Whenever a number of devices interrupt a CPU at a time, and if the processor is
able to handle them properly, it is said to have multiple interrupt processing capability.
For example, 8085 has five hardware interrupt pins and it is able to handle the
interrupts simultaneously under the control of software. In case of 8086, there are two
interrupt pins, viz. NMI and INTR. The NMI is a nonmaskable interrupt input pin which
means that any interrupt request at NMI input cannot be masked or disabled by any
means. The INTR interrupt, however, may be masked using the Interrupt Flag (IF). The
INTR, further, is of 256 types. The INTR types may be from 00 to FFH (or 00 to 255).

The following image shows the types of interrupts we have in a 8086

microprocessor −

Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal
through a specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-
maskable interrupt and INTR is a maskable interrupt having lower priority.
One more interrupt pin associated is INTA called interrupt acknowledge.

NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the
maskable interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value
of the return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.

INTR
The INTR is a maskable interrupt because the microprocessor will be
interrupted only if interrupts are enabled using set interrupt flag instruction. It
should not be enabled using clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and
NMI is disabled, then the microprocessor first completes the current
execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs
the external device to get ready and during the second ‘0’ the microprocessor
receives the 8 bit, say X, from the programmable interrupt controller.
These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the
return address are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts
Some instructions are inserted at the desired position into the program to
create interrupts. These interrupt instructions can be used to test the working
of various interrupt handlers. It includes −

INT- Interrupt instruction with type number

It is 2-byte instruction. First byte provides the op-code and the second byte
provides the interrupt type number. There are 256 interrupt types under this
group.
Its execution includes the following steps −
 Flag register value is pushed on to the stack.
 CS value of the return address and IP value of the return address are
pushed on to the stack.
 IP is loaded from the contents of the word location ‘type number’ × 4
 CS is loaded from the contents of the next word location.
 Interrupt Flag and Trap Flag are reset to 0
The starting address for type0 interrupt is 000000H, for type1 interrupt is
00004H similarly for type2 is 00008H and ……so on. The first five pointers
are dedicated interrupt pointers. i.e. −
 TYPE 0 interrupt represents division by zero situation.
 TYPE 1 interrupt represents single-step execution during the debugging
of a program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors, and interrupts from 32 to Type 255 are available for
hardware and software interrupts.

1.8 Interrupt Cycle of 8086/8088

Broadly, there are two types of interrupts. The first out of them is external
interrupt and the second is internal interrupt. In external interrupt, an external device or
a signal interrupts the processor from outside or, in other words, the interrupt is
generated outside the processor, for example, a keyboard interrupt. The internal
interrupt, on the other hand, is generated internally by the processor circuit, or by the
execution of an interrupt instruction. The examples of this type are divide by zero
interrupt, overflow interrupt, interrupts due to INT instructions, etc.

Suppose an external device interrupts the CPU at the interrupt pin, either NMI or
INTR of the 8086, while the CPU is executing an instruction of a programme. The CPU
first completes the execution of the current instruction. The IP is then incremented to
point to the next instruction. The CPU then acknowledges the requesting device on its
pin immediately if it is a NMI, TRAP or Divide by Zero interrupt. If it is an INT
request, the CPU checks the IF flag. If the IF is set, the interrupt request is
acknowledged using the pin. If the IF is not set, the interrupt requests are ignored.
Note that the responses to the NMI, TRAP and Divide by Zero interrupt requests are
independent of the IF flag. After an interrupt is acknowledged, the CPU computes the
vector address from the type of the interrupt that may be passed to the interrupt
structure of the CPU internally (in case of software interrupts, NMI, TRAP and Divide by
Zero interrupts) or externally, i. e. from an interrupt controller in case of external
interrupts. (The contents of IP and CS are next pushed to the stack. The contents of IP
and CS now point to the address of the next instruction of the main programme from
which the execution is to be continued after executing the ISR. The PSW is also pushed
to the stack). The Interrupt Flag (IF) is cleared. The TF is also cleared, after every
response to the single step interrupt. The control is then transferred to the interrupt
service routine for serving the interrupting device. The new address of ISR is found out
from the interrupt vector table. The execution of the ISR starts. If further interrupts are to
be responded to during the time the first interrupt is being serviced, the IF should again
be set to 1 by the ISR of the first interrupt. If the interrupt flag is not set, the subsequent
interrupt signals will not be acknowledged by the processor, till the current one is
completed. The programmable interrupt controller is used for managing such multiple
interrupts based on their priorities. At the end of ISR the last instruction should be IRET.
When the CPU executes IRET, the contents of flags, IP and CS which were saved at
the start by the CALL instruction are now retrieved to the respective registers. The
execution continues onwards from this address, received by IP and CS.
 We now discuss how the 8086/88 finds out the address of an ISR. Every external
and internal interrupt is assigned with a type (N), that is either implicit (in case of NMI,
TRAP ad Divide by Zero) or specified in the instruction INT N (in case of internal
interrupts). In case of external interrupts, the type is passed to the processor by an
external hardware like programmable interrupt controller. In the zeroth segment of
physical address space, i. e. CS = 0000, Intel has reserved 1,024 locations for storing
the interrupt vector table. The 8086 supports a total of 256 types of the interrupts, i. e.
from 00 to FFH. Each interrupt requires 4 bytes, i. e. two bytes each for IP and CS of its
ISR. Thus a total of 1,024 bytes are required for 256 interrupt types, hence the interrupt
vector table starts at location 0000:0000 and ends at 0000:03FFH. The interrupt vector
table contains the IP and CS of all the interrupt types stored sequentially from address
0000:0000 to 0000:03FFH. The interrupt type N is multiplied by 4 and the hexadecimal
multiplication obtained gives the offset address in the
zeroeth code segment at which the IP and CS addresses of the interrupt service routine
(ISR) are stored. The execution automatically starts from the new CS : IP.

Fig.5.14 shows the interrupt sequence o 8086/88 and Fig.5.15 shows the
structure of interrupt vector table.
 Fig.5.14 Interrupt Response Sequence

Fig.5.15 Structure of Interrupt Vector Table of 8086

1.9 Non-Maskable and Maskable Interrupt

1.9.1 Non-Maskable Interrupt

The processor 8086/88 has a Non-Maskable Interrupt input pin (NMI), that has
the highest priority among the external interrupts. TRAP (Single Step-Type 1) is an
internal interrupt having the highest priority amongst all the interrupts except the Divide
by Zero (Type 0) exception. The NMI is activated on a positive transition (low to high
voltage). The assertion of the NMI interrupt is equivalent to an execution of instruction
INT 02, i. e. Type 2 INTR interrupt.
The NMI pin should remain high for at least two clock cycles and need not
synchronized with the clock for being sensed. When the NMI is activated, the current
instruction being executed is completed and then the NMI is served. In case of string
type instructions, this interrupt will be served only after the complete string has been
manipulated. Another high going edge on the NMI pin of 8086, during the period in
which the first NMI is served, triggers another response. The signal on the NMI pin must
be free of logical bounces to avoid erratic NMI responses.

1.9.2 Maskable Interrupt (INTR)

The processor 8086 also provides a pin INTR, that has lower priority as
compared to NMI. Further the priorities within the INTR types are decided by the type of
the INTR signal that is to be passed to the processor via data bus by some external
device like the programmable interrupt controller. The INTR signal is level triggered and
can be masked by resetting the interrupt flag. It is internally synchronized with the high
transition of the CLK. For the INTR signal, to be responded to in the next instruction
cycle, it must go high in the last clock cycle of the current instruction or before that. The
INTR requests appearing after the last clock cycle of the current instruction will be
responded to after the execution of the next instruction. The status of the pending
interrupts is checked at the end of each instruction cycle.
If the IF is set, the processor is ready to respond to any INTR interrupt if the IF is
reset, the processor will not serve any interrupt appearing at this pin. However, once the
processor responds to an INTR signal, the IF is automatically reset. If one wants the
processor to further respond to any type of INTR signal, the IF should again be set. The
interrupt acknowledge sequence is as shown in Fig.5.16.

Fig.5.16 Interrupt Acknowledge Sequence of

8086