Experiment-11: Chalamala Sujith Reddy 19CS01009
Experiment-11: Chalamala Sujith Reddy 19CS01009
Experiment-11: Chalamala Sujith Reddy 19CS01009
Truth Table:
CLK QA QB QC QD
0 1 1 1 1
1 0 1 1 1
2 1 0 1 1
3 0 0 1 1
4 1 1 0 1
5 0 1 0 1
6 1 0 0 1
7 0 0 0 1
8 1 1 1 0
9 0 1 1 0
10 1 0 1 0
11 0 0 1 0
12 1 1 0 0
13 0 1 0 0
14 1 0 0 0
15 0 0 0 0
Characteristic Table:
MOD-10 Ripple Counter:(UP Counter)
Truth Table:
CLK QA(LSB) QB QC QD(MSB)
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0
Circuit:
Discussion:
1. Whether counter is up/down counter is decided by whether we are
attaching Q/~Q of flipflop to clock of next flip flop.
2. We can make any Mod counter by attaching a AND gate to reset
3. Since one flip flop is dependent on previous flip flop, there will be
propagation delay making it asynchronous.
Conclusion:
4-bit Rippler Counter & mod-10, mod-12 ripple counter has been designed and
truth table is verified.