MCS@51 MICROCONTROLLER

FAMILY USER’S MANUAL

ORDER NO.: 272383-002

FEBRUARY 1994
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 MCS” 51 CONTENTS PAGE

MICROCONTROLLER c“*pTf== 1
FAMILY MCS 51 Family of Microcontrollers
Archkedural Ovewiew .............................l-l
USER’S MANUAL
CHAPTER 2
MCS 51 Programmer’s Guide and
Instruction Set ..........................................2-l
CHAPTER 3
8051, 8052 and 80C51 Hardware
Description ...............................................3.l
CHAPTER 4
8XC52J54/58 Hardware Description ............4-1
CHAPTER 5
8XC51 FX Hardware Description .................5-1

CHAPTER 6
87C51GB Hardware Description .................8-1

CHAPTER 7
83CI 52 Hardware Description ....................7-1
MCS@ 51 Family of 1

Microcontrollers
Architectural Overview
 MCS@51 FAMILY OF CONTENTS PAGE

MICROCONTROLLERS INTRODUCTION .........................................1-3

ARCHITECTURAL CHMOSDevices .....”.....’.......”.....-...-..........I-5

OVERVIEW M;~$&:RGA-~oN INMc- 51

.................................................1-6
Lo ical Separation of Program and Data
h emoy ....................................................l+
Program Memo~ .........................................l-7
Data Memory ...............................................1 -8

THE MC951 INSTRUCTION SET .............1 -9

Program Status Word ..................................1 -9
Addressing Modes .....................................l-l O
Arithmetic Instructions ...............................1-10
Logical lnstrudions ....................................l.l2
Data Tran#ers ...........................................l.l2
Boolean Instructions ..................................1-14
Jump Instructions ......................................1-16

CPU TIMING .............................................l-l7

Machine Cycles .........................................1-18
Interrupt Structure ......................................l.2O

ADDITIONAL REFERENCES ...................1 -22

1-1
ir&L M~@.51 ARCHITECTURAL OVERVIEW

INTRODUCTION
The8051 is the original member of the MCW-51 family, and is the core for allMCS-51 devices. The features of the
8051 core are -
● 8-bit CPU optimized for control applications

● Extensive Boolean processing (Single-blt logic) capabtilties

● 64K Program Memory address space

● 64K Data Memory address space
● 4K bytes of on-chip Program Memory
● 128 bytesof on-chip Data RAM
● 32 bidirectional and individually addressable 1/0 lines
● Two 16-bit timer/counters
● Full duplex UART
● 6-source/5-vector interrupt structure with two priority levels
● On-chip clock oscillator

The basic architectural structure of this 8051 core is shown in Figure L

EXTERNAL
INTERRUPTS
,, I I
COUNTER
INPUTS

w II H H
BUS
CONTROL

11
Po
4 1/0 PORTS

P2

AODRESS/DATA
PI P3
Q SERIAL
PORT

TXO RXD

270251-1

Figure 1. Block Diagram of the 8051 Core

1-3
intd. MCS@-51 ARCHITECTURAL OVERVIEW

1-4
i~. MCS@’-5l ARCHITECTURAL OVERVIEW

1-5
i~. M~@.51 ARCHITECTURAL OVERVIEW

PROORAMMrhtosv OATAMEMORY
(REM ONLY) (RW/WRlT2)
* ----------- -------------- ------------------------ . . . . .
8 $ t 8
1 FFFFw s 8 8
1 I I I
1 1 1 I
1 1 I 0
1 T - 1 8 I
1 1 I *
1 1 I 0
I 1 I I
1 1 EXIERNALm I
I 1 : #
o 1 o I
8 1 # I
0 1 8 I
0 EXTERNAL 1 9 I
0 1 8 I
8 1 8 - I
0 1 0 1
0 I 0
9 1 9 :
I 1 t 1
I 1 # I
I I I I
, , ,
1 B 1 IN7ERNM I
I I : FfH: ------ 1
I
: 0: I
# G=o m.1 : 9,
o e, 1
0 2STERNAL IN7ERNAL : 9
1 0 0 1
0 9 9
@ * 8 0
* I 1 1
I 0000 I I 00
,1+ 0000 J: 1
I
: 1
● - --- -------- -------- -.! ● -------- --------- ..- -. -.-:

1% tiR
270251-2

Figure 2. MCW’-51 Memory Structure

CHMOS Devices MEMORY ORGANIZATION IN

MCS@-51 DEVICES
Functionally, the CHMOS devices (designated with
“C” in the middle of the device name) me all fiuy
compatible with the 8051, but being CMOS, draw less Logical Separation of Program and
current than an HMOS counterpart. To further exploit Data Memory
the power savings available in CMOS circuitry, two re-
duced power modes are added AU MCS-51 devices have separate address spacea for
● Software-invoked Idle Mode, during which the CPU Program and Data Memory, as shown in Figure 2. The
is turned off while the RAM and other on-chip logical separation of Program and Data Memory allows
peripherals continue operating. In this mode, cur- the Data Memory to be acceased by 8-bit addressea,
rent draw is reduced to about 15% of the current which can be more quickly stored and manipulated by
drawn when the device is fully active. an 8-bit CPU. Nevertheless, ld-bh Data Memory ad-
dresses can also be generated through the DPTR regis-
● Software-invoked Power Down Mode, during which
ter.
all on-chip activities are suspended. The on-chip
RAM continues to hold its data. In this mode the
Program Memory can only be read, not written to.
device typically draws less than 10 pA.
There can be up to 64K bytes of Program Memory. In
Although the 80C51BH is functionally compatible with the ROM and EPROM versions of these devices the
its HMOS counterpart, s~lc differeneea between the loweat 4K, 8K or 16K bytes of Program Memory are
two types of devices must be considered in the design of provided on-chip. Refer to Table 1 for the amount of
an application circuit if one wiahea to ensure complete on-chip ROM (or EPROM) on each device. In the
interchangeability between the HMOS and CHMOS ROMleas versions all Program Memory is external.
devices. These considerations are discussed in the Ap The read strobe for external Program Memory is the
plieation Note AP-252, “Designing with the signal PSEN @rogram Store Enable).
80C5lBH.

For more information on the individual devices and

features listed in Table 1, refer to the Hardware De
scriptions and Data Sheets of the specific device.

1-6
intel. MCS@-51 ARCHITECTURAL OVERVIEW

Data Memory occupies a separate addrexs space from The lowest 4K (or SK or 16K) bytes of Program Mem-
%OgrCt122 hkznory. Up to 64K bytes of exterttd RAM ory can be either in the on-chip ROM or in an external
can be addreased in the externrd Data Memo~. ROM. This selection is made by strapping the ~ (Ex-
The CPU generatea read and write signals RD and ternal Access) pin to either VCC or Vss.
~, as needed during external Data Memory accesses.
In the 4K byte ROM devices, if the= pin is strapped
External Program Memory and external Data Memory to VcC, then program fetches to addresses 0000H
~~ combined if-desired by applying the ~ ~d through OFFFH are directed to the internal ROM. Pro-
PSEN signals to the inputs of an AND gate and using gram fetches to addresses 1000H through FFFFH are
the output of the gate as the read strobe to the external directed to external ROM.
Program/Data memory.
In the SK byte ROM devices, = = Vcc selects ad-
dresses (XtOOHthrough lFFFH to be internal, and ad-
ProgramMemory dresses 2000H through F’FFFH to be external.

Figure 3 shows a map of the lower part of the Program In the 16K byte ROM devices, = = VCC selects ad-
Memory. After reset, the CPU begins execution from dresses 0000H through 3FFFH to be internal, and ad-
location OWOH. dresses 4000H through FFFFH to be external.

AS shown in F@ure 3, each interrupt is assigned a tixed If the ~ pin is strapped to Vss, then all program
location in Program Memory. The interrupt causes the fetches are directed to external ROM. The ROMleas
CPU to jump to that location, where it commences exe- parts must have this pin externally strapped to VSS to
cution of the serviee routine. External Interrupt O, for enable them to execute properly.
example, is assigned to location 0003H. If External In-
terrupt O is going to & used, its service routine must The read strobe to externally: PSEN, is used for all
begin at location 0003H. If the interrupt is not going to external oro.cram fetches. PSEN LSnot activated for in-
be used, its service location is available as general pur-
pose Program Memory.

m%

l== 1
EPROM

..-.
&
(O033H)
‘s 1 Po

m
INSTR.

002EH =
ALE
002SH LArcn AOOR
INTSRRUPT
LOCATIONS
00IBH

0013H II
Ssvrm
a’s ‘z~
000SH 270251-4

0003H Figure 4. Executing from External

R2S~ 0000H
i Program Memory
270251-3
The hardware configuration for external program exe-
Figure 3. MCW’-51 Program Memory cution is shown in Figure 4. Note that 16 I/O lines
(Ports O and 2) are dedicated to bus fictions during
The interrupt aeMce locations are spaced at 8-byte in- external Program Memory f~hes. Port O(PO in Figure
tervak 0U03H for External Interrupt O, 000BH for 4) servex as a multiplexed address/data bus. It emits
Tmer O, 0013H for External Interrupt 1, 00IBH for the low byte of the Program Counter (PCL) as an ad-
Timer 1, etc. If an interrupt service routine is short dress, snd then goes into a float state awaiting the arriv-
enough (as is often the case in control applications), it al of the code byte from the Program Memory. During
can reside entirely within that 8-byte interval. Longer the time that the low byte of the Program Counter is
service routinea can use a jump instruction to skip over valid on PO, the signal ALE (Address Latch Enable)
subsequent interrupt locations, if other interrupts are in clocks this byte into an address latch. Meanwhile, Port
use. 2 (P2 in Figure 4) emits the high byte of the Program
Countex (WI-I). Then ~ strobex the EPROM and
the code byte is read into the microcontroller.

1-7
 MCS@-51 ARCHITECTURAL OVERVIEW

Program Memory addresses are always 16 bits wide, Internal Data Memory is mapped in Figure 6. The
even though the aotual amount of Program Memory memory space is shown divided into three bloeka,
used ntSy be kSS than 64K bytes. External prOq which are generally referred to as the Lower 128, the
exeoutiorssacrifices two of the 8-bit ports, PO and P2, to Upper 128, and SFR space.
the fisnction of addressing the Program Memory.
Internal Data Memory addresses are always one byte
Wid%which implies an address space of only 256 bytes.
Data Memory However, the addressing modes for intemssl RAM ean
in fact seeommodate 384 bytes, using a simple trick.
Theright half of Figure 2 shows the internal and exter- Direct addresses higher than 7FH awes one memory
nal Dats Memory spaces available to the MCS-51 user. space, and indirect addresses higher than 7FH access a
different memory space. Thus Figure 6 shows the Up-
F@ure 5 shows a hardware configuration for accessing per 128 and SFR spaceoccupyingthe ssmeblockof
up to 2K bytes of external RAM. The CPU in this ease addrq 80H throu~ FFH, slthoud they are physi-
is executing from internal ROM. Port O serves as a cally separateentities;
multiplexed address/data bus to the RAM, and 3 lines
of Port 2 are bein~d to page the RAM. The CPU

n
generates = and WR signals as needed during exter-
7FH
ial WM ameases. -

BANK 2FH
SELECT SN-ACORESSASLSSPACE
BRS IN (S~ A~ESSES O-7F)
‘1 20H 1
1FH
“{ lSH
17H
‘0{ 10H 4 SANKSOF
8 REGIS7SRS
OFH RO-R7
0’{ OBH
07H RESETVALUEOF
eo{o Ill S7ACKPOIN7ER
270251-7
1’ I I
270251-5 Figure 7. The Lower 128 Bytes of internal RAM

Figure 5. Accessing External Data Memory. The Imwer 128 bytes of W are present in all
If the Program Memory is Internal, the Other MCS-51 devices as mapped in F@ure 7. The lowest 32
Bits of P2 are Available as 1/0. bytes are grouped into 4 banks of 8 registers. Program
instructions call out these registers as RO through R7.
There ean be up to 64K bytea of external Data Memo- Two bits in the Program Status Word (PSW) seleet
ry. External Data Memory addresses can be either 1 or which register bank is in use. This allows more effieient
2 bytes wide. One-byte addresses are often used in cxm- use of code space, since register instructions are shorter
junction with one or more other 1/0 lines to page the than instructions that use direet addreasiig.
R4M, as shown in Figure 5. Two-byte addresws ears
atso be used, irz which case the high address byte is
emitted at Port 2. FFH

I
~:.. .-... - FFH NO SIT-AOORSSSABLE
, AC=IELE ACCESSIBLE SPACES

EP
UPP~ , SV INDIREC7 BV OIRECT
: AtORESSING AODRSSSING AVAIUBLE AS S7ACK
ONLY SPACEIN DEVICESWMI
SDH9 80H 256 BWES RAM

128
‘m
LOWER
ACCESSIBLE
SY 01REC7
ANO INC+REC7
o AGGRESSING
W 1
SPWAL
NC710N &oAmm~o
‘E~m CONTROLems
NOT IMPLE14EN7ED
IN 8051

TIMER
RE—
STACKiolN7ER 80H
ACCUMULATOR 270251-8
(’nC.)
270251-6 Figure 6. The Upper 128 Bytes of Internal RAM
Figure 6. Internal Data Memory

I-6
in~. M~@-51 ARCHITECTURAL OVERVIEW

CTIAC] FOIRSIIRBO[ OVI I P

I
b a a A * A
1 KWO
CARRYFLAGRECEIVESCMi/fmw; PARllYOFACCLWUIATORSS7
FROU BIT 1 Of ALU OPERANOS ~ NARoWARCTO 1 IF IT CONTAINS
AN 000 NUMBEROF 1S, OTHERWISE
171SRESE7TO0

Psw6— — Psw 1
AUXILIARYCARRYFLAG RECEIVES USER OEFINABLEFUG
CARRYOUT FROM B171 OF
AOOMON OPERANOS

nw5 Psw 2
GENERALPURPOSES7ATUS FLAG OVERFLOWFIAO SET BY
ARITIMCWOPERAl!ONS

Psw3
REGtS7ER
BANKSW’% t REOSJER
BANKSELECT
Bll O
270251-10

-. .- . . . . . .- . . . ... .. . . . ------ ----

Figure 1u. Psw (Progrsm ssssus worn) Register m mc5w-51 t2evtces

The next 16 bytea above the register bankBform a block !%teers addresses in SFR mace are both byte. and bit.
of bit-addressable memory apace. The MCS-51 instruc- addressable. The blt-addre&able SFRS are ‘those whose
tion set includes a wide seleetion of single-blt instruc- address ends in 000B. The bit addresses in this ares are
tions, and the 128 bits in this area can be directly ad- 80H throUgh FFH.
dressed by these irsstmctions. The bit addreascs in this
area are W)H through 7FH.
THE MCS@-51 INSTRUCTION SET
All of the bytes in the LQwer 128 can be accessed by
either direct or indirect addressing. The Upper 128 All members of the MCS-51 family execute the same
(Figure 8) can only be accessed by indirect addressing. instruction set. The MCS-51 instruction set is opti-
The Upper 128 bytes of RAM are not implemented in mized for 8-bit control applications. It provides a vari-
the 8051, but me in the devices with 256 bytea of RAM. ety of fast addressing modes for accessing the internal
(Se Table 1). MM to facilitate byte operations on small data struc-
tures. The instruction sd provides extensive support for
Figure 9 gives a brief look at the Special Funotion Reg- one-bit variables as a separate data t% allowing direct
ister (SFR) space. SFRS include the Port latchea, tim- blt manipulation in control and logic systems that re-
ers, pe2iphA controls, etc. l%ese registers can only& quire Boolean prmessirsg.
-seal by dmect addressing. In general, all MCS-51
microcontrollers have the same SFRB as the 8051, and An overview of the MCS-51 instruction set is prrsented
at the same addresses in SFR space. However, enhance- below, with a brief description of how certain instruc-
ments to the 8051 have additional SFRB that are not tions might be used. References to “the assembler” in
present in the 8051, nor perhaps in other proliferations this discussion are to Intel’sMCS-51 Macro Assembler,
of the family. ASM51. More detailed information on the instruction
set can be found in the MCS-51 Macro Assembler Us-
er’s Guide (Grder No. 9W3937 for 1S1SSystems, Grder
No. 122752 for DOS Systems).
“u
EOH
RE~MAPPSO POR7S

AOORESSES7NAT END IN Program Status Word

OH OR EN ARCALSO
B~-AOORESSABLE
m The Program Status Word (PSW) contains several
80H PORT .3
status bits that reflect the current state of the CPU. The
-POR7 PINS
-ACCUMULATOR PSW, shown in Figure 10, resides in SFR space. It con-
-Psw tains the Csrry bi~ the Auxdiary Carry (for BCD oper-
AOH Porn 2 (E7c.)
ations), the two register bank select bits, the Gvesflow
POR7 1
flag, a Parity bit, and two userdefinable status tlags.
90H
B
The Carry bit, other than serving the functions of a
J-A--I Carry bit in arithmetic operations, also sesws as the
“Accumulator” for a number of Boolean operations.
270251-9

Figure 9. SFR Spsce

1-9
 MCS@-51 ARCHITECTURAL OVERVIEW

The bits RSOand RSl are wed to select one of the four IMMEDIATE CONSTANTS
register banks shown in Figure 7. A number of instruc-
tions refer to these RAM locations as RO through R7. The value of a constant can follow the opcode in Pro-
The selection of which of the four banks is being re- gram Memory. For example,
ferred to is made on the basis of the bits RSO and RS1
at execution time. MOV A, # 100

The Parity bit reflects the number of 1s in the Accumu- loads the Accumulator with the decimal number 100.
lator P = 1 if the Accumulator contains an odd num- The same number could be specified in hex digitz as
ber of 1s, and P = O if the Accumulator contains an 64H.
even number of 1s. Thus the number of 1s in the Accu-
mulator plus P is always even.
INDEXED ADDRESSING
Two bits in the PSW are uncommitted and maybe used
only Program Memory can be amessed with indexed
as general purpose status flags. addressing, and it can only be read. This addressing
mode is intended for reading look-up tables in Program
Memory. A Id-bit base register (either DPTR or the
Addressing Modes Program Counter) points to the base of the table, and
The addressing modes in the MCS-51 instruction set the Accumulator is setup with the table entry number.
The address of the table entry in Program Memory is
are as follows
formed by adding the Accumulator data to the base
pointer.
DIRECT ADDRESSING
Another type of indexed addreaaing is used in the “case
In direct addressing the operand is specitied by an 8-bit jump” instruction. In this case the destination address
addreas field in the instruction. Only internal Data of a jump instruction is computed as the sum of the
RAM and SFRS can be directly addressed. base pointer and the Accumulator &ta.

INDIRECT ADDRESSING
Arithmetic Instructions
In indirect addressing the instruction specifies a register
which contains the address of the operand. Both inter- Themenu of arithmetic instructions is listed in Table 2.
The table indicates the addressing modes that can be
nal and external RAM can be indirectly addressed.
used with each instruction to access the <byte> oper-
The address register for 8-bit addresses can be RO or and. For example, the ADD A, <byte> instruction can
RI of the selected register bank, or the Stack Pointer. be written as
The addreas register for id-bit addresses can only be the
id-bit “data pointer” register, DPTR.
ADD A,7FH (direct addressing)
ADD A,@RO (indirect addressing)
ADD A,R7 (register addressing)
REGISTER INSTRUCTIONS ADD A, # 127 (iediate constant)

The register banks, containing registers RO through R7, The execution times listed in Table 2 assume a 12 MHz
can be accemed by certain instructions which carry a clock frequency. All of the arithmetic instructions exe-
3-bit register specification within the opcode of the in- cute in 1 ps except the INC DPTR instruction, which
struction. Instructions that access the registers this way takes 2 W, snd the Multiply and Divide instructions,
are code efficient, since this mode elirninatez an addreas which take 4 ps.
byte. When the instruction is executedj one of the eight
registers in the selected bank is amessed. One of four Note that any byte in the internal Data Memory space
banks is selected at execution time by the two bank can be incremented or decremented without going
select bits in the PSW. through the Accumulator.

One of the INC instructions operates on the Id-bit

REGISTER-SPECIFIC INSTRUCTIONS
Data Pointer. The Data Pointer is used to generate
Some instructions are specific to a certain register. For 16-bit addresses for external memory, w being able to
example, some instructions always operate on the Ac- increment it in one 16-bit operation is a usefirl feature.
cumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that. In- The MUL AB instruction multiplies the Accumulator
structions that refer to the Accurrdator as A assemble by the data in the B register and puts the Id-bit product
as accumulator-specific opcmdes. into the concatenated B and Accumulator registers.

1-1o
inl# MCS@-51 ARCHITECTURAL OVERVIEW

Table 2 A Ust of the MCS@I-51 Arithmetic Instructions

Addressing Modes Execution

Mnemonic Operation
Time (@
Dk I Ind Rq lmm
ADD A, <byte> A = A + <byte> x x x x 1
I ADDOA, <byte> I A= A+< byte>+C I X I X I X I X ] 1 I
SUBB A, <byte> A= A–<byte>-C x x x x 1
INC A I A=A+l I Accumulator onlv I 1
I INC . <byte> I <byte> =<byte>+l I X I X I X I 11-1
I lhJC DPTR I DPTR = DpTR + 1 I Data Pointer only 121
I DEC A I A= A-l I Accumulator only Ill
DEC <byte> <byte> = <byte> – 1 x I x x I 1
MUL AB B.A=Bx A ACC and B only 4

I DIV AB
I A = Int [A/B]
B = MOd [A/Bl
ACC and B only
I 4
I
IDAA I Decimal Adjust I Accumulatoronly Ill
The DIV AB instruction divides the Accumulator by eompletcs the shift in 4 p.s and leaves the B register
the data in the B register and leevea the 8-bit quotient holding the bits that were shifted out.
in the Accumulator, and the 8-bit remainder in the B
register. The DA A instruction is for BCD arithmetic opera-
tions. In BCD arithmetic, ADD and ADDC instruc-
Oddly enough, DIV AB finds lees use in arithmetic tions should always be followed by a DA A operation,
“divide” routines than in radix eonversions and pro- to ensure that the red is also in BCD. Note that DA
~ble shift operstioILs. k example of the use of A will not convert a binary number to BCD. The DA
DIV AB in a radix conversion will be given later. In A operation produces a meaningfid result only as the
s~ operations, dividing a number by 2n shifts its n second step in the addition of two BCD bytes.
bits to the right. Using DIV AS to perform the division
Table 3. A Uet of the MCS@J-51Logical Instructions

I I I
Addressing Modes Execution
Mnemonic Operation
Time (ps)
Dir Ind I Reg I Imm

ANL A,< byte> A = A .AND. <byte> x x x x 1

ANL <byte>,A <byte> = <byte> .AND. A x 1
ANL <bvte>, #data <byte> = <byte> .AND. #data x 2
ORL A,< byte> I A= A.OR. <byte>
I X1X1X1X 1
ORL <bvte>,A <byte> = <byte> .OR. A x 1
ORL <byte>, #data I <byte> = <byte> .OR. #data x 2
XRL A,< byte> A = A .XOR. <byte> X1X1X x 1

XRL <byte>,A I
<byte> = <byte> .XOR. A x I I 1
XRL <byte>, #data <byte> = <byte> .XOR. #data I X I 2

CRL A A=OOH Accumulator only 1

CPL A A = .NOT. A Accumulator only I 1
IRL A I Rotate ACC Left 1 bit I Accumulator onlv Ill
RLC A I Rotate Left through Csrry I Accumulator only I 1
RR A Rotate ACC Right 1 bit Accumulator only 1
RRC A Rotate Right through Carry Accumulator only 1

SWAP A Swap Nibbles in A Accumulator onlv 1

1-11
irrtel. MCS@-51 ARCHITECTURAL OVERVIEW

Logical Instructions The SWAP A instruction interchanges the high and

low nibbles within the Accumulator. This is a useful
Table 3 shows the list ofMCS-51 logical instructions. operation in BCD manipulations. For exampie+ if the
The instructions that perform Boolean operations Accumulator contains a binary number which is known
(AND, OIL Exclusive OIL NOT) on bytes perform the to be leas thsn IQ it can be qnickly converted to BCD
operation on a bit-by-bit bssis. That is, if the Aecumu- by the following code:
Iator contains 001101OIB and <byte> contains
O1OIOOIIB,then MOV B,# 10
DIV AB
ANL A, <byte> SWAP A
ADD A,B
will leave the Accumulator holding OOO1OOOIB.
Dividing the number by 10 leaves the tens digit in the
The addrcasing modes that can be used to access the low nibble of the Accumulator, and the ones digit in the
<byte> operand are listedin Table 3. Thus, the ANL B register. The SWAP and ADD instructions move the
A, <byte> instruction may take any of the forms tens digit to the high nibble of the Accumulator, and
the onea digit to the low nibble.
ANL A,7FH (direct addressing)
ANL A,@Rl (indirect addressing)
ANL A,R6 (register addressing) Data Transfers
ANL A, # 53H (immediate constant)
INTERNAL RAM
AU of the logical instructions that are Accumulator-
specflc execute in lps (using a 12 MHz clock). The Table 4 shows the menu of instructions that are avail-
othem take 2 ps. able for moving data around within the internal memo-
ry spaces, and the addressing modes that can be used
Note that Boolean operations can be performed on any with each one. Wkh a 12 MHz clock, all of these in-
byte in the lower 128 internal Data Memory space or structions execute in either 1 or 2 ps.
the SFR space using direct addressing, without having
to use the Accumulator. The XRL <byte >, #data in- The MOV < dest >, < src > instruction allows dats to
struction, for example offets a quick and easy way to be transferred between any two internal RAM or SFR
invert port bits, as in lwations without going through the Accumulator. Re-
member the Upper 128 byes of data RAM can be ac-
XRL Pl,#oFFH wased only by indirect addressing, and SFR space only
by direct addressing.
If the operation is in response to an interrupt, not using
the Accumulator saves the time and effort to stack it in Note that in all MCS-51 devices, the stack resides in
the service routine. on-chip RAM, and grows upwards. The PUSH instruc-
tion first increments the Stack Pointer (SP), then copies
The Rotate instructions (3U & RLC A, etc.) shift the the byte into the stack. PUSH and POP use only dkcct
Aeeurtmlator 1 bit to the MI or right. For a left rota- addressing to identify the byte being saved or restored,
tion, the MSB rolls into the LSB position. For a right
rotation, the LSB rolls into the MSB position.
Table 4. A List of the MCS@-51 Data Tranafer Instructions that Access Internal Data Memory Space

Addressing Modes Execution

Mnemonic Operation
Time (ps)
Dir Ind Reg Imm

MOV A, <src> A = <src> x x x x 1

MOV <cleat> ,A <dest> = A x x x 1
MOV <dest>, <src> <dest> = <src> x x x x 2
MOV DPTR,#data16 DPTR = 16-bit immediate constant. x 2

PUSH <WC> INC SP: MOV “@’SP’, <src> x 2

POP <dest> MOV <dest>, “@SP”: DEC SP x 2
XCH A, <byte> ACC and <byte> exchange data x x x 1
XCHD A,@Ri ACC and @Riexchange low nibbles x 1

1-12
i~o MCS@-51 ARCHITECTURAL OVERVIEW

but the stack itself is accessed by indirect addressing Atler the routine has been executed, the Accumulator
using the SP register. This means the stack can go into contains the two digits that were shitled out on the
the Upper 128, if they are implemented, but not into right. Doing the routine with direct MOVS uses 14 code
SFR space. bytes and 9 ps of execution time (assuming a 12 MHs
clock). The same operation with XCHS uses less code
In devices that do not implement the Upper 128, if the and executes almost twice as fast.
SP points to the Upper 128, PUSHed bytes are lost, and
POPped bytes are indeterminate. To right-shift by an odd number of digits, a one-digit
shift must be executed. Figure 12 shows a sample of
The Data Transfer instructions include a id-bit MOV code that will right-shii a BCD number one digi~ us-
that can be used to initialise the Data Pointer (DPTR) ing the XCHD instruction. Again, the contents of the
for look-up tables in Program Memory, or for Id-bit registers holding the number and of the Accumulator
external Data Memory accesw. are shownalongsideeachinstruction.
The XCH A, <byte> instruction causes the Amu-
lator snd addressed byte to exchsnge data. The XCHD
A, @Ri instruction is similar, but only the low nibbles MOV Rl, #2EH
are involved in the exchange. MOV RO,#2DH m
loop for R1 = 2EH
To see how XCH and XCHD can be used to fatitate
.00P MOV A,@Rl 00 12 34 56 78 76
data manipulations, consider first the problem of shit%- XCHD A,@RO 00 12 34 56 78 76
ing an 8digit BCD number two digits to the right. Fig- SWAP A 00 12 34 58 78 67
ure 11 shows how this can be done using direct MOVS, MOV @Rl,A 00 12 34 58 67 67
and for comparison how it can be done using XCH DEC RI 00 12 34 58 67 67
instructions. To aid in understanding how the code DEC RO 00 12 34 56 67 67
works, the contents of the registers that are holding the CJNE Rl,#2AH,LOOP
BCD number and the content of the Accumulator are Imp for RI = 2DH 00 12 36 45 67 45
shown alongside each instruction to indicate their loop for R1 = 2CH: 00 18 23 45 67 23
status after the instruction has been executed. ioop for RI = 2BH: 0s 01 22 45 67 01
CLR A 06 01 23 45 67 00
XCH A,2AH 00 01 23 45 67 06

n3JMm
MOV

MOV
A,2EH
MOV 2EH2DH
2CH:2BH
%
00
;;
12
: % ~
Figure 12. Shifting a SCD Number
One Digit to the Right

First, pointers RI and RO are setup to point to the two

gm
bytea containing the last four BCD digits. Then a loop
(a) Using direct MOVS 14 bytes, 9 ps
is executed which leaves the last byte, location 2EIL
holding the last two digits of the shifted number. The
pointers are decrernented, and the loop is repeated for
location 2DH. The CJNE instruction (Compare and
Jump if Not Equal) is a loop control that will be de-
scribed later.
~
(b) Using XCHS 9 bytes, 5 ps The loop is executed from LOOP to CJNE for R1 =
.. 2EH, 2DH, 2CH and 2BH. At that point the digit that
Figure 11. Shifting a BCD Number was originally shii out on the right has propagated
Two Dlgite to the Right to location 2AH. Siice that location should be left with
0s, the lost digit is moved to the Accumulator.

1-13
 M~@.51 ARCHITECTURAL OVERVIEW

EXTERNAL RAM Table 6. Tha MCS3’-51 Lookup

Table Read Inetmctions
Table 5 shows a list of the Data Transfer inatmctions
that acceas external Data Memory. Only indirect ad-
&easing can be used. The choice is whether to use a
one-byte address, @M where Ri can be either RO or
RI of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using 16-bit addresses if
I at (A + PC) -
only a few K bytesof externalRAMare involvedis 1
that 16-bit addresses use alf 8 bits of Port 2 as addreas
bus. On the other hand, S-bit addresses allow one to The first MOVC instruction in Table 6 can accommo-
address a few K bytes of RAM, as shown in Figure 5, date a table of up to 256 entries, numbered O through
without having to sacrifice all of Port 2. 255. The number of the desired entry is loaded into the
Accumulator, and the Data Pointer is setup to point to
Alf of these instructions execute in 2 pa, with a beginning of the table. Then
12 MHz clock.
Tabfe 5. A List of the MCS@-51 Data MOVC A,@A+DPTR
Trsnafer Instructions that Accees
Extarnsl Data Memory Spaoe
copies the desired table entry into the Accumulator.

Address Execution The other MOVC instruction works the same way, ex-
Mnemonic Operation
Width Time (*) cept the Program Counter (PC) is used as the table
8 b~ MOVX A,@’Ri
Read external ~ base, and the table is accewed through a subroutine.
RAM @Ri First the number of the desired entry is loaded into the
Write external Accumulator, and the subroutine is cslled:
8 bb MOVX @Ri,A 2
RAM @Ri
Read external MOV &ENTRY_NUMBER
2 CALL TABLE
‘6 bns ‘ovx “@DpTR RAM @DPTR
Writa exlemal
16 bfia 2 The subroutine “TABLE” would look like this:
‘ovx ‘DmR’A RAM @DPTR

TABLE: MOVC A,@A + PC

Note that in all external Data RAM acaases, the Ac-
cumulator is always either the destination or source of
the data.
The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
The read and write strobes to external RAM are acti-
have up to 255 entries, numbered 1 through 255. Num-
vated only during the execution of a MOVX instruc-
ber O can not be used, because at the time the MOVC
tion. Normally these signals are inactive and in fact if
instruction is executed, the PC contains the address of
they’re not going to be used at u their pins are avail-
the RET instruction. An entry numbered O would be
able as extra 1/0 lines. More about that later.
the RET opcode itseff.

LOOKUP TABLES
Boolean Instructions
Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since MCS-51 devices contain a complete Boolean (single-bit)
these instructions access only Program Memory, the processor. The internal RAM contains 128 addressable
lookup tablea can only be read, not updated. The nme- bits, and the SFR space can support up to 128 other
monic is MOVC for “move constant”. addressable blta. Afl of the port lines are bWaddress-
abl% and each one csn be treated as a separate single-
If the table access is to external Program Memory, then blt port. The instructions that access these bits are not
the read strobe is PSEN. just conditional branches, but a complete menu of
move, aeL clear, complement, OR and AND instmc-
tions. These kinds of bit operations are not essily ob-
tained in other architectures with any amount of byte-
Oriented Sottware.

1-14
intd. MCS@-51 ARCHITECTURAL OVERVIEW

Table 7. A List of the MCS’@-51 Note that the Boolean instruction set includes ANL
Boolean Instrutilons and ORL operations, but not the XRL (_ExclusiveOR)
operation. An XRL operation is simple to implement in
Execution sof?.ware.Suppose, for example, it is Wuired @ form
Mnemonic Operation
Time (us) the Exclusive OR of two bits
ANL C,bit IC = C .AND. bit I 2
C = bitl .XRL. bit2
ANL C./bit !IC = C .AND. .NOT. bit I1 2
nnl n G. 16= C.OR. bit 2 The sot%vare to do that could be as follows:

MOV C,bit 1

F
MO\
MO\
ICLR
UIL,U I UIL
c Ic=o
– w 1=

1
I

1
OVER
CPL
(continue)
bit2,0VER
C

CLR bit ]bit=o 1 Fkst, bit 1 is moved to the Carry. If bit2 = O, then C
SETB C Ic=l I 1 now contains the correct reauh. That is, bit 1 .XRL. bit2
= bitl ifbiti = O. On the other hand, ifbit2 = 1 C
SETB bn Ibit= 1 1 now contains the complement of the correct result. It
CPL C I C = .NOT. C 1 need only be inverted (CPL C) to complete the opcrs-
1 tion.
CPL bit I bit = .NOT. bit
JC rel lJumpif C= 1 2 This code uses the JNB instruction, one of a series of
JNC rel Jump if C = O 2 bk-teat instructions which execute a jump if the ad-
dressed bit is set (JC, JB, JBC) or if the addressed bit is
JB bit,rel Jump if bti = 1 2 not set (JNG JNB). In the above case, blt2 is being
JNB bit,rel Jump if bit = O 2 tested, and if bitZ = Othe CPL C instruction is jumped
JBC bit,rel IJump if bti = 1; CLR bit I 2 over.

JBC executes the jump if the addressed bit is set, and

The instruction set for the Boolean processor is shown also clears the bit. Thus a fig can be teated and cleared
in Table 7. Alt bit ameaaca are by direct addressing. Blt in one operation.
addreases OOHthrough 7PH are in the Lower 128, and
bit addresses 80H through FFH are in SFR space. All the PSW bits are directly addressable so the Parity
bit, or the general purpose flags, for example, are also
Note how easily an internal ilag can be moved to a port available to the bit-test instructions.
pin:

MOV C,PLAG RELATIVE OFFSET

MOV P1.o,c
The destination address for these jumps is specitied to
In this example, FLAG is the name of any addressable the assembler by a label or by an actual address in
bit in the Lower 128 or SFR space. An 1/0 line (the Program Memory. However, the destination address
LSB of Port 1, in this case) is set or cleared depending assembles to a relative offset byte. This is a signed
on whether the flag blt is 1 or O. (two’s complement) oftket byte which is added to the
PC in two’s complement arithmetic if the jump is exe-
The bTy bit in the PsW isused as the single-bit ACCU. cuted.
mulator of the Boolean processor. Bit instructions that
refer to the Carry bit as C assemble as Carry-specflc The range of the jump is therefore -128 to + 127 Pro-
instructions (CLR C, etc). The Carry bit also has a gram Memory bytes relative to the first byte following
direct addreas, since it resides in the PSW register, the instruction.
which is bit-addressable.

1-15
i~. MCS@-51 ARCHITECTURAL OVERVIEW

Jump lnstruMlons the Accumulator. Typically, DPTR is set up with the

addms of a jump table, and the Accumulator is given
Table 8 shows the list of unconditional jumps. an index to the table. In a 5-way branch, for examplq
an integer Othrough 4 is loaded into the Accumulator.
Table 8. Unconditional Jumps The code to be executed might be ax follows
in MCW’-51 Oavices
MOV DPTR, #JUMP_TABLE
I Mnarnonic
I Operation
Exeeution
Tilna (us) MOV
RLA
A,INDEX_NUMBER
I JMP addr I Jumo to addr 121 @A+DPTR
JMP
JMP @A+ DPTR I Jump to A+ DPTR 2
I
CALL addr I Call subroutine at addr 2 The RL A instruction converts the index number (O
through 4) to an even number on the range Othrough 8,
1RET I Return
fromsubroutine I z I because each entry in the jump table is 2 bytee long:
I RETI I Returnfrominterrupt I 2 I
NOP No oparation 1 ~P_TABLE
MMP CASE_O
AJMP CASE_l
The Table lists a single “JMP addr” instruction, but in AJMP CASE_2
fact there are three-SJMP, LJMP and AMP-which AJMP CASE_3
differ in the format of the destination address. JMP is a CASE_4
generic mnemonic which can be used if the program-
mer does not care which way the jump is eneoded. Table 8 shows a single “CALL addr” instruction, but
there are two of them-LCALL and ACALL-which
The SJMP instruction eneodes the destination address differ in the format in which the subroutine address is
as a relative offset, as deaeribed above. The instruction given to the CPU. CALL is a generic mnemonic which
is 2 bytes long, eonsiating of the opeode and the relative ean be used if the programmer does not care which way
offset byte. The jump distance is limited to a range of the address is encoded.
-128 to + 127 bytes reIative to the instruction follow-
ing the SJMP. The LCALL instruction uses the Id-bit address format,
and the subroutine ean be anywhere in the 64K Pro-
The LJMP instruction eneodea the destination address gram Memory space. The ACALL instruction uses the
as a Id-bit constant. The instruction is 3 bytes long, 1l-bit format, and the subroutine most be in the same
consisting of the opeode and two address bytes. The 2K bkxk as the instruction following the ACALL.
destination address ean be anywhere in the 64K Pro-
gram Memory SPSW. In any case the programmer specifies the subroutine
address to the assembler in the same way as a label or
The AJMP instruction encodes the destination address as a 16-bit constant. The assembler will put the address
as an 1l-bit constant. The instruction is 2 bytee long, into the correct format for the given instructions.
eonaisting of the opode, which itself contains 3 of the
11 address bits, followed by another byte containing the Subroutines should end with a RET instruction, which
low 8 bits of the destination address. When the instruc- returns execution to the instruction following the
tion is executed, these 11 bits are simply substituted for CALL.
the low 11 bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same 2K RETI is used to return from an interrupt service rou-
block as the instruction following the AJMP. tine. The only difference between RET and RETI is
that RETI tells the interrupt control system that the
In all eases the programmer specifies the de&nation interrupt in progress is done. If there is no interrupt in
address to the assembler in the same way as a label or progress at the time RETI is executed, then the RETI
as a id-bit constant. The assembler will put the destina- is functionally identical to RBT.
tion address into the eormct format for the given in-
struction. If the format required by the instruction will Table 9 shows the list of conditional jumps available to
not support the distance to the specified destination rtd- the MCS-51 user. All of these jumps specify the desti-
dresa, a “Destination out of range” message is written nation address by the relative ot%et meth~ and so are
into the Lkt fde. lindted to a jump distance of – 128 to + 127 bytes from
the instruction following the conditional jump instruc-
The JMP @A+ DPTR instruction supports ease tion. Important to note, however, the user speeifies to
jumps. The destination address is computed at exeeu- the assembler the actual destination address the same
tion time as the sum of the lti-bit DPTR register and way as the other jump as a label or a id-bit constant.

1-16
i~. MCS@-51 ARCHITECTURAL OVERVIEW

Table 9. Conditions Jumps in MCS@-51 Devioes

Addressing Modes Execution
Mnemonic Operation
Dir ind Rag imm Time (ps)
JZ rei Jump if A = O Accumulator oniy 2
JNZ rel Jumpif A+O Accumulator oniy 2
DJNZ <byte> ,rel Deorement and jump if not zero x x 2
CJNE A, <byte> ,rei Jumpif A # <byte> x x 2
CJNE <byte> ,#data,rei Jump if <byte> # #data x x 2

There is no Zero bit in the PSW. The JZ and JNZ

instructions test the Accumulator data for thst ccmdi- @
Mes-51
tion.

‘4-J
HIAOS
ORCHMOS

The DJNZ instruction (Dezrement and Jump if Not STAL7.

OUART&&~WA; > Cl
Zero) is for loop control. To execute a loop N times, RrsONAmR 57.
load a counter byte with N and tersninate the loop with
S-TAL1
a DJNZ to the beginning of the loop, as shown below
Vss
for N = 10:
=
270251-11
MOV com~#lo
LOOP: (begin loop) Figure 13. Using the On-Chip Oeciilator
●

(;d Imp) w’%

-4-I
HMOS
DJNZ COUNTER,LOOP ORCnuos
(continue) SmLS

The CJNE instruction (Compare and Jump if Not

Equal) can also be used for loop control as in Figure 12. CLOCK STAL1
SIGNAL
Two bytes are specified in the operand field of the in-
struction. The jump is executed only if the two bytes =
are not equal. In the example of Figure 12, the two 270251-12
bytes were the data in R1 and the constant 2AH. The A. HMOS or CHMOS
initial data in R1 was 2EH. Every time the loop was
executed, R 1 was decresnertted, and the looping was to
Mcs”-51
continue until the R1 &ta reached 2AH.

-i-l
HMOS
ONLY
EilSRNAL
Another application of this instruction is in “great= CLOCK STAL2

than, less than” comparisons. The two bytes in the op

erand field are taken as unsigned integers. If the first is
STAL1
less than the second, then the Carry bit is set (l). If the
first is greater than or equal to the second, then the Vss

Carry bit is cleared. =

270251-13
B. HMOS Only

u
CPU TIMING
Mm%!
CHMOS
All MCS-51 microcontrollers have an on-chip oscillator ONLY
which can be used if desired as the clock source for the (w) STU.2
CPU. To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTAL1 and XTAL2 WRNAL
pins of the microcontroller, and capacitors to ground as nut
L=
shown in Figure 13. Vss
s
270251-14
C. CHMOS only

Figure 14. Using an Externai Ciock

1-17
i~. MCS’5’-51 ARCHITECTURAL OVERVIEW

Examples of how to drive the clock with an external Machine Cycles

oscillator are shown in Figure 14. Note that in the
HMOS devices (S051, etc.) the signal at the XTAL2 pin A machine cycle consists of a sequence of 6 statea,
actually drives the internal clock generator. In the numbered S1 through S6. Each state time lasts for two
CHMOS devices (SOC5lBH, ete.) the signsl at the oscillator periods. Thus a machine cycle takes 12 Oscil-
XTAL1 pin drives the internal clock generator. If only lator periods or 1 ps if the oscillator frequency is
one pin is going to be driven with the external oscillator 12 MHz.
signal, make sure it is the right pin.
Each state is divided into a Phase 1 half and a Phase 2
The internal clock generator defmea the sequence of half. Figure 15 shows the fetch/execute sequences in
states that make up the MCS-51 machine cycle.

(%L)
51 52 as se
Plm Prps PIP2 PIPS
as
PIPs
.%
Pips PIPS
s 52
Pips
as
PIP2 mm L
S4.SE

P2 PIPS
as
Pips
51

I I
ALE
1 J
!
I I
I
I - nw OPCODE. READ NEXT

:,,-4ir-NEmo”oOEAGA
~ I
(A)t-byts, l-eydshs2mdh, e.g., WC A.
I
I
I
I I I
r READ OPCODE.
I
I
I
I I
(B)2-byte. 1* lm@s2b. *.e.. Aoo A,mdma i I
I I 1
I
READ NEXT OPCODE AGAIN. ~
OPCOOE (DISCARD).
I I

------- [
I
1 , jI-----
------- S1 as es e4ae Seslases e4aEes
------
I I I
[c) l-byle,2qs4C imhlesm ●.s., INC DPTR.
I I
I I RSAO NEXT OPCODE AGAIN.
— READ OPCOOE
I (MWX). NO
READ NEXT NO FETCH.
I OPCOOE (OISCARD) , ‘1=”” I
~NOALE
I ? 1~ 1
------ ,,; -----
sla2a2s4] as eel S11S21S2]24SSSS
----- - .-----
AOOR DATA I
I
[0) MOW (l-, S-c@@ I
J
I ACCESS EXTERNAL MEMORY I

270251-15

Figure 15. Stete Sequences in MCS@’-5l Devices

1-18
in~e MCS@-51 ARCHITECTURAL OVERVIEW

states and phases for various kinds of instructions. Nor- The fetch/execute sequences are the same whether the
malIy two program fetches sre generated during each Program Memory is internal or external to the chip.
machine cycle, even if the instruction being executed Execution times do not depend on whether the Pro-
doesn’t require it. If the instruction being executed gram Memory is internal or external.
doesn’t need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not incre- Figure 16 shows the signals and timing involved in pro-
mented. gram fetches when the Program Memory is external. If
Program Memo~xternsl, then the Program Memo-
Execution of a one-cycle instruction (Figure 15A and ry read strobe PSEN is normally activated twice per
B) begins during State 1 of the machine cycle when the machine cycle, as shown in Figure 16(A).
opcode is latched into the Instruction Register. A sec-
ond fetch occurs during S4 of the same machine cycle, If an access to external Data Memory occurs, as shown
Execution is complete at the end of State 6 of this ms- in Figure 16(B), two PSENS are skippe$ because the
chine cycle. address and data bus are being used for the Data Mem-
ory access.
The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the see Note that a Data Memory bus cycle takes twice as
ond cycle of a MOVX instruction. This is the ordy time much time as a Program Memory bus cycle. Figure 16
program fetches are skipped. The fetch/execute se- shows the relative timing of the addresses being emitted
quence for MOVX instructions is shown in Figure at Ports Oand 2, and of ALE and PSEN. ALE is used
15(D). to latch the low address bvte from PO into the address
latch.

ALE
r ONE MACHINE CVCLS

sl[a21s21s41aslss

I I
T
ONE MACIUNE CYCLE

SIIS21S21S41SE

I 1
1126

!
,

-N ~ I I I
1
I L r I 1 I 1 I
1 I
1
I
1 I I I
ro I 1 1
1 I 1 I WITH%)UT A
1 1 I I I MOVX.
P2 PCH OUTX PCH OUT x [ PCH OUT x’ I PCNOUT
1

I I 1

t~::$m t5i:F ty;LL&T &T

G:v:m’lxm:m

) I I ,

I I 1
-N ~ 1 1 1 I
I 1
I 1
E
I (B)
I I I
I I I WITH A
I I I 1 MOVX.
P2PcHc@( ! PCHOUT x! OPH OUT OR P2 OUT x: PCH OUT )( PWOUT

t P&m&T iAC:O&UT

2702!31 -16

Figure 16. Bus Cycles in MCS@-51 Oevices Extilng irom External Program Memory

1-19
i~e MCS@-51 ARCHITECTURAL OVERVIEW

When the CPU is executing from intemrd Program natned IE (Interrupt Enable). This register also con-
Memory, ~ is not activated, and program address- tains a global disable bit, which can be cleared to dis-
es are not emitted. However, ALE continues to be acti- able all interrupts at once. Figure 17 shows the IE reg-
vated twice per machine cycle and so is available as a ister for the 8051.
clock output signal. Note, however, that one ALE is
skipprd during the execution of the MOVX instmction.
INTERRUPT PRIORITIES

Each interrupt source can also be individually pro-

Interrupt Structure
~ed t? one of two priority levels by setting or

The 8051 core provides 5 interrupt sources 2 external clearing a blt m the SFR named 1P (Interrupt Priority).
interrupts, 2 timer interrupts, and the serial pat inter- Figure 18 shows the 1P register in the 8051.
rupt. What follows is an overview of the interrupt
structure for the t3051.Other MCS-51 devices have ad- A low-priority interrupt w be interrupted bya high-
ditional interrupt sources and vectors as shown in Ta- priority interrupt, but not by another low-priority inter-
ble 1. Refer to the appropriate chapters on other devic- IUpt. A high-priority interrupt can’t beinterrupted by
es for further information on their interrupts. any other interrupt source.

If two interrupt rquests of different priority levels are

INTERRUPT ENABLES received simultaneously, the request of Klgher priority
level is serviced. If interrupt requests of the same prior-
Each of the interrupt sources can be individually en- itylevel are received simultaneously, an interred polling
abled or disabled by setting or clearing a bit in the SFR sequence determines which request is serviced. Thus
within each priority level there is a second priority
structure determined by the polling sequence.
(MSB) (LSB)
EAl — I—IESIETI IEXIIETOIEXO
Figure 19 shows, for the 8051, how the IE and IP regie-
Enablebk = 1 enablesb interqf. ters and the polling sequence work to determine which
Ensblebk =odieabksit
if any inttipt Wiilbe-serviced.
symbol Pmiti9n Function
EA IE.7 d&bles all intempts. If EA = O, no
interruptW be acknowledged.If EA (MSB) (LSB)
= 1, each intenupt source is —— — IPSIPTI IPXIIPTOIPXO
itiiuslfy enabled or disebled by
Prforifybit=lsssign shighpriwity.
settingw clearingite eneblebit.
— Prioritytit = OassignslowprWity.
IE.6 reserved”
— IE.5 reewed” symbol POeitiQn Functfon
ES IE.4 Ser!41Pwf Intemuptenabletin. — IP.7 resewed”
ETl IE.3 TImw 1 OverflowInterrupteneblebit IP.6 rewed”
Exl IE.2 Gtsmsl Intenupf1 enable bit — IP.5 reserved-
ETo IE.1 TimerOflwrffw Interruptenabfebm Ps IP.4 Serial Porfinterruptp+eritybii
Exo IE.O EstemslIntenuptOenablebit PTl IP.3 Timer 1 intenuptpfbrity bfi.
“Thesereservedbiteare used in otherMCS-51devices. Pxl IP2 ExternalIntenupt1 ptirity bit.
PTo lP.1 limsr Ointerruptpriorftybii
Figure 17. IE (Interrupt Enable) Pxo fP.o ExternalIntellupto priorityMt.
Register in the 8051 “These resewedtits are usedin other MCB-51devices.

Figure 18. 1P (Interrupt Priority)

Register in the 8051

1-20
intd. M~@-51 ARCHITEC~RAL OVERVIEW

HIGH PRIORllY
INTERRUPT
IE REGISTER 1P REGISTER

o b
1.
+h-O+io
1 I
I

e b
INTERRUPT
TFo /&+.
‘POLUNG
1 SEQUENCE

o ●
-&-J.
1 I
:
0 b
7FI J&o
I
I
: 0 ➤ v
RI
J+
n
I
A \
~ LyPwPNrr

270251-17
.-
Figure 19.8051 Intermpt control system

In operatiom all the interrupt tlags are latched into the pleted in lms time than it takes other architectures to
interrupt control system during State 5 of every ma- commence them.
chine cycle. The samples are polled during the follow-
ing machine cycle- If the flag for an enabled interrupt is
found to be set (l), the interrupt system generates an SIMULATING A THIRD PRIORITV LEVEL IN
SOFIWARE
LCALL to the appropriate location in Program Memo-
ry, unless some other condition blocks the interrupt. Some applications require more than the two priority
Several conditions can block an interrupt, among them levels that are provided by on-chip hardware in
that an interrupt of equal or higher priority level is MCS-51 devices. In these cases, relatively simple soft-
already in progress. ware can be written to produce the same effect as a
thkd priority level.
The hardware-generated LCALL csusea the contents of
the Program Counter to be pushed onto the stack, and Firat, interrupts that are to have higher priority than 1
reloads the PC with the beginning address of the service are ssaigned to priority 1 in the 1P (Interrupt Priority)
routine. As previously noted (Rgare 3), the service rou- register. The service routines for priority 1 interrupts
tine for each interrupt begins at a fixed location. that are supposed to be interruptible by “priority 2“
interrupts are written to include the following code
Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Hav- PUSH IE
ing only the PC be automatically saved allows the pro- MOV IE, #MASK
grammer to decide how much time to spend saving CALL LABEL
which other registers. This enhances the interrupt re- ● ******

sponse time, albdt at the expense of increasing the pro- (execute service routine)
-er’s bu~en of responsibility. As a result, many ● ******

snterrupt functions that are typical in control applics- POP IE

tions-togghmg a port pim for example, or reloading a RET
timer, or unloading a serial but%r-can otten be mm- LABEL RETI

1-21
 MCS@I-51 ARCHITECTURAL OVERVIEW

As soon as any priority 1 interrupt is acknowledged, ADDITIONAL REFERENCES

the IE (Interrupt Enable) register is m-defined so as to
disable all but “priority 2“ interrupts. Then, a CALL to The following application notes are found in the Em-
LAEEL exeoutes the RETI instruction, which clears bedded Chstml AppIicatwns handbook. (Order Num-
the priority 1 interrupt-in-program tlip-flop. At this ber: 270648)
point SIly priority 1 interrupt that is enabled can be
1. AP-69 “An Introductionto the Intel MCS@-5I Sin.
seticed, but Ody “priority’ 2“ illtCSTUptSare enabled. gle-Chip Microcomputer Family”
POPping IE restores the original enable byte. Tberr a 2. AP-70 “Using the Intel MCW-51 Boolean Process-
normal RET (rather than another RETI) is used to ing Capabtities”
terminate the service routine. The additional software
adds 10 ps (at 12 MHz) to priority 1 interrupts.

1-22
MCS@51Programmer’s 2
Guide and Instruction Set
MCWI51 PROGRAMMER’S CONTENTS PAGE
GUIDE AND MEMORYORGANIZATION........................2-3
INSTRUCTION SET PROGRAM MEMORY .................................2-3
Data Memory...............................................2-4
INDIRECT ADDRESS AREA,...........,.........2-6

DIRECT AND INDIRECT ADDRESS

AREA ......................................................2-6

SPECIAL FUNCTION REGISTERS............2-8

WHAT DO THE SFRS CONTAIN JUST
AFTER POWER-ON OR A RESET,......,,2-9

SFR MEMORY MAP .................................2-lo

PSW: PROGRAM STATUS WORD. BIT
ADDRESSABLE ...................................2-1 1

PCON: POWER CONTROL REGISTER.

NOT BIT ADDRESSABLE .....,..,........,..2-1 1

INTERRUPTS ............................................2-1 2

IE: INTERRUPT ENABLE REGISTER.

BIT ADDRESSABLE ............................2-12

ASSIGNING HIGHER PRIORITY TO

ONE OR MORE INTERRUPTS ..,.........,2-13
PRIORITY WITHIN LEVEL .......................2-13
1P:INTERRUPT PRIORITY REGISTER.
BIT ADDRESSABLE ..,..........,.,,...........2-13

TCON: TIMEFVCOUNTER CONTROL

REGISTER. BIT ADDRESSABLE ......,.2-14

TMOD: TIMEWCOUNTER MODE

CONTROL REGISTER. NOT BIT
ADDRESSABLE ...................................2-14
TIMER SET-UP .........................................2-1 5

TIMEFVCOUNTER
O ,..............,..,........,.,..2-15
TIMER/COUNTER 1..................................2-16

T2CON: TIMEWCOUNTER 2 CONTROL

REGISTER. BIT ADDRESSABLE ........2-17

TIMEWCOUNTER 2 SET-UP ...................2-18

SCON: SERIAL PORT CONTROL

REGISTER. BIT ADDRESSABLE ....,...2-19

2-1
CONTENTS PAGE CONTENTS PAGE
SERIAL PORT SET-UP............................ 2-19 USING TIMEFUCOUNTER2 TO
GENERATE BAUD RATES ..................2-20
GENERATING BAUD RATES ..................2-1 9
Serial Port in Mode O................................ 2-19 ‘ER’AL ‘ORT ‘N ‘ODE 2 .“.”””-””-””””.”..”;-”2-20
Serial Port in Mode 1 ................................ 2-19 SERIAL PORT IN MODE 3 ...................O. 2-20

USING TIMER/COUNTER 1 TO M=&51 INSTRUCTION SET .................2-21

GENERATE BAUD RATES ..................2-20
INSTRUCTION DEFINITIONS ................. 2-28

2-2
i~. MCS@-51
PROGRAMMER’S
GUIDEAND INSTRUCTION SET

The informationpreaentedin this chapter is collectedfrom the MCW-51 ArchitecturalOverviewand the Hardware
Descriptionof the 8051,8052and 80C51chapters of this book. The material has been selected and rearrangedto
form a quick and convenientreferencefor the programmersof the MCS-51.This guidepertains specificallyto the
8051,8052and 80C51.

MEMORY ORGANIZATION

PROGRAM MEMORY
The 8051 has separateaddressspacesfor Program Memoryand Data Memory.The Program Memorycan be up to
64K bytes long.The lower4K (8K for the 8052)may resideon-chip.

Figure 1 showsa map of the 8051program memory,and Figure 2 showsa map of the 8052program memory.

m. FFFF

WK
BwEe
exrmful.
64K
— OR evree
EXTERNAL

10M

Omo
270249-1

Figure1. The 8051 Program Memory

2-3
 MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

S4K
BWEB

270249-2

Data Memory:
The 8051can address up to 64K bytes of Data Memoryexternal to the chip. The “MOW? instmetion is used to
access the external data memory.(Refer to the MCS-51Instmction Set, in this chapter, for detailed deaeriptionof
instructions).
The 8051has 128bytesof on-chipRAM (256bytesin the 8052)plus a numberof SpecialFunctionRegisters(SFRS).
The lower 128byteaof 3Uh4 can be accessedeither by direct addressing(MOVdata addr) or by indirect addressing
(MOV @Ri).Figure 3 showsthe 8051and the 8052Data Memoryorganization.

2-4
in~e MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

OFFF

“F
64K
Bwea

9—————IDIRECT
&
INomECT
Aoon~

270249-3

Figure 3a. The 8051 Data Memory

I
FFFl
m’rEmAL

IWIRECT

6 ADORESSING
ONLY
em To FFn

w’
64K
ema m-me
OmE(n ExnmNAL
om.Y
m
n=
Olmcl &
INOIRECT
AwnEaslNG

00.
270249-4
Figure 3b. The 8052 Date Memory

2-5
i~. MCS@-51PROGRAMMER’S GUIDE AND INSTRUCTION SET

INDIRECT ADDRESS AREA:

Note that in Figure 3b the SFRSand the indirect address RAM have the same addreasea(80H-OFFH).Neverthe-
less, they are two separate areas and are amesaed in two diiferentways.

For examplethe instruction

MOV 8oH,#o&lH

writesOAAHto Port Owhichis one of the SFRSand the instruction

MOV Rr),#80H

MOV @RO,#OBBH

writesOBBHin location 80H of the data RAM. Thus, after executionof both of the aboveinstructionsPort Owill
contain OAAHand location 80 of the MM will contain OBBH.

Note that the stack operationsare examplesof indirect addressing,so the upper 128bytesof data MM are available
as stack space in those deviceswhich implement 256 bytesof internal RAM.

DIRECT AND INDIRECT ADDRESS AREA:

The 128bytesof W whichcan be ameasedby both direct and indirect addressingcan be dividedinto 3 segments
as listedbelow and shownin Figure 4.

1. Registar Banks O-3:LocationsOthrough lFH (32 bytes).ASM-51and the deviceafter reset defaultto register
bank O. To use the other register banks the user must select them in the software (refer to the MCS-51Micro
AssemblerUser’s Guide). Each register bank contains 8 one-byteregisters, Othrough 7.

Resetinitiahzesthe StackPointerto location 07H and it is incrementedonceto start from location08Hwhichis the
first register(RO) of the secondregister bank. Thus, in order to use more than one register bank, the SP shouldbe
intiaked to a different locationof the RAM where it is not used for data storage (ie, higher part of the WNW).

2. Bit AddressableArex 16bytes have been assignedfor this segment,20H-2FH.Each one of the 128bits of this
wgmmt can be directly addressed(0-7FH).
The bits can be referred to in two ways both of which are acaptable by the ASM-51.One way is to refer to their
address ie. Oto 7FH. The other way is with referenceto bytes20H to 2FH. Thus,bits O-7 can alsobe referred to
as bits 20.0-20.7, and bits 8-FH are the same as 21.0-21.7 and so on.

Each of the 16bytes in this segmentcan also be addressedas a byte.

3. Scratch Pad Arex Bytes30H through 7FH are availableto the user as &ta MM. However,if the stack pointex
has been initializedto this arm enoughnumber of bytes shouldbe left aside to prevent 5P data destruction.

2-6
in~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

Figure4 shows the difYerentsegmentsof the on-chipRAM.

sol
SCRATCH

Pm

ARSA
4SI 14P
1.7

I 3F
301
2s . . . 7F 2P
AaaRLLs
20 0... 27 SSGMENT
18 3 IF

10 2 1? RSGISIER

0s 1 OF BANKS

00 0 07

270249-5

Figure 4.128 Bytes of RAM Direct and Indirect Addreeesble

2-7
in~. MCS@-51PROGRAMMER’S GUIDE AND INSTRIJCTlON SET

SPECIAL FUNCTION REGISTERS:

Table 1 containsa list of all the SFRs end their addressee.

ComparingTable 1and Figure 5 showsthat all of the SFRs that are byteand bit addressableare locatedon the first
col~n of-the diagram in Figure 5.
Table 1

Symbol Name Address

*ACC Accumulator OEOH
*B B Register OFOH
“Psw ProgramStatusWord ODOH
SP Stack Pointer 81H
DPTR Data Pointer2 Bytes
DPL LowByte 82H
DPH HighByte 83H
*PO Porto 80H
*P1 Port1 90H
●P2 Port2 OAOH
*P3 Port3 OBOH
*IP InterruptPriorityControl OB8H
*IE InterruptEnable Control OA8H
TMOD Timer/Counter Mode Control 89H
“TCON Timer/Counter Control 88H
*+ T2CON Timer/Counter 2 Control OC8H
THO Timer/Counter O HighByte 8CH
TLO Timer/Counter O LowByte 8AH
TH1 Timer/Counter 1 HighByte 8DH
TL1 Timer/Counter 1 LowByte 8BH
+TH2 Timer/Counter 2 HighByte OCDH
+TL2 Timer/Counter 2 LowByte OCCH
+ RCAP2H T/C 2 Capture Reg. HighByte OCBH
+ RCAP2L T/C 2 Capture Reg. LowByte OCAH
●SCON SerialControl 98H
SBUF Serial Data Buffer 99H
PCON PowerControl 87H
= Bitaddreaaable
+ = 8052 only

2-8
int& M~@.51 PROGRAMMERS GUIDE AND INSTRUCTION SET

WHAT DO THE SFRS CONTAIN JUST A~ER POWER-ON OR A RESET?

Table 2 lists the contents of each SFR after power-onor a hardware reset.

Table 2. Conte ) of the SFRS after reset

Register Value in Binary
“ACC 00000000
“B 00000000
*PSW 00000000
SP 00000111
DPTR
DPH 00000000
DPL 00000000
*PO 11111111
*P1 11111111
*P2 11111111
*P3 11111111
*IP 8051 XXXOOOOO,
8052 XXOOOOOO
*IE 8051 OXXOOOOO,
8052 OXOOOOOO
TMOD 00000000
●TCON 00000000
● +T2CON 00000000
THO 00000000
TLO 00000000
TH1 00000000
TL1 00000000
+TH2 00000000
+TL2 00000000
+RCAP2H 00000000
+RCAP2L 00000000
●SCON 00000000
SBUF Indeterminate
PCON HMOS OXXXXXXX
CHMOS OXXXOOOO
= Undefined
= BitAddreassble
+ = 8052only

2-9
intd. M(3%51 PROGRAMMERS GUIDE AND INSTRUCTION SET

SFR MEMORY MAP

8 Bytes
F8 FF
FO B F7
E8 EF
EO ACC E7
D8 DF
DO Psw D7
C8 T2CON RCAP2L RCAP2H TL2 TH2 CF
co C7
B8 1P BF
BO P3 B7
A8 IE AF
AO P2 A7
98 SCON SBUF 9F
90 PI 97
88 TCON TMOD TLO TL1 THO TH1 8F
80 Po SP DPL DPH PCON 87
-r Figure 5
Bit
Addressable

2-1o
i~. M=@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

Those SFRsthat havetheir bits assignedfor variousfunctionsare listedin this section.A briefdescriptionof each bit
is providedfor quick reference.For more detailed informationrefer to the Architecture Chapter of this book.

PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.

CY AC FO RS1 RSO Ov I — I P
CY PSW.7 Carry Flag.
AC PSW.6 AuxiliaryCarry Flag,
FO PSW.5 Flag Oavailableto the user for generalpurpose.
Rsl PSW.4 RegisterBank selector bit 1 (SEE NOTE 1).
Rso PSW.3 RegisterBank selector bit O(SEE NOTE 1).
Ov PSW.2 OverflowFlag.
— Psw.1 User definableflag.
P Psw.o Parity flag. Set/cleared by herdwareeach instructioncycleto indicateerrodd/werr number of
‘1’bita in the accumulator.
NOTE:
1. Thevaluepresented
byRSOandRS1selectsthecorresponding
registerbank.

RS1 RSO Register Bank Address

o 0 0 OOH-07H
o 1 1 08H-OFH
1 0 2 10H-17H
1 1 3 18H-l FH

PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.

SMOD I — I — I — GF1 GFO PD IDL

SMOD Double baud rate bit. If Timer 1 is used to generatebaud rate end SMOD = 1, the baud rate is doubled
when the SeriatPort is used in modes 1, 2, or 3.
— Not implemented,reservedfor future w.*
— Not implemented,reservedfor future w.*
— Not implemented,reservedfor future use.”
GF1 General purposeflag bit.
GFO General purposeflag bit.
PD Power Down bit. Setting this bit activates Power Down operation in the 80C51BH.(Availableonly in
CHMOS).
IDL Idle Modebit. %.ttittgthis bit activatesIdle Modeoperationin the 80C51BH.(Availableonlyin CHMOS).

If 1sare writtento PD andIDL at thesametimejPD tske$precedence,

●Usersoftwareshouldnotwrite1s to reservedbita.Thaeebitsmaybe usedin futureMCS-51productsto invokenew
featurea.In thatcase,theresetor inactivevalueofthe newbitwillbeO,anditsectivevaluewillbe 1.

2-11
irltele McS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

INTERRUPTS:
In order to use any of the interrupts in the MCS-51,the followingthree steps must be taken.
1. 3et the EA (enableall) bit in the IE register to 1.
2. Set the correspondingindividualinterrupt enablebit in the IE register to 1.
3. Beginthe interruptserviceroutineat the em-respondingVector Addressof that interrupt. SeeTablebelow.

I Interrupt
Souroe I Vector
Address I
IEO OO03H
TFO OOOBH
IE1 O013H
TF1 OOIBH
RI &Tl O023H
TF2 & EXF2 O02BH

In addition,for extemaf interrupts,pins~ and INT1 (P3.2and P3.3)must be set to 1,and dependingon whether
the intermpt is to be level or transitionactivated, bits ITOor IT1 in the TCON register may needto be set to 1.
ITx = Olevel activated

ITx = 1 transitionactivated

IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.

If the bit is O,the correspondinginterrupt is disabled.If the bit is 1,the correspondinginterruptis enabled.
EA — ET2 ES ETl EX1 ETo EXO

EA IE.7 Disablesall interrupts.IfEA = O,no interrupt willbe acknowledged.IfEA = 1,each interrupt

source is individuallyenabledor disabledby setting or elearing its enablebit.
— IE.6 Not implemented,reservedfor future use.*
ET2 IE.5 Enable or disablethe Timer 2 overflowor capture interrupt (8052only).
Es IE.4 Enable or disablethe serial port interrupt.
ET1 IE.3 Enable or disablethe Timer 1 overtlowinterrupt.
EX1 IE.2 Enable or disableExternal Interrupt 1.
ETO IE.1 Enable or disablethe Timer Ooverflowinterrupt.
EXO IE.O Enable or disableExternal Interrupt O.
*Usersoftwareshould not write 1sto reserved bits. These bits may be used in futore MCS-51preducts to invoke
new features. In that case, the reset or inactivevalue of the new bit wilt be O,and its active valuewillbe 1.

2-12
 M=@-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:

In order to assign higher priority to an interrupt the correspondingbit in the 1Pregister must be set to 1.

Rememberthat whilean interrupt servieeis in progress,it cannot be interrupted by a lower or same levelinterrupt.

PRIORITV WITHIN LEVEL:

Priority within level is only to resolvesimultaneousrequestsof the same priority level.

From high to low, interrupt sourcesare listed below:

IEO
TFo
IE1
TF1
RI or TI
TF2 or EXF2

1P:INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.

If the bit is O,the correspondinginterrupt has a lowerpriority and if the bit is 1 the correspondinginterrupt has a
higher priority.
— — PT2 Ps PTl Pxl PTO Pxo
I
— 1P.7 Not irnplementi reservedfor future use.*
— 1P.6 Not implemented,reservedfor future use.*
PT2 1P. 5 Detines the Timer 2 interrupt priority level(8052only).
Ps 1P.4 Definesthe SerialPort interrupt priority level.
Pm 1P. 3 Definesthe Timer 1 interrupt priority level.
Pxl 1P.2 Defines External Interrupt 1 priority lexwl.
PTo 1P. 1 Defines the Timer Ointerrupt priority level.
Pxo 1P.O Definesthe External Interrupt Opriority level.
*Usersoftware should not write 1s to reserved bits. Theaebits may be used in fiture MCS-51products to invoke
new features. In that case, the reset or inactive valueof the new bit will be O,and its active value willbe 1.

2-13
intel. M=@-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

TCON: TIMER/COUNTER CONTROL REGISTER. BIT ADDRESSABLE.

TFl TR1 TFO TRO IE1 IT1 IEO ITO

TFl TCON. 7 Timer 1 overflowflag. Setby hardware when the Timer/Counter 1 overtlows.Clearedby hsrd-
ware as processorvectorsto the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/ckared by softwareto turn Timer/Counter 1 ON/OFF.
TFO TCON. 5 Timer Ooverflowflag. Setby hardware when the Timer/Counter Ooverflows.Clearedby hsrd-
ware as proceasorvectorsto the seMce routine.
TRO TCON.4 TixnerOrun control bit. Set/cleared by software to turn Timer/Counter OON/OFF.
IEI TCON. 3 External Interrupt 1 edge flag. Set by hardware when Extemsf Interrupt edge is detected.
Clearedby hardware wheninterrupt is proeesaed.
IT1 TCON.2 Interrupt 1 type control bit. Set/cleared by sotlwsre to specifyfalling edgeflowleveltriggered
External Interrupt.
IEO TCON. 1 External Interrupt Oedgeflag.Set by hardware when ExternalInterrupt edgedeteeted.Cleared
by hardware when interrupt is proeeased.
ITO TCGN.O Interrupt Otype control bit. Set/cleared by sotlwsre to specifyfsfling edge/low leveltriggered
External Interrupt.

TMOD: TIMER/COUNTER MODE CONTROL REGISTER. NOT BIT

ADDRESSABLE.

TIMER 1 TIMER O
GATE WhenTRx (in TCON) is set rmdGATE = 1,TIMEIUCOUNTERxwillrun only whileINTx pinis high
(hardware ecmtrol).When GATE = O,TWIER./C0UNTERx will run only while TRx = 1 (software
control).
CiT’ Timer or Counter seleetor. Ckred for Timer operation(input from internal system clock).Set for Coun-
ter operation(input from Tx input pin).
Ml Mode selectorbit. (NOTE 1)
MO Mode selectorbit. (NOTE 1)
NOTE1:

Ml MO Operating Mode
o 00 13-bit Timer (MCSA8 compatible)
o 1 1 16-bit Timer/Counter
1 02 8-bit Auto-ReloadTimer/Counter
1 1 3 mimer o).TLois an a-bitTimer/Counter controlledby the standard Timer o
controlbite,THOisan 8-bitTimer and is controlledby Timer 1 controlbits.
1 1 3 (Timer 1) Timer/Counter 1 stopped.

2-14
intel. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

TIMER SET-UP
Tables 3 through 6 give some valuesfor TMOD whicheen be used to setup Timer Oin differentmodes.

It is assumedthat only one timer is beingused at a time. If it is desiredto run TimersOend 1simukaneoudy,in snY
mod% the valuein TMOD for Timer Omust be ORed with the value shownfor Timer 1 (Tables5 and 6).
For example,ifit is desired to run Timer Oin mode1GATE (externalcontrol),and Timer 1in mode2 COUNTER,
then the value that must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6).
Moreover.it is assumedthat the user, at this mint, is not ready to turn the timers on and will do that at a different
point in he programby setting bit T-Rx(in TCON)to 1. -

TIMER/COUNTER O

As a Timer:

m
Table 3

MODE

o
““N
13-bit Timer OOH 08H
1 16-bit Timer OIH 09H
2 8-bit Auto-Reload 02H OAH
3 two 6-bit Timera 03H OBH

As a Counter:
Table 4

TMOD
COUNTER 0 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
o 13-bitTimer 04H OCH
1 16-bitTimer 05H ODH
2 8-bit Auto-Reload 06H OEH
3 one8-bitCounter 07H OFH

NOTES
1. TheTimeristurnedON/OFF by eettinglclearing
bitTROinthesotlwere.
2. The Timeria turnedON/OFF by the 1 to Otransition
on ~ (P3.2)whenTRO= 1
(herdwarecontrol).

2-15
intd. M@@.51 PROGRAMMERS GUIDE AND INSTRUCTION SET

TIMER/COUNTER 1

As a Time~
Table 5

TMOD
TIMER 1 INTERNAL EXTERNAL
MODE
FUNCTION CONTROL CONTROL
(NOTE 1) (NOTE 2)
o 13-bitTimer OOH 80H
1 16-bitTimer 10H 90H
2 8-bit Auto-Reload 20H AOH
3 does notrun 30H BOH

As a Counter:
Table 6

o 13-bitTimer 40H WH
1 16-bitTimer 50H DOH
2 8-bitAuto-Reload 60H EOH
3 not available — —

NOTES
1.TheTimeristurnedON/OFFbysetting/claaring bitTR1 inthesoftware.
2. The Timeris turnedON/OFF by the 1 to O transition
on ~ (P3.3)whenTR1 = 1
(hardwerecontrol).

2-16
i@. McS@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

T2CON: TIMER/COUNTER 2 CONTROL REGISTER. BIT ADDRESSABLE

8052 Only
TF2 EXF2 RCLK TCLK EXEN2 TR2 Cln cP/m
TP2 T2CON.7 Timer 2 overfiowtlag set by hardware and cleared by software. TP2 cannotbe set when
either RCLK = 1 or CLK = 1
EXP2 T2CON.6 Timer 2 external fig set wheneithera c.mtureor reload is causedbv a nemtive transition on
T2EX,and EXEN2-= 1.WhenTimer2 ktermpt is enabl~ EXF2-= 1‘%11causethe CPU
to vector to the Timer 2 interrupt routine.EXF2 must be cleared by software
RCLK T2C0N. 5 Receiveclock tlag. When set, causesthe Serial Port to use Timer 2 overtlowpulses for its
receiveclockin modes 1& 3. RCLK = OcausesTimer 1 overflowto be used for the receive
clock.
TLCK T2C0N. 4 Transmit clock flag. When set, causesthe Serial Port to use Timer 2 overtlowpulses for its
transmit clock in modes 1 & 3. TCLK = O causes Timer 1 overflowsto be used for the
transmit clcck.
EXEN2 T2C0N. 3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = OcauaeaTimer 2 to ignoreeventsat T2EX.
TR2 T2CON.2 SoftwareSTART/STOP control for Timer 2. A logic 1 starts the Timer.
CRT T2CON. 1 Timer or Counter select.
O = Internal Timer. 1 = ExternalEventCounter (fallingedgetriggered).
cP/Rm T2CON.o Capture/Reload flag. Whereset, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, AuteReloads will occur either with Timer 2 overflowsor
negativetransitions at TZEXwhenEXEN2 = 1. When either RCLK = 1 or TCLK = 1,
this bit is ignoredand the Timer is forcedto Auto-Reloadon Timer 2 overflow.

2-17
in~. M~Q.51 PROGRAMMERS GUIDE AND INSTRUCTION SET

TIMER/COUNTER 2 SET-UP
Ex~t for the baud rate mnerstor mode. the values aiven for T2CONdo not include the settine of the TR2 bit.
ller~fore, bit TR2 must ~ set, separately,to turn th~Timer on.

As a Timer:
Table 7

T2CON

MODE INTERNAL EXTERNAL

CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bitAuto-Reload OOH 08H
16-bitCapture OIH 09H
BAUD rate generatorreceive&
transmitsame baudrate 34H 36H
receive only 24H 26H
transmitonlv 14H 16H

4s a Counter:
Table 8

I TMOD I

MODE INTERNAL EXTERNAL

CONTROL CONTROL
(NOTE 1) (NOTE 2)
16-bitAuto-Reload 02H OAH
16-bitCapture 03H OBH

NOTES
1. Capture/Reload
occursonlyonTimer/Counter
overflow.
2. Capture/Reloadoccurson Timer/Counter
overflowand a 1 to O transition
on T2EX
(P1.1)pinexceptwhenTimer2 isusedinthebaudrategeneratingmode.

2-18
i~e McS@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE.

TB8 TI RI
I SMO SM1 SM2 REN RB8
SMO SCON.7 Serial Port modespecifier.(NOTE 1).
SM1 SCON.6 Serial Port modespecifier.(NOTE 1).
SM2 SCON.5 Enablesthe multiproceasor eomrnunieationfeaturein modes2 & 3. In mode2 or 3, if SM2is set
to 1 then RI will not be activated if the -veal 9th data bit (RB8)is O.In mode 1,ifSM2 = 1
then RI will not be activated if a valid stop bit was not received.In modeO,SM2 shouldbe O.
(SeeTable 9).
REN SCON.4 Set/Cleared by softwareto Enable/Disable reeeption.
TB8 SCON.3 The 9th bit that will be transmitted in modes2 & 3. Set/Cleared by software,
RB8 SCON.2 In modes2 & 3, is the 9th data bit that was received.In mode 1,ifSM2 = O,RB8is the stop bit
that was received.In mode O,RB8 is not used.
TI SCON.1 Transmit interrupt tlag. Set by hardware at the end of the 8th bit time in mode O,or at the
beginningof the stop bit in the other modes.Must be cleared by software.
RI SCON.O Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode O,or halfway
through the stop bit time in the other modes(exceptsee SM2).Must be cleared by software.
NOTE1:

SMO SM1 Mode Deaoription Saud Rate

o 0 0 SHl~ REGISTER FOSC.112
o 1 1 8-Bit UART Variable
1 0 2 9-Bit UART Fo.sc./64OR
Fosc./32
1 1 3 9-Bit UART Variable

SERIAL PORT SET-UP:

Table 9
MODE SCON SM2 VARIATION
o 10H
SingleProcessor
1 50H
Environment
2 90H
(SM2 = O)
3 DOH
o
Multiprocessor
1 :0;
Environment
2 BOH
(SM2 = 1)
3 FOH

GENERATING BAUD RATES

Serial Port in Mode O:

ModeOhas a freedbaud rate whichis 1/12 of the oscillatorfrequency.To run the serial port in this mode none of
the Timer/Countersneed to be set
up. Only the SCON register needsto be defined.

Baud Rate = Y

Serial Port in Mode 1:

Mode 1 hss a variablebaud rate. The baud rate can be generatedby either Timer 1 or Timer 2 (8052only).
2-19
i~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET
I
USING TIMER/COUNTER 1 TO GENERATE BAUD RATES:
For this purpose,Timer 1 is used in mode 2 (Aut@Reload).Refer to Timer Setupsectionof this chapter.
Kx Oscillator
Freq.
BaudRate=
32X 12x [256 – (THI)]

If SMOD = O,then K = 1.
If SMOD = 1, then K = 2. (SMODis the PCON register).

Most of the time the user knowsthe baud rate and needsto know the reload valuefor TH1.
Therefore,the equation to calculate IT-Hcan be written as:

TH1 must be an integer value.Roundingoff THl to the neareat integer may not producethe desired baud rate. In
this casejthe user may have to chooseenother crystal frequency.

Sincethe PCON register is not bit addressable,one wayto set the bit is logicalORingthe PCON register. (ie, ORL
PCON,#80H). The address of PCON is 87H.

USING TIMER/COUNTER 2 TO GENERATE BAUD RATES:

For this purpose,Timer 2 must be used in the baud rate generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is beingclockedthrough pin T2 (P1.0)the baud rate is:
BaudRate = Timer2 OverflowRate
16

And if it is beingclockedinternallythe baud rate is:

OscFraq
BaudRate=
32X [65536- (RCAP2H,RCAP2L)]

To obtain the reload value for RCAP2Hand RCAP2Lthe aboveequationcan be rewritten as:

RCAP2H,RCAP2L= 65536 – 32 ;:a::ate

SERIAL PORT IN MODE 2:

Thebaud rate is fixedin this modeand is 7,, or%. of the oscillatorfrequencydpding on the v~ue of the SMOD
bit in the PCON register.

In this modenone of the Timers are used and the clock comesfrom the internal phase 2 clock.
SMOD = 1, Baud Rate = YWOsc Frcq.

SMOD = O,Baud Rate = yWw FrMI.

To set the SMODbit: ORL pcON, #80H. The address of PCON is 87H.

SERIAL PORT IN MODE 3:

Thebaud rate in mode 3 is variableand sets up exactlythe same as in mode 1.

2-20
i~. M=”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

M=@-51 INSTRUCTION SET

Table 10.8051 Inatruotion Set Summary

Interrupt ResponseTime: Refer to Hardware De- Oaeilfstor

Mnemonic Dsseription
scription Chapter. ‘m Period
Instructions that Affect Flag Settings(l) ---
ADD
.-
A,Rn
.
Ma registerto 1 12
Instruetkm Ffsg Inetmetion Flsg Accumulator
C OV AC C OV AC ADD A,direct Adddirectbyteto 2 12
ADD xx X CLRC o Accumulator
ADDC xx X CPLC x ADD A,@Ri Addindirect
RAM 1 12
SUBB xx X ANLC,bit X toAccumulator
MUL ox ANLC,/bit X ADD A,#date Addimmediate 2 12
DIV ox ORLC,bit X dateto
DA x ORLC,bit X Accumulator
RRC x MOVC,bit X ADDC A,Rn Addregister
to 1 12
RLC x CJNE x Accumulator
SETBC 1 withCarry
(l)FJotethat operationson SFR byte address 208or ADDC A,dirsct Adddirectbyteto 2 12
bit addresses 209-215(i.e., the PSW or bits in the Accumulator
PSW) will also afect flag settings. withCarry
ADDC A.@Ri Addindirect 1 12
Nota on inetruetionsat and ad&aesingmodes: RAMto
Rn — Register R7-RO of the currently se- Accumulator
lectedRegister Bank. withCarry
direct — 8-bit internal data location’s address. ADDC A,#date Addimmediate 2 12
This could been Internal Dsta RAM datetoAcc
locetion (0-127) or a SFR [i.e., I/O withCeny
pofi control register, status register, SUBB A,Rn Subtract
Register 1 12
etc. (128-255)]. fromAcewith
@Ri — 8-bit internal data RAM location (O- borrow
255)addreasedindirectly through reg- SUBB A,direct Subtrectdirect 2 12
ister R1 or RO. bytefromAcc
#data — 8-bitco~~t includedin instruction. withborrow
#data 16— 16-bitconstant includedin instmction. SUBB A.@Ri Subfrectindiract 1 12
addr 16 — 16-bit destination address. Used by RAMfromACC
LCALL & LJMP. A branch can be withborrow
anywhere within the 64K-byte Pro- A.#date Subtract 2 12
gram Memory SddR$S SpCCe. immediatedate
addr 1 — n-bit destination sddrrss. Used by fromAccwith
ACALL& AJMP. The branch willbe borrw
within the same 2K-byte page of pro- INC A Increment 1 12
gram memo~ as the first byte of the Accumulator
foil-g instruction. INC Rn Incrsmsnt
register 1 12
rel — Signed(two’scomplement)S-bitoffset INC direct Increment direct 2 12
byte.Usedby SJMP end all condition- byte
al jumps. Range is -128 to + 127 INC @Ri Incrementdirect 1 12
bytes relative to first byte of the fol- RAM
lowinginstruction. DEC A Decrement 1 12
bit — Direct Addressedbit in Internal Data Accumulator
W or SpecialFunction Register. DEC Rn Decrement 1 12
Regieter
DEC direct Decrement direct 2 12
byte
DEC @Ri Decrement 1 12
indirect
RAM
WImnemonics
copyrighted
@lntelCor’pxetion
1980

.
2-21
i~e McS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

Table 10.8051 Inetruotion Sat Summary (Continued)

~we o:acw~r
Mnemonic Deaoription

tRITNWTIC OPERATIONS (Continued)

.LUUIGAL
------ urtm
----------
IIUNS {wmunuao)
,A . . ,.

NC DPTR Increment Date 1 24 RL A 1 12

Pointer Accumulator Left
dUL AB MultiPiy
A& B 1 48 RLC A Rotate 1 12
)IV AB Ditie A byB 1 48 Accumulator Left
)A A DecimelAdjuet 1 12 through theCarry
Accumulator RR A Rotate 1 12
.OGICALOPERATtONS Accumulator
\NL A,Rn ANDRegieterto 1 12 Right
Accumulator RRC A Rotate 1 12
tNL A,direct ANDdiractbyte 2 12 Accumulator
toAccumulator Rightthrough
4NL A,@Ri ANDindirect 1 12 mecerry
RAMto SWAP A Swapnibbles 1 12
Accumulator withinthe
4NL A,#date ANDimmediate 2 12 Accumulator
datato DATATRANSFER
Accumulator MOV A,Rn Move 1 12
4NL direct,A ANDAccumulator 2 12 register
to
todirectbyte Accumulator
4NL diract,#data ANDimmediate 3 24 MOV A,direct Movediract 2 12
datatodirectbyte byteto
)RL A,Rn ORregister to 1 12 Accumulator
Accumulator MOV A,@Ri Moveindirect 1 12
2RL A,direct ORdirectbyteto 2 12 RAMto
Accumulator Accumulator
2RL A,@Ri ORindiractRAM 1 12 MOV A,#date Move 2 12
toAccumulator immediate
3RL A,#date ORimmediate 2 12 dateto
datato Accumulator
Accumulator MOV Rn.A Move 1 12
3RL dirac4,A ORAccumulator 2 12 Accumulator
todirectbyte toregister
3RL dirsct,~date ORimmediate 3 24 MOV Rn,direot Movedirect 2 24
detetodiractbyte byteto
KRL A,Rn Excluaiva-OR 1 12 register
regieterto MOV Rn,#date Move 2 12
Armmulator immediate date
I(RL A,diraot ExclusMe-OR 2 12 toregister
directbyteto MOV direct,A Mova 2 12
Accumulator Accumulator
KRL A,@Ri Exclush/e-OR 1 12 todirectbyte
indirect
RAMto MOV direct,Rn Moveregister 2 24
Accumulator todirectbyte
KRL A,#data Exclusiva-OR 2 12 MOV diract,directMovedirect 3 24
immediate datato bytatodiract
Accumulator MOV direct,@Ri Moveindirect 2 24
KRL direct,A Excluaive-OR 2 12 RAMto
Accumulator to directbyte
directbyte MOV direct,#date Move 3 24
KRL direct,gdata Exclueive-OR 3 24 immediate data
immediate date todireotbyte
todirectbyte MOV @Ri,A Move 1 12
CLR A Clear 1 12 Accumulator to
Accumulate
Complement 1 12
I indirect
RAM
CPL A Allmnemonics
copyrighted@lnteiCorporation
19S0
Accumulator
.2-22
in~. M=”-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

Table 10.8051 Instruction Set Summary(Continued)

I Mnemonic OeecriptfonByte ~~k~o’ Mnemonic Description Byte

Oeciltetor
Period
IDATATRANSFER (continued) BOOLEAN VARIABLEMANIPULATION
MOV @Ri,direct Movedirect 2 24 GLH L wearwny 1 12
byteto CLR bit Clesrdirectbit 2 12
indirect RAM SETB c SetCarry 1 12
MOV @Ri,#date Move 2 12 bit Setdirectbit 2 12
immediate CPL c Complement 1 12
dateto carry
indirect RAM CPL bit Complement 2 12
MOV DPTR,#data16LoedDets 3 24 directbit
Pointerwitha ANL C,bit ANDdirectbit 2 24
16-bitconstant toCARRY
MOVC A,@A+DPTR MoveMe 1 24 ANL C,/bit ANDcomplement 2 24
byterelativeto ofdirectbit
DPTRtoAcc tocarry
MOVC A,@A+PC MoveCode 1 24 ORL C,bit ORdirectbit 2 24
byterelativeto tocarry
PCtoAcc ORL C,/bit ORcomplement 2 24
MOVX A,@Ri Move 1 24 ofdirectbit
External tocarry
RAM(8-bit MOV C,bit Movedirectbit 2 12
eddr)toAcc tocarry
MOVX A,@DPTR Move 1 24 MOV bit,C MoveCsrryto 2 24
External directbit
RAM(l&bit JC rel JumpifCsny 2 24
addr)toAcc isset
MOVX @Ri,A MoveAccto 1 24 JNC rel JumpifCarry 2 24
External RAM notset
(8-bitaddr) JB bit,rel Jumpifdirecf 3 24
MOVX @DPTR,A MoveAccto 1 24 Bitisset
External RAM JNB bi$rel Jumpifdirect 3 24
(lS-bitaddr) BitisNotset
PUSH direct Pushdirect 2 24 JBC bit.rel Jumoifdirect 3 24
byteonto Bitisset&
stack clearbit
POP direct Popdirect 2 24 PROGRAMBRANCHING
bytefrom ACALL addrl1 Absolute 2 24
stack Subroutine
XCH A,Rn Exchange 1 12 call
registerwith LCALL addr16 Long 3 24
Subroutine
XCH A,direct Exchange 2 12 call
directbyte RET Returnfrom 1 24
with Subroutine
RETI Retumfrom 1 24
XCH A,@Ri Exchange 1 12 intempt
indirect
RAM AJMP addrll Absolute 2 24
with Jump
WMP addr16 LongJump 3 24
XCHD A,@Ri Exchange low- 1 12 SJMP rel ShortJumo 2 24
orderDigif (relativeaddr)
indirect
RAM VImnemonicscopyrigMed @lntelCorporation
1980
with Acc
I

2-23
int# MCS@-51PROGRAMMER’S GUIDE AND INSTRUCTION SET

Table 10.8051 Instruction Set SummarY (Continued)

Mnemonic Description Byte ‘~or Mnemonic Description Syte ~~or

.FmWrIANI
. . . . . .. BmANGmNQ
-m . ..-,,,..- ,-- —.,....
(wnunueq
.’,
PROGRAM BRANCHING (Continued)
JMP @A+DPTR Jumpindirecf 1 24 CJNE Rn,#date,rei Compare 3 24
relativetothe immediate to
DPTR register
and
JZ rel Jumpif 2 24 JumpifNot
Accumulator Equal
isZero CJNE @Ri,#data,rel Compare 3 24
JNZ rel Jumpif 2 24 immediate to
Accumulator indirect
and
isNotZero JumpifNot
CJNE A,direct,rei Compare 3 24 Equal
directbyteto DJNZ Rn,rei Decrement 2 24
AccandJump registerand
ifNotEquai JumpifNot
CJNE A,#date,rel Compare 3 24 Zero
immediate to DJNZ direct,rel Decrement 3 24
AccandJumo directbyte
ifNotEqual andJumpif
NotZero
NOP NoOperation 1 12
dlmnemonics
copyrighted @intelCorporation
1980

2-24
i~. M~@-51 PROGRAMMERS GUIDE AND INSTRUCTION SET

Table 11. Instruction Q i in Haxadecirnal Order

Hex Number Hex Number
Mnemonic Operands Mnemonic operands
Code of Bytes code of Bytes
00 1 NOP 33 1 RLC A
01 2 AJMP codesddr 34 2 ADDC A,#data
02 3 WMP codesddr 35 2 ADDC A,datsaddr
03 1 RR A 36 1 ADDC A,@RO
04 1 INC A 37 1 ADDC A,@Rl
05 2 INC dstsaddr 36 1 ADDC A,RO
06 1 INC @RO 39 1 ADDC A,R1
07 1 INC @Rl 3A 1 ADDC A,R2
06 1 INC RO 3B 1 ADDC A,R3
Oe 1 INC RI 3C 1 ADDC A,R4
OA 1 INC R2 3D 1 ADDC A,R5
OB 1 INC R3 3E 1 ADDC A,R6
Oc 1 INC R4 3F 1 ADD(2 A,R7
OD 1 INC R5 40 2 JC codeaddr
OE 1 INC R6 41 2 AJMP codeaddr
OF 1 INC R7 42 2 ORL datsaddr,A
10 3 JBC bitaddr,codeaddr 43 3 ORL dateaddr,#data
11 2 ACALL codeaddr 44 2 ORL A,#data
12 3 LCALL codeaddr 45 2 ORL A,dataaddr
13 1 RRC A 46 1 ORL A,@RO
14 1 DEC A 47 1 ORL A,@Rl
15 2 DEC dataaddr 46 1 ORL A,RO
16 1 DEC @RO 49 1 ORL A,R1
17 1 DEC @Rl 4A 1 ORL A,R2
16 1 DEC RO 4B 1 ORL A,R3
19 1 DEC RI 4C 1 ORL A,R4
1A 1 DEC R2 4D 1 ORL A,R5
lB 1 DEC R3 4E 1 ORL A,Re
lC 1 DEC R4 4F 1 ORL A,R7
ID 1 DEC R5 50 2 JNC codeaddr
lE 1 DEC R6 51 2 ACALL codeaddr
IF 1 DEC R7 52 2 ANL dataaddr,A
20 3 JB bifaddr,codeaddr 53 3 ANL dataaddr,#data
21 2 AJMP codeaddr 54 2 ANL A,#data
22 1 RET 55 2 ANL A,datsaddr
23 1 RL A 56 1 ANL A,@RO
24 2 ADD A,#dats 57 1 ANL A,@Rl
25 2 ADD A,datsaddr 5e 1 ANL A,RO
26 1 ADD A,@RO 59 1 ANL A,R1
27 1 ADD A,@Rl 5A 1 ANL A,R2
28 1 ADD A,RO 5B 1 ANL A,R3
23 1 ADD A,R1 5C 1 ANL A,R4
2A 1 ADD A,R2 5D 1 ANL A,R5
2B 1 ADD A,R3 5E 1 ANL A,R6
2C 1 ADD A,R4 5F 1 ANL A,R7
2D ADD A,R5 eo 2 JZ codeaddr
2E ; ADD A,R6 61 2 AJMP codeaddr
2F ADD A,R7 62 2 XRL datesddr,A
30 : JNB bitaddr,codeaddl 63 3 XRL datesddr,#data
31 2 ACALL codeaddr 64 2 XRL A,#data
32 1 RETI 65 2 XRL A,dataaddr

2-25
int# M~@.51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

s .. . . .-—-------- ----- ,--. .....---,

Hex Number Hex Number

Mnemonic Oparanda Mnemonic operands
Code of Bytaa Coda of Bytaa
5s 1 XRL A,@RO 99 1 SUBB A,R1
57 1 XRL A,@Rl 9A 1 SUBB A,R2
56 1 XRL ~RO 9B 1 SUBB A,R3
59 1 XRL A,RI 9C 1 SUBB A,R4
3A 1 XRL A,R2 9D 1 SUBB A,R5
5B 1 XRL A,R3 9E 1 SUBB A,R6
5C 1 XRL A,R4 9F 1 SUBB A,R7
6D 1 XRL A,R5 AO 2 ORL C,/bitaddr
SE 1 XRL A,R6 Al 2 AJMP codeaddr
SF 1 XRL A,R7 A2 2 MOV C,bitaddr
70 2 JNZ codeaddr A3 1 INC DPTR
71 2 ACALL codeaddr A4 1 MUL AB
72 2 ORL C,bitaddr A5 reaervad
73 1 JMP @A+DPTR A6 2 MOV @RO,dataaddr
74 2 MOV A,#data A7 2 MOV @Rl,dataaddr
75 3 MOV datsaddr,#data A8 2 MOV RO,dataaddr
76 2 MOV @RO, #data A9 2 MOV Rl,dataaddr
77 2 MOV @Rl,#data AA 2 MOV R2,dataaddr
76 2 MOV RO,#data AB 2 MOV R3,dstaaddr
79 2 MOV Rl, #data AC 2 MOV R4,dataaddr
7A 2 MOV R2,#data AD 2 MOV R5,dataaddr
70 2 MOV R3,#data AE 2 MOV R6,dataaddr
7C 2 hAov R4,#data AF 2 MOV R7,dataaddr
7D 2 Mov R5,#data BO 2 ANL C,/bitaddr
7E 2 MOV R6,#data B1 2 ACALL codeaddr
7F 2 MOV R7,#data 02 2 CPL bitaddr
80 2 SJMP codeaddr B3 1 CPL c
81 2 AJMP codeaddr 24 3 CJNE A,#data,codeaddr
82 2 ANL C,bitaddr B5 3 CJNE A,dataaddr,code
addr
83 1 MOVC A,@A+PC B6 3 CJNE @RO, #dats,codaaddr
84 1 DIV AB B7 3 CJNE @Rl,#data,codeaddr
85 3 MOV dataaddr,dataaddr 08 3 CJNE RO,#data,codeaddr
86 2 MOV dataaddr,@RO B9 3 CJNE Rl,#datasodeaddr
87 2 MOV dataaddr,@Rl BA 3 CJNE R2,#data$odeaddr
66 2 MOV dataaddr,RO BB 3 CJNE R3,#daQcodeaddr
89 2 MOV dataaddr,Rl BC 3 CJNE R4,#dats@de addr
8A 2 MOV dataaddr,R2 BD 3 CJNE R5,#data,codeaddr
8B 2 MOV dataaddr,R3 BE 3 CJNE R8,#data,codeaddr
SC 2 MOV dataaddr,R4 BF 3 CJNE R7,#data,codeaddr
8D 2 MOV dataaddr,R5 co 2 PUSH dataaddr
8E 2 MOV dataaddr,R6 c1 2 AJMP codeaddr
8F 2 MOV dataaddr,R7 C2 2 CLR bitaddr
90 3 MOV DPTR,#data C3 1 CLR c
91 2 ACALL codeaddr C4 1 SWAP A
92 2 MOV bitsddr,C C5 2 XCH A,dataaddr
93 1 MOVC A,@A+DPTR C8 1 XCH A,@RO
94 2 SUBB A,#data C7 1 XCH A,@Rl
95 2 SUBB A,dataaddr C8 1 XCH A,RO
M 1 SUBB A,@RO C9 1 XCH A,R1
97 1 SUBB A,@Rl CA 1 XCH A,R2
98 1 SUBB A,RO CB 1 XCH A,R3

2-26
ir& M=@-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

Table 11. Instruction Opoode In1 xadecimal Order (Continued)

Hex Number Hex Number
Operende Mnemonic Operande
Code of Bytee ‘nemonic Code of Bytee
cc 1 XCH A,R4 E6 1 MOV A,@RO
CD 1 XCH A,R5 E7 1 MOV A,@Rl
CE 1 XCH A,R6 E8 1 MOV A,RO
CF 1 XCH A,R7 E9 1 MOV A,R1
Do 2 POP dateaddr EA 1 MOV A,R2
D1 2 ACALL codaaddr EB 1 MOV A,R3
D2 2 SETB biladdr EC 1 MOV A,R4
D3 1 SETB c ED 1 MOV A,R5
D4 1 DA A EE i MOV A,R6
D5 3 DJNZ dateaddr,codeaddr EF 1 MOV A,R7
D6 1 XCHD A,@RO FO 1 MOVX @DPTR,A
D7 1 XCHD A,@Rl FI 2 ACALL codeaddr
CM 2 DJNZ RO,code addr F2 1 MOVX @RO,A
D9 2 DJNZ Rl,codeaddr F3 1 MOVX @Rl,A
DA 2 DJNZ R2,codeaddr F4 1 CPL A
DB 2 DJNZ R3,cadeaddr F5 2 MOV dataaddr,A
DC 2 DJNZ R4,codeaddr F6 1 MOV @RO,A
DD 2 DJNZ R5,codaaddr F7 1 MOV @Rl~
DE 2 DJNZ R6,c0deaddr F8 1 MOV RO,A
DF 2 DJNZ R7,codeaddr F9 1 MOV RI,A
EO 1 MOVX A,@DPTR FA 1 MOV R2,A
El 2 AJMP codeaddr FB 1 MOV R3,A
E2 1 MOVX A,@RO FC 1 MOV R4,A
E3 1 MOVX A,@Rl FD 1 MOV R5,A
E4 1 CLR A FE 1 MOV R6,A
E5 2 MOV A,dateaddr FF 1 MOV R7,A

2-27
 WS@-51 PROGRAMMER’S
GUIDEAND INSTRUCTION SET

INSTRUCTION DEFINITIONS
ACALL addrll

Function: AbsoluteCall
Deaoription: ACALL unconditionallycalls a subroutinelocated at the indicated address.The instruction
incrementsthe PC twim to obtain the address of the followinginstruction, then Duaheathe
Id-bit result onto the stack (low-orderbyte fret) and incremen~ the Stack Pointer&vice.The
destinationaddress is obtainedby suceesm “velyconcatenatingthe five high-orderbits of the
incrementedPC opcodebits 7-5,and the secondbyte of the instruction.The subroutinecalled
must therefore start within the same2K block of the programmemoryas the fsrstbyte of the
instrueticmfollowingACALL. No flagsare affected.
Example: InitiallySP equals 07H. The label “SUBRTN”is at programmemorylocation0345H. After
executingthe instruction,

ACALL SUBRTN

at location0123H, SP will contain 09H, internal IL4M locations08H and 09H will contain
25H and OIH, respectively,and the PC will contain 0345H.
Bytw 2
Cyclw 2

Encoding: I alO a9 a8 1 0001 a7 a6 a5 a4 a3 a2 al aO

ACALL
(PC)- (PC)+ 2
(SP) + (SP) + 1
((sP)) + (PC74)
(SP) + (SP) + 1
((SP))- (PC15.8)
(PClo.o)+ page address

2-26
in~o M~’@.51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

ADD A,<src-byte>

Function: Add
Description: ADD adds the bytevariableindicatedto the Acewmdator,leavingthe result in the Accumula-
tor. The carry and awdliary-carrytlags ~e set, respectively,if there is a carry-outfrom bit 7 or
bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an
overtlowoeared.

OVis set if there is a carry-out of bit 6 but not out of bit 7, or a carry-outof bit 7 but not bit 6;
otherwiseOV is cleared. When addingsigmd integera,OV indicates a negativenumber pro-
duced as the sum of two positiveoperandsjor a paitive sum from two negativeoperands.

Foursouree operandaddressingmodesare allowed:register,direcLregister-indirect,or imme-

diate.
Example: The Accumulatorholds OC3H(11OOOO11B)
and register O holds OAAH(10101O1OB).The
instruction,

ADD A,RO

willleave6DH (O11O1IO1B)
in the Accumulatorwith the AC flag clearedand both the carry
flag and OV SWto L

ADD A,Rn
Bytes: 1
Cycles: 1

Encoding: 0010 Irrr

Operation: ADD
(A) + (A) + @O

ADD A,direct
Bytatx 2
cycles: 1

Encoding: 0010 0101 I directaddress

Operation: ADD
(A) + (A) + (direct)

2-29
 MCS”-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

ADD A,@Ri
Bytes: 1
Cycles: 1

Encoding: IO O1OI Ollil

Operation: ADD
(A) - (A) + ((%))

ADD &#dats
Bytes 2
Cycles: 1

Encoding: 0010 0100 [

immediatedata

Operation: ADD
(A) - (A) + #data

ADDC A,<src-byte>

Function: Add with Carry

Description: ADDC simultaneouslyadds the byte variableindicated, the carry tlag and the Accumulator
contents, leavingthe result in the Accumulator.The carry and auxiliary-carryfiags are set,
respectively,if there is a carry-out from bit 7 or bit 3, and cleared otherwise.When adding
unsignedintegers,the carry tlag indicatesan overtlowOccured.

OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-outof bit 7 but not out of
bit 6; otherwiseOV is cleared. When addingsignedintegers, OV indicatssa negativenumber
producedas the sum of two positiveoperandsor a positivesum from two negativeoperands.
Four souroeoperandaddressingmodesare allowed:register, direct, register-indirect,or imme-
diate.
Example: ‘l%eAccumulatorholds OC3H(11OOOO11B)
and register OholdsOAAH(10101O1OB)with the
~ fig set. The instruction,
ADDC A,RO

will leave6EH (0110111OB)

in the Accumulatorwith AC clearedand both the Carry flag and
Ov set to 1.

2-30
intd. MCS@-51
PROGRAMMER’S
GUIDE AND INSTRUCTION SET

ADDC A,Rn
Bytes: 1
Cyclm 1

Encoding: 0011 Irrr

Operation: ADDC
(A) - (A) + (0 +(%)

ADDC A,direct
Bytes: 2
Cycles: 1

Encoding: 0011 0101 1 directaddress

Operation: ADDC
(A) + (A) + (C) + (direct)

ADDC A,@Ri
Bytes: 1
Cycles: 1

Encoding: 0011 Olli

Operation: ADDC
(A) + (A) + (C) + ((IQ)

ADOC A,+dats
Bytes: 2
Cyclesx 1

Enooding: 0011 0100 immediatedata

I
Operation: ADDC
(A) +- (A) + (C) + #data

2-31
i~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

AJMP addrll

AbsoluteJultlp
AJMP transfers program executionto the indicated address,which ia formedat run-time by
concatenatingthe high-orderfivebits of the PC (afier incrementingthe PC twice),opcodebits
7-5,and the secondbyte of the instruction. The destinationmust thereforebe withinthe same
2K block of program memoryas the first byte of the instructionfollowingAJMP.
Example The label “JMPADR” is at program memory location0123H.The instruction,

AJMP JMPADR

is at location 0345Hand will load the PC with O123H.

Bytas .L
Cycles 2

Encoding: alO a9 a8 O 0001 a7 a6 a5 a4 a3 S2 al aO

Operation: AJMP
@’cl+ (m + 2
(PClo.o)+ page address

ANL <dest-byte>, <src-byte>

Funotion: I.@cal-AND for byte variables

ANL performsthe bitwiselogical-ANDoperation betweenthe variablesindicatedand storea
the results in the destinationvariable. No flags are affected.

The two operandsallowsix addressingmode combinations.When the destinationis the Accu-

mulator, the source can w register, direct, regiater-indirec~or immediateaddressing;when
the destinationis a direct address, the source can be the Accumulatoror immediatedata.

Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch not the input pins.
Example: If the Accumulatorholds OC3H(11OOUHIB)and registerOholds 55H (O1OIO1O1B)
then the
instruction,

ANL A,RO

will leave 41H (OIOWOOIB)

in the Accumulator.
When the destinationis a directly addressed byte, this instruction will clear combinationsof
bits in SOYRAM locationor hardware register. The maskbyte determiningthe pattern of bits
to beclearedwouldeitherbe a constantcontainedintheinstructionor a valuecomputedin
the Accumulatorat run-time.The instruction,

ANL Pl, #Ol110011B

will clear bits 7, 3, and 2 of output port 1.

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in~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

ANL A,Rn
Bytes: 1
Cycles: 1

Encoding: 0101 Irrr

Operation:

ANL A,direct
Bytee:
Cycles:

Encoding: 0101 0101 directaddress

Operation: ANL

(A) ~ (A) A (direct)

ANL &@Ri
Bytes: 1
Cyclee: 1

Encoding: 0101 Olli

Operation: ANL

(A) + (A) A (w))

ANL A,#data
Bytes: 2
Cycles: 1

Encoding: 0101 0100 immediate date

Operation: ANL
(A) + (A) A #data

ANL dire@A
Bytas: 2
cycles 1

Encoding: 10101 00101 directaddress

Operation: ANL
(direct) + (direct) A (A)

2-33
i~. M=@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

ANL dire@ #dats

Bytes: 3
Cycles: 2

Encoding: 0101 0011 directaddress immediatedata

Operation: ANL
(direct) + (direct) A #data

ANL C,<src-bit>

Function: Logioal-ANDfor bit variables

Description: If the Booleanvalueof the sourcebit is a logicalOthen clear the carry flag;otherwiseleavethe
carry flag in its current stste. A slash (“/”) precedingthe operandin the assemblylanguage
indicatesthat the logicalcomplementof the addressedbit is used as the sourcevaluq but the
source bit itself & not affwed. No other flsgs are affected.

Onlydirect addressingis allowedfor the source -d.

Set the carry flag if, and only if, P1.O= 1, ACC. 7 = 1, and OV = O:
MOV C,P1.O ;LOAD CARRY WITH INPUT PIN STATE
ANL ~ACC.7 ;AND CARRY WITH ACCUM. BIT 7

ANL C,/OV ;AND WITH INVERSEOF OVERFLOWFLAG

ANL C,bit
Bytes: 2
Cycles: 2

Encoding: 1000
100101 H
Operation: ANL
(C) ~ (C) A (bit)

ANL C,/bit
Bytes: 2
Cycles:
.

Encoding: 1o11 0000

=
Operation: ANL
(C) + (C)A 1 (bit)

2-34
it@l. MCS’@-51PROGRAMMER’S GUIDE AND INSTRUCTION SET

CJNE <dest-byte>,<src-byte>, rel

Function: Compareand Jump if Not Equal.

Description: CJNE comparesthe magnitudesof the fmt two operands,and branches if their valuesare not
equal. The branch destinationis computedby addingthe signedrelative-displacementin the
last instructionbyte to the PC, after incrementingthe PC to the start of the next instruction.
The carry flag is set if the unsignedinteger value of <dest-byte> is less than the unsigned
integer valueof <src-byte>; otherwise,the carry is cleared. Neither operand is tided.
The first two operands allow four addressingmode combinations:the Accumulatormay be
comparedwith any directlyaddressedbyte or immediateda~ and any indirectRAM location
or worldngregister can be comparedwith an immediateconstant.
The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the se-
quence

CJNE R7,#60H, NOT-EQ

..... ; R7 = 60H.
NOT—EQ: JC
“‘“ REoLLOw ; IF R7 < &3H.
... ..... ; R7 > 60H.

sets the carry flag and branchesto the instructionat labelNOT-EQ. Bytestingthe carry flag,
this instructiondetermines whether R7 is greater or less than 60H.

If the data being presentedto Port 1 is also 34H, then the instruction,
WAIT: CJNE A,P1,WAIT

clears the carry tlag and continueswith the next instructionin sequence,sincethe Accumula-
tor doesequal the data read from P1. (If someother valuewas beinginput on Pl, the program
will loopat this point until the PI data changesto 34H.)

CJNE A,direct,rel
Bytes: 3
Cycles: 2

Encoding: 1o11 0101 I ‘ire”addressI EiEl

Operation: (PC) - (PC) + 3
IF (A) <> (direct)
THEN
(PC) + (PC) + relativeoffket
IF (A) < (direct)
THEN
~L~E (c) -1
(c)+ o

2-35
intel. M&0h51 PROGRAMMERS GUIDE AND INSTRUCTION SET

CJNE A,4$data,rei
Bytee: 3
Cycles: 2

Encoding: 1o11 0100 ] immediatedats I ! rel. address I

Operation: (-PC)+ (PC) + 3

IF (A) <> data
THEN
(PC) - (PC)+ relative offiet

IF (A) < data

THEN
EME (c) -1
(c) + o

CJNE Rn,#dats,rel
Bytea: 3
Cyclea: 2

Encoding: 1o11 Irrr I immediate data

EEl
Operation: (PC) + (Pc) + 3
IF (Rn) <> data
THEN
(PC) + m) + relative ofiet

IF (R@ < data

THEN
(c) + 1
ELSE
(c)+ o

CJNE @Ri,#data,rel
Bytea: 3
Cyclea: 2

Encoding: I 1o11 Olli I immediatedate I I rel.addressI

Operation: (P(2)+ (PC) + 3

IF ((Ri)) <> data
THEN
(PC) t (PC!)
+ rehztive oflset
IF (@i)) < data
THEN
ELSE (c) -1
(c) + r)

2-36
intd. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

CLR A

Function: Clear Aecunlulator

Description: The Aecunmlatoris cleared (all bits set on zero). No flags are affeeted.
Example: The Accumulatorcontsins 5CH (010111OOB).
The instruction,

CLR A
will leave the Accumulatorset to OOH(~ B).
Bytee: 1
Cyclea: 1

Encoding: 1110 0100

Operation: CLR
(A) + O

CLR bit

Function: Clear bit

Description: The indicatedbit is cleared(reset to zero).No other flagsare atkted. CLR ean operateon the
CSITYtig or any directlyaddressablebit.
Example: Port 1 has previouslybeen written with 5DH (O1O111O1B).
The instruction,

CLR P1.2

will leave the port set to 59H (O1O11CK)1B).

CLR C
Bytea: 1
cycle= 1

Encoding: I 1100 0011 I

Operation: CLR
(c)+ o

CLR bit
Bytea: 2
Cyclea: 1

Encoding: 1 100 0010 I bitaddress I

Operation: CLR
(bit) + O

2-37
intelo MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

CPL A

Function: ComplementAccumulator
Description: Each bit of the Accumulatoris logicallycomplemented(one’scomplement).Bits whichprevi-
ouslycontaineda one are changedto a zero and vice-versa.No tlags are affected.
Example: The Accumulatorcontains 5CH (O1O111CX3B).
The instruction,

CPL A
will leave the Accumulatorset to OA3H(101OOO11B).
Bytes: 1
Cycles: 1

Enooding: 1111 0100

Operation: CPL
(A) -1 (A)

CPL bit

Function: Complementbit
Deeoription: The bit variablespecifiedis complemented.A bit which had beena one is changedto zero and
vice-versa.No other flagsare affected.CLR can operate on the carry or any directly address-
able bit.

Note:Whenthis instructionis usedto modifyan output pin,the valueused as the originaldata

will be read from the output data latch, not the input pin.
Example: Port 1 has previouslybeen written with 5BH (O1O1I1O1B).
The instruction sequence,

CPL P1.1

CPL P1.2
will leavethe port set to 5BH(O1O11O11B).

CPL C
Bytes: 1
Cycletx 1

Encoding: I 1o11 0011

Operation: CPL
(c)+ 1 (c)

2-38
i~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

CPL bit
Bytes: 2
Cycles: 1

Encoding: 1o11
100’01 EEiEl
Operstion: CPL
(bit) ~l(bit)

DA A

Funotion: Decimrd-adjust Accumulatorfor Addition

Description: DA A adjusts the eight-bitvaluein the Accumulatorresultingfrom the earlieradditionof two
variables(each in packed-BCDformat), producingtwo four-bitdigits. Any ADD or ADDC
instruction may have been usedto perform the addition.
IfA ccurmdatorbits 3-Oare greater than nine (xxxxlOIO-XXXX1 I1I), or if the AC tlag is onq
six is added to the Accunndatorproducingthe proper J3CDdigit in the low-ordernibble.This
internal additionwouldset the carryflag ifa carry-outof the low-orderfour-bitfieldpropagat-
ed through all high-orderbits, but it would not clear the carry tlag otherwise.

If the carry tlag is now seLor if the four high-orderbits nowexceednine (101OXXXX-1I1XXXX),
thesehigh-orderbits are incrementedby six, producingthe properBCDdigitin the high-order
nibble.Again, this wouldset the carry flag if there was a carry-out of the high-orderbits, but
wouldn’tclear the carry. The carry flag thus indicates if the sum of the original two BCD
variablesis greater than 1120,allowingmultipleprecisiondecimaladdition.OVis not affected.

All of this occurs during the one instruction cycle. Essentially,this instructionperforms the
decimal conversionby addingOOH,06H, 60H, or 66H to the Accurnulator, depending on
initial Accurmdatorand P3W conditions.
Note:DA A cannot simplyconverta hexadecimalnumber in the Accrumdatorto BCD nota-
tion, nor does DA A apply to decimalsubtraction.

2-39
intd. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

The Accumulatorholdsthe value56H(OIO1OI1OB) representingthe packedBCDdigits of the

decimal number 56. Register 3 containsthe value 67H (0110011lB)representingthe packed
BCD digits of the decimal number 67. The carry flag is set. The instructionsequence.

ADDC A,R3
DA A
wdl first perform a standard twos-complementbinary addition, resultingin the value OBEH
(10111110)in the Accumulator. The carry and auxiliary carry flags will be cleared.

The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(OO1OO1OOB), indicatingthe packedBCDdigitsof the decimal number 24, the low-ordertwo
digitsof the decimalsum of 56,67, and the carry-in.The carry tlag willbe set by the Decimal
Adjust instruction,indicatingthat a ddnal overflowoccurred. The true sum 56,67, and 1 is
124.

BCDvariablescan be incrementedor decrementedby addingOIHor 99H.If the Accumulator

initially holds 30H (representingthe digitsof 30 decimal),then the instructionsequence,

ADD A#99H

DA A

will leave the carry set and 29H in the Accumulator,since 30 + 99 = 129.The low-order
byte of the sum can be interpreted to mean 30 – 1 = 29.
Bytes 1
Cycles: 1

Encoding: 1101 0100

Operstion: DA
-contents of Accumulatorare BCD
IF [[(A3-13)>91 V [(AC) = 111
THEN(A34)- (A343)+ 6
AND

IF [[(A7-4)> 9] V [(C) = 111

THEN (A74) - (A74) + 6

2-40
in~. MCS”-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

DEC byte

Function: Decrement
Description: The variableindicatedis decrementedby 1.An originalvalueof OOHwill underilowto OFFH.
No flags are affected. Four operand addressingmodes are allowed:accumulator, register,
&r@ or register-indirect.

Note: When this instruction is used to modifyan output port, the value used as the original
port data willbe read from the output data latch, not the input pins.
Exampte: Register Ocontains 7FH (0111111IB). Internal RAM locations7EH and 7FH contain OOH
and 40H, respectively.The instructionsequence

DEC @RO

DEC RO

DEC @RO

will leave registerOset to 7EH and internal RAM locations7EH and 7FH set to OFFHand
3FI-I.

DEC A
Bytes: 1
Cyclx 1

Encoding: 0001 0100

Operation: DEC
(A) - (A) – 1

DEC Rn
Bytes: 1
cycles: 1

Encoding: 0001 lrrr

Operation: DEC
(Rn) + @l) – 1

241
i~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

DEC direct
Bytes: 2
Cycles: 1

Encoding: 0001 0101

I directaddress

Operation: DEC
(direct) - (direct) – 1

DEC @Ri
Bytes: 1
Cycles: 1

Encoding: 10001 I Ollil

Operation: DEC
(w)) -((N)) – I

DIV AB

Function: Divide
Description: DIV AB divideathe unsignedeight-bitinteger in the Accumulatorby the unsignedeight-bit
integer in register B. The Accumulator receivesthe integer part of the quotient; register B
receivesthe integer remainder.The carry snd OV tlags will be cleared.

Exception: ifB had originallycontainedOOH,the valuesreturned in the Accumulatorand B-

register will be undefinedand the overflowflag will be set. The carry tlag is cleared in any
case.
Example: The Accumulatorcontains251(OFBHor 11111011B)
and B contains 18(12Hor OOO1OO1OB).
The instruction,
DIV AB
will leave 13in the Accumulator(ODHor OOOO11O1B) and the value 17(lIH or OOO1OOO1B)
in B, since 251 = (13 X 18) + 17.Carry and OV willboth be cleared.
Bytes: 1
Cycles: 4

Enooding: 1000 0100

I

Operation: DIV
(A)15.8
~)74 - (A)/@t)

2-42
in~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

DJNZ <byte>, <rel-addr>

Function: DecrementandJumpif Not =0

Description: DJNZ decrementsthe location indicated by 1, and branchesto the address indicatedby the
second operandif the resulting value is not zero. An originalvalue of OOHwill underflowto
OFFH.No tlags are at%cted.The branch destinationwouldbe computedby addingthe signed
relative-displacementvaluein the last instructionbyteto the PC, after incrementingthe PC to
the first byte of the followinginstruction.

The location decreznentedmaybe a register or directlyaddressedbyte.

Note: When this instruction is used to modfi an output port, the value used as the original
port data will be read from the output data latch, not the input pins.
Example: Internal RAM locations40H, 50~ and 60H containthe values OIH, 70H, and 15H,respec-
tively. The instructionsequence,

DJNZ 40H,LABEL-1
DJNZ 50H,LABEL-2
DJNZ 60H,LABEL-3

will cause a jump to the instructionat label LABEL-2 withthe valuesOOH,6FH, and 15Hin
the three W locations The first jump was not taken becausethe result was zero.

This instruction provideaa simpleway of executinga programloop a givennumberof times,

or for addinga moderatetime delay (from 2 to 512machinecycles)with a singleinstruction.
The instruction sequence,

MOV R2,#8
TOOOLE: CPL P1.7
DJNZ R2,TOOGLE

will toggle P1.7 eight times, causing four output pukes to appear at bit 7 of output Port 1.
Each pulse will last three machinecycles;two for DJNZ and one to alter the pin.

DJNZ Rn,rel
Bytee: 2
cycles: 2

Encoding: I 1101 11’”1 EEl

Operation: DJNZ
(PC!)- (PC) + 2
m) -(w – 1
w ~~~ 0 or (I@ < t)

(PC)+ (PC)+ rd

2-43
int& MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

DJNZ direct@
Byte= 3
Cycles 2

Encoding: 1101 0101

I ‘irw’addressI EiEl
Operation: DJNZ
(PC) + (PC) + 2
(direct) + (direct) – 1
IF (direot) >0 or (direct) <0
THEN
(PC) -(PC) + ml

INC <byte>

Function: Incmsnent
Description: INC incrementsthe indicatedvariableby 1. An originalvalueof OFFHwill overflowto OOH.
No figs are affected.Three addressingmodesare allowed:register,direct, or register-indirect.

Note.”When this instruction is used to modifyan output port, the value used ss the original
port data will be read from the output data latch, not the input pins.
Exsmple: RegisterOcontains7EH (01111111OB).
Internal RAM locations7EHand 7FH mntain OFFH
and 40H, respectively.The instructionsequence,

INC @RO
INC RO
INC @RO

will leaveregisterOset to 7FH and internal RAM locations7EHand 7FH holding(respective-

ly) (XIHand 41H.

INC A
Bytes: 1
cycles: 1

Encoding: 0000 0100

Operstion: INC
(A) + (A) + 1

2-44
i~e M=”-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

INC Rn
Bytes: 1
cycles 1

Encoding: 0000 Irrr

Operation: INC
m)+ w) + 1

INC direct
Bytee: 2
Cycles: 1

Encoding: 0000 0101

1
directaddress

Operation: INC
(direct) ~ (direct) + 1

INC @Ri
Bytes: 1
Cycles: 1

Encoding: 0000 Olli

Operation: INC
(m)) + (m)) + 1

INC DPTR

Function: Increment Dsta Pointer

Description: Increment the id-bit data pointer by 1. A id-bit increment (modulo216)is performed;an
overflowof the low-orderbyte of the data pointer (DPL) from OFFHto COHwill increment
the high-orderbyte (DPH). No tlsgs are sfkted.

This is the only id-bit register whichcan be incremented.

Example: RegistersDPH and DPL contsin 12Hsnd OFEH,respectively.The instruction sequence,
INC DPTR
INC DFTR
INC DPTR

will chsnge DPH and DPL to 13Hsnd OIH.

Bytes: 1
Cycle= 2

Encoding: 1o1o 0011

Operation: INC
(DPTR) - (DFITl) + 1

245
i~. MCS@-5f PROGRAMMER’SGUIDE AND INSTRUCTION SET

JB bityrei

Function: Jump if Bit set

Description: If the indicated bit is a one,jump to the addreasindicat@ otherwiseproceedwith the next
instruction.The branch destinationis computedby addingthe signedreistive-displscement in
the third instruction byte to the PC, after incrementingthe PC to the fnt byte of the next
instruction. The bit tested k nor modified. No tlags are affected.
The data present at input port 1 is 11OO1O1OB.
The Accumulatorhoids 56(O1O1O11OB).
The
instructionsequence,
JB P1.2,LABEL1

JB ACC.2,LABEL2

will causeprogram executionto branch to the instruction at label LABEL2.

Bytes: 3
Cycierx 2

Encoding: 00101004 EEzEEl EizEl

Operstion: JB
(PC)+ (PC)+ 3
IF (bit) = 1
THEN
(PC) +- (PC) + rel

JBC bitrei

Function: lump if Bit is setand Clearbit

Description: If the indicated bit is one, branch to the address indicated; otherwiseproceedwith the next
instruction. 17rebit wili not be cleared ~~itis already a zero. The branch destinationis comput-
ed by adding the signedrelative-displacementin the third instruction byte to the PC, after
incrementingthe PC to the tlrst byte of the next instruction. No flags are affected.

Note:When this instructionis used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Exempie: The Accumulatorholds 56H (01010110B).The instruction sequence,

JBC ACC.3,LABELI
3BC ACC.2,LABEL2

will cause program executionto continueat the instruction identifiedby the label LABEL2,
with the Accumulator modifiedto 52H (OIO1OO1OB).

2-46
 M=”-51 programmers GUIDE AND INSTRUCTION SET

Bytes: 3
Cycles: 2

Encoding:
I“” ”’l” ”””1 DEEl EiEiEl
Operation: JBc
(PC) - (PC) + 3
IF (bit) = 1
THEN
(bit) * O
(PC) ~ (PC) + rel

JC rel

Function: Jump if Carry is set

Daacription: If the carry flag is set, branch to the addreas indicated; otherwise proceed with the next
instruction.The branch destinationis computedby addingthe signedrelative-displacementin
the secondinstructionbyte to the PC, after incrementingthe PC twice. No flagsare afkted.
Exsmple: The carry flagis clesred. The instruction sequence,
JC LABEL1
CPL C
JC LABEL2

will set the carry and cause program executionto continueat the instructionidentifiedby the
label LABEL2.
Bytes 2
cycles: 2

Encoding: 0100 0000 =

Operation: JC
(PC)+ (PC)+ 2
IF (C) = 1
THEN
(PC) ~ (PC) + rel

2-47
i@. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

JMP @A+DPIR

Function: ]umpindirect
Add the eight-bitunsignedcontentsof the Accurnulator with the sixteen-bitdata pointer, and
load the resultingsum to the programcounter.This willbe the addressfor subsequentinstruc-
tion fetches.Sixteen-bitaddition is performed(modrdo216):a camy-outfrom the low-order
eight bits propagatesthrough the higher-orderbits. Neither the Accumulator nor the Data
Pointer is altered.No tlags are affected.
An evennumberfromOto 6 is in the Accumulator.The followingsequenceof instructionswill
branch to one of four AJMP instructionsin a jump table starting at JMP-TBL:
MOV DPTRj#JMP-TBL
JMP @A+DPTR
JMP-TBL: AJMP LABEL.O
AJMP LABEL1
AJMP LABEL2
AJMP LABEL3
If the Accumulatorequals 04H when starting this sequence,execution will jump to label
LABEL2.Rememberthat AJMP is a two-byteinstruction,so the jump instructions start at
every other address.
Bytex 1
Oycies: 2

Encoding: 10111 00111

Opersliorx JMP
W)+ (A) + WW

2-48
 MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SH

JNB bi~rel

Function: Jump if Bit Not set

If the indicatedbit is a zero, branch to the indicatedaddress;otherwiseproceedwith the next
instruction.The branch destinationis computedby addingthe signedrelative-displacementin
the third instruction byte to the PC, after incrementingthe PC to the first byte of the next
instruction. The bit tested is not modt~ed. No flags are affected.
Example: The data present at input port 1is 11W101OB.
The Accumulatorholds 56H(01010110B).The
instruction sequence,

JNB P1.3,LABEL1
JNB ACC.3,LABEL2

will cause program executionto continueat the instructionat label LABEL2.

Bytes: 3
Cycles: 2

Encoding: 0011 100001 LGzEl EEl

Operation: JNB
$W:)y; +3
THEN (PC) t (PC) + rel.

JNC rel

Function: Jump if Carry not set

Description: If the carry tlag is a zero, branch to the addreas indicated;otherwiseproceed with the next
instruction.The branch destinationis computedby addingthe signedrelative-displacementin
the second instruction byte to the PC, after incrementingthe PC twice to point to the next
inatruetion.The carry tlag is not moditled.
Example: The carrytlag is set. The instructionsequence,

JNC LABEL1
CPL C
JNc LABEL2
will clear the carry and cause program executionto continueat the instruction identitkd by
the label LABEL2.
Bytes 2
Cycles: 2

Encoding: 0101
100001 -
Operation: JNC
(PC) - (PC) + 2
IF (C) = O
THEN (PC) t (PC) + rel

2-49
i~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

JNZ rel

Function: Jump if AccumulatorNot Zero

If any bit of the Accumulator is a one, branch to the indicatedaddress;otherwiseproceedwith
the next instruction. The branch destination is computedby adding the signed relativedis-
placement in the second instruction byte to the PC, after incrementingthe PC twice. The
Accumulator is not modified.No tlags are affected.
Example: The Accumulator originallyholdsOOH.The instructionsequence,

JNZ LABEL1
INC A
JNZ LAEEL2

will set the Accumulatorto OIH and continueat label LABEL2.

Bytea: 2
Cyclea: 2

Encoding: 0111 10’001 EiEl

Operation: JNz
(PC)+ (PC) + 2
IF (A) # O
THEN (PC) ~ (PC) + rel

JZ rel

Function: Jump if AccumulatorZero

Daaoription: If all bits of the Accumulatorare zero, branch to the addressindica@ otherwiseproceedwith
the next instruction. The branch destination is computedby adding the signed relative-dis-
placement in the second instruction byte to the PC, after incrementingthe PC twice. The
Accumulator is not modified.No flags are affected.
The Accumulator originallycontainsOIH. The instruction sequen~

JZ LABELI
DEC A
JZ LABEL2

will change the Aec.umulator to OOHand cause programexeeutionto continueat the instruc-
tion identifiedby the label LABEL2.
Bytea: “

.4

Cycles: 2

E“ncodirrg: I 0110 0000

[
rel. addreee

Operation: Jz
(PCJ)
+ (w)+ 2
IF (A) = O
THEN (PC) t @C) + rel

2-50
in~. M=”-51 programmers GUIDE AND INSTRUCTION SET

LCALL addr16

Function: Longcall
Description: LCALLcalls a subroutineIooatedat the indicatedaddress. The instructionadds three to the
program counter to generate the address of the next instruction and then pushes the Id-bit
result onto the stack (low byte first), incrementingthe Stack Pointer by two. The high-order
and low-orderbytesof the PC are then loaded,respectively,with the secondand third bytes of
the LCALLinstruction.Programexeoutionrxmtinueswith the instructionat this address.The
subroutinemaythereforebeginanywherein the full 64K-byteprogrammemoryaddress space.
No ilags are affeeted.
Example: Initiallythe Stack Pointer equals07H.The label “SUBRTN”is assignedto programmemory
location 1234H.After exeoutingthe instruction,

LCALL SUBRTN

at location0123H,the Stack Pointer will contain09H, internal IL4M Iccations08H and 09H
will contain26H and OIH, and the PC will contain 1234H.
Bytes: 3
Cycles: 2

Encoding: 0001 0010 I addr’’-add’ I EEEiEl

Operation: LCALL
(PC) + (PC) + 3
(SP) + (SP) + 1
((sP)) - (PC74)
(SP) - (SP) + 1
((sP)) - (PC15.8)
(PC) ~ addr15~

UMP addr16

Function: Long Jump

Description: LJMP causesan unconditionalbranch to the indiested address,by loadingthe high-orderand
low-orderbytes of the PC (respectively)with the second and third instruction bytes. The
destinationmay therefore be anywherein the full 64K program memoryaddress sparx. No
flags are affected.
Example: The label“JMPADR” is assignedto the instructionat programmemorylocation 1234H.The
instruction

LJMP JMPADR

at location0123Hwill load the programcounter with 1234H.

Cycles:

Enooding:

operation:

2-51
i~. M=@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

MOV <dest-byte>, <erc-byte>

Function: Movebyte vmiable

Oeacription: The byte variableindicatedby the secondoperandis copiedinto the locationspecifiedby the
first operand.The source byte is not affeeted.No other register or flag is at%eted.

This is by far the mmt flexible operation. Fifteen combinationsof source and destination
addressingmodes are allowed.
Example: Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H.The data
prcaentat input port 1 is 11OO1O1OB
(OCAH).

MOV RO,#30H ;RO < = 30H

MOV A,@RO ;A < = 40H
MOV R1,A ;Rl < = 40H
MOV B,@Rl ;B < = 10H
MOV @Rl,Pl ;RAM (4X-I)< = OCAH
MOV P2,PI ;P2 #OCAH

leavesthe value30Hin register O,40Hin both the Aecumulator and register 1, 10Hitsregister
B, and OCAH(11OO1O1OB) both in RAM Ioeation40H and output on port 2.

MOV A,Rn
Bytes: 1
Cycles: 1

Encoding: 1110 lrrr

Operation: MOV
(A) + (RIO

*MOV A,direct
Bytes: 2
Cycles: 1

Encoding: 1110 0101 direct address

Operation: MOV
(A) + (direct)

MOV~ACC ie not a valid instruction.

2-52
intd. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SH

MOV A,@Ri
Bytes: 1.
Cycles: 1

Encoding: 1110 Olli

Operation: MOV
(A) - (~))

MOV A,#data
Bytes: 2
Cycles: 1

Encoding: 0111 0100 immediatedata

I
Operation: MOV
(A) + #data

MOV Ftn,A
Bytes: 1
Cycles: 1

Encoding: I 1111 I Irrrl

Operation: MOV
~) t (A)

MOV Rn,direot
Bytee:
.L
Cyclea: 2

Encoding: I 1010
Ilr’rl -
Operation: MOV
(I@ + (direct)

MOV Rn, #data

Bytes:
.

cycles: 1

Encoding: 0111 lrrr immediatedata

Operation: MOV
(R@ - #dsts

2-53
irrtd. M~@-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

MOV directJl
Bytetx 2
Cycle$x 1

Encoding: 1111 0101 directaddress

Operation: MOV
(direct)
- (A)

MOV dire@Rn
Bytes: 2
Cyciee: 2

Encoding: 1000 Irrr directaddress

Operation: MOV
(direct)
+ (lb)

MOV directjdirect
Bytw 3
Cycie= 2

Encoding: 1000 0101 dir.addr. (src) dir.addr. (dest)

I I
Operation: MOV
(direct) +- (direct)

MOV direct@Ri
Bytes: 2
Cycles: 2

Encoding: 1000 Olli

I
Operation: MOV
(MM) + (w))

MOV direc$xdats
%yte= 3

Cycle= 2

Encoding: 0111 0101 directaddress immediatedata I

Operation: MOV
(direct) + #date

2-54
intd. MCS@-51PROGRAMMEWSGUIDE AND INSTRUCTION SET

MOV @Ri&
B- .1
cycles: 1

Encoding: 1111 Olli

Operation: MOV
(@i)) + (A)

MOV @Ri,direct
Bytes: 2
Cycles: 2

Encoding: llOIOIOllil I directaddr. I

Operation: MOV
(@i)) + (direct)

MOV @Ri,#data
Bytes: 2
Cycles: .1

Encoding: 0111 Olli immediate data

I
Operation: MOV
((RI)) + #data

MOV <cleat-bit>, <erc-bit>

Function: Move bit

data
Description: The Booleanvariableindicatedby the second operand is copiedinto the locationspecitkd by
the first operand. One of the operandsmust be the carry flag; the other may be any directly
addressablebit. No other registeror flag is affected.
Example: The carry tlag is originallyset. The data present at input Port 3 is 11OOO1OIB.
The data
previouslywritten to output Port 1 is 35H (03110101
B).

MOV P1.3,C
MOV C,P3.3
MOV P1.2,C
will leavethecarrycleared and changePort 1 to 39H (OO111OO1B).

2-55
I I
int& M=@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

MOV C,blt
Bytes: 2
Cycles: 1

Enooding: 1o1o
1“0’01 EiEl
Operstion: MOV
(~+(bit)

MOV bi&C
Bytes:
.L
Cycles: 2

Enooding: 1001
1“0’01 E
Operstion: MOV
(bit) + (C)

MOV DPTR,#dsts16

Function: Load Data Pointer with a Id-bit constant

Description: The Data Pointer is loaded with the Id-bit constant indicated.The id-bit constant is loaded
into the second and third bytes of the instruction. The secondbyte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-orderbyte. No tlags are atTeeted.

This is the only instruction whichmovea 16bits of tits at once.

Example: The instruction,
MOV DPTR, # 1234H

willload the value 1234Hinto the Data Pointer: DPH willhold 12Hand DPL will hold 34H.
Bytesx 3
Cycles: .L

Encoding: 1001 0000 immed.data7-O

I immed. dsts15-6 I
Operation: MOV
(DPTR) ~ #data154
DPH ❑ DPL + #&ltS15.8❑ #data73

2-56
intd. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

MOVC A,@A+<baas-reg>

Function: MoveCode byte

Description: The MOVCinatmctionsload the Accumulatorwith a oode byte, or constant from program
memory.The addressof the byte fetchedis the sum of the originalunsignedeight-bitAccumu-
lator contents and the contents of a sixteen-bitbase register, which may be either the Data
Pointer or the PC. In the latter case, the PC is incrementedto the addressof the following
instruction before being added with the Accumulator; otherwise the base register is not al-
tered. Sixteen-bitaddition is performed so a carry-out from the low-ordereight bits may
propagatethrough higha-order bits. No flags are affected.
Example: A valuebetweenOand 3 is in the Accumulator.The followinginstructionswill translate the
valuein the Accumulatorto one of four valuesdefimedby the DB (definebyte) directive.

REL-PC: INC A

MOVC A,@A+PC

RET
DB 66H
DB 77H

DB 88H
DB 99H
If the subroutineis called with the Accumulatorequal to OIH, it will return with 77H in the
Auxmmlator. The INCA beforethe MOVCinstruction is neededto “get around” the RET
instructionabovethe table. If severalbytes of code separated the MOVCfrom the table, the
correspondingnumber wouldbe added to the Accumulator instead.

MOVC ~@A+ DPTR

Bytes: 1
Cycles: 2

Encoding: 11001 10011 I

Operation: MOVC
(A) + ((A) + (D~))

MOVC A,@A + Pc

Bytes: 1
Cycles: 2

Encoding: 1000 0011

Operation: MOVC
(PC) + (PC) + 1
(A) - ((A) + (PC))

2-57
int& MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

MOVX <dest-byte>, <sin-byte>

Function: Move External

Deaoription: The MOVX instructions transfer data betweenthe Accumulator and a byte of exa data
memory,hence the “X” appendedto MOV.There are two types of instructions,differingin
whetherthey providean eight-bitor sixteen-bitindirect address to the externrddata RAM.

In the first typq the contents of ROor R] in the current register bank providean eight-bit
address multiplexedwith data on PO.Eight bits are sufficient for external 1/0 expansion
decodingor for a relativelysmall RAM array. For somewhatlarger arrays, any output port
pins can be used to output higher-orderaddress bits. These pins wouldbe controlled by an
output instructionprecedingthe MOVX.

In the secondtype of MOVXinstruction,the Data Pointer generatesa sixteen-bitaddress. P2

outputsthe high-ordereight addressbits (the contents of DPH) whilePOmultiplexesthe low-
order eightbits (DPL) with data. The P2 SpecialFunction Register retains its previouscon-
tents whilethe P2 ouQut buffers are emitting the contents of DPH. This form is faster and
more efticientwhen accessingvery large data arrays (up to 64K bytes), since no additional
instructionsare neededto set up the output ports.

It is possiblein some situations to mix the two MOVX types. A large R4M array with its
high~rder address lines driven by P2 can be addressed via the Data Pointer,or with code to
output high-orderaddress bits to P2 followedby a MOVX instructionusingROor RI.
Example: An external256 byte RAM usingmultiplexed
address/&talines(e.g.,an Mel 8155UM/
I/Oflimer) is connected to the 8051Port O. Port 3 provides control lines for the external
W. Ports 1 and 2 are used for normal 1/0. Registers O and 1 contain 12H and 34H.
Location34Hof the extemsJ RAM holdsthe value 56H. The instructionsequence,
MOVX A@Rl

MOVX @RO,A

copiesthe value 56H into both the Accumulatorand external RAM location 12H.

2-58
i~o M=@-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

MOVX &@Ri
Bytes: 1
Cycles: 2

Encoding: 1110 OOli

Operation: MOVX
(A) - (~))

MOVX A@DPIR
Bytes: 1
Cycles: 2

Encoding: 1110 0000

Operation:

MOVX @Ri,A
Bytes: 1
Cycles: 2

Encoding: 1111 OOli

Operation: MOVX

MOVX @DPIR#l
Bytes: 1
cycles: 2

Encoding: 1111 0000

Operation: MOVX
(DPTR) - (A)

2-59
i~e MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

MUL AB

Multiply
Deeoriptiors: MUL AB multipliesthe unsignedeight-bit integers itsthe Accumulator and register B. The
Iow-orderbyteof the sixteen-bitproduct is left in the Accumulator,and the high-orderbyte in
B. If the product is greater than 255 (OPPH)the ovcrtlowflag is set; otherwiseit is cleared.
The carry fiag is alwayscleared.
Example Originallythe Accumulatorholds the value 80 (50H).RegisterB holds the value 160(OAOH).
The instruction,

MuLAB

will givethe product 12,S00(3200H),so B is changedto 32H(OO11OO1OB)

and the Accumula-
tor is cleared. The overflowflag is set, carry is cleared.
Bytes: 1
Cycles: 4

Encoding: I 101 OIO1OOI

Operation: MUL
(A)74 + (A) X (B)
(B)15-8

NOP

Function: No Operation
Description: Executioncontinuesat the followinginstruction. Other than the PC, no registersor flagsare
affected.
Example: It is desired to producea low-goingouQut pulse on bit 7 of Port 2 lasting exactly5 cycles.A
simple SETB/CLRsequencewouldgeneratea one-cyclepulse,so four additionalcyclesmust
be inserted. This may be done (ssauming no interrupts are enabled) with the instruction
SeqUenee,

CLR P2.7
NOP
NOP
NOP
NOP
SETB P2.7
Bytes 1
Cycles: 1

Encoding: 000010000

Operation: NOP
(PC)+ (-PC)
+1

2-00
in~. MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

ORL <dest-btie> <src-byte>

Funotion: Logicsl-ORfor byte variables

ORL performs the bitwiselogical-ORoperationbetweenthe indicated variables,storing the
results in the destinationbyte. No flags are affected.

The two operandsallowsixaddressingmodecombinations.Whenthe destinationis the Accu-

mulator, the source can use register, direct, register-indirect,or immediateaddressing;when
the destinationis a direct addreas,the source can be the Accumulatoror immediatedata.
Note.-When this instructionis used to modifyan output port, the value used as the original
port dats will be resd from the output data latch, not the input pins.
Example: If the Accumulator holds OC3H(I1OOOO1IB)
and ROholds 55H (O1O1O1O1B)
then the in-
struction,

ORL A,RO

will leave the Accumulatorholdingthe value OD7H(110101llB).

When the destinationis a directlyaddreasedbyte, the instructioncan set combinationsof bits

in any RAM location or hardware register. The pattern of bits to be set is determinedby a
mask byte, whichmaybe eithera constantdata valuein the instructionor a variablecomputed
in the Aecunndator at rim-time.The instruction,

ORL P1,#OOllOOIOB

will set bits 5,4, and 1 of output Port 1.

ORL &Rn
Bytes: 1
Cycles: 1

Encoding: 0100 lrrr

Operstion: ORL
(A) +- (A) V K)

2-61
i~e M=a-sl
PROGRAMMER’S
GUIDEAND INSTRUCTION SET

ORL &direct
Bytes: 2
Cycles: 1

Encoding: 1010010101 I directaddress

Operation: ORL
(A) + (A) V (direct)

ORL &@Ri
Bytes: 1
Cycles: 1

Encoding: 0100 Olli

Operation:

ORL A,#dets
Bytes: 2
Cycles: 1

Encoding: Iolool O1oo1 immediatedata

Operation: ORL
(A) - (A) V #dsts

ORL direct,A
Bytes:
Cyclea: 1

Encoding: 0100 0010 directaddress

Operation: ORL
(direct) ~(direct) V (A)

ORL direcQ*data
Bytes: 3
Cycles: 2

Encoding: 0100 0011 I EEEl immediate date

I

Orwstion: ORL
(direct)+ (direct) V #data

2-62
in~. MCS@-51PROGRAMMER’S GUIDE AND INSTRUCTION SET

ORL C,<src-bit>

Function: Logical-ORfor bit variables

Description: *t the carry flagif the Booleanvalue is a logical 1; leave the carry in its current state
otherwise. A slash (“/”) precedingthe operand in the assemblylanguageindicatesthat the
logicalcomplementof the addressedbit is used as the source value,but the sourcebit itselfis
not at%cted.No other tlags are afkcted.
Example: Set the carry flag if and only ifP1.O = 1, ACC. 7 = 1, or OV = O:

MOV CPI.O ;LOAD CARRY WITH INPUT PIN P1O

ORL C,ACC.7 ;OR CARRY WITH THE ACC. BIT 7

ORL Wov ;OR CARRY WITH THE INVERSEOF OV.

ORL C,bit
Bytes: 2
Cycles: 2

Encoding: 0111
IOO1OI EEl
Operation:

ORL C,/bit
Bytes: 2
Cycles:
.

Encoding: I 1010 100001 EEEl

Operation: ORL
(c)+ (c) v @=)

2-63
i~. M~eI-51 programmers GUIDE AND INSTRUCTION SET

POP direot

mrsctiom Pop from stack.

The contents of the internal RAM location addressedby the Stack Pointer is read, and the
Stack Pointer is decrementedby one. The value read is then transferred to the directly ad-
dressedbyte indicated.No flags are affected.
Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and OIH, respectively.The instructionsequen~

POP DPH

POP DPL

willleavethe Stsck Pointer equal to the value30Hand the Data Pointer set to 0123H.At this
point the instruction,

POP SP

will leave the Stick Pointer set to 20H. Note that in this special case the Stack Pointer was
*remented to 2FH beforebeing loaded with the value popped (20H).
Bytea: 2
Cycla$s 2

Encoding: I 1101 0000 directaddress

Operation: POP
(direct) + ((sP))
(SP) 4-(SP) – 1

PUSH direct

Function: push onto stack

Description: The StackPointeris incrementedby one. The contentsof the indicatedvariableis then copied
into the internal RAM locationaddressedby the Stack Pointer. Otherwiseno flagsare affect-
ed.
On entaing an interrupt routine the Stack Pointercontains09H. The Data Pointer holds the
value O123H.The instruction sequence,

PUSH DPL
PUSH DPH
will leave the Stack Pointer set to OBHand store 23H and OIH in internal FL4Mlocations
OAHand OBH,respectively.
Bytes: 2
Cycletx 2

Enooding: 1100 0000 I directaddreaa

Operation: PUSH
(SP) + (SP) + 1
((SP))- (direct)

2-04
int& M~tV-51 PROGRAMMER’SGUIDEANDINSTRUCTIONSET

RET

Function: Return tlom subroutine

Description: RET pops the high-and low-orderbytes of the PC successivelyfrom the staclGdecrementing
the Stack Pointer by two. Program executioncontinuesat the resultingaddress,generallythe
instruction immediatelyfollowingan ACALLor LCALL. No tlags are affected.
Example: The Stack Pointer originallycontains the valueOBH.Internal RAM locationsOAHand OBH
contain the value-a23H and OIH, respectively.The instruction,

RET
will leave the Stack Pointer equal to the value 09H. Program executionwill continue at
Ioeation0123H.
Bytm 1
cycles: 2

Encoding: 10010100101
Operation: RET
(Pc~~-s)
+- ((sP))
(SP) +(SP) – 1
(PC74) + ((sP))
(SP) + (SP) -1

RETI

Function: Return from interrupt

Description: RETI pops the high- and low-orderbytes of the PC successivelyfrom the stack, and reatores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed.The Stack Pointer is left decrementrdby two. No other registersare aik%sd; the
PSW is not automaticallyrestored to its pre-interruptstatus. Program executioncontinuesat
the resultingaddress, which is generallythe instructionimmediatelyafter the point at which
the interrupt requestwas detected. Ifa lower-or same-levelinterrupt had beenpendingwhen
the RETI instruction is executed, that one instruction will be executedbefore the pending
interrupt is processed.
Exemple: The Stack Pointer originally contains the value OBH.An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations OAHand OBHcontain the
values 23H and OIH, reapeotively.The instruction,

RETI
wilt leave the Stack Pointer equat to O$IHand return program executionto locationO123H.
Bytes: 1
Cyclee: 2

Encoding: 10011 I 00101

Operation:
(PCls.s)
+ ((sP))
(sP)+ (SP) -1
(PC74) + ((sP))
(SP) -(SP) -1

2-65
intd. M=”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

RL A

Function: Rotate Aecurnulator Left

Description: The eight bits in the Aeeurmdatorare rotated one bit to the left. Bit 7 is rotated into the bit O
position.No flagsare akted.
Example: The Aeeumulatorholds the value OC5H(11OQO1O1B).
The instruction,

RLA

leavesthe Accumulatorholdingthe value 8BH (1OOO1O11B)

with the carry unaffected.
Bytes: 1
Cycle= L

Encoding: 0010 0011 I

Operation: RL
(~ + 1) - (An) n = O – 6
(AO)+ (A7)

RLC A

Function: Rotate Accumulator L-et?through the Carry flag

Description: The eightbits in the Aeeumulator and the carry tlag are togetherrotated onebit to the left. Bit
7 movesinto the carry flag;the originalstate of the carry tlag movesinto the bit Oposition.No
other flags are affeeted.
Example: The Accumulatorholds the valueOC5H(110CHI101B),
and the carry is zero. The instruction,

RLC A
leavesthe Accumulatorholdingthe value 8BH (1OOO1O1OB)
with the carry set.
Bytes: 1
Cycle= 1

Encoding: 0011 0011

Operation: RLc
(An+ 1)~ (An) n = O – 6
(AO)+ (C)
(C) +- (A7)

2-66
intd. M~@-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET

RR A

Functiorx Rotate AccumulatorRight

Description: The eight bits in the Aeoumulatorare rotated onebit to the right. Bit Ois rotated into the bit 7
position.No flags are affected.
Example: The Accumulator holds the value OC5H(11COO1O1B).
The instruction,

RRA
leavesthe Aecmmdatorholdingthe value OE2H(111OOOIOB)
with the carry unattested.
Bytes: 1
cycles: 1

Encoding: 0000 0011

Operation: RR
(An) + (An + 1) n = O – 6
(A7) - (AO)

RRC A

Rotate Aeeumulator Right through Carry flag

Description: The eightbits in the Accumulatorand the carry flag are togetherrotated one bit to the right.
Bit O moves into the carry tlag; the originrd value of the carry flag moves into the bit 7
position.No other figs are affected.
Example: The Accumulator holds the value OC5H(11OOO1O1B),
the carry is zero. The instruction,

RRC A
leavesthe Accumulatorholdingthe value 62 (O11OOO1OB)
with the carry set.
Bytes: 1
cycles: 1

Encoding: 0001 0011

Operation: RRc
(An) + (h + 1) n = O – 6
(A7) - (C)
(C) + (AO)

2-67
i~e M(3@-51 PROGRAMMER~SGUIDE AND INSTRUCTION SET

SETB <bit>

Function: Set Bit

SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressablebit. No other flags are affected.
Example: The carry flagis clesred.Output Port 1has beenwritten with the value34H(OO11O1OOB).
The
instructions,

SETE C

SETB PI.O

will leave the carry tlag set to 1 and changethe data output on Port 1 to 35H (OO11O1O1B).

SETB C
Bytes: 1
cycles: 1

Encoding: 11101 10011 I

Operation: SETB
(c) + 1

SETB bit
Bytes: 2
cycles: 1

Encoding: 1101
100101 EiEEl
Operation: SETB
(bit)+ 1

2-68
i~. MCS@-51PROGRAMMER’S GUIDE AND INSTRUCTION SET

SJMP rel

Function: Short JurnP

Deaoription: Programcontrol branchss unconditionallyto the address indicated.The branch destinationis
computedby adding the signed displacementin the second instructionbyte to the PC, after
incrementingthe PC twice. Therefore, the range of destinationsallowedis from 128bytes
precedingthis instruction to 127bytes followingit.
Example: The label“RELADR” is assignedto an instruction at program memorylocation0123H.The
instruction,

SJMP RELADR

will assembleinto location O1OOH.

After the instruction is executed,the PC will ccmti the
value0123H.

(Norc Under the aboveconditionsthe instruction followingSJMPwillbeat 102H.Therefore,

the displacementbyte of the instructionwillbe the relativeoffset(O123H-O1O2H)
= 21H. Put
another way,an SJMP with a displacementof OFEHwouldbe a one-instructioninfiniteloop.)
Bytes: 2
Cycles: 2

Encoding: 1000 100”01 EEl

Operation: SJMP
(PC) + (PC) + 2
(PC) - (PC) + rel

2-69
i@. MCS”-51PROGRAMMER’S
GUIDEANDINSTRUCTIONSET

SUBB A<sro-byte>

Function: Subtract with bOrrOW

Deeoription: SUBBsubtracts the indicated variable and the carry tlag together from the Accumulator,
lesvingthe result in the Accumulator.SUBBsets the carry (borrow)tlag if a borrowis needed
for bit 7, and cleam C otherwise. (H c was set bqfors executing a SUBBinstruction, this
indicates that a borrow was neededfor the previousstepin a multipleprecisionsubtraction,so
the csrry is subtracted from the Accumulatoralong with the source operand.)AC is set if a
borrowis neededfor bit 3, and clearedotherwise.OVis set ifa borrowis neededinto bit 6, but
not into bit 7, or into bit 7, but not bit 6.

When subtraetm“ g signedintegersOV indicatesa negativenumber produwd whena negative

value is subtracted from a positive value, or a positive result when a positive number is
subtractedfrom a negativenumber.

The sourceoperandallowsfour addressingmodes:register,direct, register-indirecLor imme-

diate.
The AccumulatorholdsOC9H(11OO1OO1B),
register2 holds 54H (O1O1O1OOB),
and the carry
flag is set. The instruction,
SUBB A,R2

will leavethe value 74H (O1I1O1OOB)

in the accumulator,with the cany flag and AC cleared
but OVset.
Notice that OC9Hminus 54H is 75H.The differencebetweemthis and the aboveresult is due
to the carry (borrow)flag beingset beforethe operation.If the state of the carry is not known
before starting a singleor multiple-precisionsubtraction, it should be explicitlycleared by a
CLR C instruction.

SUBB A,Rn
Bytes: 1
Cycles: 1

Irrr
Encoding: I 1001
Operation: SUBB
(A) - (A) - (C) - (IQ

2-70
intel. MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

SUBB ~direct
Bytes: 2
cycles: 1

Encoding: I 1001 0101

I directaddress
Operation: SUBB
(A) - (A) – (C) – (direct)

SUBB A@Ri
Bytes: 1
cycles: 1

Encoding: I1OO1 IOllil

Operation: SUBB
(A) - (A) - (C) - ((M))

SUBB A,4$dats
Bytes:
.f
Cycles: 1

Encoding: 1001 0100

I immediate data
Operation: SUBB
(A) - (A) - (C) – #data

SWAP A

Function: Swapnibbleswithinthe Accumulator

Description: SWAP A interchange the low- and high-ordernibblea(four-bit fields) of the Accumulator
(bits 3-0md bits 7-4).The operationcan ako be thoughtof as a four-bitrotate instruction.No
flags are affected.
Example: The Accumulatorholdsthe value OC5H(11OO31O1B).
The instruction,
SWAP A
leavesthe Accumulatorholdingthe value 5CH (O1O111OOB).
Bytes: 1
Cycles: 1

Encoding: 1100 0100

Operation: SWAP
(A3-0)~ (A7-4)

2-71
intd. MC=’-5l PROGRAMMER’SGUIDEANDINSTRUCTIONSET

XCH Aj<byte>

Function: BxchangeAccumulatorwith byte variable

Description: XCH leads the Accumulatorwith the contents of the indicated variable, at the same time
writing the originalAccumulator contents to the indicated variable. The source/destination
operand ean w register,direet, or register-indirectaddressing.
Example: ROcontains the address20H. The Accumulatorholds the value 3FH (OO1lllllB). Internal
RAM location20H holds the value 75H (01110101B).The instruction,

X3-I A,@RO

will leaveRAM location20H holdingthe values3FH (0011111IB) and 75H (O111O1O1B)

in
the accumulator.

XCH A,Rn
Bytee: 1
Cycles: 1

Encoding: 1100 Irrr

Operation: XCH
(A) z (R@

XCH A,direct
Bytes: 2
Cycles: 1

Encoding: 1100 0101 directaddress

I
Operation: XCH
(A) z (direet)

XCH A,@Ri
Bytes: 1
cycles: 1

Encoding: 1100 Olli

Operation: XCH
(A) ~ (@))

2-72
i~. MCS”-51 programmers GUIDE AND INSTRUCTION SET

XCHD A,@Ri

Funotion: ExchangeDigit
XCHD exchangesthe low-ordernibbleof the Accumulator(bits 3-O),generallyrepresentinga
hexadecimalor BCD digit,withthat of the internal IGUkilocationindirectlyaddressedby the
sapp~ti=gister. me high-ordernibbles(bits 7-4) of each register are not af%cted.No tlsgs

Example: ROcontains the address 20H. The Accunndator holds the value 36H (OO11O1IOB).
Internal
W location 20H holdsthe value 75H (O111O1O1B). The instruction,

XCHD A,@RO

willleaveRAM location20Hholdingthe value76H(O111O11OB)

and 35H(OIM1O1O1B)
in the
Accumulator.
Bytes: 1
cycles: 1

Encoding: 1101 Olli

Operation: XCHD
(A~~) Z ((lti~~))

XRL <cleat-byte>, <src-byte>

Function: LogicalExclusive-ORfor byte vsriablea

Description: XRL performs the bitwiselogicalExcIusive-ORoperation between the indicated variables,
storing the results in the destination.No flags are affected.

The two operandsallowsixaddressingmode combinations.Whenthe destinationis the Accu-

mulator, the source can use register,direcL register-indirect,or immediateaddressing;when
the destinationis a direct address,the source can be the Accumulatoror immediate data.
(Note When this instructionis used to modifyan output port, the value used as the original
port dats will be read from the output data latch, not the input pins.)
Example: If the Accumulator holdsOC3H(11000011B)and register Oholds OAAH(101OIO1OB)
then
the instruction,

XRL A,RO
will leavethe Accumulator holdingthe vatue 69H (O11OIOOIB).
When the destinationis a directlyaddressedbyte this instructioncan complementcombina-
tionsofbitsinanyMM locationor hardwareregister.Thepatternofbitstobecomplement-
ed by a maskbyte eithera constsntcontainedin the instructionor a
ed is then determin
variable computedin theAccumulatorat run-time.Theinstruction,
XRL Pl,#OOllOOOIB
will complementbits 5, 4, and Oof output Port 1.

2-73
intJ MCS”-51 PROGRAMMER’SGUIDE AND INSTRUCTION SET

I(RL A,ml
Bytes: 1
Cycles; 1

Encoding: 0110 Irrr

Operation: XRL
(4+- (4 ~ (W

XRL A,direct
Bytes 2
Cycles: 1

Encoding: 10110101011 ] directaddress I

Operation: XRL
(A) + (A) V (direct)

XRL A,@Ri
Bytes: 1
Cycles: 1

Enwding: 0110 Olli

Operation:

XRL A,#data
Bytes: 2
Cycles: 1

Encoding: 0110 01001 I immediatedats I

Operation: XRL
(A) + (A) V #data

XRL tiire@A
Bytes: 2

cycles 1

Encoding: 0110 0010 direct address

Operation: XRL
(dinzt) + (direct) V (A)

2-74
 MCS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET

XRL dire@ #date

Bytea: 3
Cydea: 2

Encoding: 0110 0011 direct address immediate date

I
Operation: XRL
(direct)+ (direct) Y #data

2-75
8 and 80C51
0 53
Hardware Description
 8051,8052 and 80C51 Hardware Description

CONTENTS PAGE CONTENTS PAGE

INTRODUCTION ........................................ 3-3 INTERRUPTS ........................................... 3-23

Special Function Registers ......................... 3-3 Priority Level Structure ............................. 3-24
How Interrupts Are Handled ..................... 3-24
PORT STRUCTURES AND
OPERATION........................................... 3-6 External Interrupts .................................... 3-25
[/0 Configurations....................................... 3-7 Response Time. ........................................ 3-25
Writing to a Port .......................................... 3-7 SINGLE-STEP OPERATION.................... 3-26
Port Loading and Interfacing ...................... 3-8
Read-Modify-Write Feature ........................ 3-9 RESET...................................................... 3-26

ACCESSING EXTERNAL MEMORY.........3-9 POWER-ON RESET................................. 3-27

TIMEWCOUNTERS ................................... 3-9 POWER-SAVING MODES OF

OPERATfON ......................................... 3-27
Timer Oand Timer 1.................................. 3-10
CHMOS Power Reduction Modes ............ 3-27
Timer 2...................................................... 3-12
EPROM VERSIONS .................................3-29
SERIAL INTERFACE ............................... 3-13
Exposure to Light...................................... 3-29
Multiprocessor Communications .............. 3-14
Program Memory Locks ........................... 3-29
Serial Port Control Register ...................... 3-14
ONCE Mode ............................................. 3-30
Baud Rates...............................................3-15
More About Mode O.................................. 3-17 THE ON-CHIP OSCILLATORS ................3-30
More About Mode 1 .................................. 3-17 HMOS Versions ........................................ 3-30
More About Modes 2 and 3 ...................... 3-20 CHMOS Versions ..................................... 3-32
INTERNAL TIMING .................................. 3-33

3-1
 8051, 8052 AND 80C51
HARDWARE DESCRIPTION

INTRODUCTION ● The EPROMversionsof the 8051AH, 8052AHand

80C51BH
Thischapter preaents a comprehensivedescription of
the on-chip hardware featuresof the MCS@-51micro- The devicesunder considerationare listed in Table 1.
controller. Includedin this descriptionare As it becomesunwieldyto be constantly referring to
● The port drivers and how they function both as
each of these devicesby their individualnam~ we will
ports and, for Ports Oand 2, in bus operations adopt a convcmtionof referring to them genericallyas
8051sand 8052s,unlessa specificmemberof the group
● The Timer/Counters is beingreferred to, in which case it willbe specifically
● The Serial Interface named. The “8051s” include the 8051AH, 80C51BH,
● The Interrupt System
and their ROMlessand EPROM versions.The “8052s”
are the 8052AH,8032AHand 8752BH.
● Reset

. The ReducedPower Modesin the CHMOSdevices Figure 1showsa functionalblockdiagramof the 8051s
and 8052s.

Table 1.The MCS-51 Family of Mien ontroiiera

[ Devioe ROMleaa EPROM ROM
1 Name I Version Veraion
8751H, 8751BH
Bytes
4K
8051AH 8031AH
8052AH 8032AH 8752BH 8K
80C51BH 80C31BH 87C51 4K
m

SpecialFunctionRegisters
A map of the on-chipmemoryarea called SFR (SpecialFunctionRegister)spaceis shownin Figure2. SFRSmarked
by parentheses are residentin the 8052sbut not in the 8051s.

3-3
i~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

PO.O-PQ.7 P2.O-P2.7

B
mAo~:AAt
I
v REGISTER

mm?
I REG%TER
BUFFER

I
I r I I [ INCRE%NTE@
I
I PORTANDTIMER
BLOCKS
I
WA Ee
ALE TIMING :K’ I
>~
C2#%OL ~:
=-
RST
g

li~
I

P
POUT1 PORT3
I LATCH LATCH

/ ‘=
mmi Pom3
DRIVERS ORWERS
[ –-––– —————— —— ——— —,
XTAL1 X7AL2
w .. ‘Rddenli. 805s/s0320mJy.

4&JJ
=
P3,0-P1.7 P3,0-P3.7

270252-1

Figure 1. MCS-51 Architectural Block Diagram

3-4
 HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

8Bytes
F8 FF
FO B F7
E8 EF
EO ACC E7
lx DF
Do Psw , , 1 D7
C8 (T2CON) I (RCAP2L) (RCAP2H) I (-m) (TH2) CF
m 1. I 1 [ [ c?
S8 ,, BF
BO Ps B7
AS IE AF
AO m I I 1 1 I i 1 A7
98 S&N SBUF 9F
90 PI I I, II I1 II I, I1 97
88 T&N TMOD TLO TL1 THO THI I 8F
80 Po SP DPL DPH I PCON 87

Figure 2. SFR Map. (... ) Indicates Resident in 8052s, not in 8051s

Note that not all of the addressesare occupied.Unoc- to hold a 16-bitaddress. It may be manimdatedas a
cupied addreaaea are not implementedon the chip. id-bit register or as two ind~-dent 8-bit-registers.
Read accemesto theae addresseawill in general return
random da@ and write accesseswillhave no effect. PORTS O TO 3
User software should not write 1s to these unimple- PO,Pl, P2 and P3 are the SFR latches of Ports O,1,2
mented locations, since they may be used in future and 3, respectively.
MCS-51producta to invokenew features. In that case
the reset or inactive values of the newbits will always SERiAL DATA BUFFER
be O,and their active values willbe 1.
The Serial Data ButTeris actually two separate regis-
The fi.mctionsof the SFRSare outlinedbelow. ters, a transmit butTerand a receive butTerregister.
When &ta is movedto SBUF, it goes to the transmit
ACCUMULATOR buffer where it is held for aerial transmission.(Moving
ACC is the Accumulator register.The mnemonicsfor a byte to SBUF is what initiatea the transmission.)
Accmnulator-Speciticinstructions, however, refer to When data is moved from SBUF, it comes from the
the Accumulatorsimply as A. receivebuffer.

B REGISTER TIMER REGiSTERS

The B register is used during multiplyand divideoper- Register pairs (THO,TLO), (TH1, TL1), and (TI-D,
ations.For other instructionsit can be treated as anoth- TL2) are the id-bit Countingregistersfor Timer/Coun-
er scratch pad register. ters O, 1, and 2, reqectively.

PROGRAM STATUS WORD CAPTURE REGiSTERS

The PSWregister contains program status information The register pair (RCAP2H RCAP2L) are the Cap-
as detailedin Figure 3.
ture registetxfor the Timer 2 “Capture Mcde.” In this
mode, in responseto a transition at the 8052’sT2EX
STACKPOINTER pin, TH2 and TL2 are copied into RCAP2H and
The StackPointer Register is 8 bitswide.It is incre- RCAP2L. Timer 2 alsohas a 16-bitauto-reloadmode,
mentedbefore data is stored duringPUSH and CALL and RCAP2H and RCAP2Lhold the reload valuefor
executions.Whilethe stack mayresideanywherein on- this mode. More about Timer 2’s festures in a later
chip RAM, the Stack Pointer is initializedto 07H after section.
a reset. This causes the stack to beginat location08H.
CONTROL REGiSTERS
DATA POiNTER
Special Function Registers 1P, IE, TMOD, TCON,
The Data Pointer (IXTR) consists of a high byte T2CON,SCON,and PC(3Ncontain control and status
(DPH) and a low byte (DPL). Its intendedftmction is bits for the interrupt system,the Timer/Count~ and
the serial port. They are describedin later sections.

3-5
in~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

(MSB) (LSB)

I CY I AC FO Rsl I RSO Ov — P 1

symbol PoeJtlOn f&nseand

Slgniflemee Symbol PoaStlon Name and Slgnifiaanee
CY PSW.7 Calwflaa. Ov PSW.2 Overflow
fiag.
AC PSW.6 Ausii~-&yfleg. — Psw.1 Uaerd&fneMe flag.
(For SCD~rafiLWs.) P Psw.o Parifyfleg.
FO PSW.5 FlagO Saflclesred by hardwsm eaeh
(Availabletofhe uaerforgenersl insfmfion cycle to indicatean odd/
Pm-.) swannumber of “one” bits in the
RSI PSW.4 lWaterbsnk edectsontrol b~ I & Aecumulatw, i.e., even parity.
RSO PSW.3 O.Set/cleared tyadhssreto NOTE:
dstermineworking mgisterbank (see The contents of (RS1, RSO) enable the working register banks as
follows:
Note).
(0.0)-Bank O (OOH-07H)
(0.1)-Senk 1 (08 H-OFH)
(1.0)-Bank 2 (1OH-17H)
(1.1)-sank 3 (18H-lFH)

Figure 3. PSW: Program Status Word Register

AODR/OATA
READ
LATCH

INT.BuS
WRITE
TO
LATCH

REAO
PIN
270252-3
2702S2-2
B. Port 1 Bit
A. Porf OBit ALTERNATE
OUTPUT
FUNCTION
P.oon
CONTROL
Vcc
READ
LATCH

INT.BuS
WRITE
TO d
LATCH

REAO
PIN -.
FUNCTION
270252-4
270252-5
C. Port 2 Bit D. Port 3 Bit
Figure 4.8051 Port Bit Latches and 1/0 Buffers
*SeeFigure5 for detailsof the internal pultup.

PORT STRUCTURESAND external memory addres3, time-multiplexedwith the

OPERATION byte beingwritten or read. Port 2 outputs the highbyte
of the external memoryaddress when the address is 16
AUfour ports in the 8051are bidirectional.Each con- bits wide. Otherwisethe Port 2 pine continue to emit
sists of a latch (SpecialFunction Regietera PO through the P2 SFR content.
P3), en output driver, and an input buflkr.
All the Port 3 pina,and (in the 8052)two Port 1 pins
The output driversof Ports Oand 2, and the input butF- are multifunctional.They are not onfy port pins, but
era of Port O,are used in ameaaesto external memory. afao serve the functionsof various special featurea as
In this application,Port Ooutputs the low byte of the listed on the followingpage.

3-6
in~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Port Pin Alternate Function ADDIVDATA BUS).To be usedas an input, the port
“P1.o T2 (Timer/Counter2 bit latch must contain a 1, which turns off the output
externalinput) driver FBT. Then, for Ports 1, 2, and 3, the pin is
*P1.1 T2EX(Timer/Counter2 pulled high by the internal puflup,but can be pulfed
low by an external source.
Capture/Reloadtrigger)
P3.O RXD (serialinputport) Port Odiffersin not havinginternsdpullups.The ptiup
P3.1 TXD (serialoutputport) FBT in the POoutput driver (seeFigure4) is used onfy
P3.2 INTO(externalinterrupt) when the Port is ernitdng 1s during external memory
P3.3 ~ (externalinterrupt) accasea otherwise the pullupFET is off. Conaequent-
P3.4 TO (Timer/CounterOexternal Iy POlima that are being used as output port lines are
input) open drain. Writing a 1 to the bit latch leaves both
P3.5 T1 (Timer/Counter I external
output FETs off, so the pin floats. In that conditionit
input)
can be used a high-impedanceinput.
P3.6 ~ (externalData Memory BecausePorts 1, 2, and 3 have fixed internaf pullups
write strobe) they are sometimescalled “qussi-bidirectional”porta.
P3.7 ~ (external DataMemory Whets eontigured as inputs they pull high and will
readstrobe) sourcecurrent (IIL, in the data sheets)whenextemafly
pulled low. Port O, on the other hand, is considered
●P1.Oand P1.1 serve these aftemate fuctions onlyon “true” bidirectional,becausewheneont@red as an in-
the 8052. put it floats.
The alternate functionscan onlybe activatedif the cor- Affthe port latches itsthe 8051have 1swritten to them
respondingbit latch in the pm-tSFR containsa 1.0th- by the reset function.If a Ois subsequentlywritten to a
erwise the port pin is stuck at O. port latch, it can be reconfiguredas an input by writing
a 1 to it.

1/0 Configurations
Writingto a Port
Figure 4 shows a fictional diagram of a typical bit
latch and 1/0 buffer in each of the four ports. The bit In the executionof an instructionthat changesthe val-
latch (one bit its the port’s SFR) is represented as a ue in a port latch, the new value arrives at the latch
Type D tlipflop, which will clock in a value from the during S6P2of the final cycleof the instruction. How-
internal bus in response to a “write to latch” signal ever, port latches are in fact sampledby their output
from the CPU. The Q output of the tlipflop is placed buffers O~Y during Phase 1 of SSlyclock period. @IK-
on the intersttdbus itsresponseto a “read latch” signal ittg Phase 2 the output buffer holds the value it saw
from the CPU. The levelof the port pin itselfis placed during the previous Phase 1). Consequently,the new
on the internal bus in response to a “read pin” signal value in the port latch won’t actually appear at the
from the CPU. Someinstructionsthat read a port acti- output pin until the next Phase 1,whichwillbe at SIP1
vate the “read latch” signal, and others activate the of the next machinecycle.SeeFigure39in the Internal
“read pin” signal.More about that later. Timingsection.

As shownin Figure4, the output drivers of Ports Oand If the changerequiresa O-to-1transitionin Port 1,2, or
2 are switchableto an istternrdADDR and ADDR/ 3, art additional pullup is turned on during SIP1 and
DATA bus by an internal CONTROLsignalfor w its S1P2of the cyclein whichthe transitionocmu-s..This is
external memoryaccesam.During external memoryac- done to increasethe transition speed.The extra pullup
cesses,the P2 SFR rcsrm“nsunchanged,but the POSFR can sourceabout 100timesthe current that the normal
gets 1s written to it. pullup can. It shouldbe noted that the internal pttllups
are field-effecttransistors, not linear resistors.Tlseptdl-
Nso shownin Figure4, is that ifa P3 bit latch contains up -CInCntS are shownin Figure 5.
a 1, then the output level is controlled by the signal
labeled “alternate output function.” The actual P3.X In HMOS veraionsof the 8051,the fixed part of the
pin levelis afwaysavailableto the pin’salternate input pullup is a depletion-modetransistor with the gate
function, if any. wiredto the source.This transistorwillallowthe pin to
source about 0.25 mA when shorted to ground. In
Ports 1,2, and 3 have internal puUups.Port Ohas open parallel with the fixed pullupis assenhancement-mode
drain outputs.Each I/O line ean be independentlyused transistor, which is activated during S1 wheneverthe
as an input or an output. (Ports O and 2 may not be port bit doesa O-to-1transition.Duringthis intervaf,if
used as general purpose I/O whetsbeing used as the the port pin is shorted to ground,this extra transistor
will allowthe pin to sourcean additional30 sttA.
3-7
intd. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Vcc

Vv,,
270252-6
A. HMOS Configuration. The enhancement mode transistor
is turned on for 2 OSC.periods after~ makes a O-to-1 transition.
‘JCc WC %c

2 OSC.PERIODS

PI

n 1’- ‘
6 D
FROMPORT
LATCH

=-’@-’@
D-J
“AD
PORTPIN
270262-7
B. CHMOS Configuration. pFET 1 is turned on for 2 OSC.periods after~
makes a O-to-1transition. During this time, pFET 1 also turns on pFET 3
through the inverter to form a latch whioh holds the 1. pFET 2 is also on.

Figure 5. Porta 1 And 3 HMOS And CHMOS Internal Pullup Configurations.

Port 2 is Similar Exoept That It Holds The Strong Pullup On While Emitting
1s That Are Address Bits. (See Text, “Acceaaing External Memory”.)

In the CHMOSversions,the pullup consists of three Port Loadingand Interfacing

DFETs. It shordd be noted that an n-channel FET
@ET) is turned on wherea logical 1 is applied to its The output buffersof Porta 1,2, and 3 ean each drive4
gate, and is turned off whena logicalOis appliedto its LS TTL inputs. These porta on HMOSversionscan be
gate. A p-channelFET (pFET) is the opposite:it is on drivenin a normal manner by any ITL or NMOS cir-
when its gate seesa O,and off when its gate sees a 1. enit. Both HMOS and CHMOS @lS can be dliVell by
open-collectorand open-drainoutputs, but note that O-
pFETl in Figure5 is the transistor that is turned on for to-1transitions will not be fast. In the HMOSdevi~ if
2 oscillatorperiodsafter a O-to-1transition in the port the pin is driven by an open-cdleetor output, a O-to-1
latch. While it’s on, it turns on PFET3 (a weak pull- transition will have to be drivenby the relativelyweak
UP),throughthe inverter.This inverterand pFET form depletionmode FET in Figure 5(A). In the CHMOS
a latch whichhold the 1. device,sssinput OtllmSOffpldklppFET3, kwislg Only
the very weak pullup pFET2 to drive the transition.
Note that if the pin is emittinga 1, a negativeglitch on
the pin from someexternal sourceean turn off PFET3, In external bus mode, Port Ooutput buffers can each
causingthe pin to go into a float state. pFET2 is a very drive8 L3 ITL inputs. As port pins,they require exter-
weak pullup whichis on wheneverthe nFET is off, in nal pultups to drive any inputs.
traditional CMOSstyle.It’s onlyabout ‘/10the strength
of pFET3.Its functionis to restorea 1 to the pin in the
event the pin had a 1 and lost it to a glitch.

3-8
i~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Read-Modify-WriteFeature Whenevera id-bit addressis used, the highbyte of the

address comes out on Port 2, where it is held for the
Someinstructions that read a port read the latch and duration of the read or write cycle.Note that the Port 2
others read the pin. Whichonesdo which?The instruc- drivers use the strong pullups during the entire time
tionsthat read the latch rather than the pin are the ones that they are emittingaddress bits that are 1s. This is
that read a value possiblychangeit, and then rewrite it duringthe executionof a MOVX@DPTRinstruction.
to the latch. These are called “read-modify-write”in- Duringthis time the Port 2 latch (the SpecialFunction
structions.The instructionslisted beloware read-mod- Register)does not haveto contain 1s,and the contents
ify-writeinstructions. When the destinationoperand is of the Port 2 SFR are not modified,If the external
a wrt, or a PII bit, these instructions read the latch memory cycle is not immediatelyfoflowedby another
rather than the pin: external memorycycle,the undisturbedcontentsof the
ANL (logicalAND, e.g., ANL PI, A) Port 2 SFR will reappearin the next cycle.
ORL (logicalOR, e.g., ORL P2, A) If an 8-bit address is being used (MOVX @Ri), the
XRL (logicalEXIOR,e.g., XRL P3, A) contents of the Port 2 SFR remain at the Port 2 pins
throughoutthe externafmemorycycle.This will facili-
JBC (jump if bit = 1 and clear bit, e.g., tate paging.
JBC P1.1, LABEL)
CPL (complementbit, e.g., CPL P3.0) In any case, the low byte of the address is time-muki-
plexed with the data byte on Port O. The ADDR/
INC (increment,e.g., INC P2) DATA signal drives both FETs in the Port O output
DEC (decrement,e.g., DEC P2) buffers.Thus, in this applicationthe Port Opins me not
DJNZ (decrernent and jump if not zero, e.g., open-drainoutputs, and do not require external pull-
DJNZ P3, LABEL) ups. Signal ALE (Address Latch Enable) shoufd be
usedto capture the addressbyte into an external latch.
MOV,PX.Y, C (movecarry bit to bit Y of Port X) The address byte is valid at the negativetransition of
CLR PX.Y (clear bit Y of Port X) ALE. Then, in a write cycle,the data byte to be written
SETBPX.Y (set bit Y of Port X) appears on Port Ojustbrrm ~ is activated,and re-
mains there until after WR is deactivated. In a read
It is not obviousthat the fast three instructions in this cycle, the incomingbyte is accepted at Port Ojust be-
list are read-modify-writeinstructions, but they are. fore the read strobe is deactivated.
Theyread the port byt%all 8bits, modifythe addressed Duringany accessto externalmemory,the CPU writes
bit, then write the new byte back to the latch. OFFHto the Port Olatch (the SpecialFunction Regis-
ter), thus obliteratingwhateverinformationthe Port O
The reason that read-modify-writeinstructions are di- SFRmay havebeenholding.If the user writeato Port O
rected to the latch rather than the pin is to avoid a during an external memory fetch, the incomingcode
possiblemisinterpretation of the voltage level at the byte is corrupted. Therefore,do not write to Port O if
pin. For example,a port bit mightbe used to drive the external program memoryis used.
base of a transistor. When a 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same External Program Memoryis amessedunder two con-
port bit at the pin rather than the latch, it will read the ditions:
base voltage of the transistor and interpret it as a O. 1) Wheneversignal= is active; or
Reading the latch rather than the pin will return the
correct vafue of 1. 2) Whenever the program counter (PC) contains a
number that is larger than OFFFH(WFFH for the
8052).
ACCESSING EXTERNAL MEMORY This requiresthat the ROMleasversionshave~ wired
lowto enablethelower4K (8Kforthe 8032)program
Accessesto external memoryare of two types: accewes bytes to be fetched from extemafmemory.
to external Program Memoryand amesaes to external
Data Memory. Accessesto external program Memory When the CPU is executingout of external Program
use signal PSEN (program store enable) as the read Memory,all 8 bits of Port 2 are dedicatedto an output
strobe. Accesses to external Data Memory use ~ or fimctionand may not be used for generalpurposeI/O.
~ (alternate functionsof P3.7and P3.6) to strobe the During external program fetches they output the high
memory.Refer to Figures36through38 in the Internal byte of the PC. Duringthis time the Port 2 drivers use
Tintingsection. the strong pullups to emit PC bits that are 1s.

Fetches from externrdProgram Memory always use a

16bit address. Accessesto external Data Memory can TIMER/COUNTERS
use either a l~bit address (MOVX @DPTR) or an The 8051has two 16-bitTimer/Counterregisters:Tim-
8-bitaddress (MOVX @w). er O and Timer 1. The 8052has these two plus one
3-9
int& HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

more:Timer 2. AUthree can be ccmflgurecito operate four operatingmod- which are selectedby bit-pairs
either as timers or event counters. (M1. MO)in TMOD. Modes O, 1, and 2 are the same
for both Timer/Counters.Mode 3 is different.The four
In the “Timer” function, the register is incremented operatingmodesare describeditsthe followingtext.
everymachinecycle.Thw onecan think of it as count-
ingmachinecycles.Sincea machinecycleconsistsof 12
oscillatorperiods,the count rate is 1/,, of the oscillator MODEO
frequency. EitherTimerin ModeO is an 8-bit Counter with a
divide-by-32preacaler. This 13-bit timer is MCS-48
In the “Counter” timction, the register is incremented compatible.Figure 7 showsthe Mode Ooperationas it
in responseto a l-to-Otransition at its corresponding appliesto Timer 1.
externrdinput pin, TO,T1 or (in the 8052)T2. In this
timction,the externalinputis sampledduring S5P2of In this mode, the Timer regiater is configured as a
everymachine cycle.When the samplesshowa high in 13-Bitregister.As the count rolls over fromail 1sto ail
onecycleand a lowin the nextcycle,the countis incre- 0s, it sets the Timer interrupt flag TF1. The cmnted
mented. The new count value appeara in the register input is enabledto the Timer whenTR1 = 1and either
duringS3P1of the cyclefollowingthe one in whichthe GATE = Oor ~ = 1. (SettingGATE = 1 aflows
transitionwas detected.Sinceit takes 2 machinecycles the Timer to be controlledby externafinput INT1, to
(24 oscillator periods)to recognizea l-to-Otransition, facilitate pulse width measurements.)TRl is a control
the maxiMuMcount rate is 2/24of the oaciliator fre- bit in the SpeciafFunction Register TCON (Figure 8).
quency.There are no restrictions on the duty cycle of GATE is in TMOD.
the external input signaf, but to ensure that a given
level is sampled at least once before it changes, it The 13-Bitregister consistsof ail 8 bits of THl and the
shouldbe held for at least one full machinecycle. lower 5 bits of TL1. The upper 3 bits of TLl are ittde-
terminate and shouIdbe ignored. Settingthe run flag
In addition to the “Timer” or “Counter” selection, (’TR1)doesnot clear the registers.
Timer Oand Timer 1 have four operatingmodesfrom
whichto select. Timer 2, in the 8052,has three modes ModeOoperationis the same for Timer Oas for Timer
of operation: “Capture,“ “Auto-Relrxid”and “baud 1. SubstituteTRO,TFOand ~ for the correspond-
rate generator.” ing Timer 1sigmdsin Figure 7. There are two dif%rent
GATE bia one for Timer 1 (TMOD.7) and one for
Timer O(TMOD.3).
TimerOand Timer 1
TheaeTimer/Counteraarepreaent in both the 8051and MODE 1
the 8052.The “Timerr’or “Counter” functionis aelect-
ed by control bits Cfl in the SpeciaiFunctionRegister Mode 1 is the same as Mode O,except that the Tima
TMOD (Figure 6). These two Timer/Countem have registeris beingrun with all 16bits. -

(MSB) (LSB)
GATE C/T I Ml I MO I GATE C/7 I Ml MO
A
Timer 1 Timer O
Gadng
conrrol
whensaLTirnar/Countar “x” is anablad WI MO Opamtfng Mode
cmlywhilempin is hiohand “TRx’”mntrol pinis o 0 S-bitlimar/@ntar’’THX” with.<TIJ,, as ~it
set When cberedTimaf “x” is anabledwharfaver prese%r.
“7Rx” eontrolbitkeat. o 1 IS-bil T!mar/Ccunter 4“THx’,and 4.TIX am
Timaror CounterSalaetor daaradfor Timer opwstiOn cascadad; there is no ~r.
(inwtfromifttmelwetafn ebek). sattorcountar 1 0 S-bitauto-reloadTimSr/~ntar “THx” holdsa
Won (inputfrom “Tx” inputpin). value whichis toba reloadad info“TLx” asch
time it OYWIIOWS.
1 1 (i_knwO)TLOisanS-bitTimer/Counter
mntrolled by the st@ard Timar Ocontrolbti.
THOisanB-bit
Wwr@rmntdld bytimarI
Centml
Ms.
1 1 flimerl) 7imer/Ccunter 1 stcopad.

Figure 6. TMOD: Timer/Counter Mode Control Register

3-1o
i~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Osc

‘ ICOJTROL’(5%
’J:L’H
[A I
k
‘F’
INTERRUPT

270252-9

Figure 7. Timer/Counter 1 Mode O:13-Bit Counter

(MSB] (LSB)
[ TFl TRl TFo TRO IE1 IT1 IEO ITO

symbol POaltlon Nelnesnds@meanm -1 Posltlon Neme mdslgnlffcenm

TF1 TCON.7 llner 1 overflowFlag. Set by IE1 Tc%+J.3 Interrupt1 Edgs flsg. Sstbyhardwsre
hardware on Tw/Counter overflow. when external intenupt~ge
Cleared byherdwerewtten proc- deteeted. Cfesmdwhen interrupt
veetorsto intemuptroutine. prmeesed.
TR1 TmN.6 l%ner 1 Run eontml biLSet/cleared IT1 TCON.2 Intenupt 1 Type mntrd bk Set/
by sottwsreto tum Tkn6f/Counte?WI elearadbyaofttnr etoapecifyfsiiing
off. sdgdbw level biggwadesternel
interrupts.
TFo TCON.5 Timer Oovsrfiow Flag.Set by
herdwsreon Timef/Camter overflow. IEO TU)N.1 lntenuptOEdgsfleg. Set byhsrdwsre
Cleared byhsrdware whan pmmee.or when external intsfruptedge
veetorsto intemuptmutine. detected. Cleared * interrupt
TRO TCON.4 Timer ORuncontml ML SatJcleared ~.
byeoftwareto tum Timer/Counter on/ ITO TCON.O InterruptOTyPSmntrol biLSet/
off, cleared by sdtwereto speeifyfslling
ed@k3wlevel tr@geredexternsl
interrupt

Figure 8.TCON: Timer/Counter Control Register

MODE 2 Timer O in Mode 3 establieheaTLOand THOas two

separate counters.The logicfor Mode 3 on Timer Ois
Mode2 configures theTimerregisterasan 8-bitCoun- sh_own
inFigure10.TLO&estheTimerOcontrolbits:
ter (’TLl)with automatic reload, as shownin Figure 9. Cfi, GATE,TRO,INTO,and TFO.THOis lockedinto
OverfiowfromTL1 not only sets TFl, but also reloads a timer function (counting machine cycles)and takes
TL1 with the contentsof THl, which is preset by aoft- over the useof TR1 and TFl fromTimer 1.Thus THO
ware. The reload leav~ THI unchanged. now controlsthe “Timer 1“ interrupt.

Mode 2 operationis the same for Timer/Counter O. Mode 3 is providedfor applicationsrequiringan extra
8-bit timer or counter. With Timer o in Mode 3, gIL
8051ean looklike it has three Timer/Counte~ and an
MODE 3 8052, like it has four. When Timer O is in Mode 3.
Timer 1in Mode3 simplyholds its count.The effeetis Tim~ 1 een be tinned on and off by switchingit out of
the ssrne as setting TRl = O. and into its own Mode 3, or esn still be used by the
serial DOrtae s baud rate mnerstor, or in fact, in any
appli~tion not requiring& iaterru~t.
3-11
 HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

[M
CIT. o

., PINJ*” ‘ROL~ INTERRUPT

270252-10

Figure9. Timer/Counter1 Mode 2: 8-Bit Auto-Reload

EI--EI-’’”SC”SC
11121~’~

/t I — INTERRUPT
.PIN~fi=l 1 ‘
CONTROL

1/12 1“’~ Id’ _ INTERRUPT

~

I CONTROL
TR1
~
270252-11

Figure 10. Timer/Counter OMode 3: Two 6-Bit Countere

Timer2
Table 2. Timer 2 Operating Modea
Timer 2 is a 16-bit Timer/Counter which is present
only in the 8052.Like Timers Oand 1, it can operate IRCLK + TCLKlCPI~lTR21 Mode
either as a timer or as an eventcounter. Thisis selected o 0 1 16-bitAuto-Reload
by bit Cm in the SpecialFunction Register T2C0N o 1 1 16-bitCapture
(Figure 11).It haa three operating modes: “capture,” 1 x 1 Baud Rate Generator
“autdoad” and “baud rate generator,” which are se-
lectedbybitsin T2CONas shownin Table2.

3-12
i~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

(MSB) (Lss)
TF2 EXF2 I RCLK TCLK EXEN2 I TR2 cm cPlm 1
symbol POaRion Named Signllkenw

TF2 T2CX3N.7 Timer 20vedlowflag ~bya Tiir2 ovarflowand mustbe cleeredbyaoffwara.

TF2will not be astwtsen eW@rRCLK = 1 orTCLK = 1.
EXF2 T2CON.6 limer2exfemal flag eetwheneifhar a eapfura orraload iseaumd bya negative
t~SifiOn on T2EX and EXEN2 = 1. When Tirrwr2 interruptiaenablad, EXF2 = 1
will eauaafha CPU toveeforte tha T}mer2 intarruptrwtine. EXF2 must be
cfeared trysoftware.
RCLK T2CON.5 Raeeivecloek ffsg.When eat, eausesthe aerfal porttouee Tirnw2 overflow
pulseaforits raceiva clookin Modaa 1 and 3. RCLK = Oeauaaa Timer 1 ovarlfow
to be @ ferfha raeeive Clock.
TCLK T2CON.4 Transmitclock flag.Whenaat, eaueeethe aafisl port to uee Timw2 overflow
puleeafwitat ranemit deck in modes 1 and 3. TCLK = OcaueeaTmer 1
overflcws to ba uaad for fhefranamif deck.
EXEN2 T2CON.3 Tirnar2 external enebleffag. When set, allows aeapfure o+raleedtoooeures a
result ofa negativatranaifiemon T2EX ifllnar2 is not beinguaadto eiockthe
til PM. EXEN2 = Ocausea Timar2 to ignoreevenfset T2EX.
TR2 T2mN.2 Start/atop cmItrolfor Timar2. A logic 1 afarta Usatimer.
CII’2 T2CZ)N.1 Timarorcountaraalect flimer2)
O = Internaltimar (OSC/12)
1 = ~1 event muntar (fallingedgetrfggered).
cP/m T2c0N.o Captwe/RaloadflW. Wheneet ~tureawillr rccuronnagstivet renaifions et
T2EX if EXEN2 = I.When eiaarad, aufo.ralosdswill occuraifherwithTimer2
overflowsor nSgatiVetranaifiorreatT2EX wlwn EXEN2 = 1. When eifher RCLK
= 1 or TCLK = 1, this bfiis ignciad and the timer is foreed foeute-rafoedem
Timar20verflew.

-. . . ———-.. —. .-
Figure 11. TZCON: Timer/Counter 2 Control Register
In the Capture Mode there are two options which are added feature that a l-to-o transition at external irmfrt
selected by bit EXEN2 in T2CON. If EXEN2 = O, T2EX will alaotrigger the id-bit reload and set E&2.
then Timer 2 is a Id-bit timer or counter which upon
overtlowingeeta bit TF2, the Timer 2 overflowbit, The auto-reloadmede is ilfuetratedin Figure 13.
which can be used to generatean interrupt. If EXEN2
= 1, then Timer 2 still does the above, but with the The baud rate generatormodeis selectedby RCLK =
added feature that a l-to-Otransition at external input 1 and/or TCLK = 1. Itwill bedescribedin ecmjunc-
T2EX causesthe current valuein the Timer 2 registers, tion with the aerial port.
TL2 and TH2, to be captured into registers RCAP2L
and RCAP2H, respectively.(RCAP2L and RCAP2H
are new Special Function Registers in the 8052.) In SERIAL INTERFACE
addition, the transition at T2EX causes bit EXF2 in
T2CONto be set, and EXF2,like TF2, an generateen The seriaf port is full duplex,meaningit can transmit
interrupt. and receive eimultarseously.It is aleo receivebutTered,
meaning it can commencereception of a second byte
The Capture Modeis illustrated in Figure 12. before a previouslyreceivedbyte has beersresd from
the reeeive register. (However,if the tirat byte still
In the auto-reloadmcdethereare againtwo options, hasn’tbeenreadby the timereceptionof the second
which are selected by bit EXEN2 in T2CON. If byte is completq one of the bytes wilf be lost). The
EXEN2 = O,then whenTimer 2 rolla over it not only serial port receive end transmit registers are both ac-
sets TF2 but also causes the Timer 2 registers to be ceeaedat SpeeialFunctionRegister SBUF.Writing to
reloaded with the l~bit va2uein registera RCAP2L SBUF loada the transmit register, and reading SBUF
and RCAP2H,whichare presetby software.If EXEN2 aeceeeeaa physieaflyseparatereceiveregister.
= 1, then Timer 2 still does the above, but with the

3-13
 irrtd. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Sxlins
270252-12
Figure 12. Timer 2 in CaptureMode

The serial port can operatein 4 modes: MultiprocessorCommunications

Mode O: Serial date enters end exits through RXD. Modes 2 end 3 have a special provisionfor muMpro-
TXD outputs the shift clock.8 bits are tranamittext/re- ceasorcommunications.In these mod- 9 data bita are
ceived:8 date bits (LSBftrat).The baud rate is tixed at received.The 9th one goea into RB8. Then comes a
1/12 the oscillator frequency. stop bit. The port can be programmedsuch that when
the stop bit is received,the aerialPrt interrupt will be
- Mode 1: 10bits are transmitted (through TXD) or re- activated only if RB8 = 1. This feature is enabled by
ceived(through RXD): a start bit (0), 8 data bits (LSB setting bitSM2in SCON. A wayto use this fmture in
first), and a stop bit (l). On receive+the stop bit goes multiprocessorsystems is 22folfows.
into RB8 in Special Function Register SCON. The
baud rate is variable. Whenthe master proceaaor wantsto trananu“ta blockof
data to one of several slaves, it firat sends out an ad-
Mode 2: 11bits are transmitted (through TXD) or re- dress byte which identifiesthe target slave.An address
ceived(through RXD): a start bit (0), 8 data bits (LSB byte differsfroma data byte in that the 9tb bit is 1in en
fret), a programmeble 9th data bit, and a stop bit (l). eddress byte and Oin a data byte.With SM2 = 1, no
On Transmit, the 9th data bit (TB8 in SCON)can be slave will be interrupted by a date byte. An eddreas
eaaignedthe valueof Oor 1.Or, for example,the parity byte, however, will interrupt elf slav= so that each
bit (P, in the PSW) coufdbe moved into TB8. On re- alevecan exsmine the receivedbyteend seeifit is being
ceive,the 9th data bit goesinto RB8 in SpecialFuncton eddreaaed.The addressed slave will clear ita SM2 bit
RegisterSCON,whilethe stop bit is ignored.The baud end prepare to remive the data bytesthat will be com-
rate is programmableto either ‘/”2or ‘\e4the oscillator ing. The slaves thatweren’tbeingaddressedleave their
frequency. SM2Sset and go on about their business,ignoringthe
comingdata bytes.
Mode 3: 11bits are transmitted (through TXD) or re- SM2 has no effect in Mode O,and in Mode 1 can be
ceived(through IUD): a start bit (0), 8 data bits (LSB
used to check the validityof the stop bit. In a Mode 1
first), a programmable9th data bit and a stop bit (l). In reception,ifSM2 = 1, the@ve interruptwillnotbe
fac~ Mode 3 is thesameesMode 2 in all reapeeta activated unlessa vatid atop bit is received.
except the baud rate. The baud rate in Mode 3 is veri-
able.
SerialPortControlRegister
In all four modes, transmissionis initiated by any in-
struction that uses SBUFes a destinationregister.Re- The serialport control end status registeris the Speciaf
ception is initiated in ModeOby the conditionRI = O Function Register SCON, shown in Figure 14. This
and REN = 1. Reception is initiated in the other register mntains not only the mode selectionbits, but
modesby the incomingstart bit if RBN = 1. also the 9th data bit for transmit and receive(TB8and
RB8), and the aerial port interrupt bits (TTand RI).

3-14
intd. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

l++ +12

TR2

nEmAO

-R 2
llslEmnlWr
Max PfN

axaNa

270252-13

Figure 13. Timer 2 in Auto-Reload Mode

(MSB) (LSB)
SMO SM1 SM2 REN I TB8 I RSS ] n I RI

Where SMO, SM1 epeeify the aefial pommode, as follows: ● TSS ie the Sthdate bifthetwill be
bans- in Modaa2 end3. % or
SMO aMl mode Deeerfpnorl Scud Rate
dear byaoftwareaa rtaairad.
o 0 0 Shiftragiatar f=flz
1 vadable ● RSS in Modes 2and 3, iatha Sthdata bit
o 1 S-bifUART
thatwes received. In Mode 1, ifSM2
1 o 2 9-bit UART f-/s4
= O,RSS iethe atopbitthet wea
or
f=,/32 received. In MOdeO,RS3 is rrotuaed.
1 1 3 9-btuARTvenable ● TI iewenemif irstarruptflag.Set by
hardsrareatthe end ofttw8th bittime
s SM2 enebleethe muftipromaeor
communieatfonfeature in Modes 2 in M*O, oratthe beginningof the
and 3.InM*20r3, if SM2isaetto *P bit in the offwrrnodes,in any
1 than RI willnotbaactf.mtad if the aerieffmnamieaion.Muetbecleared
received 3th date bit(R*) iaO. In byaoftware.
Mode 1, if SM2 = 1 then RI willnot
● RI is receive irsferruptflag.Sat by
baatited ifavalid stop bhwea not
recefvad. In Mode O,SM2 ahouldbe herdware atthe end of thesth bit time
o. in Mode O,or helfweythrcrughthe atop
b4ttirrwin the other modes,inany
● REN enableeaeriel reqstion. %by
eoftwareto enable raoaption.Clear serial recefdkm (exoepta8a SM2).
byeoftwaretodieeble raee+stkm Muaf be Cia byeoftwere.

—. . ----- - . . — — —
Figure 14. SCON: Serial Port Control Register

The baud rate in Mode Ois tlxed: 2SMOD

Mode 2 BaudRate= ~X(Oscillator Frequency)
OscillatorFrequency
ModeOBaud Rate =
12 In the 8051.the baud ratea in Modes1and 3 are deter-
minedby the Timer 1 overflowrate. In the 8052,these
The baud rate in Mode 2 dependeon the value of bit baud ratea earsbe determinedby Timer 1, or by Timer
SMODin SpecialFunction RegisterPCON. If SMOD 2, or by both (one for transmit end the other for re-
= O(whichis the valueon reset),the baud rate % the eeive).
oaeillatorfrequency.If SMOD = 1, the baud rate ie
%2 the oscillatorfrequency.

3-15
i~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

UsingTimer 1 to Generate Baud Rates mode (high nibbleof TMOD = OO1OB), In that ease,
the baud rate is givenby the formula
When Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 are determined by the Modes 1, 3 2SMOD~ OscillatorFrequency
Timer 1 overflowrate and the valueof SMOD as fol- BaudRate = —
32 L% [256- (THI)I
lows:
ModesL 3 2SMOD One ean achievevery low baud rates withTimer 1 by
BaudRate = — X (Timer 1OverflowRate) leavingthe Timer 1 interrupt enabl~ and mntlguring
32 the Timer to run as a 16-bit timer (hish nibble of
TMOD = OOOIB), and using the TiM~ I_interruptto
The Timer 1 interrupt shouldbe disabledin this appli- do a lti-bit softwarereload.
cation. The Timer itself can be configuredfor either
“timer” or “cormter” operation, and in any of its 3 Figure 15lists variouseommordyused baud rates and
running modes. In the most typioaiaprdication~ it is how they can be obtsined from Timer 1.
contl~ed for “timer” operati6n, in ‘the auto-reload

Timer 1

I Saud Rate

Mode OMax:1 MHZ

I f~c

12 MHZ
SMOD

x
Cfl
T
Mode
x
Reload
Value
x
Mode2 Msx:375K 12 MHZ 1 x x x
Modes 1,3: 62.5K 12 MHZ 1 o 2 FFH
19.2K 11.059 MHZ 1 0 2 FDH
9.6K 11.059 MHZ o 0 2 FDH
4.8K 11.059 MHZ o 0 2 FAH
2.4K 11.059 MHZ o 0 2 F4H
1.2K 11.059 MHZ o 0 2 E8H
137.5 11.986 MHZ o 0 2 lDH
110 6 MHZ o 0 2 72H
110 12 MHZ o 0 1 FEEBH
Figure 15.Timer 1 Ganerated Commonly Ueed Baud Rates

Using Timer 2 to Generate SaudRates 11).Note then the baud rates for transmit and reoeive
can be simultaneouslydifferent.SettingRCLK and/or
In the 8052,Timer 2 is selectedas the baud rate genera- TCLK puts Timer 2 into its baud rate generatormode,
tor by setting TCLK rind/or RCLKin T2CON (Figure as shownin Figure 16.

piol?:lxcmm ls- Svam’rlz r+l+2

k.
“ ---amo
i

2!3?’
.,” .W,

Inm Mm -- ---

.,’ mx-
.1,, “o-
------

r=
-— +,’ ‘1’ XCLOCK

““-=’ L.z.——— 270252-14

Figure 16. Timer 2 in Saud RateGeneratorMode

3-16
in~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

The baud rate generatormode is similar to the auto-re- Trsnamissionis initiated by any instruction that uses
loadmcde, in that a rolloverin TH2 causesthe Timer 2 SBUF as a destinationregister. The “write to SBUF’
registerstObe reloadedwith the Id-bit vahsein registers signalat S6P2also loadsa 1into the 9th positionof the
RCAP2Hand RCAP2L,which are preset by software. transmit shift registerand tells the TX Controlblockto
commencea transmission.The internal timing is such
Now, the baud rates in Modes 1 and 3 are determined that one till machine cycle will elapse between“write
by Timer 2’soverflowrate as follows: to SBUF,” and activationof SEND.
Timer 2 @clfiow Rate SEND enables the output of the shift register to the
Modes 1,3 BaudRate = alternate output functionline of P3.0, and sdsoenables
16
SHIFf CLOCKto the alternate output functionline of
The Tim= can be configured for either “timer” or P3.1. SHIPT CLOCK is low during S3, S4, and S5 of
“counter” operation.In the most typicalapplications,it everymachinecycle,and high during S6,S1and S2.At
is configuredfor “timer” operation(C/T2 = O).“Tim- S6P2of everymachinecycle in which SEND is active,
er” operationis a fittle different for Timer 2 when it’s the contents of the transmit shift register are shiftedto
being used as a baud rate generator. Normally, as a the right one position.
timer it wouldincrement every machine cycle(thus at As data bits shift out to the right, zeroescomein from
Y,, the mdlator frequency). Asa baud rate generator, the left. Whenthe MSBof the data byte is at the output
however,it incrementsevery state time (thus at ~, the positionof the shift register, then the 1that was initial-
oscillatorfrequency).In that case the baud rate is given Iy loaded into the 9th position,is just to the left of the
by the formula MSB,and all positionsto the left of that containzeroes
Mcdes 1,3 This condition flags the TX Control block to do one
OscillatorFrequency last shitl and then deactivateSEND and set TL Bothof
‘aud ‘te = 32x [65536– (RCAP2H,RCAP2L)1 these actions occur at SIP1 of the loth machinecycle
after “write to SBUF.”
where (RCAP2H, RCAF2L) is the content of
RCAP2Hand RCAP2Ltaken as a Id-bit unsignedin- Receptionis initiated by the condition REN = 1 and
teger. R1 = O.At S6P2of the next machine cyclq the RX
Control unit writes the bits 11111110to the receive
Timer 2 as a baud rate generatoris shownin Figure 16. shift register,and in the next clock phaseactivatesRE-
This Figure is valid only if RCLK + TCLK = 1 in CEIVE.
T2CON.Note that a rolloverin TH2 doesnot set TP2,
and willnot generatean interrupt. Therefore,the Timer RECEIVE enables SHIFT CLOCK to the alterstate
2 interrupt doesnot have to be disabledwhenTimer 2 output function line of P3.1. SHIIW CLOCK makes
is in the baud rate generator mode. Note too, that if transitions at S3P1and S6P1 of every machine cycle.
EXEN2 is set, a l-to-O transition in T2EX will set At S6P2of everymachinecycle in which RECEIVEis
EXF2 but will not cause a reload from (RCAP2H, active,the contentsof the receiveshift registerare shift-
RCAP2L)to (TH2,TL2). Thus whenTimer 2 is in use ed to the left one position. The value that comes in
as a baud rate generator,T2EX can be usedas an extra from the right is the vrduethat was sampledat the P3.O
external interrupt, if desired. pin at S5P2of the same machine cycle.
As &ta bits comein from the righL 1sshift out to the
It shouldbe noted that when Timer 2 is running(TR2 left. When the Othat was initiallyloadedinto the right-
= 1) in “timer” function in the baud rate generator most positionarrivesat the leftmostpositionin the shift
mod~ one shouldnot try to read or write TH2or TL2. register, it flags the RX Control block to do one last
Under these conditionsthe Timer is beingincremented shift and load SBUF. At SIP1 of the Klth machine
everystate time, and the results of a read or write may cycle after the write to SCON that cleared RI, RE-
not be accurate.The RCAP rcgistm may be read, but CEIVE is cleared and RI is set.
shouldn’tbe written to, becausea write mightoverlapa
reload and cause write and/or reload errors. Turn the
Timer off (clear TR2) before ruessing the Timer 2 or MoreAboutMode 1
RCAP registers,in this case. Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), 8 data bits (LSBtirst),
MoreAboutModeO and a stop bit (l). on receive, the stop bit gces into
RBg in SCON.In the 8051the baud rate is determined
Serial
dataenters and exits through RXD. TXD out- by the Timer 1 overflowrate. In the 8052it is deter-
puts the shifl clock. 8 bits are tranarnitted/received:8 minedeither by the Timer 1overtlowratej or the Timer
data bits (LSBfwst).The baud rate is fixedat !/,2 the 2 overtlowrate or both (one for transmit and the other
oscillatorfrequency. for receive).
Figure 17showsa simplifiedfunctioneddiagramof the Figure 18showsa simplitlsdfunctionaldiagramof the
serial port in ModeO,and associatedtiming. serial port in Mode 1, and associatedtimingsfor trsns-
mit receive.
3-17
 HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Sosl
MTERNALws

WRITE
TO RXD
SBUF PS.OALT
OUTPUT
FUNCTION

SHIFT
Tx CONTROL
26

SERIAL
PORT l-m
INTERRUPT P3.1 ALT
OUTPUT
FUNCTION

REN
R RX(I
. . ...
P!?OALT
INPUT

~T”
FUNCTION

u
I SeuF
1
REAO
SBUF

nwRrTEToseuF
SEND -
SNIFT II n n n n n n n
W 1 01 x lx? , w 1 M x m I 06 1 07 \ TRANSMIT
MD {DATAOUTI \
Tli6i6\
n I
n WRITE T08CON(CUAR Ill)

am I
RECEIVE I RECEIVE
SNm n n n I-I n n n n
M “m .Ds .0s “m .0s .06 D?
RXD(DATAIN)
L
mmwmaocm
270252-15

Figure 17. 8erial Port Mode O

3-18
i~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

TIMER 1 TIMER2 20s1INTERNALBUS

OVERFLOW OVERFLOW
TSS

!?
SMOD
=0
+2
SMOD
=1
WRITS
TO —
SBUF
TXD

RCLK----

IFFH

RXD
LOAD
SBUF

SSUF

READ
SSUF
*

lx
@oclq I I I I I
IWWTSTOSSUF
sEND
OATA SIPF r rRANsMrT
sNln 1 1 0 I
~L I 00 z m 1 m r 03 1 0s 1 D5 r 0s 1 n7 1 STOPBtl
1! STARTSIT
+1’1
-lsnEsm
.S
RXO MT” STOPOIT
RECEIVE ● TM=-—=
Blwf
l-++++++:
RI

270262-16

Figure 18. Serial Port Mode 1. TCLK, RCLK and TTmer2 are Preaent in the 8052/8032 Only.

Trammission is initiated by any instruction that oses timesare synchronisedto the divide-by-16counter, not
SBUF as a destinationregister. The “write to SBUF” to the “write to SBUF” signal).
sid * IOSdSa 1 into the 9th bit position of the
transmit shift register and flags the TX Control unit The transmission begins with activation of SEND,
that a transmissionis requested.Tmnsmission aotually which puts the start bit at TXD. One bit time later,
commencesat SIP1 of the machinecycle followingthe DATA is activated, whichenablesthe output bit of the
next rolloverin the divide-by-16counter. (Thus,the bit transmit shift register to TXD. The first shift pulse cc-
curs one bit time after that.
3-19
in~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

As data bita shift out to the right, zeroesare clockedin mit, the 9th data bit (TB8)can be assignedthe value of
from the left. When the MSBof the data byte is at the Oor 1. On receivejthe 9th data bit goes into RB8 in
output positionof the shift register,then the 1 that was SCON.The baud rate is programmableto either Y&or
initiallyloadedinto the 9th positionisjust to the left of %. the oscillatorfrequency in Mcde2. Mode3 may
the MSB, and all positionsto the left of that contain havea variablebaud rate generatedfromeither Timer 1
zeroes. This conditiontlags the TX Control unit to do or 2 dependingon the state of TCLK and RCLK.
one last shift and then deactivate SEND and set TI.
This occurs at the loth divide-by-16rollover after Figurca 19 and 20 show a fictional diagram of the
“write to SBUF.” serial port in Modes 2 and 3. The receive portion is
exactly the same as in Mode 1. The transmit portion
Receptionis initiated by a detected l-to-Otransition at differsfrom Mode 1 only in the 9th bit of the transmit
RXD. For this purposeRXD is sampledat a rate of 16 shift register.
times whateverbaud rate has been established.When a
transitionis detected,the divide-by-16counter is immed- Transmissionis initiated by any instruction that uses
iately reaet, and IFFH is written into the input shift SBUF as a destinationregister. The “write to SBUF”
register. Reaetting the divide-by-16counter aligns its signal also bads TB8 into the 9th bit position of the
rolloverswith the boundariesof the incomingbit titnea. transmit shift register and flags the TX Control unit
that a transmiasion is requested. Transmissioncom-
The 16 states of the counter divide each bit time into mencesat SIP1 of the machinecyclefollowingthe next
16ths.At the 7th, 8th, and 9th counterstates of each bit rollover in the divide-by-16counter. (Thus, the bit
time, the bit detector sampleathe value of RXD. The timesare synchronizedto the divide-by-16counter,not
value acceptedis the valuethat was seen in at least 2 of to the “write to SBUF”signal.)
the 3 samples. This is done for noise rejection. If the
value accepted during the first bit time is not O, the The transmission begins with activation of SEND,
receivecircuits are reset and the unit goeaback to look- which puts the start bit at TXD. One bit time later,
ing for another l-to-Otransition. This is to providere- DATA is activated,whichenablesthe outputbit of the
jection of false start bita. If the start bit proves valid, it transmit shift registerto TXD. The first shitl pulse oc-
is shifted into the input shift register, and reception of curs one bit time after that. The first shift clocks a 1
the rest of the thrne will proceed. (the stop bit) into the 9th bit positionof the W regis-
ter. Thereafter, ordy seroes are clocked in. Thus, as
As data bits come in from the right, 1s shift out to the data bits shift out to the right, zeroes are clocked in
left. When the start bit arrives at the leftmost position fromthe left. WhenTB8is at the output positionof the
in the shift register, (which in mode 1 is a 9-bit regis- shitl register, then the stop bit isjust to the left of TB8,
ter), it figs the RX Controlblock to do one last shift, and all positionsto the left of that containzeroes.This
load SBUF and RB8, and set RL The signal to led conditionflagsthe TX Controlunit to do one last shift
SBUFand RB8, and to set RI, will be generatedif, and and then deactivate SEND and set TL This occurs at
onlyif, the followingconditionsare met at the time the the llth divide-by-16rolloverafter “write to SBUF.”
final shifl pulse is generat.d
Receptionis initiated by a detected 1-W3transition at
1) RI and
= O, RXD. For this purposeRXD is sampledat a rate of 16
2) EitherSM2 = O,orthereceivedstopbit = 1 timeswhateverbaud rate has been established.When a
transitionis detect~ the divide-by-16counteris immed-
If either of these two conditionsis not met, the received iately reaet, and lFFH is written to the input shift
frame is irretrievably lost. If both conditionsare met, register.
the stop bit goes into RB8, the 8 data bits go into
SBUF, and RI is activated. At this time, whether the At the 7th, 8tb and 9th counter ststes of each bit time
aboveconditionsare met or not, the unit goes bsek to the bit detector samplesthe vrdueof RXD. The value
lookingfor a l-to-Otransition in RXD. acceptedis the valuethat was seen in at least 2 of the 3
samplea.If the value acceptedduring the first bit time
is notO,the receivecircuitsareresetandtheunitgoes
MoreAbout Modes2 and 3 back to looking for another l-to-O transition. If the
start bit provea valid, it is shifted into the input shift
Elevenbita are transmitted (throughTXD), or received register,and receptionof the rest of the frame will pro-
(throughRXD): a start bit (0),8 data bits (LSBfit), a eecd.
programmable9th data bit, and a stop bit (l). On trans-

3-20
i~. HARDWARE DESCRIPTlON OF THE 8051,8052 AND 80C51

S0S1INTERNAL BUS

TSS

WRITE

S~tF
TXD

PHASE 2 CLOCK
(% fosc)

STOP 91T
MOOE 2 START GEN, ‘H’mDATA
TX CONTROL
TX CLOCK TI Sm

LOAO +

IFFH

RxD
LOAD
SBUF

~LOC~ 1 n t n n n R 1 n
n n
I WRITE TO SBUF
I
OATA
sNIPr n n a n 11 n I o TRANSMIT
n

TI
STOPRl~ r
lSRESET
ICLOCK 1 1 n 8 n 1 n o n m 1
Rxo m I D1 1 02 I D3 I M r 06 I
B17DETEcToR15’m’~/ m 1 07 1 ma k.4.pP
RECEIVE SAMPLE TIMES m !4!4 m W Im m Es u m M
SHIT 1 n n n n n n n n n
I

270252-17

Figure 19. Serial Port Mode 2

3-21
 HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

TIMER 1 TIME S051INTSRNALBUS

OVERFLOW OVEI .Ow II

Qr-
TSB

WRITE
:2 TO —
SSUF
SMOD
SMOD =1
:0

TCLK -

RCLK ----
rw
,“..%

--

“o”’

r
,...

,.,..
1

—--7--A
I+%’E
;“’”l
+1$L
RX CLOCK RI
I
LOAD+
/

-lE&El-

I I IFFH

!’ ,
v

RXD
LOAD
SBUF

*
READ
SBUF
*
-
Tx

‘1
&LOCl$ n
I WRITE TO S8UF

DATA
SHIFT TRANSMIT

STOP SIT
-r,

Figure20.5enalPortMode3. TCLK,RCLK,andTimer2 arePresentinthe6052/8032Only.

3-22
in~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

As data bits come in from the right, 1sshift out to the was transition-activated.If the interrupt was level-acti-
left. Whenthe start bit arrives at the leftmost position vat@ then the externalrequestingsource is what con-
in the shift register (whichin Modes 2 and 3 is a 9-bit trols the requestflag,rather than the on-chiphardware.
register), it flags the RX Control block to do one last
shit%load SBUF and RIM, and set RI. The signal to The Timer Oand Timer 1 Interrupts are generatedby
load SBUFand RB8, and to set RI, willbe generatedif, TFOand TFl, which are set by a rollover in their re-
and onlyif, the followingconditionsare met at the time spectiveTimer/Counterregkters (exceptseeTimerOin
the final shift pulse is generated: Mode 3). Whena tinter interrupt is generated,the flag
that generated it is cleared by the on-chip hardware
1)RI= O,artd when the serviceroutine is vectoredto.
2) EitherSM2= Oor the received9thdata bit = I
The SerialPort Interrupt is generatedby the logicalOR
If either of these conditions is not met, the received of RI and TI. Neither of these flags is cleared by hard-
three is irretrievably lost, and RI is not set. If both ware when the cervix routine ia vectored to. In fact,
conditionsare met, the received9th data bit goes into the service routine will normally have to determine
RB8, and the tiret 8 &ta bits go into SBUF. One bit whether it was RI or TI that generated the interrupt,
time later, whether the aboveconditionswere met or and the bit will have to be cleared in software.
not, the unit goesback to lookingfor a l-tQ-Otransition
at the RXD input. In the 8052,the Timer 2 Interrupt is generatedby the
logicalOR of TF2 and EXF2. Neither of these flags is
Note that the value of the receivedstop bit is irrelevant cleared by hardware when the service routine is vec-
to SBUF,RB8, or RI. tored to. In fact, the serviceroutine may have to deter-
mine whether it wee TF2 or EXF2 that generatedthe
interrupL and the bit will have to be cleared in soft-
INTERRUPTS ware.
The 8051 provides 5 interrupt sources. The 8052pro- All of the bite that generate interrupt can be setor
vides6. These are shown in Figure 21. cleared by software,with the same result as though it
had beenset or clearedby hardware.That is, interrupts
The External Interrupts ~ and INT1 carseach be can be generatedor pendinginterrupts can be canceled
either level-activatedor transition-activate&depending insoftware.
on bita ~ and ITl in RegisterTCON. The tlags that
actuallygenerate these interrupts are bits IEQand IE1 (MSS) (LSB)
in TCON.Whetsen externalinterrupt is generated,the
m] — I E72 I ES I ~1 I EXl I ETO ] EXO
tlag that generated it is cleared by the hardware when
Enable S4 = 1 enaMss the infwrupt
the serviceroutine is vectoredto only if the interrupt Ensble Sit = O dieebles it

symbol Position Function

.J?--#GJ,
EA IE.7 &eek4es sII interrupts.If EA = 0, no
intemuptwillbeeeknowledged. If EA
= I,eeehinterrupt solneeie
indbiduskyenebled wdissbled by
settingorclearing meaaeble bit.
IE.6 resewed.
m D
ET2 IE.5 litnw2 intenupf enable bit
I

A?--@+=
ES IE.4 Serial P&t infamuptenebletit.
El-l IE.3 ITmer 1 imenupl ensbfe bit.
Exl IE2 Extarrsalinterrupt1 ertablebt
ETo IE.t Timw Oikttanuptenablsbit.
Exo IE.O ExterrKaintenuptO eneblebit
m P
Usersotiwaraslwuld navarwrits Istourtimplamwfad bits,since
~MSYbausad infutureMCS-51 @ueta

Figure22.IE:InterruptEnableRsgister

exn (mssOMLo
-J
270252-19

Figurs 21. MCS@-51Intarrupt Sources

3-23
infd. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Each of these interrupt sourcescan be itldividdy en- ceivedsimultaneously,an internal pollingsequencede-

abled or disabledby settingor clearing a bit in Special termines which request is serviced. Thus within each
Function Register IE (Figure 22). IE contains also a priority levelthere is a second priority structure deter-
global disablebit, EA, which disables all interrupts at mined by the pollingsequence,as follows:
once.
Source Priority Within Level
Note in Figure 22 that bit position IE.6 is unimple- 1. IEO (highest)
mented. In the 8051s bit positionIE.5 is also tmimple- 2. TFO
mented. User softwareshouldnot write 1s to these bit 3. IE1
positions, since they may be used in future MCS-51 4. TF1
products. 5. RI +Tl
6. TF2 + EXF2 (lowest)
PriorityLevelStructure
Note that the “prioritywithin level” structureis only
Eachinterrupt source can also be individually pro- usedto resolvem“muitaneousrequests of thesomeprion-
grammed to one of two priority levels by setting or ty level.
clearing a bit in SpecialFunction Register 1P (Figure
23). A low-priorityinterrupt can itself be interrupted The 1P register contains a numbes of unimplemented
by a high-priorityinterrup~but not by another low-pri- bits. IP.7 and IP.6 are vacant in the 8052s,and in the
ority interrupt. A high-priority interrupt can’t be inter- 8051sthese and IP.5 are vacant. User softwareshould
rupted by ~y other-int&rupt-aource. - not write 1s to these bit positions,since they may be
used in future MCS-51products.
(MSB) (LSB)
— — PT2 PS PTl Pxl PTo Pxo How InterruptsAre HandIed
Riwity bit = 1 assigns high priortty. The interrupt flags are sampled at S5P2 of every ma-
Priorftybit = Osssigns low priority.
chine cycle. The samplesare polled during the follow-
Symbol Poeitforl Funefion ing machine cycle.The 8052’sTimer 2 interrupt cycle
— IP.7 reserved is ditkrent as describedin the ResponseTime Section.
IP.6 resewed Hone of the ilagswasin a set conditionat S5P2of the
PT2 IP.5 Tmer2 intemuptprie+ftybit. P~ “ g cycle the polling cycle will find it and the
interrupt systemwillgeneratean L-CALLto the appro-
Ps IP.4 Swisl Port intenupt prioritybl priate serviceroutine,providedthis hardwere-generat-
PTl IP.3 Timer 1 intenupt primityMt. ed LCALL is not blockedby any of the followingcon-
Pxl IP.2 Externalintenupt 1 pttofitybit ditions:
MO IP.1 lim6r0 interruptpttoiitybit. 1. An interrupt of equal or higher priority level is al-
Pxo IP.O Extemsl intenupt Oprioritybit ready in progress.
User soffwareshould neverwite 1$ to unimplementedbits,since 2. The current (polling)cycle is not the final cycle in
theYmbe used ifIfufurs M@51 P+oducts. the executionof the instruction in progress.
3. The instructionin progressis RETI or any write to
Figure 23. 1P:Interrupt Priority Register the IE or 1Pregisters.

If two requests of dikent priority levelsare received Any of these three conditionswill blockthe generation
simultaneously,the request of higher priority level is of the LCALL to the interrupt serviceroutine. tXmdi-
serviced. If requests of the same priority level are re- tion 2 cn3urcethat the instruction in progress wilt be

ISEP21 % I

m ‘:
A A . . .. .
INTERRU~ LONGCALLTO INIERRUPTHOUllNE
AREPOLLSO IM’ERRUPT
INTERRUPT INTERRUPT VECTORAOOQESS
GOES LATCHEO
ACTWE
270252-20
Ttisisthefeetestpossible reeponee vhn C2isthefinel cydeofaninettuctien ottwrthert RETI oranaeaesto IEorlP.

Ftgure24. Interrupt ResponseTimingDisgrem

3-24
intdo HARDWARE DESCRIPllON OF THE 8051,8052 AND 80C51

completedbeforevectoringto any serviceroutine.Con- ExternalInterrupts

dition 3 ensures that if the instruction in progress is
RETI or any accessto IE or 1P, then at least one more The externalsourcescan be programmedto be level-ac-
instruction wiffbe executedbefore any interrupt is vec- tivated or transition-activatedby setting or clearing bit
tored to. ITI or ITOin Register TCON. If ITx = O, extemaf
interrupt x is triggered by a detectedlow at the INTx
The polfing cycleis repeated with each machinecycl~ pin. If ITx = 1, external interrupt x is edge-tiered.
and the valuespolledare the valuesthat werepresentat In this mode if successive samples of the INTx pin
S5P2 of the previousmachine cycle. Note then that if show a high in one cycle and a low in the next CYCIG
an interrupt flagis activebut not beingrespondedto for interrupt requeatflag IEx in TCONis set. Flag bit IEx
one of the aboveconditions,and is not still active when then requeststhe interrupt.
the blockingconditionis removed,the deniedinterrupt
will not be serviced.In other wor& the fact that the Sincethe extemaf interrupt pinsare sampledonce each
interrupt tlag was once active but not servicedis not machinecycle, an input high or lowshould hold for at
remembemd.Everypoflingcycle is new. least 12 oscillator periods to ensure sampfing. If the
external interrupt is transition-activated,the external
The pofling cycle/LCALL sequence is illustrated in sourcehas to hold the requeatpin high for at least one
Figure 24. machine cycle, and then hold it low for at least one
machine cycle to ensure that the transition is seen so
Note that if an interrupt of higher priority Ievefgoes that interrupt request flag IEx will be set. IEx will be
active prior to S5P2of the machine cyclelabeledC3 in automatically cleared by the CPU when the service
Figure 24, then in accordance with the aboverules it routine is called.
@ be Vectored to during C5 and cd, without Stlyin-
struction of the lowerpriority routine havingbeenexe- If the external interrupt is level-activated,the external
cuted. sourcehas to hold the requestactiveuntil the requested
interrupt is actually generated.Then it has to deacti-
Thus the procesaor acknowledgesan interrupt request vate the request before the interrupt service routine is
by executinga hardware-generatedLCALL to the ap complet~ or else another interrupt will be generated.
propriate servicingroutine. In some casesit also clears
the flag that generatedthe interrupt, and in other cases
it doesn’t. It never clears the Serial Port or Timer 2 ResponseTime
flags. This has to be done in the user’s software. It The ~ and INT1 levels are inverted and latched
clears an external interrupt flag (IEOor IEl) only if it into the interrupt tlags IEOand IEl at S5P2 of every
was transition-activated. The hardware-generated machine Cycle.Similarly,the Timer 2 flag EXF2 and
LCALL pushes the contents of the Program Counter the Serial Port flags RI and TI are set at S5P2. The
onto the stack (but it does not save the PSW) and re- valuesare not actually polledby the circuitry until the
loads the PC with an address that depends on the next machinecycle.
source of the interrupt being vectoredto, as ahownbe-
low. The TimerOand Timer 1flags,TFOand TFl, are set at
Vector S5P2 of the cycle in which the timers overflow.The
8ource
Address vafuesare then polledby the circuitryin the next cycle.
IEO OO03H However,the Timer 2 flag TF2 is set at S2P2 and is
TFO OOOBH polledin the same cycle in whichthe timer overtlows.
IE1 O013H
TF1 OOIBH If a requeatis active and conditionsare right for it to be
RI + TI O023H
acknowledged,a hardware subroutinecd to the re-
questedserviceroutine wittbe the nextinstructionto be
TF2 + EXF2 O02BH executed.The call itself takes two cycles.Thus, a mini-
mum ofthreecompletemachinecycleselapsebetween
Executionproceedsfromthat locationuntilthe RETI activation of an external interrupt request and the be-
instructionis encountered.The RETI instructionin- ginningof executionof the first instructionof the aerv-
formsthe processo r that this interruptroutineis no iceroutine.Figure 24showsinterruptresponsetimings.
longerin progr~ then popsthe top twobyteafromthe
stack and reloads the program Counter. Executionof A longer response time woufdresult if the request is
the interrupted program continues from where it left blockedby one of the 3 previouslyfisted conditions.If
off. an interrupt of equal or higherpriority level is already
in progress,the additionalwait time obviouslydepends
Note that a simple RET instruction would also have on the nature of the other interrupt’sserviceroutine. If
returned executionto the interrupted progmrn,but it the instruction in progressis not in its final cycl~ the
would have left the interrupt control system thinking additionalwait time cannotbe morethan 3 cycles,since
an interrupt was stiIl in progress. the longest instructions (MUL and DIV) are only 4
3-25
intel. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

cycles long, and if the instructionin progress is RET2 RESET

or an accessto IE or 1P, the additionalwait time can-
not be more than 5 cycles (a maximumof one more The reset input is the RST pin, whichis the input to a
cycle to complete the instruction in progress, plus 4 SchmittTrigger.
cyclesto completethe next instructionif the instruction
is MUL or DIV). A reset is accomplishedby holdingthe RST pin high
for at least two machine cycles(24 oscillator periods),
Thus, in a single-interruptsystenLthe responsetime is while the asciIlator h rwnning. The CPU responds by
rdwaysmore than 3 cyclesand less than 9 cycles. generatingan internal res@ with the timing shown in
Figure 25.

SINGLE-STEPOPERATION The externalreset signalis asynchronousto the internal

clock. The RST pin is sampledduring State 5 Phase 2
The 8051interrupt structure allowssingle-stepexecu- of every machine cycle. The port pins will maintain
tion with very little software overhead.As previously their current activ@iesfor 19 oscillatorperiods after a
noted, an interrupt request will not be responded to logic 1 has been sampledat the RST pin; that is, for 19
whilean interrupt of equal prioritylevelis still in prog- to 31 oscillator periods after the external reset signal
ress, nor will it be respondedto after RETI until at has been applied to the RST pin.
least one other instruction has been executed. Thus,
once an interrupt routine has beenentered,it cannot be Whilethe RST pin is high, ALE and PSEN are weakly
reentered until at least one instructionof the interrupt- pulledhigh. Mer RSTis pulledlow,it will take 1 to 2
ed programis executed.One wayto use this feature for machine cycles for ALE and PSEN to start clocking.
single-stopoperationis to programone of the external For this reason, other devicescan not be synchronized
interrupts (say, INTO)to be level-activated.The service to the internal timingsof the 8051.
routine for the interrupt willterminatewith the follow-
ing cude: Driving the ALE and PSEN pins to O while reset is
active could cause the deviceto go into an indetermin-
JNB P3.2,$ ;Wait Here Till~Goes High
ate state.
JB P3.2,$ ;NowWait HereTill it Goes Low
RETI :Go Back and ExecuteOne Instruction The internal reset algorithm writes 0s to all the SFRS
except the port latch= the Stack Pointer, and SBUF.
Now if the ~ pin, whichis alsothe P3.2 pin, is held The port latches are initialized to FFH, the Stack
normallylow, the CPU will go right into the External Pointer to 07H, and SBUF is indeterminate. Table 3
Interrupt Oroutine and stay there until ~ is pulsed lists the SFRSand their reset values.
(from low to high to low). Then it will execute RETI,
go back to the task program, executeone instruction, The internal R4M is not affectedby reset. On power
and immediatelyre-enter the Extend Interrupt Orou- up the ILkM content is indeterminate
tine to await the next pulsingof P3.2. One step of the
task program is executedeach time P3.2 is puked.

~t2 OSC. PERIODS ~

RST:
I//l/l/l///w IN7ERNAL RESETSIGNAL
SAMPti, RST SAMPLE RST
, I

~:
1 I I ~1 I I [ I I t,, 1

Po: INST
!(
I ,
—11 Osc. PERIOOS
—19 OSC. PERIODS —
270252-33

Figure 25. Reset Timing

3-26
i~o HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Table 3. Reset Values of the SFRS POWER-ONRESET

I Pc
SFR Name

ACC
Reset Value
OOOOH
OOH
For HMOSdeviceswhenVCCis turned on an automat-
ic reset can be obtainedby connectingthe RST pin to
V~ througha 10pF capacitor and to Vss throughan
B OOH
8.2 Kf2 reeistor (Figure 26). The CHMOSdeviceado
not require this resistor although its presencedoea no
Psw OOH harm. In fact, for CHMOSdevicesthe externalresistor
SP 07H can be removedbecausethey havean internalpulldown
I DPTR I OOOOH I
on the RST pin. The capacitor valuecould then be r-
duced to 1 pF.
I PO-P3 I FFH I
1P(8051) XXXOOOOOB Whenpoweris turned on, the circuit holdsthe RSTpin
1P(8052) XXOOOOOOB highfor an amount of time that dependson the capaci-
tor value and the rate at whichit charges.To ensure a
IE [8051) OXXOOOOOB valid reset the RST pin must be held high long enough

1 IE (8052) OXOOOOOOB to allow the oscillator to stsrt up plus two machine

TMOD OOH cycles.
TCON OOH On power up, VCCshould rise within approximately
THO OOH ten milliseconds.The oscillator start-up time will de-
TLO OOH
pendon the oscillatorfrequency.Fora 10MHz crystal,
the start-up timeis typically 1rns.For a 1MHz crystal,
TH1 OOH the start-up time is typically 10ms.
I TL1 I OOH I
TH2 (8052) OOH
With the givencircui~ reducingVW quicklyto Ocaus-
[ I J es the RST pin voltageto momentarilyfall below OV.
TL2 (8052) OOH However,this voltageis internzdlylimitedand will not
RCAP2H(8052) OOH harm the device.
RCAP2L(8052) OOH
NOTE:
SCON OOH The port pins will be in a random state until
SBUF Indeterminate the oscillatorhas started and the internal reset
PCON (HMOS) OXXXXXXXB algorithmhas written 1s to them.
PCON (CHMOS) OXXXOOOOB Powering up the device without a valid reset could
cause the CPU to start executinginstructionsfrom an
indeterrninatelocation. This is becausethe SFRs, ape-
citically the Program Counter, may not get properly
initialized.

,.”,l POWER-SAVINGMODESOF

k3
‘cc OPERATION
For applicationswhere power consumptionis critical
Sml the CHMOSversionprovideapowerreducedmodesof
operationas a standard feature. The powerdownmode
in HMOS devicesis nolongera standardfeatureandis
ST beingphased OUt.
UKIL

CHMOSPowerReductionModes
Isa
=
CHMOS versions have two power-reducingmodes,
Idle and PowerDown.The input throughwhichback-
270252-21 up power is suppliedduring these operationsis VCC.
Figure 27 shows the internal circuitry which imple-
Figure25. PoweronResetCircuit ments these features. In the Idle mode(IDL = 1), the
oscillator continuea to run and the Interrupt, Serial
Port, and Timer blockscontinueto be clocked,but the
3-27
intel. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

clock signal is gated off to the CPU. In Power Down

(MSB) (Lss)
(PD = 1), the oscillator is frozen.The Idle and Power
Down modes are activated by setting bits in Special SMOO I-I-I- GF1 GFO PD IOL

Function RegisterPCON. The address of this regiete.r

symbol PoSnIOrt Natrteattd Furtotic+t
is 87H. Figure 26 details ita contents.
SMOD PCON.7 OoubleSaud rats bit.When aattoa 1
and Timer 1 is used togenerrda baud
In the HMOSdeviceathe PCON registeronlycontains rate, andfhs SsrW .%rl is used in
SMOD. The other four bits are implementedonly in modes 1,2, 0r3.
the CHMOSdevices.User softwareshouldneverwrite
PCON.6 (Reserved)
1s to unimplementedbita, since they may be used in
t%tureMCS-51products. FCON.5 (Reserved)
— PCON.4 (Reaswsd)
GF1 PCON.3 General-purpose flag bit
IDLE MODE
GFO PCX2N.2 Gemaraf-pu~ flqlrit.
An instructionthat sets PCON.Ocausesthat to be the PD FCX2N.I Powsr Down M. Satfingthisbit
last instruction executed before going into the Idle activates powsrdewmoperation.
mode. In the Idle mode, the internal clock signal is IDL PCON.O Idle mode bit.Setfingthk btiactivataa
gated off to the CPU, but not to the Interrupt, Timer, idle mode opsratiort
and Serial Port functions.The CPU statue is preserved If 1s arewrfrren to PD and IDL at the aametime, PDfskes
in its entirety: the Stack Pointer, Program Counter, precedence.l%areeetvaluaof PCONia(OXXXOCOO).
Program StatueWord, Accumulator,and all other reg- In tfw HMOSd- * ~N @2taroII~contains SMOD.
isters maintain their data during Idle. The port pins Ttwofherfcurtit eareimpkmer!tsd onfyintlw CHMOSdsvioea.
hold the logical statea they had at the time Idle was User mftwsre sfwuld rwverwite Istourimplememtsd bita,ainm
tfwymaybeuasdin future MCS-51 pmduote.
activated. ALE and PSEN hold at logichigh levels.

There are two waysto t-ate the Idle. Activationof Figure 28. PCON: PowerControlRegister
any enabledinterropt will cause PCON.Oto be ckared
by hardware termma “ ting the Idle mode.The interrupt The tlag bite GPO end GFI can be used to give an
will be aervic@ and followingRETI the next instruc- indiesti;n if en interrupt occurred duringnorm~ oper-
tion to be executed will be the one followingthe in- ation or during an Idle. For example, an instruction
struction that put the deviceinto Idle. that activates Idle can also set one or both flag bita.
When Idle is terrmna“ ted by an interrupt, the interrupt
serviceroutine can examine the fig bita.

riOh The other way of termma“ ting the Idle mode is with a
hardware reset. Since the clock oscillator is still run-
ning the hardwarereset needsto be heldactivefor only
2rAL2 two machinecycles (24 oscillator periods)to complete
the reset.
The signal at the RST pin clears the IDL bit directly
and asynchronously.At this time the CPU resumes
‘L...
programexecutionfrom where it left off;that is, at the
b-- instruction following the one that invoked the Idle
Mode. As shown in Figure 25, two or three machine
cyclesof programexecutionmay take pleee beforethe
internal reset algorithm takes control. On-chip hard-
ware inhibita access to the internal RAM during this
Figure 27. Idle and Power Down Hardware time, but aeccas to the port pins is not inhibited. To
eliminate the possibilityof unexpectedoutputs at the
port pine,the instructionfollowingthe onethat invokes
Idle should not be one that writes to a port pin or to
external Data RAM.

POWER DOWN MODE

An instructionthat seta PCON.1 cauaeathat to be the
last instruction executed before going into the Power
Down mode. In the Power Down mode, the on-chip
oscillator is stopped. With the clock frozen, all func-

3-28
in~. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Table4. EPROMVersionsof the 8051and8052

Device EPROM EPROM Ckt Time Required to
VPP
Name Version Bytes Type ProgramEntireArray
8051AH 8751H/8751BH 4K HMOS 21.0V112.75V 4 minutes
80C51BH 87C51 4K CHMOS 12.75V 13 seconds

1 8052AH 8752BH 8K HMOS 12.75V 26 seconds

tions are stopped, but the on-chip RAM and Special ProgramMemoryLocks
Function Registeraare held. The port pins output the
valuesheld by their reapecdveSFRS.ALE and P8EN In somemicrocontrollerapplicationsit is desirablethat
output lows. the Program Memorybe secure from software piracy.
Intel has responded to this need by implementinga
The only exit from Power Down for the 80C51is a Program Memorylockingschemein someof the MCS-
hardware reset. Reset redefinesall the SPRS,but does 51devices.Whileit is impossiblefor anyoneto guaran-
not changethe on-chip W. tee absolutesecurity againatall levelsof technological
sophistication,the ProgramMemorylocksin the MCS-
In the Power Down mode of operation, VCC can be 51deviceswillpresenta substantialbarrier againatille-
reducedto as low as 2V. Care must be taken, however, gal readout of proteetedsoftware.
to ensure that VCC is not reduced before the Power
Downmodeis invoked,and that VCCis restoredto its
normaloperatinglevel,beforethe PowerDownmodeis One Lock Bit Scheme on 8751H
terminated.The reset that terminatesPowerDownalso
The 8751H contains a lock bit which, once pro-
frees the oaeillator. The reset should not be activated
before VCC is restored to its normal operating level, grammed, denies electrical access by any external
and must be held active longenoughto allowthe oscil- means to the on-chipProgram Memory. The etht of
lator to restart and stabilise (normally less than 10 this lock bit is that whileit is programmedthe internal
maec). Program Memorycan not be read out, the devicecan
not be further programmed,and it can not execute ex-
ternal ?%ognamMemory. Erasing the EPROM array
deactivates the lock bit and restores the device’sfull
EPROMVERSIONS functionality.It can then be re-progratnmed.
The EPROM versionsof these devieesare listedin Ta-
ble 4. The 8751Hprograms at VPP = 21Vusing one The procedurefor programmingthe lock bit is detailed
50 msec PROO pulse per byte programmed.This re- in the 8751Hdata sheet.
sults in a total programmingtime (4K bytes)of approx-
imately4 minutes. Two ProgramMemoryLockSshemes
The 8751BH, 8752BH and 87C51 use the faster The 8751BH,8752BHand 87C51contain two Program
‘@i~k-p~>> pro~gm ~gorithm. ~= de- Memory lockingschemes:Encryptedverify and Lock
12.75Vusing a series of Bits.
twenty-fiveIMlps PROO pulsesper byteprogrammed.
This results in a total programmingtime of approxi- EncryptionArraw Within the EPROM is an array of
mately 26 seconds for the 8752BH (8 Kbytes) and encryptionbytes that are initially unprogrammCd(au
13seeondsfor the 87C51(4 Kbytes). l’s). The user ean program the array to encrypt the
code bytes during EPROM veriftcstion. The verifica-
Detailedprocedures for programming and verifying tion procedure sequentiallyXNORS each code byte
each deviceare givenin the data sheets. with oneof the keybytes.Whenthe last keybyte in the
-Y k reached,the verifyroutine starts over with the
first byte of the array for the next code byte. If the key
Exposureto Light byteaare unprogrammed,the XNOR processleavesthe
code byte unchanged.With the keybytes programmed,
It is good practice to cover the EPROM windowwith the code bytes are encryptedand can be read correctly
an opaquelabel when the deviceis in operation.This is only if the key bytes are knownin their proper order.
not so much to protect the EPROM array from inad- Table 6 lists the number of encryptionbytrs available
vertent erssure but to protect the RAM and other on- on the variousproducts.
chip logic.Allowinglight to impingeon the silicondie
whilethe deviceis operatingcan csuae logicalmalfhne- Whenusingthe encryptionarray, one important factor
tion. should be considered. If a code byte has the value
3-29
i@. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

OFFH,ven~g the byte will prqduce the encryption When Lock Bit 1 is programm~ the logiclevelat the
byte value. If a large block of code is letl unpro- ~ pin is sampledand latched during react. If the de-
grammed,a verificationroutinewilldisplaythe encryp- vice is poweredup withouta reset, the latch inidalizes
tion array contents. For this reason all unused code to a random value, and holds that value until reset is
bytea should be progrsmmed with some value other activated. It is ncassary that the latched value of ~
than OFFH, and not all of them the same value. This be in agreement with the current logic levelat that pin
will ensure maximumprogramprotection. in order for the deviceto function properly.

Prosram Lack Bita: Also included in the Program

Lack scheme are Lock Bits which csn be enabled to ROM PROTECTION
providevaryingdegreesof protection,Table 5 lists the The 8051AHP and 30C51BHP are ROM Protectrd
L.cckBits and their correspondingeffecton the micro- versionsof the 3051AHand 30C51BH,respectively.To
controller.Refer to Table 6 for the Lock Bits available incorporate this Protection Feature, program verifica-
on the variousproducts. tion has been disabled and extcrnaf memory amessca
have been limited to 4K. Refer to the data sheets on
Erasing the EPROM also erases the EncryptionArray these parts for more information.
and the Lack Bits,returningthe part to full functionali-
ty.

Table 5. Program Lo k Bits and their Features ONCETMMode

Program Loci 3ita The ONCE (“on-circuit emulation”) mode facilitates
—— Protection Type testing and debuggingof systemsusingthe devicewith-
LB1 LB2 LB3 out the &vice havingto be removed from the circuit.
Y- u No programlock features The ONCE mode is invokedby:
enabled.(Code verifywill 1. Pull ALE low whilethe deviceis in reactand PSEN
stillbe encryptedbythe is high;
encryptionarray if 2. Hold ALE low as RST is deactivated.
programmed.)
T u MOVC instructions While the deviceis in ONCE modq the Port Opins go
executedfromexternal into a float state, and the other port pins and ALE and
programmemoryare ~ are weakly pulled high. The oscillator circuit
disabledfromfetching remains active. While the device is in this modq an
code bytesfrom internal emulator or teat CPU can be used to drive the circuit.
memory,EA is sampled Normal operation is restored after a normal reset is
and latchedon reset,and applied.
furtherprogrammingof
the EPROM is disabled.
THE ON-CHIPOSCILLATORS
P P u Same 2, also verifyis
as
disabled. -
P P P Same as 3, also external HMOSVersions
executionis disabled. cm-chip oscillator circuitry for the HMOS
— — — The
gremmed (HMOS-Iand HMOS-11)membersof the MCS-51fsm-
mogrammed ily is a singlestage tinearinverter (Figure 29), intended
for usc as a crystal-controlled,positivereactance oscil-
Any other combinationof the LockBits is not defied. lator (Figure 30). In this appficstionthe crystal is oper-
ated in ita fundsmentafresponsemode as an inductive
Table6. ProgramProtection reactarw in psralfel resonancewith capacitance-exter-
Device LocfrBite Enorypt Any nal to the crystal.
8751BH LB1, LB2 32 Bytes
8752BH LB1, LB2 32 Bytes
87C51 LB1, LB2, LB3 84 Bfles

3-30
in~. HARDWARE DESCRIPTION OF THE 8051,8052 AND80C51

xrALl

T
Suesl.
J&
01
ar
Oa

a4
loamm4AL
rnllo CUTS

ImLz

- %s
270252-23

Figure29.On-ChipOsciiiatorCircuitryinthe HMOS Versions of the MCS@-51Famiiy

In general, crystals used with these devices typically

V=*”=
have the followingspecifications:

ESR (EquivalentSeriesResistance) seeFigure 31

c20(ShuntCapacitance) 7.opFmax.
CL(bid ~pr$ei~ee) 30pF *3 pF

!-+=9
--------
msl
xrALl ---- xraLr -----
Drive Level 1 mW
ouAnr2cRvalAL
ORC6RANICRESOWIOR
0
‘a%’
. 270252-24

Figure 30. Using the HMOS On-Chip Oeciiiator

The crvstal meeifkationa and cauacitanee values (Cl

and C2-inFi&re 30)are not criti&l. 30 pF can be u&i
irr these positionsat any frequencywith good quality
crystals. A ceramic resonator can be used in place of 4 a 12 16
the crystal in cost-sensitiveapplications. When a ce- CRYS7ALFSEQUEHCV
in MHz
ramic resonatoris used,Cl and C2arenormally seleet- 270252-34
edto beof somewhat highervaluea, typically,47 pF. —. - -—— -
The manufacturer of the ceramic resonator should be Figure 31. ESR VSFr6!qUenOy
consulted for recmnmcndationson the vaiucs of thCSC
capacitors.

3-31
i@. HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

Frequency,toleranceand temperaturerange are deter- CHMOSVersions

mined by the systemrequirements.
The on-chip oscillator circuitry for the 80C51BH,
A more in-depthdiscussionof crystalspeciticstions,ce- shown in Figure 33, consists of a single stage linear
ramic reaonstors,and the selectionof valuesfor Cl and inverter intended for use as a crystal-controlled,posi-
C2 can be foundin ApplicationNoteAP-155,“Oscilla- tive reactance oscillator in the same manner as the
tors for Microcontrollers,” which is included in the HMOSparta. However, there are some important dif-
Embedded Appticatwnz Handbook. ferences.
To drive the HMOS parts with an external clock One differenceis that the 80C51BHis able to turn off
source, apply the external clock signalto XTAL2, rmd its oscillatorunder software control (by writing a 1 to
ground XTAL1,as shownin Figure32.A pullup reais- the PD bit in PCON). Another differenceis that in the
tor may be used (to increase noisemargin), but is op- 80C51BHthe internal clockingcircuitry is driven by
tional ifVOH of the drivinggate exceedsthe VIH MIN the signalat XTAL1, whereasin the HMOSversionsit
specificationof XTAL2. -- is by the signalat XTAL2.
The feedbackresistor Rfin Figure 33 consistsof paral-
leledn- and p- channel FETs controlledby the PD bit,
such that Rf is opened when PD = 1. The diodeaD1

+-!4
msl and D2, which act as clamps to VCC and VSS, are
parasitic to the Rf FETs.
EXTSRNAL
XTAU
oeenLAloR The oscillatorcan be used with the same external com-
SIGNAL XTAL1
t ponentsas the HMOS versio~ as shownin Figure 34.

V&
Typically,Cl = C2 = 30 pF when the feedbackele-
GATE v= mentis a quartz crystal, and Cl = C2 = 47 pF whena
mTsu.PoLe
ceramicreaonator is used.
OUTPUT ‘
270252-25
To drive the CHMOS parts with ass external clock
sourcq apply the external clocksignalto XTAL1, and
Figure32.Drivingthe HMOSMCS@-51 leaveXT-=2 float, as shownin F&ssre35.
Partewithan ExtemsdClockSource

m L
Mon
xrALl
c1
s

r?“
02

al

Q%e
I
270252-26

Figure 33. On-Chip Osoillsstor Circuitry In the CHMOS Versions of the MCS@-51 Family

3-32
i~e HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

w
he
70 m?lsmu F5
nsaNo curs

%s
---- —--- xrMl
----- xrAL2------

I w v 1
c1 Q
=
270252-27

Figure 34. Usingthe CHMOS On-ChipOscillator

Soeal INTERNALTIMING
MC+
I X-rAu
Figures 36 through 39 show when the various strobe
and port signals are clockedinternally.The figuresdo
not showrise and fall times of the signals,nor do they
showpropagationdelaysbetweenthe XTALsignaland
eventsat other pins.
*
Rise and fall times are dependenton the external load-
270252-28 ingthat each pin must drive.They are oftentaken to be
somethingin the neighborhoodof 10 ~ measured
Figura 35. Driving the CHMOS MCS@’-5l bemveen0.8V and 2.OV.
Parts with an External Clock Source
Propagationdelays are differentfor differentpins. For
The reason for this change from the way the HMOS a given pin they vary with pin loading temperature,
part is drivencan be seenby comparingFigures29 and VCC,and manufacturinglot. If the XTALwaveformis
33. In the HMOS devices the internal timing oircuits taken as the timing referenee, prop delays may vary
are driven by the signal at XTAL2. In the CHMOS from 25 to 125nsec.
devicesthe internal timing circuits are driven by the
signalat XTAL1. The AC Timingssectionof the data sheetsdo not refer-
ence any timing to the XTAL waveform.Rather, they
relate the criticsdedges of control and input signalsto
eaoh other. The timings published in the data sheets
include the effects of propagation delays under the
specitledtest conditions.

3-33
 HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

SYATS1 STATS2 STAY53 STATS4 SYATS5 STATS6 STATS1 ~AlS2

Imlmlmlmlnlmlmlmlm lmlmlmlmlnlm,nl
XIAk

ALS: ~

~:
4
DATA
+aANPLsD
OATA
I OATA
-SAMPLSO
w: 1 8 1 E

P2: Pet’loul Pctlour Pcnoul

270252-29
Figure 36. External Program Memory Fetches

STATS 4 STATE 5 SYATS6 SYATE1 SYAYE2 STATS3 STA= 4 SIATE5

ln,mlPllmlnlml Mlml MlwlPllmlPl IAIF+I
XTAL

‘“: ~

~& PCLOUYF
1 PRoGw NSNORY
OAIA2AMPLS0
- s axrER?4AL
OPLOR
RI FLOAT
PO:
OUT If

P2: PCHOR 0% ORP2SFRour PCHOR

P2am P2am
270252-20

Figure37.ExtemelDateMemoryRead~cle

3-34
intdo HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51

STATE4 STATE 5 2TATE 6 STATE 1 STATE

2 STATE 3 STATE4 STATE 5
I‘11’2 IPllP2IPI1’2I‘11’2I‘11’2 I PI1’2I PllP2I ‘1 I ‘2 I
XTAIJ

“’~

~: PCLOUTF
1 1 PROGRAM MEMORV
16exramu

DPLORRI
PO: OATAOUT
OuT

‘2
P2em
PcHOn
oPHoRP2amour
I Pctl
On
P2eFu 270252-31

Figure38. External Data Memory WriteCycle

STATE4 STATE 6 STATE6 2TATE 1 STATE 2 STATES STAlE4 STATES

PllP21PllP21Pl lmlnlmlmlnlmlnl nlmlPllml

Irrk

“–’HpD” x:”

NovPowr,eRc: OLOOATA N2WOATA

s!~
+ +nxo --- RxoeAuPLeo+ +
270252-32
Figure 39. Port Operation

3-35
i~. HARDWARE DESCRIPTION OF THE 8051,8052 AND80C51

ADDITIONALREFERENCES
The following application notes and articles are found in the Embedded Applications handbook.
(Order Number:270648)
1. AP-125“DesigningMicrocontrollerSystemsfor ElectricallyNoisy Environments”.
2. AP-155“Oscillatorsfor Microcontrollers”.
3. AP-252“Designingwith the 80C51BH”.
4. AR-517“Usingthe 8051Microcontrollerwith ResonantTransducers”.

3-36
8XC5U54/58Hardware 4
Description
 8XC52/54/58 CONTENTS PAGE
HARDWARE DESCRIPTION lNTRODUCTION ........................................ 4-3
PIN DESCRIPTION .................................... 4-3

DATAMEMORY ......................................... 4-3

SPECIAL FUNCTION REGISTERS........... 4-3

TIMER 2 ..................................................... 4-4

CAPTURE MODE ...................................... 4-6

AUTO-RELOAD (Up or
Down Counter) ...................................... 4-6

BAUD RATE GENERATOR........................ 4-8

PROGRAMMABLE CLOCK OUT.............. 4-9

UART..........................................................4-9
INTERRUPTS ........................................... 4-11
InterruptPriorityStructure......................... 4-11

POWER DOWN MODE ............................ 4-12

POWER OFF FLAG ................................. 4-12

ProgramMemory Lock............................. 4-12

ONCE MODE ........................................... 4-13

ADDITIONAL REFERENCES .................. 4-13

4-1
 8XC52/54/58 HARDWARE DESCRIPTION

INTRODUCTION PIN DESCRIPTION

The 8XC52/54/58 is a highly integrated 8-bit rnicro- The8XC5X pin-out is the same as the 80C51. The only
controlkx bed onthe MCSQ-51architecture.The key dit%rence is the rdternatefunction of pins P1.O and
featuresare an enhanced serial pOrtfor multi-processor P1.1. P1.Ois the external clock input for Timer 2. P1.1
communications and an up/down timer/counter. As is the Reload/Capture/Direction Control for Timer 2.
this product is CHMOS, it has two software selectable
reduced power modes: Idle Mode and Power Down
Mode. Being a member of the MCS-51 family, the DATA MEMORY
8XC52/54/58 is optimized for control applications.
The8XC5X implements 256 bytes of on-chip RAM.
This document presents a comprehensive descriptionof The upper 128 bytes occupy a parallel address space to
the on-chip hardware features of the 8XC52/54/58 as the Special Function Registers. That means they have
they ditTerfrom the 80C51BH. It begins by describing the same addresses, but they are physically separate
how the 1/0 functions are different and then discusses from SFR space.
each of the peripheralsas follows:
When an instruction acceaaesan internal location above
● 256 Bytes on-chip RAM
address 7FH, the CPU knows whether the access is to
● Special Function Registers (SFR) the upper 128 bytes of RAM or the SFR space by the
● Timer 2 addressing mode used in the instruction. Instructions
that use direct addressingaccess SFR space. For exam-
— CaptureTimer/Counter
ple,
— Up/Down Timer/Counter
— Baud Rate Generator MOV OAOH,#data (Direct Addressing)
● Full-Duplex Programmable Serial Interface with
accesses the SFR at location OAOH(which is P2). In-
— Framing Error Detection structions that use indirect addressing access the upper
— Automatic Address Recognition 128 bytes of W. For example,
● 6 InterruptSources
MOV @RO,#data (Indirect Addressing)
. Enhanced Power Down Mode
● Power Off Flag where ROcontains OAOH,accesses the data byte at ad-
dress OAOH,rather than P2 (whose address is OAOH).
● ONCE Mode
Note that stack operations are examples of indirect ad-
dressing, so the upper 128 byteaof data RAM are avail-
The 8XC52/54/58 uses the standard 8051 instruction
able as stack space.
set and is pin-for-pin mmpatible with the existing
MCS-51 family of products. Table 1 summarks the
product names and memory differences of the various
8XC52/54/58 products currently available. Through- SPECIAL FUNCTION REGISTERS
out this documentj the products will generally be re- A map of the on-chip memory area called the Special
ferred to as the 8XC5X. Function Register (SFR) space is shown in Table 2.
Table1.8XC52/54/58Microcontrollers Notethst not all ofthe addreaaesare occupied,Unoc-
~ ROM I EPROM I ROMlessl ROM/EPROM I RAM 1 cupied addresses may not be implemented on the chip.
Device Version Version Bytes Bytes Read accesses to these addresses will in general return
random dam and write amesses will have an indetermi-
80C52 87C52 80C32 8K 256 nate effect.
80C54 87C54 80C32 16K 256
80C58 87C56 80C32 32K 256 User software should not write 1s to these unlisted lo-
cations, since they may be used in future MCS-51 prod-
ucts to invoke new features. In that case the reset or
For a description of the features that are the same as
inactive values of the new bits will always be O.
the 80C51, the reader should refer to the MCS-51 Ar-
chitectural Overview, MCS-51 ProgrammersGuide/
Instruction Set, and the Hardware Description of the
80C51 in the Embedded Microcontrollers ~d pr~
sors Handbook (Order #270645).
4-3 OrdarNumbeR27078S-W4
intd. 8XC52/54/58 HARDWARE DESCRIPTION

Table 2. 8XC5X SFRMapandResetValues

OF8H OFFH

B OF7H
OFOH
)0000000

OE8H OEFH

ACC OE7H
OEOH
30000000

OD8H ODFH

Psw
ODOH OD7H
Dooooooo
T2CON T2MOD RCAP2L RCAP2H TL2 TH2
oC8H oCFH
Oooooooo
Xxxxxxoo 00000000 000000000000000000000000

OCOH OC7H

1P SADEN OBFH
OB8H Xooooooo00000000

P3 IPH
OBOF , OB7H
11111111 Xooooooo
IE SADDR OAFH
oA8k
OoooooooOooooooo
P2 OA7H
OAOl-
11111111
SCON SBUF 9FH
98t
00000000 Xxxxxxxx
P1 97H
9ot
11111111
TCON TMOD TLO TL1 THO TH1
881- 8FH
00000000 00000000 Ooooooo0 0000000000000000OoOmooo
Po SP DPL DPH PCON
8ot ~ 87H
0
11111111 00000111 00000000 0000000 00000000
L

TimerRegist ers-flmtrol and status bits areeontairred Interrupt Regiate-The individual interrupt enable
in registersT2CON and T2MOD for Timer 2. The reg- bits are in the IE register. Two prioritiescan be set for
ister pair (RCAP2H, RCAP2L) are the Capture/Re- each of the 6 interrupt sources in the IP register. The
load registersfor Timer 2 in Id-bit capture mode or 16- IPH registerallows four priorities.
bit aut&reload mode.

Serial Port Regiaters-RegM.ers SADDR and SA- TIMER 2

DEN are used to define the Given and the Broadcast
addresses for the Automatic Address Recognition fea- Timer 2 is a id-bit Timer/Counter which can operate
ture. either as a timer or an event counter. This is selectable
by bit Cm in the SPR T2CON (Table 3). It has three

4-4
i~e 8XC52/54/58 HARDWARE DESCRIPTION

operating modes:Captur%auto-reload (up or down ternafinput pin, T2. In this function, the external input
counting), and baud rate generator.The modes are ae- is sampled during S5P2 of every machine cycle. When
lected by bits in T2CON as shown in Table 4. the samples show a high in one cycle and a low in the
next cycle, the count is irtcremented.The new count
Timer 2 consists of two 8-bit registers, TH2 and TL2. value appears in the register during S3P1 of the cycle
In the Timer function, the TL2 register is incremented following the one in which the transition was detected.
every machine cycle. Thus one can think of it as count- Since it takes 2 machine cycles (24 oscillator periods) to
ing machine cycles Siuce a machine cycle consists of 12 ~- a l-to-o transition, the maximum count m~
oscillator perioda,the count rate is 1/12of the oscillator IS1/2,of the oscillator frequency. To ensure that a given
frequency. level is sampled at least once before it changes, it
should be heid for at least one fidl machine cycl;.
In the Counter function, the register is incremented in
response to a l-to-O transition at its corresponding ex-

Table 3. T2CON—Timer/Counter 2 Control Reaieter

T2CONAddress= OC8H ResetValue= 0000OOOOB

BitAddressable
TF2 EXF2 RCLK TCLK EXEN2 TR2 cPfm cP/m

Bit 7 6 5 4 3 2 1 0
Symbol Function
TF2 Timer2 overflow
flagsetbya Timer2 overflowandmustbe clearedbysoftware.TF2
willnotbe setwheneitherRCLK= 1 orTCLK= 1.
EXF2 Timer2 externalflag set wheneithera captureor reloadia causedby a negative
transition
onT2EXandEXEN2= 1. WhenTimer2 interrupt isenabled,EXF2= 1 will
causethe CPUto veetorto the Timer2 interruptroutine.EXF2mustbe clearedby
software.EXF2doesnotcausean interrupt inup/downcountermode (DCEN = 1).
RCLK Receiveclockenable.Whense~causestheserialportto useTimer2 overflowpulses
foritsreceiveclockin serial portModes 1 and 3. RCLK = Ocauses Timer 1 overflow
to
be usedforthereceiveclock.
TCLK Transmit clockenable.Whenset,causestheserialportto useTimer2 overflow pulses
for itstransmit
clockin serial port Modes 1 and 3. TCLK = (1~usgs Timgr 1 ovgrflows
to beusedforthetransmitclock.
EXEN2 Timer2 externalenable.Whenset,allowsa ~pture or reloadto occurssa resultof a
negativetransition
onT2EXifTimer2 isnotbeingusedto clocktheserialport.EXEN2
= OcausesTimer2 to ignoreeventsat T2EX.
TR2 Start/StopcontrolforTimer2. TR2 = 1 startsthetimer.
cm! TimerorcounterselectforTimer2.C/~ = Ofortimerfunction.
C/~ = 1 forexternal
eventcounter(fallingedgetriggered).
cPlm Capture/Reloadselect.CP/~ = 1 causescapturesto occuronnegative transitions
at T2EXif EXEN2= 1. CP/~ = Ocausesautomatic reloadsto occurwhenTimer2
overflowsor negativetransitions
occurat T2EXwhenEXEN2= 1. WheneitherRCLK
or TCLK= 1, thisbit is ignoredandthe timeris forcedto auto-reload
on Timer2
overtlow.

4-5
 8XC52/54/58 HARDWARE DESCRIPTION

Table 4. Timer 2 Operating Modes

RCLK + TCLK cPlm TR2 MODE
o 0 1 16-BitAuto-Reload
I o I 1 Ill 16-BitCapture I
I 1 I x Ill BaudRateGenerator I
I x I x Iol oft-l I
CAPTURE MODE is invoked by a bit named DCEN (Down Counter En-
able) located in the SFR T2MOD (see Table 5). Upon
In the capture mode there are two options selected by reset the DCEN bit is set to O so that Timer 2 wilf
bit EXEN2 in T2CON. If EXEN2 = O, Timer 2 is a default to count up. When DCEN is set, Timer 2 can
16-bit timer or counter which upon overfiow sets bit count up or down depending on the value of the T2EX
TF2 in T2CON. This bit can then be used to generate pin.
an interrupt. If EXEN2 = 1, Timer 2 still does the
above, but with the added feature that a 1-to-Otran- Figure 2 shows Timer 2 automatically counting up
sition at external input T2EX eauaes the current value when DCEN = O.In this mode there are two options
in TH2 and ‘fZ2 to be captured into RCAP2H and selected by bit EXEN2 in T2CON. If EXEN2 = O,
RCAP2L, respectively. In additio~ the transition at Timer 2 counts up to OFFFFH and then sets the TF2
T2EX esuaes bit EXF2 in T2CON to be set. The EXF2 bit upon overflow. The overtlow also causes the timer
bit, like TF2, ean generate an interrupt. The capture registers to be reloaded with the 16-bit value in
mode is illustrated in Figure 1. RCAP2H and RCAP2L. The values in RCAP2H and
RCAP2L are preset by software. If EXEN2 = 1, a
16-bitreload can be triggeredeither by an overfiow or
AUTO-RELOAD (Up or Down Counter) by a l-to-O transition at external input T2EX. This
transition also sets the EXF2 bit. Eoth the TF2 and
Timer 2 can be programmedto count up or down when EXF2 bita ean generatean intemupt if enabled.
contlgursd in its 16-bit auto-reload mode. This feature

OJ c/E = 1 I CONTROL
TR2
-.m-..--

piaiim
LAt’l UKt.
T2 PIN I II

TRANSITION
OUECTION
I +
TIMER2
INTERRUPT

T2EX PIN I
+X1 ~

I CONTROL
EXEN2
2707S3-1

Figure1.Timer2 inCaptureMode

4-6
i@. 8XC52/54/58 HARDWARE DESCRIPTION

----- -. .------ ...... . - ------ -------- ..-=-----

T2MODAddress= OC9H ResetValue= )(XXXXXOOB

NotBitAddressable
— — — — — — T20E DCEN

Bit 7 6 5 4 3 2 1 0

8ymbol Function
Notimplemented,
reservedforfutureuse.
T20E Timer2 OutputEnablebit.
DCEN Whenset,thisbitallowsTimer2 to be configured
asan up/downcounter.

OVERFLOW
cm= 1
TR2
d RELOAD
T2 PIN
TIMER2
INTERRUPT

TRANSMON
DEI’ECTION

T2EX PIN
I+q

I CONTROL
EXEN2
2707S2-2

Figure 2. Timer2 Auto Reload Mode (DCEN = O)

(DOWN COUNTINGRELOADVALUE)
TOGGLE
OFFH 1 OFFH
1 [

cfi2=t #~NTROL TIMER2

&f
INTERRUPT
T2 PIN

(UP COUNTINGRELOADVALUE)

T2EX PIN
2707SS-3

Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

4-7
i~m 8XC52/54/58 HARDWARE DESCRIPTION

l-l
I Osc 1
1

I
TL2 : TH2
● (S.-Blt$) :(S-Bite)

I
TR2

) Cfi Bit

P1.o
(T2)
1
I +2
}
I*
1
a
1
I I

~T&%:n T20E (T!2MO0.1)

P1.1
(’22X)
1<1
I
I

I
EXF2
I ‘
Timer 2
Interrupt

EX~N2
270783-6

Figure 4. Timer 2 in Clock-Out Mode

Setting the DCEN bit enables Timer 2 to count up or BAUD RATE GENERATOR
down as shown in Figure 3. In this mode the T2EX pin
controls the direetion of count. A logic 1 at T2EX Timer 2 is selectedas the baud rate generatorby setting
makes Timer 2 count up. The timer will overflow at TCLK and/or RCLK in T2CON (Table 3). Note that
OFFFFH and set the TF2 bit. This overtlow also causes the baud ratesfor transmit and receive can be different.
the 16-bit value in RCAP2H and RCAP2L to be re- This is accomplished by using Timer 2 for the receiver
loaded into the timer registers, TH2 and TL2, respec- or transmitterand using Timer 1 for the other function.
tively. Setting RCLK rind/or TCLK puts Timer 2 into its
baud rate generatormode, as shown in Figure 5.
A logic O at T2EX makes Timer 2 count down. Now
the timer underfiows when TH2 and TL2 equal the The baud rategeneratormode is similar to the auto-re-
values stored in RCAP2H and RCAP2L. The rmder- load mod%in that a rollover in TH2 causes the Timer 2
flow sets the TF2 bit and causes OFFFFH to be reload- registersto be reloadedwith the id-bit vrduein registers
ed into the timer registers. RCAP2H and RCAP2L, which are preset by software.

The EXF2 bit toggles whenever Timer 2 overtlows or The baud rates in Modes 1 and 3 are determined by
undertows. This bit ean be used as a 17th bit of resolu- Timer 2’s overtlowrate as follows:
tion ifdeaired. In this operating mode, EXF2 does not
flag an interrupt. Timer2 Overflow Rate
Modea 1 and 3 Baud Ratea =
16

4-8
intde 8XC52/54/58 HARDWARE DESCRIPTION

The Timer can be configured for either “timer” or The Clock-Out frequencydepends on the oscillator fre-
“counter” operation. In most apj&ations, it is contlg- quency and the reload value of Timer 2 capture regis-
ured for “timer”operation (CP/T2 = O).The “timer” ters (RCAP2H, TCAP2L) as shown in this equation:
operation is different for Timer 2 when it’s being used
es a baud rategenerator. Normally, as a timer, it incre- Oscillator
Frequency
ments every machine cycle (thus at 1/lz the oscillator
Clock-Out
Frequency
=
4 X (65536 - RCAP2ti, RC2AP2L)
frequency). As a baud rate generator,however, it incre-
ments every state time (thus at 1/2the oscillator fre- In the clock-out mode, Timer 2 roll-overs will not gen-
quency). The baud rate formula is given below: erate an interrupt. This is similar to when Timer 2 is
used as a baud-rate generator.It is possible to use Tim-
Modes 1 and3 = OscillatorFrequency er 2 as a baud-rate generator and a clock generator
Baud Rate 32X [65536 – (RCAP2H, RCAP2L)1 simultaneously. Note, however, that the baud-rate and
clock-out frequencies can not be determined indepen-
where (RCAP2H, RCAP2L) is the content of dently from one another since they both use RCAP2H
RCAP2H end RCAP2L takemas a 16-bit unsigned in- and RCAP2L.
teger.

Timer 2 es a baud rate gemerstoris shown in Figure 5. UART

This figure is valid only if RCLK or TCLK = 1 in
T2CON. Note that a rollover in TH2 does not set TF2, TheUART in the 8XC5X operates identically to the
and will not generate an interrupt. Note too, that if UART in the 80C51 except for the following enhsnce-
EXEN2 is se~ a l-to-O transition in T2EX will set menta. For a complete understanding of the 8XC5X
EXF2 but will not cause a reload from (RCAP2H, UART please refer to the description in the 30C51
RCAP2L) to (’fH2, TL2). Thus when Timer 2 is in use Hardware Description chapter in the Embedded Mi-
as a baud rategenerator, T2EX can be used as an extra crocontroller’sand ProcessorsHandbook.
exte.mal interrupt,if desired.
Franting Error Detection-Framin g Error Detection
It should be noted that when Timer 2 is running (TM allows the serial port to check for valid stop bits in
= 1) in “tinter” fintction in the baud rate generator modes 1, 2 or 3. A missing stop bit can be caused for
mode, one should not try to read or write TH2 or TL2. example, by noise on the seriallinesj or transmission by
Under these conditions the Timer is being incremented two CPUS simultaneously.
every state time, end the results of a reed or write may
not be accurate.The RCAP2 registersmaybe remLbut If a stop bit is missing a Framing Error bit (FE) is set.
shouldn’t be written to, because a write might overlap a The FE bit can be checked in softwsre after each recep-
reload end cause write end/or reload errora.The timer tion to detect communication errors. Once set, the FE
should be turned off (clear TR2) before accessing the bit must be cleared in sotlwsre. A valid stop bit will not
Timer 2 or RCAP2 registers. clear FE.

The FE bit is located in SCON and shares the same bit

PROGRAMMABLE CLOCK OUT addreesas SMO.Control bit SMODOin the PCON reg-
ister (location PCON.6) determines whether the SMO
A 50% duty cycle clock can be programmed to come or FE bit is amessed. If SMODO = O,then mcesaes to
out on P1.O.This pim besides being a regular1/0 pin, SCON.7 are to SMO.If SMODO = 1, then -ses to
has two alternatetimctions. It can be programmed (1) SCON.7 are to FE.
to input the external clock for Timer/Counter 2 or (2)
to output a 50~0 duty cycle clock ranging from 61 Hz Automatic Address R eeognition-Autornatic Address
to 4 MHz at a 16 MHz operating frequency. Recognition reduces the CPU time required to service
theserialport.SincetheCPUisonlyinterruptedwhen
To configurethe Timer/Counter 2 as a clock generator, it receives its own address, the software overhead to
bit C/T.2 (T2CON.1) must be cleared and bit T20E compare addresses is eliminated. With this featureen-
(T2MOD.1) must be set. Bit TR2 (T2CON.2) starts abled in one of the 9-bit modes, the Receive Interrupt
and stops the timer. (RI) tlag will only get set when the received byte corre-
sponds to either a Oiven or Broadcast address.

4-9
infd. 8XC52/54/58 HARDWARE DESCRIPTION

TIMER 1 OVERFLOW

=&Os::Q::”B:NOT .

----- --- RCLK Rx

.fl~., %dRCJL
TR2
d
T2 PIN

TRANSmON
DETECTION

T2EX PIN
+X1 ;+

[ CONTROL
EXEN2
2707SS-4
—. — —
Fi9ure 5. Timer 2 in BaudRate Generator Mode

A way to use this feature in multiprocessor systems is A slave’s individual addreas is specifkd in SADDR.
asfollows: SADEN is a mask byte that defines don’t-care bits to
form the Given Addreas.These don’t-caresallow flexi-
When the master processorwantato transmit a block of bility in the user-defined protocol to address one or
&ta to one of several slaves, it ftrst sends out an ad- more slavea at a time. The following is an example of
dreaabyte which identities the target slave. Remember, how the user ecndddefine Given Addresses to selective-
an address byte has its 9th bit set to 1, whereas a data ly address ditYerentslavea.
byte has its 9th bit set to O. AU the slave processors
should have their SM2 bits set to 1 so they will only be Slave 1:
interruptedby an addreasbyte. The Automatic Address .
Recognition feature allows only the addressed slave to
SADDR 11110001
SADEN . 11111010
be interrupted. In this modej the addreaacomparison
occurs in hardware, not software. (On the 80C51 aerial GIVEN . 1111oxox
port, an address byte interruptsall slaves for an address
comparison).
Steve2:
The addressed slave then clears its SM2 bit and pr~ SADDR . 11110011
pares to receive the data byteathat will be coming. The SADEN . 11111001
other slaves are unaffected by these data bytea as they
are still waiting to receive an address byte. GIVEN — 1111 Oxxl
The feature works the same way in the 8-bit mode TheSADENbitsareselectedsuchthat eachslavecan
(Mode 1) as in the 9-bit modes, except that the stop bit be addressedseparately. Notice that bit O (LSB) is a
takes the place of the 9th data bit. If SM2 is @ the RI don’t-care for Slave 1’s Given Address, but bit O = 1
flag is set only if the receivedbyte matches the Given or for Slave 2. Thus, to selectively comtnunieate with just
Broadeast Address and is terminated by a valid stop Slave 1 thetnaster must send an address with bit O = O
bit. Setting the SM2 bit has no effect on Mode O. (e.g., 1111 OOIM).

The master can selectively communicate with groups of Similarly, bit 1 = Ofor Slave 1, but is a don’t-care for
slavea by using the Given Address. Addressing all Slave 2. Now to communicate with just Slave 2 an ad-
slaves at once is possible with the Broadcast Address. dreaawith bit 1 = 1 must be used (e.g., 1111 0111).
These addresses are defined for each slave by two Spe-
eial Function Registers:SADDR and SADEN.

4-1o
it@le 8XC52/54/58 HARDWARE DESCRIPTION

Finally, for a master to communicate with both slaves rupts (Timers O, 1 and 2) and the serial port interrupt.
at once the addressmust have bit O = 1 and bit 1 = O. These interrupts are all shown in Figure 6.
Notice, however, that bit 2 is a don’t-care for both
slaves. This allows two difTerentaddresses to select Tinter 2 Interruptis generatedby the logical OR of bits
both slaves (1111 0001 or 1111 0101). If a third slave TF2 and EXF2 in register T2CON. Neither of theae
was added that required its bit 2 = O, then the latter flags is cleared by hardwarewhen the scMce routine is
addreascould be used to communicate with Slave 1 and vectored to. In fact, the service routine may have to
2 but not Slave 3. determine whether it was TF2 or EXF2 that generated
the intemupt and that bit will have to be cleared in
The master can also communicate with all slaves at software.
once with the BroadcastAddress. It is formed from the
logical OR of the SADDR and SADEN registerswith The Timer Oand Timer 1 flags, TFOand TF1, are set at
zeroes defined as don’t-cares. The don’t-cares also al- S5P2 of the cycle in which the tinters overtlow. The
low flexibility in defiig the Broadcast Address, but in values are then polled by the circuitryin the next cycle.
most applications a BroadcastAddress will be OFFH. However, the Timer 2 tlag, TF2 is set at S2P2 and is
polled in the same cycle in which the timer overflows.
SADDR and SADEN are located at addressOA9Hand
OB9H, respectively. On reset, the SADDR and
SADEN registers are inidalized to OOHwhich defines Interrupt Priority Structure
the Oiven and Broadcast Addresses as XXXX XXXX
(all don’t-cam). This assuresthe 8XC5X serial port to A seumd Interrupt Priority register (ET-I) has been
be backwards compatible with other MCS@-51prod- added, increasing the number of prioritylevels to four.
ucts which do not implement automatic address recog- Table 6 shows this second register.The added register
nition. becomes the MSB of the priority select bits and the
existing 1P register acts as the LSB. This scheme main-
tains compatibility with the reatof the MCS-51 family.
INTERRUPTS Table 7 shows the bit values and prioritylevels associ-
ated with each combination. “
The8XC5X hasa——
total of 6 interrupt vectors: two ex-
ternal interrupts (INTO and INT1), three timer inter-

.- -
IPH Address= OB7H ResetValue= XOOO
0000
— PPCH PT2H PSH PTIH PXIH PTOH PXOH

Bit 7 6 5 4 3 2 1 0

Symbol Function
— NotImplemented,
reserved
forfutureuse.
PPCH PCAinterrupt
priorityhighbit.
PT2H Timer2 interruptpriority high bit.

PSH serial Port interrupt priority high bit.

PTIH Timer1interrupt
priority
highbit.
PXIH External
interrupt
1 priority
highbit.
PTOH TimerOinterrupt
priority
highbit.
PXOH External
interrupt
priority
highbit.

4-11
in~. 8XC52/54/55 HARDWARE DESCRIPTION

Table 7. Priority Level Bit Values With an external interrupt, ~ or ~ must be en-
abled and configured as level-sensitive before entering
Power Down. Holding the pin low restartsthe Oscilla-
tor and bringing the pin back high completes the exit.
After the RETI instruction is executed in the interrupt
seMce routin%the next instruction will be the one fol-
lowing the instruction that put the device in Pow=
Down.
11101 Level2 I
11111 Level3 (Hiahest) I
POWER OFF FLAG
ThePower Off Flag (POF) located at PCON.4 is set by
POWER DOWN MODE hardwarewhen VCCrises from Oto approximately 5V.
POF can also be set or cleared by software.This allows
The 8XC5X can exit Power Down with either a hard- the user to distinguish between a “cold start” reset and
ware reaetor external interrupt. Reset redefines all the a “warm start” reset.
SFRS but deea not change the on-chiD RAM. An exter-
nal interrupt allows ~th the SF& (except PD in A cold start reaet is one that is coincident with Vcc
PCON) and the on-chip RAM to retairstheir values being turned onto the device after it was turned off. A
warm start reset occurs while VCCis still applied to the
device and could be generated, for example, by an exit
from Power Down.

Immediately after reset, the usefs software can check

the status of the POF bit. POF = 1 would indicate a
cold start. The software then clears POF and com-
mences ita tasks. POF = O immediately after reset
would indieete a warm start.

Vcc must remain above 3V for POF to retain a O.

‘*
Program Memory Lock
In some microcontroller applicationsit is desirable that
the Program Memory be secure from software piracy.
The 8XC5X has varying degrees of programprotection
depending on the device. Table 8 outlines the lock
schemes available for each device.

Encryption Array: Within the EPROM/ROM is sssar-

ray of encryption bytes that are initially unprogrammed
(sU l’s). For EPROM devices, the user can program
the encryption array to encrypt the programcode bytes
during EPROM veritktion. For ROM devices, the
risersubmits the encryption arrayto be programmed by
the factory. If an encryption array is submitted, LB1
will also beprograrnrnedby the factory.The encryption
array is not available without the Lock Bit. Program
Figure 6. Interrupt Bources cmle verificationis petformed as usual except that each
code byte comes out exclusive-NOR’ed ~NOR) with
To properlyterminate Power Down the reset or exter- one of the key bytes. Therefore, to read the
nal interrupt should not be applied before VCC is re- ROIWEPROM cede, the user has to know the encryp-
stored to its normal operating level and must be held tion key bytes in their proper sequence.
active long enough for the oscillator to reatartand sta-
bilize (normally leas than 10 msec). Unprogrammed bytes have the value OFFH. If the En-
cryption Array is left unprogrammed,all the key bytes
have the value OFFH. Since any code byte XNOR’ed

4-12
i@. 8XC52/54/58 HARDWARE DESCRIPTION

with OFFH leaves the byte unchanged, leaving the En- ONCE MODE
cryption Array unprogrammed in effect bypasses the
encryption festure. TheON-Circuit Emulation (ONCE) mode facilitates
testing and debugging of systems using the 8XC5X
e Lock Bits: Also included in the Program without having to remove the device from the circuit.
Lock scheme are Lock Bits which can be enabled to The ONCE mode is invoked by either:
provide varying degreea of protection. Table 9 lists the
1. _ ALE low while the device is in reset and
Lock Bits and their correspondinginfluence on the mic- PSEN is high;
rocontroller. Refer to Table 8 for the Lock Bits avsil-
able on the various products. The useris responsiblefor 2. Holding ALE low as RESET is deactivated.
programming the Lock Bits on EPROM devices. On
ROM deviwsi, LB1 is automatically set by the factory While the device is in ONCE mode, the Port Opins go
when the encryption array is submitted. The Lock Bit into a float state and the other port pins, ALE and
is not available without the encryptionarray on ROM PSEN are weakly pulled high. The oscillator circuit
devices. remains active. While the device is in this mode, an
emulator or test CPU can be used to drive the circuit.
Erasing the EPROM also erases the Encryption Array
and the Lock Bits, returning the partto tldl functionali- Normal operation is restored after a valid reset is ap
ty. plied.

Table 8. Program Protection

ADDITIONAL REFERENCES
Devioe Lock Bits Encrypt Array
80C52 LB1 84 Bytes Thefollowingapplication notes provide supplemental
information to this document and can be found in the
80C54 LB1 84 Bytes
EmbeddedApplicatwnshandbook (Order No. 270648).
80C58 LB1 84 Bytes
LB1, LB2, LB3 84 Bytee 1. AP-125 “Designing Microcontroller Systems for
87C52
Electrically Noisy Environments”
87C54 LB1, LB2, LB3 64 Bytes
87C58 LB1, LB2, LB3 84 Bytes 2. AP-155 “Oscillatorsfor Microcontrollers”
3. AP-252“Deaigning with the 80C51BH”
4. AP-41O“Enhanced serial Port on the 83C51FA”

Table9. LockBits
I Program I I
LockBite Protection Type
LBl LB2 LB3
1 u u u Noprogram lockfeaturesenabled.(Codeverifywillstillbeencrypted
bythe
encryption
arrayifprogrammed.)
P u -u-fetching
MOVCinstructions
executedfromexternalprogram
codebytesfrominternalmemory,
memoryaredisabled
EAissampledandlatchedon
from

reset,andfurtherprogramming
oftheEPROMisdisabled.
I 3 I P I P I U I Bameas2.alsoverifvisdisabled. I
4 P P P Bameas 3, also externalexecution
isdisabled.
P = Programmed
U = Unprogrammed
Any other combination of Lock Bits is not defined.

4-13
8XC51FX Hardware 5
Description
 HARDWARE DESCRIPTION OF THE 8XC51FX

CONTENTS PAGE CONTENTS PAGE

1.0 INTRODUCTION .................................. 5-3 7.4 Baud Rates .................................... 5-3o
7.5 Using llmer 1 to Generate Baud
2.0 MEMORY..............................................5-3 Rates ................................................ 5-30
2.1 Program Memory ............................. 5-3 7.6 Using Timer 2 to Generate Baud
2.2 Data Memory ................................... 5-3 Rates ................................................ 5-30
3.0 SPECIAL FUNCTION 8.0 INTERRUPTS .....................................5-32
REGISTERS ........................................... 5-4 8.1 External Interrupts ......................... 5-33
4.0 PORT STRUCTURES AND 8.2 Timer Interrupts.............................. 5-33
OPERATION ........................................... 5-7 8.3 PCA Interrupt ................................. 5-33
4.1 [/0 Configurations ............................ 5-7 8.4 Serial Porl Interrupt........................ 5-33
4.2 Writing to a Port ............................... 5-8 8.5 Interrupt Enable ............................. 5-33
4.3 Port Loading and Interfacing .......... 5-1Cl 8.6 Priority Level Structure ..................5-33
4.4 Read-Modify-Write Feature............ 5-10 8.7 Response Time. ............................. 5-37
4.5 Accessing External Memory .......... 5-10
9.0 RESET ................................................5-37
5.0 TIMERWCOUNTERS ......................... 5-12 9.1 Power-On Reset ............................ 5-38
5.1 TIMER OAND TIMER 1.................5-12
10.0 POWER-SAVING MODES OF
5.2 TIMER 2.... ..................................... 5-15 OPERATION ......................................... 5-38
6.fl~l:~RAMMABLE COUNTER 10.1 idle Mode ..................................... 5-38
..................................................5-18 10.2 Power Down Mode ...................... 5-40
6.1 PCA 16-Bit Timer/Counter ............. 5-20 10.3 Power Off Flag ............................. 5-40
6.2 Capture/Compare Modules............ 5-22
11.0 EPROM VERSIONS ......................... 5-40
6.3 16-Bit Capture Mode...................... 5-24
6.4 16-Bit Software Timer Mode .......... 5-24 12.0 PROGRAM MEMORY LOCK. .......... 5-40
6.5 High Speed Output Mode .............. 5-25
13.0 ONCE MODE ................................... 5-41
6.6 Watchdog Tmer Mode................... 5-25
6.7 Pulse Width Modulator Mode. ........ 5-26 14.0 ON-CHIP OSCILLATOR................... 5-42

7.0 SERIAL INTERFACE ......................... 5-27 15.0 CPU TIMING .................................... 5-43
7.1 Framing Error Deteotion ................ 5-28
7.2 Multiprocessor Communications.... 5-28
7.3 Automatic Address Recognition ..... 5-28

5-1
in~. 8XC51FX HARDWARE DESCRIPTION

1.0 INTRODUCTION Table1.C51FXFamilyof Microcontroller

The 8XC51FX is a highly integrated 8-bit rnicroeon- ROM/

ROM
trollerbasedon the MCS-51 architecture.As a member ‘PR?M ‘OM!es EPROM ‘AM
Device Version VeraIon ~mes Sytes
of the MCS-51 family, the 8XC51FX is optimized for
control applications. Its key feature is the programma- 83C51FA 87C51FA 80C51FA 8K 256
ble counterarray (PCA) which is capableof measuring
and generatingpulse information on five 1/0 pina. Also 183C51FB187C51FBI 80C51FAI 18K I 256 I
included are an enhanced serial port for muM-proces-
i83C51FC187C51FCI 80C51FAI 32K I 256 t
sor communications, an up/down timer/counter, and a
programlock scheme for the on-chip programmemory.
Since the 8XC51FX products are CHMOS, they have
two software selectable reduced power modes: Idle 2.0 MEMORY ORGANIZATION
Mode and Power Down Mode.
All MCS-51 devices have a separate address space for
The 8XC51FX usea the standard 8051 instruction set Program and Data Memory. Up to 64 Kbytes each of
and is pin-for-pin compatible with the existing MCS-51 external Programand Data Memory can be addressed.
family of products.

This domrnent presents a comprehensivedescription of 2.1 Program Memory

the on-chip hardware features of the 8XC51FX. It be-
gins with a discussion of the on-chip memory and then If the= pin is connected to VX, all program fetches
discuaseaeach of the peripherals listed below. are directed to external memory. On the 83C51FA (or
87C51FA), if the = pin is connected to VCc, then
Please note that 8XC51FX does not include the program fetches to addresses OOWHthrough IFFFH
80C51FA and 83C51FA. l%ereforq these devices do are directed to internal ROM and fetches to addresses
not have some of the features found on the 8XC51FX. 2000H through FFFFH are to external memory.
These featuresare: progmmmable clock out, four level
interrupt priority structure, enhanced program lock On the 83C51F%(or 87C51FB) if= is connected to
scheme and asynchronous port reset. VCC, program fetches to addresses OOOOH through
3FFFH are directed to internal ROM, and fetches to
● Four 8-Bit Bidirectional Parallel Ports
addresses40tMHthrough FFFFH are to externalmem-
● Three 16-Bit Timer/Counters with ory.
— One Up/Down Timer/Counter
On the 83C51FC (or 87C51FC) if= is connected to
— Clock Out Vcc, program fetches to addreasra OOOOH through
● pro~ble COunterArrsY with 7FFFH are directed to internal ROM or EPROM and
— Compare/Capture fetches to addresses 8CCIOH
through FFFFH are to ex-
ternal memory.
— SoftwareTimer
— High Speed Output
— Pulse Width Modulator 2.2 Data Memory
— Watchdog Timer The C51FX implements 256 bytea of on-chip data
c Full-Duplex Prograrmnable Serial Port with RAM. The upper 128 bytes occupy a parallel address
space to the Special Function Registers. That means
— Framing Error Detection
they have the same addresses, but are physically sepa-
— Automatic Address Recognition rate from SFR space
● Interrupt Stmcturewith
When an instruction accessraan internal location above
— SevenInterrupt Som
address 7FH, the CPU knows whether the access is to
— Four priority kds the upper 128 bytes of data RAM or to SFR space by
● Power-SavingModea the addressing mode used in the instruction. Instmc-
tions that use direct addressing access SFR space. For
— Idle Mode
example:
— Power Down Mode
MOV OAOH,#data
Table 1 summarizs the product names and memory
differencesof the various 8XC51FX products currently
available.Throughout this document, the products will
generallybe referredto as the C51FX.

5-3
i~o 8XC51FX HARDWARE DESCRIPTION

PO.O-PO.7 P2.O- P2.7

g
;?
r ----------

!!8-&!#
----------
m
I I
I
I F g --
5
()!== I
I
Posl o 1
IA7CH I
I
I
1
I
I I
u #
I II :
c
I
I
1 till
ACC

I
I
I
I

!-f- m II II Imrl I
I

HI I
m ----------- ------
POSTS
ORNSRS
I
I t I

INN]
-- A

JxL ‘“ P1.O-P1.7 P3.O-PS.7

L
=
270S53-1
-:-----
rlgure .i. =Ak.alrA
..”.-. E.- .?..
rurwuonal DIUGKwagram -_t, ---, c.. -_,. m:--.._—

accesses the SFR at location OAOH(which is P2). In- 3.0 SPECIAL FUNCTION REGISTERS
structionsthat useindirectaddressingaccess the upper
128 bytes of data IUM. For example: A map of the on-chip memory area called the SFR
(Speciaf Function Register) space is shown in Table 2.
MOV @RO,#data
Note that not alf of the addresses are occupied. Unoc-
where ROcontains OAOH,accesses the data byte at ad- cupied addresses are not implemented on the chip.
dress OAOH,rather than P2 (whose address is OAOH). Read aweases to these addresses will in generafreturn
Note that stack operations are examples of indireet ad- random dam and write aeceaseswill have no effect.
dressing,so the upper 128 bytes of data IWM are avail-
able as stack space.

5-4
irrtd. 8XC51FX HARDWARE DESCRIPTION

User software should not write 1s to these unimple- The fhnctionsof the SFRS are outlined below. More
mented locations, sinoe they may be used in future information on the use of specific SFRS for each periph-
MCS-51 products to invoke new features In that ease eral is included in the description of that peripheral.
the reset or inactive values of the new bits will always
be O,and their active values will be 1. Accumdaton ACC is the Accumulator register. The
mnemonies for AecurnuMor-Speoitic instructions,
however, refer to the Accumulator simply as A.

Table 2.SFRMappingand ReaetValuea

F8 CH CCAPOH CCAPIH CCAP2H CCAP3H CCAP4H FF
00000000 Xxxxxxxx Xxxxxxx Xxxxxxxx XxxxMxx Xxxxxxx
FO “B F7
00000000
E8 CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L EF
00000000 )waxxxx XxxxXXX XmxxxXX Xxxxxxxx Xxxxxxxx
EO * ACC E7
00000000
Da CCON CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4 DF
OoxoooooOoxxxooo Xooooooo Xooooooo Xooooooo Xooooooo Xooooooo
Do * Psw D7
00000000
C8 T2CON T2MOD RCAP2L RCAP2H T12 TH2 CF
00000000Xxxxxxoo 00000000 00000000 00000000 00000000
co C7

B8 * 1P SADEN BF
Xooooooo 00000000
BO * P3 IPH B7
11111111 Xooooooo
A8 * IE SADDR AF
00000000 00000000
AO “ P2 A7
11111111
98 “ SCON * SBUF 9F
OooooooaXxxxXxX
90 * P1 97
11111111
88 * TCON * TMOD * TLO * TL1 * THO ● TH1 8F
00000000 00000000 00000000 00000000 00000000 00000000
80 * Po ● SP “ DPL * DPH “ PCQN● * 87
11111111 00000111 00000000 00000000 Ooxxoooo
*= Foundinthe8051core(see8051HardwareDasoriotion
forexplanations
of theseSFRS).
..
“* = Seedescription
of PCONSFR.BitPCON.4
is notaffectedbyreset.
X = Llndafinad.

5-5
i~e 8XC51FXHARDWAREDESCRIPTION

Table 3. PSW: Program Statua Word Regiater

Psw Address= ODOH ResetValue= 0000OOOOB

BitAddressable
CY AC FO RSI RSO Ov I — P
Bit 7 6 5 4 3 2 1 0

Symbol Function
CY Carryflag.
AC AuxiliaryCarryflag. (For BCDOperations)
FO FlagO.(Availableto the userfor generalpurposes).
RS1 Registerbankselectbit 1.
RSO Registerbankselectbit O.
RS1 RSO Working Register Sank and Addreee
o 0 BankO (OOH-07H)
o 1 Bank1 (08H-OFH)
1 0 Bank2 (1OH-17H)
1 1 Bank3 (18H-l FH)
Ov Overflowflag.
— Userdefinableflag.
P Parityflag. Set/clearedbyhardwareeachinstructioncycleto indicateanodd/even
numberof “one” bitsinthe Accumulator,i.e.,evenparity.

B RegisteE The B registeris used during multiply and RCAP2L) are the capture/reload registemfor Timer 2
divide operations.For other instructions it can be treat- in Id-bit capture mode or Id-bit auto-reload mode.
ed as another scratch pad register.
Pmgmmmable Counter Array (PCA) Re@ters: The
Stack Pointer: The Stsek Pointer Register is 8 bits 16-bit PCA timer/counter cxmsistsof registers CH and
wide. It is incremented before &ta is stored during CL. Registers CCON and CMOD contain the control
PUSH and CALL executions. The stsek may reside and status bits for the PCA. The CCAPMn (n = O, 1,
~ywhere in on-chip R4M.Onreset, the Stack Pointer 2, 3, or4) registerscontrol the mode for each of the five
is initialized to 07H causing the stack to begin at loca- PCA modules. The registerpairs (CCAPnH, CCAPnL)
tion 08H. are the id-bit compare/capture registersfor each PCA
module.
Data PointeE The Data Pointer (DPTR) consists of a
high byte (DPH) and a low byte (DPL). Its intended Serial Port Registers: The Serial Data ButTer,SBUF,
function is to hold a 16-bit address, but it may be ma- is actually two separate registers:a transmit buffer and
nipulated as a Id-bit register or as two independent a receivebutYerregister. When data is moved to SBUF,
8-bit registers. it goes to the transmit buffer where it is held for serial
transmission. (Moving a byte to SBUF initiates the
Program Status Word: The PSW registercontains pr- transmission). When data is moved from SBUF, it
gram statusinformationasdetailedin Table3. comesfrom thereceive
btier. Register
SCONcontains
the control and status bits for the Serial Port. Registers
Ports Oto 3 Registers: PO,Pl, P2, and P3 are the SFR SADDR and SADEN are used to define the Given and
latches of Port O,Port 1, Port 2, and Port 3 respective- the Broadcast addresses for the Automatic Address
ly. Recognition feeture.

Timer Registers:Registerpairs (THO,TLO), (’THL Interrupt Regiatam: The individual interrupt enable
TL1), and (TH2, TL2) are the id-bit count registersfor bits are in the IE register. Two prioritiescan be set for
Timer/Counters O, 1, and 2 rqeetively. Control and each of the 7 interrupts in the 1P register.
statusbita are containedin registersTCON and TMOD
for Timers O and 1 and in registers T2CON and Power Control Register: PCON controls the Power
T2MOD for Timer 2. The register pair @CAF2H, Reduetion Modes. Idle and Power Down Modes.

5-6
i@. 8XC51FXHARDWAREDESCRIPTION

4.0 PORT STRUCTURES AND Table 4. Alternate Port Functions

OPERATION
Port Pin AlternatePunction
All four ports in the C51FX are bidirectional. Wch
consists of a latch (Special Function Registers PO PO.O/ADO- Multiplexed Byte of Address/Data for
through P3), an output driver, and an input buffer. PO.7/AD7 External Memory
P1.OA--2 Timer 2 External Clock Input/Clock-
The output drivers of Ports Oand 2, and the input buK- Out
ers of Port O,are used in accesses to external memory. P1.1/TX3X Timer 2 Reload/Capture/Direction
In this application, Port O outputs the low byte of the Control
external memory address, time-multiplexed with the
byte being written or read. Port 2 outputs the high byte P1.2/ECI PCA External Clock Input
of the external memory address when the address is P1.3/CEXO PCA Module OCaptureInput,
16 bits wide. Otherwise the Port 2 pins continue to emit Compare/PWM Output
the P2 SFR content. P1.4/CEXl PCA Module 1 CaptureInput,
Compare/TWM Output
All the Port 1 and Port 3 pins are multifimctional.
They are not only port pins, but also serve the functions P1.5/CEX2 PCA Module 2 CaptureInput,
of various special featureaas listed in Table 4. COmpare/PWMOutput
P1.6/CEX3 PCAModule 3 CaptureInpuL
The alternatetimctions can only be activated if the cor- Compare/PWM Output
respondingbit latch in the port SFR contains a 1. Oth- P1.7/CEX4 PCA Module 4 Capture Input,
erwise the port pin is stuck at O. Compare/PWM Output

P2.O/A8- High Byte of Address for External

4.1 1/0 Configurations P2.7/A15 hiemory

Figure 2 shows a functional diagram of a typical bit P3.O/RXD Serial Port Input
latch and I/O butTerin each of the four ports. The bit
latch (one bit in the port’s SFR) is represented as a P3,1iTXD Serird port Output
Type D flipflop, which clocks in a value from the itt- P3.2/INTO External InterruptO
ternal bus in response to a “write to latch” signal from P3.3/INT ExternaI Interrupt 1
the CPU. The Q output of the flip-flop is placed on the
internal bus in response to a “read latch” signal from P3.4/To Timer OExternal Clock Input
the CPU. The level of the port pin itself is placed on the P3.5fll Timer 1 External Clock Input
internal bus in response to a “readpin” signal from the P3.6~ Write Strobe for External Memory
CPU. Some instructions that read a pert activate the
“read latch” signal, and others activate the “read pin” P3.7m Read Strobe for External Memory
signal. See the Read-Modify-WriteFeature section.

As shown in Figure 2, the output driversof Ports Oand

2 are switchable to an internal ADDRESS and AD-
DRESYDATA bus by an internal CONTROL signal
for use in external memory aecmaes. During external
memory accesses, the P2 SFR remains unchanged, but
the POSFR gets 1s written to it.

5-7
 8XC51FXHARDWAREDESCRIPTION

A. PortO Bit B. Port 1 or Porl 3 Bit

ADDRIOATA ALTERNATE
Vcc OUTPUT

h’
READ CONTROL
FUNCTION
LATCH
i READ
LATCH
INT.BUS
NRITE
i El INT.BUS
ro ‘.%: -C T
.ATCH
CL
Y + wRITE Iu
* TO
wl— LATCH-+ ~—

REAO
270653-2 PIN
ALTERNATE
INPUT
FUNCTION
270W3-4

C. Port 2 Bit
ADDR
----
“tALl
kONTRoL ‘?c ---
LATCH

INT,MN
WRITE LATCH
TO 1 - CL E
LATCH

READ ~
PIN
270653-3
●SeeFiwre4 for details of the internal pullup
—. ——
.—..— . .. . . . . .- - ..
Figure 2. C51FX Port Bit Latcnes ana vw 6urrera

Also shown in Figure 2 is that if a PI or P3 latch When configured as inputs they pull high and will
contains a 1. then the outrmt level is controlled by the source current (IIL in the data sheets) when externally
signal label~ “alternate output function.” The a-~usl pulled low. Port O, on the other hand, is considered
pin level is always available to the pin’s akernate input “true” bidirectional, because it floats when configured
functiom if any. as an input.

Ports 1, 2, and 3 have internal pullups. Port Ohas open Ml the port latches have 1s written to them by the reset
drain outputs. Each 1/0 line can be independently used function. If a Ois subsequently written toa port latch, it
as an input or an output (Ports Oand 2 may not be used can be recotrtljuredas an input by writing a 1 to it.
= general P- 1/0 when being used as the ~-
DRESWDATA BUS). To be used as an input, the port
bit latch must contsin a 1, which turns off the output 4.2 Writing to a Port
driver FET. On Ports 1,2, and 3, the pin is pulled high
by the internal pullup, but can be putled low by an In the execution of an instruction that changes the
external source. value in a port latch, the new value arrivesat the latch
during State 6 Phase2 of thefinal cycleof theinstrtrc-
Port Odiffers from the other ports in not having inter- tion. However, port latches are in fact sampled by their
nal pullups. The ptdlup PET in the PO output driver output btiers only during Phase 1 of any clock period.
(see Figure 2) is used only when the Port is emitting 1s (During Phase 2 the output butlsr holds the value it
during external memory accesses.otherwise the pullup saw during the previous Phase 1). Consequently, the
PET is off. Cawqucrttly POlines that are being used as new value in the port latch won’t actually appearat the
output port lines are open drain. Writing a 1 to the bit output pin until the next Phase 1, which will be at SIP1
latch leaves both output FETs off, which floats the pin of the next machine cycle. Refer to Figure 3. For more
and allows it to be used as a high-impedance input. information on internal timings refer to the CPU Tim-
Because Ports 1 through 3 have fixed internal pullups ing section.
they are sometimes call “quasi-bidirectional” ports.

5-8
intd. 8XC51FXHARDWAREDESCRIPTION

SIAIS 4 STATS5 STATS6 STATS1 6TATS2 STATS3 STATS4 STATS5

lmlnlmlmlmlmImlmlPllmlmlmlHlmlmd
XTALI:

-–’mp:” “’”’’””MI
NOVPONT, SRC: OLOOATA
I NSWOATA

270S53-33
I
Figure 3. Port Operation

If the change requireaa O-to-1transition in Porta 1, 2, pFET 1 in is the transistor that is turned on for 2 oscil-
and 3, an additional pullup is turned on duxing SIP1 lator periods after a o-t~l transition in the port latch.
and S1P2 of the cycle in which the transition occurs. A 1 at the port pin turns on pFET3 (a weak pull-up),
This is done to increase the transition speed. The extra through the invertor. This invertor and pFET form a
pullup can source about 100 times the currentthat the latch which hold the 1.
normal pullup can. The internal pollups are field-effect
transistors, not linear resistors. ‘l%epull-up arrange- If the pin is emitting a 1, a negative glitch on the pin
ments are shown in Figure 4. from some external source can turn off pFET3, causing
the pin to go into a float state. EFET2 k a very weak
The pullup consists of three pFETs. Note that an pullup whi;h is on whenever th; nFET is off, ~ tradi-
n-channel FET (r@ET)is turned on when a logical 1 is tional CMOS style. It’s onIy about Y,Othe strength of
applied to its gate, and is turned off when a logical Ois pFET3. Its futtction is to restore a 1 to the pin in the
applied to its gate. A p-channel FET (pFET) is the event the pio had a 1 and lost it to a glitch.
opposite:it is on when its gate sees a O,and off when its
gate sees a 1.

Vcc ‘JCc Vcc

TTT
PI

()

n
6 D
FROM PORT
LATCH
I
INPUT ~ J
DATA

“A”
PORT PIN
DJ
270S53-5
2HMOS Configuration. pFET1iaturnedonfor2 OSC. perioda after~ makea a O-to-1 transition.
Duringthistime,pFEr1
alsoturnsonPFET3 throughtheinverterto forma latchwhichholdathe1.PFET2 is alsoon.Port2 issimilarexcept
thatit holdathe strongDUIIUIIon while emitting1s that are addreaa bits. (See text, “Acceaaing External
Memory”.)
— .- . .— .. — .. ..
Figure 4. Ports 1 artct3 Internal Pullup configurations

5-9
i@L 8XC51FX HARDWARE DESCRIPTION

4.3 Port Loading and Interfacing DJNZ (decrement and jump if not zero, e.g.,
DJNZ P3, LABEL)
The output bfiers of Ports 1, 2, and 3 can each sink MOV, PX.Y, C (move carry bit to bit Y of Port X)
1.6 MA at 0.45 V. These port pil13can be dliVeIl by
CLR PX.Y (clear bit Y of Port X)
open-collector and open-drain outputs although o-to-l
transitions will not be fast since there is little current SETB PX.Y (set
bit Y of Port X)
pulling the pin up. An input Oturns off pullup pFET3,
leaving only the very weak pullup pFET2 to drive the It is not obvious that the last three instructions in this
transition. list are read-modify-write instructions, but they are.
They read the port byte, all 8 bits, modify the addressed
In external bus mode, Port O output buffers can each bit, then write the new byte back to the latch.
sink 3.2 MA at 0.45 V. However, as port pins they
require externalpullups to be able to drive any inputs. The reason that read-modify-writeinstructions are di-
rected to the latch rather than the pin is to avoid a
Sec the latest revision of the data sheet for design-in possible misinterpretation of the voltage level at the
information. pin. For example, a port bit might be used to drive the
base of a transiator.When a 1 is written to the bit, the
transistoris turned on. If the CPU then reads the same
4.4 Read-Modify-Write Feature port bit at the pin ratherthan the latch, it will read the
Some instructions that read a port read the latch and base voltage of the transistor and interpret it as a O.
others read the pin. Which ones do which? The instruc- Reading the latch rather than the pin will return the
tions that readthe latch ratherthan the pin are the ones correct value of 1.
that read a VAIU% possibly change it, and then rewriteit
to the latch. These are called “read-modify-write”in-
structions. Listed below are the read-modify-write in-
4.5 Accessing External Memory
structions. When the destination operand is a port, or a Accesses to external memory are of two types: accesses
port bit, these instructions read the latch rather than to externrdProgram Memory and acccases to external
the pin: Data Merno~Accesses to external Program Memory
ANL (logical AND, e.g., ANL Pl, A) use signal PSEN (program store enable) as the read
strobe. Accesam to external Data Memory use ~ or
ORL (logical OR, e.g., ORL P2, A) ~ (alternatefunctions of P3.7 and P3.6) to strobethe
XRL (logical EX-OR, e.g., XRL P3, A) memory. Refer to Figures 5 through 7.
JBc (jump if bit = 1 and clear bit, e.g.,
JBC P1.1, LABEL) Fetches from external Program Memory always use a
lfibit address. Accesses to external Data Memory can
CPL (complement bit, e.g., CPL P3.0) use either a 16-bit address (MOVX @ DPTR) or an
INC (increment, e.g., INC P2) 8-bit address (MOVX @ Ri);
DEC (decrernen~ e.g., DEC P2)

=A~ 1 =A’= 2 STATE3 STATS4 STATES ~ATS 6 STATS1 STATS2

IPtlnlP!lmlmlnl Ptlmlmlml Pl,nlPllmlFllnl
ATAL1:

ALE, ~

~: OATA OATA
--l +~ +SAMPLSO

PO: z ,

P2: PCHOU7 . Pcnolrr Pmour

270S53-30
Figure 5. External Program Memory Fetches
5-1o
int& 8XC51FX HARDWARE DESCRIPTION

STATS4 STATS5 STATS6 STATE1 STATS2 S7ATSS STATS4 STATS5

IPllnlmlnlPllml PllmlPllnlPllml fJtlP21Pllml
XTALI:

“: ~

n: FCLOUTIF
1 mooRAMMsMORv
OATASAW2.SO IS SXTSRNAL

FLOAT
Fo: 1
1

PmIon FC160R
P2: OPHORP2SFROUT
P2SFR P2SFR
27C&53-31

Figure 6. External Data Memory Read Cycle

STA?E4 STATS6 STATS6 S7AlS 1 STATS2 STATS3 STATS4 STATS5

IPIIP21 P*lF21PdP21PdF2 Ldnl PllP2LllF21FllP21
XTAL1:

‘“’ ~

fi: FOLOUTIF
I F610GRAUMSMORV
ls~

m:
Id
DPLORRI
OATAOUT
PcL

P2 PcHoa PcHor4
OP140RF2SFROUT
P2SFR F2SF14
270653-32

Figure 7. External Date Memory Write Cycle

5-11
 8XC51FX HARDWARE DESCRIPTION

Whenever a 16-bit address is used, the high byte of the 5.0 TIMERS/COUNTERS
address comes out on Port 2, where it is held for the
duration of the read or write cycle. The Port 2 drivers TheC51FXhasthreeid-bit Timer/Counters:
TimerO,
use the strong pullups during the entire time that they Timer 1, and Tinter 2. Each consists of two 8-bit regis-
are emitting address bits that are 1s. This occurs when ters, THx and TLL (X = O, 1, and 2). All three can be
the MOVX @ DPTR instruction is executed. During configuredto operateeither as timers or event counters.
this time the Port 2 latch (the Special Function Regis-
ter) does not have to contain 1s, and the contents of the In the Timer function, the TLx registeris incremented
Port 2 SFR are not moditied. If the external memory every machine cycle. Thus one can think of it as count-
cycle is not immediately followed by another external ing machine cycles. Since a machine cycle consists of 12
memory cycle the undisturbed contents of the Port 2 oscillator periods, the count rate is 1/12 of the oscilla-
SFR will reappearin the next cycle. tor frequency.

If an 8-bit address is being used (MOVX @ Ri), the In the Counter function, the register is incremented in
contents of the Port 2 SFR remain at the Port 2 pins response to a l-to-O transition at its corresponding ex-
throughout the external memory cycle. In this casG ternal input pin-TO, Tl, or T2. In this function, the
Port 2 pins can be used to page the external data mem- external input is sampled during S5P2 of every machine
ory. cycle. When the samples show a high in one cycle and a
low in the next cycle the count is incremented. The
In either case, the low byte of the address is time-multip- new count value appearsin the registerduring S3P1 of
lexed with the data byte on Port O. The ADDRESS/ the cycle following the one in which the transition was
DATA signal drives both FETs in the Port O output detected. Since it takes 2 machine cycles (24 oscillator
buffers. Thus, in external bus mode the Port Opins are periods) to remgnixe a l-to-O transition, the maximum
not open-drain outputs and do not require external count rate is 1/2, of the oscillator frequency. There are
pullups. The ALE (Address Latch Enable) signrd no restrictions on the duty cycle of the exte.mal input
should b-eused to capture the address byte into an ex- signal, but to ensure that a given level is sampled at
ternal latch. The address byte is valid at the negative least once before it chang~ it should be held for at
transition of ALE. Then, in a write cycle, the data byte least one full machine cycle.
to be written appearson Port Ojust before ~ is acti-
vated, and mrnainsthere until after ~ is deactivated. In addition to the Timer or Counter sektion, Timer O
In a read cycl%the inmrningb-yte ia accepted at Port O and Timer 1 have four operating modes from which to
just before the read strobe (RD) is deactivated. select: Modes O -3. Timer 2 has three modes of opera-
tion: Capture, Auto-Reload, and Baud Rate Generator.
During Sny access to external memory, the CPU writes
OFFH to the Port Olatch (the Special Function Regis-
ter), thus obliterating the information in the Port O 5.1 Timer Oand Timer 1
SFR. Also, a MOV POinstruction must not take place
during external memory accesses. If the user writes to The Timer or Counter fimction is selected by control
Port Oduring an external memory fetch the incoming bits Cfi in the Special Function Register TMOD (Ta-
code byte is corrupted. Therefore, do not write to Port ble 5). These two Timer/Counters have four operating
O if external programmemory is used. mod= which are selected by bit-pairs (Ml, MO) in
TMOD. Modes O, 1, and 2 are the same for both Tim-
External Program Memory is accessed under two con- er/Counters. Mode 3 operation is different for the two
ditions: timers.
1. Whenever signal ~ is active, or
2. Whenever the programcounter (PC) contains an ad- MODE 0
dress greater than IFFFH (8K) for the 8XC51FA or
3FFFH (16K) for the 8XC51FB, or 7FFFH (32K) Either Timer Oor Timer 1 in Mode O is an 8-bit Cmm.
ter with a divide-by-32 prescaler. Figure 8 shows the
forthe87C51FC.
Mcde O operation for either timer.
This requiresthat the ROMless veraionshave ~ wired
to Vss enable the lower 8K, 16K, or 32K program In this mode, the Timer register is contlgured as a
bytes to be fetched from external memory. 13-bit register.As the count rolls over from all 1s to all
0s, it sets the Timer interrupt flag TFx. The counted
When the CPU is executing out of external Program input is enabled to the Timer when TRx = 1 and either
Memory, all 8 bits of Port 2 are dedicated to an output GATE = Oor ~ = 1. (Setting GATE = 1 allows
function and may not be used for general purpose I/O. the Timer to be controlled by external input INTx, to
During external program fetches they output the high facilitate pulse width measurements).TW and TFx are
byte of the PC with the Port 2 drivers using the strong
puUups to emit bits that are 1s.
5-12
i~. 8XC51FXHARDWAREDESCRIPTION

control bits in SFR TCON (Table 6). The GATE bit is MODE 2
in TMOD. There are two different GATE bits, one for
Timer 1 (TMOD.7) and one for Timer O(TMOD.3). Mcde 2 mnfigures the Timer registeras an 8-bit Coun-
ter (TLx) with automatic reload, as shown in Figure 10.
The 13-bit registermnsists of all 8 bits of THx and the Overtlowfrom TLx not only sets TFx, but also reloads
lower 5 bits of TLx. The unmx 3 bits of TLx are inde- TLx with the ecmtentsof THx. which is oreaet bv soft-
terminateand should be i~ored. Setting the run flag ware. The reload leaves THx tichanged~ -
(TRx) does not clear these registers.

MODE 1

Mode 1 is the same as Mode O,except that the Timer

registeruses all 16 bita. Refer to Figure 9. In this mode,
THx and TLx are cascaded; there is no presc.aler.

Table 5. TMOD: Timer/Counter Mode Control Regiater

TMOD Address = 89H Reset Value = 0000 OOOOB

Not BitAddressable
TIMER 1 TIMER O
GATE C/~ I Ml MO GATE c/T Ml I MO
Bit 7 6 5 4 3 2 1 0

Symbol Function
GATE Gatingcontrolwhenset.Timer/CounterOor 1 is enabledonlywhile~ or~ pin
is highandTROor TR1controlpinis set.Whencleared,TimerOor 1 is enabled
wheneverTROor TR1controlbit is set.
cm Timeror CounterSelector.Clearfor Timeroperation(inputfrominternalsystem
clock).Setfor Counteroperation(inputfromTOorTl inputpin).

Ml MO Operating Mode
00 8-bitTimer/Counter.THx withTLx as 5-bitpresceler.
01 16-bitTimer/Counter.THx and TLx are cascaded;there is no prescaler.
10 8-bitauto-reloadTimer/Counter. THx holdsa valuewhichis to be reloadedintoTLx
each time it overflows.
11 (TimerO)TLOis an 8-bit Timer/Countercontrolledby the standardTimer Ocontrol
bits.THOis an8-bittimeronlycontrolledbyTimer1 controlbits.
1 1 Timer 1)~mer/Counterstopped.

,“.-__J CONTROL OVERFLOW

I

x= O or1
270653-6

Figure 8. Timer/Counter Oor 1 in Mode O:13-Bit Counter

5-13
intel. 8XC51FXHARDWAREDESCRIPTION

Table 6. TCON: Timer/Counter Control Register

I
TCON Address = 88H Reset Value = 0000 OOOOB

BitAddressable
TR1 TRO IE1 IT1 ITO
I TF1 TFO IEO
Bit 7 6 5 4 3 2 1 0

Symbol Function
TF1 Timer1overflowFlag.Set by hardwareonTimer/Counteroverflow.Clearedby
hardwerewhenproceseorvectorsto interruptroutine.
TR1 Timer1 Runcontrolbit. Set/clearedbysoftwareto turnTimer/Counter1 on/off.
TFO TimerOoverflowFlag.Set by hardwareonTimer/CounterOoverflow.Clearedby
hardwarewhenprocessorvectorsto interruptroutine.
TRO TimerORuncontrolbit.Set/clearedbysoftwareto turnTimer/CounterOon/off.
IE1 Interrupt1flag.Setbyhardwarewhenexternalinterrupt1 edgeis detected
(transmittedor level-activated).Clearedwheninterruptprocessedonlyif transition-
activated.
IT1 Interrupt1Typecontrolbit. Set/clearedbysoftwareto specifyfallingedge/lowlevel
triggeredexternalinterrupt1.
IEO InterruptOflag.SetbyhardwarewhenexternalinterruptOedgeis detected
(transmittedor level-activated).
Clearedwheninterruptprocessedonlyif transition-
activated.
ITO InterruptOTypecontrolbit.Set/clearedbysoftwareto specifyfallingedge/lowlevel
triggeredexternalinterruptO.

x= Oor 1

270S53-S4
Figure 9. Timer/counter Oor 1 in Mode 1: 16-Bit Counter

MODE3 a timerfunction(counting
machine
cycles)andtakes
of TRl and TFl from Timer 1. Thus THO
over the use
Timer 1 in Mode 3 simply holds its count. The effect is now controls the Timer 1 interrupt.
the same as setting TR1 = O.
Mode 3 is provided for applications requiringan extra
Timer O in Mode 3 establishes TLO and THO as two 8-bit timer or counter. When Timer O is in Mode 3,
separatecounters. Tlse logic for Mode 3 on Timer Ois Timer 1 can be turned on and off by switching it out of
she–m in Figure 11. TLOusea the Timer Ocontrol bits: and into its own Mode 3, or can still be used by the
C/T, GATE, TRO,INTO, and TFO.THOis locked into serial port as a baud rate generator,or in any applica-
tion not requiring an interrupt.

5-14
intele 8XC51FXHARDWAREDESCRIPTION

Osc — -12

IJ INTERRUPT

,X.N2CE” ‘ ‘COJTROL ‘“=” “V’’’’owi ‘x h

RELOAD
TRx

GATE
(elk)
I
~ PIN
x= owl
27065S-7

Figure 10. Timer/Counter 1 Mode 2 8-Bit Auto-Reload

E1-El--’’12f0sc
lllzfo’~

* TLo - INTERRUPT
~b
(8Bib)
.p,.~cf~’l I ~
CONTFIOL OVERFLOW

TRO

GATE

~ PIN

1/12 f“= l~i INTERRUPT

:
*
CONTFIOL OVERFLOW
TR1
270S5S-8
Figure 11. ~mer/Counter 0 Mode 3: Two S-BitCountere

5.2 Timer 2 Tablei Timer 2 Operating Modes

Timer 2 is a 16-bit Timer/Counter which can operate
RCLK+ TCLK cP/m T2”OE TR2 Mode
either as a timer or as an event counter. This is selected o o 0 1 I&Bit
by bit Cm in the Speoial Function Register T2CON Auto-Reload
cable 8). It has three operating modes: capture, auto- 0 1 o 1 16-Bit
relosd (up or down counting), and b+mdrate generator.
Capture
The modes are selected by bits in T2CON as shown in
Table 7.
1 x x 1 Baud-Rate
Generator
x o 1 1 Clock-Out
‘on PI.0
x x x 0 TimerOff
in~e 8XC51FX HARDWARE DESCRIPTION

Table 8. T2CON: Timer/Counter 2 Control Register

T2CON Address= OC8H ResetValue= 0000OOOOB

Bit Addressable
I TF2 EXF2 RCLK TCLK EXEN2 TR2 cl= cPlm
Bit 7 6 5 4 3 2 1 0

Svmbol Function
TF2 Timer2 overflow flagsetbya Timer2 overflowandmustbeclearedbysoftware.TF2will
notbesetwheneitherRCLK= 1 or TCLK= 1.
EXF2 Timer2 externalflagsetwheneithera captureor reloadiscausedbya negativetransition
onT2EXandEXEN2= 1.WhenTimer2 interruptis enabledEXF2= 1 will causethe CPU
to vectorto the Timer2 interrupt routine. EXF2mustbe clearedbysoftware.EXF2doesnot
causeaninterruptin up/downcountermode(DCEN= 1).
RCLK Receiveclockflag.Whenset,causesthe serialportto useTimer2 overflowpulsesfor its
receiveclockin serialport Modes1and3. RCLK= OcausesTimer1 overflowto beused
for the receiveclock.
TCLK Transmitclockflag.Whenset,causesthe serialportto useTimer2 overflowpulsesfor its
transmitclockin serialportModes1 and3. TCLK= OcausesTimer1overflowsto beused
for thetransmitclock.
EXEN2 Timer2 externalenableflag.Whenset,allowsa captureor reloadto occurasa resultof a
negativetransitionon T2EXif Timer2 is not beingusedto clocktheserialport.EXEN2= O
causesThmer2 to ignoreeventsat T2EX.
TR2 Start/stopcontrolfor Timer2. A logic1 startsthe timer.
c/E Timeror counterselect.(Timer2)
O= Internaltimer(OSC/12or OSC/2in baudrategeneratormode).
1 = Externaleventcounter(fallingedgetriggered).
cP/m Csoture/Reloadflaa.Whenset.cattureswill occuron neaativetransitionsat T2EXif
EXEN2 = 1.When;leared,aut&eloadswill occureitherfiith Timer2 overflowsor
negativetransitionsat T2EXwhenEXEN2= 1.WheneitherRCLK= 1 or TCLK= 1,this
bitis ignoredand thetimerisforcedto auto-reloadon Timer2 overflow.

CAPTURE MODE 16-bit timer or counter which upon overflow sets bit
TF2 in T2CON. This bit can then be used to generate
In the cmtrsremode there are two oDtionsselected bv SD internmt. If EXEN2 = 1, Timer 2 still does the
bit EXEN2 in T2CON. If EXEN2 ~ O, Timer 2 is ~ above, bu; with the added f~ture that a l-to-O tran-

CAPTURE llMER 2
IN7ERRUPT
TRANSITION

T22X PN 2xF2
+! !~
CONTROL

DZN2
270653-9

Figure 12. llmer 2 in Capture Mode

5-16
 8XC51FXHARDWAREDESCRIPTION

sition at extermdinput T2EX causeathe current value defauh to count up. When DCEN is set, Timer 2 ean
in the Timer 2 registers,TH2 and TL2, to be captured count up or down depending on the value of the T2EX
into registersRCAP2H and RCAP2~ respectively. In pin.
addition, the transition at T2EX eausea bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, ean generate Figure 13 showsTimer 2 automatically counting up
an interrupt. The capture mode is illustrated in Figure when DCEN = O. In this mode there are two options
12. seleeted by bit EXEN2 in T2CON. If EXEN2 = O,
Timer 2 counts up to OFFFFH and then sets the TF2
bit upon overflow. The overflow also causes the timer
AUTO-RELOAD MODE registers to be reloaded with the 16-bit value in
(UP OR DOWN COUNTER) RCAP2H and RCAP2L. The values in RCAP2H and
Timer 2 can be progrsmmed to emmtup or down when RCAP2L are preset by software.If EXEN2 = 1, a 16-
bit reload can be triggeredeitherby an overtlow or by a
eonfigured in its 16-bit auto-reload mode. This feature
is invoked by a bit named DCEN (Down CmrnterEn- l-to-o transition at external input T2EX. This tran-
sition also sets the EXF2 bit. Either the TF2 or EXF2
able) located in the SFR T2MOD (see Table 9). Upon
reset the DCEN bit is set to O w that Timer 2 will bit can generate the Timer 2 interruptif it is enabled.

Table 9. T2MOD: Timer 2 ModeControl Register

I

II T2MOD Address = OC9H

Not Bit Addressable

Reset Value= XXXXXXOOB

I— — — — — — T20E DCEN
Bit 7 6 5 4 3 2 1 0

Symbol Function
— Not implemented,reservedfor futureuse.*
T20E Timer2OutputEnablebit.
DCEN DownCountEnablebit.Whenset,thisallowsTimer2 to beconfiguredasanup/down
counter.
‘User software should not write 1s to reserved bits.These bitemaybe used in future8051 familyproductsto invoke
new featurea.In that case, the reset or inaetivsvalue of the new bit will be O,and its activevaluewillbe 1. The value
read from a reservedbit is indeterminate.

OVSSFLOW

TR2
RELOAD

7SANSITION
OETEC7YJN

A. nws 2
1 IN7ESRUPT
T2EXPIN EXF2
~x~~
CONTROL

EXiN2
2706S-10

Figure 13. Timer 2 Auto Rslosd Mode (DCEN = O)

5-17
in~. 8XC51FXHARDWAREDESCRIPTION

Betting the DCEN bit enables Timer 2 to count up or The Clock-out frequency depends on the oscillator fre-
down as shown in Figure 14. In this mode the T2EX quency and the reload value of Timer 2 capture regis-
pin controls the direction of count. A logic 1 at T2EX ters (RCAP2H, RCAP2L) es shown in this equation:
makes Timer 2 count up. The timer will overtlow at
OFFFFH and set the TF2 bit which can then generate Clock-outFrequency =
an interruptifit is enabled. This overflow also causes a
the 16-bit vrdue in RCAP2H end RCAP2L to be re- OscillatorFrequency
loaded into the timer registers, TH2 and TL2, respec- 4 X (65536 - RCAP2H,RCAP2L)
tively.
In the Clock-Out mode Timer 2 redl-overswill not gen-
A logic O at T2EX makes Timer 2 count down. Now erate err interrupt. This is similar to when Timer 2 is
the timer undertows when TH2 and TL2 equal the used as a baud-rate generator.It is possible to use Tim-
values stored in RCAP2H and RCAP2L. The under- er 2 as a baud-rate generator and a clock generator
flow sets the TF2 bit and causesOFFFFH to be reload- simultaneously. Note, however, that the baud-rate end
ed into the timer registers. Clock-out frequencies cannot be determined indepen-
dently of one snother since they both use the values in
The EXF2 bit toggles whenever Timer 2 overflows or RCAP2H and RCAP2L.
underflows. This bit can be used es a 17th bit of resolu-
tion if desired. In this operatingmodq EXF2 does not
generate en interrupt. 6.0 PROGRAMMABLE COUNTER
ARRAY
BAUD RATE GENERATOR MODE The Pw=-ble count~ AITSYfJ’W e-ists of a
16-bit timer/camter end five 16-bit compare/cepture
The baud rate generatormode is selected by setting the
modules es shown in Figure 15a.The PCA timer/cmur-
RCLK end/or TCLK bits in T2CON. Timer 2 in this
ter serves as a common time base for the five modulea
mode will be described in conjunction with the serial
end is the only timer which can service the PCA. Its
port.
clock input cartbe prograrnmed to count any one of the
following signals:
PROGRAMMABLE CLOCK OUT ● oscillator frequency + 12
A 50% duty cycle clock can be programmed to come ● oscillator frequency + 4
out on P1.O.This pin, besides being a regular 1/0 pin, ● Timer O OVdOW
has two alternate functions. It can be programmed (1) ● external input on ECI (P1.2).
to input the external clock for Timer/Counter 2 or (2)
to output a so~o duty cycle clock ranging from 61 Hz Each compere/cspture mcdule can be programmed in
to 4 MHz at a 16 MHz operatingfrequency. any one of the following modes:
To configure the Timer/Counter 2 as a clock generator, . rising rind/or falling edge capture
bit Cf12 (in T2CON) must be cleared end bit T20E in ● softwere timer
T2MOD must be set. Bit TR2 (T2CON.2) also must be ● high speed output
set to start the timer (see Table 6 for operating modes).
. pulse width modulator.

Module 4 can also be programmedas a watchdog tim-

er.

When the compere/cspture modules are programmed

in the capture mod%softwaretimer, or high speed out-
put mode, an interrupt can be generated when the med-
uleexecutes
itsfunction.
Allfivemodules
plusthePCA
timer overtlow share one interrupt vector (more about
this in the PCA Interrupt section).

5-18
 8XC51FXHARDWAREDESCRIPTION

(DOWNCOUNTINGRELOADVALUE)

FFH ; FFH
I TOOOLE

TR2
A, COUNT
DIRECTION
1 = UP
O = DOWN

(UP COUNnNGRELOADVALUE)
n
T2EX PIN
270653-11

Figure 14. Timer 2Auto Reload Mode (DCEN = 1)

Osc +2
1~1 I ●
TL2
(8-Blt8)
: TH2
;(8-BNs)
I I

I 1“
TR2

A
) cm Bit

PI .0
(12)
&
w I +2
I

T20E (T2uoD.1)
7T=~

P1.1 I Timer2
(125X) 1 Interrupt
1
1 %

EXEN2
270653-35

Figure 15. Timer 2 in Clock-Out Mode

5-19
in~. 8XC51FXHARDWAREDESCRIPTION

- 16 BITS EACH +

P1 .3/CEXO

P1.4/cExl

— 16 BIT6 —

PI .5/cEx2

P1.6/CEX3

PI .7/cEx4
270653-12

Figure 15a. Programmable Counter Array

The PCA timer/counter and compare/captore modules gram of this timer. The clock input can bc selected
share Port 1 pins for external I/O. These pins are listed from the following four modes:
below. If the port pin is not used for the PCA, it cars ● Oscillator frequency + 12
still be used for standard I/O. The CL register is incremented at S5P2 of every
machine cycle. With a 16 MHz crystal, the timer
PCA Component External 1/0 Pin increments every 750 mmosecorids.
16-bit Counter P1.2I ECI
● Oscillator frequency + 4
16-bitModuleO P1.3/ CEXO The CL register is incremented at S1P2, S3P2 and
16-bitModule1 PI.41 CEX1 S5P2 of every machine cycle. With a 16 MHz crys-
16-bitModule2 P1.5/ CEX2 tal, the timer increments every 250 nanoseconds.
16-bitModule3 P1.6/ CEX3 ● Timer Oovertlows
16-bitModule4 P1.7I CEX4 The CL register is incremented at S5P2 of the ma-
chine cycle when Timer O overfiows.This mode al-
lows a programmableinput frequencyto the PCA.
6.1 PCA 16-Bit Timer/Counter . External input
The PCA has a free-running 16-bit timer/counter con- The CL re~ster is incremented at the first one of
sisting of registersCH and CL (the high and low bytea S1P2, S3P2 and S5P2 after a l-to-O transi-
of the count value). These two registerscan be read or tion is detected on the ECI pin (P1.2). P1.2 is aam-
written to at any time. Figure 16 shows a block dia- pled at S1P2, S3P2 and S5P2 of every machine cy-
cle. The maximum input frequency in this mode is
oscillator frequency ~ 8.

CPS1 cPsO TO PCA MoOULES O-4

——

FOsc/12
00
FOSC/4 / 01
1<
TIMER O . INTERRuPT
,
OVERFLOW 1 1
EXTERNAL P -
tNPUT
CONTROL lb ENASLE
L I
I I
n
(Eel)

CR

XJ ECF

270663-13

Figure16.PCA Timer/Counter
5-20
i~. 8XC51FXHARDWAREDESCRIPTION

CH is incremented after two oscillator periods when The CCON register, shown in Table 11, contains two
CL OVdOWS. more bits which are associated with the PCA timer/
counter. The CF bit gets set by hardwme when the
The mode register CMOD contains the Count Puke counter overtlows, and the CR bit is set or cleared to
8elect bits (C%l and CPSO)to specify the clock input. turn the counter on or off. The other five bits in this
CMOD is shown in Table 10. This register also eon- register are the event figs for the compare/capture
tains the ECF bit which enables the PCA counter over- moduks and will be diseuaaedin the next section.
flow to generate the PCA interrupt. In addition, the
user has the option of turning off the PCA timer during
Idle Mode by setting the Counter Idle bit (CIDL). The
Watchdog Timer Enable bit (WDTE) will be diaoussed
in a later section.

Table 10. CMOD: PCA Counter Mode Register

CMOD Address= OD9H ResetValue= OOXX

XOOOB

Not Bit Addressable

CIDL WDTE — — — CPS1 CPSO ECF
Bit 7 6 5 4 3 2 1 0

SYmbol Function
CIDL CounterIdlecontrol:CIDL= Oprogramsthe PCACountertocontinuefunctioningduring
idleMode.CIDL= 1programsit to begatedoff duringidle.
WDTE WatchdogTimerEnable:WDTE= OdiaeblesWatchdogTimerfunctionon PCAModule4.
WDTE= 1 enablesit.
— Notimplemented,resewedfor futureuse.*
CPS1 PCACountPuleeSelectbit 1.
CPSO PCACountPulseSelectbitO.
CPS1 CPSO Selected PCA Input**
o 0 Internalclock,Fosc+ 12
0 1 Internalclock,FOSC+4
1 0 Timer Ooverflow
1 1 Externalclockat ECVP1.2pin(max.rate = Fosc+8)
ECF PCAEnableCounterOverflowinterrupt ECF= 1 enablesCFbit in CCONto generatean
interrupt.ECF= Odisablesthatfunctionof CF.
NOTE
*Uaersoftware
shouldnotwritsIs to raaerved
bik. ThSSS
bitsmaybeusedin futureS051 familyproduetato invoke
new featurea. In that ease, the reset or inaetkfe value of the new bit will be O, and ifs active value will be 1. The value
read from a reaerved bit is indeterminate.
●*FOSC = oscillator frequeney

5-21
i~. 8XC51FXHARDWAREDESCRIPTION

Table 11. CCON: PCA Counter Control Register

CCON Address= OD8H ResetValue= OOXO

OOOOB

Bit Addressable
I CF CR — CCF4 CCF3 CCF2 CCF1 CCFO
Bit 7 6 5 4 3 2 1 0

Symbol Function
CF PCACounterOverflowflag.Setbyhardwarewhenthe counterrollsover.CFflagsan
interruptif bit ECFin CMODis set.CFmaybeset byeitherhardwareor softwarebutcan
onlybeclearedbysoftware.
CR PCACounterRuncontrol bit. Set by software to turn the PCAcounteron. Mustbecleared
bysoftwareto turnthe PCAcounteroff.
— Notimplemented,reservedfor futureuse”.
CCF4 PCAModule4 interruptflag.Setbyhardwarewhena matchor captureoccurs.Mustbe
clearedbysoftware.
CCF3 PCAModule3 interruptflag.Setbyhardwarewhena matchor captureoccurs.Mustbe
clearedbysoftware.
CCF2 PCAModule2 interruptflag.Setbyhardwarewhena matchor captureoccurs.Mustbe
clearedbysoftware.
CCF1 PCAModule1 interruptflag.Setbyhardwarewhena matchor captureoccurs.Mustbe
clearedbyeoftware.
CCFO PCAModuleOinterruptflag.Setbyhardwarewhena matchor captureocours.Mustbe
clearedbysoftware.

Usersoftware shouldnotwriteIs to resend bits,Thesebitsmaybeusedinfuture8051familyproducts to invoke

new features. In that case, the reset or inaotive value of the new bit will be O, and its active value will be 1. The value
read from a reserved bit is indeterminate.

6.2 Capture/Compare Modules when a module’s event flag is set. The event flags
(CCFn) are located in the CCON register and get set
Each of the five compare/capture modules has six pos- when a capture event, software timer, or high speed
sible functions it can perform: outputevtit occurs for a given module. - -
— Id-bit Capture, positive-edge triggered
Table 13 shows the combinations of bits in the
— l~bit Capture, negative-edge triggered CCAPMn register that are valid and have a defined
— 16-bit Capture, both positive and negative-edge function. Invalid combinations will produce undefined
triggered results.
— 16-bit Software Timer
Each module also has a pair of 8-bit compsre/capture
— 16-bit High Speed Output registers (CCAPnH and CCAPnL) associated with it.
— 8-bit pulse Width Modulator. These registers store the time when a capture event oc-
curredorwhena compare
eventshouldoccur.Forthe
In addition, module 4 can be used as a Watchdog Time- PWM mode, the high byte regiser CCAPnH controls
r. Themodules
canbeprogrammed
in sny combina- the duty cycle of the wsveform.
tion of the different modes.
The next five sections describe each of the compare/
Each module has s mode register called CCAPMn capture modes in detail.
(n = O, 1, 2, 3, or 4) to select which fimction it will
perform. The CCAPMn register is shown in Table 12.
Note the ECCFn bit which enables the PCA interrupt

5-22
 8XC51FXHARDWAREDESCRIPTION

Table 12. CCAPMn: PCA Modules Compare/Capture Regiatere

CCAPMn Address CCAPMO ODAH Reset Value = XOOO00006

(n = O-4) CCAPMI ODBH
CCAPM2 ODCH
CCAPM3 ODDH
CCAPM4 ODEH
Not Bit Addressable
— ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit 7 6 5 4 3 2 1 0

Symbol Funotion
— Notimplemented,reservedfor futureuse*.
ECOMn Enablecomparator.ECOMn= 1enablesthe comparatorfun~”on.
CAPPn CapturePositive,CAPPn= 1 enablespositiveedgecapture.
CAPNn CaptureNegative,CAPNn= 1enablesnegativeedgecapture.
MATn Match.WhenMATn= 1,a matchofthe PCAcounterwiththismodule’scompare/cepture
registercausesthe CCFnbit inCCONto be set,flagginganinterrupt.
TOGn Toggle.WhenTOGn= 1,a matchofthe PCAcounterwiththismodule’scompare/capture
registercausesthe CEXnpinto toggle.
PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be usedasa pulsewidth
modulatedoutput.
ECCFn EnableCCFinterrupt.Enablescompare/captureflagCCFnintheCCONregisterto generate
aninterrupt.
NOTE:
*User softwareshoutdnot write Is to reservedbits.These bite may be used in future8051 familyproductsto invoke
new features.In that case, the reset or inscttie valueof the new bit will be O,and its acfNe value willbe 1. The value
read from a reservedbit is indeterminate.

Tabfe 13. PCA Module Modes (CCAPMn Regiater)

I - lECOMnlCAPPnlCAPNnlMATnl TOGnlPWMnlECCFnl ModuleFunction I
I x I o I o I o I o I O I o I o INoot)erstion I
x x 1 0 0 0 0 x 16-bit capture by a postive-edgetriggeron CEXn
x x o 1 0 0 0 x Ie-bitcapturebya negative-edge
triggeron CEXn
x x 1 1 0 0 0 x 16-bifcapturebyatrsnsition on CEXn
x 1 I o 0 1 I Ololx 16-bifSoftwareTimer
x 1 0 0 1 1 0 x 16-bit High Speed Output

x I[ 1 I1 o 1
0 1
0 1
0 1
1 t
0 !8-bit
I
PWM

x 1 0 0 1 x Olx Watchdog
Timer
X = Don’t Care

5-23
i~o 8XC51FXHARDWAREDESCRIPTION

6.3 16-Bit Capture Mode In the interrupt service routine, the lt%it capture value
must be saved in IL4M before the next capture event
Bothpositiveandnegative transitionseantriggera cap- ocours. A subsequent capture on the same CEXn pin
turewith thePCA. This gives the PCA the flexibility to will write over the first capture value in CCAPnH and
measure perio& pulse widths, duty cycles, and phase CCAPnL.
differences on up to five separate inputs. Setting the
CAPPn snd/or CAPNn in the CCAPMn mode register
select the input trigger-positive snd/or negative tran- 6.4 16-Bit Software Timer Mode
sition-for module n. Refer to Figure 17.
In the eotnpare modej the 16-bitvalue of the PCA tim-
The external input pins CEXOthrough CEX4 are sam- er is compared with a 16-bit value pm-loaded in the
pled for a transition. When a valid transition is detected module’s compare registers(CCAPnH, CCAPnL). The
(psitive rind/or negativeedge), hardware loads the comparison oeours three times per machine cycle in
16-bit vrdueof the PCA timer (CH, CL) into the mod- order to recognize the fastest possible clock input (i.e.
de’s capture registers (CCAPnH, CCAPnL). The re- ~. x oscillator frequency). Setting the ECOMn bit in
sulting value in the capture registers reflects the PCA the mode register CCAPMn enables the comparator
timer value at the time a transitionwas detected on the function as shown in Figure 18.
CEXn pin.
For the Software Timer mode, the MATn bit also needs
Upon a capture, the module’s event flag (CCFn) in to be set. When a match occurs between the PCA timer
CCON is set, and an interrupt is flagged if the ECCFn and the compare registen, a match signal is generated
bit in the mode regista CCAPMn is set. The PCA in- and the module’s event flag (CCFn) is set. An interrupt
terrupt will then be generatedifit is enabled. Since the is then flagged if the ECCFn bit is set. The PCA inter-
hardware does not clear an event tlag when the inter- rupt is generated ordy if it has been properly enabled.
rupt is vectored to, the tlag must be cleared in software. software must clear the event flag before the next inter-
rupt will be flagged.

——

+-’N”RRUM

CEXn
&
PIN
+-l
+KJ
1/1
1
I

I /1
I
I
z
CAPTURE
8

GGl
CH :
I
CL

8
PCA
llMER/COUNIER

I
I I I

I
x
I o

CCAPMnMOOEREGISTER
I I o o ECCFn
n = O, 1, 2, 3 or 4
x = OOtrt Care

270653-14

Figure 17. PCA 16-Bit Capture Mode

5-24
intel. 8XC51FXHARDWAREDESCRIPTION

During the interrupt routine, a new 16-bitcompare vaf- regularhold-off signals to the Watchdog. These circtits
ue canbe written to the compareregisters (CCAPnH are used in applications that are subject to electrical
and CCAPnL). Notice, however, that a wn”te to noisq power glitches, electrostatic diseharg% etc., or
CCAPnL clears the ECOMn bit which temparily dir- where high reliability is required.
ables the companstorjimction while these registens are
being updated so an invalid match does not occur. A The Watchdog Timer function is only available on
write to CCAPnH sets the ECOMn bit and re-enables PCA module 4. In this mode, every time the count in
the comparator. For this reason, user software should the PCA timer matchea the value stored in module 4’s
write to CCAPnL first, then CCAPnH. compare registers, an internal reset is generated. (See
Figure 19.) The bit that selects this mode is WDTE in
the CMOD register. Module 4 must be setup in either
6.5 High Speed Output Mode comparemode as a SoftwareTimer or High Speed Out-
put.
The High Speed Output (HSO) mcde toggles a CEXn
pin when a match occurs between the PCA timer and a When the PCA Watchdog Timer timeaout, it resets the
pm-loaded value in a module’s compare registers. For chip just like a hardware re@ except that it doea not
this mode, the TOGn bit needs to be set in addition to drive the reset pin high.
the ECOMn and MATn bits as seen in Figure 18. By
setting or clearing the pin in software, the user can To hold off the reset, the user has three options:
select whether the CEXn pin will change from a logical (1) periodically change the compare value so it will
O to a logicaf 1 or vice versa. The user rdso b the
never match the PCA timer,
option of flagging an interrupt when a match event oc-
curs by setting the ECCFn bit. (2) periodically change the PCA timer vafue so it will
never match the compare value,
The HSO mode is more accurate than toggling port (3) disable the Watchdog by clearing the WDTE bit
pins in software because the toggle occurs before before a match occurs and therrfater re-enable it.
branching to an interrupt. That iy interrupt latency
will not effect the accuracy of the output. If the user The first two options are more refiable because the
does not change the compare registers in an interrupt Watchdog Timer is never disabled as in option #3. The
routin~ the next toggle will occur when the PCA timer second option is not recommended if other PCA mod-
rolls over and matches the last compare value. ules are being used since this timer is the time base for
all five modules. Thus in most applications the first
solution is the best option.
6.6 Watchdoa Timer Mode
If a Watchdog Timer is not needed, modufe 4 can still
A Watchdog Timer is a circuit that automatically in- be used in other modes.
vokea a reset unless the system being watched sends

PT

PCA PIN
l’ws/cou

270S5S-15

Figure 18. PCA 18-Bit Comparator Mode: Software Timer and High Bpeed Output

5-25
 8XC51FXHARDWAREDESCRIPTION

6.7 Pulse Width Modulator Mode The PCA generates8-bit PWMS by comparing the low
byte of the PCA timer (CL) with the low byte of the
Any or all of the five PCA modules can be pro- module’s compareregisters(CCAPnL). Refer to Figure
p~ to be a PukeWidthModulator. The PWM 20. When CL < CCAPnL the output is low. When CL
output can be used to convert digital data to an analog > CCAPnL the output is high. The value in CCAPnL
signal by simple externalcircuitry. The frequencyof the controls the duty cycle of the waveform. To change the
PWM depends on the clock sources for the PCA timer. value in CCAPnL without output glitches, the user
With a 16 MHz crystal the maximum frequency of the must write to the high byte register (CCAPrsH). This
PWM waveform is 15.6 KHz. value is then shifted by hardware into CCAPnL when
CL rolls over from 01%-I to WIHwhich correspondsto
the next period of the output.

wDSS

PCA

I I* I
x KO144 o
I
o
I
1

CC4PM4 MODEREOISTER
I
x
I
o
I
x
I
RSsEl
WRm TO
CCAP4L
,,0 ,,

WRm m x = Don’t Cere

CCAP4H
,, 1,,
a
270653-16

Figure 19. Watchdog Timer Mode

&
CCAPnH

CL MADE
rrmoo
IRANSlllDN

“o,,
CL < CC4PnL
8-Slf
CL rnMpARA70R CL= ~PnL ~ CESnPIN
[ t
WBLE
,,1,,

n = O, 1, 2, 3 w 4
x = Don’tCere =
Cf2.APMnMOE REOUSXR
270653-17

Figure 20. PCA 6-Bit PWM Mode

I
5-26
in~. 8XC51FXHARDWAREDESCRIPTION

Dus-feYcLE CCAPnH OUTPUTWAVSFORM

100% 00

90%
25 ~

50%
128 ~

10Z
230 ~

0.4Z
25’ ~ ,706=-18

Figure 21. CCAPnH Variea Duty Cycle

CCAPnH oancontain any integer from Oto 255 to vary The serial port can operatein 4 modes:
the duty cycle from a 100% to 0.4% (see Figure 21).
Mode tk Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 bits are transrnitted/re-
7.0 SERIAL INTERFACE cekd: 8 data bits (LSB ilrst). The baud rate is fixed at
1/12 the oscillator frequency.
The serial port is full duplex, meaning it ean transmit
and receive simultaneously. It is also receive-buffered, Mode 1: 10 bits are transmitted (through TXD) or r~
meaning it ean eommenee reeeption of a second byte ceived (through RXD): a start bit (0), 8 &ts bita (LSB
before a previously reeeived byte has been read fkom tirst), and a stop bit (l). On reeeive, the stop bit goes
the receive register. (However, if the first byte still into RB8 in Special Function Register SCON. The
hasn’t beersread by the time reeeption of the seeond baud rate is variable.
byte is complete, one of the bytea will be lost). The
serial port receive and tranams “t registers are both ac- Mode 2: 11 bits are transmitted (through TXD) or re-
cessed through Speeial Function Register SBUF. Actu- cekd (through RXD): a start bit (0), 8 data bits (LSB
ally, SBUF is two separate registers, a transmit buffer first), a programmable 9th data bit, and a stop bit (l).
and a receivebuffer. Writing to SBUF loads the trans- Refer to Figure 22. On Transmit, the 9th data bit (TB8
mit register, and reading SBUF amxsses a physically in SCON) oan be assigrwdthe value of O or L Or, for
separate receive register. example+the paritybit (P in the PSW) could be moved
into TBS. 0ss receiv~ the 9th data bit goea into RB8 in
The serialport control and status registeris the Special SCON, while the stop bit is ignored. (The validity of
Function Register SCON, shown in Table 14. This reg- the stop bit ean be checked with Framing Error Detec-
ister contains the mode selection bits (SMOand SM1); tion.) The baud rate is r.romarnmableto either %. or
the SM2 bit for the multiprocessor modes (see Msdti-
procea.sorCommunications seetion); the Receive En-
able bit (REIN);the 9th data bit for transmit and receive
(1’B8 and RB8); and the serial port interrupt bits (’H
and RI).

Figure 22. Dsta Frame: Modes 1,2 and 3

5-27
intelo 8XC51FXHARDWAREDESCRIPTION

Mode 3: 11 bits are transmitted (through TXD) or re- byte has its 9th bit set to O. All the slave processors
ceived (~ough ~): a start bit (0), 8 data bits (L.SB should have their SM2 bits set to 1 so they will only be
tit), a progremmable9th data bit and a stop bit(l). In interruptedby an addreasbyte. In fact, the C51FX has
fa~ Mode 3 is the same as Mode 2 in all respects an Automatic Address Recognition feature which al-
except the baud rate. The baud rate in Mode 3 is vari- lows only the addreasedslave to be interrupted. That k+
able. the addreas comparison occurs in hardware, not aoft-
ware. (On the 8051 serial port, an address byte inter-
In elf four modes, trananm “ sion is initiated by any in- rupts all slavea for an address comparison.)
struction that uses SBUF es a destination register. Re-
ception is initiated in Mode Oby the condition RI = O The addressed slave’s software then clears its SM2 bit
and REN = 1. Reception is initiated in the other and preparesto receive the data bytes that wilf be com-
modes by the incoming start bit if REN = 1. For more ing. The other slaves are unaffected by these &ta byt~.
detailed information on each aerialport mod%refer to They are still waiting to be addressed since their SM2
the “Hardware Description of the 8051, 8052, and bits are all set.
80C51.”

7.3 Automatic Address Recognition

7.1 Framing Error Detection
Automatic Address Recognition reduces the CPU time
Framing ErrorDetection allows the serialport to check required to seMce the serial port. Since the CPU is
for valid stop bits in modes 1,2, or 3. A missing stop bit only interrupted when it receives its own address, the
can be caused, for example, by noise on the serial lines, software overhead to compare addresses is eliminated.
or transmissionby two CPUS simukaneously. With this f=ture enabled in one of the 9-bit modes, the
Receive Interrupt (RI) flag wilI only get set when the
If a stop bit is missing, a Freming Error bit FE is set. received byte corresponds to either a Given or Broad-
The FE bit can be checked in softwareafter each recep- cast address.
tion to detect canrnunication errors. Once set, the FE
bit must be clearedin software.A valid stop bit will not The feature works the same way in the 8-bit mode
clear FE. (Mode 1) es in the 9-bit modes, except that the stop bit
takeathe place of the 9th data bit. If SM2 is set, the RI
The FE bit is located in SCON and shares the same bit flag is set ordyif the receivedbyte matches the Given or
address as SMO.Control bit SMODOin the PCON reg- Broadcast Address and is terminated by a valid stop
ister (location PCON.6) determines whether the SMO bit. Setting the SM2 bit has no effect in Mode O.
or FE bit is accessed. If SMODO = O,then accesses to
SCON.7 are to SMO.If SMODO = 1, themaccesses to The master can Selectivelycommunicate with groups of
SCON.7 are to FE. slaves by using the Given Address. Addressing all
slaves at once is possible with the Broadcast Addreas.
These addresses are defimxl for each slave by two Spe-
7.2 Multiprocessor Communications cial Function Registers:SADDR and SADEN.

Modes 2 and 3 provide a 9-bit mode to facilitate muki- A slave’s individual address is specifkd in SADDR
proceasorcomunicetion. The 9th bit allows the control- SADEN is a mask byte that defines don’t-cares to form
ler to distinguish between eddress and date bytes. The the Given Address. Theae don’t-cam alfow flexibility
9th bit is set to 1 for addressbytes and set to Ofor data in the userdetined protocol to address one or more
bytes. When receiving, the 9th bit goes into RB8 in slaves at a time. The following is an example of how the
SCON. When transmitting, TB8 is set or cleared in user could define Given Addreases to selectively ad-
softwere. dress dithrent slaves.

The amid port can be programmedsuch that when the Stave 1:

stop bit is receivedthe serial port interruptwill be acti- SADDR = 1111 0001
vated ordy if the received byte is an address byte (RB8 SADEN = 1111 1010
= 1).Thisfeature isenabled bysettingtheSM2bitin
SCON. A way to use this featurein multiproceesor sys- GIVEN = 1111 oxox
tems is es follows.
Slave 2:
Wherethe masterprocessorwants to transmit a block of SADDR = 1111 0011
data to one of several slaves, it first sends out an ad- SADEN = 1111 1001
dress byte which identities the target slave. Remember,
anaddress byte has its 9th bit set to 1, whereas a data GIVEN = 1111 Oxxl

5-28
in~. 8XC51FXHARDWAREDESCRIPTION

Table 14. SOON:Serial Port Control Register

SCON Address= 98H ResetValue= 0000OOOOB

Bit Addressable
SMO/FE SM1 SM2 REN TB8 RB8 TI RI
Bit: 5 4 3 2 1 0
(SM% = 0?1)”

Svmbol Function
FE FramingErrorbit.Thisbit is set bythe receiverwhenan invalidstopbit is detected.TheFE
bit is notclearedbyvalidframesbutshouldbe clearedbysoftware.TheSMODO*bit mustbe
setto enableaccessto the FEbit.
SMO SerialPortModeBit O,(SMODOmust= Oto access bit SMO)
SM1 SerialPorlModeBit 1
SMO SM1 Mode Description Saud Rate**
o 0 0 shiftregister Foscl12
o 1 1 8-bitUART variable
1 0 2 9-bitUART Fosc184or Fosc/32
1 1 3 9-bitUART variable
SM2 EnablestheAutomaticAddressRecognitionfeaturein Modes2 or 3. If SM2 = 1thenRIwill
not besetunlessthe received9thdatebit (RB8)is 1,indicatinganaddress,andthe received
byteiSa Givenor BroadcastAddress.In Mode1,if SM2 = 1thenRIwillnot be activated
unlessa validstopbit wasreceived,andthe receivedbyteis a Givenor BroadcastAddress.
In ModeO,SM2shouldbeO.
REN Enablesserialreception.Setbysoftwareto enablereception.Clearbysoftwareto disable
reception.
TB8 The9thdatabitthat will betransmittedin Modes2 and3. Setor clearbysoftwareas
desired.
RB8 In modes2and3, the 9th databit thatwasreceived.In Mode1,if SM2= O,RB8isthe stop
bitthatwasreceived.In ModeO,RB8is not Urjed.
TI Transmitinterruptflag.Setby herdwareat the endof the 8thbit timein ModeO,or at the
beginningof the stopbit in the othermodes,in anyserialtransmission.Mustbe clearedby
software.
RI Receiveinterruptflag.Setbyhardwareat the endof the 8thbit timein ModeO,or halfway
throughthe stopbit timein the othermodes,in anyserialreception(exceptseeSM2).Must
beclearedbysoftware.
NOTE:
●SMOOO
is Ioeated at PCON6.
●*F= = oaoillatm trequeney

The SADEN bvte are selected such that each slave can Notice, however, that bit 3 is a don’t-care for both
be addreased-tely. Notice that bit 1 (MB) is a slaves.This allowstwo ditTerentaddressesto seleet
don’t-carefor Slave1’sGivenAddress,but bit 1 = 1 bothslaves(11110001or 11110101).If a thirdslave
for Slave2. l’h~ to selectively communicate with just was added that required its bit 3 = O, then the latter
Slave 1 the master must send an addreeswith bit 1 = O addreascould be used to communicate with Slave 1 and
(e.g. 1111 0000). 2 but not Slave 3.

Similarly, bit 2 = Ofor Slave 1, but is a don’t-esre for The master cart also communicate with all slaves at
Slave 2. Now to cammunieate with just Slave 2 an sd- onoe with the BroadeastAddress. It is formed from the
dress with bit 2 = 1 must be used (e.g. 1111 0111). logical OR of the SADDR and SADEN registers with
zeros defined as don’t-cares.The don’t-caresalso allow
Finally, for a master to eommunieste with both slaves
at once the address must have bit 1 = 1 and bit 2 = O.
5-29
i~. 8XC51FXHARDWAREDESCRIPTION

flexibility in detiningthe Broadcast Address, but in 3 = 2SMOD1x Timer 1 OverflowRate

MocactilR:mJ
most applications a BroadeastAddress will be OFFH. 32

SADDR and SADEN are located at address A9H and TheTimer1interruptshouldbedisabledin thisappli-
B9H, respectively. On rese~ the SADDR and SADEN cation.The Timeritselfcan be configuredfor either
registersare initiahzed to OOHwhich defines the Given “timer”or “counter”operatiom and in any of its 3
and Broadeast Addrcaseaas XXXX XXX?( (all don’t- running modes. In most applications, it is configured
cares). This assures the C51FX serial port to be back- for “timer” operation in the auto-reload mode (high
wards compatibility with other MCW-51 products nibble of TMOD = OO1OB).In this casq the baud rate
which do not implement Automatic Addrmsing. is given by the formula:

Modes I and3 = ~MOD1x OscillatorFrequency

7.4 Baud Rates BaudRate 32X 12 X ~56– (THl)]

The baud rate in Mcde Ois fixed: Onecanaohieve verylow baud rateswithTimer1 by
leaving the Timer 1 interrupt enabled, and eontiguring
OscillatorFrequency the Timer to run as a Id-bit timer (high nibble of
ModeOBaudRate =
12 TMOD = OOOIB),and using the Timer 1 interrupt to
do a 16-bit software reload.
The baud rate in Mode 2 depends on the value of bit
SMOD1 in Special Function Register PCON. If Table 15 lists various commonly used baud rates and
SMOD1 = O (which is the value on reset), the baud how they earsbe obtained from Timer 1.
rate is 1\e4the oscillator frequency.If SMOD1 = 1, the
baud rate is ~$2the oaeillatorfrequency.
7.6 Using Timer 2 to Generate Baud
Mode 2Baud Rate = 2srJoDl x ‘i’’a’o[requenq Rates
Timer 2 is selected asthe bad rate generatorby setting
The baud ratea in Modes 1 and 3 are deterrnined by the TCLK and/or RCLK in T2CON (Table 7). Note that
Timer 1 overflow rate, or by Timer 2 overflow rak or the baud rates for transmit and receive can be simuka-
by both (one for transrnr
“tand the other for receive). neously different. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate geueratormode, as shown in
Figure 23.
7.5 Using Timer 1 to Generate Baud
Rates The baud rate generatormode is similar to the auto-re-
load mode in that a rollover in TH2 eauseathe Timer 2
WhenTimer 1 is used as the baud rate generator, the registersto be reloadedwith the 16-bitvalue in registers
baud rates in Modes 1 and 3 are dctermrn “ ed by the RCAP2H and RCAP21+ which are prsaetby software.
Timer 1 overflow rate and the value of SMOD1 as fol-
lows:

Table 15. Timel Generated ( UsedSaud Rates

Timel
BarsdRate fofjc Reload
C17 Value
ModeOMax:1 MHz 12MHz x x x x
Mode 2 Max:375K 12 MHz 1 x x
Modes1,3: 62.5K 12MHz 1 o 2 F:H
19.2K 11.059MHz 1 0 2 FDH
9.6K 11.059 MHz 0 0 2 FDH
4.8K 11.059MHz 0 0 2 FAH
2.4K 11.059MHz 0 0 2 F4H
1.2K 11.059MHz 0 0 2 E6H
137.5 11.986MHz 0 0 2 IDH
110 6 MHz 0 0 2 72H
110 12MHz 0 0 1 FEEBH

5-30
in~. 8XC51FXHARDWAREDESCRIPTION

The baud rates in Modas 1 and 3 are deterrnined by as a baud rate generator, T2EX can be used as an extra
Timer 2’s overflow rate as follows: external interrupt, if desired.

It should be noted that when Timer 2 is *J3 w

Modesland3BaudRates= ‘i’”’r20’’’tO’Rate’
Rate
= 1) in “timer” firncticmin the baud rate generator
mode, one should not try to reador write TH2 or TL2.
The Timer can be contlgured for either “timer” or Under these conditions the Timer is being incremented
“counter” operation. In most a~lications, it is config- every state time, and the results of a read or write may
ured for “timer” operation (C/T2 = O).The “Timer” not be accurate. The RCAP2 registersmaybe read, but
operation is different for Timer 2 when it’s being used shouldn’tbe written to, because a writemight overlap a
as a baud rate generator. Normally, as a timer, it incre- reload and cause write and/or reloademors. The timer
ments every machine cycle (1/12 the oscillator frequen- should be turned off (clear TR2) before accessing the
Cy).AS a baud rste generator, however, it increments Timer 2 or RCAP2 registers.
every state time (1/2the oscillatorfrequency).The baud
rate formula is given below: Table 16 lists commonly used baud ratesand how they
can be obtained from Timer 2.
Modes 1 and 3 = Oscillator Frequency
Baud Rate 32 X [65536 - (RCAP2H, RCAP2L)] Table 16.Timer 2 Generated
Commonly Used Baud Rates
where (RCAP2H, RCAP2L) is the content of
RCAP2H and RCAP2L taken as a l~bit unsigned Baud Osc Timer 2
integer. Rate Fraq RCAP2H RCAP2L

Timer 2 as a baud rate generatoris shown in Figure 23. 375K 12 MHz FF FF

This tigureis valid only if RCLKand/or TCLK = 1 in 9.6K 12 MHz FF D9
T2CON. Note that a rollover in TH2 does not set TF2, 4.6K 12 MHz FF B2
and will not generatean interrupt.Therefore the Timer 2.4K 12 MHz FF 84
2 interruptdoes not have to be disabled when Timer 2 1.2K 12 MHz FE C8
is in the baud rate generator mode. Note too, that if 300 12 MHz FB IE
EXEN2 is seL a l-to-O transition in T2EX will set 110 12 MHz F2 AF
EXF2 but will not cause a reload from (RCAP2H, FD
300 6 MHz 8F
RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use
110 6 MHz F9 57

ml
Ovsnn.ow

+-l
r NomOec.Psao.
taolnDaoBY 2, MOT 12.
D
+’2
I
74 1
-L TH2 TLS

.Rx Cmex

1 1 1 1 ? ‘—
RCAP2L
I 1
r=
RCAP2H TX CLOCK
I

L non! ~ OFAmrnonu axramsL Wrremw’r

270S53-20

Figura 23. Timer 2 in Baud Rate Generator Mode

5-31
i~. 8XC51FXHARDWAREDESCRIPTION

8.0 INTERRUPTS All of the bits that generate interrupts earrbe set or
cleared bv software, with the same reault as though it
The C51FX h33 a total of 7 interruptveetors: two ex- had been-setor clea&l by hardware.That is, intefipts
temal interrupts (INTO and ~), three timer inter- earlbe generatedor pending interrllpt3ean be cancelled
rupts (Them O, 1, and 2), the PCA interrupt, and the in sot%vare.
serial port interrupt. Theae interruptsare all shown in
Figure 24. Each of these interrupts will be briefly deaeribedfol-
lowed by a discussion of the interrupt enable bits and
the interrupt priority levels.

o
mm

TFo
1

ql~

➤
I
I

o
m [El ➤
1
1

ql~

TFl
‘1

o 1 I INTERRUPT
SOURCES

CCFn J ECCFn

1
5,

n
RI
I
J:~ J 2706S3-21
(SeeexcretionswhenTimer2 isusedsebaudrategenerator
oranup/downcounter.)
Figure 24. interrupt 8ources

5-32
in~. 8XC51FXHARDWAREDESCRIPTION

8.1 External lnterrupta 8.3 PCA Interrupt

External
Interrupts~ and INT1 can each be either The PCA interrupt is generated by the logical OR of
level-activated or transition-activated, depending on CF, CCFO,CCFI, CCFZ, CCF3, and CCF4 in register
bits ITOand IT1 in registerTCON. If ITx = O,exter- CCON. None of these flags is cleared by hardware
nal interrupt x is triggered by a detected low at the when the service routine is vectored to. Normally the
~ pin. If ITx = 1, external intemupt x is negative service routine will have to determine which bit flagged
edge-triggered.The flags that actually generate these the interrupt and ckar that bit in software. The PCA
interrupts are bits IEOand IEl in TCON. These flags interrupt is enabled by bit EC in the Interrupt Enable
are cleared by hardware when the service routine is register (see Table 16). In addition, the CF flag and
vectored to only if the interrupt was tranaition-aetivat- each of the CCFn flags must also be enabled by bits
ed. If the interrupt was Ievel-aetivatq then the exter- ECF and ECCFn in registers CMOD and CCAPMn
md requesting source is what controls the request tlag, respectively, in orderfor that flag to be able to causean
ratherthantheon-chiphardware. interrupt.
Since the externalinterrupt pins are sampled once each
machine cycle an input high or low should hold for at 8.4 Serial Port Interrupt
least 12 oscillator perioda to ensure sampling. If the
external interrupt is transition-activated, the external The serirdport interruptis generatedby the logical OR
sourcz has to hold the request pin high for at least one of bits RI and TI in register SCON. Neither of these
cycle, and then hold it low for at least one cycle to tlags is cleared by hardwarewhen the service routine is
ensure that the transition is seen so that interrupt re- vectored to. The seMee routine will normally have to
quest flag IEx will be set. IEx will be automatically determine whether it was RI or ‘H that generated the
cleared by the CPU when the seMce routine is called. interrupt, and the bit will have to be cleared in sotl-
ware.
If external interrupt ~ or ~ is level-activat~
the external source has to hold the request active until
the requested interrupt is actually generated. Then it 8.5 Interrupt Enable
has to deactivate the request before the interrupt serv-
ice routine is completed, or else another interrupt will Each of these interrupt sources can be individually en-
be generated. abled or disabled by setting or clearing a bit in the
Interrupt Enable (fE) register. (See Table 17.) Note
that IE also contains a global disable bit, EA. If EA is
8.2 Timer Interrupts set (1), the interrupts are individually enabled or dis-
abled by their corresponding bits in IE. If EA is clear
Timer Oand Timer 1 Interrupts are generatedby TFO (0), all interrupts are disabled.
and TFl in registerTCON, which are set by a rollover
in their respectiveTimer/Counter registers (except see
Timer Oin Mode 3). When a timer interrupt is generat- 8.6 Priority Level Structure
ed, the tlag that generated it is cleared by the on-chip
hardwarewhen the service routine is vectored to. Each interrupt source can also be individually pro-
_ed to one of two priority levels, by setting or
Timer 2 Interruptis generatedby the logical OR of bits clearing a bit in the Intemupt Priority (1P) register
TF2 and EXF2 in register T2CON. Neither of these shown in Table 18. A low-priority interrupt can itself
tlags is cleared by hardwarewhen the service routine is be interruptedby a higher priority interrupt, but not by
vectored to. In f- the service routine may have to another low-priority interrupt. A high priority inter-
determine whetlm it was TF2 or EXF2 that generated rupt CSIUIOt be interrupted by my Other interrupt
the interrupt, and the bit will have to be cleared in source.
software.

5-33
i~e 8XC51FXHARDWAREDESCRIPTION

Table 17. IE: Interrupt Enable Register

IE Address= OA8H ResetValue= 000000006

Bit Addressable
I EA EC ET2 ES ETl EX1 ETo Exo
Bit 7 6 5 4 3 2 1 0
EnableBit = 1 enablesthe interrupt.
EnableBit = Odisablesit.
Svmbol Function
EA Globaldisablebit. If EA = O,all Interruptsaredisabled.If EA = 1,eachInterruptcanbe
individuallyenabledor disabledbysettingor clearingitsenablebit.
EC PCAinterruptenablebit.
ET2 Timer2 interrupt enable bit.
ES SerialPorfinterruptenablebit.
ETl Timer1 interruptenablebit.
Exl Externalinterrupt1 enablebit.
HO TimerOinterruptenablebit.
EXO ExternalinterruptOenablebit.

Table 18. 1P:Interrupt PrioritY Re9isters

1P Address = OB8H Reset Value = XOOOOOOOB

Bit Addressable
— PPC PT2 Ps PTl Pxl PTO Pxo
Bit 7 6 5 4 3 2 1 0
PriorityBit = 1 assigns highpriority
PriorityBit = Oassignslowpriority

Symbol Function
— Notimplemented,reservedfor futureuse.*
PPC PCAinterruptprioritybit.
PT2 Timer2 interruptprioritybit.
Ps SerialPortinterruptprioritybit.
PT1 Timer 1 interrupt priority bit.
Pxl Externalinterrupt1 prioritybit
PTO TimerOinterruptprioritybit.
Pxo ExternalinterruptOprioritybit.
NOTE:
●User softwareshouldnot wrtte Is to reservedbits.These bits maybe usad in future8051 familyproductsto invoke
new features.In that case, the reset or inactivevalue of the new bitwillba O,and its active value willbe 1. The value
read from a reservedbit is indeterminate.

5-34
i~. 8XC51FXHARDWAREDESCRIPTION

If two requests of different priority levels are received Table 21. Priority Level Bit Values
simultaneously, the request of higher priority level is
servieed. If requests of the same priority level are re- Priority
Bits Interrupt Priority
ceived simultaneously, an internal polling sequence de-
Level
termines which request is servieed. Thus within each IPH.x IP.X
priority level there is a second priority structure deter-
mined by the potling sequence shown in Table 19. o 0 LevelO (Lowest)

Note that the “priority within level” structure is only

1o11 I Levell I
used to resolvesimultaneous requestsof thesameprian”- 11 I O I Level2 I
ty level.
1111 I Leve13 [Hiahest) I
Table 19. Interrupt Priority
within Level Polling Seauence
How Interrupts are Handled
1 (Highest) INTO
2 TimerO Theinterruptflagsare sampled at S5P2 of every ma-
chine cycle. The samples are polled during the follow-
3 m
ing machine cycle. The Timer 2 interrupt cycle is
4 Timer1 slightly different, as described in the Response Time
5 PCA section. If one of the tlags was in a set condition at
6 SerialPort S5P2 of the precading cycle, the polling cycle will fmd
7 (Lowest) Timer2 it and the interrupt system will generate an LCALL to
the appropriate serviee routine, provided this hard-
ware-generated LCALL is not blocked by any of the
8XC51FXInterrupt Priority Struoture following conditions:
1. An interrupt of equal or higher priority level is al-
In the 8XC51FX, a second Interrupt Priority register
ready in progress.
(IPH) has been added, increasingthe number of priori-
ty levels to four. Table 20 shows this second register. 2. The current (polling) cycle is not the final cycle in
The added register becomes the MSB of the priority the execution of the instruction in progress.
select bits and the existing 1P registeracts as the LSB. 3. The instruction in nroaressis RETI or anv write to
This scheme maintains eotnpatibility with the rest of the IE or 1P regiat~rs.-
the MCS-51 family. Table 21 shows the bit values and
priority levels associated with each combination.

Table 20. IPH: Interrupt Priority High Register

IPH Address = OB7H Reeet Value = XOOO0000

Not Bit Addressable

— PPCH PT2H PSH PTIH PXIH PTOH PXOH
Bit 7 6 5 4 3 2 1 0

Svmbol Funotion
— Notimplemented, reservedfor futureuse.
PPCH PCAinterrupt priority high bit.
PT2H Timer2 interruptpriorityhighbit.
PSH SerialPortinterruptpriorityhighbit.
PTIH Timer1interruptpriorityhighbit.
PXIH Externalinterrupt1 priorityhighbit.
PTOH TimerOinterruptpriorityhighbit.
PXOH Externalinterruptpriorityhighbit.

5-35
i~. 8XC51FXHARDWAREDESCRIPTION

Any of these three conditions will block the generation Table . Interrupt ~ ctor Addn la
of the LCALL to the interrupt service routine. Condi-
tion 2 ensures that the instruction in progress will be
mmpleted before vectoring to any seMce routine. Con-
dition 3 ensures that if the instruction in progress is
Interrupt
Source
m
Interrupt

IEO
LXearedby Veotor
?equeetBite l+srdware Address
No (level)
7
OO03H
RETI or any write to IE or 1P, then at least one more Yea (trans.)
instruction will be executed before any interrupt is vec-
tored to.
TIMERO TFO Yes OOOBH
The polling cycle is repeated with each machine CYC1%
and the values polled are the values that were present at m IEI No (level) O013H
S5P2 of the previous machine cycle. If the interrupt Yea (trans.)
fig for a Zeve/-sensitiveexternal interrupt is active but
not being responded to for one of the above conditions TIMER1 TF1 Yes OOIBH
and is not still active when the blocking wndition is
removed, the denied interrupt will not be serviced. In ;ERIALPOR1 Rl,TI No O023H
other worda, the fact that the interrupt flag was once
active but not serviced is not remembered. Every poll-
ing cycle is new. TIMER2 TF2,EXF2 No O02BH

The polling cycle/LCALL sequence is illustrated in PCA CF,CCFn No O033H

Figure 25. (n = O-4)

Note that if an interrupt of a higher priority level goes Execution proceeds from that location until the RETI
active prior to S5P2 of the machine cycle labeled C3 in instructicm-is enwuntered. The RETI instruction in-
Figure 25, then in awordance with the above rules it forms the proceasor that this intemupt routine is no
will be vectored to during C5 and C6, without any in- longer in progress,then pops the top two byteafkomthe
struction of the lower priority routine having been exe- stack and reloads the Program Counter. Execution of
cuted. the interrupted program wntinuee from where it left
off.
Thus the proceasor acknowledges an interrupt request
by executing a hardware-generatedLCALL to the ap Note that a simple RET instruction would also have
propriate servicing routine. The hardware-generated returned execution to the interrupted program, but it
LCALL pushes the contents of the Program Counter would have left the interrupt control system thinking
onto the stsck (but it does not save the P3W) and re- interrupt was still in profyess.
loads the PC with an address that depends on the
source of the interrupt being vectored to, as shown in Note that the starting addresses of consecutive inter-
Table 22. rupt service routines are only 8 bytes apart.That means
if consecutive interrrmtsare being used (IEOand TFO.
for example, or TFO&d IEl), ma ifthe’first interrupt
routine is more than 7 bytes long, then that routine will
have to execute a jump to some other memory location
where the service routine can be wmpleted without
overlapping the starting address of the next interrupt

laaPal Se I

““””””””~~~~--
.....

6 INTERRUPTS LONG CALL TO INTERRuPT ROUTINE

f-1 ARE POLLED INTSRRUPT
INTERRUPT INTERRUPT VECTOR AOORESS
GOES LATCHEO
ACTIVE
270SS2-22
This is the fastest possibleresponsewhen C2 is the final cycleof an instructionother then REH or writeIE or 1P.

Figure 25. Interrupt Response Timing Diagram

5-36
intd. 8XC51FXHARDWAREDESCRIPTION

8.7 Response Time or write to IE or IP, the additional wait time cannot be
—— more than 5 cycles (a maximum of one or more cycle to
The INTO and INT1 levels are inverted and latched complete the instruction in progress, plus 4 cycles to
into the Interrupt Flags IEOand IE1 at S5P2 of every complete the next instruction if the instruction is MUL
machine cycle. Similarly, the Timer 2 flag EXF2 and or DIV).
the serial Port tlags RI and TI are set at S5P2. The
values are not actually polled by the circuitry until the Thus,ina single-interrupt
system, the response time is
next machine cycle. always more than 3 cycles and less than 9 cycles.

The Timer Oand Timer 1 flags, TFOand TFl, are set at

S5P2 of the cycle in which the timers overflow. The 9.0 RESET
values are then polled by the circuitryin the next cycle.
However, the Timer 2 flag TF2 is set at S2P2 and is The reset input is the RST pirL which has a Schmitt
polled in the same cycle in which the timer overflows. Trigger input. A reset is accomplishcd by holding the
RST pin high for at least two machine cycles (24 oscil-
If a requestis active and conditions are right for it to be lator periods) while the Oscilbtor is running. The CPU
acknowledged, a hardware subroutine call to the re- r~nds by generating an internal r= with the tim-
quested serviceroutine will be the next instruction to be ing shown in Figure 26.
executed. The call itself takes two cycles. Thus, a mini-
mum of three complete machine cycles elapseabetween The externalreset signal is asynchronousto the internal
activation of an external interrupt request and the be- clock. The RST pin is sampled during State 5 Phase 2
ginning Of execution of the service routine’s @t in. of every machine cycle. ALE and PSEN will maintain
struction. Figure 25 shows interrupt response timing. their current activities for 19 oscillator periods after a
logic 1 has been sampled at the RST pirLthat is, for 19
A longer response time would result if the request is to 31 oscillator periods after the external reset signal
blocked by one of the 3 previously listed conditions. If has been applied to the RST pin. The port pine are
an interrupt of equal or higher priority level is already driven to their reaet state as soon as a valid high is
in Proaress,the additional wait time obviouslv dmends detected on the RST pin, regardkas of whether the
on-the-natureof the other interrupt’sservice;outine. If clock is running.
the instruction in progress is not in its final cycle+the
additional wait time cannot be more than 3 cycles, since
the longest instructions (MUL and DIV) are only 4
cycles long, and if the instruction in progress is RETI

~12 OSC. PERIODS-----+

I S5 I S6 I S1 I S2 ] S3 I S4 I S5 I S6 I S1 I S2 I S3 I S4 I S5 I S6 I S1 I S2 I S3 I S4 [

RST:
//////////!
~lNTERNAL RESET SIGNAL
SAMP~ RST SAMP~E RST
, 1 I
, ,
1
ALE: ,

PSEN:
I II I I I I I I
I
,

I , I

Po: INST INST ADDR

~
f I
—11 OSC. PERIoDS — 19 OSC. PERIODS _
270653-23

Figure 26. Reset Timing

5-37
i~. 8XC51FXHARDWAREDESCRIPTION

while the RST pin is high, the port pins, ALE and Note that theportpins wiilbe in a mndom state until the
PSEN are weakly pulled high. After RST is pulled low, oscillator has started and the internal reset aigorithm
it will take 1 to 2 machine cycles for ALE and FSEN to has wn”ttenIs to them.
start clocking. For this reason, other devices can not be
synchronized to the internal timings of the 8XC51FX. Powering up the device without a valid reset could
cause the CPU to start executing instructions from an
Driving the ALE and PSEN pins to O while react is indeterminate location. This is because the SFRS, spe-
active could cause the device to go into an indetermi- cifically the Program Counter, may not get properly
nate state. initialized.

The internalreset algorithm redefinesall the SFRS. Ta-

ble 1 lists the SFRS and their reset values. The internal 10.0 POWER-SAVING MODES OF
RAM is not affected by reset. On power up the RAM OPERATION
content is indeterminate.
For applications where power consumption is critical,
the C51FX provides two power reducing modes of op-
9.1 Power-On Reset eration: Idle and Power Down. The input through
which backup power is supplied during these opera-
For CHMOS devices, when VCC is turned on, an auto- tions is Vcc. Figure 28 shows the internal circuitty
matic reset can be obtained by connecting the RST pin which implements these featurea. In the Idle mode
to VCC through a 1 pF capacitor (Figure 27). The (IDL = 1), the oscillator continues to run and the In-
CHMOS devices do not requirean externalreaistorlike terrupt, Serial Port, PCA, and Timer blocks continue
the HMOS devices because they have an internal pull- to be clocked, but the clock signal is gated off to the
down on the RST pin. CPU. In Power Down (PD = 1), the oscillator is fro-
zen. The Idle and Power Down modes are activated by
When poweris turned on, the circuit holds the RST pin setting bits in Special Function Register PCON (Table
high for an amount of time that depends on the eapaei- 23).
tor value and the rate at which it charges. To ensure a
valid resetthe RST pin must be held high long enough
to allow the oscillator to start up plus two machine 10.1 Idle Mode
cycles.
Aninstruction that sets PCON.O causes that to be the
last instruction executed before going into the Idle
mode. In the Idle mode, the internal clock signal is

1+
gated off to the CPU, but not to the Interrupt, Timer,

n’
and Serial Port fimctions. The PCA can be pro-
v#J grammed either to pause or continue operating during
1 pf Idle (refer to the PCA section for more details). The
3XC51FA/lB/FC CPU status is preservedin its entirety:the Stack Point-
er, Program Counter, Program Status Word, Accumu-
RST lator, and all other registers maintain their data during
Idle. The port pins hold the logical states they had at
the time Idle was activated. ALE and FSEN hold at
%s logic high levels.

= There are two ways to terminate the Idle Mode. Activa-

270S53-24
tion of any enabled interrupt will cause PCON.Oto be
cleared by hardware, terroinating the Idle mode. The
Figure 27. Power on Reset Circuitry
interruptwill be serviced, and following RETI the next
instruction to be executed will be the one fOUowingthe
On powerup, VCCshouldrisewithinapproximately
ten millkeonds. The oscillator start-uDtime will de- instruction
thatputthedevice
intoIdle.
pendon the oscillator frequency. For a iOMHz crystal, The flag bits (GFO and GF1) can be used to give art
the start-up time is typically1 msec.For a 1 MHz
indication if an interrupt occurred during normal oper-
crystal,the start-uptime is typically 10 masc. ation or during Idle. For example an instruction that
activates Idle can also set one or keth flag bits. Wheo
With the given circuit, reducing Vcc quickly to Ocaus-
Idle is terminated by an interrupt, the interruptservice
es the RST pin voltage to momentarily fall below OV.
routine can examine the flag bits.
However, this voltage is internally limited and will not
harm the device.

5-38
intdo 8XC51FXHARDWAREDESCRIPTION

The other way of terrninating the Idle mode is with a The signal at the RST pin clears the IDL bit directly
hardware reset. Since the clock oscillator is still nm- snd asynchronously. At this time the CPU resumes
ning, the hardwarereset needs to be held active for only program execution from where it left off; that is, at the
two machine cycles (24 oscillator periods) to complete instruction following the one that invoked the Idle
the reset. Mode. As shown in Figure 26, two or three machine
cycles of program execution may take place before the

2’7
STAL2
1
II
T
= xTAL1
I

Oac

+ %-lI
CLOCS
GEN.
1
INTERRUPT,
DSERIAL PORT,
TIMER BLOCKS

Figure 28. Idle and Power Down Hardware

Table 23. PCON:Power Control ReQieter

PCON Address = 87H Reset Value = OOXXOOOOB

Not Bit Addressable

SMOD1SMODO — POF GF1 GFO PD IDL I
Bit 7 6 5 4 3 2 1 0

Symbol Funotion
SMOD1 DoubleBaudratebit.Whensetto a 1 andTimer1 is usedto generatebaudrates,andthe
SerialPortis usedin modes1,2, or 3.
SMODO Whenset,Read/Writeaccessesto SCON.7areto the FEbit.Whenclear,Read/Write
accessesto SCON.7areto the SMObit.
— Not implemented,reservedfor futureuee.*
POF Power Off Flag. Set by hardware on the rising edge of VCC. Set or cleared by software. This
flag allows deteetion of a power failure caused reset. V= must remain above 3V to retain
this bit.
GF1 General-purpose flag bit.
GFO General-purpose flagbit.
PD PowerDownbit.Settingthis bitactivatesPowerDownoperation.
IDL Idlemodebit.Settingthisbit activatesidlemodesoperation.
If 1sarewrittento PDandIDLat the sametime,PDtakesprecedence.
NOTE
*Uaer softwareshouldnot write la to unimplementedbits.These bits msy be used in future8051 familyproductsto
invokenew featurea. In that ease, the reset or inactivevalue of the new tit will be O, and ifa active valus will be 1.
The vslueread from a reservedbit is indeterminate

5-39
i@e 8XC51FX HARDWARE DESCRIPTION

internal reset algorithm takes control. On-chip hard- warm start reset occurswhile VCCis still applied to the
ware inhibits access to the internal IUM during this device and could be generated, for example, by a
time, but acceas to the port pins is not inhibited. To Watchdog Timer or an exit from Power Down.
eliminate the possibility of unexpected outputs at the
port pins, the instruction following the one that invokes Immediately after reset, the user’s software can check
Idle should not be one that writes to a port pin or to the atatus of the POF bit. POF = 1 would indicate a
external Data RAM. cold atart. The software then clears POF and com-
mences its tasks. POF = O immediately after reset
would indicate a warm start.
10.2 Power Down Mode
Vcc must remain above 3 volts for POF to retain a O.
Aninstruction that sets PCON.1 causes that to be the
last instruction executed before going into the Power
Down mode. In this mode the on-chip oscillator is 11.0 EPROM VERSIONS
stopped. With the clock frozen, all functions are
stopped, but the on-chip RAM and Special Function The8XC51FX mea the Improved “Quick-Pulse” pr~
Registem are held. The port pins output the values held _gm ~gorithrn. ~- devices pro-at VPP
by their respective SFRS and ALE and PSEN output = 12.75~d V~ = 5.OV) using a series of five
lows. In Power Down Vcc can be reduced to as low as 100 ps PROO pulaeaper byte programmed. This re-
2V. Care must be taken, however, to ensure that Va is auhs its a total programmingtime of approximately 5
not reduced before Power Down is invoked. seconds for the 87C51FA’S8 Kbyt~ 10 seconds for the
87C51FB’S 16 Kbytes, and 20 seconds for the
The C51FX can exit Power Down with either a hard- 87C51FC”S32 Kbytea.
ware reset or external interrupt. Reset redefineaall the
SFRS but doeanot change the on-chip IUUkf.An exter- Exposare to Light The EPROM window must be cov-
nal interrupt allows both the SFRS and the on-chip ered with an opaque label when the device is in opera-
IUUU to retairstheir valuea. tion. This is not so much to protect the EPROM array
from inadvertent erasure,but to protect the RAM and
To properly terminate Power Down the reset or exter- other on-chip logic. Allowing light to impinge on the
nal interrupt should not be executed before VCC is silicon die while the device is operating oan cause logi-
restored to its normal operating level and must be held cal malfunction.
active long enough for the oscillator to restart and sta-
bilize (normally leas than 10 maec).
—— 12.0 PROGRAM MEMORY LOCK
With an external intermpL INTO or INT1 must be en-
abled and configured as level-sensitive. Holding the pin In some microcontroller applications, it is desirable
low restarta the oscillator and bringing the pin back that the Program Memory be secure from software pi-
high completes the exit. After the RETI instruction is racy. The C51FX has varying degrees of program pro-
executed in the interrupt service routine, the next in- tection depending on the device. Table 24 outlines the
struction will be the one following the instruction that lock schemes availablefor each device.
put the device in Power Down.
EmYPtion Array:within the EPROM/ROM is MSiu-
ray of encryption bytes that are initially unprogrammed
10.3 Power Off Flag (all l’s). For EPROM devi% the user can program
the encryption arrayto encrypt the programcode bytea
ThePower Off Flag (POP) located at PCON.4, is set during EPROM verification. For ROM devices, the
by hardware when VCCrises from O to 5 Volts. POF user submits the encryptionarrayto be programmed by
can rdsobe set or cleared by software. This allows the the factory. If an encryption array is submitted, LB1
user to distinguish betw$mta “cold start” reset and a will also be programmedby the factory. The encryption
“warns start” reset. array is not available without the Leek Bit. Program
code verifkation is performedas usual, except that each
A cold start reset is one that is coincident with Vcc code byte comes out exclusive-NOR’ed (XNOR) with
being turned onto the device after it was turned off. A

5-40
int@ 8XC51FXHARDWAREDESCRIPTION

one of the key bytes. Therefore,to read the Table 24. C51FX Program Protection
ROM/EPROM code, the user has to know the encryp-
tion key bytes in their proper sequence. Device Lock Bite Encrypt Array
I 83C51FA I None I None I
Unprogrammed bytes have the value OFFH. If the En-
cwtion Array is left unprogrsrmnedj all the key bytes
have the value OPPH. Since any code byte XNOR’ed
with OFFH leaves the byte unchanged, leaving the En-
cryption Array unprogrammed in efkt bypassea the
encryption feature.

When using the encryption array feature, one import- I 87C51FC I LB1,LB2,LB3 I 64 Bytes I
ant factor should be considered. If a code byte has the
value OFFH, verifyingthe byte will produce the encryp-
tion byte vsdue.If a large block (>64 bytes) of code is
13.0 ONCETM MODE
left rmprograrmned,a verification routine will display
the encryption array contents. For this reason all un- The ONCE (ON-Circuit Emulation) mode facilitstea
used code bytes should be progrsmmed with some val- testing and debugging of systems using the C51FX
ue other than OFFH,and not all of them the same val- without having to remove the device from the circuit.
ue. This will ensure maximum program protection. The ONCE mode is invoked by:
Program Lack Bits: Alao included in the Program 1. Pulling ALE low while the device is in reset and
Lock scheme are Lock Bits which can be enabled to PSEN is higiu
provide varyingdegr- of protection. Table 25 lists the 2. Holding ALE low as RST is deactivated.
Lock Bita and their corresponding influence on the mi-
crocontroller. Referto Table 24 for the Lack Bits avail- While the device is in ONCE mode, the Port Opins go
able on the variousproducts. The user is responsiblefor into a float state, and the other port pins, ALE, and
pro-g the Lock Bits on EpROM devi~. on PSEN are weakly pulkd high. The oscillator circuit
ROM devices, LB1 is automatically set by the factory remains active. While the device is in this mode, an
when the encryption array is submitted. The LmckBit emulator or test CPU can be used to drive the circuit.
is not available without the encryption array on ROM
devices. Normrd operation is restored after a valid reset is ap-
plied.
Erasing the EPROM also erases the Encryption Array
and the Lock Bits, returningthe part to full functionali-
ty.

Table 25. Lock Bita

Program Lock Bite
Protection Type
LB1 LB2 I LB3

IIIuuu
I No programlockfeaturesenabled.(Codeverifywill still beencryptedbythe
encryptionarray if programmed.) I
II2PUU
I MOVCinstructionsexecutedfromexternalprogrammemory are disabled from
fetchina code bvtes from internal rnemow. EA is samDled and latched on
reset ~ndfutlherprogramming
of the EPROMis di=bled.
I
31 P I P I u ] 3ameas2, alsoverifyisdisabled.
41 P I P ] P Sameas3, alsoexternalexecutionis disabled. I
P = Programmed
U = Unprogrammed
Any other combinationof the Lock Bita is not defined.

5-41
intele 8XC51FXHARDWAREDESCRIPTION

14.0 ON-CHIP OSCILLATOR Frequency, tolerance, and temperaturerange are deter-

mined by the system requirements.
The on-chip oscillator for the CHMOS devices, shown
in Figure 29, consists of a single stage linear inverter A ceramic resonator can be used in place of the crystal
intended for use as a crystal-controlled, positive reac- in cost-sensitive applications. When a ceramic resona-
tance oscillator. In this applicationthe crystal is operat- tor is us-ad,Cl and C2 are normally selected ss higher
ing in its fimdamental response mode as an inductive values, typically 47 pF. The manufacturerof the ceram-
reactancein parallel resonance with capacitance exter- ic resonator should be consulted for recommendations
nal to the crystal (Figure 30). on the values of these capacitors.

The oscillatoron the CHMOS devicescan be turned off A more in-depth discussion of crystalspecifications, ce-
under software control by setting the PD bit in the ramic resonators,and the selection of valueafor Cl and
PCON register. The feedback resistor Rf in Figure 29 C2 can be found in Application Note AP-155, “Oscilla-
consists of paralleled n- and p-channelFETs controlled tors for Microcontrollers” in the Embedded Applica-
by the PD bit, such that Rf is opened when PD = 1. tions handbook.
The diodes D1 and D2, which act as clamps to VcC
and V~, are parasitic to the Rf FETs. To drive the CHMOS parts with an extemrd clock
source, apply the external ckwk signal to XTAL1 and
The crystal specifications and capacitance valus (Cl leave XTAL2 floating as shown in Figure 31. This is an
and C2 in Figure 30) arc not critical. 30 pF can be used ~po~t ~crcnce from the HMOS parts. With
in these pesitions at any frequency with good quality HMOS, the external clock sourceis applied to XTAL2,
crystals. In general, crystals used with these devices and XTAL1 is grounded.
typically have the following specifications:
ESR (Equivalent Series Resistance) see Figure 32 h external oscillator may encounter as much as a
100 PF load at XTAL1 when it startsup. This is due to
~ (shunt capacitance) 7.0 pF maximum inte~tion between the amplitier and ~ts feedback ca-
CL~OSdmptiti=) 30 pF *3 pF pacitance. Once the external signal meets the VIL and
VIH specifications the capacitanm will not exceed
Drive Level lMW
20 pF.

Vcc
lo INTERNAL
nNING Clcrs T

ma m

;+
Xm.1 XlU2

r?‘ 1
02

‘m+
F

mm

27066S-26

Figure 29. On-Chip Oscillator Circuitry

5-42
intel. 8XC51FXHARDWAREDESCRIPTION

m
v=
70 m7aRNA1. m
mmri rxrrs

v=
-------- XTAL1----- XIAE?------
meal

270653-27

Figure 30. Ueing the CHMOS On-Chip Oscillator

NC ~
I
X7AL2
8XC51FX

500 11

Pigure31. Driving the CHMOS Parts with an

ExtemelClockSource
I
4 a 12 16
CRVS7ALFREOUENCYIn MHz
270653-23
15.0 CPU TIMING
The internal clock generator defiies the sequence of Figure32.ESRvsFrequency
states that make up a machine cycle. A machine cycle
consists of 6 states, numbered S1 through S6. Each each other. The timings published in the data sheets
state time lasts for two oscillator periods. Thus a mac- include the etkets of-propagation delays under the
hine cycle takes 12 oscillator periodsor 1 microsecond
specified test condition.
if the oscillator frequency is 12 MHz. Each state is then
divided into a Phase 1 and Phase 2 half.
ADDITIONAL REFERENCES
Rise and fall times are dependent on the external load-
ing that each pin must drive. They are approximately
Thefollowing application notes provide supplemental
information to this document and can be found in the
10 nsec, measured between 0.8V and 2.OV.
Embedded Applications handbook.
Propagation delays are different for different pins. For 1. AP-125 “Designing Microcontroller Systems for
a given pin they vary with pin loading, temperature, Electrically Noisy Environments”
VCc, and manufacturing lot. If the XTAL1 wavefomr 2. AP-155 “Oscillators forMicrocontrollers”
is taken as the timing reference, propagation delays
may vary from 25 to 125 nsec.
3.AP-252“Designing
withthe 80C51BH”
4, APA$10“Enhanced serial Port on the 83C51FA”
The AC Timings section of the datasheets do not refer- 5. AP415 “83C51FA/FB PCA Cookbook”
ence any timing to the XTAL1 waveform. Rather, they
6. AIMl “Software SerirdPort Implemented with the
relate the critical edges of control and input signals to
PCA”
7. AP-425 “Small DC Motor Control”
8. The appropriatedata sheet.

5-43
87C51GBHardware 6
Description
 87C51GB Hardware Description

CONTENTS PAGE CONTENTS PAGE

1.(&NTtTt::UCTION TO THE 7.OF+::?RAMMABLE COUNTER

................................................ 6-3 .................................................. 6-23
7.1 PCA Timer/Counter........................ 6-24
2.0 MEMORY ORGANIZATION .................6-3
Readingthe PCA Timer .................. 6-26
2.1 ProgramMemory............................. 6-3
7.2 Compare/CaptureModules............ 6-26
2.2 Data Memory................................... 6-3
7.3 PCA CaptureMode........................ 6-27
3.0 SPECIAL FUNCTION 7.4 SoftwareTimer Mode..................... 6-29
REGISTERS ........................................... 6-5
7.5 High Speed OutputMode .............. 6-30
4.0 I/o PORTS............................................6-8 7.6 WatchdogTimer Mode................... 6-30
4.1 1/0 Configurations............................ 6-8 7.7 PulseWidth ModulatorMode......... 6-31
4.2 Writingto a Port............................... 6-9
8.0 SERIAL PORT.................................... 6-33
4.3 Port Loadingand Interfacing.......... 6-10
8.1 FramingErrorDetection................ 6-35
4.4 Read-Modify-WriteInstructions ...... 6-10
8.2 MultiprocessorCommunications....8-35
4.5 AccessingExternalMemory........... 6-11
8.3 AutomaticAddressRecognition ..... 6-36
5.0 TIMEWCOUNTERS ........................... 6-13 8.4 Baud Rates.................................... 6-36
5.1 llmer Oand Timer 1....................... 6-13 8.~:irn:r 1 to Generate Baud
Mode O............................................ 6-14 ................................................ 6-36
Mode 1 ............................................ 6-15 8.\:tm:r 2 to Generate Baud
................................................ 6-37
Mode 2 ............................................ 6-16
Mode 3.... ........................................ 6-16 9.0 SERIAL EXPANSION PORT.............. 6-38
5.2 Timer 2.... ....................................... 6-17 9.1 ProgrammableModesand Clock
Options.............................................6-39
Timer 2 CaptureMode .................... 6-18
9.2 SEP Transmissionor Reception.... 6-40
Timer 2 Auto-ReloadMode............. 6-18
5.3 ProgrammableClockOut .............. 6-20 IOJIJ##DWARE WATCHDOG
................................................... 6-40
6.0 A/D CONVERTER .............................. 6-21 10.1 Usingthe WDT ............................ 6-40
6.1 A/D Special FunctionRegisters..... 6-21 10.2 WDT DuringPower Downand
6.2 A/D ComparisonMode .................. 6-22 Idle ................................................... 640
6.3 ND Trigger Mode......................,.... 6-22 11.0 OSCILLATOR FAIL DETECT........... 6-40
6.4 A/D Input Modes............................ 6-22 11.1 OFD DuringPowerDown............. 6-41
6.5 Usingthe A/D with Fewer than 8
Inputs............................................... 6-22
6.6 PJDin Power Down........................ 6-23

&l
CONTENTS PAGE CONTENTS PAGE

12.0 INTERRUPTS................................... 6-41 14.0 POWER-SAVINGMODES ...............6-49

12.1 ExternalInterrupts....................... 6-41 14.1 IdleMode..................................... 6-51
12.2 Timer Interrupts............................ 6-43 14.2 PowerDown Mode ...................... 6-51
12.3 PCA Interrupt............................... 643 14.3 PowerOff Flag............................. 6-51
12.4 Serial Port Interrupt..................... 643
15.0 EPROM/OTP PROGRAMMING ....... 6-52
12.5 InterruptEnable........................... 643
15.1 ProgramMemory Lock................ 6-52
12.6 InterruptPriorities........................ 6-45
ProgramLockBits............................ 6-52
12.7 InterruptProcessing..................... 6-47
12.8 InterruptResponseTime ............. 6-48 16.0 ONCE MODE ................................... 6-52

13.0 RESET.............................................. 6-49 17.0 ON-CHIP OSCILLATOR..,................ 6-52

13.1 Power-OnReset .......................... 6-49 18.0 CPU TIMING .................................... 6-54

62
int& 87C51GB HARDWARE DESCRIPTION

1.0 INTRODUCTION TO THE . Interrupt Structure with

8XC51GB — 15interrupt sourcea
— Four priority levels
The 8XC51GBis a highly integrated 8-bit microcm-
● Power-SavingModes
troller basedon the MCS@-51architecture. As a mem-
ber of the MCS-51family, the 8XC51GBis optimizcd — Idle Mode
for control applications.Its key features are an analog — PowerDown Mode
to digitalconverterand two prograrnmable counter ar-
rays (PC@ capable of measuringand generatingpulse The table belowsummarizesthe product names of the
informationon ten 1/0 pins. Also includedare an en- various 8XC51GB products currently available.
hancedserialport for multi-processor communications, Throughoutthis docmnen~the productswill generally
a serial expansion port, hardware watchdogtimer, os- be referredto as the 8XC51GB.Figure 1showsa func-
cillatorfail detection,an up/down timer/counter and a tional blockdiagram of the 8XC51GB.
programlockschemefor the on-chipprogrammemory.
Since the 8XC51GBis CHMOS, it has two software
selectablereducedpower modes:Idle Mode and Power
DownMode.

The 8XC51GBused the standard 8051instruction set

and is functionally compatible with the existing
MCS-51familyof products.

This documentpresents a comprehensivedescriptionof 2.0 MEMORY ORGANIZATION

the on-chiphardware features of the 8XC51GB.It be-
ginswith a discussionof howthe memoryis organized, All MCS-51deviceshave a separate address space for
followedby the instructionset, and then discusseseach ProgramMemoryand Data Memory.The logicalsepa-
of the peripheralslisted below. ration of Program and Data Memoryallowsthe Data
● Six8-bitBidirectionalParallel Ports
Memoryto be accessedby 8-bitaddresses,whichcan be
more quicklystored and manipulatedby an 8-bitCPU.
● Three 16-bitTimer/Counters with Nevertheless id-bit Data Memory addressescan also
— One Up/Down Timer/Counter be generated through the DPTR register. Up to
— Programmable Clock Output 64 Kbyteseach of externalProgramand Data Memory
can be addressed.
. Analogto Digital converter with
— 8 channels
— 8-bitresolution 2.1 Program Memory
— comparemode Program Memory can only be read, not written to.
● Two Programmable Counter Arrays with There can be up to 64 Kbytes of Program Memory.
The read strobe for external Program Memory is the
— Compare/Capture signalFSEN(ProgramStoreEnable).PSENis not acti-
— SoftwareTimer vated for internal program fetches.
— High speed output
If the ~ (ExternalAwes) pin is eomected to V~, all
— Pulse Width Modulator programfetches are directed to external memory.For
— WatchdogTimer (PCA only) the ROMISSSdevices,all~rogram fetches must be to
. Full-DuplexProgranunable SerialPort with external memory. If the EA pin is connectedto VCC,
— Framing Error Detection then program fetches greater than 8K are to external
addressesforthe 8XC51GBproducts
— AutomaticAddress Recognition
● SerialExpansionPort On the 87C51GBwith = connectedto VCGprogram
— four programmablemcdes fetches to addresses OOOOH
throughIFFFH are to in-
ternal ROMyand fetches to addresses2(OOHthrough
— four selectablefrequencies FFFFH are to external memory.
. Hardware WatchdogTimer
● Reset
2.2 Date Memory
— asynchronous
— activelow The 8XC51GBimplements 256 bytes of on-chip data
RAM. The memoryspace is dividedinto three blocks,
● OscillatorFail Detection

6-3
i~o 87C51GB HARDWARE DESCRIPTION

...- .
PO.O-PO.7 P2.O-P2.7

“%. --------
.... -.J~l]JIJ\-J[m;.------------------,
I
,
I

1 1
1 I
, I
I 1
* s
1 I
* *
I ,
I I
I #
1
, I
I
1
1
1
I
I 8
1 #
I ,
1
1
I w’” PSA.1
Zr#-’ ‘I “E’
‘“” ‘I 11’ 3MALP0RTS
Ill ‘c
INCSEM3NT2S
~ 1
I
I
*

,—

~ ~
I
rE-w-=J=/fRj -A’”
A A
c-c
Pt,O-P!.7 P5.O-PS7 P4.O-P4.7 P3.O-PS.7 H N
* 0 7

270S97-1
-,----- . .--,?.-- =,--,. m:--—-
rlgure 1. ufva IUD DnJGKumgram

which are generally referred to as the Lower 128,the Whenan instructionaccessesan internal locationabove
Upper 128,and SFR space.The Upper 128bytesoccu- address 7FH, the CPU knowswhether the accessis to
py a paralleladdressspacetotheSpecialFunctionReg- the upper128bytesof dataRAMor to SFRspaceby
iaters. That means they have the same addresaesjbut the addressingmode used in the instruction. Instmc-
they are physicallyseparate from SFRspace. tionsthat use direct addressingaccessSFRspace.For
example,
The Lower 128 bytes of RAM are present in all
MCS-51devices.All of the bytes in the Lower 128can MOVOAOH,data
be accessedby either director indirect addressing.The
lowest32byteaare groupedinto 4 banksof 8 registers. acceaaesthe SFR at locationOAOH(which is P2). In-
Program instructions call out these regiaters as RO stmctions that w indirectaddressingaeeessthe upper
through R7. Two bits in the Program Status Word 128bytes of data RAM. For example,
(PSW)selectwhich register bank is in use. This allows
more Mlcient use of cede space, since register instmc- NOV@RO, data
tions are shorter than instructions that use direct ad-
dressing.

6-4
i~. 87C51GB HARDWARE DESCRIPTION

where ROcontainsOAOH,acceaseathe data byte at ad- Iatches, timen peripheralcontrols, etc. These registers
dress OAOH,rather than P2 (whoseaddress is OAOH). can only be accessedby direct addressing.Sixteenad-
Note that stack operationsare examplesof indirect ad- dressesin SFRspaceare both byte-and bit-addressable.
dressing,so the upper 128byka of data RAM are avail- The bit-addressableSFRSare those whoseaddress ends
able as stack space. in OOOB. The bit addresseain this area are 80Hthrough
OFFH.

3.0 SPECIAL FUNCTION REGISTERS Not all of the addressesare occupied.Unoccupiedad-

dressesare not implementedon the chip. Read acceases
A map of the on-chipmesnoryarea cafled by the SFR to these addreaseswilf in general return random &@
(SpecialFunctionRegister) space is shownin Table 1. and write accesseswill have no effect.
Special Function Registers (SFRS) include the Port

Table1.SFRMalminaandReeetValues
P5 CH CCAPOH CCAPIH CCAP2H CCAP3H CCAP4H
F8 FF
00000000 00000000 xXxxXXxX Xxxxxxxx xxxxWxx xmxxxxx xXxxXXxX
●B AD7
FO
00000000 00000000 z::: ‘7
CICON CL CCAPOL CCAP1L CCAP2L CCAP3L CCAP4L
E8 EF
+Oooooooo00000000 Xxxxxxxx Mxxxxxx Xxxxxxxx Xxxxxxx
*ACC ADO
EO a E7
Oooooooo 00000000
CCON I CMOD CCAPMO CCAPM1 CCAPM2 CCAPM3 CCAPM4
D8 DF
Ooxoooool
Ooxxxooo Xooooooo XoooooooXooooooo XoooooooXooooooo
*PSW AD5
‘0 ooom 00000000 )%$$%0 ‘7
T2CON T2MOD RCAP2L RCAP2H TL2 TH2
CF
m 00000000Xxxxxxoo 00000000 00000000 00000000 00000000
P4 AD4
co Oooooooo 00000000 ;%%::0 0:::;0 C7
●IP SADEN CICAPOH CICAPIH C1CAP2H C1CAP3H C1CAP4H CH1
‘8 Xooooooo00000000 Xxxxxxxx Xxxxxxxx Xxxxxxxx Xxxxxxx xxxxxxM 00000000 ‘F
*P3 AD3 IPAH IPA IPH B7
BO
11111111 00000000 00000000 00000000 Xooooooo
*IE SADDR CICAPOL CICAP1L C1CAP2L C1CAP3L C1CAP4L
‘8 00000000 00000000 Xxxxxxxx Xwxxxxx X)wuxxx Xxxxxxxx Xxxxxxxx 00%”00 ‘F
●P2 AD2 OSCR WDTRST IEA
‘0 00000000 00000000 XxxXXxXoXxxxmxx 00000000 ‘7
*SCON “SBUF CICAPMO CICAPM1 C1CAPM2 C1CAPM3 C1CAPM4 CIMOD
98 00000000XXxxmxx XoooooooXooooooo Xooooooo XoooooooXoooooooXxxxoooo ‘F
●P1 AD1
90
00000000 00000000 X)%Hoo ‘7
*TCON ●TMOD *TLO “TL1 *THO “THI
8F
88 00000000 Oooooooo00000000 00000000 00000000 00000000
●PO ●SP “DPL ●DPH ADO
80 11111111 00000111 00000000 00000000 00000000 X2::: 87

- = Foundinthe 8051core(see8051Hardware
DescriptionforexplanationsoftheseSFRS).
●* = Seedescription
ofPCONSFR.BitPCON.4isnotaffected byreset.
X = Undefined.

8-5
in~. 87C51GB HARDWARE DESCRIPTION

User software should not write 1’s to these unimple- Ports Oto 5 Registers: PO,Pl, P2, P3, P4, and P5 are
mented locations, since they may be used in future the SFR latches of Ports Othrough 5 respectively.
MCS-51productsto invokenew features. In that case
the reset or inactivevalues of the new bits will always Timer Registers: Regista pairs (’IWO,TLO), (THl,
be O,and their activevalues will be 1. TL1) and (TH2, TL2) are the id-bit count registers for
Timer/Counters O, 1, and 2 respectively.Control and
The functions of the SFRS sre outlined below. More statusbits are containedin registersTCON and TMOD
informationon the w of apecificSFRSfor each periph- for Timers O and 1 and in registers T2CON and
eral is includedin the descriptionof that
peripheral. T2MOD for Timer 2. The register pair (RCAP2H,
RCAF2L)are the capture/reload registers for Timer 2
AccumsdatoRACC is the Accumulator register. The in id-bit capture mode or 16-bitauto-reloadmode.
mnemonics for Accumulator-Specific instructions,
however,refer to the Accmrmdatoraimplyas A. Prosrsrnmsble auntar AITSY ~CA =d PCA1)Re@-
tera: The id-bit PCA and PCA1timer/counters consist
B Register: The B register is used during multiplyand of register CH (CH1) and CL (CL1).Registers CCON
divideoperations.For other instructionsit can be treat- (CICON) and CMOD (CIMOD) contain the control
ed as another scratch pad register. and status bits for the PCA (and PCA1). The
CCAPMn (n = O, 1, 2, 3, or 4) and the CICAPMn
StackPointaE The Stack Pointer Register is 8 bits registerscontrol the modefor each of the five PCA and
wide. It is incrementedbefore data is stored during the five PCA1 modules.The register pairs (CCAPnH,
PUSH and CALL execution. The stack may reside CCAPnL and CICAPnH, CICAPnL) are the lti-bit
anywherein on-chipR4M. On reset, the StackPointer compare/capture registers for each PCA and PCA1
is initializedto 07H causing the stack ta beginat loca- module.
tion 08H.
SerisdPort Registers:The SerialData Buffer,SBUF,is
Data PoisItec The Data Pointer (DPTR) consists of a actually two separate registers:a transmit buffer and a
high byte (DPH) and a low byte (DPL). Its intended receivebufferregister.Whendata is movedto SBUF,it
fimction is to hold a 16-bitaddress,but it may be ma- comesfrom the rexive buffer.RegisterSCONcontaina
nipulated as a Id-bit register or as two independent the control and status bits for the SerialPort. Registers
8-bit registers. SADDRand SADENare usedto definethe Oiven and
the Broadcast addreaaes for the Automatic Address
Rogrsun Status Word:The PSWregister containspro- Recognitionfeature.
- ststus informationas detailed in Table 2.

Psw Address= ODOH ResetValue= 0000OOOOB

BitAddressable
CY ] AC FO RS1 RSO Ov — P
Bit 7 6 5 4 3 2 1 0
Symbol Function

CY Carryflag.
AC Auxiliary
Carryflag.(ForBCDOperations)
FlagO.(Availabletotheuserforgeneralpurposes).
& Registerbankselectbit1.
RSO Registerbankselectbito.

RS1 RSO WorkingRegisterBankandAddress

o 0 BankO (OOH-07H)
01 Bank1 (08H-OFH)
1 0 Bank2 (1OH-17H)
1 1 Bank3 (18H-l FH)
Ov Overflow flag.
— Userdefinable flag.
P Parityflag.Set/clearedbyhardware eachinstruction
cycletoindicate
anodd/evennumber
of“one”bitsintheAccumulator, i.e.,evenparity.

6-6
i~. 87C51GB HARDWARE DESCRIPTION

SerialExpansionPort Registers:The Serial Expansion channelsOthrough 7 respectively.The register ACMP

Port is controlled through the register SEPCON. contains the results of the A/D comparison feature.
SEPDAT contains data for the Serial ExpansionPort ACON is the control registerfor A/D conversions.
and SEPSTATis used to monitorits status.
PowerControlR- PCONcontrolsthe PowerRe-
Interrupt Registers: The individual interrupt enable duction Modes, Idle and PowerDown.
bits are in the IE and IEA registers.One of four priori-
ty levelscan be selectedfor eachinterrupt usingthe W, Oscillator Fail Detest Register:The OSCR register is
IPH, IPA and IPAH registers.The EXICON register used both to monitor the status of the OPD circuitry
controls the selection of the activation polarity for ex- and to disable the feature.
temal interrupts two and three.
Watchdog Timer Register: The WatchDog Timer
Analos to Digital Converter Resisters: The results of ReSeT(WDTRST) retister is used to keerrthe watch-
A/D ~nvers~ons are placed in-registers ADO, ADl, dog timer from peno&ally resettingthe part.
AD2, AD3, AD4, AD5, AD6, and AD7 for analog

1 Me 3. AlternatePortFunotions
Port Pin AlternateFunction
Po.o/ADo-Po.7/AD7 Multiplexed
ByteofAddreee/Data
forexternalmemow.
P1.O/T2 Timer2 External
Clockinput/Clockout
P1.1/T2EX Timer2 Reload/Capture/Direction
Control
P1.2/ECl PCAExternalClockInput
P1.3/CEXO PCAModuleOCaptureInput,Compare/PWM Output
PI.41CEXI PCAModule1 CaptureInput,Compare/PWM Output
P1.5/CEX2 PCAModule2 CaptureInput,Compare/PWM Output
P1.61CEX3 PCAModule3 CaptureInput,Compare/PWM Output
P1.7/CEX4 PCAModule4 CaDtureInr.wt.comDare/pWM (lttmt
P2.O/A8-P2.71A15 HighByteofAddress
forExternalMemcrry
P3.o/RxD SerialPortInput
P3.1/TXD SerialPortOutput
P3.2/~ ExternalInterrupt
O
P3.3/m ExternalInterrupt
1
P3.4fT0 17mer0External ClockInput
P3.5/Tl Timer1 ExternalClockInput
P3.6/~ WriteStrobeforExternalMemory
P3.7/m ReadStrobeforExternalMemory
P4.OISEPCLK ClockSourceforSEP
P4.IASEPDAT Date1/0 forSEP
P4.2/ECll PCA1ExternalClockInput
P4.3/cl Exo PCA1ModuleO,CaptureInput,Compare/PWM Output
P4.4/cl Exl PCA1Module1,CaptureInput,Compare/PWM Output
P4.5/cl Ex2 PCA1Module2, CaptureInput,Compare/PWM Output
P4.6/ClEX3 PCA1Module3, CaptureInput,Compare/PWMOutput
P4.71CIEX4 PCAI Module4, CaptureInOut.ChrIIDadF%’Vkf Outout
P5.2/lNT2 ExternalInterrupt
2
P5.3/lNT3 ExternalInterrupt
3
P5.4/lNT4 ExternalInterrupt
4
P5.5/lNT5 Externalinterrupt
5
P5.6/lNT6 ExternalInterrupt
6

NOTE
Thealternatefunctionsc-anonlybe activatedifthe correspondingbitIatehinthe IMrlSFRcontainsa 1. Otherwisethe DOrt
pinwillnotgo high.

6-7
i~. 87C51GB HARDWARE DESCRIPTION

4.0 1/0 PORTS 4.1 1/0 Configurations

All six ports in the 8XC51GBare bidirectional.Each Functional diagrams of a bit latch end 1/0 bufRwin
consists of a latch (Special Frmction Register PO each of the four ports are shownin Figure 2.
through P5), output driver end an input buffer.All the
ports, except for Port O,have SchmittTriggerinputs. The bit latch (one bit in the port’s SFR) is represented
as a TypeD tliptlop, which clocksin a valuefrom the
The output driversof Ports Oend 2, end the input buff- internal bus in response to a “write to latch” signal
ers of Port O,are used in acceses to external memory. from the CPU. The Q output of the flip-flopis placed
In this application,Port Ooutputs the low byte of the on the internal bus in responseto a “read latch” signaf
external memory address, time-multiplexedwith the from the CPU. The levelof the port pin itself is placed
byte beingwritten or read. Port 2 outputs the high byte on the internal bus in responseto a “read pin” signal
of the external memoryaddresswhenthe address is 16 from the CPU. Someinstructionsthat read a port acti-
bitswide. Otherwise the Port 2 pins continue to emit vate the “read latch” signal, end others activate the
the P2 SFR content. “read pin” signal. Those that read the latch are the
Read-Modify-Writeinstructions.
All thePort 1, Port 3, Port4 endmostofPort5 pins
aremulti-functional. T’heyarenotonly port pins, but The outputdriversof Ports Oand 2 are switchableto an
also serve the functions of various special features as internal ADDRESSand ADDRESS/DATAbus by an
shown in Table 3. internal control signal for use in external memory ae-
ceses. During external memory accease$the P2 SFR

ADDRIDATA ALTERNATE
Vcc OUTPUT

ill%““-:D*
CONTROL FUNCTION

uPe.x
pm

a
.
IN 1. BUS
Mux D ~x au I
WRITE LATCH
TO CL F
LATCH

270897-2
ALTERNATE
tl. PortII Bit INPUT
FUNCTION
270897-3
B. Port 1,3,4, or 5 Bit
ADDR
Vcc
REAO CONTROL
LATCH

INT.BuS
WRITE
To d - CL G
LATCH

READ
PIN
270897-4
C. Port2 Bit
%eaFigure
4 fordetailsofthe internalPUIIUP.
Figure2. 8XC51GBPortBitLatchesand1/() Buffers

6-8
i~. 87C51GB HARDWARE DESCRIPTION

remains unchanged,
but the POSF’Rgets 1s written to port lines are open drain. Writing a 1 to the bit latch
it. leavesboth output FBTs off, which floats the pin and
allowsit to be usedas a high-impedanceinput. Because
If a PI through P5 latch containsa 1, then the output Ports 1 through 5 have freed internal pullupsthey are
level is controlledby the signal labeled“alternate out- sometirneacalled “quasi-bidirectional”porta.
put function.” The pin level is alwaysavailableto the
pin’salternate input function,if any. When configured as inputs they pull high and will
source current (IIL in the data sheets) whenexternally
Ports 1 through 5 have internal pullupa. Port O has pulled low. Port O, on the other hand, is considered
opendrain outputs.Each 1/0 line canbe independently “true” bidirectional,because it floats when configured
usedas an input or an output (Ports Oand 2 maynot be as an input.
used as general purpose 3/0 when being used as the
ADDRBWDATA BUS).To be used as an inpuLthe The latchesfor ports Oand 3 have 1swrittento them by
port bit latch must contain a 1, which turns off the the reset function. If a O is subsequentlywritten to a
output driver PET. On Ports I through 5 the pin is port latch, it can be reconfiguredas an input by writing
pulled high by the internal pullup, but can be pulled a 1 to it.
low by an external source.

PI, P2, P4, and P5 reset to a low state. Whilein reset 4.2 Writing to a Port
these pins can sink large amounts of current. If these
ports are to be used as inputs and externally driven In theexecution ofaninstruction thatchangea theval-
high whilein reset, the user shouldbe awareof possible uein a portlatch,thenewvaluearrivesat thelatch
contention.A simple solution is to use open collector duringState6,Phase 2 ofthefti cycleoftheinstruc-
interfaces with these port pins or to bufferthe inputs. tion. Howewr, port latch= are sampledby their output
bufkrs only during Phase 1 of any clockperiod. (Dur-
Port Odiffersfrom the other ports in not havinginter- ing Phase 2 the output buffer holds the value it saw
nal puliups.The pullup FET in the POoutput driver is during the previousPhase 1). Consequently,the new
used only whenthe port is emitting 1sduring external value in the port latch won’t actually appear at the
memory acceses. otherwise the pullup FET is off. output pin un~ilthe next Phaac 1,which~ be at SIPI
ConsequentlyPO lines that are being used as output of the next machinecycle. Refer to Figure 3.

SIAIE4 STA7E
.5 STATE
6 SIAIE1 STATE
2 SIAIE3 STATE
4 STATE
5
lPllmlmlmlmlnlPl lnlml*Imlmlmlml Pllml
XTAL1:

VI-.
PO.P1,PZ,PS,P4,P6 PO,P1,PZ,P3.P4,P6
wu?a aAnPLEo:
=

UovPORT,SRC: OLOOATA NEW

OATA
I

iiiEF~+ +RXDPINSANIUO RXOSAMPUO+ k-

270S97-5

Figure3. PortOperation

6-9
i~. 87C51GB HARDWARE DESCRIPTION

For more informationon internal timingsrefer to the 4.3 Port Loading and Interfacing
CPU Timingsection.
Theoutputbuffers of Ports1through5 caneachsink
If the change requirea a o-t-l transition in Ports 1 at leasttheamountof currentspecitied byVoL in the
through 5, an additional pullup is turned on during dataSheet. TheseportPiIIScanbedliV~ by q)cn-col-
SIPI and S1P2 of the cycle in which the transition lector and open-drain outputs slthoug3 O-to-1tran-
occurs. This is done to increase the transition speed. sitions will not be fast since there is little current pull-
The extra pullup can source about 100times the cur- ing the pin up. An input O turns off pollup pFET2,
rent that the normal pullup can. The internal pullups leavingonly the very weak pullup pFET2 to drive the
are field-effecttransistors, not linearreaistors.The pull- transition.
UParrangementsare shown in Figure 4.
In external bns mode, Port Ooutput butkrs can each
The ptdlup consists of three pFETs. Note that an sink the amount of current specitiedat the test condi-
n-channelF13T(nFET) is turned on whena logical1 is tionsfor VOL1in the data sheet. However,as port pins
applied to its gate, and is turned off whena logicalOis they require external pullups to be able to drive any
applied to its gate. A p-channel FET @ET) is the inputs.
opposite:it is on when its gate seesa O,and offwhenits
gate seesa 1. See the latest revision of the data sheet for design-in
information.
pFET 1 is the transistor that is turned on for 2 oscilla-
tor periodsafter a O-to-1transition in the port latch. A
1 at the port pin turns on pFET3 (a weak pullup), 4.4 Read-Modify-Write Instructions
through the inverter. This inverter and pFET form a
latch whichhold the 1. Someinstructions thatreada portreadthelatchand
others read the pin. Whichonesdo which?The instruc-
If the pin is emitting a 1, a negativeglitch on the pin tionsthat read the latch rather than the pin are the ones
from someexternalsource can turn offpFET2,causing that read a VSJU?possiblychangeit, andthenrewriteit
the pin to go into a float state. pFET2 is a very weak to the latch. Theae are called “read-modify-write”
pullup whichis on wheneverthe nFET is off, in tradi- instructions. Listed on the following page, are the
tional CMOSstyle. It’s only about Ylothe strength of read-modfjwrite instructions. When the destination
pFET2. Its function is to restore a 1 to the pin in the
event the pin had a 1 and lost it to a glitch.

v~~ v~~ v~~

PI P2 P3

,, Iil ~ POUT
PIN
6 D
n I’
FROMPORT
LATCH

INPUT
DATA

READ
PORTPIN
270897-6

NOTE:
CHMOSCotiiguration.pFET1isturned
onfor2 OSC. periods afterU msdesa O-to-1transition.During
thistime,pFET1
alsoturnsonpFET3 through
theinverter
toforma latchwhkhholds the1.pFET2 iaalsoon.Port2 issimilar except
thatitholds
thestrong
pullup
onwhileemittingIs that are addressbits.(Seetext,“AcceaaingExternalMemory”.)
,
Figure4. Ports1,3,4, and5 internalPullupConfiguration

6-10
intd. 87C51GB HARDWARE DESCRIPTION

operand is a port, or a port bit, these instructionsread Theyread the port bytejall 8 bitsj modifythe addressed
the latch rather than the pin: bit, then write the new byte back to the latch.
ANL (logicalAND, e.g. ANL PI, A)
The reason that read-modify-writeinstructions are di-
ORL (logical011 e.g. ORL P2, A) rected to the latch rather than the pin is to avoid a
XRL (logicalEX-OK e.g. XRL P3, A) possible misinterpretation of the voltage level at the
JBc (jumpifbit = 1and clear bit, e.g.JBC pin. For example,a port bit might be used to drive the
P1.1, LABEL) base of a transistor. Whena 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same
CPL (complementbit, e.g. CPL P3.0) port bit at the pin rather than the latch, it will read the
INC (increment,e.g. INC P2) base voltage of the transistor and interpret it as a O.
DEC (decrernen~e.g. DEC P2) Reading the latch rather than the pin will return the
correct value of 1.
DJNZ (decrement and jump if not zero, e.g.
DJNZ P3, LABEL)
MOVPX.Y, C (movecarry bit to bit Y of Port X) 4.5 Accesaing External Memory
CLR PX.Y (clear bit Y of Port X)
Accesses toexternal memory areoftwotypes:am—ewes
SETBPX.Y (set bit Y of Port X) to external Program Memory and amesses to external
Data Merno~Accessra to external Program Memory
It is not obviousthat the last three instructions in this use signal PSEN (program store enable) as the read
list are read-modify-writeinstructions, but they are. strobe. Accessesto external Data Memory use = or
~ (alternate functionsof P3.7 and P3.6)to strobe the
memory.Refer to Figures 5 through 7.

STATS
1 STATE
2 STATS
3 STATS
4 STAIES STATE
6 STATS
1 STATS
2
IPIIP21PIIP21PIIPSIPIIP21PIIP21PIIF21PIIP21PIIml
XTAL1:

I 1 I I i 1

REii: I
OATA OATA DATA
--l ~sAuPLso k-aAuPLEo

PO: I
I I
~ ~ 1A
I I
~ ~ I
L
PCL
OUT
I

P2:
I PCHour I
PCHOUT I PCHOUT
,
270697-7

Figure5. ExternalProgramMemoryFetcttaa

6-11
i~e 87C51GB HARDWARE DESCRIPTION

STATS4 STATS5 STAT56 S7AT51 STATS2 STAT53 STAT54 STATE

5
IPllmlPllmlmlml MlnlPllmlPllnlm lnlnlnl
XTALI:

‘“’ ~

~D: PCLOUTIP
1 PaoGlwNMEMoRY
OATASANPLSO ISEXTSRNAL

DPL~Rl PLOAT
m: 1
i~ll

P3: PCHOR PCHOR

DPHORP3SPROUT
P3SPR Psalm
270S97-8

Figure 6. External Data MemoryReadCycie

SIAIE 4 STAIE 5 STA756 SIAIE 1 S7ATS2 STATS3 STATS4 STATS5

IPllJPtlPzlPl ,nlPl,nlnlmlmim lnlmlm IP31
xrALl:

‘“’ ~

*: PCLOUTIP
PuoaRAMM5moRY
lsE31EnML

w:
LIDPLORRI
DATA
OUT

P3 PcHon Paion
oP140nP3smou’f
P3sFa PssFn
270S97-9

Figure7. ExternalDataMemoryWriteCycle

6-12
i~e 87C51GB HARDWARE DESCRIPTION

Fetches from external Program Memoryalways use a functionand may not be used for generalpurpose I/O.
16-bitaddreas.Accessesto external Data Memory can During external program fetches they output the high
use either a 16-bitaddress (MOVX @ DPTR) or an byte of the PC with the Port 2 drivers usingthe strong
8-bit address (MOVX@Ri). pullupsto emit bits that are 1s.

Whenevera l~bit addreasis used,the high byte of the

addreas corneaout on Port Z where it is held for the 5.0 TIMER/COUNTERS
duration of the read or wsite cycle.The Port 2 drivers
use the strong pullups during the entire time that they The8XC51GBhas three Id-bit Timer/Counters: Tim-
are emittingaddressbits that are 1s.This occurs when er O,Timer 1, and Timer 2. Each consistsof two 8-bit
the MOVX @ DPTR instruction is executed. During registers:THx and TLx with x = O, 1, or 2. All three
this time the Port 2 latch (the SpecialFunction Regis- can be configuredto operate either as timers or event
ter) doeanot haveto contain 1s,and the contentsof the calnters.
Port 2 SFR are not moditkd. If the external memory
cycle is not immediatelyfollowedby another external In the Timer fimction,the TLx register is incremented
memory cycle, the undisturbedcontents of the Port 2 everymachinecycle.Thus, youcan think of it as cOunt-
SFR will reappear in the next cycle. ingmachinecycles.Sincea machinecycleconsistsof 12
oscillatorperioda,the count rate is ~2 of the oscillator
If an 8-bit address is being used (MOVX @ Ri), the frequency.
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. In this case, In the Counter function, the register is incremented in
Port 2 pins can be used to pagethe externaldata mern- responseto a l-to-Otransition at its correspondingex-
Ory. ternal input pin: TO,Tl, or T2. In this function, the
externalinput is sampledduringS5P2of everymachine
In either case,the lowbyteof the addressis tirne-muM- cycle.Whenthe samplesshowa highin onecycle and a
plexedwith the &ta byte on Port O.The ADDRESS/ low in the next cycle, the count is incremented. The
DATA signal drives both FETs in the Port O output new count value appears in the register during S3P1of
buffera.Thus, in externalbus modethe Port Opins are the cyclefollowingthe one in whichthe transition was
not open-drain outputs and do not require extemrd detected Sinceit takes 2 machine cycles(24 oscillator
psdlupa. The ALE (Address Latch Enable) signal periods)to recognizea l-to-Otransition, the maximum
should be used to capture the addressbyte into an ex- count rate is V24of the oscillatorfrequency.There ue
ternal latch. The address byte is valid at the negative no restrictions on the duty cycle of the external input
transition of ALE. Then, in a write cycle,the data byte signaLbut to ensure that a given levet is sampled at
to be written appears on Port Ojust beforeWR is acti- least once before it changes, it should be held for at
vated, and remainsthere until after ~ is deactivated. least one full machine cycle.
In a read cycle,the incominf@te is acceptedat Port O
just beforethe read strobe @D) is deactivated. Timer Oand Timer 1 have four operatingmodes:
Mtie O: 13-bittimer
During any accessto externsdmemory,the CPU writes Mode1: id-bit timer
OFFHto the Port Olatch (the SpecialFunction Regis-
ter), thus obliterating the information in the Port O Mode2: 8-bit auto-reloadtimer
SFR. Also, a MOVPOinstructionmust not take place Mode3: Timer Oas two separate 8-bit timers
during external memory awesses. If the user writes to
Port Oduring an external memoryfetch, the incoming Also,its possibleto use Timer 1 to generatebaud rates
code byte is corrupted.Therefore,do not vnite to Port
Oif external program memoryis used. Timer 2 has three modesof operation:
External Program MernoIYis accessedunder two con- Timer 2 Capture
ditions: Timer 2 Auto-Reload(up or down counting),and
1. Wheneversignal= is bigh, or Timer 2 as a Baud Rate Generator
2. Wheneverthe programcounter(PC) containsan ad-
dress greater than IFFFH (8K).
5.1 Timer O and Timer 1
This requiresthat the ROMlessversionshave= wired TheTimer/Gunter fimctionis selectedby control bits
to VgSto enablethe lower SK of programbytes to be C—TXin TMOD (Table 4). These two Timer/Coun-
fetched from external memory. ters have four operating modes, which are selected by
bit-pairs(MIL MOX)also in TMOD. Mode O,Mode 1,
When the CPU is executingout of external Program and Mode 2 are the same for both Timer/Counters.
Memory,all 8 bits of Port 2 are dedicatedto an output Mode 3 operation is diKerentfor the two timers.

6-13
i~. 87C51GB HARDWARE DESCRIPTION

Table4. TMOD:Timer/CounterModeControlRedeter

TMOD Address= 89H ResetValue= 0000OOOOB

NotBitAddressable
TIMER1 I TIMERO
I GATE I C/7 [ Ml I MO I GATEI C/~ I Ml I MO I
Bit 7 6 5 4 3 2 1 0

Symbol Funotion
GATE Gatingcontrolwhenset.Timer/Counter Oor1 isenabledonlywhileINTOor~ pin
ishighandTROorTRl controlpinisset.Whencleared,17merOor1 isenabled
whenever TROorTRl controlbitisset.
c/T TimerorCounterSelector.ClearforTimeroperation(inputfrominternalsystem
clock).SetforCounteroperation
(inputfromTOorT1 inputpin).
Ml MO OperatingMode
00 8-bitTimer/Counter.THxwithTLxas5-bitpresceler.
01 16-bitTimer/Counter.THxandTLxarecascaded; thereisnoprescaler.
10 8-bitauto-reload
Timer/Counter.
THxholdsa valuewhichistobereloadedintoTLx
eachtimeitoverflowa.
11 (TimerO)TLOisan8-bitTimer/Counter controlled
bythestandard TimerOcontrol
bite.THOisan8-bittimeronlycontrolled
byTimer1 controlbits.
11 (Timer1)Timer/Counter stopped.

MODEO Asthecount rolls over from all 1sto all 0s, it sets the
timer interrupt flag TFUor TF1. The countedinput is
EitherTimer Oor Timer 1in ModeOis an 8-bitcounter enabledto the timer whenTROor TRl = 1,and either
with a divid&by-32preaesler. In this mb the Timer GATEx = Oor INTx pin = 1. (8ettingGATEx = 1
regiSter is cotilgur~ as a 13-bit register. Figure 8 allows the Timer to & controlled by-external input
showsthe Mode Ooperationfor either timer. ~ pin, to facilitate pulse width measurements).

I Osc

1 <,1 1
INTERRUPT

1 ICO!TROLI”TL’ !(”=)HOWWX F

270897-10

Figure8. Timer/CounterOor 1 inMode1%13-BitCounter

6-14
i~. 87C51GB HARDWARE DESCRIPTION

TRxand TFx are control bits in the SFR TCON. The MODE1
GATExbitsare in TMOD. There are two different
GATE bits: one for Timer 1 (TMOD.7)and one for Mode 1 is the same as Mode 0, exeept that the Timer
Timer O(TMOD.3). registerusesall Id-bits.In this mode,THx and TLx are
cascaded;there is no presesler. Refer to Figure 9.
The 13-bitregister consistsof all 8 bits of THx and the
lower5 bits of TLx. The upper 3 bits of TLx are inde As the count rolls over from all 1s to all 0s, it sets the
terminate and should be imored. %ttin~ the run tlaiz timer interrupt fhz TFOor TF1. The countedinput is
(TRx)does not clear these-registers. - - enabledto th~tim~rwhenTROor TRl = 1,and ~ther
GATEx = Oor INTx pin = 1. (SettingGATE%= 1

Table5.TCON:Timer/CounterControlRegister

TCON Address= 88H Reset= 0000OOOOB

BitAddressable
TF1 TR1 TFO TRO IEI IT1 IEO ITO
Bfi 7 6 5 4 3 2 1 0

Symbol Function
TF1 Timer1 overflow Flag.Setbyhardware onTimer/Countar overflow.Clearedbyhardware
whenprocessor vectoratointerrupt
routine.
TR1 Timer1 Runcontrolbit.Set/clesredbysoftwaretoturnTimer/Counter 1 on/off.
TFO TimerOoverflowFlag.Setbyhardware onTimer/Counter Ooverflow. Clearedbyhardware
whenprocessor vectorstointerrupt
routine.
TRO TimerORuncontrolbit.Set/clearedbysoftwaretoturnlimer/CounterOon/off.
IE1 Interrupt
1flag.Setbyhardware whenexternalinterrupt
1edgeisdetected(transmitted or
level-activated).
Clearedwheninterruptprocessedonlyiftransition-activated.
IT1 Interrupt1Typecontrolbit.Set/clearedbysoftwaratospecifiyfalling
edge/lowleveltriggered
externalinterrupt
1.
IEO Interrupt
Oflag.Setbyhardware whenexternalinterrupt
Oedgeisdetected(transmitted or
level-activated).
Clearedwheninterruptprocessedonlyiftransition-activated.
ITO Interrupt
OTypecontrolbit.Set/clearedbyaoftwaretospecifyfallingedge/lowleveltriggered
externalinterrupt
O.

Osc

I 270S97-11

Figure9. Timer/CounterOor 1 In Mode1:16-BitCounter

6-15
i@. 87C51GB HARDWARE DESCRIPTION

allows the Timer to be mntrolled by external input (SettingGATEx = 1allowsthe Timer to be controlled
IIVTXpinto facilitatepuke width measurements). by external input INTx pin, to facilitate pulse width
measurements).
TRx and TFx are control bits in the SRF TCGN. The
GATEx bits are in TMOD. There are two different ~ and TFx are control bits in the SFR TCON. The
GATE bits: one for Timer 1 (TMOD.7) and one for GATEx bits are in TMOD. There are two different
Timer O(TMOD.3). GATE bits: one for Timer 1 (TMOD.7)and one for
Timer O(TMOD.3).
MODE2
MODE3
Mode2 configures theTimer register as an 8-bitCoun-
ter (TLx)with automaticreload as shownin F@re 10. Timer 1 in Mode3 simplyholdsits count. The effectis
Overtlowfrom TLx not onlysets TFx, but also reloads the same as settingTRl = O.
TLx with the contentsof THx, which is preset by soft-
ware. The reload leavesTHx unchanged. Timer O in Mode 3 establishesTLOand THOas two
smarate counters. TLOuses the Timer O cxmtrolbits:
The countedinput is enabledto the timer whenTROor C2T0, GATEO,TRO,and TFO.THOis locked into a
TRl = 1, and either GATEx = Oor INTx pin = 1.

Oac
I

L 1+ I INTERRuPT

,X.NJ::: ‘ ‘C’JJ

TRx

GATE Tffx
(aalfs)
I
immti

270897-12

Figure10.Timer/Counter1 Mode2:S-BitAuto-Reload

+ls 1/12 lo~~

IOSCH t-
l/12fo=

1~1 INTERRUPT
.F.,N~@’1 I :
CONTROL OVERFLOW

l/12 foa~ I -G 1 INTERRUPT

CONTROL OVERFLOW
TR1
270897-13

Figure11.Tmer/CounterOMode3:Two8-BitCountere
6-16
in~. 87C51GB HARDWARE DESCRIPTION

timer function (counting machine cycles) and takes Timer 2 Auto-Reload(up or down counting),and
over the use of TRl and TFl from Timer 1.Thus THO Timer 2 as a Baud Rate Oenerstor.
nowcontrolsthe Timer 1interrupt. The logicfor Mode
3 on Timer Ois shownin Figure 11. The modes are also selected by bits in T2CON as
shownin Table 6.
Mode 3 is providedfor applicationsrequiringan extra
8-bit timer or counter. When Timer O is in Mode 3, TableI rimer 2 )peral dea
Timer 1 can be turned on and offby switchingit out of
and into its own Mode 3, or can still lx used by the ICLK+ ICLif :P/m r2”oE Mode
serial port as a baud rate generator, or in any applica- o o o 1 16-Bit
tion not reqtig an interrupt.
Auto-Reload
0 1 0 1 l&Bit
5.2 Timer 2 Capture
1 x x 1 Baud-Rate
Timer 2 is a 16-bitTimer/Counter which can operate Generator
either as a diner or as an eventcounter.This is selected x o 1 1 Clock-out
by bit C—T2in the SFR T2CON(Table 7). It has the onPI.0*
followingthree operating modes: x x x 0 TimerOff
Timer 2 Capture, ●Present
onlyonthe87C51
FC

Table7.T2CON:Timer/Counter2 ControlRegister

T200N Address= OC6H ReaetValue= 0000OOOOB

BitAddressable

Bit
I TF2
7
EXF2
6
RCLKI TCLK I EXEN2 TR2
5 4 3 2
Clz
1
cP/m
0

8ymbol Function
TF2 Timer2 overflow flagsetbya Timer2 overflow andmustbeclearedbysoftware.TF2willnot
besetwheneitherRCLK= 1orTCLK= 1.
EXF2 Timer2 externalflagsetwheneithera captureorreloadiscausedbya negative transitionon
T2EXandEXEN2= 1.WhenTimer2interrupt isenabledEXF2= 1willcausetheCPUto
vectortotheTimer2 interrupt routine.EXF2mustbeclearedbysoflware. EXF2doeanot
causeaninterrupt inup/downcountermode(DOEN= 1).
RCLK Receiveclockflag.Whenset, causestheserialporttouseTimer2 overflow pulsesforits
receiveclockinserialportModes1 and3. RCLK= OcausesTimer1overflow tobeusedfor
thereceiveclock.
TCLK Transmit clockflag.Whenset,causestheserialportto useTimer2 overflow pulsesforits
transmit clockinserialportModes1and3.TCLK= OcausesTimer1 overflows to beused
forthetransmitclock.
EXEN2 Timer2 externalenableflag.Whenset allowsa captureorreloadtooccurasa resultofa
negative transitiononT2EXifTimer2 isnotbeingusedtoclocktheserialport.EXEN2= O
causesTimer2 toignoreeventaatT2EX.
TR2 Start/stop oontrol for Timer 2. A logic 1 starts the timer.
cm Timer or counter select, (Timer 2)
O = Internal timer (OSC/12 or OSC/2 in baud rate generator mode.)
1 = External event counter (falling edge triggered).
cP/RD Capture/Reload flag. When set, captures will occur on negative transition at T2EX if EXEN2
= 1. When cleared, auto-reloads will occureitherwithTimer2 overflows ornegative
transitions
atT2EXwhenEXEN2= 1.WheneitherRCLK= 1 orTCLK= 1,&is bitis
ignored andthetimerisforcedtoauto-reload
on17mer2overflow.

6-17
i~. 87C51GB HARDWARE DESCRIPTION

The T2 Pin has another alternate function on the addition, the transition at T2EX causes bit EXF2 in
87C51GB.It can be configuredas a Programmable T2CONto be set. The EXF2bit likeTF2, can generate
ClockOut. an interrupt. Figure 12illustratesthis.

TIMER2 CAPTUREMODE TIMER 2 AUTO-RELOAD

(UP OR DOWNCOUNTER)
In the capture mode there are two o~tions selected by
bit EXEN2 in T2CON. If EXEN2 ~ O,Timer 2 is ~ Timer 2 can be programmedto count up or downwhen
16-bittimer on counter which,upon overflow,sets bit cont@red in its Id-bit auto-reloadmode. This feature
TF2 in T2CON. This bit oan then be used to generate is invokedby a bit named DCEN (Down Counter En-
an interrupt. If EXEN2 = 1, Timer 2 still does the able) located in the SFR T2MOD(see Table 8). Upon
above, but with the added feature that a l-to-Otran- reset the DCEN bit is set to O so that Timer 2 will
sition at external input T2EXcauses the current value default to count UD.When DCEN is set. Timer 2 can
in the Timer 2 regis~ers(TI-12and TL2) to be captured count up or down~ependingon the vrdueof the T2EX
into registers RCAKU-Iand RCAP2L, respectively.In pin.

OVERFLOW
72 PIN
7s2

~PTURE TIMER2
INTERRUPT
7RANSMON
DETECTION
I

EXEN2
270897-14

Figure12.Timer2 inCaptureMode

Table8. T2MOD:Timer2 ModeControlRegister

T2MOD Address= OC9H ResetValue= XXXXXXOOB

NotBitAddressable
— — — — — — T20E DCEN
Bit 7 6 5 4 3 2 1 0

Symbol Function
Notimplemented, reserved for future use.*
T20E Timer2 OutputEnablebit.
DECN DownCountEnablebit.Whenset,thisallowsTimer2 to beconfigured
asanup/down
counter
*Usersoftwareshould notwrite1storeserved bits.Thesebitsmeybeusedinfuture8051family products to invoke
newfeaturea.Inthat case, the reset or inactivevalueof the new bitwillbe O,and ita active value will be 1. The value
read from a reserved bit is indeterminate.

6-18
in~. 87C51GB HARDWARE DESCRIPTION

In the auto-reload mode with DCEN = O, there are Settingthe DCEN bit enablesTimer 2 to count up or
two options selected by bit EXEN2 in T2CON. If down as show-nin Figure 14. In this mode the T2EX
EXEN2 = O,Timer 2 countsup to OFFFFHand then pin czmtrolsthe direction of count. A logic 1 at T2EX
sets the TF2 bit uponovertlow.The ovezilowalso caus- makes Timer 2 count up. The timer wiUovertlow at
es the timer registers to be reloaded with the 16-bit OFFFFHand set the TF2 bit whichcan then generate
value in RCAP2H and RCAP2L. The values in an interrupt if it is enabled. This overtlowalso causes
RCAP2H and RCAF2L are preaet by software. If the 16-bitvalue in RCAP2H and RCAP2L to be re-
EXEN2 = 1, a id-bit reloadcarsbe triggeredeither by loaded into the timer regis~ TH2 and TL2, respec-
an overflowor by a l-to-Otransition at external input tively.
T2EX. This transition also sets the EXF2 bit. Either
the TF2 or EXF2 bit can generate the Timer 2 inter- A logic Oat T2EX makes Timer 2 count down. Now
rupt if it is enabled.Figure 13showstimer 2 automati- the timer undertows when TH2 and TL2 equal the
cdy counting Up when DCEN = O. vahs stored in RCAP2H and RCAP2L.‘he under-

OVERFLOW
72PN
7s2
RELOAD

TRAtmnol~
OETscnob

J AL TIMER2
INTERRuPT
T2EXPIN
~\
I CONTROL

SX;N2
270897-15

Figure13.Timer2 AutoReloadMode(DCEN= O)

(OOWN
COUNTNG
RELOAO
VALUE)

I FFH : FFH
I TOGGLE

TR2
AL COUNT
DIRECITDN
1 = UP
o = OOWN

(UPCOUNTING
RELOAO
VALUE)
❑
T2EXPIN
270897-16

Figure14.Timer2 AutoReloadMode(DCEN= 1)

6-19
i~e 87C51GB HARDWARE DESCRIPTION

flowsets the TF2 bit and causeaOFFFFHto be reload- To configurethe Timer/Counter 2 as a clockgenerator,
ed into the timer registers. bit C—T2(in T2CON) must be clearedand bit T20E
$us~&M~~jof~ ~esetet~it TR2 (in T2CON) ako
The EXF2 bit toggleawheneverTimer 2 overflowsor
underflows.Thisbit can be usedas a 17thbit of resolu-
tion if desired.In this operatingmode,EXF2 does not The ClockOut frequencydependson the osdator fre-
generatean interrupt. quencyand the reload value of Timer 2 capture regis-
ters (RCAP2H,RCAP2L) m shownin this equation:

5.3 Programmable Clock Out Clock

Out. oscillator Frequency
Frequency 4 x [65536– (Rc/4p2H, Rr&4p2L)]
The 87C51GBhas a new feature. A 50% duty cvcle
clock can be programmed to come out on P1.b. h In the Clock Out mode, Timer 2 roll-overswill not
pin, besidesbeinga regular 1/0 pin, has two alternate generatean interrupt. This is similar to whenit is used
functions.It can be programmed(1) to input the exter- as a baud-rategenerator. It is possibleto useTimer 2 as
nal clockfor Timer/Counter 2, or (2) to output a 50% a baud-rate generator and a clock generator simulta-
duty cycle clock ranging from 61 Hz to 4 MHz at a neously. Note+however, that the baud-rate and the
16MHz operatingfrequency.Figure 15showsTimer 2 clock-outfrequencywill be the same.
in clock-outmode.

-T--r+J 11
WI
P1.o
(12)
!
1- c“Bit EIEl I +2
1>1
1
I
w I I 1

I
T20E (T2M0D. t)
~T&N%:N
P1.1 [-l
(122)0 t
I

I
EX~N2
270897-17

Figure15.Timer2 inClook-OutMode

6-2o
intdo 87C51GB HARDWARE DESCRIPTION

6.0 A/D CONVERTER Table9.AID SFRa

TheA/D converter on the 8XC51GBconsists of: 8 (MSB) (LBB)

analog inputs (ACHO-ACH7), an external trigger in-
~~;::z’”
put (TRIGIN), separate analogvoltagesupplies(AV~
and AV~), a comparison reference input (MSB) (LsB)
(COMPREF) and internal circuitry. The internal cir- —— AIF , ACE ACS1 ACSO AIM , ATM
ACQN
cuitry includea:an 8 channel multiplexer,a 256element OS7H
reaiativeladder, a comparator, sample-and-holdcapaci-
(MSB) (LSB)
tor, successive approximation register, A/D trigger ACMP
control, a comparisonresult registerand 8 MD result CC7H
registers as shown in the A/D blcck diagram, Figure
16.
ADOthrough AD7 contain the results of the 8 analog
AV~F must be held within the tolerances stated on conversion.Each SFR is updated as each cmversion is
the 8XC51GBdata sheet. The accuracy of the A/D complete,starting with the lowest channel and ending
cannot be improved,for instance, by tying AVREFto with channel7.
y, the voltageon VCC.
ACMP is the comparisonresult register. ACMP is or-
- differently than all the other SFRS in that
6.1 A/D Special Function Registers CMPOoccupiesthe MSB and CMP7 the LSB.CMPO
TheA/D has 10SFRSassociatedwithit. The SFR6are
shownin Table 9.

‘O”’’””O”s
T ~ ------
8
It TRIGIN(Trigger

AVm
In)

CONVERSION
ENABLE
(ACE)

!...- – ,
*--------- I
: ADORESULT
b--------a + I I i I AfUWR
i I I I A’=~’J
I I
●
● , ACHO
●✍✍✍✍✍✍✍✍✍ Ak
; AD6RESULT ●
b--------a ‘1 — I .
I
!I-71! ●

ACH7

I I
b ----- ●

4 ?i’EZi4\SELECT(AIM)
If

COh4PREFAVs5
270897-1S

Figure16.A/D BlockDiagram

6-21
 87C51GB HARDWARE DESCRIPTION

thrOU@ CMP7 correspondto analog iStPUtS Othrough edgeisdetected,the A/D mnversiottsbeginon the next
7. CMPn is set to a 1if the analoginput is greater than machinecycleand completewhen channel7 is convert-
COMPREF.CMPnis clearedif the analoginput is leas ed. After channel 7 is czxsvert@ AIF is set and the
than or equal to COMPREF. conversionshalt until another trigger is detected while
ACE= 1. External triggersare ignoredwhilea conver-
ACON is the A/D control register and contains the sion cycle is in progreas.
A/D Interrupt Flag (AIF), A/D ConversionEnable
(ACE), A/D ChannelSelect (ACSOand ACS1),A/D
Input Mode (AIM), and A/D Trigger Mode (ATM). 6.4 A/D Input Modes
The 8XC51GBhas two input modes: Scan mode and
6.2 A/D Comparison Mode Select mode. Clearing AIM places the 8XC51GBin
Scanmode.In Scanmodethe arsrdogconversionsoccur
TheA/D Comparisonmode is alwaysactive whilethe in the sequenceACHO,ACH1, ACH2, ACH3,ACH4,
A/D converter is enabled. The Comparison mode is ACH5, ACH6, and ACH7. The reault of each analog
used to compareeach analog input against an external conversionis placedin the correspondinganalogremdt
referencevoltageappliedto COMPREF.Wheneverthe register: ADO, ADl, AD2, AD3, AD4, AD5, AD6,
A/D converteris triggered,each bit in ACMPis updat- and AD7.
ed as each analog conversion is completed, starting
with channel Oup to channel 7 regardless of whether SettingAIM activatesselect mode. In Selectmode one
Selector Scanmodeis invoked.The comparisonmode of the lower 4 analog inputs (ACHO-ACH3) is con-
can providea quicker“greater-than or leas-than”deci. verted four times. After the first four conversionsare
sionthan can be performedwith softwareand it is more complete the cycle continues with ACH4 through
codeeffkient. It can also be used to cmsvertthe analog ACH7. The results of the first four conversionare
inputs into digital inputs with a variable threshold. If placed in the lowerfour result registers (ADOthrough
the comparisonmode is not w@ COMPREF should AD3). The rest of the conversionsare placed in their
be tied to Vcc or VW. matching result register. ACSOand ACS1 determine
which analog inputs are used as ahownin Table 10.

6.3 A/D Trigger Mode Table10.A/D Channelselection

Theanalog convertercanbetriggered either internally Seiected
ACS1 ACSO
or externally.To enable internal trigger mode, ATM Channel
shouldbe ck.ared. o 0 ACHO
o 1 ACH1
Whenin internal triggermode, A/D conversionsbegin
1 0 ACH2
in the machine cycle which followsthe setting of the
ACE bit. The lowestcharmeI(see “AA) Input Modes” 1 1 ACH3
below)is convertedtlraLfollowedby all the other chan-
nels in sequence.The AIF fiag is set upon completion
of the channel7 conversion.AIF will tlag an interrupt 6.5 Using the A/D with Fewer than
if the A/D interrupt is enabled.once a conversioncy- 8 Inputs
cle is complete4 a new cycle be- starting with the
loweatchannel. If the user wishes each channel to be There are severaloptionsfor a user whowishesto con-
convertedonly once, the ACE bit should be cleared. vert fewer than eight analog input channels.If time is
ClearingACE stops all A/D conversionactivity. If a not critical the user can simplywait for the A/D inter-
new A/D cycle begin$ the result of the previouscon- rupt to be generatedby the AIF bit after channel 7 is
versionwill be overwritten. convertedand can ignore the results for unused chan-
nels. Ifa user needsto knowthe resutts of a conversion
In external mode, the A/D conversionsbegin when a immediatelyafter it occw a tinter should be used to
fallingedgeisdetectedat the TRIGIN pin. There is no generatean interrupt.Theamountoftimerequiredfor
edge detector on the TRIGIN pin; is it sampledonce each A/D conversionis specitiedin the 8XC51GBdata
everymachinecycle. sheet. The user could also periodicallypoll the result
rebte~: provided he or she is lcoking only for a
A negativeedgeis recognizedwhenTRIGIN is highin change m the analog voltage. Using the Select mode
one machinecycleand lowin the next. For this reason, (seeabove)doesnot reducethe time requiredfor a con-
TRIGIN shouldbe held high for at least onemachine version cycle but will convert a given channel more
cycle and low for one machine cycle. Once the fklling frequently.

6-22
intd. 87C51GB HARDWARE DESCRIPTION

6.6 A/D in Power Down Table11.PCAandPCA1SFRS

The AfD on the 8XC51GBcontainscircuitry that lim- PCA PCAI
its the amount of current dissipated during Power SFRS:
Down mode to leakagecurrent only. For this circuitry CCON. . . . . . . . . . . . . . . . . . . . . . CICON
to tknction properly, AV~ should be tied to VW CMOD. . . . . . . . . . . . . . . . . . . . . . CIMOD
during power down.The IpD specificationin the data CCAPMO. . . . . . . . . . . . . . . . . . . CICAPMO
sheet includes the current for the entire chip. While
AV~ is tied to Vw during PowerDown,the voltage CCAPM1. . . . . . . . . . . . . . . . . . . CICAPM1
may be reduced to the minimum voltage as shownin CCAPM2. . . . . . . . . . . . . . . . . . . C1CAPM2
the data sheet. CCAPM3. . . . . . . . . . . . . . . . . . . C1CAPM3
CCAPM4. . . . . . . . . . . . . . . . . . . C1CAPM4
CL . . . . . . . . . . . . . . . . . . . . . . . . . CL1
7.0 PROGRAMMABLECOUNTER CCAPOL . . . . . . . . . . . . . . . . . . . . CICAPOL
ARRAY CCAPIL. . . . . . . . . . . . . . . . . . . . CICAPIL
CCAP2L. . . . . . . . . . . . . . . . . . . . C1CAP2L
Programmable Counter Arrays (PCAS)provide more CCAP3L. . . . . . . . . . . . . . . . . . . . C1CAP3L
timing capabilitieswith leasCPU interventionthan the
standard timer/cmsnters. Their advantagesincludere- CCAP4L. . . . . . . . . . . . . . . . . . . . C1CAP4L
duced sofiware overheadand improvedaccuracy.For CH. . . . . . . . . . . . . . . . . . . . . . . . . CH1
exampl% a PCA can provide better resolution than CCAPOH . . . . . . . . . . . . . . . . . . . . CICAPOH
Timers O, 1, and 2 becausethe PCA clock rate can be CCAPIH. . . . . . . . . . . . . . . . . . . . CICAP1H
three times fa6ter.A PCA can dSOpSSfOrM MSXly t@S CCAP2H. . . . . . . . . . . . . . . . . . . . C1CAP2H
that these hardware timers cannot (i.e. measure phase CCAP3H. . . . . . . . . . . . . . . . . . . . C1CAP3H
differencesbetweensignalsor generate PWM6). CCAP4H. . . . . . . . . . . . . . . . . . . . C1CAP4H
The 8XC51GBhas two PCAs called PCA and PCA1. BITS:
The followingtext and figures address only PCA but ECI. . . . . . . . . . . . . . . . . . . . . . . . . ECI1
are also applicableto PCA1 with the followingexcep- CEXO.. . . . . . . . . . . . . . . . . . . . . . CIEXO
tions: CEX1. . . . . . . . . . . . . . . . . . . . . . . CIEX1
1. PCA1, Module 4 does not support the Watchdog CEX2. . . . . . . . . . . . . . . . . . . . . . . C1EX2
Timer CEX3. . . . . . . . . . . . . . . . . . . . . . . C1EX3
2. All the SFRs and bits have 1s added to their names CEX4. . . . . . . . . . . . . . . . . . . . . . . C1EX4
(see Table 11). CCFO. . . . . . . . . . . . . . . . . . . . . . . CICFO
3. Port 4 k the interfacefor PCA1: CCF1. . . . . . . . . . . . . . . . . . . . . . . CICF1
P4.2 ECI1 CCF2. . . . . . . . . . . . . . . . . . . . . . . C1CF2
P4.3 CIEX1 CCF3. . . . . . . . . . . . . . . . . . . . . . . C1CF3
P4.4 CIEX2 CCF4. . . . . . . . . . . . . . . . . . . . . . . C1CF4
P4.5 C1EX2 CR. . . . . . . . . . . . . . . . . . . . . . . . . CR1
P4.6 C1EX3 CF . . . . . . . . . . . . . . . . . . . . . . . . . CF1
P4.7 C1EX4

16 BITSEACH

-“3’’”0

I 16 B17S
P1.4/cExl

P1.5/CEX2

t-@--’’cEx3Ex3 P1.7/CEX4
270S97-19

I%gure17.PCABlockDiagram
6-23
intd. 87C51GB HARDWARE DESCRIPTION

4. There has been one additionalbit added to CICON When the compare/capture modulesare programmed
to ~OWboth PCASto be enabledsirmdtrmeou.dy. in the capture mod$ softwaretimer, or high speedout-
The bit is called CRE and occupiesbit position 5 of put mode, an interrupt can be generatedwhenexerthe
CICN. Its bit address is OEDH.When CRE is set, moduleexecutesits function.All fivemodulesplus the
both CR and CR1 must be set to enable PCA1. PCA timer overflowshare one PCA interrupt vector.

Each PCA mnsiats of a id-bit tisner/counter and five The PCA timer/counter and compare/capture mcdules
16-bit compare/capture modules as shown in Figure share Port 1pins for external1/0. These pins are listed
17. The PCA timer/counter servesas a common time below.If the port pin is not used for the PCAj it can
base for the five modulesand is the only timer which still be used for st&dard 1/0.
can service the PCA. Its clock input can be pro-
grammedto count any one of the followingsignals: PCAComponent External1/0 Pin
Oscillatorfrequency/ 12 16-bitCounter P1.2/ ECI
oscillator fkequency/ 4 16-bitModuleO P1.3/ CEXO
Timer Ooverflow 16-bitModule1 P1.4I CEX1
External input on ECI (P1.2). 16-bitModule2 P1.5/ CEX2
16-bitModule3 P1.6/ CEX3
The comparehpture modulescan be programmed in 16-bitModule4 P1.7 / CEX4
any one of the followingmodes:
rising and/or fallingedge capture
softwaretimer 7.1 PCATimer/Counter
high Speedoutput The PCA has a free-running16-bittimer/counter con-
pulse width modulator. sistingof registers CH and CL (the high and low bytes
of the count value). These two registerscan be read or
Module 4 can also be programmed as a watchdog written to at any time. Readingthe PCA timer as a full
timer. 16-bitvalue simultaneouslyrequires using one of the
PCA mcduleain the capture modeand togglinga port
pin in sotlware.

-w ~‘~
CPSI
CPSO TO PCA MODULSS0-4

&~
——
00
FOsc/12
01

“7’-
Fosc/4
TIMER 0 10 CF INTERRuPT
(s:Hm) { (8c&s)
OVERFLOW 1 1
EXTERMAL CONTROL ENASLE
INPUT
(ECI)

CR

CIDL
PROCSSSORIN
IDLE UOOE
/

Figure18.PCATimer/Counter

6-24
 87C51GB HARDWARE DESCRIPTION

The clockinput can be selectedfrom the followingfour Externalinput:

modes:
ThePCA timer incrementswhen a l-to-Otransition is
detected on the ECI pin (P1.2). The maximuminput
Oscillatorfraquancy/ 12: frequencyin this mode is oscillatorfrequency/ 8.
The PCA timer increments once per machine cycle.
With a 16 MIiz crystal, the timer increments evety The mode register CMOD (Table 12) contains the
750m. CountPulse Selectbits (CPS1and CPSO)to specifythe
clock input. This register also contains the ECF bit
which enables the PCA counter overflowto generate
Oscillatorfrequency/ 4: the PCA interrupt. In addition,the user has the option
of turning off the PCA timer during Idle Modeby set-
The PCA timer increments three times per machine ting the Counter Idle bit (CIDL). This can further re-
cycle. With a 16 MHz crystal, the timer increments duce power consumptionby an additional30%.
every250ns.
The CCON (Table 13)register containstwo more bits
whichare associatedwith the PCA timer/munter. The
TimerOoverflows: CF bit gets set by hardware when the counter over-
The PCA timer increments whenever Timer O over- flows,and the CR bit is set or clearedto turn the coun-
flows. This mode allows a programmable input fre- teron or off.
quencyto the PCA.
Table12.CMOD:PCACounterModeRegister

CMOD Address= OD9H ResetValue= OOXX

XOOOB
NotBitAddressable
CIDL WDTE —l— — CPS1 CPSO ECF 1
Bit 7 6 5 4 3 2 1 0

symbol Funotion
CIDL Canter Idlecontrol:
CIDL= Oprograms thePCACountertocontinue functioning
during
idleMode.CIDL= 1 programs itto begatedoffduringidle.
WDTE Watchdog TimerEnable:WDTE = Odiaables Watchdog Timerfunction
onPCAModule4.
WDTE= 1enablesit.
— Notimplemented,reservedforfutureuse.*
CPS1 PCACountPulseSelectbit1.
CPSO PCACountPulseSaIectbitO.
CPS1 CPSO SelectedPCAInput**
o 0 Internal clock, Foac+ 12
0 1 Internalclock,FOSC+4
1 0 Timer O overflow
1 1 External ciookat EC1/Pl.2 pin (max. rate = Fosc+8)
ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generste an
interrupt. ECF = O disables that funotion of CF.

NOTE:
“Usar softwareshould notwrite Is to reserved bits. These bits maybe used in future 8051family products toinvoke
newfeatures. In that case, the reset or inactivevalue of the new bitwill be O,and its activevalue will be 1. The value
read from a reserved bit is indeterminate.
..F~ = ~llator frSIJUenCY

6-25
irrl& 87C51GB HARDWARE DESCRIPTION

Table13.CCON:PCACounterControlR~ieter

CCON Address= OD6H ResetValue= OOXO

00006

BitAddressable
! W ! CR I – I CCF4 ] CCF3I CCF2 I CCFI I CCFOI
Bit 7 6 5 4 3 2 1 0

Svmbol Function
CF PCACounterOverflow flag.Setbyhardware whenthecounterrolls over. CF flags an
interrupt if bit ECF in CMODis
set.CFmaybesetbyeitherhardware orsoftwarebutcan
onlybeclearedbysoftware.
CR PCACounterRuncontrolbit.SetbysoftwaretoturnthePCAcounteron.Mustbecleared
byeoflwaretoturnthePCAcounteroff.
Notimplemented,reserved forfutureuse*.
CCF4 PCAModule4 interruptflag.Setbyhardwere whena matchorcaptureoccurs.Mustbe
clearedbysoftware.
CCF3 PCAModule3 interruptflag.Setbyhardware whena matchorcaptureoccurs.Mustbe
clearedbysoftware.
CCF2 PCAModule2 interruptflag.Setbyhardware whena matchorcaptureoccurs.Mustbe
clearedbysoftware.
CCF1 PCAModule1 interruptflag.Setbyherdware whena matchorcaptureoccurs.Mustbe
clearedbysoftware.
CCFO PCAModuleOinterrupt flag.Setbyhardware whena matchorcaptureoccurs.Mustbe
clearedbysoftware.
●NOTE:
Useraoftwsre shouldnotwritele toreserved bite.Thesebitsmeybeusedinfuture 8051familyproducts toinvoke
newfeeturee. Inthatease,theresetor insotiveveluaofthe newbitwillba O,end itsactivevaluewillbe 1.Thevalue
read froma resewedbitis indeterminate.

READINGTHE PCATIMER 7.2 Compare/Capture Modules

Someapplicationsmay requirethat the full Id-bit PCA Each of the fivecompere/capture meduks has six pos-
timer value be read simultaneously.Since the timer siblefunctionsit can perform:
consistsof two 8-bit registers(CH, CL), it would nor- 16-bitCapturq positive-edgetriggered
mally take two MOV instructions to read the whole
timer value.An invalidread couldoccur if the registers id-bit Capture,negative-edgetriggered
rolled over in betweenthe executionof the two MOVS. id-bit Capture,both positiveand negative-edge
triggered
However,with the PCA CaptureModethe M-bittimer 16-bitsoftware Timer
value can be loaded into the capture registers by tog-
gling a port pin. For example,cofigure Module Oto 16-bitHigh SpeedOutput
cspture falling edges end initialize P1.3 to be high. 8-bitPulseWidth ModuIetor.
Then, when the user wants to read the P(2Atimer,
clearPL3 and thefull I&bittimervaluewillbe saved In eddition,module4 can be used es a WatchdogTim-
in the captureregisters.It’sstilloptionalwhetherthe er. The modulescan be programmedin any combina-
userwantsto generateen interruptwiththe capture. tion of the differentmodea.

6-26
intel. 87C51GB HARDWARE DESCRIPTION

Each module has a mode register called CCAPMn 7.3 PCACaptureMode

(n = O, 1, 2, 3, or 4) to select which function it will
perform. The ECCFn bit enables the PCA interrupt Bothpositiveand negativetransitionsoentriggera cap-
when a module’s event flag is set. The event tlags ture withthe PCA. This givesthe PCA the flexibilityto
(CCFn) are located in the CCON register and get set measure periods,pulse widths, duty cycles+and phase
when a capture event, software timer, or high speed differenceson up to five separate inputs. Setting the
output eventoccurs for a givenmodule. CAPPn snd/or CAPNn bits in the CCAPMn mode
register (’fable 14) selects the input trigger-positive
Each mcdule also has a pair of 8-bit compare/capture end/or negativetransition-for modulen. Refer to Fig-
registers (CCAPnH and CCAPnL) associatedwith it. m 19.
These registersstore the time whena capture event oc-
curred or whena compare event shouldoccur. For the Table 15 shows the combinations of bits in the
PWM mode,the high byte register CCAPnH controls CCAPMn register that are valid and have a defined
the duty cycleof the waveform. function.Invalid combinationswill produce undetined
results.

Table14.CCAPMn:PCAModulesCompare/Capture
Registers

CCAPMnAddress CCAPMOODAH ResetValue= XOOO

OOOOB
(n = O-4) CCAPM1 ODBH
CCAPM2 ODCH
CCAPM3 ODDH
CCAPM4 ODEH
NotBitAddressable
— ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
I
Bit 7 6 5 4 3 2 1 0

SymbolFunction
— Notimplemented, reserved
forfutureuse*.
ECOMnEnableComparator. ECOMn= 1 enablesthecomparator function.
CAPPn capturePositive,CAPPn= 1 enablespositive
edgecapture.
CAPNn CaptureNegative,CAPNn= 1 enablesnegative edgecapture.
MATn Match.WhenMATn= 1,a matchofthePCAcounterwith thismodule’acompare/cspture
registercausestheCCFnbitinCCONto bsset,flagginganinterrupt.
TOGn Toggle.WhenTOGn= 1,a matchofthePCAcounterwith thismodule’scompare/cspture
registercausestheCEXnpintotoggle.
PWMn PulseWidthModulation Mode.PWMn= 1 enablestheCEXnpintobeusedasa pulsewidth
modulated output.
ECCFn EnableCCFinterrupt.Ensblescompare/captureflagCCFnintheCCONregistertogenerate
aninterrupt.
NOTE
●User software should not write 1s to resarved bite.These bite maybe used in future 8051 family products to invoke
new features. In that ceae,the reset or inactive value of the new bit will be O, and its aofive value will be 1. The value
read from a reasrvsd bit is indsterrninate.

6-27
intd. 87C51GB HARDWARE DESCRIPTION

Table15.PCAModuleModes(CCAPMnRegister)
- ECOMnCAPPnCAPNnMATn IOGnPWMnECCFn ModuleFunotion
x o 0 0 0 0 0 0 Noomration
x x 1 0 0 0 0 x I&bit espture bya postive-sdgetriggeron CEXn
x x o 1 0 0 0 x 16-bit capturebya nagativa-edgetriggeron CEXn
x x 1 1 0 0 0 x 16-bit capture byatransition on CEXn

x 1 0 0 1 0 0 x 16-bit Software Timer

x 1 0 0 1 1 0 x 16-bitHigh Spaad Output

x 1 0 0 1 x o x Watchdog Timer

X = Don’tCare

I I u’”’’=’”

, m ,
x o o o ECCFn
I I I I n = O, 1, 2, 3 w 4
CCAPMn MOOE REGIS7ER x = C-motCare
270897-21
-. .- --- .- . .. - . .. .
rlgure IY. IWA m-m ~pmma moae

The externalinput pins CEXOthroush CEX4are aam- In the interrupt serviceroutine,the Id-bit eeoture value
pled fora tram~tiori.Whena validtr&sition is detected must be sav~ in FUW before the next .+ure ewent
(positive and/or negative edge), hardware loads the oeeurs. A subsequentcapture on the same CEXn pin
Id-bit valueof the PCA timer (C!H,CL) into the mod- will write over the first capture valuein CCAPnI-iand
ule’s capture registers (CCAPnH, CCAPnL). The re- CCAPnL.
sulting valuein the capture registers reflects the PCA
timer valueat the time a transition was detectedon the The time it takes to servicethis interrupt routine deter-
cExn pin. mines the resolution of back-to-backeventa with the
same PCA module. To store two 8-bit registers and
Upott a capture, the module’sevent flag (CCFn) in clear the event flags takes at least 9 machine cycles.
CCON is set, and an ittterrupt is fiaggedif the ECCFn That includes the all to the interrupt routine. At
bit in the moderegister CCAPMnis set. Tbe PCA in- 12MH2,this routinewotddtake lessthan 10ps. How-
terrupt willthen be generatedifit is enabled.Sincethe ever, dependingon the frequencyand interrupt latency,
bardware does not cleer an event flag when the ittter- the resolutionwill vary with each application.
rupt is vectoredto, the flagmust be clearedin software.

6-28
infd. 87C51GB HARDWARE DESCRIPTION

7.4 SoftwareTimerMode For the SoftwareTimermcde,the MATnbit also needs

to be set. Whena matchoccursbetweenthe PCA timer
In most applicationsa softwaretimer is used to trigger and the conqmreregisters,a match signalis generated
interruptroutineswhichmustoccurat periodicinter- and the module’seventtlag (CCFn) is set. An interrupt
vals. The user preloads a id-bit value in a module’s is then flaggedif the ECCFnbit is set. The PCA inter-
compare registers.When a match occurs betweenthis rupt is generated only if it has been properlyenabled.
compare valueand the PCA timer value,an event flag Softwaremust clear the eventfig beforethe next ir2ter-
is set and an interrupt can then be generated. rupt will be flagged.

In the PCA comparemode the 16-bitvalueof the PCA During the interrupt routine,a new id-bit compareval-
timer is comparedwith a Id-bit value pre-loadedin the ue can be written to the compare registers (CCAPnH
module’s compare registers (CCAPnH, CCAPnL) as and CCAPnL). Notice, however, that a write to
seen in Figure 20. The comparisonoccurs three times CCAPnLclearsthe ECOMnbit whichtemporarilydis-
per machine cyclein order to r~gnize the fastest pas- ables the comparatorfunctionwhile these registers are
sible clock input (i.e. ~, X oscillator frequency).Set- being updated so an invalidmatch does not occur. A
ting the ECOMn bit in the mode register CCAPMn write to CCAPnH sets the ECOMn bit and re-enables
a-bles the comparatorfunction. - the comparator. For this reason, user softwareshoold
write to CCAPnLfirst, then CCAPnH.

I ➤IN7ERRUPT

PcA

4
ENABLE

x o MATn ECCFn
I I
t CCAPMn MOOE REGISTER
RESET
wRITE
TO
CCAPnL ,,0,,

WRmTO
CCAPnH
,,,.,
a
270897-22

Figure20.PCA16-BitComparatorMode:SoftwareTimer

6-29
intd. 87C51GE HARDWARE DESCRIPTION

7.5 HighSpeedOutputMode Without any CPU intervention, the fastest waveform

the PCA can generatewith the HSOmodeis a 30.5Hz
The High SpeedOutput (1-ISO)mode togglesa CEXn signalat 16MHz.
pin whena match occursbetweenthe PCA timer and a
pm-loadedvalue in a module’smmpare registers. For
this mod%the TOOn bit needs to be set in additionto 7.6 WatchdogTimerMode
the ECOMn and MATn bits in the CCAPMn mode
register. By setting or clearirrg the pin in software,the A WatchdogTimer is a circuit that automatically in-
user can selectwhetherthe CEXn pin willchangefrom vokes a reset unless the system being watched sends
a logicalOto a logical1or viceversa. The user also has regularhold4f signalsto the Watchdog.Thesecircuits
the option of flaggingan interrupt whena match event are used in applications that arc subject to electrical
occurs by settingthe ECCFn bit. SeeFigure 21. noi~ power glitches, electrostatic discharg~ etc., or
where high reliabilityis required.
The HSO mode is more accurate than toggling port
pins in software because the toggle occurs before The Watchdog Timer function is only available on
branching to an interrupt. That N interrupt latency PCA Module 4. If a WatchdogTimer is not needed,
will not effect the accuracy of the output. In fact, the Module4 can still be used in other modes.
interrupt is optional.Only if the user wants to change
the time for the neat toggleis it necemaryto updatethe As a Watchdogtimer, everytime the count in the PCA
compare registers.Otherwise,the next togglewilloccur timer matches the value stored in module4’s compare
when the PCA timer rolls over and matches the last registers,an internal reset is generated(see Figure 22).
~— value.
comnare —.. The bit that selectsthis modeis WDTE in the CMOD
register. Module 4 must be set up in either compare
modeas a “SoftwareTimer” or High SpeedOutput.

TERRUF7

CEXn PIN
llMCR/%

270297-23
Figure21.PCA16-BitComparatorMode:HighSpeedOutput

6-30
int& 87C51GB HARDWARE DESCRIPTION

WDTE
~ 16
I
1
16 1
MATCH *
16-BIT
COMPARATOR
I ‘“4 :T ‘

I
ENABLE

I
x
1’1I
ECOM4 O 0
I
1
I
x
I
o
I
x
I

=--l
CCAPM4MOOEREGISTER
RES~
WRITETO
CCAP4L ,,0,,

WWE TO
CCAP4H
,,1,,
-
270S97-24
-.— -- .. . . . . — .. .
rlgurez. walcnaogmmerMoae
JO hold off the ream the user has three options: counter goes astray and gets stuck in an intinite loop,
1.periodicallychange the comparevalueso it will nev- interrupts will still be serviced,and the watchdog will
er match the PCA timer, not resetthe controller.Thus, the purposeof the watch-
dog would be defeated. Instead, call this subroutine
2. periodicallychange the PCA timer value so it will from the main program within 65536counts of the
never match the comparevalue, PCA timer.
3. disablethe Watchdogby clearingthe WDTE bit be-
fore a match occurs and then later rc-enable it.
7.7 PulseWidthModulatorMode
The first two options are more reliable because the
WatchdogTimer is neverdisabledas in option 4$3.The Any or all of the five PCA modules can be pr~
secondoption is not recommendedif other PCA mod- grammedto be a Pulse Width Modulator.The PWM
ules are beingused since this timer is the time base for output can be used to convert digitaldata to an analog
all five modules. 11~ in moat applicationsthe fnt ~@ by ~ple m~ circuitry. The frequency
ofthe
solutionis the beat option. PWMdependson the clock sourcefor the PCA timer.
With a 16MHz crystal the maximumfrequencyof the
The watchdog routine should not be part of an inter- PWM waveformis 15.6KHz. Table 16showsthe vari-
rupt service routine.Why?Bwwse if the program ous frequenciesthat are possible.

6-31
i~. 87C51GB HARDWARE DESCRIPTION

Table16.PWMFrequencies
PWMFrequenoy
PCATimerMode
12MHz 16MHz
1/12 Osc.Frequency 3.9 KHz 5.2 KHz
1f4 Osc.Frequency 11.8 KHz 15.6 KHz

TimerOOverflow:
8-bit 15.5Hz 20.3HZ
16-bit 0.06iiz 0.08 Hz
8-bitAuto-Reload 3.9KHzto 15.3Iiz 5.2 KHzto20.3tiz
ExternalInput(Max) 5.9KHz 7.8 KHz

For this mode the ECOMn bit and the PWMn bits in The value in CCAPnL controls the duty cycle of the
the CCAPMn mode register need to be set. The PCA waveform.To change the value in CCAPnL without
generates8-bitPWMSby comparingthe low byte of the output glitches, the user must write to the high byte
PCA timer (CL) with the low byte of the module’s register(CCAPnH).This valueis then shiftedby hard-
compare registers (CCAPnL). When CL < CCAPnL ware into CCAPnLwhen CL rolls over from OFFIIto
the output is low. When CL > CCAPnLthe outrmt is OOHwhich correspondsto the next tied of the out-
high. R-eferto Figure 23. put.

I
CL
CL MADE
FF TO 00
IRANSillON

z CCAPnH

CCAPnL

T
ENABLE
CL C CCAPnL
CL Z CCAPnL
.,09.

.,1,,
w
I
CEXnPIN

CCAPMnMODEREGISTER
270887-25

Figure23.PCA6-BitPWMMode

6-32
in~o 87C51GB HARDWARE DESCRIPTION

CCAPnHcan containany integerfrom Oto 255to vary the receive register. (However, if the first byte still
the duty cyclefrom a 100%to 0.4%. A 0%0 duty cycle hasn’t been read by the time reception of the second
can be obtainedby writing directlyto the port pin with byte is complete,one of the bytes will be lost).
the CLRbit instruction.To calculatethe CCAPnHval-
ue for a givenduty cycle, w the followingequation: The serial port receive and transmit registers are both
accessedthroughSpecialFunction RegisterSBUF.Ac-
CCAPnH
= 256x (1 - DutyCycle) tually, SBUFis two separate registera,a transmit but%r
and a receivebuffer.Writing to SBUFloads the trans-
where CCAPUHis an 8-bit integer and Duty Cycleis mit register, and reading SBUF accessesa physically
expressedas a fraction. See Figure 24. separate receiveregister.
The serialport cantrol and status registeris the Special
8.0 SERIALPORT FunctionRegisterSCK)Ncable 17).This registercxm-
tains the modeselectionbits (SMOand SM1);the SM2
The serial port is full duple~ meaningit can transmit bit for the multiprocessor modes; the ReceiveEnable
and receivesimultaneously.lt is also receive-buffered, bit (REN); the 9th data bit for transmit and receive
meaningit can commencereception of a second byte (TB8 and RB8); and the serial port interrupt bits (T1
before a previouslyreceived byte has been read horn and RI).

Din-f CYCLE CCAPnH OUTPUT WAVEFORM

100% 00

90%

50%
128 ~

10%

0.4%
255 ~
270697-26

Figure24.CCAPnHVeriesDutyCycle

6-33
i~. 87C51GB HARDWARE DESCRIPTION

Table17.SCON:SerialPortControlRegister

SCON Address= 98H ResetValue= 0000OOOOB

BitAddreeseble

SMO/FE SM1 SM2 REN ~8 RB8 TI RI

Bit: 5 4 3 2 1 0
(sM:m=o/L

Symbol Function
FE FramingErrorbit.Thisbitissetbythereceiverwhenaninvalidstopbitisdetected.me FE
bitisnotclearedbyvalidframesbutshouldbeclearedbysoftware. TheSMODO*bitmust
besettoenableaccesstotheFEbit.
SMO SerialPortModeBitO,(SMODO must= OtoaccessSMO)
SM1 SerialPortModeBit1
SMO SM1 Mode Description BaudRate”’
000 shiftregister Fac/12
01 1 8-bitUART variable
10 0 9-bitUART Fo5c/64orFo~/32
1 1 3 9-bitUART variable
SM2 EnablestheAutomatic Address Recognition featureinModes2or3. If SM2= 1thenRI
willnotbesetunlessthereceived byteisa GivenorBroadcast Address. InMode1,
ifSM2 = 1thenRIwillnotbeactivatedunlessa validstopbitwasreceived, andthe
receivedbyteisa GivenorBroadcast Address.InModeO,SM2shouldbeO.
REN Enablesserialreception.
Setbysoftwaretoenablereception. Clearadbysoftware to
disablereception.
TB8 The9thdatabitthatwillbetransmitted inModes2 and 3. Set or clear by software as
desired.
RB8 recetied.InMode1 ifSM2=0, RB8isthestop
In modes 2 and 3, the 9th data bit that was
bitthatwasreceived.InModeO,RB8isnotused.
TI Transmitinterrupt
flag.Setbyherdwere
attheendofthe8thbittimeinModeO,oratthe
beginningofthestopbitintheothermodes,inanyserialtransmission.
Mustbeclearedby
software.
RI Receiveinterrupt
flag.Setbyhardware
attheendofthe8thbittimeinModeOorhalfway
throughthestopbittimeintheothermodes,inanyserialreoeption
(exceptseeSM2).
Mustbeclearedbysoftwere.
NOTE
●SMOOO islocated at PCON6.
●*Foec = oaclllatorfrequeney

Tbeaerialporteanoperate in 4 mcdes: In all four modes, transmissionis initiated bv snv in-

Mode O: ShitlRegister, freed frequency structionthat * SBUFas a deatinstionregker~Re-
ceptionis initiatedin ModeOby tbe conditionRI = O
Mode 1: 8-BitUART,variablefreqsseney smd RBN = 1. Reception is initiated in the other
Mode2: 9-BitUART,fixedffequency modesby the incomingstart bit if REN = 1.
Mode 3: 9-BitUART, variable frequeney
Mode O: Serial data enters and exits through RXD.
The baud rate in some modes is fixed and in others is TXD outputs the shift clock. 8 bitaare transmitted/re-
generated by Timer 1 or Timer 2. eeived:8 data bits (L3Bfirst). Tbe baud rate is fixedat
1/12 the oscillatorfrequency.

6-34
 I

i~e 87C51GB HARDWARE DESCRIPTION

Mode 1: 10bits are transmitted (through TXD) or re- 8.1 Framing Error Detection
ceived(through RXD): a start bit (0), 8 data bits (LSB
tirst), and a stop bit (l). On receive,the stop bit goes FrainingError Detectionallowsthe serialport to check
into RB8 in SCON.The bsud rate in Mode 1 is vari- for validstop bitsin modes1,2, or 3. A missingstop bit
able: youcan use either Timer 1 to generatebaud rates can be caused, for example by noise on the serial lines,
and/or Timer 2 to generatebaud rates. Figure25 shows or transmissionby two CPUSsimultaneously.
the mode 1 Data Frame.
If a stop bit is missing,a Framing Error bit (FE) is set.
The FE bit can be checkedin softwareafter each recep-
tion to detect communicationerrors. Once set, the FE
bit must be clearedin software.A validstop bit will not
clear FE.

I Stati Bit Stop Bit

270S97-27 I The FE bit is locatedin SCONand sham the same bit
address as SMO.Controlbit SMODOin the PCON reg-
ister determineswhetherthe SMOor FE bit is amessed.
Figure25.Mode1 DataFrame If SMODO= O,then accessesto SCON.7are to SMO.
If SMODO= 1, then accessesto SCON.7are to FE.
Mode 2: 11bits are transmitted (through TXD) or re-
ceived(through RXD): a start bit (0), 8 data bits (LSB
first), a programmable9th data bit, and a stop bit (l). 8.2 MultiprocessorCommunications
OnT ransmit, the 9tb &ts bit (TB8 in SCON)can be
assignedthe valueof Oor 1. Or, for example,the parity Modes2 and3 providea 9-bitmode to facilitate mtdti-
bit @ in the PSW) could be moved into TB8. 011re- processorcommunication.The 9th bit allows the con-
ceive,the 9th data bit goes into RB8 in SCON, while troller to distinguishbetweenaddress and data bytea.
the stop bit is ignored.(The validityof the stop bit can The 9th bit is set to 1 for addreasand set to Ofor data
be checked with Framing Error Detection.) The baud bytes. When receiving,the 9th bit goea into RB8 in
rate is programmableto either 1/32 or 1/64 the oscilla- SCON.When transmitting, the ninth bit TB8 is set or
tor frequency.See Figure 26. cleared in software.

The aerialport can be prograrnmed such that when the

stop bit is receivedthe serial port interrupt will be acti-
vated only if the receivedbyte is an address byte (RB8
= 1).This feature is enabledby setting the SM2bit in
SCON.A wayto use this feature in mukiprocesaorsys-
I Start Bit I stop Bn 1 tems is as follows.

I Ninth &a
270S97-2B
Blt
I Whenthe master procesaor wantsto tranamr“ta blockof
data to one of several slaves, it first sends out an ad-
Figure26.Mode2 DataFrame dreasbyte which identifiesthe target slave.Remember,
an addreas byte has its 9th bit set to 1, whereas a data
Mode3: 11bits are transmitted (through TXD) or re- byte has its 9th bit set to O. All the slave processors
ceived(through RXD): a start bit (0), 8 data bits (LSB shouldhave their SM2bits set to 1 so they will onlybe
first), a programmabIe9th data bit and a stop bit (1). In interrupted by an address byte. In fac~ the 8XC51GB
fact, Mode 3 is the same as Mode 2 in all respects has an Automatic Address Recognition feature which
exceptthe baud rate. The baud rate in Mode 3 is vti- allows only the addressedslave to be interrupted. That
able: you can use Timer 1 and/or Timer 2 to generate is, the addresscomparisoncecumin hardware,not sofi-
baud rates. See Figure 27. ware. (On the 8051serial po~ sn address byte inter-
rupts sll slsves for sn sddress comparison.)

The addressed slave then clears its SM2 bit and pre-
II 00 I D1 I D2 I 03 I 04 I D5 j 0S I D7 I OS
! 1
pares to receivethe data bytesthat will be coming.The
Data Byte other slaves are unaffectedby these data bytes. They
‘1’1
are still waitingto be addreasedsince their SM2bits are
Stat+ Bit I St+ Bit all set.
Ninth Data Bit
270S97-2S

Figure27.Mode3 DataFrame

6-36
 87C51GB HARDWAREDESCRIPTION

8.3 AutomaticAddressRecognition zeros definedas don’t-cares.The don’t-caresalso allow

flexibility in defining the Broadcast Address, but in
AutomaticAddress Recognitionreduces the CPU time most applicationsa BroadcastAddresswill be OFFH.
required to service the serial port. Since the CPU is
only interrupted when it receivesits own ad- the The feature works the same way in the 8-bit mode
s&ware overhead to compareaddresses is eliminated. (Mode 1)as in the 9-bitmodes,exceptthat the stop bit
Automatic addreasrecognitionis enabledby setting the takes the place of the 9th data bit. If SM2is set, the RI
SM2bit in SCON.With this feature enabled in one of flagis set onlyif the receivedbyte matchesthe Givenor
the 9-bit modes, the ReceiveInterrupt (RI) flag will Broadcast Addreas and is termma “ ted by a valid stop
only get set when the receivedbyte cm-respondsto ei- bit. Settingthe SM2bit has no &Teetin Mode O.
ther a Given or Broadcastaddress.
On reset, the SADDRand SADENregistersare initial-
The master can selectivelycommunicatewith groupsof ized to OOH,which defies the Given and Broadcast
slaves by using the Given Address. Addressing all Addressesas XXXX = (~ don’t-cares).‘fhiSas-
slaves at once is possiblewith the Broadcast Address. sures the 8XC51GBserial port to be backwardscom-
These addressesare definedfor each slave by two Spe- patibility with other MCS-51products which do not
cial Function Registers:SADDR and SADEN. implementAutomaticAddressing.

A slave’s individual addreas is specified in SADDR.

SADENis a maskbyte that definesdon’t-caresto form 8.4 BaudRates
the Given Address. These don’t-careaallow flexibility
in the user-defined protocol to address one or more The baud rate in ModeOis freed:
slavesat a time. The followingis an exampleof howthe
user could define Given Addresses to selectivelyad- OscillatorFrequency
Mode OBaudRate =
dreas different slavea. 12

Slave 1: The baud rate in Mode 2 dependson the value of bit

SADDR= 1111 0001 SMOD1 in Special Function Register PCON. If
SADEN= 1111 lOlO SMOD1 = O(which is the value on reset), the baud
rate is 1/64 the oscillatorr%quency.If SMOD1 = 1,
GIVEN= 1111 oxox the baud rate is 1/32 the oscillatorfrequency.
Slave2: Mode2 BaudRate = 2 SMOD1 x
OscillatorFrequency
SADDR= 1111 0011 e4
SADEN= 1111 1001
The baud rates in Mode 1 and Mode 3 are determined
GIVEN= 1111 Oxxl by the Timer 1 overflowrate, or by Timer 2 overtlow
rate, or by both (one for transmit and the other for
TheSADENbyteaare selectedsuch that each slavecan receive).
be addressed separately. Notice that bit 1 (LSB) is a
don’t-carefor Slave 1’sGivenAddreas, but bit 1 = 1
for Slave2. Thus, to selectivelycommunicatewithjust 8.5 Timer 1 to GenerateBaudRates
Slave1the master must sendan address with bit 1 = O
(e.g. 11110000).Similarly,bit 2 = Ofor Slave 1,but is WhenTimer 1 is used as the baud rate generator, the
a don’t-carefor Slave2. Nowto cmnmunicatewithjust baud ratea in Mcdes 1 and 3 are determined by the
Slave2 an address with bit 2 = 1 must be used (e.g. Timer 1 overtlowrate and the value of SMOD1as fol-
11110111).Finally, for a master to eornmunicate with lows:
both slavesat oncethe addreasmust havebit 1 = 1and
bit 2 = O. Timer 1 OverflowRate
#a~;&&md 3 = 2 SMOD1 X
32
Notice, however, that bit 3 is a don’t-care for both
slaves.
Thisallows
twoMerent addreasesto select Figure 28 showshow commonlyused Baud Rates may
both slaves (11110001 or 11110101). If a third slave be generated.The Timer 1 interrupt shouldbe disabled
was added that required its bit 3 = O,then the latter in this application.Timer 1can be configuredfor either
addreasmuld be used to communicatewith Slave1and “timer” or “counter” operation, and in any of its 3
2 but not Slave3. running modes. In most applications,it is configured
for “timer” operation in the auto-reload mode (high
The master can also communicate with all slavea at
oncewith the BroadcastAddress.It is formedfrom the
logicalOR of the SADDR and SADEN registers with

6-36
i~. 87C51GB HARDWARE DESCRIPTION

nibbleof TMOD = OO1OB).In this case,the baud rate 8.6 Timer2 to GenerateBaudRates
is-.
aivenby the formula:
Timer2 is sekted as the baud rate generatorby setting
Oscillator Frequancy TCLK snd/or RCLK in T2CON. Note that the baud
~~~~t~nd 3 = 2 SWlll X
32 X 12 X [25S– (THl)] rates for transmit and receive can be simultaneously
different.Setting RCLK snd/or TCLK puts Timer 2
One can achievevery low baud rates with Timer 1 by into its baud rate generator mode as shown in Figure
leavingthe Timer 1 interrupt ensbled,and configuring 29.
the Timer to run as a id-bit timer (high nibble of
TMOD = OOOIB), and using the Timer 1 interrupt to
do a id-bit softwarereload.

Timer 1
BaudRate F= SMOD
C—T Mode ReloadValue
ModeOMax:1 MHz 12MHz x x x x
Mode2 Max 375K 12MHz 1 x x x
Modes1 &3: 62.5K 12MHz 1 o 2 FFH
19.2K 11.059MHz 1 0 2 FDH
9.6K 11.059MHz 0 0 2 FDH
4.6K 11.059MHz 0 0 2 FAH
2.4K 11.059MHz 0 0 2 F4H
1.2K 11.059MHz 0 0 2 E6H
137.5 11.986MHz 0 0 2 lDH
110 6 MHz 0 0 2 72H
110 12MHz 0 0 1 FEEBH
Figure28.Timer1GeneratedCommonlyUeedBaudRatea

nwn 1
Ovawlaw
1

ma: osc msasavs4so eva sol 12.

ma -rLz

RX CLOCK
ma
------ lus

RCAPZH RCAPZL TX CLOCK

I I
r%%%
4

Tzaxml
-11 Hq+-El- ..TNER 2.
INTSRRUPT

CemRoL
Sxam

L Nols AwLsm.m*smnmML SXIERSAL INTSRSUP?

270S97-30

Figure29.Timer2 in BaudRateGeneratorMode

6-37
in~. 87C51GB HARDWARE DESCRIPTION

The baud rate generator modeis similarto the auto-re- Table 18Iistscommonlyusedbaud rates end how they
load mcde,in that a rolloverin TH2 causesthe Timer 2 can be obtainedfrom Timer 2.
registersto be reloadedwith the Id-bitvsduein registers
RCAP2Hand RCAP2L, whichare presetby software. It shouldbe noted that whenTimer 2 is running (TR2
= 1) in “timer” function in the baud rate generator
The baud rates in Modes 1 and 3 are determined by mode,oneshouldnot try to read or write TH2 or TL2.
Timer 2’soverflowrate as follows: Under these conditionsthe Timer is beingincremented
everystate time, and the results of a read or write may
Modes I and 3 = ~mer 2 ov~~ Rate not be accurate. The RCAP2registersmaybe read, but
BaudRates 16 shouldn’tbe written to, becausea writemight overlapa
reloadand cause write and/or reload errors. The timer
Timer2 canbecont@redfor either “timer” or “coun- shouldbe turned off (clear TR2) before accessingthe
ter” operation.In most applicati~ it is con@ured for Timer 2 or RCAP2 registers.
“timer” operation (C—T2 = O).The “Timer” opere-
tion is differentfor Timer 2 when it’s being used as a Table18, imer2 Ge erstedBaudRates
baudrats generator.Normally,es a timer, it increments Tilt r2
everymachinecycle(1/12 the osciUatorfrequency).As BaudRate F=
a baud rate generator, howwer, it increments every RCAP2H RCAP2L
state time (1/2the oscillator frequency).The baud rate
formulais givenbelow: 375K 12MHz FFH FFH
9.6K 12MHz FFH D9H
Mcdaa
1 and 3. OscillatorFrsqueney 4.8K 12MHz FFH B2H
BaudRate 32 x [65536 - (RCAP2H,RCAP2L)] 2.4K 12MHz FFH 64H
1.2K 12MHz FEH C8H
where (RCAP2H, RCAP2L) is the content of 300 12 MHz FBH IEH
RCAP2Hand RCAP2L taken as a M-bitunsignedin- 110 12MHz F2H AFH
teger. 300 6 MHz FDH 6FH
110 6 MHz F9H 57H
Timer2 as a baud rate generatoris validonly if RCLK
and/or TCLK = 1 in T2CGN. Note that a rollover in
TH2 doesnot set TF2, end will not generatean inter-
rupt. Therefore,the Timer 2 interrupt doesnot have to 9.0 SERIALEXPANSIONPORT
be disabledwhen Timer 2 is in the baud rate generator
mode. Note too, that if EXEN2 is set, a l-to-O tran- The SerialExpansionPort (SEP) allowsa wide variety
sitionon the T2EXpin willset EXF2but willnot esuse of serially hosted peripherals to be connected to the
a reload from (RCAP2H, RCAP2L) to (TH2, TL2). 8XC51GB.The SEP has four programmable modes
Thus whenTimer 2 is in use as a baud rate gesmretor, and four clock options.There is a singlebi-directional
T2EX can be used as an extra external interrupt, if data pin (P4.1) and a clock output pin (P4.0). Data
desired. transfersconsistof 8 clockswith 8 bits of dati received
or transmitted.When not transmittingor receivingthe
data and clockuins are inactive.Thereare 3 SFRSM
ciated with the’SEP as shownin Figure 30.

(MSB) ‘ (LSB) sEmN

— SEPE , SEPREN, CLKPOL, CLKPH , SEPS1 BEPSO
OD7H

(MSB) (LSB)
6EPSTAT
— — , SEPFWR, SEPFRD SEPIF
I t , OF7H
I
Figure30.SEPSFRS

6-%
i~. 87C51GB HARDWARE DESCRIPTION

None of the SEP SFRSare bit addressable.However, Table19.Determination’of

SEPModes
the individualbits of SEPSTATand SEPCONare sig-
nificantand have symbolicnamesassociatedwith them CLKPOL CLKPH SEPMode 1
as shown.The meaning of these bits are: 0 0 SEPMODEO
SEPE — SEP Enablebit o 1 SEPMODE1“
SEPREN— SEP ReceiveENable 1 0 SEPMODE2
1 1 SEPMODE3*
CLKPOL— CLOCKPOLarity
CLKPH — CLOCKPHaae
Thefour clockoptionsdeterminethe rate at whichdata
SEPS1 — SEP Speedselect 1 is shifted out of or into the SEP. All four rates are
SEPSO — SEP SpeedselectO fractionsof the oscillatorfrequency.Table 20showsthe
SEPFWR— SEP Fault during WRite variousrates that can be sel&tecfor the SEP.
SEPFRD — SEP Fault during ReaD Tabfe20. SEPDataRates
SEPIF — SEP Interrupt Flag

9.1 ProgrammableModesand
ClockOptions
The four programmablemodes deterrmn “ e the inactive m
level of the clock pin and which edge of the clock is
used for transmission or reception.These four modes
are shownin Figure 31.Table 19showshowthe modes
are determined.

SEPMODEO CLOCK
....~....

SEPMOOE2 CLOCK
—---~---—

“TAsAMPLED
~
DATAOUTPUT —

“ SEPMOOE1 CLOCK
—...~....

“ SEPMODE3 CLOCK
—“--~---—

Figure31.SEPModes

6-39
intd. 87C51GB HARDWARE DESCRIPTION

9.2 SEPTransmissionor Reception rupt maystillbeserviced,evenaftera softwareupset.

TomakethebmtuseoftheWDT,it shouldbeserviced
To trananu“tor receivea byte the user shouldinitialize in those sectionsof code that will periodicallybe exe
the SEPmode(CLKPOLand CLKPH), clockfrequen- cutexiwithinthe time requiredto preventa WDT reset.
cy (SEPS1and SEPSO),and enablethe SEP(SEPE).A
transmission then occurs if the user loads data into
SEPDATA. A reception occurs if the user seta 10.2 ~fT DuringPowerDownand
SEPREN while SEPDATA is empty and a trammrs “.
aion is not in progress.When 8 bits have beenreceived
SEPREN willbe clearedby hardware. Once the trans- InPowerDownmodethe oscillatorstops,whichmeans
mission or reception is mmple@ SEPIF wiUbe set. the WDT also stops. While in Power Down the user
SEPIF remainsset until cleared by software.SEPIF is dces not needto servicethe WDT.There are two meth-
also the sourceof the SEP interrupt. Data is transmit- ods of exiting Power Down: by a reset or via a level
ted and rSCeiVed MSBfirst. activated externrdinterrupt which is enabled prior to
entering Power Down. If Power Down is exited with
If the user attempts to read or write the SEPDATA rest, servicingof the WDT shouldoccur as it normally
register or writeto the SEPCONregister whilethe SEP does wheneverthe 8XC51GBis reset. Exiting Power
is transmitting or receiving an error bit is set. The Down with art interrupt is significantlydifferent. The
SEPFWRbit is set if the action occurred whilethe SEP interruptis held low which brings the device out of
was transmitting.The SEPFRD bit is set if the action Power Down and starts the oscillator. The user must
occurred whilethe SEP was receiving.There is no in- hold the interrupt lowlong enoughfor the oscillatorto
terrupt associatedwith these error bits. The bit remains stabilise.Whenthe interrupt is broughthigh,the inter-
set until cleared by aotlware. The attempted read or rupt ia serviced.To prevent the WDT from resetting
write of the registeris ignored.The receptionof trans- the devicewhilethe interrupt pin is held low,the WDT
missionthat was in progresswill not be affected. is not started until the interrupt is pulled high. It is
suggestedthat the WDT be react during the interrupt
seMce routine for the interrupt used to exit Power
10.0 HARDWAREWATCHDOGTIMER Down.

The hardware WatchDog Timer (WDT) rmets the To ensure that the WDT doea not overflowwithin a
gXC51GBwhenit overflows.The WDT is intendedas fewstates of exitingof powerdown,it is beatto reset the
a recoverymethodin situationswhere the CPU maybe WDT just beforeenteringpowerdown.
subjectedto a softwareupset. The WDT consists of a
14-bit counter and the WatchDog Timer ReSeT In Idle mode, the oscillator continues to rum To pre-
(WDTRST)SFR. The WDT is alwaysenabledand in- vent the WDT from resetting the 8XC51GBwhile in
crements while the oscillator is running. There is no Idle, the user should always set up a timer that will
wayto disablethe WDT.This means that the user must periodicallyexit MI%service the WDT, and re-enter
still service the WDT while testing or debuggingan Idle mcde.
appli~tion. The WDT is loaded tith o Whm the
8XC51GBexits reset. The WDT describd in this sec-
tion is not the WatchdogTimer associatedwith PCA 11.0 OSCILLATORFAIL DETECT
module4. The WDT does not drive the Reset pin.
The Oscillator Fail Detect (OFD) circuitry keeps the
8XC51GBin reset when the oscillator speed is below
10.1 Usingthe WDT the OFD triggerfrequency.The OFD triggerfrequency
is shown in the data sheet as a minimum and maxi-
Since the WDT is automatically enabled while the mum. If the oscillatorfrequencyis belowthe minimum,
processor is running, the user only needs to be con- the deviceis held in reset. If the oscillatorfrequencyis
cerned with servicingit. The 14-bitcounter overflows greater thsn the tnsximtunjthe device willnot be held
whenit rcachcs 16383(3FFFH). The WDT increments in reset. If the frequencyis betweenthe minimumand
once every machine cycle. This means the user must maximum,it is indeterminatewhether the device will
reaet the WDT at least every 16383machinecycles.If be held in reset or not.
the user does not wish to use the functionalityof the
WDT in an application,a timer interrupt can be used The OFD is automatically enabled when the device
to reset the WDT. To reset the WDT the user must corneaout of reset or when PowerDown is exitedwith
write OIEH and OEIH to WDTRST. WDTRST is a a reset or an interrupt.
write onlyregister.The WDT count cannotbe read or
written. Usinga timer interrupt is not recommendedin The OFD is intended to function only in situations
aPPfimtiomthat make use of the WDT becauseinter- where there
is a grossfailure of the oscillator,such as a

6-40
int# 87C51GB HARDWARE DESCRIPTION

broken crystal. To fultillthis need the OFD trigger fre-

quencyis significantlybelowthe normal operatingt%-
quency. The OFD will not reset the 8XC51GBif the
oscillator frequencyshould change to another point
within the operatingrange.

11.1 OFDDuringPowerDown
In Power Down, the 8XC51GBoscillator stops in or-
der to conservepower.To prevent the 8XC51GBfrom
immediately resetting itself out of power down the
OFD must be disabledprior to settingthe PD bit. Writ-
ing the sequence “OEIH, OIEH” to the Oscillator
(OSCR) SFR, turns the OFD off. Once disabl~ the
‘+
To
OFD can only be re-enabledby a reset or exit from
Power Down with an interrupt. The status of the OFD m-)’ 0
Kf

-’-ii
(whether on or otl) can be determined by reading
OSCR. The LSBindicatesthe status of the OFD. The
upper 7 bits of OSCRwill alwaysbe 1s when read. If
OSCR = OFFH, the OFD is enabled. If OSCR =
OFEH.the OFD is disabled.

12.0 INTERRUPTS
The 8XC51GBhasa—— total of 15interrupt vectors:seven
external interrupts (INTO,INT1, INT2, INT3, INT4,
INT5, and INT6), three timer illterrUpt3(TimersO, 1,
and 2), two PCA interrupts(PCAOand PCA1),the A/
D interrupt, the SEP interrupt, and the serial port in-
--A
terrupt. Figure 32showsthe interrupt sources. ‘1-
All of the bits that generate interrupts can be set or
cleared by software,with the same result as though it
had beenset or clearedby hardware.That is, interrupts
can be generatedor pendinginterrupts can be canceled
,.32
in software. ‘1-

12.1 ExternalInterrupts
——
External Interrupts INTOand INT1 can each be either
level-activatedor negativeedge-triggered,dependingon
bits ITOand ITl in register TCON. If ITx = O,exter-
nal interrupt x is triggered by a detected low at the
INTx pin. If ITx = 1, external interrupt x is negative

=i5-
edge-triggered.
CF1
INT2 and INT3 can each be either negativeor positive
edge-trigger@ dependingon bits IT2 and IT3 in regia-
ter EXICON. IfITx = O,externalintermptx is nega-
tiveedge-triggered.
If ITx = I, externalinterruptx is
positiveedge-triggered.
INT4, INT5, and INT6 are pmitive edge-triggered
only.
270897-32 I
Figure32. InterruptSources

6-41
i~. 87C51GB HARDWARE DESCRIPTION

Table21.EXICON:ExternalInterruptControlRegister

EXICON ResetValue= XOOO OOOOB

Address= O(%H NotBitAddressable
Bit 7 6 5 4 3 2 1 0
EXICON — IE6 IE5 IE4 IE3 IE2 IT3 IT2
Symbol Function
— Notimplemented, reserved forfutureuse.*
IE6 interrupt
6 Edgeffag.Thisbitissetbyhardware whenanexternalinterruptedge
isdetected.
IE5 Interrupt
5 Edgeflag.Thisbitissetbyhardware whenanexternalinterruptedge
isdetected.
IE4 interrupt
4 Edgeflag.Thisbitissetbyhardware whenanexternalinterruptedge
isdetected.
IE3 Interrupt
3 Edgeflag.Thisbitissetbyhardware whenanerrternalinterrupt
edge
isdetected.
IE2 Interrupt
2 Edgeflag.Thisbitissetbyhardware whenanexternalinterruptedge
isdetected.
IT3 Interrupt
3 Typecontrolbit.Thisbitissetorclearedbysoftwaretocontrol
whetherINT3ispositiveornegative transitionactivated.WhenIT3ishigh,IE3is
setbya positive
transition
onpinINT3.WhenIT3islow,IE3issetbya negative
transition
onpinINT3.
IT2 Interrupt
2 Typecontrolbit.Thisbitissetorclearedbysoftwaretocontrol
wheth&lNT2iapositive ornegativetransition activated.WhenIT2ishigh,IE2is
setbya positive
transition
onpinINT2.WhenIT2islow,IE2issetbya negative
transition
onpinINT2.
“UsingsoftwareshouldnotwriteIs toreserved
bits.ThaaebitsmaybeusadinfutureS051family
Products
toinvoke

Inewf&tures. Inthatcase,theresetorinactive
readfromresewed btiisindeterminate.
valueofthenewbtiwillbeO,anditsactive
value-will
be1,Thevalue

The flagsthatactuallygeneratethe interrupts are bits extemsl interrupt is transition-activata the external
IEOand IE1 in TCON and IQ IE3, IE4, IE5, and IE6 sourcehas to hold the request pin high for at least one
in EXICON.These flagsare clearedby hardwarewhen cycle, and then hold it low for at least one cycle to
the service routine is vectoredto if the interrupt was ensure that the transition is seen so that interrupt re-
transition-activated.If the interruptwas level-activated, quest flag IEx will be set. IEx will be automatically
then the external requestingsourceis what controlsthe clearedby the CPU when the serviceroutine is called.
requestflag, rather than the on-chiphardware. The ex-
ternrd interrupts are enabled through bits EXO and If external interrupt INTOor ~ is level-activated,
EXl in the IE register and EX2,EX3, EX4, EX5, and the external source has to hold the request active until
EX6 in the IEA register. the requested interrupt is actually generated. Then it
has to deactivate the request beforethe interrupt serv-
Sincethe external interrupt pinsare sampledonce each ice routine is completed,or elseanother interrupt will
machinecycle an input highor low shouldhold for at be generated.
least 12 oscillator periods to ensure sampling. If the

642
i~. 87C51GB HARDWARE DESCRIPTION

12.2 Timer Interrupts The PCA interrupt is enabledby bit EC in the 333regis-
ter. The PCA1 interrupt is enabled by bit EC1 in the
Tinter Oand Tinter 1 interrupts are generated by TFO IEA register. In addition, the CF (CF1) flag and each
and TF1 in register TCON, whichare set by a rollover of the CCFn (CICFn) flags mustalso beindividually
itstheir respectiveTimer/Counter registers; the excep enabledby bits ECF (13CFl)and ECCFn(ECICFn) in
tion is Timer Oin Mode 3. When a timer interrupt is registers CMOD (CIMOD) and CCAPMn
generated, the tlag that generatedit is cleared by the (CICAPMn), respectively,in order for that tlag to be
on-chiphardware when the serviceroutine is vectored able to causean interrupt.
to. These timer interrupts are enabledby bits ETOand
ET1 in the IE register.
12.4 SerialPort Interrupt
Timer 2 interrupt is generatedby the logicalOR of bits
TF2 and EXF2 in register T2CON. Neither of these The serialport interrupt is generatedby the logicalOR
*is cl~~ by hardwarewh~ the servieeroutke is of bits RI and TXits register SCON. Neither of these
vectored to. In fact, the serviceroutine may have to tlags is clearedby hardware when the servieeroutine is
determm “ e whethexit was TF2 or EXF2 that generated veetoredto. The serviee routine will normallyhave to
the interrupt, and the bit will have to be cleared in determine whether it was RI or TI that generatedthe
software.The Timer 2 interrupt is enabled by the ET2 interrup~ and the bit will have to be cleared in sofi-
bit in the IE register. ware. The serial port interrupt is enabledby bit ES in
the IE register.

12.3 PCA Interrupt

12.5 InterruptEnable
The PCA interrupts are generatedby the IogiealOR of
five event tlags (CCFn, CICFn) and the PCA timer Each of these interrupt sourecs can be individuallyen-
oveflow flag (CF, CF1) in the registers CCON and abled or disabled by setting or clearing a bit in the
ClCON. None of these tlags are cleared by hardware Interrupt Enable (3)3and IEA) registemas shown in
when the seMce routine is vectoredto. Normally the Table 22. Note that IE also contains a global disable
serviceroutine will have to determinewhichbit flagged bit, EA. If EA is set (l), the interrupts are individually
the interrupt and clear that bit in software.This allows enabkd or disabled by their correspondingbits in IE
the user to define the priority of servieing each PCA and IEA. If EA is clear (0), all interrupts are disabled.
module. Figure 33 showsthe interrupt control system.

6-43
in~. 87C51GB HARDWARE DESCRIPTION

Il@hti
F Prbrny
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,,.:.,.,.....,:,
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Figure33.InterruptControlSystem

644
i@ 87C51GB HARDWARE DESCRIPTION

Table22.InterruptEnable Registers

Address= OA8H ResetValue= 000000006

BitAddressable
EA EC I ET2 ] ES ETl Exl Ho EXO
Bit 7 6 5 4 3 2 I o
IEA Address= OA7H ResetValue= 0000OOOOB

Not BitAddressable
EAD EX6 I EX5 EX4 EX3 EX2 EC1 I ESEP
Bit 7 6 5 4 3 2 1 0

Enablebit = 1 enablesthe interrupt

Enablebit = Odisablesthe interrupt

Symbol Function
EA Globaldisablebit.If EA=O,allInterrupts
aredisabled.If EA= 1,eachInterrupt
canbe
individually
enabledordisabled bysettingorclearing
itsenablebit.
EC PCAinterrupt enable bit.
ET2 Timer 2 interrupt enable bit
ES Serial Port interrupt enable bit.
ETl Timer 1 interrupt enable bit.
EX1 External interrupt 1 enable bit.
ETo Timer O interrupt enablebit.
EXO ExternalinterruptOenablebit.
EAD A/D converter interrupt
enablebit.
EX6 Externalinterrupt6 enablebit.
EX5 Externalinterrupt5 enablebit.
EX4 Externalinterrupt4 enablebit.
EX3 Externalinterrupt3 enablebit.
EX2 Externalintemspt 2 enablebit.
EC1 PCA1interrupt enablebit.
ESEP SerialExpansion Portinterrupt enablebit.

12.6 InterruptPriorities A low-priorityinterrupt oan itself be interrupted by a

higher mioritv interruut. but not by another interrtmt
Each interrupt source on the 8XC51GBesn be individ- of~he&ne priority.fie”highest pti&ity interrupt*-
uallyprogrammed to one of four prioritylevels,by set- not be interrupted by any other interrupt source.
ting or c1earing the bits in the Interrupt Priority (IP
and IPA) registers and the Interrupt PriorityHigh If twoor morerequestsof differentprioritylevelsare
(IPHend IPAH) registers. SeeTable23. The IPH reg- receivedsimultaneously,the requestof higher priority
istershavethesame bit mapas the IP registerswith an level is seMced.If requestsof thessmeprioritylevel
“H” addedto each bit’s name.This giveseach interrupt are receivedsimultaneously, an internal polling se-
source two bits for setting the priority levels.The LSB quence determines which request is serviced. Thus
of the Priority Seleet Bits is in the 1P S~ and the within each priority lewelthere is a second priority
MSBis in the IPH SFR. structure deterrmn
“ ed by the pollingsequeneeshownin
Table 24.

6-45
i~. 87C51GB
HARDWARE
DESCRIPTION

Table23.InterruptPriorityRegisters

1P Address= OB8H ResetValue= XOOO

OOOOB
BitAd&esesble
— PPC I PT2 ] PS PT1 Pxl PTo Pxo
1
IPA Address= OB8H ResetValue= 0000OOOOB
NotBitAddressable
PAD I PX6 PX5 I PX4 PX3 PX2 PCI I PSEP
IPH Address= OB7H ResetValue= XOOO
00006

NotBitAddressable
— PPPC PT2H PSH PTIH PXIH PTOH PXOH
I
IPHA Address= OB5H ResetValue= 0000OOOOB
NotBitAddressable
PADH PX6H PX5H PX4H PX3H PX2H PCIH PSEP

PriorityBit I PriorityBitH I Priority I

o 0 Lowest
o 1
1 0
1 1 Hiahest

Symbol Function
— NotImplemented, reserved for future use*
PPC,PPCH PCA interrupt priority bits
PT2,PT2H Timer 2 interrupt priority bits
PS,PSH Serial Port interrupt priority bits
PT1,PTIH Timer 1 interrupt priority bits
PX1,PXIH External intermpt 1 interrupt priority bits
PTO,PTOH Timer O intenupt priority bits
PXO,PXOH External interrupt O interrupt priority bits
PAD,PADH A/D converter interruptpriority
bits
PX6,PX6H External
interrupt 6 interrupt
prioritybits
PX5,PX5H External
interrupt 5 interrupt
prioritybits
PX4,PX4H Externalinterrupt4 interrupt
prioritybits
PX3,PX3H Externalinterrupt3 interrupt
prioritybits
PX2,PX2H EXtOfrtSl
interrupt2 interrupt
prioritybits
PCl, PCIH PCAIintermptpriority bits
PSEP,PSEPH SerialExpansion Portinterrupt priority
bits
NOTE:
‘IJser software should not write Is to resewed bits. These bits may be used in future 8051 family products to invoke
new features. In that case, thereset orinaotive
valueof the new bit will be O, and h active value will be 1. The value
read from a resewed bit is indeterminate.

6-46
in~o 87C51GB HARDWARE DESCRIPTION

Table24.InterruptPollingSequence not being respondedto for one of the aboveconditions

and is not still active when the blockingcondition is
1 (Highest) INTO removed the denied interruptwill not be serviced. In
2 SEP other word$ the fact that the interrupt f&g was once
3 INT2 active but not servicedis not remembered.Every poll-
4 TimerO ing cycle is new.
5 PCAI
6 INT3 T’hepollingcycle/LCALLsequenceis illustrated in the
7 m Interrupt ResponseTimingDisgrarn.
6 AfD
Note that if an interrupt of a higher priority level goes
9 INT4 active prior to S5P2of the machinecyclelabeledC3 in
10 Timer1 the diagram, then in accordancewith the aboverules it
11 PCA will be vectoredto during C5 and C6, without any in-
12 INT5 struction of the lowerpriorityroutine havingbeen exe-
13 PCA cuted. This is the fastest possibleresponsewhen C2 is
14 Timer2 the tinal cycle of an instruction other than RETI or
15 (Lowest) INT6 write IE or 1P.

Thus the processoracknowledgesan interrupt request

Note that the “miority within level” structure is OtdY by executinga hardware-generatedLCALLto the ap-
used to resolves-tiul~eous requestsof the sameprior- propriate servicing routine. The hardware-generated
ity level. LCALL pushes the contents of the Program Counter
onto the stack (but it does not save the PSW) and re-
loads the PC with an address that depends on the
12.7 InterruptProcessing source of the interrupt being vectored to. Table 25
shows the interrupt vectoraddresses.
The interrupt flags are sampled at S5P2 of every mac-
hine cycle. The samplesare polled during the follow- Table25.InternmtVeotorAddresses
ing machine cycle. The Timer 2 overflowinterrupt is
slightly dif%rent, ss described in the Interrupt Re- Interrupt Interrupt Clearedby Vector
sponse Time section. If one of the flags was in a set Souroa RequestBite Hardware Addraae
condition at S5P2 of the preceding cycle+the polling No(level) OO03H
cycle will find it and the interrupt system will generate m IEO
so LCALLto the appropriateserviceroutine, provided Yes(trans.)
this hardwsre-generatedLCALLis not blockedby any I TimerO I TFO I Yes I OOOBH!
of the followingconditions:
1. An interrupt of equal or higher priority level is al-
m IE1 No(level) O013H
resdy in progress. Yes(trans.)
2. The current (polling)cycle is not the final cycle in Timer1 TF1 Yes OOIBH
the executionof the instructionin progress. SerialPortI Rl,TI No O023H
3. The instruction in progressis RETI or any write to
the IE or 1P registers. Timer2 TF2,EXF2 No O02BH

Any of these three conditionswill block the generation

of the LCALL to the interrupt serviceroutine. Condi-
tion 2 ensures that the instruction in progress will be
completedbeforevect*g to any serviceroutine. Con-
dition 3 ensures that f the instruction in progress is
RETIor anywriteto IE or 1P,thenat leastonemore
instructionwillbe executedbeforeany interrupt is vec- SEP SEPIF No O04BH
tored to. INT2 IE2 Yes O053H
The pollingcycle is repeatedwith each machine cycle, INT3 IE3 Yes O05BH
and the valuespolledare the valuesthat were presentat
S5P2 of the previous machine cycle. If the interrupt INT4 IE4 Yes O063H
flag for a level-sensitiveexternal interrupt is active but INT5 IE5 Yes O06BH
I INT6 I IE6 ! Yes I O073H I

6-47
htdo 87C51GB HARDWARE DESCRIPTION

Executionproceedsfrom that locationuntil the RETI TheTimerOand Timer 1flags,TFOend TFl, are set at
instruction is encountered.The RETI instruction in- S5P2 of the cycle in which the timers overtlow. The
forms the processor that this interrupt routine is no valuesare then polledby the circuitryin the next cycle.
longerin progr~ then popsthe top twobytmfrom the However,the Timer 2 fisg TF2 is set at S2P2 and is
stack end reloads the Program Counter. Executionof polledin the same cycle in whichthe timer overflows.
the interrupted program continuesfrom where it left
off. Ifa requestis active and conditionsare right for it to be
acknowledged,a hardware subroutine cell to the re-
Note that a simple RET instruction would also have questedserviceroutine willbe the nextinstruction to be
returned executionto the interrupted program, but it executed.The call itself tekes two cycles.Thus, a mini-
would have I& the interrupt control system thinking mum of three completemachinecycleselapsesbetween
interrupt was still in progress. activationof an external interrupt request end the tre-
ginningof execution of the service routine’s first in-
The starting addrrsses of consecutiveinterrupt service struction.See FQure 34.
routines are only 8 byteaapart. That meens if consecu-
tive interruptaare beingused (IEOand TFO,for examp- A longer response time would result if the request is
le, or TFOand IE1),end if the first interrupt routineis blockedby one of the 3 conditionsdiscussedin the In-
more than 7 bytes long,then that routine will have to terrupt Proccesingsection. If en interrupt of equal or
execute a jump to some other memorylocation where higherprioritylevelis alreadyin progress,the addition-
the service routine can be completedwithout overlap al wait time obviouslydepends on the nature of the
ping the sterting address of the next interrupt routine other interrupt’s service routine. If the instruction in
progressis not in its finalcycle,the additionalwait time
cannotbe more than 3 cycles,sincethe longestinstruc-
12.8 InterruptResponseTime tions (MULand DIV) are only4 cycleslon~ and if the
instructionin progressis RETI or writeto IE or 1P, the
The ~ end INT1 levels are inverted and latched additionalweit time carmot be more than 5 cycles (a
into the Interrupt Flags IEO,and IE1 at S5P2of every maximumof one or more cycleeto complete the in-
machine cycle. The level of interrupts 2 through 6 are structionin progrewAplus 4 cyclesto completethe next
also latched into the appropriate flags (IE2-IE6) in instructionif the instruction is MUL or DIV).
S5P2.Similarly,the Timer 2 tlag EXF2 and the Serial
Port flagsRI and IT are set at S5P2.The valuesare not Thus, in a single-interruptsys~ the response time is
actually polledby the circuitry until the next machine always more than 3 cycles andlessthan9 cycles.
cycle.

.....
l-t
INTERRUPT
e
INTERRUPT
INTERRUPTS
ARE POLLED
LONG CALLTO
INTSRRUPT
VEC!TORAOORESS
INTERRUP7ROUNNE

GOES LATCHED
ACTIVE
270SS7-S4
This is the fastest possibleresponsewhen C2 is the final cycle of an instructionother then RETI or write IE or 1P.

Figure
34.InterruptResponseliming Disgrsm

6-46
i@. 87C51GB HARDWARE DESCRIPTION

13.0 RESET When power is turned on, the circuit holds the
RESETpin high for an amountof time that dependson
The resetinput is the RESETpin, whichhas a Schmitt the capacitorvalue and the rate at whichit charges.To
Trigger input. A reset is accomplishedby holding the ensurea valid reset the RESET pin must be held low
RESET pin low for at least two machine cycles (24 longenoughto allow the oscillatorto start up plus two
oscillator periods). On the 8XC51GB,reset is asyn- machinecycles.
chronousto the CPU clock. This meansthat the oacil-
Iator doesnot have to be runningfor the I/O pins to be On power up, Vcc should rise within approximately
in their reset condition.However,VW has to be within ten milhseconda. The oscillator start-up time will de-
the specitiedoperating conditions. pendon the oscillatorfrequency.For a 10MHz crystal,
the start-uptime is typically1rns.For a 1MHz crystal,
Once Reset has reached a high level, the 8XC51GB the start-up time is typically 10ms.
may remainin its reset state for up to 5 machinecycles.
This is causedby the OFD circuitry. Poweringup the device without a valid reset could
cause the CPU to start executinginstructionsfrom ass
While the RESET pin is low, the port pins, ALE and indeterminatelocation. This is becausethe SFRS,spe-
PSEN are weakly pulled high. After RESET is pulled oiticslly the Program Counter, may not get properly
~it ~ take Upto 5 machinecyclesfor ALE md inidalized.
PSEN to start clocking.For this reason, other devices
can not be synchronizedto the internal timings of the
8XC51GB. 14.0 POWER-SAVINGMODES
Driving the ALE and PSEN pins to O while reaet is For applicationswhere power consumptionis critic+d,
active could cause the deviceto go into an indetermi- the 8XC51GBprovideatwo power reducingmodes of
nate state. operation:Idle and Power Down. The input through
which backup power is supplied during these opera-
The internal reset algorithm redefines most of the tions is VCC.The Idle and Power Down modes are
SFRS.Refer to individualSFRSfor their reset values. activatedby setting bits IDL and PD, respectively,in
The internal W is not affectedby reset. On power the SFR PCON (Table 26). Figure 36 showsthe Idle
up the RAM content is indeterminate. and power Down CirCUitry.

In the Idle mode(IDL = 1),the oscillatorcontinuesto

13.1 Power-OnReset run and the InterrupL Serial Port, PCA, and Timer
blockscontinue to be clocked,but the clock signal is
For CHMOSdevices,whenVCCis turned om an auto- gated off to the CPU. In Power Down (PD = 1), the
matic reset can be obtained by connecting the oscillatoris frozen.
RE3ET pin to V~ through a 1 pF capacitor. The
CHMOSdevicesdo not require an externalresistor like
the HMOSdevicesbecausethey havean internal pullup
on the= pin. Figure 35 showsthis.

a
Vcc

ii5i Vcc
+
1 /br 8XC51GS

%s

Vss
27C$.97-35

Figure 35. Power-OnReeetCircuitry

6-49
intel. 87C51GB HARDWARE DESCRIPTION

Table26.PCON:PowerControlRe9ieter

PCON Address= 87H ResetValue= OOXX

OOOOB

NotBitAddressable
SMOD1SMODO — ] POF GF1 GFO PD IDL
Bit 7 6 5 4 3 2 1 0
Symbol Function
SMOD1 DoubleBaudratebit.Whensettoa 1 andTimer1isusedto generate baud rates, and the
Serial Portisusedinmodes1,2, or3.

SMODO Whenset,Read/Writeacceasesto SCON.7aretotheFEbit.Whenclear,Read/Write

accesses toSCON.7aretotheSMObit.
— Notimplemented, reservedforfutureuse.*
POF PowerOffFlag.Setbyhardware onthetisingedgeofVCC.Setorclearedbysoftware. This
flagallowsdetectionofa powerfailurecausedreset.VcCmustremainabove3Vto retain
thisbit.
GF1 Generel-purpoee flagbit.
GFO General-purpose flagbit.
PD PowerDownbit.Settingthisbitactivates PowerDownoperation.
IDL Idlemodebit.Settingthisbt activatesidlemodesoperation.
If 1sarewrittento PDandIDLatthesametime,PDtakesprecedence.
NOTE
*Ueersoftware
should
notwriteIs tounimplemented
bits.These bite maybe used in futureS051 familyproduotsto
invokenew features. In that case, the reset or inactivevalue of the new bh will be O, and its active value will be 1.
The value read from a raeervad bil is indeterminate.

KI m
xTAL 2 s X7AL 1

Oac
INTSRRUPT,
DSSRIALPORT,
TIMER SLOCKS

Cw
E

=
270S97-36

Figure36.IdleandPowerDownHardware

6-50
int# 87C51GB HARDWARE DESCRIPTION

14.1 IdleMode 14.2 PowerDownMode

An instruction that sets the IDL bit csuaes that to be An instructionthat sets the PD bit causesthat to be the
the last instructionexecutedbefore goinginto the Idle last instruction executed before going into the Power
mode. In the Idle mode, the internal clock signal is Down mode. In this mode the on-chip oscillator is
gated off to the CPU, but not to the IntermpL Timer, stopped. With the clock frosen, all functions are
and Serial Port functions.The PCA and PCA1 timers stopped, but the on-chip RAM and S- Function
Canbe programmed either to pause or continueoperat- Registersare held.The port pinsoutput the valuesheld
ing during Idle with the CIDL (CIIDL) bit in CMOD by their respectiveSFRS,and ALE and PSEN output
(CIMOD). The CPU ststus is preservedin its entirety: lows.In PowerDown,VW can be reducedto as lowas
the Stack Pointer, Program Counter, Program Status 2V.Care must be taken, however,to ensurethat VCCis
Word, Accumulator, and all other registers rttaintsin not reduced beforePower Down is invoked.If the Os-
their data during Idle. The port pins hold the logical cillator Fail Detect circuitry is not disabledbefore en-
states they had at the time Idle was activated.ALE and tering powerdown,the part will met itself (seeSection
PSEN hold at logichigh levels.Refer to Table 27. 11.0 “oscillator Fail Detect”). Table 28 shows the
status of externrdpins during Power Down mode.
Table27.Statusof the ExternalPins
duringidieMode Tabie28.Statusof the ErrtemsiPine
duringPowerDown Mode
Pwrsm ALE ~ Ports
porto Port1 Port2 345
Memory ,,
Internal 1 1 Date Data Data Data
Extemai 1 1 Fiost Data Address Data internal O 0 Date Data Data Date
External O 0 Fioat Data Date Date
Thereare two waysto terminatethe Idle Mode.Activa-
tion of any enabledinterrupt will cause the IDL bit to The 8XC51GBcan exit Power Down with either a
be C]=ed by hardware terminatingthe Idle mode.The hardware reset or external interrupt. Reset redetines
interrupt willbe serviced,and foUowingRETI the next most of the SFRSbut does not change the on-chip
instructionto be executedwill be the one followingthe RAM. An externalinterrupt allowsboth the SFRSand
instruction that put the deviceinto Idle. the on-chipRAM to retain their values.

The flag bits (GFUand GF1 in PCON) can be used to To properly terminatePower Downthe reset or exter-
giveso indicationif an interrupt occurred during nor- nal interrupt shouldnot be executedbefore VCCis re-
mal operationor during Idle. For example,an ittstruc- stored to its normal operating level and must be held
tion that activatesIdle can also set one or both flagbits. active long enoughfor the oscillatorto restart and sta-
When Idle is terminated by an interrupt, the interrupt bilize (normallylessthan 10ins).
serviceroutine can examine the flag bits.
With so externalinterrupt, ~0 or INTI must be en-
The other way of terminatingthe Idle mode is with a abledand con@uredas level-sensitive.Holdingthe pin
hardware reset. Since the clock oscillator is still run- low restarts the oscillator and bringing the pin back
ning,the hardwareresetneedsto be held activefor only high completesthe exit. After the RETI instruction is
two machinecycles(24 oscillator periods)to complete executed in the interrupt service routine, the next in-
the reaet. struction will be the one followingthe instructionthat
put the devicein Power Down.
The signalat the RESETpin clears the IDL bit directly
and asynchronously.At this time the CPU resumes
programexecutionfrom where it left off;that ~ at the 14.3 PowerOff Flag
instruction followingthe one that invokedthe Idle
Mode.Asshownin the ResetTimingdiagram,twoor ThePowerOffFlag(PW) locatedat PCON,4issetby
threemachinecyclesof programexecutionmaytake hardware whenVCCrises fromOVto 5V.POFcartdSO
placebeforetheinternalreactalgorithmtakescontrol. be set or cleared by software. This allows the user to
On-chiphardwareinhibitsaccessto the internrdRAM distinguishbetweena “cold start” reset and a “warm
duringthis time,but accessto the port pins is not inhib- start” reset.
ited. To eliminatethe possibilityof unexpectedoutputs
at the port pins, the instruction followingthe one that A cold stsrt reset is one that is coincident with Vcc
invokesIdle shouldnot be one that writes to a port pin beingturned on to the deviceafter it was turned off.A
or to external Data IWM. warm stsrt resetoccurswhileVCCis still appliedto the
deviu and could be generated, for axamplej by a
WatchdogTimer or an exit from Power Down.

6-51
intd. 87C51GBHARDWAREDESCRIPTION

Immediatelyafter reset, the user’s software can check Table29.EPROM/OTPLockBite

the status of the POF bit. POF = 1 worddindicate a
cold start. The Aware then clears POF and corn- Program
mencea its tasks. POF = O immediately atler reset LockBite LogicEnabled
wouldindicatea warm start. LB1 LB2 LB3

Vcc must remainabove 3V for POF to retain a O.

Uuu No ProgramLockfeatures
enabled.(CodeVerifywillstill
beencrypted bythe
EncryptionArray.)
15.0 EPROM/OTPPROGRAMMING
Puu MOVCinstructions executed
The 8XC51GBuses the fast “Quick-Puke” Programm- fromexternalprogram
ing algorithm. The devices program at Vpp = memory aredisabledfrom
12.75V(and Vcc = 5.OV)usinga seriesof five 100pa fetchingcodebytesfrom
PROG pukes per byte programmed. internalmemory.EZ is
sampled andlatchedon
reset,andfurther
15.1 ProgramMemoryLock programming ofEPROMis
disabled.
Insomemicrocontroller
applicationsit is desirablethat
the Program Memorybe secure from softwarepiracy. PPU Sameasabove,butVerifyis
The 8XC51GBhas a three-levelprogram lock feature alsodisabled
(option
which protects the code of the on-chipEPROM/OTP available
onEPROMonly).
or ROM. PPP Sameasaboveandall
externalprogramexecution
is
Within the EPROM/OTP/ROM are 64 bytes of En- inhibited
andinternalRAM
CIYPti~ Array that are initially unprograrnmed (all oannotbereadexternally.
1s). The user can program the Encryption *Y to
encrypt the programeodebyteaduringEPROM/OTP/
ROM verification.The verification procedure is per- All other combinations of lock bits may produce indetermi-
formed as usual except that esoh code byte comesout nate resultsand shouldnot be used
exclusive-NOR’ed(XNOR) with one of the key bytes
Therefore,to read the ROM codethe user has to know
the 64 keybytesin their proper sequeru. 16.0 ONCE MODE
Unprogrammed bytes have the value OFFH.So if the The ONCE (ON-Circuit Emulation) mode facilitates
Encryption Array is left unprogramrned, all the key testing and debuggingof systemsusing the 8XC51GB
bytes have the value OFFH. Since any code byte without having to removethe dexieefrom the circuit.
XNORed with OFFHleaves the byte unchanged,leav- The ONCE mode is invokedby:
ing the EncryptionArray unprogrammedin effectby- 1.g ALE low whilethe deviceis in reset and
- the enWption feature. PSEN is high;
2. HoldingALE low as RST is deactivated.
PROGRAMLOCKBITS
While the deviceis in ONCE mode,the Port Opins go
Alsoincludedin the Program Lack scheme are three into a float state, and the other port pins, ALE, and
Lock Bits whichcan be programmedto disablecertain ~ are weakly pulled high. The oscillator circuit
functionsas shownin Table 29. remains active. While the &vice is in this mode, an
emulator or test CPU can be usedto drive the circuit.
TOobtain maximumsecurity of the on-boardprogram
and data, all 3 LockBits and the EncyptionArray must Normal operation is restored after a valid reset is ap-
be programmed. plied.
ErasingtheEPROMalsoerasesthe EncryptionArray
andthe Lock Bitsjreturningthe part to fullfunctionali- 17.0 ON-CHIP OSCILLATOR
ty.
The on-chiposcillatorfor the CHMOSdevicesconsists
of a single stage linear inverter intended for use as a

6-52
i~. 87C51GB HARDWARE DESCRIPTION

crystal-controlled,positivereactance oscillator. In this The crystal specificationsand capacitance valuea (Cl

application the crystal is operatingin its fundamental and C2 in Figure 39)are not critical. 30 pF can be used
responsemodess an inductivereactance in parallel rea- in these positions at any frequencywith good quality
onance with capacitanceexternalto the crystal. Figure crystals. In general, crystals used with these devices
37 showsthe on-chiposcillatorcircuitry. typicallyhave the followingspecifications:
The oscillatoron the CHMOSdevicescarIbe turned off ESR (EquivalentSeriesResistance)
under sotlware control by setting the PD bit in the 7.0 pF maximum
CO (shunt ~pti~-)
PCON register (Figure 38). The feedback reaistor Rf
shownin the figureconsistsof paralleln- and p-channel CL (loadcapacitance) 30pF *3 PF
PETs controll~ by the PD bit, such that Rf is opened Drive Level IMW
when PD = 1. The diodes+D1 and D2, which act as
clamps to VCCand V.S.S, are parasitic to tie Rf FETs.

Vcc
70 INrERNAL
nwffi CKTS
A

D1
l-l
XIALl

+%
270s97-37

Figure 37. On-Chip Osciiiator Circuitry

70 INlwtNAL
llmffi CK7S

f%

v=
-------- ~ALl----- XTAU ------
Wcal
~ QUAR7ZCRYSTAL
tb 4I OR CERANIC
:0: RSSONATOR

=
270S97-38

Figure38.UsingtheCHMOSOn-ChipOacillstor
6-53
intd. 87C51GBHARDWAREDESCRIPTION

There are no requirements on the duty cycle of the

external clock signal, since the input to the internal
cheking circuitry is through a divide-by-twofiipflop.
500 However,minimumand maximumhigh and low times
qao spsd%d in the data sheets must be observed.Refer to
x the External Clock Specificationsfor this information.
:s00
E
h extermd oscillator may encounter as much as a
z 2Ga 100pF loadat XTAL1 whenit starts up. This is due to
interaction betweenthe amplifierand its feedbackca-
100 pacitance. Once the external signalmeets the VII-.and
: :~
k’~ speeiticationa, the capacitarm will not exceed
20 pF.
4 8 12 16
CRYSTALFREQUENCVIn MHz
270897-39
18.0 CPU TIMING
Figure39.ESRvsFrequency The internal clock generator &tines the sequence of
. states that make up a machinecycle.A machine cycle
Frequency,tolerate% and temperaturerange are deter- consists of 6 ststea, numbered S1 through S6. Each
mined by the systemrequirements. state time lasts for two oscillator periods.‘fIms a nta-
chine cycle takes 12 oscillator periodsor 1 ps if the
A ceramic resonatorcan be used in place of the crystal oscillator frequencyis 12 MHs. Each state is then di-
in cost-sensitiveapplications.when a ceramic resona- videdinto a Phase 1 and Phase 2 half.
tor is used Cl and C2 are normallyselectedas higher
values,typicslly47 pF. The manufacturerof the ceram- Rise and fall times are dependenton the external load-
ic resonator shouldbe consultedfor recommendations ing that each pin must drive. They are approximately
on the values of theae capacitors. 10n$ measuredbetween0.8Vand 2.OV.
A more indepth discussionof crystal specifications,ce- Propagationdelaysare ditkent for differentpins. For
ramic reaonatom and the selectionof valuesfor Cl and a given pin they vary with pin loading,temperature,
C2 can be foundin ApplicationNote AP-155,“Oscilla- V~, and manufacturinglot. If the XTAL1waveform
tors for Micrmontrollers” in the Embedded Control is taken as the timing reference, propagation delays
Applicationshandbook. may vary fmm 25 ns to 125m.
To drive the CHMOS parts with an external clock The AC Timingssectionof the data sheetsdo not refer-
source, apply the external clock signal to XTALI and enceany timingto the XTAL1waveform.Rather, they
leave XTAL2 floating. Refer to the External Clock relate the critical edgesof control and input signals to
Source diagram. This is an impmtant differencefrom each other. The timings publishedin the data sheets
the HMOS parts. With HMOS, the external clock include the effects of propagation delays under the
source is applied to XTAL2,and XTAL1 is grounded. specified test
condition
See Figure 40.

-+4
8XC51GB

NC XTAL2
Ext*rnal
Oscilidor XTAL1
Signal
CMOS ode Vss
Vss
270S97-40

Figure40.Drivingthe CHMOS Deviceswithan ExternalClock Sources

6-54
8 Hardware 7 3
Description
83C152 HARDWARE CONTENTS PAGE
DESCRIPTION l,olNTRoDucTloN
.................................. 7-3
2.0 COMPARISON OF 80C152 AND
80C51 BH FEATURES ............................ 7-3
2.1 MemorySpace................................. 7-3
2.2 interruptStructure.......................... 7-11
2.3 Reset ............................................. 7-12
2.4 Ports4, 5 and 6 ............................. 7-13
2.5 Tmere/Counters............................ 7-13
2.6 Package......................................... 7-13
2.7 Pin Description............................... 7-14
2.8 Power Downand Idle..................... 7-17
2.9 LocalSerial Channel...................... 7-17

3.0 GLOBAL SERIAL CHANNEL ............7-17

3.1 Introduction.................................... 7-17
3.2 CSMA/CD Operation..................... 7-20
3.3 SDLC Operation............................ 7-27
3.4 User DefinedProtocols.................. 7-34
3.5 Usingthe GSC ............................... 7-34
3.6 GCS Operation.............................. 7-42
3.7 RegisterDescriptions..................... 7-44
3.8 Serial Backplanevs Network
Environment..................................... 7-47

4.0 DMA OPERATION ............................. 7-47

4.1 DMA withthe 80C152......... ........... 7-47
4.2 TimingDiagrams............................ 7-50
4.3 Hold/HoldAcknowledge................. 7-50
4.4 DMA Arbitration............................. 7-55
4.5 Summaryof DMA ControlBits....... 7-59

5.0 INTERRUPT STRUCTURE ................7-60

5.1 GSC TransmitterError
Conditions........................................ 7-62
5.2 GSC ReceiverError
Conditions........................................ 7-63

6.0 GLOSSARY ........................................7-64

7-1
 83C152 HARDWARE DESCRIPTION
1.0 INTRODUCTION useof externalprograntmemory.The seconddifference
is that RESET is active low in the 83C152and active
The 83C152Universal CommunicationsController is highin the 80C51BH.This is veryimportant to deaign-
an 8-bit microcontroller designed for the intelligent ers whomaycurrently be usingthe 80C51BHand plrm-
managementof peripheralsystemsor components.The ning to use the 83C152,or are planning on using both
83C152is a derivativeof the 80C51BHand retains the deviceson the same board. The third differenceis that
same functionality.The 83C152is fabricated on the GPOand GF1, general purpose flags in PCON, have
same CHMOS 111process as the 80C51BH. What been renamed GFIEN and XRCLK. GFIEN enables
makes the 83C152ditTerentis that it has added func- icfletlags to be generatedin SDLCmode,and XRCLK
tions and peripherals to the basic 80C51BHarchitec- enablesthe receiverto be externallyclocked.All of the
ture that are supportedby new SpecialFunction Regis- previouslyunused bits are now being used and inter-
ters (SFRS).Theseenhancementsinclude:a high speed rupt vectors have been added to support the new en-
multi-protocol serial communication interface, two hancements.Programmersusingold codegeneratedfor
channelsfor DMA transfers, HOLD/HLDA bus con- the 80C51BHwill have to examine their programs to
trol, a tifth 1/0 port, expanded&ta memory, and ex- ensure that new bits are properlyloaded, and that the
panded programmemory. new interrupt vectors will not interfere with their pro-
m
In addition to a standard UART, referred to here as
Local Serial Channel (LSC), the 83C152has an on- Throughoutthe rest of this manualthe 80C152and the
board multi-protocolcommunicationcontroller called 83C152will be referred to genericallyss the “C152”.
the Global Serial Channel (GSC). The GSC interface
supports SDLC, CSMA/CD, user definableprotocols, The C152is based on the 80C51BHarchitecture and
and a subsetof HDLC protocols.The GSC capabilities utilizesthe same 80C51BHinstructionset. Figure 1.1is
include:address recqnition, collisionresolution, CRC a block diagram of the C152. Readers are urged to
generation,tlag generation, automatic retransmission, compare this block diagram with the 80C51BHblock
and a hardware baaed acknowledgefeature. This high diagram. There have been no new instructions added.
s@ ~ channel is capable of implementing the All the new features and peripheralsare supported by
Data LmkLayerand the PhysicalLinkLayer as shown an extensionof the SpecialFunctionRegisters (SFRS).
in the 0S1 open systems communicationmodel. This Veg little of the informationpertamm “ g specificallyto
modelcan be foundin the document“ReferenceModel the 80C51BHcore will be discussedin this chapter.
for Open Systems Interconnection Architecture”, The detailedinformation on such functions as: the in-
ISO/TC97/SC16N309. struction set, port operation, timer/counters, etc., can
be found in the MCW-51 Architecture chapter in the
The DMA circuitry consists of two 8-bit DMA chan- Intel EmbeddedController Handbook.Knowledge of
nels with id-bit addressability. The control signala; the 80C51BHis required to fullyunderstand this man-
= ~, = (WR), hold and hold acknowledge ual and the operation of the C152.To gain a basic un-
(HOLD/HLDA) are used to accessexternal memory. derstanding on the operation of the 80C51BH, the
The DMA channels are capable of addressing up to reader shouldfamiliarise himselfwith the entire MCS-
64K bytes (16 bits). The destinationor source address 51 chapter of the EmbeddedControllerHandbook.
can be automaticallyincremented.The lower 8 bits of
the addressare multiplexedon the data bus Port Oand Anothersourceof informationthat the reader may find
the uppereightbits of addresswillbe on Port 2. Data is helpfulis Intel’s LAN ComponentsUser’s Manual, or-
transmitted overan 8-bit addreWdata bus. Up to 64K der number 230814.Inside are descriptionsof various
bytesof data maybe transmitted for each DMA activa- protmols, application examples,and application notes
tion. dealing with ditTerentserial communicationenviron-
ments.
The newI/O port(P4) functionsthe same as Ports 1-3,
found on the 80C51BH.
2.0 COMPARISON OF 80C152 AND
Internal memoryhas beendoubledin the 83C152.Data 80C51BH FEATURES
memoryhas been expandedto 256bytes, and internal
program memoryhas been expandedto SK bytes.
2.1 Memory Space
There are also some specific ditTerencesbetween the
83C152and the 80C51BH.The fmt is that the number- A goodunderstandingof the memoryspace and how it
ing system betweenthe 83C152and the 80C51BHis isused in the operation of MCS-51products is eaaen-
slightly different. The 83C152and the 80C51BHare tial. Ml the enhancementson the C152are implement-
factory masked ROM devices. The 80C152 and the ed by accessing Special Function Registers (SFRS),
80C31BH are ROMless devices which require the added data memory, or added programmemory.
7-3
int& 83C152 HARDWARE DESCRIPTION

I 1 I 1

II — 1=

Kd II
I —, , -. , , —, , —J I

. . -. .—
Figure 1.1. Block IJiagram
7-4
in~. 83C152 HARDWARE DESCRIPTION

2.1.1 SPECIAL FUNCTION REGISTERS (SFRS) (IDA), Source Addreas Space bit (SAS), Increment
Source Address bit (ISA), DMA Channel Mode bit
The following list contains all the SW their names (DM), Transfer Mode bit (TM), DMA Done bit
and function. All of the SFRSof the 80C51BHare re- (DONE), and the 00 bit (GO). DCONOis used to
tained and for a detailedexplanationof their operation, control DMA ChannelO.
please refer to the chapter, “Hardware Descriptionof
the 8051 and 8052” that is found in the Embedded DCONI - (93H) Same as DCONOexcept this is for
ControllerHandbook.An overviewof the new SFRSis DMA Channel 1.
foundin Section2.1.1.1,with a detailedexplanationin
Section3.7, Section4.5, and 6.0. GMOD - (84H) Contains the Protocol bit (PR), the
Preamble Mgth (PL1,O),CRC Type (CT), Addf-
Lersgth(AL),Mode select (M1,O),and ExternalTrans-
2.1.1.1 New SFRS mit Clock(TXc). This register is used for GSC opera-
The followingdescriptionsare quick overviewsof the tion only.
new SFRS,and not intended to givea completeunder- IENI - (OC8H)Interrupt enableregister for DMA and
standing of their use. The reader should refer to the GSC illtt31111ptS.
detailed explanation in Section 3 for the GSC SFRS,
and Section4 for the DMA SFRS. IFS - (OA4H)Determinesthe numberof bit times sepa-
rating transmittedframes.
ADR 0,1,2,3- (95H, OA5H,OB5H,OC5H)Contains
the four bytes for address matchingduringGSCopera- IPN1 - (OF8H)Interrupt priority register for DMA
tion. and GSC interrupts.
AMSKO- (OD5H)selects “don’t care” bits to be used MYSLOT- (OF5H)Contains the Jamming mode bit
with ADRO. (DC.7),the Deterministic Collision Resolution Algo-
rithm bit (DCR), and the DCR slot address for the
AMSK1 - (OE5H)Selects“don’t care” bits to be used GSC.
with ADR1.
P4 - (oCOII)COntainsthe memory“image” of Port 4.
BAUD - (W-I) Contains the prograrnmable value for
the baud rate generatorfor the GSC.The baudrate will PRBS - (OE4H)Contains a pseudo-randomnumber to
equal (foac)/((BAW+ 1) X 8). be usedin CSMA/CDbackoffalgorithms.Maybe read
or written to by user software.
BCRLO- (OE2H)Contains the low byte of a comrt-
down counter that determines when the DMA access RFIFO - (F4H)RFIFO is usedto accessa 3-byteFIFO
for Channel Ois complete. that containsthe receivedata from the GSC.
BCRHO- (OE3H)Contains the high byte for count- RSTAT - (OE8H)Contsins the Hardware Based Ac-
downcounter for ChannelO. knowledgeEnable bit (HABEN), Global ReceiveEn-
able bit (GREN), Receive FIFO Not Empty bit
BCRL1 - (OF2H)Same as BCRLOexcept for DMA
Channel L =), Receive Done bit (RDN), CRC Error bit
(CRCE), Alignment Error bit (AE), Receiver Colli-
BCRH1 - (OF3H)Same as BCRHOexcept for DMA sion/Abort detect bit (RCABT), and the overrun bit
Channel 1. (OVR),used with both DMA and GSC.

BKOFF - (OC4H)An 8-bit count-downtimer used SARLO- (OA2H)Contains the low byte of the source
with the CSMA/CD resolutionatgorithm. address for DMA transfers.

DARLO- (OC2H)Containsthe lowbyte of the destina- SARHO- (OA3H)Gmtsins the high byte of the source
tion address for DMA Channel0, address for DMA transfers.

DARHO- (OC3H)Containsthe highbyte of the desti- SARL1- (OB2H)Sameas SARLObut for DMA Chan-
nation address for DMA channel O. nel 1.

DARL1 - (OD2H)Same as DARLOexcept for DMA SARH1- (oB3H)Sameas SARH1but for DMA Chan-
Channel 1. nel 1.

DARH1 - (OD3H)Same as DARHOexceptfor DMA SLOTTM- (OB4H)Determines the length of the slot
Channel 1. time in CSMA/CD.

DCONO - (92H) Contains the Destination Address TCDCNT - (OD4H)Contains the numberof collisions
Space bit (DAS), Increment Destination Address bit in the current frame if using CSMA/CD GSC.

7-5
i~e 83C152 HARDWARE DESCRIPTION

Old(O)/New(N) Name Addr Function

o A OEOH ACCUMULATOR
N ADRO 095H GSC MATCHADDRESS O
N ADR1 OA5H GSC MATCHADDRESS 1
N ADR2 OB5H GSC MATCHADDRESS 2
N ADR3 OC5H GSC MATCHADDRESS 3
N AMSKO OD5H GSC ADDRESSMASK O
AMSK1 OE5H GSC ADDRESSMASK 1
: B OFOH B REGISTER
N BAUD 094H GSC BAUDRATE
N BCRLO OE2H DMA BYTECOUNT O(LOW)
N BCRHO OE3H DMA BYTECOUNT O(HIGH)
N BCRL1 OF2H DMA BYTECOUNT 1 (LOW)
N BCRH1 OF3H DMA BYTECOUNT 1 (HIGH)
N BKOFF OC4H GSC BACKOFFTIMER
N DARLO OC2H DMA DESTINATIONADDR O(LOW)
N DARHO OC3H DMA DESTINATIONADDR O (HIGH)
N DARL1 OD2H DMA DESTINATIONADDR 1 (LOW)
N DARH1 OD3H DMA DESTINATIONADDR 1 (HIGH)
N DCONO 092H DMA CONTROLO
N DCON1 093H DMA CONTROL 1
o DPH 083H DATAPOINTER (HIGH)
0 DPL 082H DATA POINTER(LOW)
GMOD 084H GSC MODE
: IE OA8H INTERRUPTENABLE REGISTER O
N IEN1 OC8H INTERRUPTENABLEREGISTER 1
IFS OA4H GSC INTERFRAMESPACING
~ 1P OB8H INTERRUPTPRIORITY REGISTER O
N IPN1 OF8H INTERRUPTPRIORITY REGISTER 1
MYSLOT OF5H GSC SLOTADDRESS
: Po 060H PORT O
o P1 090H PORT 1
0 P2 OAOH PORT2
0 P3 OBOH PORT 3
N P4 OCOH PORT 4
N P5 091H PORT 5

B P6
PC(3N
OAIH
087H
PORT6
POWERCONTROL

:N PRBS
Psw
RFIFO
OE4H
ODOH
OF4H
GSC PSEUDO-RANDOMSEQUENCE
PROGRAMSTATUS WORD
GSC RECEIVEBUFFER
N RSTAT OE8H RECEIVESTATUS (DMA & GSC)
N SARLO OA2H DMA SOURCEADDR O(LOW)
N SARHO OA3H DMASOURCE ADDR O(HIGH)
N SARLI OB2H DMA SOURCEADDR 1 (LOW)
N SARH1 OB3H DMASOURCEADDR 1 (HIGH)
o SBUF 099H LOCALSERIALCHANNEL (LSC) BUFFER
0 SCON 098H LOCALSERIALCHANNEL (LSC)CONTROL
N SLOITM OB4H GSC SLOTTIME
o SP 081H STACKPOINTER
N TCDCNT OD4H GSCTRANSMIT COLLISION COUNTER
o TCON 088H TIMER CONTROL
TFIFO 085H GSCTRANSMIT BUFFER
: THO 08CH TIMER O(HIGH)
o TH1 08DH TIMER 1 (HIGH)
0 TLO 08AH TIMER O(LOW)
0 TL1 08BH TIMER 1 (LOW
0 TMOD 089H TIMER MODE
N TSTAT OD8H TRANSMIT STATUS (DMA & GSC)

7-6
in~. 83C152 HARDWARE DESCRIPTION

TFIFO - (85H)TFIFO is usedto accessa 3-byteFIFO The addressesof the second 128bytes of data memory
that containsthe transmissiondata for the GSC. happen to overlap the SFR addressee.The SFRSand
th~u memory lo&tions are shown in Figure 2.2. This
TSTAT - (OD8H) Contains the DMA SeMce bit means that internal &ta memoryspaces have the same
(DMA), Transmit Enable bit (TEN), Transmit FIFO address es the SFR address. However, each type of
Not Full bit (TFNF), Transmit Done bit (TDN), memoryis addresseddii%erently. To accessdata memo-
Transmit CollisionDetect bit (TCDT), Underrun bit ry above 80H, indirect eddreaaingor the DMA chan-
(UR), No Acknowledgebit (NOACK), and the Re- nels must be used. To accessthe SFRS,direct address-
ceive Data Line Idle bit (LNI). This register is used ing is used. Whendirect addressingis used, the address
with both DMA end GSC. is the source or destination,e.g. MOV A, IOH,moves
the contents of location IOH-into the “accmnulator.
The generalpurposeflagbita (GFOand GF1) that exist When indirect addressingis used, the address of the
on the 80C51BHare no longer availableon the C152. destinetionor sourceexistswithinsnother register, e.g.
GFO has been renamed GFIEN (GSC Flag Idle En- MOV A, @RO.This instruction movesthe contents of
able) end is used to enableidle fill flags.Also GF1 has the memorylocationaddressedby ROinto the accumu-
been renamed XRCLK (External Receive Clock En- lator. Directly addressingthe locations 80H to OFFH
able) end is used to enable the receiver to be clocked will-s the SFRS.Anotherform of indirect address-
externally. ing is with the usc of Stack Pointer operations. If the
StackPointer containsan addressand a PUSH or POP
2.1.2 DATAMEMORY
instruction is executed,indirect addressing is actually
used. Directly accessingan unused SFR address will
Internal data memoryconsistsof 256bytesas shownin giveundefinedresults.
Figure 2.1. The tirst 128 bytes are addressed exactly Physically,there are separate SFR memory and date
like an 80C51BH,using direct addressing. memory spaces elloeated on the chip. Since there are
separate spaces,the SFRSdo not diminishthe available
data memoryspace.

OFFH
(“)

OVERLAPPING
MEMORY
AOGRESSES

080H
(“) (“)
SPECIALPUNC710N
REOSTER
SPACE

02FH
Err AOORESSASLE
MEUOSYSPACE
020H
OIFH
REGISTER
SANK3
017H
REGIS7ER
SANK2
O1OH
RECFJERBANK1
O07H
REGISTER
BANKO
OOOH
USEROATAMEMORY
SPACE 270427-1

“NOTE:
UeerdatememoryaboveSOHmustbe addressedindirectly.
Using directaddressing
above80H acceaeesthe Special
Function
Registers.
-. - . - . .. .-
rlgure 2.1. Data MemO~ MafJ
7-7
i~. 83C152 HARDWARE DESCRIPTION

External data memory is accessed like an 80C51BH, 2.1.2.1 Bit Addressable Memory
with “MOVX” instructions.Addresaeaup to 64K may
be massed when using the Data Pointer (DPTR). The C152has severrdmemoryspaces in whichthe bits
when accesshg externaldata memorywith the D- are directly addressedby their location. The directly
the address appears on Port Oand 2. When using the addressablebits and their symbolicnamesare shownin
DPTR, if leas than 64K of external data memory is Figure 2.3A, 2.3B,and 2.3C.
u- the address is emitted on all sixteen pim. This
means that when usingthe DPTR, the pins of Port 2 Bit addreaaesO to 7FH reaide in on-board user data
not used for addressescarmotbe used for generalpur- RAM in byte addresses20H to 2FH (seeFigure 2.3A).
pose 1/0. An alternativeto using Id-bit addresseswith
the DPTR is to use ROor R1 to address the external Bit addream 80Hto OFFHreside in the SFR memory
data memory.When usingthe registers to address ex- space, but not everySFR is bit addressable,see Figure
ternal data memory,the addressrange is limited to 256 2.3B.The addressablebits are scattered throughoutthe
bytea. However,softwaremanipulationof I/O Port 2 SFRS.The addressablebits occur everyeighth SFR ad-
pins as normal 1/0, allowsthis 256bytes restrictionto dress starting at 80Hand occupythe entire byte. Most
be expandedvia bank switching.When usingROor RI of the bits that are addressablein the SFRShave been
as data pointers, Port 2 pins that are not used for ad- given symbolicnsrne3.These names will often be re-
dressing,can be used as generalpurpose 1/0. ferred to in this or other documentationon the C152.
Most assemblers also allow the use of the symbolic
names when writing in assembly language. These
namesare shownin ~igure 2.3C. - - -

(*)lml OfBH
SLOITM OWH
MKLOT OF3H sARnl ~H
RFIFO OF4H SARL1 OB2H
BCRH1 Of3H
ScsLl OF2H (9P3 OBOH
(0)B OFOH (*)IE OABH
[.)55TAT O~H ADRl OASH
IFS OA4H
4Amtl OE3H SARHo OA3H
..DI. II.*U
PRB3 OE4H
BcRHo Os3H (*)P2 OAOH
I I I I I I I
KsLo m?H /////////////////////////////////
OSSH
(*)A OEoH (*)=F SW I %1 [ SM2 I ECNI TEE i SSS ] n I RI OBaH
*rlnrl m..
(.) TSTAT ~H

MISKO O03H
TmcNT Oo4H
OAXH1 Oo3n
OARLl C02H

(*)PSW OooH

(.)12N1 Orm TLO OsAH

AcR3 OC3H
BXOFF CuH
w Oc3n
/////////////////
OARLO Oc2H ,,.
I’nrn” Im’au
—,,

(*)P4 OCOH
OMooKlclJ(l Ml [ MO 1 M i CT I PL1 I PLO I PS OB4H
CPH OS3H
m OB2H
(*)IP OBSH -.
OBIH

270427-2

Figure 2.2. Special Function Registers

7-8
i~. 83C152 HARDWARE DESCRIPTION

Data Memory Map

. (bite):
. .
Byte BITADDRESSES
Address (MSB) (LSB)
020H 07 08 05 04 03 02 01 00
021H OF OE OD Oc OB OA 09 08
022H 17 16 15 14 13 12 11 10
023H
024H I 27 I 26 I 25 I 24 I 23 1 22 I 21 I 2(I I
025H
026H
027H 3F 3E 3D 3C 3B 3A 39 38
028H 47 46 45 44 43 42 41 40
029H 4F 4E 4D 4C 46 4A 49 48
02AH 57 56 55 54 53 52 51 50
02BH 5F 5E 5D 5C 5B 5A 59 58
02CH 67 66 65 64 63 62 61 60
02DH 6F 6E 6D 6C 6B 6A 69 68
02EH 77 76 75 74 73 72 71 70
02FH 7F 7E 7D 7C 7B 7A 79 78
Figure 2.3A. Bit Addresses

Byte BIT ADDRESSES

Address (MSB) O-SB)
080H (Po)
088H 8F 6E 8D 8C 8B 8A 89 88 (TCON)
97 96 95 94 93 92 91 90 (Pi)
098H 9F 9E 9D 8C I 96 9A 99 98 (SCON)
OAOH A7 A6 A5 A4 A3 A2 Al AO (P2)
OA8H (IE)
OBOH B? B6 B5 B4 B3 B2 B1 BO (P3)
OB8H BC BB BA B9 B8 (1P)
OCOH C7 C6 C5 C4 C3 C2 cl co (P4)
OC6H CD cc CB CA C9 C6 (IEN1)
ODOH D7 D6 D5 D4 D3 D2 D1 DO (Psw)
OD8H DF DE DD Dc DB DA D9 D8 (TSTAT)
OEOH E7 E6 E5 E4 E3 E2 El EO (A)
OE8H EF EE ED EC EB EA E9 E8 (RSTAT)
OFOH (B)
OF8H FD FC I FB FA F9 F8 1 (IPN1)
Figure 2.36. Bit Addresses

7-9
intd. 83C152 HARDWARE DESCRIPTION

Byte SYMBOUCNAMEBITMAP
Address (MSB) (LSB)
080H PO.7 PO.6 PO.5 PO.4 PO.3 PO.2 Po.1 Po.o (Po)
088H TF1 .TR1 TFO TRO IE1 ITI IEO ITO (TCON)
090H P1.7 I P1.6 I P1.5 I P1.4 I P1.3 I P1.2 I P1.1 I P1.O I (Pi)
098H SMO I SM1 I SM2 I REN I TB8 I RB8 I TI I RI I (SCON)
OAOH P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.O (P2)
OA8H EA — — ES ETl EX1 ETo EXO (IE)
OBOH P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.O (P3)
OB8H — — — Ps PT1 Pxl PTO Pxo (1P)
OCOH P4.7 I P4.6 I P4.5 I P4.4 I P4.3 ! P4.2 I P4.1 I P4,0 (P4)
OC6H — — I EGSTE ] EDMA1 I EGSTV ] EDMAO I EGSRE I EGSRV (IEN1)
ODOH CY I AC FO I RS1 RSO Ov I — P (Psw)
OD8H LNI I NOACK I UR I TCDT I TDN I TFNF I TEN I DMA (TSTAT)
OEOH (A)
OE8H OVRI RCABTI AE I CRCE I RDN I RFNE I GREN I HABEN (RSTAT)
OFOH (B)
OF8H — — PGSTE PDMA1 PGSTV PDMAO PGSRE PGSRV (IPN1)
Figure 2.3C. Bit Addresses

2.1.3 PROGRAMMEMORY
The 83C152 contains SK of ROM program memory, FFFFH
and the 80C152uses only external program memory.
Figure 2.4 shows the program memorylocations and
where they reside. The user is alloweda maximum of EXTERNAL
64K of program memory. In the 83C152 program
memoryfetchesbeyond 8K automaticallyaccessexter-
nal programmemory.Whenprogrammemoryis exter-
nally addr- all of the Port 2 pinsemit the address.
Since all of Port 2 is affectedby the address, unused
addresspinscannot be usedas normalI/O ports evenif
less than 64K of memoryis beingaccessed.

1FFFH

EXTERNAL
IF~= O
INTERNAL
IF~= 1

OOOOH
270427-4

Figure 2.4. Program Memory

7-1o
in~e 83C152 HARDWARE DESCRIPTION

2.2 Interrupt Structure interrupts and IPN1 (F8H) for settingthe priority.For
an explanationon how the priority of interrupts affects
The C152retains all fiveinterruptsof the 80C51BH.In their operationpleasereferto the MCS-51Architecture
additiorLsix new interrupts havebeenadded for a total and Hardware Chapters io the Intel EmbeddedCon-
of 11available interrupts. Two SFRShave beerradded troller Handbook.A detailed description on how the
to the C152 for control of the new interrupta. These interrupts function is in the MC$W51 Architectural
added SFRS are IEN1 (C8H) for enabling the Overview.

I IEN1 FUNCTIONS I
Symbol I Position Vector Function
— I
IFN1
.-. . . . 7. I
I
I1 RFGFBVFn
------- . -- sm~do not e~st on chip.
-..
I — ——-——. .——
I
IEIN1.6 i I RESERVED anddonotexist
-. n
“..n~hin
-...~.
EGSTE IEN1.5 04BH GSC TRANSMITERROR-Theinterrupt serviceroutineat
4BHisinvoked
if NOACKorTCDTissetwhen the GSC is
I I I I underCPUcontrolandEGSTEisenabled.Thisinterrupt
serviceroutineisinvokedifNOACK,TCDT,orURissetwhen
the GSC is underDMAcontrolandEGSTEisenabled.
I
EDMA1 IEN1.4 053H DMACHANNELREQUESTl-The interrupt serviceroutine
at 53H is invokedwhen DCON1.1 (DONE) is set and EDMA1
is enabled.
EGSTV IEN1.3 043H GSC TRANSMIT VALID-lTre interruptservice routineat 43H
is invokedifTFNF is set whenthe GSC is under CPUcontrol
andEGSTVisenabled.Thisinterrupt serviceroutineis
invoked
if TDN isset whenthe GSC is underDMA controland
EGSTV is enabled.
EDMAO IEN1.2 03BH DMA CHANNEL REQUEST (+The interruptserviceroutine
at 3BH willbe invokedwhen DCONO.1(DONE) is sat and
EDMAOis enabled.
EGSRE IEN1.1 033H GSC RECEIVE ERROR-The interruptserviceroutineat 33H
is invokedif CRCE, OVR, RCABT,or AE is set when the GSC
is underCPU or DMA controland EGSRE is enabled.
EGSRV IEN1.O 02BH GSC RECEIVE VALID-The interruptseMce routineat 2BH
is invokedif RFNE is set whenthe GSC is underCPU control
and EGSRV is enabled.This interruptserviceroutineis
invokedif RDN is set when the GSC is underDMA controland
EGSRV is enabled.

IPN1 is used the same way the current 80C51BHinterrupt priority register (1P) is. By assigninga “l” to the
approptite bit, thst interrupt has a higherpriority than an interrupt with a “O”assignedto it in the priorityregister.
The new interrupt priority register(IPN1) contents are:

Symbol Position Function

PGSTE IPN1.5 GSCTRANSMIT ERROR
PDMA1 , IPN1.4 DMA CHANNELREQUEST 1
I PGSTV IPN1.3 GSCTRANSMITVALID
PDMAO IPN1.2 DMA CHANNELREQUEST O
PGSRE IPN1.1 GSC RECEIVEERROR
PGSRV IPN1.O GSC RECEIVEVALID

7-11
i@. 83C152 HARDWARE DESCRIPTION

The eleveninterrupts are sampledin the followingorder whenassignedthe same priority levelin the 1P and IPN1
registers:
Priority Priority Interrupt Interrupt
Priority Symbolic Symbolic Symbolic Symbolic Vector
Sequence Address Name Address Name Address
1 IP.O Pxo IE.O EXO 03H (FIRST)
2 IPN1.O PGSRV IEN1.O EGSRV 2BH
3 IP.1 PTO IE.1 ETO OBH
4 IPN1.1 PGSRE IEN1.1 EGSRE 33H
5 IPN1.2 PDMAO IEN1.2 EDMAO 3BH
6 IP.2 Pxl IE.2 EX1 13H
7 IPN1.3 PGSTV IEN1.3 EGSTV 43H
8 IPN1.4 PDMA1 IEN1.4 EDMA1 53H
9 IP.3 PT1 IE.3 ETl IBH
10 IPN1.5 PGSTE IEN1.5 EGSTE 4BH
11 IP.4 Ps IE.4 ES 23H (LAST)

2.3 Reset
RE3ET performsthe same operationsin both the 80C51BHand the C152and those conditionsthat exist at the end
of a valid RESETare:
Register Contents Regiater Contents
ACC OOH PO-P6 OFFH
ADRO-3 OOH PCON OXXXOOOOB
AMSKO OOH PRBS OOH
AMSK1 OOH Psw OOH
B OOH RFIFO INDETERMINATE
BAUD OOH RSTAT OOOOOOOOB
BCRHO INDETERMINATE SARHO INDETERMINATE
BCRH1 INDETERMINATE SARH1 INDETERMINATE
BCRLO INDETERMINATE SARLO INDETERMINATE
CRL1 INDETERMINATE SARL1 INDETERMINATE
BKOFF INDETERMINATE SBUF INDETERMINATE
DARHO INDETERMINATE SCON OOH
DARH1 INDETERMINATE SLOITM OOH
DARLO INDETERMINATE SP 07H
DARL1 INDETERMINATE TCDCNT INDETERMINATE
DCONO OOH TCON OOH
DCONI OOH TFIFO INDETERMINATE
DPTR OOOOH THO OOH
GMOD XOOOOOOOB TH1 OOH
IE OXXOOOOOB TLO OOH
IENI XXOOOOOOB TL1 OOH
IFS OOH TMOD OOH
1P XXXOOOOOB TSTAT XXOOO1OOB
IPNI XXOOOOOOB Pc OOOOH
MYSLOT oOOOOOOOB

7-12
 83C152 HARDWARE DESCRIPTION

The same conditionsapply for both the 80C51BHand to the Intel EmbeddedControllerHandbookwhich de-
C152for a correct reaet pulse or “power-on”reset ex- scribes the timer/counters and their use. The user
cept that Reset is active low on the C152.Pleaserefer shouldbear in mind, whenreadingthe Intel Embedded
to the 8051/52 Hardware Description Chapter of the ControllerHandbookthat the C152does not have the
Intel EmbeddedController Handbookfor an explana- third eventtimer namedTimer 2, whichis in the 8052.
tion on how to provi& a proper power-onreset. Since
R-is active low on the C152,the resistor shouldbe 2.6 Package
tied to VCC and the capacitor shouldbe tied to VSS.
The 83C152is packagedin a 48 pin DIP and a 68 lead
Because the clockingon part of the GSC circuitry is PLCC. This differs from the 40 pin DIP and 44 pin
independentof thhrocesao r clock, data may still be PLCC of the 80C51BH.The larger packageis required
transmitted and DEN active for sometime after resetis to accommodatethe extra 8 bit I/O port (P4). Figures
applied. The transmission may continue for a maxi- 2.5A, 2.5B and 2.5C show the packageaand the pin
mum of four machine cycles after reset is tirst pulled names.
low. AlthoughReset has to be held low for onlythree
machinecyclesto be recognizedby the GSChardware,
all of the GSC circuitry may not be reset until four u
(GRXD) PI.oc 1 4a a v=
machine cyclea have passed. If it is important in the (GTXD) P1.1 c 2 47 3 P4.O
user application that all transmission and ~ be-
(m) P1.2C 3 46 3 P4.1
comes inactive at the end of a reset, then ~ will
(We) P1.3C 4 45 3 P4.2
have to be held low for a minimum of four machine
cycles. (m) P1.4C 5 44 3 P4.3
(me) P1.5 c 6 43 3 P4.4
2.4 Ports 4,5 and 6 (=A) P1.6C 7 42 3 P4.5
P1.7 c a 41 2 P4.6
Ports 4, 5 and 6 operation is identical to Ports 1-3on
the 80C51BH.The descriptionof port operationcan be R1’5rrc 9 40 3 P4.7
foundin the 8051/52Hardware DescriptionChapterof (RxD) P3.o c 10 39 3 m
the Intel EmbeddedController Handbook.Ports 5 and (Txo) P3.1 E 11 38 Z ALE
6 exist only on the “3B” and “JD” versionof the C152 (=) P3.2 r 12 :;:;:::;:J 37 J-N
and can either fimctionas standard 1/0 ports or can be (m) P3.3 c 13 36 Z P2.7 (A15)
contlgured so that program memory fetches are per- (TO) P3.4C 14 35 3 P2.6 (A14)
formedwith thesetwo ports. To configureports 5 and 6 (Tl) P3.5 E 15 34 ~ P2.5 (A13)
as standard I/O ports, EBEN is tied to a logic low.
(WR) P3.6C 16 33 5 P2.4 (A12)
When in this configuration,ports 5 and 6 operationis
(m) P3.7 c 17 32 3 P2.3 (Al 1)
identical to that of port 4 except they are not bit ad-
dressable.To configureports 5 and 6 to fetch program (A/W) PO.Oc 18 31 3 P2.2 (Al O)
memory, EBEN is tied to a logic high. When using (A/01) PO.1 c 19 30 3 P2.1 (A9)
ports 5 ~d 6 to fetch the program memory,the si~ (A/02) PO.2c 20 29 3 P2.O (A8)
EPSEN B used to enable the external memorydevice (A/D3) P0,3c 21 28 3 po.7 (A/D7)
instead of PSEN.Regardlessof whichports are usedto XTAL2c 22 27 D po.s (A/06)
fetch program memog, all data memog fetchesoccur XTAL1c 23 26 J po.5 (A/D5)
over ports Oand 2. The 80C152JBand 80C152JDare v~~c 24 25 ~ PO.4 (A/04)
availableas ROMleasdevicesonly. ALE is still usedto
latch the address in all contlgurations.Table 2.1 sum- 270427-5
marizes the control signals and how the ports may be
-. - -. --- -. - .
used.

2.5Timer/Counters
The 80C51BHand C152 have the same pair of 16-bit
general purpose tirner/cmmters. The user shouldrefer
Table 2.1 Program Memory Fetches
Program — —
EBEN Ezi PSEN EPSEN Comments
Fetch via
o 0 PO.P2 Active Inactive AddressesO-OFFFFH
o 1 N/A N/A N/A invalidCombination
1 0 P5, P6 Inactive Active AddressesO-OFFFFH
1 1 P5, P6 Inactive Active AddressesO-1 FFFH
Po, P2 Active Inactive Addresses> 2000H

7-13
int& 83C152 HARDWARE DESCRIPTION

c
E
P1.6C 10 PI.6 10 30 P4.5
P1.7C 11 PI .7 c 11 59 P4.6
22ENC 12 58 ?4.7
N.C,C 12
KErC 13
P3.OC 14 56
Rsrrc 13
PSOc 14 56L
57

55 Au
P3.S

1
P3,?c 15
P3,1C 1s
P3.2c 36 rww 54 F3rii
P3.2C 16 54 3=
FSOc 17 53 ma
N.c.c 17 5s J N,C. 80C152J6
80Cf52JA/JC P3.3c 18 52 P6.2
P33C 18 S2 aN,c. 80C152JD
83C152JA/JC P3.4c 19 51 P6.7
PSAC 19 s! 3N.C.
P5,1c m 50 ?2.4
NC C 20 34 3N.C.
P5.2C 21 49 P3.7
49 JN.C.
P5,3C 22 40 F-2.7
a 3 P2.7 P3.5c 23 47 Pm
47 3 P2.6 PM c 24 46 P2.5
46 3P2.S P3.7c 25 45 P2.4
43 3P2.4 NC. R 26 44 P2.3
44 3 P2.3
...0 -.” . ..-..0-.”
. . . . . . . . . . . . . . . . .

0 ~ N n ~ ~ g.. * m ~ ~ J ~ 0 y N
2SS8SS>SRZS222 :=:
xx 270427-37
270427-6

Figure 2.5B. PLCC Pin Out Figure 25C. PLCCPin Out

2.7 Pin Description

The rindeacriution for the ~51BHakoamhes tothe C152andis listed below.Chsngeahavebeenmsdeto the
dss&iptionsm’theyapply tothe C152. ““

PIN DESCRIPTIOI
Pin#
Description
DIP
48 2
24 3,33(2) VSS-Circuit around.
18-21, 27-30, Port fJ-Port Ois an 8-bit opendrainbi-directional1/0 port.As an outputpart each
25-28 34-37 pincan sink8 LS lTL inputs.PortOpinsthat have 1s writtento them float, and in
that state can be usedas high-impedanceinputs.
PortOisalso the multiplexedlow-orderaddress and data busduringaccesses to
externalprogrammemoryif EBEN is pulledlow. Duringaccessesto external Date
Memory,PortOalwaysemitsthe low-orderaddressbyteand serves as the
multiplexeddata bus. in these applicationsit uses stronginternalpullupswhen
emitting 1s.
Pod Oalso outputs
thecodebytesduringprogramverification.
ExternalPUIIUPS
are
required
duringprogram
verification.

NOTES:
1. N.C. pins on PLCC package may be connected to internal die and should not be usad in customer applications.
2. It is recommended that both Pin 3 and Pin 33 be grounded for PLIX devicea.

7-14
int& 83C152 HARDWARE DESCRIPTION

PIN DESCRIPTION(Continued)
Pin #
Deeoription
DIP PLCC(l)
1-8 4-11 Port l—Port 1 is an B-bitbidirectional1/0 portwithinternalpullups.Port1 pinsthat
have 1s writtento them are pulledhighby the internalpullups,and inthat atate can
be usedas inputs.As inputs,Port1 pinsthat are externallybeingpulledIowwill
sourcecurrent(l[L,on the data sheet) because of the internalpullups.
Port1 also serves the functionsof variousspecialfeaturesof the 8XC152, as listed
below:
Pin Name Alternate Function
P1.o GRXD GSC date inputpin
P1.1 GTXD GSC date outputpin
P1.2 m GSC enable signalfor an externaldfier
P1.3 TXC GSC inputpinfor externaltransmitclock
P1.4 m GSC inputpinfor external receiveclock
P1.5 m DMA holdinput/output
P1.6 HLDA DMA holdacknowledgeinput/output
29-36 41-48 Port 2-Port 2 is an 8-bit bi-directionall/O portwithinternalpullups.Port2 pinsthat
have 1s writtento them are pulledhighby the internalpullups,and inthat state can
be used as inputs.As inputs,Port2 pinsthat are externallybeingpulledlowwill
sourcecurrent(lIL,on the data sheet) because of the internalpullups.
Port2 emitsthe high-orderaddressbyte duringfetches fromexternalProgram
Memoryif EBEN is pulledlow.Duringaccesses to externalDate Memorythat use
16-bitaddresees(MOVX @DPTRand DMA operations),Port2 emitstha high-order
addressbyte. In these applicationsit uses stronginternalpullupswhenemitting1s.
Duringaccesses to externalData Memorythat use 8-bit addresses(MOVX @Ri),
Port2 emitsthe contentsof the P2 Special FunctionRegister.
Port2 also receivesthe high-orderaddress biteduringprogramvetilcation.
10-17 14-16, Port 3--Port 3 is an 8-bit bi-directional1/0 portwithinternalpullups.Port3 pinsthat
18,19, have 1s writtento them are pulledhighby the internalpullups,and inthat state can
23-25 be used as inputs.As inputs,Port3 pinsthat are externallybeingpulledlowwill
sourcecurrent([IL,on the data sheet)because of the pullupa.
Port3 also serves the functionsof variousspecialfeaturesof the MCS-51 Family,
as listedbelow:
Pin Name Alternate Function
P3.O RXD Serialinputline
P3.1 TXD Serialoutputline
P3.2 m ExternalinterruptO
P3.3 INT1 Externalinterrupt1
P3.4 TO Timer Oexternalinput
P3.5 T1 Timer 1 externalinput
P3.6 m ExternalData Memory Write strobe
P3.7 m ExternalData MemoryRead strobe
47-40 65-58 Port 4-Port 4 is an 8-bitbi-directional1/0 portwithinternalpullups.Port4 pinathat
have 1s writtento them are pulledhighby the internalpullups,and inthat state can
be used es inputs.As inputs,Port4 pinsthat are externallybeingpulledlowwill
Source current(!IL,on the data sheet) because of the internalpullups.In addition,
Port4 also receivesthe low-orderaddressbytesduringprogramverification.

NOTES:
1. N.C. pins on PLCCpackagemaybe conneotedto internaldieand shouldnotbe usedincustomerapplications.
2. Itis raoommendedthat bothPin3 and Pin33 be groundedforPLCCdevices.

7-15
intd. 83C152 HARDWARE DESCRIPTION

PIN DESCRIPTION(Continued)
Pin #
Description
DIP PLCC(l)
9 13 =-Reset input.A logiclowon this pinfor three machinecycleswhilethe
oscillatoris runningresetsthe device.An internalpullupresistorpermitsa power-
on reset to be generatedusingonlyan externalcapacitorto V.SS.Althoughthe GSC
recognizesthe reset after three machinecycles,data may continueto be
transmittedfor UPto 4 machinecyclesafter Reset is firstapplied.
55 ALE—Addresa LatchEnable outputsignalforlatching
thelowbyteoftheaddress
duringaccesses
toexternalmemory.
In normaloperationALE is emitted at a constantrate of 1/6the oscillatorfrequency,
and may be usedfor externaltimingor clockingpurposes.Note, however,that one
ALE pulseis skippadduringeach access to externalData Memory.Whilein Reset
ALE remainsat a constanthighlevel.
37 54 PSEN-Program Store Enable isthe Read strobeto ExternalPro ram Memory.
When the 8XC152 is executingfrom externalprogrammemory,P -+ EN isactive
(low).When the device is executingcode fromExternalProgramMemory,= is
activatedtwiceeach machinecycle, exceptthat two= activationsare skipped
duringeach accessto ExternalData Memory.While in Reset = remainsat a
constanthiahlevel.
39 56 ~-External Accessenable. = mustbe externallypulledlowin orderto enable
the 8XC152 to fetch code from ExternalProgramMemory locations
OOOOHto
OFFFH.
~ mustbe connectedto VCCfor internalprogramexecution.
23 32 XTAL1-lnputto the invertingoscillatoramplifierand inputto the internalclock
generatingcircuits.
22 31 XTAL2-Outputfromtheoscillator
amplifier.
N/A 17,20 Port S-Port 5 is an 8-bit bi-directional1/0 portwithinternalpullups.Port5 pins
21,22 that have 1s writtento them are pulledhighbythe internalPUIIUPS, and inthat state
38,39 can be usedas inputs.As inputa,Port5 pinsthat are externallybeingpulledlowwill
40,49 sourcecurrent(IIL,on the data sheet) becauseof the internalpullups.
Port5 is also the multiplexedIow-orderaddreasand data busduringaccessesto
externalprogrammemoryif EBEN is pulledhigh.In this applicationit usesstrong
OUIIUOS whenemittina1s.
NIA 67,66 Port 8-Port 6 isan 6-bit bi-directional1/0 portwithinternalpullups.Port6 pins
52,57 that have Is writtento them are pulledhighbytheinternalpulluPs, andinthatstate
50,66 can be usedas inputa.As inputs,Port6 pinsthat are externallypulledlowwill
1,51 sourcecurrent(lIL,on the data sheet) becauseof.the internalPUIIUPS.
Port6 emitsthe high-orderaddress byteduringfetches from externalProgram
Memory if EBEN is pulledhigh.In thisapplicationit uses strongpullupswhen
emitting1s.
N/A 12 EBEN-E-Bus Enableinputthat designateswhetherprogrammemoryfetchestake
placevia Ports O and 2 or Ports 5 and 6. Table 2.1 shows how the ports are used in
conjunctionwith EBEN.
53 EPSEN-E-bus ProgramStore Enable isthe Read strobeto externalprogram
memorywhen EBEN is high.Table 2.1 showswhen= is usedrelativeto
~ dependingon thestatusof EBEN and=.

1. N.C.Dinson PLCCPaclws mavbe connectedto internaldie snd ehouldnotbe used in customer applications.
2. It is kcommended~hatk-th Pi; 3 and Pin33 be groundedforPLCCdevices.

7-16
int& 83C152 HARDWARE DESCRIPTION

2.8 Power Downand Idle 2.9 LocalSerialChannel

Bothof these operations function identicallyas in the The Local Serial Channel (LSC) is the name given to
80C51BH.ApplicationNote 252, “Deaigningwith the the UART that exists on all MCS-51 devices. The
SOC51BH”givesan excellentexplanationon the use of LSC’Sfunctionand operationis exactlythe same as on
the reduced power consumptionmodes. Some of the the 80C51BH.For a descriptionon the use of the LSC,
itemsnot coveredin AP-252are the cxmsiderationsthat refer to the 8051/52Hardware DescriptionChapter in
are applicablewhen using the GSC or DMA in con- the Intel EmbeddedControllerHandbook,under serial
junction with the power savingmodea. Interface.

The GSC continues to operate in Idle ss long as the

interrupts are enabled. The interrupts need to be en- 3.0 GLOBALSERIALCHANNEL
abled,so that the CPU can seMce the FIFO’S.In order
to properlytetminate a reception or transmissionthe
C152must not be in idle when the EOF is transmitted 3.1 Introduction
or received.After servicingthe GSC, user softwarewill
need to again invoke the Idle command as the CPU The Global Serial Channel (GSC) is a multi-protocol,
does not automatically re-enter the Idle mode after high performanceserial interfacetargetedfor data rates
servicingthe interrupts. up to 2 MBPS with on-chip clock recovery,and 2.4
MBPSusingthe external clockoptions.In applications
The GSCdoesnot operatewhileitsPowerDown so the usingthe serial channel,the GSC implementsthe Data
steps required prior to entering Power Dowtsbecome Link Layerand PhysicalLinkLayeras describedin the
more complicated.The sequencewhen entering Power 1S0 referencemodel for open systemsinterconnection.
Downand the strstusof the I/O is of majorimportance
in preventingdamageto the C152or other components The GSC is designed to meet the requirements of a
in the system.Sincethe only way to exit Power Down widerangeof serial communicationsapplicationsand is
is with a R- severalproblemareas becomevery sig- optimised to implement Carrier-Sense Multi-Access
nificant. Someof the problemsthat merit carefsd con- with CollisionDetection (CSMA/CD) and Synchro-
siderationare caseswherethe PowerDownoccurs dur- nous Data Link Control (SDLC)protocols.The GSC
ing the middle of a transmission, and the possibility architectureis also designedto provideflexibilityin de-
that other stations are not or cannot enter this same ftig non-standardprotocols.This providesthe ability
mode.The state of the GSC 1/0 pins becomescritical to retrofit new products into older serial technologies,
and the GSC status will need to te savedbeforepower as well as the developmentof proprietaryinterconnect
downis entered.There will also need to be some meth- schemesfor serial backplaneenvironments.
od of identifyingto the CPU that the followingReaet is
probablynot a cold start and that other stations on the The versatilityof the GSCis demonstratedby the wide
link may have already been initialized. range of choices available to the user. The VariOUS
modes of operation are summarized in Table 3.1. In
The DMA circuitry stops operation in both Idle and subsequentsections,each availablechoiceof operation
PowerDownmodes.Sin= operationis stoppedin both will be explainedin detail.
mod- the prcesa shouldbe similar in each case. Spe-
cificsteps that need to be taken include:notificationto In usingTable 3.1, the parameters listed vertically(on
other devicesthat DMA operationis aboutto ceasefor the left hand side) represent an option that is selected
a particular station or network, proper withdrawal (X). The parameters listed horizontally(alongthe top
from DMA operation, and saving the status of the of the table) are all the parameters that could theoreti-
DMA channels.Again, the status of the 1/0 pins dur- cally be selected (Y). The symbol at the junction of
ing Power Down needs careful considerationto avoid both X and Y determinesthe applicabilityof the option
damageto the C152or other components. Y.

Port 4 returns to its input sta~ which is high l=el Note, that not all combinationsare backwardscompati-
using Wtzlk pllhp devices. ble. For example, Manchester encodingrequires half
duplex, but half duplex does not require Manchester
encoding.

7-17
 83C152 HARDWARE DESCRIPTION

Table 3.1
AVAl~BLE ~ ADDRESS
OPTIONS
I L
DATA
ENCOOINGFLAGS
01
CRC I
3 H F
DU- ACKNOW- RECOG-
PLEX LEDGE NITION
PRE-
!MBLE

I$ zz
I NN
A RR 11 :: 2 A u :? ::
N= NOTAVAILABLE N Zz If NB B L L RT NI
M= MANDATORY c I 11 El F L ME ET
O= OPTIONAL ID T + A RI
P= NORMAUYPREFERREO; IL c A LN
X=NfA s E c A
: I : T
T 0 E

NN 1P 10 0 M N 00 NO
XN PI 10 0 0 0 NN 00
I NRZ(~CLK) N NX 00 10 0 0 0 00
;NN
00
FIAGS:O111111O (SDLC) N
;Po xl
;10 0 0 0 o N
;00
11/lDLE kP lx 10 0 0 N 0 010 0 110
CRC:NONE 1 Ill 11 XN N 1 N 1 NN N Ill

16-BITCCITT o 010 00 NX N 0 0 0 +00 0 010

32-BITAUTODINII ko 010 +
00 NN x 0 N 0 00 00

3
IDUPLEX:HALF
k
00 00 10 0 x N 00 00
00 MN NM N N x NN 00
00 00 10 0 0 0 00 00
NN NO 10 0 0 N NO NO
Po 00
= 10 0 0 P 00 00

NONE/ALL o 0 0 0 0 1 0 0 0 0 0 0 0 x N N o 0 0 0 0
8-BIT o 0 0 0 0 1 0 0 0 0 0 0 0 N x N o 0 0 0 0
16-BIT o 0 0 0 0 1 0 0 0 0 0 0 0 N N x o 0 0 0 0

7-18
i~o 83C152 HARDWARE DESCRIPTION

----- 3.1
Tabk ,__......—_-,
-. . (Continued)
AVAILABLE ~ PRE-
OPTIONS AMBLE JAM CLOCK CONTROL
3 6 D c E I c D R R c s
c R x M D
N= NOT AVAILABLE : : c T : E A 4 4 :
M= MANDATORY 1 I [ E R T A k
O= OPTIONAL T T : R
P= NORMALLYPREFERRED E : &
X= N/A : : E N D
L L I
v i
SELECTED E
1 FUNCTION :
DATAENCODING:
MANCHESTER o 0 0 0 N M o 0 0 0 M N
NRZI o 0 N N N M o 0 0 0 N M
NRZ o 0 0 0 M N o 0 0 0 0 0
FIAGS:O1ll 1110 0 0 N N o 0 0 0 0 1 1 P
11/lDLE o 0 0 0 0 0 0 0 0 1 P 1
CRC:NONE 1 1 N N 1 1 1 1 1 1 1 1
l&BIT CCllT o 0 0 0 0 0 0 0 1 1 0 0
32-BITAUTODINII o 0 0 0 0 0 0 0 1 1 0 0
DUPLEX:HALF o 0 0 0 0 0 0 0 0 0 0 0
FULL o 0 N N o 0 0 0 N N N P
ACKNOWLEDGEMENT:
NONE o 0 0 0 0 0 0 0 0 0 0 0
HARDWARE o 0 0 0 N o 0 0 N N o N
USERDEFINED o 0 0 0 0 0 0 0 0 0 0 1
ADDRESSRECOGNITION:
NONE o 0 0 0 0 0 0 0 0 0 0 0
&BIT o 0 0 0 0 0 0 0 1 1 0 0
l&BIT o 0 0 0 0 0 0 0 1 1 0 0
COLLISIONRESOLUTION:
NORMAL o 0 0 0 N o 0 0 0 N M N
ALTERNATE o 0 0 0 N o 0 0 0 N M N
DETERMINISTIC o 0 0 0 N o 0 0 0 N M N
PREAMBLE:NONE N N N N o 0 0 0 0 0 N P
8-BIT N N o 0 0 0 0 0 1 1 0 0
32-BIT x N o 0 0 0 0 0 1 1 0 0
34-BIT N x o 0 0 0 0 0 1 1 0 0
JAM:D.C. o 0 x N N o 0 0 0 N M N
m o 0 N x N o 0 0 0 N M N
CLOCKING:QCrERNAL o 0 N N x N o 0 0 0 N o
INTERNAL o 0 0 0 N x o 0 0 0 0 0
CONTROISCPU o 0 0 0 0 0 x N o 0 0 0
DMA o 0 0 0 0 0 N x o 0 0 0
RAWRECEIVE: 1 1 0 0 1 1 1 1 x N 1 1
RAWTRANSMIT: 1 1 N N 1 1 1 1 N x 1 1
CSMAICD: o 0 0 0 N o 0 0 0 0 x N
SDLC: o 0 N N o 0 0 0 0 0 N x

7-19
 intel. 83C152 HARDWARE DESCRIPTION

Note 1: Programmable in Raw transmit or receive resolvethe contention.There are three differentmodea
mode. of collisionresolutionmade availableto the user on the
C152.Re-transrnissionis attempted when a resolution
Afmostall the optionsavailablefrom Table 3.1 can be algorithmindicates that a station’soppommity has ar-
implementedwith the proper software to perform the rived.
functionsthat are necessaryfor the optionsselected.In
Table 3.1,a judgmenthas beenmade by the authors on Normally, in CSMA/CD, re-tranamissionslot assign-
which options are practical and which are not. What mentsare intendedto be random.This methodgivesall
this meansis that in Table 3.1,an “N” shouldbe inter- stations an equal opportunityto utilize the serial com-
preted as mcaningthat the optionis either not practical municationlink but also leavesthe possibilityof anoth-
whenimplementedwith user sotlwareor that it cannot er collision due to two stations having the same slot
be done. An “O” is used when that functionis one of assignment.There is an optionon the C152 which al-
severalthat can be implemented with the GSC without lowsall the stations to havetheir slot assignmentspre-
additionalw software. viouslydetemrm “ .4 by user software. This pre-asaign-
ment of slots is called the deterministic resolution
The GSC is targeted to operate at bit rates up to 2.4 mode.This method allowsresolutionafter the first col-
MBps using the external clock options and up to 2 lisionand ensureathe acceasof the link to each station
MBps using the internal baud rate generator, internal during the resolution. Deterministicresolution can be
data formattingand on-chipclock recovery.The baud advantageouswhen the link is being heavily used and
rate generator allows most standard rates to be collisionsare frequentlyoccurringand in real time ap-
achieved. These standards include the proposed plicationswhere determinism is required.Deterministic
IEEE802.3LAN standard (1.OMBPS) and the T1 stan- resolutionmay also be desirableif it is knownbefore-
dard (1.544MBPs).The baud rate is derivedfrom the hand that a certain station’scommunicationneedsto be
crystal frequency.This makes crystal selectionimpor- prioritized over those of other stations if it is involved
g the frequencyand accuracy of
tant when determining in a collision.
the baud rate.
The user needsto be aware that after reaet, the GSC is 3.2.2 CSMAICD FRAME FORMAT
in C3MA/CD mode, IFS = 256 bit times, and a bit
The frame format in CSMA/CD consistsof a preamb-
time equals 8 oscillator periods.The GSC will remain
in this mode until the interfrarne space expires. If the le, Beginningof Frame tlag (BOF), address field, in-
user changesto SDLCmode or the parameters used in formationfield, CRCj and End of Frame flag (EOF) as
CSMA/CD, these changeswill not take effectuntil the shownin Figure 3.1.
interfrarne space expirea.A requirement for the inter-
frame space timer to beginis that the receiverbe in an PREAMBLE BOF ADDRESS INFO CRC EOF
idle state. This makes it possiblefor the GSC to te in Figure 3.1 Typical CSMA/CD Frame
someother modethan the user intendsfor a signifwant
amount of time after reset. To prevent unwantedGSC PREAMBLE- The preambleis a series of alternating
errors from occurring,the user should not enable the 1sand 0s. The length of the preambleis programmable
GSC or the GSC interrupts for 170 machine cycles to be O,8, 32, or 64bits. The purposeof the preambleis
((256 X 8)/12) after LNI bit is set. to allow all the receivers to synchronizeto the same
clock edges and identifiesto the other stations on-line
that there is activity indicatingthe link is being used.
3.2 CSMA/CD Operation For these reasons zero preamblelengthis not compati-
ble with standard CSMA/CD, protocols.When using
3.2.1 CSMA/CD OVERVIEW CSMA/CD, the BOF is consideredpart of the pream-
CSMA/CD operates by sensing the transmissionline ble compared to SDLC, where the BOF is not part of
for a carrier, whichindicateslinkactivity.At the end of the preamble. This meansthat if zero preamble length
link activity,a station must wait a pericd of time, called wereto be used in CSMA/CDmcde, no BOF wouldbe
generated.It isstronglyrecommendedthat zero preamb-
the deference period, before transmission my begin.
The deferenceperiod is also known as the interfrarne le length never be used in CSMA/CD mode. If the
space. The interframe space is explained in Section preamblecontains two consecutive0s, the preamble is
3.2.3. consideredinvalid. If tie C152detects an invalid pre-
amble the frame is ignored.
With this type of operation,there is alwaysthe possibil-
ity of a collisionoccurring after the deferenw period BOF-In CSMA/CD the Begirming-Of-Frarne is a part
due to line delays.If a collisionis detected after trans- of the preamble and consistsof two sequential 1s. The
missionis started, a jammingmechanismis used to en- PUPOXof the BOF is to identifythe end of the preamb-
sure that all stations monitoringthe line are aware of le and indicate to the receiver(s)that the address will
the collision.A resolutionalgorithmis then executedto immediatelyfollow.

I
7-20
intel. 83C152 HARDWARE DESCRIPTION

ADDRESS- The addreasfieldis usedto identifywhich algorithm can be used but IEEE 802.3 uses a 32-bit
messages are intended for which stations. The user CRC. The generation polynomialthe C152 uses with
must assign addresses to each destination and source. the 32-bitCRC is:
How the addresses are assigned,how they are main- G(X) = X32+ X26+ x23 + x22 + x16 + x12 +
tained, and how each transmitter is made aware of xll + x10 + x8 + x7 + X5 + x4 + X2
whichaddresses are availableis an issue that is left to +x+1
the user. Some suggestionsare discussed in Section
3.5.5.Generally,each addressis uniqueto each station The CRC generator, as shownin Figure 3.2, operates
but there are special eases where this is not true. In by taking each bit as it is receivedand XOR’ingit with
thesespecialcases, a messageis intendedfor more than bit 31 of the current CRC. This reaultis then placedin
one station. These multi-targetedmessagesare called temporary storage. The result of XOR’ingbit 31 with
broadcast or multicast-groupaddresses. A broadcast the receivedbit is then XOR’dwithbits O, 1, 3, 4, 6, 7,
address consistingof all 1s will always be receivedby 9, 10, 11, 15,21, 22, 25 as the CRCis shith?dright one
s31stations. A multicast-groupaddress usually is indi- position.When the CRC is shiftedrigh~ the temporary
cated by using a 1ss the first addressbit. The user can storage space holdingthe result of XOR’ingbit 31 and
chooseto mask off all or selectivebits of the address so the incomingbit is shifted into positionO.The whole
that the GSC receivesall messagesor multicaat-group processis then repeated with the next incomingor out-
messages.The address lengthis programmable to be 8 goingbit.
or 16bita.h addressconsistingof all 1swill alwaysbe
receivedby the GSC on the C152.The address bits are The user has no accessto the CRCgeneratoror the bits
always passed from the GSC to the CPU. With user which constitute the CRC while in CSMA/CD. On
software,the address can be extendedbeyond 16 bits, transmission, the CRC is automaticallyappended to
but the automatic address recognitionwill only work the data beingsent, and on reception,the CRC bits are
on a maximumof 16 bita. User software will have to not normally lcmdedinto the receive FIFO. Instead,
reaolveany remsiningaddressbits. they are automaticallystripped.Theonlyindicationthe
user has for the status of the CRC is a paaa/fail tlag.
INFO - This is the informationfield and cattis the The pass/fai3 flag only operates during reception. A
data that one deviceon the link wishesto transmit to CRC is consideredas passingwhenthe the CRC gener-
another device.It can be of any length the user wishes ator has 110001110000010011011010 O1111O11B as a
but needs to be in multiplesof 8 bits. This is because remainder after all of the daa including the CRC
multiplesof 8 bits are used to transfer data into or out checksum,from the transmitting station has been cy-
of the GSC FIFOS.The informationfield is delineated cled through the CRC generator.The prearnbl%BOF
from the rest of the componentsof the frame by the and EOF are not included as part of the CRC algo-
precedingaddress field and the followingCRC. The rithm. An interrupt is availablethat will interrupt the
receiverdetermines the positionof the end of the infor- CPU if the CRC of the receiveris invalid.The user can
mation field by passingthe bytes through a temporary enablethe CRC to be passedto the CPU by placingthe
storage space. When the EOF is receivedthe bytes in receiverin the raw receivemcde.
temporary storage are the CRC, and the last bit re-
ceivedpreviousto the CRC constitute the end of the This methcd of calculatingthe CRCis compatiblewith
informationfield. IEEE 802.3.
CRC - The CyclicRedundancyCheck (CRC) is an er- EOF - The End Of Frame indicateswhenthe transmis-
ror checkingalgorithm commonlyused in serial com- sion is completed.The end flagitsCSMA/CD consists
munications.The C152offerstwo types of CRC algo- of an idle condition.h idle conditionis assumedwhen
rithms, a lWit and a 32-bit.The Id-bit algorithm is there is no transitions and the linkremainshighfor 2 or
normallyused in the SDLCmodeand will be described more bit times.
in the SDLCsection.In CTMA/CDapplicationseither

7-21
i~. 83C152 HARDWARE DESCRIPTION

?Jn=d -.
Figure
. - ---
3.2. GHG
- .
cienerator
270427-8

3.2.3 INTERFRAME SPACE In most amlicatiorm the rxriod of the interframespace

will be e@l to or ”greakr than the amount of iime
The interframespaceis the amountof time that trans- needed to turn-around the received frame. The tum-
missionis delayed after the link is sensed as beingidle armsndperiod is the amount of time that is neededby
and is used to separate transmittedframes. In alternate user software to complete the handling of a received
backoffmock the interframespacemay also be includ- frame and be prepared to receive the next frame. An
ed in the determma“ tion of whenretransmissionsmay interframespacesmallerthan the requiredturn-around
actually begin. The C152 allowsprogrammable inter- period could be used, but would allowsomeframes to
frarmespaces of even numbers of bit times from 2 to be missed.
256. The hardware enforces the interfkasnespace in
SDLC mode as well as in CSMA/CD mode. When a GSCtransmitter has a new messageto aend,it
will fmt sensethe link. If activityis detected,trrmamis-
The period of the interframespaceis determinedby the sion will be deferredto allow the frame in progressto
contents of Ill% IFS is an SFR that is programmable complete.Whenlink activity ceases,the station contin-
from Oto 254.The interframespaceis measured in bit ua deferringfor one interframe spaceperiod.
times. The value in IFS multiplied by the bit time
equals the interframe space unlessIFS equals O.If IFS As mentionedearlier, the interframe spaceis used dur-
does equal O,then the istterframespace will equal 256 ing the collisionresolutionperiodas wellas duringnor-
bit times. Gne of the considerationswhereloading the mal transmission.The backoff method selectedaffects
IFS is that only evennumbers(L3Bmust be O)can be how the deference period is handled during normal
usedbecauseonlythe 7 most significantbits are loaded transmission.If normal backoff mode is selected, the
into Ii% The LSBis controlledby the GSC and deter- intcrframespacetimer is reset if activityoccurs during
mineswhich half of the IFS is currentlybeingused. In approximatelythe tint half of the interframespace. If
some modes, the istterfratnespacetimer is m-triggered alternate backoff or deterministic backoff is selected,
if activity is &tected during the fmt half of the period. the timer is not reset. In all cases whenthe interfmme
The GSC determm “ es whichhalfof the interfratne spw space timer expires,transmissionmay begin,regardless
is currently being used by examiningthe LSB. A one if there is activity on the link or not. Although the
indicates the first half and zero indicates the second C152resets the interframe space timer inactivityia de-
half of the IFS. tected duringthe fmt one-halfof the interffamespace,
this is not necessarilytrue of all CSMA/CD systems.
After reset IFS is O,whichdelaysthe first transmission (IEEE 802.3recommendsthat the interframespace be
for both SDLC and CSMA/CD by 256 bit times (atk reset if activityis detectedduring the first two-thirdsor
reaet, a bit time equals 8 oscillatorclock periods). less of the interframespace.)

7-22
i~. 83C152 HARDWARE DESCRIPTION

3.2.4 CSMA/CDDATA ENCODING Narrow Pulses

Manchesterencoding/deccdingis automaticallyselect- A valid Manchester waveformmust stay high or low

ed whenthe user softwareselectsC3MA/CD transmis- for at least a half bit-timq nominally4 sample-times.
sion mode (See Figure 3.3). In Manchester encoding Jitter toleranceallowsa waveformwhichstays high or
the value of the bit is determined by the transition in low for 3 sampls4mes to also be ansidered vafid. A
the middleof the bit time, a positivetransitionis decod- samplesequencewhich showsa secondtransitiononly
ed as a 1 and a negative transition is decodedas a O. 1 or 2 sample-timesafter the previoustransitionis con-
The Addressand Info bytes are transmitted LSBfret. sidered to be the result of a collision. Thus, sample
The CRC is transmitted MSBfirst. sequencessuch as 0000110000and 111101111are inter-
preted as collisions.
If the external 1Xclock fatssre is chosenthe transmiss-
ion mode is always NICZ(see Section3.5.11).Using The GSChardware recognizesthe collisionto haveoc-
CSMA/CD with the external clock option is not sup- curred within 3/8 to 1/2 bit-time followingthe second
ported becausethe data needs reformattingfrom NRZ transition.
to Manchesterfor the receiverto be able to detect code
violationsand collisions.
Missing O-to-1 Transition

3.2.5 COLUSION DETECTION A O-to-1transitionis expectedto occurat thecenterof

any bit cell that beginswith O. If the previous l-to-o
The GSChardwaredetectscollisionsby detectingMan- transition occurredat the bit cell edge,ajitter tolerance
chester waveformviolations at its GRXD pin. Three of t 1 sample is allowed. Sample sequencessuch as
kinds of waveformviolations are detected: a missing 11114MO01111 and 1111:OOOIM1lllare valid, where
O-to-1transitionwhereone was expected,a l-to-o tran- “:” indicates a bit cell edge. SeqUenmsof the form
sition where none was expected,and a waveformthat 1111.00@300XXXare interpreted as collisions.
stays low (or high) for too short a time.
For theae kinds of sequences,the GSC recognizesthe
collisionto have occurred within 1 to 1 1/8 bit-times
Jitter Tolerance after the pnwious l-to-Otransition.
A validManchesterwavefomrmust havea transitionat
the midpointof any bit ceU,and may have a transition If the previous l-to-Otransition occurredat the center
at the edge of any bit cd. Therefore transitions will of the previousbit cell, a jitter toleranceof +2 samples
nominallybe separated by either 1/2 bit-time or 1 bit- is allowed. Thus, sample sequences such as
11110000:00001 111~d 1111OOOOO:OOOOO1111 are val-
time. id. Sequencesof the form 111100COO: @XIOOOXXX are
interpreted as collisions.
The GSCsamplesthe GRXD pin at the rate of 8 x the
bit rate. The sequenceof samplesfor the receivedbit
sequence001wouldnominallybe: For these kinds of sequences,the GSC recognize the
collisionto have occurred within 1 5/8 to 1 3/4 bit-
samples:11110 000:1 111 O00O:OO001 111 :
times after the previous l-to-Otransition.
bitvalue: O : o: 1“
: <-bit cell->: <-bit cell->: <-bit cell-> ~ Unexpected l-to-O Transition

The samplingsystem allows a jitter tolerance of * 1 If the line is at a logic 1duringthe first half of a bit cell,
samplefor t-tions that are 1/2 bit-time apart, and then it is expectedto make a l-to-Otransition at the
*2 samplesfor transitions that are 1 bit-timeapart. midpointof the bit cell. If the transition is missed,it is
assumedthat this bit cell is the tlrst half of an EOF tlsg

0:1:1:0:0:1:

MANCHESTER

El? ‘ ,
,
Ii
,
- 71ME-
270427-14

Figure 3.3. Manchester Encoding

7-23
int& 83C152 HARDWARE DESCRIPTION

(line idle for two bit-times). One bit-time later (which (GREN = O), and the Receive Error Interrupt tlag
marks the midpointof the next bit cell),if there is still RCABT is set. If DCR has beerr selected, the GSC
no l-to-Otransition, a valid EOF is assumedand the participatesin the resolutionalgorithm.
line idle bit (LNI in TSTAT) gets set.
Incomingbits take 1/2 bit time to get tlom the GRXD
However,if the assumed EOF flag is interrupted by a pin to the bit decoder. The bit deccder strips off the
l-to-Otransition in the bit-time followingthe fmt miaa- preamble/BOFbits, and the first bit at%r BOF is sbift-
ing transition, a collision is assumed.In that case the ed into a serial strip buffer. The length of the strip
GSC hardware recognizes the collision to have oc- buffer is equal to the number of bits in the selected
curred within 1/2 to 5/8 bit-time after the unexpected CRC. It is within this buffer that address recognition
transition. takes place. If the address is recognized as one for
which reception should proceed, then when the first
addressbit exitsthe strip but% it is shiftedinto an 8-bit
3.2.6 RESOLUTION OF COLLISIONS shift register.When the shift registeris fidl, its content
Howthe GSC reapondsto a detectedcollisiondepends is transferred to RFIFO. That is the event that deter-
on what it was doing at the time the collisionwas de- mineswhether a collisionsets RCABTor not.
tected. What it might be doingis either transmittingor
receivinga frsmq or it might be inactive. GSC Transmitting
If the GSC is in the processof transmitting a frame at
GSC Inactive the time the collisionis detected it will in every case
The collisionis detected whether the GSC is active or executeits jam/bac koff procedure.Its reponaebeyond
not. If the GSC is neither transmittingnor receivingat that dependson whetherthe first byte of the frame has
the time the collisionis detected, it takes no action un- been transferred from TFIFO to the output shift regis-
less user softwarehas selected the DeterministicColli- ter yet or not. That trarrsfertakesplaceat the beginning
sion Resolution (DCR) algorithm. If DCR has been of the first bit of the BOF;that is, 2 bit-timesbeforethe
selected,the GSC will participate in the resolution al- end of the prearnble/BOFsequence.
gorithm.
If the transfer from TFIFO hasn’t occumed ye~ the
GSC hardware will try again to gain access to the line
GSC Receiving after its baekofftime has expired. Up to 8 automatic
restarts can be attempted.If the 8th restart is interrupt-
If theGSCis alreadyin the processof receivinga frame ed by yet snother collision,the transmitter is disabled
at the time the collision is detected, its reaponse de- (TEN = O) and the Transmit Error Interrupt flag
pends on whether the first byte of the frame has been TCDT is set.
transferred into RF3F0 yet or not. If that hasn’t oc-
curredj the GSC simplyaborts the reception,but takes If the trsnsfa from TFIFO occursbeforea collisionis
no other action unless DCR has beenselected.If DCR detected, the transmitter is disabled (TEN = O) and
has been selected, the GSC participates in the resolu- the TCDT tlag is set.
tion algorithm.
The responseof the GSC to detectedcollisionsis sum-
If the reception has rdready progressedto the point marized in Figure 3.4.
where a byte has been transferred to RFIFO by the
time the collision is detected, the receiveris disabled
I What the GSC waa doing I Reaponae I
nothing None,unless DCR = 1.
If DCR = 1, beginDORcountdown.
Receivinga Frame, firat None, unlessDCR = 1.
byte not in RFIFO yet. If DCR = 1, beginDCR countdown.
Receivinga Frame, first Set RCABT,clear GREN.
byte already in RFIFO. If DCR = 1, beginDCR countdown.

I Transmittinga Frame, first

bvte stillin TFIFO I Executejam/backoff.
Restartif collisioncount s8. I
Transmittinga Frame, first Executejam/backoff.
byte already taken fromTFIFO -SetTCDT, clearTEN.
Figure 3-4. Response to a Deteoted Collision. References to DCR and the DCR Countdown
Have to 00 with the Deterministic Collision Resolution Algorithm.
7-24
i~. 83C152 HARDWARE DESCRIPTION

Jam In the Deternums

“ “tic algorithm, the GSC backs off to
await its predetermined turn.
The jam signalis generatedby any 8XC152 that is in-
volvedin transmittinga frame at the time a collisionis
detectedat its GRXD pin. This is to ensure that if one Random Backoff
transmittingstation detectsa collision,all the other sta- In either of the random algorithms,the first thing that
tions on the networkwill also detect a collision. happens after a collision is detected is that a 1 geta
shifted into the TCDCNT (Transmit Cdliaion Detect
Ifa transmitting8XC152detects a collisionduringthe Count) register, from the right.
prearnble/BOF part of the fkame that it is trying to
transmit, it will completethe preamble/BOF and then Thus if the software cleared TCDCNT before telling
begin the jam signal in the fmt bit time after BOF. If the GSC to transmit, then TCDCNT keeps track of
the collisionis detected later in the frame, the jam sig- how many times the transmission had to be aborted
nal willbeginin the next bit time after the collisionwas because of collisions:
detected.
TCDCNT = ~ first attempt
Thejam signallasts for the samenumberof bit timesas OMOOOOl first collision
the selectedCRC length-either 16-or 32-bittimes. OOOOQO1l second collision
The 8XC152provideatwo typeaofjam signalsthat can mill third collision
be selectedby user software.If the node is DC-coupled Oooo1111 fourth collision
to the networlqthe DCjam can be selected.In this case ...... .. .....
the GTXD pin is pulled to a logicOfor the durationof
the jam. If the nodeis AC-coupledto the networlqthen 11111111 eighth collision
AC jam must be selected. In this case the GSC takes
the CRC it has calculatedthus far in the transmission, After TCDCNT gets a 1 shifted into it, the logical
inverts each bit, and transmits the inverted CRC. The AND of TCDCNT and PRBS is loaded into a count-
selectionof DC or AC jam is made by setting or clear- down timer named BKOFF. PRBS is the name of an
ing the DCJ bit, which resides in the SFR named SFR which contains the output of a pseudo-random
MYSLOT. binary sequencegenerator. Its function is to providea
random number for usc in the backoffalgorithm.
When the jam signal is completed, the 8XC152goes
into an idle state. Preamneably,other stations on the Thus on the first collisionBKOFF gets loadedrandom-
networkare also generatingtheir ownjam signals,after ly with either OM030Mlor OOWO@31. If there is a sec-
whichthey too go into an idle state. When the 8XC152 ond collisionit getsloadedwith the randomselectionof
detects the idle state at its ownGRXD pin, the backoff OOOWOOO, ~1, @XXOOIO, or OtMOOO1l. On the
sequencebegins. third collisionthere willbe a randomselectionamong8
possiblenumbers.On the fourth, among 16,tic. Figure
Backoff
3.5showsthe logicalarrangementof PRBS,TCDCNT,
and BKOFF.
There are threesoftwareselectablecollisionresolution
algorithms in the 8XC152.The selection is made by BKOFF starts counting down from its prebad value,
writingvaluesto 3 bits: counting slot times. At any time, the current value in
BKOFF can be read by the CPU, but CPU writes to
DCR Ml MO Algorithm BKOFF have no effect. While BKOFF is counting
o 0 0 Normal Random down, if its current value is not O,transmissionis dis-
o 1 1 Alternate Random
abled. The output signal “BKOFF = O“ is asserted
whenBKOFF reachesO,and is used to re-enabletrans-
1 1 1 Deterministic
mission.

Ml and MO rside in GMOD, and DCR is in At that time tranrimission cart proceed, subject of
MYSLOT. course to IFS enforcement,unless:
● shiftinga 1 into TCDCNT from the right caused a 1
In the Normal Random algorithm, the GSC backs off to shift out from the MSBof TCDCNT, or
for a random number of slot times and then decides
whether to restart the transmission.The baekofftime . the collisionwas detected after TFIFO had been ac-
beginsas soonas a line idle conditionis detected. cessedby the transmit hardware.

The Alternate Random algorithm is the same as the

Normal Random except the backofftime doesn’tstart
until an IFS has trStlS@d.
7-25
int# 83C152 HARDWARE DESCRIPTION

1 PRBS
I

AND
I
II
LOAD
BKOFF
8

SLOT
CLOCK
6

COMP + BKOFF=MYSLOT

6 —

270427-38

Figure 3.5. BackOffTimer Logic

In either of these cases, the transmitter is disabled most protocols, the slot period must be equal to or
(TEN = O)and the Transmit Error flag TCDT is set. greater than the longest round trip propagation time
The automatic restatl is eaneeled. plus the jam time.

Where the Normal and Alternate Random backoffal-

gorithms differ is that in Normal Random baekoffthe Deterministic Backoff
BKOFF timer starts counting down as soon as a line In the Determinestic backoffmod%the GSCis assigned
idle condition is detected, whereas in Alternate Ran- (in software)a slot number.The slot assignmentk writ-
dom backoff the BKOFF timer doesn’t start counting ten to the low 6 bits of the register MYSLOT.This
down till the IFS expirea. same register also Contain$in the 2 high bit positions,
the control bits DCJ and DCR.
The Alternate Random mode was deaigned for net-
worksin whichthe slot time is leasthan the IFS. If the Slot assignmentsthereforecan run from Oto 63. It will
randomlyaasignedbackofftime for a giventranstm“tter turn out that the higherthe slot assignment,the sooner
happens to be O,then it is free to transmit as soonas the the GSCwill get to restart its transmissionin the event
IFS ends. If the slot time is shorter than the IFS, Nor- of a collision.
mal hndom mode would nearly guarantee that if
there’s a first collisionthere will be a second collision. The higheatslot assignmentin the network is written
The situation is avoided in Alternate Random mode, by each station’s software into its TCDCNT register.
since the BKOFF countdowndoean’tstart till the IFS Normally the higheatslot assignmentis just the total
is over. number of stations that are goingto participate in the
backoffalgorithm.
The unit of count to the BKOFF timer is the slot time.
The slot time is measured in bit-times, and is deter- In deterministicbackoffmodea collisionwill not cause
mined by a CPU write to the register SLOTTM.The a 1 to be sltitled into TCDCNT.TCDCNTwill still be
slot time clock is a l-byte downcmnter which starts its ANDed with PRBSand the result loadedinto BKOFF.
countdownfrom the value written to SLOTTM. It is In order to insure that all stations have the same value
decremented each bit time when a backoff is in prog- loaded into BKOFF, which determines the first slot
ress, and when it gets to 1 it generates one tick in the number to cccur, the PRBS should be leaded with
slot time clock.The next state after 1 is the reloadvalue OFFH;the PRBS will maintain this value until either
which was written to SLOTTM.If Ois the value wnt- the 8XC152is reset or the user writessomeother value
terr to SLOTTM,the slot time clock will equal 256bit into PRBS.After BKOFF is loadedit beginscounting
times. downslot times as soonas the IFS ends. Slot times are
definedby the user, the same wayas before,by loading
A CPU write to SLOTTMamesses the reload register. SLOTTMwith the number of bit times per slot.
A CPU read of SLOITM acassea the downcounter.In
7-26
intdo 83C152 HARDWARE DESCRIPTION

When BKOFFequalsthe slot assignment(as definedin A transmitting station with HABEN enabled expects
MYSLOT),the signal “BKOFF = MYSLOT’in Fig- an acknowledge.It must receiveone prior to the end of
ure 3.5 is asserted for one slot time, during which the the interframe space, or else an error is assumed and
GSC can restart its transmission. the NOACK bit is set. Setting of the TDN bit is also
delayeduntil the end of the interframespace.Collisions
While BKOFF is countingdown,if any activity is de- detected during the interframe space will also cause
tected at the GRXD pin, the countdownis frozen until NOACKto be set.
the activity ends, a line idle conditionis detected, and
an IFS transpires. Then the countdownresumes from If the user softwarehas enabled DMA seMcing of the
where it left off. GSC,an interrupt is generatedwhenTDN is set. TDN
willbe set at the end of the interframespace ifa hard-
If a collision is detected at the GRXD pin while warebasedacknowledgeis requiredand received.If the
BKOFF is countingdown,the collisionresolutionalgo- GSCis servicedby the CPU, the user must time out the
rithm is restarted from the beginning. interfkamespace and then check TDN before disabling
the transmitter or transmit error interrupts. NOACK
In effeckthe GSC “owns”its assignedslot number,but will generatea transmit error interrupt if the transmit-
with one exception. Nobody owns slot number O. ter and interrupts are enabled during the interframe
Therefore if the GSC is assignedslot number O, then space.
when BKOFF = O,this station and any other station
that has something to say at this time will have an
equal chance to take the line. 3.3 SDLCOperation

3.2.7 HARDWARE BASED ACKNOWLEDGE 3.3.1 SDLC OVERVIEW

Hardware BasedAcknowledge(HBA) is a data link SDLCis a communicationprotocoldevelopedby IBM

packet acknowledgingscheme that the user software and widelyused in industry. It is baaedon a primary/
can enable with CSMA/CD protocol. It is not an op- secondaryarchitecture and requires that each second-
tion with SDLCprotocol however. ary station have a unique address. The secondary sta-
tionscan onlycommunicateto the primarystation, and
In general HBA can give improved system response then, only when the primary station allowscommuni-
time ad increasedeffectivetransmissionrates over ac- cation to take place. This eliminatesthe possibilityof
knowledgeschemesimplementedin higherlayersof the contentionon the serial line caused by the Secon-
network architecture. Another benefitis the possibility station’strying to transmit simultaneously.
of early release of the transmit buffer as soon as the
acknowledgeis received. In the C152,SDLCcan be configuredto work in either
Ml or half duplex,When adheringto strict SDLC pro-
The acknowledgeconsistsof a preamblefollowedby an tocol, full duplex is required. Full duplex is selected
idle condition. A receivingstation with HABEN en- whenevera 16-bitCRC is selected.At the end of a valid
abled will send an acknowledgeonly if the incoming reset the id-bit CRC is selected. To select half duplex
address is unique to the receiving station and if the with a 16-bitCRC, the receiver must be turned off by
frame is determinedto be correct with no errors. For user software before transmission. The receiver is
the acknowledgeto be scnLTEN must be set. For the turned Off by chrin g the GREN bit (RSTAT.1).The
transmitting station to recognize the acknowledge receiverneedsto be turned off becausethe address that
GREN must be set. A zero as the LSBof the address is transmitted is the address of the secondarystation’s
indicatesthat the addreasis uniqueand not a group or receiver.If not turned off, the receivercould mistake
broadcast address. Errors ean be caused by collisions, the outgoingmessageas beingintendedfor itaelf.When
incorrect CRC, misalignment,or FIFO overflow.The 32-bitCRCSare used, half duplex is the only method
receiver sends the acknowledgeas soon as the line is availablefor transmission.
sensedto be idle.The user must programthe interhme
space and the preamble length such that the acknowl-
edge is completedbefore IFS expirea.This is normally
done by programmingIFS larger than the preamble.

7-27
intele 83C152 HARDWARE DESCRIPTION

3.3.2 SDLC Frame Format CONTROL- The control fieldis used for initialization
of the system,iden~g the sequenceof a frame to
The format of an SDLC frame is shownin Figure 3.6. identfi if the message is complem to teU secondary
The frame consists of a Beginningof Frame flag, Ad- stationsifa responseis expected,and acknowledgement
dress field, Control Field, Informationfield (optional), ofpreviouslysent frames.The user softwareis responsi-
a CRC, and the End of Frame flag. ble for m
‘ scrtion of the control field as the GSC hard-
ware has no provisions for the management of this
I BOF I ADDRESS I CONTROL I INFO I CRC I EOFI field. The interpretation and formation of the control
fieldmust also be handledby user software.The infor-
Figure 3.6. Typical SDLC Frame mation followingthe control field is typicallyused for
informationtransfer, error reporting,rmdvariousother
BOF - The begin of frame flag forSDLCis0111 1110. functions.Thesefunctionsare accomplishedby the for-
It is onlyone of two possiblecombinationsthat have six mat of the control field. There are three formats avail-
consecutiveones in SDLC. The other possibilityis an able. The types of formats are Informational,Supervi-
abort character which consistsof eightor more consec- sory,or Unnumbered.Figure3.7showsthe variousfor-
utive ones. This is because SDLC utilizes a process mat typesand how to identifythem.
calledbit stutling. Bit stuffingis the insertion of a Oas
the nextbit everytime a sequenceof fiveconsecutive1s Sincethe user softwareis responsiblefor the implemen-
is detected.The receiver automaticallyremovesa Oaf- tation of the control field,what followsis a simpleex-
ter everyconsecutivegroup of fiveones. This removrd planationon the control field and its timctions.For a
of the Obit is referred to as bit stripping.Bit stuffingis completeunderstandingand proper implementationof
discussedin Section 3.3.4.All the proceduresrequired SDLC, the user should refer to the IBM document,
for bit stutling and bit strippingare automaticallyhan- GA27-3093-2,IBM SynchronousData Link Control
dled by the GSC. GeneralInformation.Withinthat document,is another
list of IBM documents which go into detail on the
In standardSDLCprotocolthe BOFsignalsthe start of SDLCprotocoland its use.
a frame and is limited to 8 bits in length. Sincethere is
no preamblein SDLC the BOF is consideredan entire The control field is eight bits wide and the fomnatis
separate field and marks the &ginning of the ffame. determined by bits Oand 1. If bit Ois a zero, then the
The BOF also scrv= as the clock synchronisation frameis an informationalframe. If bit Ois a oneand bit
mechanismand the referencepoint for determining g the 1 a zero, then it is a supervisoryframej and if bit Ois a
positionof the addreas and control fields. one and bit 1 a one then the frame is an unnumbered
frame.
ADDRESS- The addressfieldis usedto identifywhich
stations the message is intended for. Each secondary In an informational frame bits 3,2,1 contain the se-
station must have a unique address. The primary sta- quencecount of the frame beingsent.
tion must then be made aware of which addresses are
assignedto each station. The addresslength is specitied Bit 4 is the P/F (Poll/Final) bit. If bit 4 equals 1 and
as 8-bitsin standard SDLC protocolsbut it is expand- originatesfrom the primary,then the secondarystation
able to 16-bitsin the C152.User software can further is expectedto initiate a transmkaion. If bit 4 equals 1
expandthe number of address bits, but the automatic and originatesfrom a secondarystatiorhthen the frame
addressrecognitionfeature workson a maximumof 16- is the finalframe in a transmission.
bits.
Bits 7,6,5contain the sequencecmmt a station expects
In SDLC the addresses are normally unique for each on the next transmissionto it. The sequencecount can
station. However,there are severalclassesof messages vw from OOOB to 11lB. The count then starts over
that are intendedfor more than onestation. Thesemes- againat OOOB atler the value 11IB is incremented.The
sagesare called broadcast and groupaddressedframea. acknowledgementis recognizedby the receivingstation
An addressconsistingof all 1swillalwaysbe automati- when it decodesbits 7,6,5of an incomingframe. The
cally receivedby the GSfGthis is deilnedas the broad- station sendingthe transmissionis acknowledgingthe
cast addreas in SDLC. A group address is an ad&ess framesreceivedup to the count representedin bits 7,6,5
that is common to more than one station. The GSC (sequencecount-l). With this method, up to sevense-
providesaddr$ssmaskingbits to providethe capability quential framea may be trsnamitied prior to an ac-
of receivinggroup addresses. knowledgementbeingreceived.If eight frameswere al-
lowedto passbeforean acknowledgement,the sequence
If desired,the user softwarecan mask off all the bits of count wouldroll over and this would negate the pur-
the address. This type of maskingputs the GSC in a pose of the sequencenumbers.
promiscuousmode so that all addressesare received.

7-28
i~. 83C152 HARDWARE DESCRIPTION

Posmo% —7 6 5 4 3 2 1 0
RE~EPT~10N POLL\ S~NDl$JG
SEQUENCE ‘NAL SEi2UEfi CE o
270427-15

lECEPTION SEQUENCE- The sequenceexpectedin the SENDING SEQUENCEportion of the controlbyte

n the nextreeeivedframe.This alsoconfirmsrmrrectrqtion of up to sevenframesprior to the aequeneegiven.
?OLL/FINAL - Identifiesthe frame as being a pollingrequest from the master station or the last in a serieaof
ktrnezfrom the master or aeeondary.
~ENDINGSEQUENCE- Identifiesthe sequeneeof the frame beingtransmitted.
) - If bit O = Othe frame is identifiedas a informationalformat type.

INFORMATION
-------------------------------------------------------
FORMAT
El?
POSMONS —7 6 5 4 3 2 1 0
RE~EPT;10 N POLL/ ~ (j~E /
SEQUENCE ‘lNM i 0,1

270427-16

RECEPTIONSEQUENCE- Expectedsequeneeof frame for next reception.

POLL/FINAL - Identities frame as being a pollingrequest from the master station or the last in a series of
h-armsfrom the master or seeondary.
MODE- Identifieswhetherreceiveris ready (00),not ready (10)or a framewasrejected(01).The rejectedframe
[Sidentitkd by the reeeptionsequence.
2,1- If bits 1,0 = 0,1 the frame is identifiedas a supervisoryformat type.

SUPERVISORY FORMAT
,-------------------------------------------------------
BIT
POSMONS —-7 6 5 4 3 2 1 0
C~MMA$D/ IWLL/ COMtiAND/ /
R@ PO~SE FINAL RESP@NSE 11 :

270427-17

COMMAND/RESPONSE- Identifks the type of emmand or response.

POLL/FINAL - Identifies frame as being a pollingrequest from the master station or the last in a series of
framesfrom the master or seeondary.
1,1- If bits 1,0 = 1,1the frame is identifiedas an unnumberedformat type.

NONSEQUENCED FORMAT 270427-18

Figure 3.7. SDLC Control Field

7-29
i~. 83C152 HARDWARE DESCRIPTION

Followingthe informationalcontrol field comesthe in- When the modeis 10,the sendingstation is indicating
formationto be transferred. that its receiveris not ready to accept frame.

In the supervisoryformat (bits 1,0 = 0,1) bits 3,2 de- Mode 11is an illegalmode in SDLC protocol.
terrnine whichmode is beingused.
Bits 7,6,5 representthe value of the sequencethe sta-
Wherrthe modeis 00 it indicatesthat the receiveline of tion expectswhenthe next transfer occurs for that sta-
the station that sent the supervisoryframe is enabled tion. There is no informationfollowingthe controlfield
and reSdyto SCCeptframes. when the supervisoryformat is used.

When the mode is 01, it indicates that previouslya In the unnumberedformat ~ts 1,0 = 1,1)bits 7, 6,5,
received frame was rejected. The value in the receive 3, 2 (notice bit 4 is missing)indicate commandstlom
count identifieswhich frame(s) need to be retrarsssnit- the primaryto secondarystations or requestsof sexxmd-
ted. ary stations to the primary.

The standardcommandsare:
BITS 7 6 5 3 2 Command
00000 UnnumberedInformation(Ul)
00001 Set initializationmode (SIM)
01000 Disconnect(DISC)
00100 Responseoptional(UP)
11001 Functiondescriptorin
informationfield (CFGR)
10111 Identificationin informationfield. (XID)
11100 Test patternin informationfield. (TEST)

The standardresponsesare:
BITS 7 6 5 3 2 Command
00000 Unnumberedinformation(Ul)
00001 Requestfor initialization(RIM)
00011 Stationin disconnectedmode (DM)
10001 Invalidframe reoeived(FRMR)
01100 Unnumberedacknowledgement(UA)
11111 Signalloseof input(BCN)
11001 Functiondescriptorin informationfield (CFGR)
01000 Stationwantsto disconnect(RD)
10111 Identificationin informationfield (XID)
11 100 Test patternin informationfield (TEST)

7-30
intd. 83C152 HARDWARE DESCRIPTION

In an unnumbered fraroq information of variable rithms, a 16-bit and a 32-bit.The 32-bit algorithm is
length may followthe control field if UI is used, or normally used in CSMA/CD applications and is de-
information of fixed length may follow if FRMR is scribed in section 3.2.2.In most SDLC applications a
used. 16-bitCRC is usedand the hardwareconfigurationthat
supporta16-bitCRC is shownin Figure3.8.The gener-
As stated earlier,the user softwareis responsiblefor the ating polynomialthat the CRC generatoruses with the
proper managementof the control field.This portionof 16-bitCRC is:
the frame is passedto or from the GSC FIFOSas basic
informationaltype data. G(X)= x16 + X12+ X5+ 1

INFO - ‘lMs is theinformationfield and contains the The way the CRC operatesis that as a bit is receivedit
data that one deviceon the link wishesto transmit to is XOR’dwith bit 15of the current CRC and placed in
another device.It can be of any lengththe user wishesj temporary storage. The result of XOR’ingbit 15 with
but must be a multipleof 8 bits. It is possiblethat some the receivedbit is then XOR’dwith bit 4 and bit 11as
ffames may containno informationfield.The informa- the CRC is shitled one positionto the right. The bit in
tion field is identifiedto the receivingstations by the temporaryatorageis shiftedinto positionO.
preceding control field and the followingCRC. The
GSC determineswherethe last of the informationfield The required CRC length for SDLC is 16 bits. The
is by passing the bits through the CRC generator. CRC is automaticallystrippedfrom the frame and not
When the last bit or EOF is receivedthe bits that re- passed on to the CPU. The last 16 bits are then run
main constitute the CRC. though the CRC generator to insure that the correct
remainder is left. The remainderthat is checked for is
CRC - The CyclicRedundancyCheck(CRC) is an er- 0011101000011 1lB (lDOF Hex). If there is a mis-
ror checking sequencecommonlyused in serial comm- match, an error is generated.The user softwarehas the
unications. The C152 offers two types of CRC algo- optionof enablingthis interruptso the CPU is notified.

“g?-’yq+ 270427-19

Figure 3.8. 15-Bit CRC

7-31
intel. 83C152 HARDWARE DESCRIPTION

EOF - The End Of Frame (EOF) indicates when the 3.3.5 SENDINGABORTCHARACTER
transmissionis complete.The EOF is identitkd by the
end nag. An end flag consists of the bit pattern h abort character is one of the exceptionsto the rule
01111110.The EOF can also serve as the BOF for the that disallowsmore than 5 consecutive1s. The abort
next frame. character consists of any occurrenceof seven or more
consecutiveones. The simplest way for the C152 to
send an abort character is to clear the TEN bit. This
3.3.3 DATA ENCODING causesthe output to be disabledwhich,in turn, forceait
to a constant high state. The delay necessmy to insure
The transmission of data in SDLC mode is done via
NRZI encodingas shownin Figure 3.9. NRZI encod- that the link is high for sevenbit times is a task that
ing transmits &ta by changingthe state of the output needsto be handledby user software.Other methodsof
whenever a O is being transmitted. Whenever a 1 is sendingan abort character are usingthe IF3 registeror
transmitted the state of the output remainsthe same as using the Raw Transmit mode.Using IFS still entails
the previous bit and remains valid for the entire bit Clearing the TEN bit, but TEN can be immediatelyre-
time. When SDLC mode is selected it automatically enabled.The next messagewill not begin until the II%
enables the NRZI encodingon the transmit line and expires. The IF3 begins timing out as soon as ~
NRZI decodingon the receiveline. The Address and goeshigh whichidentifiesthe end of transmission.This
Info bytesare transmitted LSBfirst. The CRC is trans- also requiresthat IFS containa valueequalto or great-
mitted MSBtirst. exthan 8. This methodmay havethe undesirableeffect
that ~ goes high and disablesthe external drivers.
The other alternative is to switch to Raw Transmit
3.3.4 BIT STUFFING/STRIPPING mode.‘fhen, writingOFFHto TFIFO wouldgeneratea
-output for 8 bit times. This method would leave
In SDLCmodeone of the primaryndea of the protocol DEN active during the tramnus ‘ “onof the abort char-
is that in any normal data transmission,there willnever acter.
be an occurrence of more than 5 consecutive 1s. The
GSCtakes care of this housekeepingchore by automat- Whenthe receiverdetectssevenor more consecutive1s
icallyinsertinga Oafter everyoccurrenceof 5 consecu- and data has been loaded into the receive FIFO, the
tive 1s and the receiver automaticallyremoves a zero RCABT flag is set in RSTAT and that fkame is ig-
after receiving5 consecutive1s.All the neceamrysteps nored. If no data has been loaded into the receive
requiredfor implementingbit stufig and strippingare FIFO, there are no abort flagsset and that frame isjust
incorporated into the GSC hardware. This makes the ignored. A retransmitted frame may immediatelyfol-
operationtransparent to the user. About the only time low an abort character, providedthe proper flags are
this operation becomes apparent to the user, is if the used.
actual data on the transmissionmediumis beingmoni-
tored by a device that is not aware of the automatic
insertion of 0s. The bit stufthghtripping guarantees
that there will be at least one transition every 6 bit
times whilethe line is active.

, 0:1:1:0:0:1;

NRZI
I
,
BIT ‘
- nME -
270427-20

Figure3.9.NRZIEncoding

7-32
i~e 83C152 HARDWARE DESCRIPTION

3.3.6 LINE IDLE passing the message to the downstreamstation. This

delay is neceasmyso that a station csn decodeits own
If 15or more consecutive1sare detectedby the receiv- address before the message is passed on. The various
er the Line Idle bit (LNI) in TSTATis set. Tbe seven networksare shownin Figure 3.10.
Is from the abort character maybe includedwhensens-
ing for a line idle condition.Thesamemethodsusedfor
sending the Abort character can be used for creating 3.3.9 HDLCISDLC COMPARISON
the Idle condition.However,the values wouldneed to HDLC (High level Dsta Link Control)is a standard
be changed to reflect 15bit times, instead of severebit
adopted by the International Standards Organization
times. (IsO). The HDLC standard is definedin the 1S0 docu-
ment r#ISO6159- HDLC unbalancedclassesof proce-
3.3.7 ACKNOWLEDGEMENT dures. IBMdevelopd the SDLCprotocolas a subsetof
HDLC. SDLC conforms to HDLC protocol require-
Acknowledgmentin SDLC is an implied acknowledge ments, but is more restrictive. SDLC contains a more
and is containedin the mntrol field.Part of the control precisedefinitionon the modes of operation.
frame is the sequence number of the next expected
frame. This sequence number is called the Receive Some of the major differences between SDLC and
Count. In transmittmg“ the ReceiveCount, the receiver HDLC are:
is in fact acknowledgingall the previousframesprior to SDLC HDLC
the count that was transmitted. This allows for the Unbalanced(primary/ Balanced
transmissionof up to sevenframesbefore an acknowl- secondary) (peerto peer)
edgeis requiredback to the transmitter. The limitation Modulo8 (no extensions MOdUiO 128 (Up to 127
of sevenframes is necemarybecausethe ReceiveCount
in the control fieldis limitedto three binary digits.This allowed,up to 7 out- outstendingframes
means that if an eighth tmmmisaion occurred this standingframesbefore beforeacknowledge
would cause the next ReceiveCount to repeat the tirst acknowledgeis required) isrequired)
count that still is waiting for an acknowledge.This 8-bitaddressingonly Extendedaddressing
woulddefeat the purposeof the acknowledgement.The Bytealigneddata VSrieblesize of data
Proceasing and general maintenance of the sequence
count must be done by the user software. The Hard- The C152does not support HDLC implementationre-
ware BasedAcknowledgeoptionthat is providedin the quiringdata alignmentother than byte alignment.The
C152is not compatiblewith standard SDLCprotocol. user willtind that many of the protocolparametersare
programmablein the C152 which allows easy imple-
mentationof proprietary or standard HDLC network.
3.3.8 PRIMARY/SECONDARY STATIONS User sotlware needs to implement the control field
All SDLC networksare basedupon a pritnsry/secmd-
functions.
ary station relationship.Therecan be only one primary
station in a networkand all the other stations are con- 3.3.10 USING A PREAMBLE IN SDLC
sidered wxdat-y. All cormmmiestionis between the
primary and secondary station. Secondary station to Whentransmittinga preamblein SDLCmode,the user
secondary station direct communicationis prohibited. should be aware that the pattern of 10101010. . . is
If there is a needfor secondaryto secondarycomrmmi- output. NRZI encodingis used in SDLCwherethe in-
cation, the user softwarewill have to make allowances ternal baud rate generator is the clocksourw and this
for the master to act as an intermediary. Secondary means that a transition will oear everytwo bit time+
stations are atlowestuse of the seriatline onlywhenthe whena Ois transmitted. This compareswith some oth-
master permits them. Thisis doneby the master polling er SDLC devices,most of which transmit the pattern
the secondary stations to see if they have a need to OOMKOOO . . . which will cause a transition every bit
accessthe serial line. This shouldprevent anycollisions time. Our past experiencehas ahownthat the C152pre-
from oecurnng, providedeachsecondarystation has its ambledoesnot cause a problemwithmost other devic-
own unique address. This arrangement also partially es. This is becausethe preambleis used only to define
determm ‘ ea the types of networks supported. Normal the relative bit time boundaries within some variation
SDLC networks consist of point-to-point,multidrop, allowedby the receivingstation, and the C152pream-
or ring cotttigurationsand the C152 supports all of ble fulfillsthis function. The C152dces not have any
these. However,some SDLCproceasors support an au- problemswith receivinga preambleconsistingof all 0s.
tomatic one bit delayat eachnodethat is not supported One note of caution however.If idle fill flags are used
by the C152. In a “Loop Mode” configuration,is is in conjunctionwith a preamble,the addressesCO(OO)H
neeessmythat the transmissionbe delayedfrom the re- and 55(55)Hshouldnot be assignedto any C152as the
ception of the frames from the upstream station before preamblefollowingthe idle fill flagswillbe interpreted
as art address

7-33
i~. 83C152 HARDWARE DESCRIPTION

3.4 UserDefinedProtocols 3.5 Usingthe GSC

The explanationon the implementationof user defined
protocols would go beyond the scope of this manual, 3.5.1 LINEDISCIPLINE
but examining Table 3.1 should givethe reader a ecm- Line disciplineis how the managementof the transfer
solidatedlist of most of the possibilities.In this manual, of data over the physical medium is controlled. Two
any deviationfrom the documents that coverthe imple- typesof line diaeiplinewill be discussedin this seetion:
mentationof CSMA/CD or SDLCare considereduser full duplexand half duplex.
definedprotocols.Examplesof this wouldbe the use of
SDLC with the 32-bit CRC selected or CSMA/CD
with hardwarebreed acknowledge.

Point-to-Point Network

c 270427-21

Multi-Drop Network

11’ PRIMARY

I I 1
➤

SECONDARY SECONDARY SECONDARY

I I
270427-22

Ring Network

SECONDARY
I SECONDARY

Figure 3.10. SDLC Networks

7-34
i~. 83C152 HARDWARE DESCRIPTION

Full duplexis the simultaneoustransmissionand recep expansionplans become a mute issue. However,it is
tion of data. Full duplex usea anywherefrom two to stronglysuggestedthat there alwaysbe someallowance
four wirea.At least one wire is neededfor transmission for future modifications.
and one wire for reception. Usuallythere will also be a
ground reference on each signal if the distance from Someof the general areas that will impact the overall
station to station is relatively long. Full-duplexopera- scheme on how to incorporate future changes to the
tion in the C152requires that both the receiveand the systemare:
transmit portion of the GSC are timctioningat the
same time. Sinceboth the transmitter and receiver are 1) Cmummicationof the change to all the stations or
operating, two CRC generators are also needed. The the primary station.
C152handles this problem by havingone 32-bit CRC
generator and one id-bit CRC generator. When sup 2) Maximumdistancefor communication.This will af-
portingfull-duplexoperation,the 32-bitCRCgenerator fect the drivers used and the slot time.
is modifiedto work as a Id-bit CRC generator.When-
everthe 16-bitCRC is selected,the GSC automatically 3) More stations may be on the line at one time. This
entersthe full duplex mode. Half duplexwith a 16-bit may impactthe interframespaceor the collisionresolu-
CRC is discussedin the followingparagraph. tion used.
Half duplexis the alternate transmissionand reception 4) If using CSMA/CD without deterrninistic resolu-
of data over a single common wire. Only one or two tion, any increasein network size will have a negative
wires are needed in half-duplexsystems.One wire is impact on the averagethroughput of the network and
neededfor the signaland if the distanceto be coveredis lower the efficiency.The user will have to give careful
longthere will also be a wire for the groundreference. considerationwhen deciding how large a system can
In halfduplex mode, only the receiver or transmitter ultimatelybe and still maintain adequate performance.
can operateat one time. When the receiveror transmit-
ter operatesis determinedby user software,but typical-
ly the receiverwill alwaysbe enabledunlessthe GSCis 3.5.3 DMA SERVICING OF GSC CHANNELS
transmitting.When using the C152in half-duplexand There are two sourcesthat can be used to control the
the receiveris connectedto the transmitter it is possible GSC.The first is CPU control and the secondis DMA
that a station will receive its’ own tmmmission. This control.
can occur if a broadcast address is senk the address
mask register(s) are filled with all 1s, or the address CPU control is used when user software takes care of
being sent matches the sending stations address the tasks such as: loadingthe TFIPO, readingthe RFI-
through the use of the address maskingregisters. The FO, checkingthe status tla~ and general tracking of
receivermust be disabledby the user whiletransmitting the transmissionprccess. As the number of tasks grow
if any of these caditions will occur, unless the user and higher data transfer ratea are used, the overhead
wants a station to receive its own transmission.The requiredby the CPU becomrsthe dominant consump-
receiveris disabledby clearingGREN (and GAREN if tion of time. Eventually,a point is reached where the
used). Halfduplex operation in the C152is supported CPU is spending 100% of its time respondingto the
with either 16-bitor 32-bit CRCS.Whenevera 32-bit needs of the GSC.An alternative is to have the DMA
CRC is selected,only halfduplex operationcan be sup channelscontrol the GSC.
portedby the GSC. It is possibleto simulatefullduplex
opmtion with a 32-bit CRC, but this would require A detailedexplanationon the generaluse of the DMA
that the CRC be performed with software.Calculating channels is coveredin Section 4. In this section only
the CRC with the CPU wouldgreatly reduce the data those detailsrequiredfor the use of the DMA channels
rates that could be used with the GSC.Whenevera 16- with the GSC will be covered.
bit CRC is selected, full-duplex operation is automati-
cally chosenand the GSC must be remntiguredif half- The DMA channelscan be configuredby user software
duplexoperation is preferred.
so that the GSC data transfers are serviced by the
DMA controller. Sincethere are two DMA channels,
3.5.2 PLANNING FOR NETWORK CHANGES onechannelcan be usedto seMce the receiver,and one
AND EXPANSIONS channelcan be usedto servicethe transmitter. In using
the DMA channels,the CPU is relievedof much of the
A complete explanation on how to plan for network time requiredto do the basic servicingof the GSCbufT-
expansionwill not be covered in this manual as there ers. The typs of servicingthat the DMA channelscan
are far too many possibilitiesthat would need to be provide are: loadingof the transmit FIFO, removing
discussed.But there are several areas that will have data tlorn the receive FIFO, notifk.ationof the CPU
major impact when allowingfor changesin the system. when the tmnsnum “ ion or receptionhas ended, and re-
In caseswherethere will neverbe any changesallowed, sponse to certain error conditions. When using the

7-35
i~. 83C152 HARDWARE DESCRIPTION

DMA channels the source or destination of the data that will be receivq up to 64K. If not usingthe Done
intended for serial transmission can be internal data flag, then GSCservicingwouldbe drivenby the receive
memory,externaldata memory,or any of the SFRS. Done (RDN) flag and/or interrupt. RDN is set when
the EOF is detected.Whenusingthe RDN tlag, RFNE
The onlytasks requiredafter initializationof the DMA ahould also be checkedto insure that all the data has
and GSC registers are enabling the proper interrupts been emptiedout of the receive FIFO.
and informingthe DMA controllerwhento start. After
the DMA channelsare started affthat is requiredof the The byte count registeris used for all transmissionsand
CPU is to respondto error conditionsor wait until the this means that all packetsgoingout will have to be of
end of transmission. the same length or the length of the packet to be sent
willhave to be knownprior to the start of transmission.
Initializationof the DMA channelsrequires settingup When using the DMA channels to seMce the GSC
the control, source, and destination address registers. transmitter, there is no practical way to disable the
On the DMA channel servicingthe receiver, the con- Done flag. This is because the transmit done fig
trol registerneedsto be loadedas folfows:DCONn.2= (TDN) is set whenthe transmit FIFO is emptyand the
O,this sets the transfer modeso that responseis to GSC last messagebit has been transmitted. But, when using
interrupts and put the DMA control in alternate cycle the DMA channel to service the tranann‘tier, loads to
modq DCONn.3 = 1, this enablesthe demandmode; the TFIFO continue to occur until the byte count
DCONn.4 = O, this clears the automatic increment reaches O.This makes it impossibleto use TDN as a
optionfor the sourceaddres$ and DCONn.5 = 1,this flag to stop the DMA transfers to TFIFO. It is possible
detbes the sourceas SFR.The DMA channelservicing to examine some other registers or conditions,such as
the receiver also needs its source address register to the current byte count, to deterrmn“ e when to stop the
contain the addreas of RFIFO (SARHN = XXII, DMA transfersto TFIFO, but this is not recommended
SARLN = OF4H).On the DMA channelservicingthe as a way to seMce the DMA and GSC whentransmit-
transmitter, the control register needs to be loaded as ting becausefrequentreadingof the DMA registerswill
follows:DCONn.2 = O;DCONn.3 = 1;DCONn.6= cause the effectiveDMA transfer rate to slow down.
O, this clears the automatic increment option for the
destinationaddress; and DCONn.7 = 1, this sets the When using the DMA chann~ ini-tion of the
destination as SFR. The DMA channel serving the GSC wouldbe exactfythe same as normal exceptthat
transmitter also requirea that its destination address TSTAT.O= 1 (DMA), this informs the GSC that the
register contains the address of TFIFO (DARHN = DMA channelsare goingto be used to servicethe GSC.
XXI-I, DARLN = 85H). Assuming that DCONO Although only TSTATis written to, betb the receiver
would be servingthe receiver and DCON1 the trans- and transmitter use this same DMA bit.
mitter, DCONOwould be loaded with XX101OXOB
and DCON1 wouldbe loaded with 10XX1OXOB. The The interrupts EGSTE (IEN1.5), GSC transmit error;
contents of SARHOand DARH1 do not have any im- EGSTV (IEN1.3), GSC transmit valid; EGSRE
pact whenusinginternal SFRSas the sourceor destina- (IENI.1), GSC receive erro~ and EGSRV (IEN1.0),
tion. GSC receivevalid;needto be enabled.The DMA inter-
rupts are normally not used when servicingthe GSC
Whenusingthe DMA channelsto seMce the GSC,the with the DMA channels.To ensure that the DMA in-
byte count registerswill also need to be initialized. terrupts are not reapondedto is a function of the user
sotlware and shoufd be checked by the software to
The Done flag for the DMA channel servicingthe re- make sure they are not enabled.Priority for these inter-
ceiver should be used if fixed packet lengths only are rupts can also be set at this time. Whether to w high
beingtransmittedor to insure that memoryis not over- or low priority needs to be decidedby the user. When
written by long receiveddata packets. Ovenvritingof respondingto the GSC interrupts, if a buffer is being
data can occur when using a smaller buffer than the used to store the GSCinformation,then the DMA reg-
packet size. In these cases the servicingof the DMA isters used for the bufferwill probablyneed updating.
and/or GSC wouldbe in responseto the DMA Done
flag when the byte count reaches zero. After this initialization,all that needs to be done when
the GSC is actuaffygoingto be used is: load the byte
In some cases the bufk size is not the limitingfactor count, set-up the source addreasesfor the DMA chan-
and the packet lengthswill be unknown.In these cases nel servicingthe transmitter, set-up the destinationad-
it would be desirableto eliminate the functionof the dresses for the DMA channel servicing the receiver,
Done tlag. To effectivelydisable the Done tlag for the and start the DMA transfer. The GSC enable bits
DMA channel servicingthe receiver, the byte count should be set iirst and then the GO bits for the DMA.
should be set to some number larger than any packet This initiates the data transfem.

7-36
intel. 83C152 HARDWARE DESCRIPTION

This simplifiesthe maintenance of the GSC and can Initialization of the system can be broken down into
make the implementation of an external buffer for several steps. First, are the assumptionsof each net-
packetizedinformationautomatic. work station.

An externalbuffercan be used as the sourceof data for The tirst assumptionis that the type of data encoding
transmission,or the destinationof data from the receiv- to be used is prcdetermined for the system and that
er. In this arrangement, the messagesize is limitedto each station willadhereto the samebasicrules detining
the W size or 64K, whicheveris smaller. By using that encoding.The secondassumptionis that the basic
an external butTer,the data carsbe aweased by otha protocol and line discipline is predetermined and
deviceswhich may want accessto the aerial data. The known.This means that all stations are using CSMA/
amount of time required for the external data moves CD or SDLC or whatever, and that all stations are
will also decrease. Under CPU contro~ a “MOVX” either Ml or half duplez. The third assumptionis that
cmmnandwouldtake 24 oscillatorperiodsto complete. the baud rate is preset for the wholesystem. Although
Under DMA control,externalto internal, or internalto the baud rate could probablybe determined by the mi-
external, data movestake only 12oscillatorperiods. croprocessorjust by monitoringthe link,it will make it
much simpler if the baud rate is knownin advance.
3.5.4 BAUD RATE One of the ftrst things that will be requiredduring sys-
The GSC baud rate is determinedby the contentsofthe
tem initializationis the assignmentof uniqueaddresses
SFR, BAUD, or the external clock. The formulaused for each station. In a two-stationonlyenvironmentthis
to determine the baud rate when using the internal is not necessaryand can be ignored.However,keep in
clock is: mind, that all systems should be constructed for easy
future expansions.‘l%erefo%evenin onlya two station
(fosc)/((BAUD+ 1)”8)
system, addresses should be assigned.There are three
basic ways in which addresses can be assigned. The
For example if a 12 MHz oscillator is used the baud tirat, and most common is preassignedaddresaeathat
rate can vary from: are loaded into the station by the user. This could be
done with a DIP-switch,through a keybcard.The sec-
12,000,000/((0+
1)”8)= 1.5 MBPS ond method of assigningaddressesis to randomly as-
sign an address and then check for its uniqueness
to: throughout the system, and the third method is to
make an inquiry to the systemfor the assignmentof a
12,000,000/((255 +1)”8) = 5.859 KBPS uniqueaddress.Oncethe methodof addreaaassignment
is deterrmn
“ ed, the method should become part of the
There are certain requirementsthat the external clcck specificationsfor the systemto whichall additionawill
will need to meet. Theae requirementsare specifkd in have to adhere. l%is, then, is the final assumption.
the data sheet. For a descriptionof the use of the GSC
with external clock please read Section3.5.11. The negotiation process may not be clear for some
readers. The followingtwo procedure are given as a
guidelinefor dynamicaddress assignment.
3.5.5 INITIALIZATION
In the fimt procedure,a station assumesa random ad-
Initializationcan be broken downinto two major com- dress and then checksfor its uniquenessthroughout the
ponents, 1) initialization of the componentso that its system. As a station is inidalized into the system it
serial port is capableof proper comnmnication;and 2) sends out a message containing its assumed addreaa.
initializationof the systemor a station so that intelligi- The format of the message should be such that any
ble communicationcan take place. station decodingthe address recognizesit as a request
for initialization. If that address is shady used, the
Most of the initializationof the componenthas already receivingstation returns a mssaage,with its own ad-
been discussedin the previoussections.Thoseitemsnot dress stating that the addressin questionis already tak-
coveredare the parameters required for the component en. The initiahzingstation then picks another address.
to effectively communicate with other components. When the initiahzing station sends its inquiry for the
These typea of issuesare commonto both systemand address check, a timer is also started If the timer ex-
componentinitializationand will be coveredin the fol- pires before the inquiry is respondedto, then that sta-
lowingtext. tion assumesthe address chosenis okay.

7-37
i~o 83C152 HARDWARE DESCRIPTION

In the secondprocedure,an initiahzingstation asks for In Raw Receive, the transmitter should be externally
an address assignmentfrom the system. This requires connectedto the receiver. To do this a port pin should
that some station on the link take care of the task of be usedto enablean external deviceto connect the two
maintaininga record of whichaddressesare used. This pinstogether.In Raw Receivemodethe receiveracts as
station will be called station-1. When the initialing normal except that all bytes followingthe BGF are
station, called station-2,gets on the link, it sends out a londedinto the receiveFIFO, includingthe CRC. Also
messagewith a broadcast address. The format of the address recognition is not active but needs to be per-
messageshould be such that all other stations on the formedin software.If SDLCis selectedas the protocol,
link recognizeit as a request for address assignment. zero-bit deletion is still enabled. The transmitter still
Part of the measagefrom station-2is a random number operates asnormal and in this modemost of the trans-
generated by the station requestingthe addreas. Sta- mitter functionsand an externaltransca“Vercan be teat-
tion-2then examinesall receivedmessagrafor this ran- ed. This is also the only waythat the CRC can be read
domnumber.The randomnumbercouldbe the addreas by the CPU, but the CRC error bit will not be set.
of the receivedmessageor couldbe withinthe informat-
ion section of a broadcast frame. All the stations, ex-
cept station-1, on the link should ignore the initializa- 3.5.7 EXTERNAL DRIVER INTERFACE
tion request.Station-1,uponreceivingthe initialization A signalis providedfrom the C152to enable transtnit-
request, assigns an addreasand returns it to station-2. ter drivers for the serial link. This is provided for sys-
Station-1willbe requiredto formatthe messagein such tems that require more than what the GSC ports are
a manner so that all stations on the link recogniseit as capableof delivering.The voltageand currents that the
a responseto initialization.This meansthat all stations GSCis capableof providingare the samelevelsas those
exceptstation-2ignorethe return message. fornonnal port operation.The signalusedto enablethe
externaldriversis ~. No similarsignalis neededfor
3.5.6 TEST MODES the receiver.
There are two test modesassociatedwith the GSC that ~ is active one bit time &fore transmissionbegins.
are made available to the user. The test modes are In C3MA/CD ~ remains active for two bit times
named Raw Receive and Raw Transmit. The teat after the CRC is transxm‘tted. In SDLC~ remains
modes are selected by the proper setting of the two activeuntil the last bit of the EOF is transmitted.
mode bits in GMOD (MO = GMOD.5, Ml =
GMOD.6). If MI,MO = 0,1 th.m Raw Transmit is se-
lected. If M1,MO= 1,0then Raw Receiveis enabled. 3.5.8 JITTER(RECEIVE)
The 32-bit CRC cannot be used in any of the teat Datajitter is the differencebetweenthe actual transmitt-
modes,or else CRC errors will occur. ed waveform and the exact calculated value(s). In
NRZI, data jitter wouldbe howmuchthe actual wave-
In Raw Transmit,the transmit output is internallycon- formexceedsor falls short of onecalculatedbit time. A
nected to the Receiver input. This is intended to be bit time equals I/baud rate. If usingManchesterencod-
used as a local loopback test mode, so that all data ing, there can be two transitionsduringone bit time as
written to the transmitter will be returned by the rc- shownin Figure 3.11. This causesa seumd parameter
ceiv~. -W Transmit m &O be used to transmit user to be consideredwhen tryingto figureout the cctmplete
&ta. If Raw Transmit is used in this way the data is &ta jitter amount. This other parameteris the half-bit
emitted with no preamble,flag, address, CRC, and no jitter. The hsdf-bitjitter is comprisedof the differencein
bit insertion. The data is still encoded with whatever time that the half-bit transition actuallyoccurs and the
format is selected,Manchesterwith CSMA/CD, NRZI calcrdatedvalue.Jitter is importantbecauseif the tran-
with SDLCor as NRZ if externalclocksare used. The sition occurs too soon it is considerednoise, and if the
receiverstill operates as normal and in this mode most transition occurs too late, then either the bit is missed
of the receivefunctionscartbe tested. or a collisionis assumed.

7-36
i@. 83C152 HARDWARE DESCRIPTION

LOGICAL I , I ~ I , I , I o I o I
VALUE :

I ,l~rJjL --lj
MANCHESTER :
ENCODING I ,

I ,
J
--- 1. . . ‘
-..
---- -.. .
---
--- -.. .
I
,--
-,
— ‘“l “ BIT TIME “l”’ BITTIME—

RECEIVEDI ; : ;
DATAI , , ,

,1 * ,
, ,1 , , t

, I
— 0’1“0BIT TIME “O” BIT nME —
.,, ,
,* , ,*, I ,*, ,

nnnnnnM nnr nnrl~

1,
,
,
, ‘1 ‘
i
RECEIVED
I ; ; ; ,1
DATAI , , , ,*
11
.-. ------
,1 ,
270427-24

Figure 3.11. Jitter

3.5.9 Transmit Waveforms In CSMA/CD the lmarnble consists of akematin~ 1s

and 0s. Ccmaequm-tly,the preamble looks like-the
The GSC is capable of three types of data encoding, waveformin Figure 3.13Aand 3.13B.
Manchester, NRZI, and NRZ. Figure 3.12 shows ex-
~Ples of a three types of data encoding.
3.5.11 External Clocking

3.5.10 Receiver Clock Racovery To selectexternal clocking,the user is given three

choices.External clockingcan be used with the trans-
The receiver is always monitored at eight times the mitter, with the receiver,or with both. To selectexter-
baud rate frequency,except wherean external clock is nal clocking for the transmitter, XTCLK (GMOD.7)
used.When usingan external clock the receiver is load- has to be set to a 1. To select external clockingfor the
ed during the clock cycle. receiver,XRCLK (PCON.3)has to be set to a 1. Set-
ting both bits to 1 forces external clockingfor the re-
In CSMA/CD mode the receiver synchronizesto the ceiver and transmitter. The minimum frequency the
transmitted data during the preamble.If a pulse is de- GSCcan be externallyclockedat is OHz (D.C.).
tected as being too short it is assumedto be noise or a
collision.If a pulse is too long it is assumed to be a The external transmit clock is appliedto pin 4 (TXC),
collisionor an idle condition. P1.3. The external reseive clock is applied to pin 5
(RXC), P1.4. To enablethe external clockfunctionon
In SDLC the synchronizationtakes place during the the port pin, that pin has to be set to a 1 in the appro-
BOF flag. In addition,pulses lessthan four sample pe- priate SFR, P1.
riods are ignored,and assumedto be noise.This sets a
lowerlimit on the pulse size of receivedzeros.

7-39
inf& 83C152 HARDWARE DESCRIPTION

, , ,
, #
, , ,
‘- T!:E ‘;
, , ,

, ,
# I ,

, ,
NRZI t
,
~
, ,
t
,
MANCHESTER

, 0
,

1:
, , ,

270427-25

Figure 3.12. Transmit Waveforms

Wheneverthe external clock optionis used, the format (AMSKO,AMSK1)in the C152.These function with
of the transmitted and received data is restricted to the GSCreceiveronly.The transmitted addressis treat-
NRZ encodingand the protocolis restricted to SDLC. ed likeany other data The addressis transmittedunder
With external clock, the bit stuftlng/stripping is still software control by placing the address byte(s) at the
activewith SDLC protocoL proper location(usually first) in the sequenceof bytes
to be output in the outgoingpacket.
3.5.12 Determining Reoeiver Errore The C152can have up to four different8-bitaddresses
It is possiblethat several receivererror bits will be set
or two different Id-bit addresses assignedto each sta-
in responseto a single cause. The multiple errors that tion. Whenusing16-bitaddressing,ADRO:ADR1form
can occur are: one address and ADR2:ADR3 form the second ad-
dress. If the receiveris enabled,it looksfor a matching
AE and CRCE IllSyboth be set when an alignment address after everyBOF ilag is detected.As the data is
error occurs due to a bad CRC caused by the rnis- received, if the 8th (or 16th) bit does not match the
rdignedframe. address recognitioncircui~, the rest of the frame is
ignoredand the search continuesfor anothertlag. If the
RCABT, AE, and CRCE may be set when an abort address does match the addreas recognitioncircuitry,
occurs. the address and all subsequentdata is passed into the
receive FIFO until the EOF flag or an error occurs.
OVR,AE, and CRCE may be set when a overrun oc- The address is not stripped and is also passed to
curs. RFIFO.
The address maskingregia~ AMSKOand AMSK1,
In order to determine the correct cause of the error a work in conjunctionwith ADROand ADR1 respective-
specificorder should be followedwhen examiningthe ly to identify“don’t care” bits. A 1 in any poaitionin
error bits. This order is: the AMSKn register makes the respective bit in the
ADRn registerirrelevant.Thesecombinationscan then
1) OVR be used for form group addresses,If the maskingregis-
2) RCBAT ters are filledwith all 1s,the C152willreceiveall pack-
3) AE ets, which is called the promiscuousmode. If id-bit
4) CRCE addressingis ~ AMSKO:AMSK1form one id-bit
address mask.
3.5.13 Addressing

There are four 8-bit address registers (ADRO,ADR1,

ADR2, ADR3) and two 8-bit address mask registers

7-40
i~o 83C152 HARDWARE DESCRIPTION

CSMA/CD Clook Recovery

4,, , .,,,!,,,,,,,,
: 1 :0:1 :0:1 : o : 1 : 1 : 1 : o : o : o : 1 : 1 : 0: 1 :
(, ,8,,,,,,,,,,,,,
IOEAL
WAVEFORM
,,, ,,, ,,, ,,, ,,, (,
,,, ,,, ,,, ,,, ,,, ,,
8XSAMPLING
RATE~
,,, ,,, ,,, ,,, ,,, ,,
,,, ,,, ,,, !,,,,,,,
ACTUAL
WAVEFORM
,, !,,,,,,,,,,,,,,
,,, ,,, ,,, ,,, ,, (,,

,,, ,,, ,,, ,,, ,,, ,,

,,, ,,, ,,, ,,, ,,, ,,
!,!!, ,,, ,,, ,4, ,,$
270427-26

Figure 3.13A. Clock Recovery

SDLC ClockReoovery
,,, ,4,,,,,,,,,,,,
:o ; 1 ; 1 ; 1 ; 1 : 1 ; 1 ; o ; o ; o : 1 : 1 ; o ; 1 ; 0; 0;
,,, ,4,,,,,,,,,,,,

IDEAL WAVEFORM
,,,
,,,
,,0,
1,,
,,,
,,,
,,,
,,

,,,
!,,,,,,,,,,
,,,
,,
,,
,,,
[m; ,,

8X SAMPLING RATE ~
,,, ,,, ,,, ,, !,,,,,
,,, ,,, ,,, ,,, ,,, ,,
,,, ,,,
ACTUAL WAVEFORM ,,, ,,,
,,, ,,, ,,, ,(, ,,, ,,
,,, ,,, ,,, ,,, ,,, ,,
RECOVEREDBr7
STREAM CLOCK n n n n n n Iln n
,,, ,,, ,,, ,,, ,,, ,!
,,, ,,, ,,, ,,, ,,, ,,
,,, ,,, ,,, ,,, ,,, ,,
270427-27

Figure 3.13B. Clock Recovery

intd. 83C152 HARDWARE DESCRIPTION

3.6 GSC Oparation If the receiver detects a collisionduring reception in

C3MA/CD mode and if any bytes have been loaded
3.6.1 Determining Line Discipline into the rrseive FIFO, the RCABTtlag is set. The GSC
hardware then halts reception and resets GREN. The
In norntai operationthe GSC uses full or half duplex user softwareneedsto falterany collisionfragment data
operation.When using a 32-bitCRC (GMOD.3 = 1), whichmay havebeenreceived.If the collisionoccurred
option can onlYbe hrdf duplex. If using a 16-bit prior to the data beingioadedinto RFIFO the CPU is
CRC (GMOD.3 = O), fufl duplex is selected by de- not notifiedand the receiveris left enabled.At the end
fault. When using a Id-bit CRC the receiver can be of a receptionthe RDN bit is set and GREN is cleared.
turned offwhiletransmitting (RSTAT.1 = O),and the In HABEN mode this causes an acknowledgementto
transmitter can be turned off during reception be transmitted if the frame did not have a broadcast or
(TSTAT.1 = O).This simulateshalf-duplexoperation multi-east address. The user software can enable the
when usinga id-bit CRC. interrupt for RDN to determinewhen a frame is com-
pleted.
Normally,HDLC uses a Id-bit CRC, so half duplexis
deterrnined by turning off the receiver or transmitter. In DMA mode the interrupts are generated by the in-
This is so that the receiver will not detect its own ad- ternal “transmit/receive done” (TDN,RDN) condi-
dress as transmissiontakes place. This also needsto be tions. When the CPU responds to TDN or RDN,
done whenusingCSMA/CD with a 16-bitCRC for the checks are performedto am if the tranamr“t underrun
same reason. error has occurred. The underrun condition is only
checkedwhen usingthe DMA channels.
3.6.2 CPWDMA CONTROL OF THE GSC
Upon power up the CPU mode is initkdized.General
The dab for transmissionor receptioncan be handled DMA control is cmwredin Section4.0. DMA control
by either the CPU (T3TAT.O= O)or DMA controller of the GSC is coveredin Section3.5.4.If DMA is to ix
(T3TAT.O= 1).This allowsthe user two sets of flags used foraervingthe GSC,it must be cofilgured into the
to control the FIFO. Associated with these flags are aerial channel demand mode and the DMA bit in
interrupts, whichmay be enabledby the user software. TSTAT has to be set.
Either oneor bdh sets of flagsmaybe usedat the same
time.
3.6.3 COLLISIONS AND BACKOFF
In CPU controimodethe flags(RFNE,TFN~ are gen- The actions that are taken by the GSC if a collision
erated by the wndition of the receive or transmit FI- occurs while transmitting depend on where the colli-
FO’S.After loading a byte into the transmit FIFO, sion occurs. If a collisionoccurs in CSMA/CD mode
there is a one machine cycle latency until the TFNF followingthe preambleand BOFflag,the TCDT fig is
flag is updated. Because of this latency, the status of set and the transmr“thardware completesa jam. When
TFNF should not be checked immediatelyfollowing this type of collisionOccurs,there will be no automatic
the instructionto load the transmit FIFO. If usingthe retry at transmiaaion. After thejam, control is returned
interrupts to service the transmit FIFO,the one ma- to the CPU and user softwaremust then initiate what-
chine cycieof latency must be consideredif the TFNF ever actions are necemaryfor a proper recovery. The
tlag is checkedprior to leavingthe subroutine. posaibditythat data might have been loaded into or
from the GSC deservesspecial consideration. If these
Whenusingthe CPU for control, transmissionnormal- fragments of a messagehave been passed on to other
Iy is initiated
by setting the TEN bit (TSTAT.1)and devi~ user softwaremay haveto performsomeextem-
themwritingto TFIFO. TEN must be set beforeload- sive error handling or notification. Before starting a
ing the transmit FIFO, as settingTEN clearsthe trans- new message, the tranmu “t and receive FIFOSwill need
mit FIFO. TCDCNT should also be checked by user to be cleared. If DMA servicingis beingused the point-
aotlware and cleared if a collisionoccurred on a prior ers must also be reinitiabd. It shouldbe noted that a
transmission. collisionshouldneveroecur after the BOF flagin a well
designedsystem, since the system slot time will likely
To enablethe receiver,GREN (RSTAT.1)is set. After be leas than the preamble length. The occurrence of
GREN is set, the GSC beginsto look for a valid BOF. such a situation is normallydue to a station on the link
After detecting a valid BOF the GSC attempts to that is not adheringto proper CSMA/CD protocol or
match the receivedaddress byte(s) against the address is not usingthe sametimingsas the rest of the network.
match registers. When a match occurs the frame is
loaded into the GSC. Due to the CRC strip hardware, A cdiaion occurringduringthe preambleor BOF flag
there is a 40 or 24 bit time delay followingthe BOF is the normal type of collisionthat is expected.When
until the first &ta byte is loadedinto RFIFO if the 32 this type of collision occurs the GSC automatically
or 16bit CRCis chosen.If the end of frame is detected
handles the retransmission attempts for as many as
beforedata is loadedinto the receiveFIFO, the receiver eight tries. If on the eighth attempt a collisionoccurs,
ignoresthat frame.
7-42
 83C152 HARDWARE DESCRIPTION

the transmitter is disabled,althoughthe jam and back- are more than 256 stations involved in the collision
off are performed. If enabled,the CPU is then inter- there would be no resolutionsince at least two of the
rupted. The user softwareshouldthen determine what stations will always have the same backoffinterval ae-
action to take. The possibilitiesrange tkomjust report- Iected.
ing the error and abortingtransmissionto reinidalizing
the serial channelregistersand attempt rctransxm “ssion. AUthe stations monitorthe link as long as that station
is active, even if not attemptingto transmit. This is to
If less than eight attemptsare desiredTCDCNT can be ensure that each station always defers the minimum
loaded with some value which will reduce the number amount of time beforeattemptinga transmissionand so
of collisionspossiblebefore TCDCNT overflows.The that addresses are recognized.However, the collision
valueloaded shouldconsistof all 1sas the least signifi- detect CircuitryO~teS Slightlydit%redy.
cant bits, e.g. 7, OFH,3FH. A solidblock of 1sis sug-
gestedbecauseTCDCNT is used as a mask when gen- In normal back-offmode a transmitting station always
erating the random slot number assignment. The monitors the link while transmitting. If a collision is
TCDCNT registeroperatesby shiftingthe contentsone detected one or more of the transmitting stations apply
bit position to the left as each collisionis detected. ~ the jam signal and all transnu“tting stations enter the
each shift occurs a 1 is loaded into the LSB. When back-off algorithm The receiving stations also con-
TCDCNT overtlows, GSC operation stops and the stantly monitor for a collisionbut do not take part in
CPU is notifiedby the setting of the TCDT bit which the resolution phase. This allows a station to try to
can tlag an interrupt. transmit in the middle of a resolution period. This in
turn may or may not causeanother collision.If the new
The amount of time that the GSChas beforeit must be station trying to transmit on the link doesso duringan
ready to retransmit after a collisionis determined by unused slot time then there willprobablynot be a colli-
the mode which is selected. The mode is determined sion. If trying to transmit duringa used slot time, then
MO(GMOD.5) and Ml (GMOD.6). If MO and Ml there will probably be a collision.The actions the re-
equal 0,0 (normal backo~ then the minimum pericd ceiver does take when detecting a collision is to just
before rctrammisaion will be either the interframe stop receiving data if data has not been loaded into
spaceor the backoffPerk@ whicheveris longer.If MO RFIFO or to stop reception, clear receiver enable
and Ml equal 1,1(alternatebacko~ then the minimum -N) and set the receiver abort flag (RCABT -
period before retransmission will be the intefikame RSTAT.6).
SP plus the backoffperiod Both of these m shown
in Figure 3.4. Alternate backoffmust be enabledif us- If determinestic resolutionis used, the transmittingsta-
ing determin”Kticresolution.If the GSC is not ready to tions go through pretty much the same proeea.sas in
retransmit by the time its assignedslot becomesavail- normal back-off, except that the slots are predeter-
able,the slot time is lost and the station must wait until mined. All the receiversgo through the back-offalgo-
the collisionresolutiontime period has passed. rithm and InSyOldytransmitduringtheir assignedS1OL

Instead of waitingfor the collisionresolution to pass,

the transmission could be aborted. The decision to 3.6.4 SUCCESSFULENDINGOF
abort is usuallydependenton the numberof stations on TRANSMISSIONS
ANDRECEPTIONS
the link and how many collisions have already oc- In both CSMA/CD and SDLCmodeajthe TDN bit is
curred. The number of collisionscan be obtained by set and TEN cleared at the end of a successfultrans-
examiningthe register,TCDCNT.The abort is normal- mission.The end of the tmmnusw‘on occurs when the
ly implementedby ckaring TEN. The new tranamia- TFIFO is empty and the last byte has beentransnu“tted.
sion begins by setting TEN and loading TFIFO. The In CiSMA/CDthe user shouldclear the TCDCNTreg-
minimumamountof time availableto initiate a retrans- ister after sucaasful transmission.
missionwouldbe one interframespace period after the
line is sensedas beingidle. At the end of a successfulreception,the RDN bit is set
and GREN is cleared. The end of reception occurs
As the numberof stationsapproach256the probability when the EOF flag is detectedby the GSC hardware.
of a successfultransmissiondecreaaearapidly. If there

7-43
i~o 83C152 HARDWARE DESCRIPTION

3.7 Register Descriptions The lengthincludesthe two bit BeginOf Frame (BOF)
tlag in CSMA/CDbut doeanot includethe SDLCflag.
ADR0,1,2,3 (95H, OA5H,OB5H,OC5H) - Address In SDLCmode,the BOF is an SDLCflag,otherwiseit
Match Registers 0,1,2,3- contains the address match is two conaecutiveones. Zero lengthis not compatible
valueawhichdetermineswhichdata willbe acceptedas in CSMA/CD mode. The user softwareis responsible
valid. In 8 bit addressingmode,a match with any of the for setting or clearing these bits.
four registerswilltrigger acceptance.In 16bit address-
ing modea match with ADRIADRO or ADR3:ADR2 GMOD.3(CT) - CRC Type-If set, 32bit AUTODIN-
will be accepted. Addressingmode is determm “edirr 11-32is used. If clear~ 16 bit CRC-CCITTis used.
GMOD (AL). The user software is responsiblefor setting or clearing
this tlag.
AMSKO,l(OD5H,OE5H)- Address Match Mask 0,1-
Identifies which bits in ADRO,l are “don’t care” bits. GMOD.4 (AL) - Address Lestgth- If set, 16 bit ad-
Writing a one to a bit in AMSKO,l masks out that dressingis used.If cleared, 8bit addressingis used. In 8
correspondingbit in ADDRO,l. bit mode a match with any of the 4 address registers
will be accepted (ADRO, ADR1, ADR2, ADR3).
BAUD (94H) - GSC Baud Rate Generator - Contains “Don’tCare” bits may be maskedin ADROand ADRI
the valueof the programmablebaud rate. The data rate with AMSKOand AMSK1. In 16bit mode, addreases
will equal (frequencyof the oscillator)/((BAUD + 1) are matched againat “ADR1:ADRO” or “ADR3:
x (8)). Writingto BAUDactuallystoreathe vahe in a ADR2”. Again, “Don’t Care” bits in ADRIA.DRO
reload register. The reload register contents are copied can be maskedin AMSK1:AMSKO.A receivedaddress
into the BAUD register whenthe Baud register deere- of all ones will alwaysbe recognizedin any mode. The
mentato OOH.ReadingBAUDyieldsthe current timer user softwareis responsiblefor settingor clearing this
value. A read during GSC operation will give a value tlag.
that may not be current becausethe timer mold decm
ment betweenthe time it is read by the CPU and by the GMOD.5,6~O,Ml) - Mode Select- Two test modes,
time the value is loadedinto its destination. = OPtiOtd “alternate backoff’ mode,or normal back.
off can be enabled with these two bits. The user aoft-
BKOFF (OC4H)- BaekoffTimer - The backofftimer is ware is responsiblefor settingor clearingthe mode bita.
an eightbit countdown timerwith a clockperiodequal
to one slot time. The backoff time is used in the Ml MO Mcde
CSMA/CD eollisiott resolution algorithm. The user o 0 Normal
softwaremay read the timer but the valuemaybe inval- o 1 RSWTransmit
id as the timer is clockedasynchronouslyto the CPU. 1 0 Raw Receive
Writing to OC4Hwill have no effeet. 1 1 Alternate Backoff

GMOD(84H) In raw receive mod%the receiveroperateaas normal

7 6543210 exeeptthat all the byte-sfollowingthe BOF are loaded
into the receiveFIFO, includingthe CRC. The trans-
XTCLK Ml MO AL CT PL1 PLO PR mitter operatesas normal.
Rgure 3.14. GMOD
In raw transmit mode the transmit output is internally
GMOD.O(PR) - Protocol-If set, SDLCprotocolswith connectedto the reeeiver input. The internal c4mnec-
NRZI encodingand SDLCflags are used. If cleared, timt is not at the acturd port pin, but inside the port
CSMA/CD link access with Manchester encoding is latch. All data transmitted is donewithouta preamble,
used. The user sotl,wareis responsiblefor setting or flag or zero bit insertion, and without appending a
Clearing this flag. CRC. The receiver operates as normal. Zero bit delet-
ion is performed.
GMOD.1,2(PLO,l)- Preamblelength
In alternate backoffmode the standardbackoffproeeas
PL1 PLOLENGTH (BITS) is modifiedso the the baekoffis delayeduntil the end of
000 the IFS. This should help to prevent collisions con-
018 stantly happeningbecausethe IFS timeis usuallylarger
1 0 32 than the slot time.
1164

7-44
i~e 83C152 HARDWARE DESCRIPTION

GMOD.7~CLK) - ExternalTransmit Clock- If set PCON (087H)

an external 1X clock is used for the transmitter. If 7654 3 210
cleared the internal baud rate generator provides the
transmit clock. The input clock is applied to P1.3 SMOD ARB REQ GAREN XRCLK GFIEN PD IDL
~~). The user software is responsible for setting or
clearing this flag. External receiveclock is enabled by PCON contains bits for power control, LSC control,
setting PCON.3. DMA control, and GSC control. The bits used for the
GSC are PCON.2, PCON.3, and PCON.4.
IFS (OA4H)- Interframe Spacing - Determm “ es the
number of bit times separating transmitted frames in PCON.2 (GFIEN) - GSC Flag Idle Enable - Setting
CSMA/CD and SDLC. A bit time is equal to l/baud GFIEN to a 1caused idle flagsto be generatedbetweem
rate. Only even interfkarnespace periodscan be used. transmitted frames in SDLC mode. SDLC idle tlags
The numberwritten into this registeris dividedby two consist of 01111110 tlags creating the sequence
and loadedin the moat significantsevenbits. Complete 01111110011111110 . .....011111110. A possibleside
interfkamespace is obtainedby countingthis seven bit effectof enablingGFIEN is that the maximum possible
number down to zero twice. A user software read of latency from writing to TFIFO until the first bit is
this registerwill givea vafuewherethe sevenmost sig- transmitted increased from approximately2 bit-times
nificantbits givesthe current count valueand the least to around 8 bit-times. GFIEN has no effect with
significantbit showsa one for the first countdown and CSMA/CD.
a zero for the secondcount. The valueread may not be
vafidas the timm is clockedin periodsnot necessarily PCON.3(XRCLK) - GSC ExternalReceiveClockEn-
associatedwith the CPU read of IFS. Loadingthis reg- able - Writinga 1 to XRCLK enablesan external clock
ister with zero results in 256bit times. to be applied to pin 5 (Port 1.4).The external clock is
used to determine when bits are loadedinto the receiv-
MYSLOT(OF5H)- Slot AddreasRegister er.
76543210
PCON.4(GAREN) - GSC AuxilimyRemiver Enable
DcJ DCR SA5 SA4 SA3 SA2 SA1 SAO Bit - This bit needsto be set to a 1 to enablethe recep-
I SAn = SLOT ADDRESS (BITS 5 – O) tion of back-to-back SDLC frames. A back-to-back
SDLC frame is when the EOF and BOF is shared te-
Figure 3.15. MYSLOT tweentwo sequentialframes intendedfor the same sta-
tion on the link. If GAREN containsa Othen the re-
MYSLOT.0,1, 2, 3, 4, 5- Slot Address- The six ad- ceiverwill be disabled upon receptionof the EOF and
dress bits choose1 of 64 slot addreases.Address63 has by the time user software re-enablesthe receiver the
the highest priority and address 1 has the lowest. A first bit(s) may have already passed,in the case of back-
value of zero wilf prevent a station from transmitting to-back frames Setting GAREN to a 1, prevents the
during the collisionresolutionperiod by waiting until receiver from being disabled by the EOF but GREN
all the possibleslot timea have efapsed.The user soft- wilfbe cleared and can be checkedby user softwareto
ware normallyinitializeathis address in the operating determinethat an EOF has beur received.GAREN has
software. no effectif the GSC is in CSMA/CD mode.
MYSLOT.6(DCR) - Deterministic CollisionResolu- PRBS (OE41-1) - Paeudo-RandomBinary Sequence -
tion Algorithm- When aeLthe alternate collisionreso- This register contains a pseudo-randomnumber to be
lution algorithmis selected.Retriggeringof the IFS on usedin the C3MA/CD backoffalgorithm.The number
reappearanceof the carrier is alsodisabled.When using is generated by using a feedbackshift register clocked
this feature Alternate BaekoffMode must be selected by the CPU phaseclocks. Writingatl onesto the PRBS
and several other registers must be initialized. User willfreezethe value at all ones.Writingany other value
softwaremust initialize TCDCNTwith the maximum to it will restart the PRBS generator.The PRBS is ini-
numba of slots that are most approptite for a particu- tialized to all zero’sduring RESET.A read of location
lar application.The PRBS register must be set to all OE4Hwill not necesard“y give the seed used in the
onea.Thisdisablesthe PRBSby freezingit’s eorttentsat baekoff algorithm because the PRBS counters are
OFFH. The backoff timer is used to count down the clockedby internal CPU phase clocks.This means the
numberofslotsbased on the slot timer valuesettingthe eontents of the PRBS may have been altered between
period of one slot. The user softwareis responsiblefor the time when the seed was generated and before a
setting or clearingthis flag. ~READ has been internally executed.
MYSLOT.7(DCJ) - D-C. Jam - Whenset selectaD.C.
type ~, when cl-, selectsA.C. type jam. The user
softwareis responsiblefor settingor clearing this flag.

7-45
 83C152 HARDWARE DESCRIPTION

RFIFO (OF4H)- Receive FIFO - RFIFO is a 3 byte RSTAT.6(RCABT)- ReceiverCollision/Abat Detect

bfier that is loaded each time the GSC receiver has a - If se~ indicatesthat a collisionwas detected afterdata
byte of data. Aaaociated with RFIFO is a pointer that is hadbeen loaded into the receiveFIFO in CSMA/CD
automaticallyupdated with each read of the FIFO. A mode.In SDLCmod%RCABTindicatesthat 7 consec-
read of RFIFO fetches the oldest data in the FIFO. utive ones were detected prior to the end tlag but after
data has been loaded into the receive FIFO. AE may
RSTAT(OE81-1)
- ReceiveStatusRegister also be set. The setting of this flag is controlledby the
7654321 0 GSC.
OR RCABTIAE CRCE RDN RFNE GREN HABEN RSTAT.7(OVR)- Overrun - If setj indicatesthat the
receiveFIFO was till and new shift register data was
Figure 3.16. RSTAT
written into it. AE and/or CRCE may also be set. The
setting of this tlag is controlled by the GSC and it is
RSTAT.O(HABEN) - Hardware BaaedAcknowledge cleared by user software.
Enable - If set, enables the hardware baaed acknowl-
edgefeature.The user softwareis responsiblefor setting SLOTTM(OBH)- SlotTime - Deterrnineathe lengthof
or clearingthis flag. the slot time used in CSMA/CD. A slot time equals
(SLOTTM)X (1 /baud rate). A read of SLOTTMwill
RSTAT.1(GREN) - ReceiverEnable- When set, the givethe value of the slot time timer but the valuemay
receiveris enabledto accept incomingframes.The user be invrdidas the timer is clockedasynchronouslyto the
must clear RFIFO with software before enabling the CPU. Loading SLOTTM with O results in 256 bit
receiver.RFIFO is cleared by readingthe contents of times.
RFIFO until RFNE = O.After eachread of RFIFO, it
takes one machine cycle for the status of RFNE to be TCDCNT(OD4H)- Transmit CollisionDetect Count-
uxti setting GREN also chars RDN, CRC~ AE, Containsthe numberof collisionsthat have occurred if
and RCABT.GREN is clearedby hardwareat the end probabilistic CSMA/CD is used. The user software
of a receptionor if any receiveerrors are detected. The must clear this registerbeforetransrm“ttinga newframe
user softwweis responsiblefor settingthis flag and the so that the GSC backoffhardware can accurately dia-
GSCor user softwarecan clear it. The status of GREN tinguiaha new frame from a retransmit attempt.
has no effecton whdm the receiverdetects a collision
in CSMA/CD mode as the receiverinput circuitry al- In determinktic backoff mode, TCDCNT is used to
ways monitom the receivepin. hold the maximumnumber of slots.
RSTAT.2(RFNE) - ReceiveFIFO Not Empty -If set, TFIFO (85H) - GSC Transmit FIFO - TFIFO is a 3
indicates that the receive FIFO containsdata. The re- byte buffer with an associatedpointer that is automati-
ceiveFIFO is a three byte bufferinto whichthe receive callyupdatedfor eachwrite by user software.Writinga
data is loaded. A CPU read of the FIFO retrieves the byte to TFIFO loads the data into the next available
oldeatdata and automaticallyupdatesthe FIFO point- locationin the transmit FIFO. SettingTEN clears the
ers. setting GREN to a one willclearthe receiveFIFO. transmit FIFO so the transmit FIFO should not be
The status of this tlag is controlledby the GSC. It is written to prior to setting TEN. If TEN is already set
cleared if user empties receiveFIFO. tranamkaionbeginsas soon as data is written to TFI-
FO.
RSTAT.3(RDN) - ReceiveDone -If set, indicates the
successfulcompletionof a receiveroperation. Will not TSTAT(OD8)- Transmit StatusRegister
be set if a CRC, alignment, abort, or FIFO overrun
error occurred. The status of this tlag is controlled by 7 6543210
the GSC. Im INOACKIURITCDTI TDNITFNFITEN IDMAI
RSTAT.4(CRCE) - CRC Error -If set, indicatesthat a Figure 3.17. TSTAT
properlyaIignedframe wasreceivedwith a mismatched
CRC. The status of this fig is controlledby the GSC. TSTAT.O(DMA) - DMA Select- If set, indicatesthat
DMA channelsare usedto servicethe GSCFIFO’sand
RSTAT.5 (AE) - Alignment Error - In CSMA/C!D GSC interrupts occur on TDN and RDN, and also en-
mode,AE is set if the receivershiftregister(an internal ables UR to becomeset. If cleared, indicateathat the
serial-to-parallelconverter) is not full and the CRC is GSC is operating in its normal mode and interrupts
bad whenan EOF is detected. In CSMA/CD the EOF occur on TFNF and RFNE. For more informationon
is a line idle condition (see LNI) for two bit times. If DMA servicingplease refer to the DMA section on
the CRC is correct while in CSMA/CD mode, AE is DMA aerial demandmode (4.2.2.3).The user software
not set and any mis-aligmnentis assumedto be caused is responsiblefor setting or clearing this flag.
by dribble bits as the line went idle. In SDLC mode,
AE is set if a non-byte-alignedflag is received.CRCE
may also be set. The setting of this tlag is controlledby
the GSC.
{46
i~. 83C152 HARDWARE DESCRIPTION

TSTAT.1(TEN) - Transmit Enable - When set causes 3.8 SerialBackplanevs. Network

TDN, UR, TCDT, and NOACK flag to be reset and Environment
the TFIFO cleared.The transmitter will clear TEN sf-
ter a successful transmission, a collision during the The C152GSCportis intended to fidfii the needs of
data, CRC or end tlag. The user softwareis responsible both serial backplaneenvironmentand the serial com-
for setting but the GSC or user softwaremay clear this municationnetworkenvironment.The serialbackplane
flag.If clearedduringa transmissionthe GSCtransmit is wheretypically,only procesaorto pmxaaor commu-
pin goesto a steadystate high level.This is the method nications take place within a self containedbox. The
usedto aendan abort character in SDLC.Also~ is communicationusually only encompassesthose items
forced to a high level.The end of transmissionoccurs which are necewary to accomplish the dedicated task
wheneverthe TFIFO is emptied. for the box.In thesetypes of applicationsthere may not
be a need for line drivers as the distance betweenthe
TSTAT.2 (TFNF) - Transmit FIFO not full - When transmitter and receiver is relatively short. The net-
set, indicates that new data may be written into the work environment;however,usuallyrequirestransmis-
transmit FIFO. The transmit FIFO is a three bytebuff- sion of &ta over large distances and requires drivers
er that loads the transmit shift register with data. The and/or repeaters to ensure the data is receivedon both
status of this flagis controlledby the GSC. ends.
TSTAT.3(TDN) - Transmit Done - When seL indi-
catesthe successfulcompletionof a frame transmission. 4.0 DMA Operation
If HABEN is set, TDN will not be set until the end of
the IFS followingthe transmitted measage,so that the The C152contains DMA (Direct MemoryAccessing)
acknowledgecan be checked. If an acknowledgeis ex- logicto performhigh speeddata transfers betweenany
pected and not roxived, TDN is not set. An acknowl- two of
edgeis not expectedfollowinga broadcastor multi-cast
packet.The status of this ilag is controlledby the GSC. Internal Data RAM
Internal SFRS
TSTAT.4(TCDT)- Transmit CollisionDetect -If seL ExternrdData RAM
indicatesthat the transmitter halted due to a collision.
It is set ifa collisionoccurs during the data or CRC or If externalRAM is involved,the Port 2 and Port O~
if there are morethan eight collisions.The status of this are used as the addreaa/data bus, and ~ and WR
tlag is controlledby the GSC. signalsare generatedas required.
TSTAT.5(U’R)- Underrun - If set, indicates that in Hardware is also implementedto generatea Hold Re-
DMA modethe last bit was shifted out of the transmit queat signal and await a Hold Acknowledgeresponse
register ~d that the DMA byte count did not equal before commencing a DMA that involves external
zero. When an underrunoccurs,the transmitterhalts RAM.
withoutsendingthe CRC or the end flag.The status of
this flag is controlledby the GSC. Alternatively,the Hold/Hold Acknowledgehardware
can be programmed to accept a Hold Request signal
TSTAT.6(NOACK)- No Acknowledge- If set, indi- from an externrddeviceand generate a Hold Acknowl-
catesthat no acknowledgewas receivedfor the previous edge signrdin response, to indicate to the requesting
frame. Will be set only if HABEN is set and no ac- devicethat the C152will not commencea DMA to or
knowledgeis received prior to the end of the IFS. from external RAM while the Hold Requestis active.
NOACK is not set followinga broadcast or a multi-
cast packet. The status of this tlag is controUedby the
GSC. 4.1 DMAwith the 80C152
TSTAT.7(LNI) - Line Idle - If set, indicates the re- The C152contains twoidentical generalpurpose 8-bit
ceiveline is idle.In SDLCprotccol it is set if 15consec- DMA charmek with 16-bitaddreasability:DMAOand
utive one are received. In CSMA/CD protocol, line DMA1.DMA transfers can be executedby either Chann-
idle is set ifGRXD remainshigh for approximately1.6 el independentof the other, but onlyby onechannelat
bit times. LNI is cleared after a transition on GRXD. a time. During the time that a DMA transfer is being
The status of this flag is controlledby the GSC. executed, program execution is suspended. A DMA
transfer takes one machine cycle (12 oscillator

7-47
1 I

83C152 HARDWARE DESCRIPTION

DMACHANNEL
O I DMACHANNEL
1

,- m, ~,-
DESTINATIONAODRESS I
m,
DESTINATIONADDRESS

m m : ,- m,
~ ,
SOURCEADDRSSS I SOURCEADORESS

,- m, ; ,- m,
BYTE COUNT I BYTECOUNT

m; m
OMAO CONTROL I DMA1 CONTROL

t Two new bits in PCON control

Hold/Hold Acknowkdge Iogk
270427-28
-. . . . .. . . . .

ueriods) oerbvte transferred. exeeotwhen thedestina- Two other bits in DCONn specifythe phyaiealsource
kon and”sourk are both in’Exte&al Data RAM. In of the &ta to be transferred. These are SAS (Source
that case the transfer takes two machine cycles per Address Space)and ISA (Increment Source Address).
byte. The term DMA Cycle will be used to mean the If SAS = O,the source is in &ta memoryexternal to
transfer of a single&ta bytej whether it takeB1 or 2 the C152.IfSAS = 1,the aoureeis internal. If SAS =
machine cycles. 1 and ISA = O,the internal source is an SFR. If SAS
= 1and ISA = 1,theioternsl sourceis in the 256-byte
Associatedwitheach channel are sevenSFRS,shownin data RAM.
Figure4.1.SARLnand SARI% holdsthe lowand high
bytes of the sourceaddress. Taken together they forma In any case,ifLSA = 1,the sourceaddressis automati-
id-bit SourceAddress Register. DARLn and DARHII cally incrementedafter each byte transfer. If ISA = O,
hold the lowand high bytea of the destinationaddress, it is not.
and together form the Destination Address Register.
BCRLnand BCRHnhold the lowand highbytesof the The functionsof thesefour ccmtrolbits are summarized
number of bytes to be transferred, and together form below:
the Byte CountRegister.DCONn conteinscontroland
flag bits. DAS IDA Destination Auto-lncrament
o 0 ExternalRAM no
Two bits in DCONn are used to speeify the physical o 1 ExternalRAM yes
destination of the data transfer. These bits are DAS
1 0 SFR no
(DestinationAddressSpace)and IDA (IncrementDes-
tination Address). If DAS = O, the destination is in 1 1 InternalRAM yes
data memoryexternal to the C152. If DAS = 1, the SAS ISA Source Auto-Increment
destination is intemsl to the C152. If DAS = 1 and
IDA = O,the internal destinationis a SpecialFunction o 0 ExternalRAM no
Register (SFR).If DAS = 1 and IDA = 1,the inter- o 1 ExternalRAM yes
nal destinationis in the 256-bytedata RAM. 1 0 SFR no
1 1 InternalRAM yes
In any case, if IDA = 1, the destination address is
automaticallyincremented after each byte transfer. If
IDA = O,it is not.

7-48
in~. 83C152 HARDWARE DESCRIPTION

There are four modesin which the DMA channel can dreas. On-chip hardware then clears the tlag (RI, TI,
operate. These are selected by the bits DM and TM RFNE, or TFNF) that initiated the DMA, and decre-
(DemandMode and Transfer Mode)in DCONn: ments BCRn. Note that sincethe tlag that initiated the
DMA is cleared, it willnot generatean interrupt unless
DM I TM Operating Mode DMA servicingis held off or the byte count equals O.
o 0 AlternateCyclesMode DMA servicingmaybe heldoff when alternate cycleis
o 1 BurstMode beingusedor by the status of the HOLD/HLDA logic.
In these situationsthe interrupt for the LSCmay occur
1 0 SerialPortDemand Mode
before the DMA can clear the RI or TI flag. This is
1 1 ErrternalDemand Mode becausethe LSC is seMced according to the status of
RI and TI, whetheror not the DMA channelsare being
The operatingmodesare describedbelow. usedfor the transferringof data. The GSC does not use
RFNE or TFNF figs whenusing the DMA channels
so these do not need to be disabled. When using the
4.1.1 ALTERNATE CYCLE MODE DMA channels to servicethe LSC it is recommended
that the interrupts (RI and TI) be disabled. If the dec-
In Alternate CyclesModethe DMA is initiated by set- remented BCRn is OOOOH, on-chip hardware then
ting the GO bit in DCONn. Followingthe instruction clears the GO bit and sets the DONE bit. The DONE
that set the 00 bit, one more instruction is executed, bit flags an interrupt.
and then the tirat data byte is transferred from the
sourceaddressto the deadnationaddress.Then snother
instructionis executed,and then another byte of data is 4.1.4 EXTERNAL DEMAND MODE
transferred,and so on in this manner.
In External Demand Mode the DMA is initiated by
Each time a data byte is transferred, BCRn (Byte one of the External Interrupt pins, providedthe GO bit
Count Register for DMA Channeln) is decremented. is set. INTO initiates a Channel O DM& and ~
When it reaches OOOOH, on-chip hardware clears the initiates a Channel 1 DMA.
GO bit and se~ the DONE bit, and the DMA ~m.
The DONE bit tlags an interrupt. If the external interrupt is configuredto be transition-
activata then each l-to-Otransition at the interrupt
pin sets the correspondingexternal interrupt flag, and
4.1.2 BURST MODE generatesone DMA Cycle.Then, BCRn is decrement-
ed. No more DMA Cycles take place until another
Burst ModedifTersfrom Alternate cycles modeonly in l-to-Otransition is seen at the external interrupt pin. If
that once the data transfer has begun,program execu- the decremented BCRn = OOOOH, on-chip hardware
tion is entirely suspendeduntil BCRn reaches OOCKIH, clears the GO bit and sets the DONE bit. If the exter-
indicatingthat all data bytesthat wereto be transferred nal interrupt is enabled,it willbe serviced.
have been transferred. The interrupt control hardware
remainsactive duringthe DMA, so interrupt tlags may If the external interrupt is configuredto be level-acti-
get set, but since program executionis suspended,the vated,thtmDMA Cyclescommencewhenthe interrupt
interrupts will not be serviced while the DMA is in pin is pulled low, and continuefor as long as the pin is
progress. held low and BCRn is not IXKOH.If BCRn reachea O
whilethe interrupt pin is stilllow,the GO bit is clear@
4.1.3 SERIAL PORT DEMAND MODE the DONE bit is set, and the DMA ceasea.If the exter-
nal interrupt is enabled,it willbe serviced.
In this modethe DMA can be usedto servicethe Lad
Serial Channel (LSC) or the Global Serial Channel If the interrupt pin is pulled up before BCRn reaches
(GSC). OOOOH, then the DMA ceases,but the GO bit is still 1
and tbe DONE bit is still 0. An external interrupt is not
In SerialPort Demand Mode the DMA is initiated by generated in this case, since in level-activatedmodq
any of the followingconditions,if the GO bit is act: pullingthe pin to a logical 1clearsthe interrupt flag. If
SourceAddress = SBUF .AND. RI = 1 the interrupt pin is then pulledlow again, DMA trans-
DestinationAddress= SBUF ,AND. TI = 1
fers will continue fkom where they were previously
stopped.
SourceAddress = RFIFO .AND. RFNE = 1
DestinationAddress= TFIFO .AND. TFNF = 1 The timing for the DMA Cycle in the tranaition-acti-
vated mode,or for the first
DMA Cyclein the level-ac-
Each time one of the above conditions is met, one tivated mode is as follows:If the l-to-O transition is
DMA Cycleis executed;that is, one data byte is trans-
ferred from the source addreas to the destination ad-

7-49
intd. 83C152 HARDWARE DESCRIPTION

detected before the final machine cycle of the instruc- and ~ and/or ~ signalsare generatedas needed,in
tion in progress,then the DMA commencesas soon as the same manner as in the execution of a MOVX
the instructionin progressis completed.Otherwise,one @’DPTRinstruction.
more instruction will be executed before the DMA
starts. No instruction is executedduring any DMA Cy-
cle. 4.3 Hold/Hold Acknowledge
Twooperatingmodesof Hold/Hold Acknowledgelog-
4.2 Timing Diagrams ic are available,and either or neither may be invoked
by software. In one mode, the C152generateaa Hold
Timing diagrams for single-byteDMA transfers are Request signal and awaits a Hold Acknowledgere-
shown in Figures 4.2 through 4.5 for four kinds of sponsebefore commencinga DMA that involvesexter-
DMA Cycles:internal memoryto internal memory,in- nal RAM. This is called the RequesterMode.
ternal memory to external memory, external memory
to internal memory, and external memory to external In the other mode, the C152accepts a Hold Request
memory.In each ease we assumethe C152is executing signrdfrom an external device and generates a Hold
out of external programmemory.If the C152is execut- Acknowledgesignal in response,to indicate to the re-
ing out of internal program memory,then IZZN is in- questing dexiee that the C152 will not commence a
active, and the Port Oand Port 2 pins emit POand P2 DMA to or from external W while the Hold Re-
SFR data. If External Data Memory is involved,the queat is active. This is called the Arbiter mode.
Port Oand Port 2 pins arc usedas the address/data bus,

.... . . . . . . . . . . .. . . ..... .. . . .. ... . .

FLOAT ~~T~
----------------------------------

P2 PCH x P’ SFR Pctl

x

~m” ew~ “fl:&y

270427-29

Figure 4.2. DMA Tranafer from Internal Memory to Internal Memory

“~
:. .
POINST
.. OARLn W DATAOUT
x x Xp” :::XI!C

I P2 PCH x OARHn x PCH

Figure 4.3. DMA Traneferfrom Internal Memory to External Memory

7-50
i~. 83C152 HARDWARE DESCRIPTION

I P2 PCH x SARH. x PCH

“~
~OUACYCLE~REs#c&yM
27@427-31

Figure 4.4. DMA Transfer from External Memory to Internal Memory

~’z p~R’”o’~’2
Os’” Os’‘“’””~
ALE

I F2m

I PO ~-~~~-
. .
- ‘ -- ;Lii--
------------
‘B;i;ir
----
OARLn x OATAOUT x X’4::E

I ‘2 PCH x SARHn x OARH. x Pm

I 270427-S2

Figure 4.5. DMATranafer from External Memory to External Memory

4.3.1 REQUESTER
MODE 4.3.2ARBITERMODE
The Requester Mode is selectedby setting the control For DMAs that are to be driven by somedeviceother
bit lU3Q,which residesin PCON. In that mode, when than the C152, a different version of the Hold/Hold
the C152wantato do a DMA to ExternalData Merno- Acknowledgeprotocol is available.In this veraiosz,the
ry, it first generatesa Hold Requestsignal,~, and deviee which is to drive the DMA sends a Hold R+
waits for a Hold Acknowledgesignal, HLDA, before quest signal,~, to the C152. If the C152is current-
commencingthe DMA o ly performinga DMA to or from ExternalData Memo-
execution continues while HLDA is awaited. The I’Y,it willcompletethis DMA beforerespondingto the
DMA is not begun until a logicalOis detected at the Hold Request. When the C152 responds to the Hold
HLDA pin. Then, oncethe DMA has begun,it goesto Request,it does so by activating a Hold Acknowledge
completionregardlessof the logiclevelat HLDA. sigd, HLDA. This indicates that the C152 will not
commence a new DMA to or from External Data
The protoed is aetivatex-1
only for DMAs (not for pro- Memorywhile~ remains active.
P fetches or MOVX operations), and only for
DMAs to or thn External Data Memory.If the data Note that in the Arbiter Mode the C152does not sus-
destination and source are both internal to the C152, penalprogram execution at all, even if it is executing
the ~/RR protocolis not used. from externalprogram memory. It does not surrender
w of its ownbus.
The HLD output is an alternate function of port pin
P1.5, and the HLDA input is an alternate firnctionof The Hold Request input, ~, is at P1.5. The Hold
port pin P1.6. Acknowledge output, HLDA, is at P1.6. This
7-51
i~. 83C152 HARDWARE DESCRIPTION

versionof the Hold/Hold Acknowledgefeature is se- ea are done only through DMA operations, not by
lectedby setting the control bit ARB in PCON. MOVXinstructions.

The functions of the ARE and REQ bits in PCON, One CPU is pro-cd to be the Arbiter and the
then, are other, to be the Requester. The ALE Switch selects
whichCPU’sALE signalwillbe directedto the address
ARB REQ Hold/Hold Acknowledge Logic latch. The Arbiter’s ALE is selectedif HLDA is high,
o 0 Disabled and the Requester’sALE is selected if= is low.
o 1 C152 generates~, detects HLDA
1 0 C152 detects ~, generatesHLDA
1 1 Invalid
‘k~m-

4.3.3 USING THE HOLD/HOLDACKNOWLEDGE

The ~~~ logic ordy affects DMA opera-
tion withexternalRAM and doesn’taffectother opera-
tions with external RAM, such as MOVXinstruction. ,+DJ 270427-34
Figure 4.6 shows a system in which two 83C152Sare
sharinga dobal RAM. In this svstem.both CPUSare Figure 4.7. ALE Switch Select
execu~g ~om internal ROM. Neith~ CPU usea the
bus exceptto accessthe shared RAM, and such access- The ALE Switchlogic csn be implementedby a single
74HCO0,as shownin Figure 4.7.

L-kL
Ws 7
ALE 4
L
SE j

tmmz 7
s

.-
AM
miim

ALE

5X352
rP REQ -~

270427-33

Figure 4.6. Two 83C152S Sharing External RAM

7-52
i@. 83C152 HARDWARE DESCRIPTION

4.3.4 INTERNAL LOGIC OF THE ARBITER When the arbiter wants to DMA the XRAM, it first
aetivateaDMXRQ.This signalpreventsQ2 from being
The internallogicof the arbiter is ahownin Figure4.8. set if it is not already set. An output low from Q2 en-
In operationan input low at HLD sets Q2 if the arbi- ables the arbiter to carry out its DMA to XRAM, and
ter’s internal signal DMXRQ is low. DMXRQ is the maintains an output high at HLDA. When the arbiter
arbiter’s “DMA to XRAM Request”. SettingQ2 aeti- completeaits DMA, the signal DMXRQ ~to O,
vates HLDA through Q3. Q2 being set also disables whichenablesQ2to acceptsignalsfromthe HLD input
any DMAs to XIU-M &at the arbikr might decideto again.
do duringthe requester’sDMA.

Figure 4.9 showsthe minimum responsetime, 4 to 7

CPU oscillator perioda, between a transition at the
HLD input and the responseat HLDA.

Inhibit Arbiter’s
DMXRQ OMA to XRAM
I 4

KD Input
(P1.5) ~ Da DO D
Q1 Q2 Q3
WA Output
> b > 6~ (P1.6)

Clock1 Clock2 Clock1

270427-39

Figure 4.8. Internal Logic of the Arbiter

7-53
intd. 83C152 HARDWARE DESCRIPTION

~ Input I
,
1,
CPU Osc. Periods
1,

Clock 1
0,

Clock 2
1,
I I
14
1 1
rm output , I
1,
II
It
1-
,2 Osc. ‘ 4 Osc. ,
Periods P*llOds
270427-40

Figure 4.9. Minimum ~/~ Response Time

Inhibit Rsqusstsr’s
DMXRQ DUA to XRAM

7r
~ Input
(P1.6) ( SQ

Q1
m output
DQ + (P1.5)
P
Q3

Clock 1 >
— DQ

QIA
Clock 1
>

Ciock 2
270427-41

Figure 4.10. Internal Logic of the Requester

(Clock 1 and Clock 2 are Shown in Figure 4.9)

7-54
i~. 83C152 HARDWARE DESCRIPTION

4.3.5 Internal Logic of the Requester the requestand receiveanotheracknowledgebefore an-

other DMA cycleto XRAM cartpti. Obviouslyin
The internal logic of the requester is shownin Figure this ~ the “alternate cycles” mode may consist of
4.10. INtially, the requester’sinternal signal DMXRQ singleDMA cyclesseparatedby anynumberof instruc-
~mto XRAM Request)is at O,so Q2 is set and the tion cycles,dependingon howlongit takes the request-
HLD output is high. As long as Q2 stays set, the re- er to regain the bus.
quester is inhibitedfrom starting any DMA to XFL4M.
A channel 1 DMA in progresswill alwaysbe overri-
When the requeaterwants to DMA the XRAM, it first ddenby a DMA requestof any kindfrom channel O.If a
aetivateaDMXRQ.This signalenablesQ2to be cleared channel 1 DMA to XRAM is in progressand is over-
(but doesn’tclear it), and, if= is high, rdsoacti- riddenby a channelODMA whichdoeanot require the
vates the ~ output. bus, DMXRQwifl~o Oduringthe channel ODMA,
thus de-activatingHLD. Again,the requester must re-
A l-to-O transition from HLDA can now clear Q2, new its requeatfor the b~ and must receivea new 1-
which will enablethe requesterto commenceits DMA to-o transitionin HLDA beforechannel 1 can continue
to XRAM. Q2 being low also maintains an output low its DMA to XRAM.
at HLD. When the DMA is completed,DMXRQgoes
to O,which sets Q2 and de-activates~.
4.4 DMAArbitration
Only DMXRQgoingto Ocan set Q2. That meansonce
Q2 gets cleared, enablingthe requester’sDMA to pro- The DMA Arbitration dsscribedin this section is not
ceed, the arbiter has no way to stop the requester’s arbitration between two devieeawanting to access a
DMA in progress.At this poinL de-activatingHLDA shared RAM, but on-chiparbitrationbetweenthe two
will have no effect on the requeater’suse of the bus. DMA channelson the 8XC152.
Only the requesteritselfcan stop the DMA in progress,
and when it does, it de-activates both DMXRQ and The 8XC152 providestwo DMA channels, either of
m. which may be called into operationat any time in re-
sDOnae to real time conditionsin the armlicationcircuit.
If the DMA is in alternate cyclesmode, then each time &we a DMA cycle alwaysusesthe ~XC152’sinternal
a DMA cycleis completedDMXRQ goesto O,thus de- bus, and there’s only one internalbus, ordyone DMA
activating ~. once ~ has been de-activated,it channel ears be serviced during a single DMA cycle.
can’t be re-asaertedtill tier HLDA has beenseento go Executingprogram instructionsalso requires the inter-
high (through flip-flop QIA). Thus every time the rsalbus, so program executionwillalsobe suspendedin
DMA is suspendedto allowan instructioncycleto pre- order for a DMA to take place.
ceed, the requeater gives up the bus and must renew

I 1

4L

270427-42

Figure4.11.InternalBus Usage

7-55
i~. 83C152 HARDWARE DESCRIPTION

Figure 4.11showsthe three tasks to which the internal The return value is based on the conditionof the 00
bus of the 8XC152can be dedicated. In this tigurq bit for each channel, and on the value returned by an-
Instruction Cycle means the complete execution of a other functio~ named modedogic (). The algorithm
single instruction, whether it takes 1, 2 or 4 machine for mode-logic () is the samefor both channels.The
cycles.DMA Cyclemeans the transfer of a singledata function is shown in Figure 4.13 as a pseudo-HLL
byte from sourceto destination,whetherit takes 1 or 2 functionjmode-logic (n), wheren = Owhenthe func-
machinecycles.Each time a DMA Cycleor an Instruc- tion is invokedfor DMA cbannelO,and n = 1 when
tion Cycleis executed,on-chiparbitration logic deter- it’sinvokedfor DMA channel 1.The valuereturned by
mines which type of cycle is to be executednext. this t%nctionis either Oor 1, and will be passed on to
the DMA arbitration logicin Figure4.12.
Note that when an instruction is executed, if the in-
struction wrote to a DMA register (definedin Figure Note that the arbitration logicas shownin Figure 4.12
4.1 but excludingPCON), tien snother instruction is alwaysgivesprecedenceto channelOover channel 1. If
executedwithout further arbitration.Therefore, a sin- 000 is set and mode-logic (0) returns a 1, then a
gle write or a series of writes to DMA registers will DMAOcycle is called withouttiwther referenm to the
preventa DMA from takingpla% and will continueto situation in channel 1. That is not to say a DMAI Cy-
prevent a DMA from taking place until at least one cle will be interrupted once it has begun.Once a cycle
instruction is executed which does not write to any has begun,be it an InstructionCycleor a DMA Cycle,
DMA register. it will be completedwithoutinterruption.

The logicthat determineswhetherthe next cyclewillbe The statements in modedogic (n), Figure4.13,are ex-
a DMAOcycle,a DMAI cycle,or an Instruction Cycle ecutedsequentiallyuntil an “if’ condition,basedon the
is shownin Figure 4,12as a pseudo-HLLfunction.The DMA mode progrsmmed into DCONn, is sstistied.
statementsin Figure 4.12 are executedsequentiallyun- For example, if the channel is configured to Burst
lessan “it” conditionis sstisfi~ in whichcase the cor- mode,then the first if-conditionis satisfied,so the “re-
responding“return” is executedand the remainder of turn 1“ exrmssion is executedand the remainderof the
the function is not. The return value of O, 1, or 2 is fimctioni; not.
passed to the arbitration logicblockin Figure 4.11 to
detemninewhich exit path from the block is used.

arbitration-logic:
if (GOO = 1 .AND. mode-logic (0) = 1) return O;

if (GO1 = 1 .AND. modeJogic (1) = 1) return 1;

else return 2;

end arbitration-logic;
Figure 4.12. DMA Arbitration Logic

7-56
intel. 83C152 HARDWARE DESCRIPTION

mode_logic (n) :

if (DCONnindicates burst-mode) return 1;

if (DCONnindicates extern_demand-mode)
{
if (demand-flag = 1) return 1;
else return O;
)
if (DCONnindicates SP-demand.mode)
(
if (SARII= SBUF .AND. RI = 1) return 1;
if (DARn= SBUF .AND. TI = 1) return 1;
if (sARn = RFIFO .AND. RFNE= 1) return 1;
if (DARII=TFIFO .AND. TFNF=l .AND.
previous-cycle = instruction_cycle) return 1;
else return O;
)
if (DCONnindicates alt-cycles_mode)
{
if (DCONmindicates .NOT. alt-cycles-mode
.OR. GOm = O)
{
if (previous_cycle = instruction_cycle’
return 1;
else return O;
1
if (previous-cycle = instruction-cycle
.AND. previousdma-cycle = .NOZ. DNAII)
return 1;
1
return O;
end mode-logic(n) ;

Figure4.13.DMAModeLogic

7-57
intd. 83C152 HARDWARE DESCRIPTION

If the channelk configuredto ExternalDemand mode, For example,considerthe situation wherechannelOis

then the tirst if-conditionis not satisfiedbut the second configuredto service TFIFO and channel 1 is config-
one k. In that case the block of statements following ured to Alternate Cyclesmode.Then DMAsto TFIFO
that if-conditionand delimited by {...) is executed:if willalwaysoverridethe alternate cyclesof channel 1.If
the demandflag (IEO for channelOand IE1 for chan- TFIFO needs more than 1 byte it will receivethem in
nel 1) is set, the “return 1“ expressionis executedand precedence over channel 1, but each DMA to TFIFO
the remainderof the tkwtion is not. If the dcrmmdtlag must be precededby an Instructioncycle.The sequemce
is not set, the “return O“expressionis executedand the of cyclesmight be:
remainderof the function is not.
DMA1 cycle
If the channel is configured to serial Port Demand Instruction cycle
mode,the sourceand destinationaddresses,SARnand DMA1 CYC1% during which TFNF gets set
DARn, have to be checked to see which Serial Port Instruction cycle
buffer is beingaddressed,and whetherits demandflag DMAOcycle
is set. Instruction cycle
DMAOcycle, as a result of which TFNF gets cleared
SARnrefersto the id-bit sourceaddressfor “this chan- Instruction cycle
nel.” Note that the condition DMA1 cycle
Instruction cycle
SARn = SBUF DMA1 cycle
cannot be true unlessthe SASand ISAbits in DCONn Instruction cycle
are contlguredto select SFR space. If SARnis numeri- .,.
cally equalto the address of SBUF(99H),and SASand
ISA are configuredto select internal RAM rather than The requirement that a DMA to TFIFO be preceded
SFR space, then SARn refers to location 99H in the by an Instruction cycle can result in the normal prece-
“upper 128”of internal RAM, not to SBUF. denceof channelOover channel 1beingthwarted.Con-
sider for examplethe situation where channelOis con-
If the test for SARn = SBUFirt% and if the flagRI figuredto serviceTFIFO, and is in the processof doing
is set, mode-logic (n) returns as 1 and the remainder so, and channel 1 decidesit wants to do a Burst mode
of the function is not executed. Otherwise,execution DMA. The sequenceof events might be:
proceedsto the next if-condition,testingDARn against
SBUFand T1 against 1. Instruction cycle (sets GO bit in DCON1)
Instruction cycle (during which TFNF gets set)
The sameconsiderationsregardingSASand ISA in the DMAOcycle
SARn teat are now applied to DAS and IDA in the DMA1 cycle
DARn test. If SFR space isn’t selected,no Serial Port DMA1 cycle
bufferis beingaddressed. DMA1 cycle
...
Note that ifDMA channel n is configuredto Alternate DMAI cycle (completeschannel 1 burst)
Cycleamode,the logicmust examinethe other DCON Instruction cycle
register, DCON~ to determm “ e if the other channelis DMAOcycle
also cordiguredto Alternate Cyclesmode and whether Instruction cycle
its 00 bit is set. In Figure 4.13, the symbolDCONn ...
refers to the DCON register for “this channel,” and
DCONm refersto “the other channel.” This sequencebegins with two Instruction cycles.The
first one acceswsa DMA registcx(DCONl), and there-
A careful examinationof the logic in Figure 4.13 will fore is followed by another Instruction cycle, which
reveal some idiosyncrasies that the user should be presumablydoes not accessa DMA register.After the
aware of. First, the logicallowssequentialDMA cycles seeond Instruction cycle both channels are ready to
to be generated to service RFIFO, but not to service generate DMA CyCIS,and Chtllld OOfcourse takes
TFIFO. This idiosyncrasy is due to internal timing preccdcmx. After the DMAO cycle, channel O must
contlicts, and results in each individualDMA cycle to wait for an Instruction cycle before it can access
TFIFO havingto be immediatelyprecededby an In- TFIFO again. Channel 1, beingin Burst mode,doesn’t
struction cycle. The logic disallowsthat there be two have that restriction, and is thereforegranteda DMA1
DMAs to TFIFO in a row. cycle. After the fnt DMA1 cyclej channel O is still
waitingfor an Instmction cycleand channel1still dces
If the user is unawareof this idiosyncrasy,it can cause not have that restriction. There foIlowsanotherDMA1
problemsin situationswhereone DMA channelis serv- cycle.
icingTFIFO and the other is configuredto a complete-
ly ditTerentmcde of operation.

7-58
i~e 83C152 HARDWARE DESCRIPTION

The result is that in this @c* css c~el o hss Function Register (SFR). If DAS = 1 and IDA = 1,
to wait until channel 1completesits BurstmodeDMA, the destinationis in Internal Data WM.
and then has to wait for an Instruction cycleto be gen-
erated, beforeit cart continueits ownDMA to TFIFO. IDA (IncrementDestinationAddress)If IDA = 1,the
The delay in servicingTFIFO can cause an Underflow destination address is automaticallyincremented after
conditionin the GSC transmission. each byte transfer. If IDA = O,it is not.
The delay will not occur if channel 1 is configuredto SAS speeitlesthe SourceAddress Space. If SAS = 0,
Alternate Cyclesma since channelOwouldthen see the source is in External Data Memory. If SAS = 1
the Instruction cycles it needs to completeits logic re- and ISA = O,the source is an SFR. If SAS = 1 and
quirementsfor amerting its request. ISA = 1, the source is internal Data RAM.

ISA (Increment source Address) If ISA = 1, the

4.4.1 DMA Arbitration with Hold/Hold Ack source address is automaticallyincrementedafter each
The Hold/Hold Acknowledgefeatureis invokedby set- byte transfer. If ISA = O,it is not.
ting either the ARB or REQ bit in PCON.Their effect
is to add the requirementsof the Hold/Hold Ack pro- DM (Demand Mode) If DM = 1, the DMA Channel
tocol to mode-logic (). This amountsto replacingev- opcrates in Demand Mode. In Demand Mcde the
ery expression“return 1“ in Figure 4.13 with the ex- DMA is initiated either by an external signal or by a
pression “return hld-hlda-logic ( )“, where SerialPort tlag, dependingon the value of the TM bit.
hld-idda-logic ( ) is a fimctionwhichreturns 1 if the If DM = O,the DMA is requestedby setting the GO
Hold/Hold Ack motocol is satisfied,and returnsOoth- bit in software.
erwise.A suitabfi definitionfor hltida-logic ( ) is
shownin Figure 4.14. TM (Transf~ Mode) If DM = 1 then TM selects
whethera DMA is initiatedby an external signal (TM
= 1) or by a Serial Port flag (TM = O).If DM = O
then TM selectswhethertie data transfers are to be in
4.5 Summaryof DMA Control Bita bursts (TM = 1) or in alternate cycles(TM = O).
DCONn [ DAS / IDA I SAS I ISA I DMI TM I DONEI GOI
DONE indicates the completionof a DMA operation
DAS spccitlesthe Destination Address Space.If DAS and tlagsan interrupt. It is set to 1by on-chiphardware
= O,the destination is in External Data Memory. If when BCRn = O,and is cleared to Oby on-chip hard-
DAS = 1 and IDA = O, the destinationis a Special ware when the interrupt is vectored to. It can also be
setor cleared by software.

hold-holda( ):

if (ARB= O .AND. REQ = O) return 1;

if sARn = XRAM. OR. DARn= XRAM)
{
if (ARB = 1 .AND. ~ = 1) return 1;
if (REQ = 1 .AND. HLDA= O) return 1;
else return O;

return 1;
end hold-holda ( );

Figure 4.14. Hold/Hold Acknowledge Logic as a Paeudo-HLL Function

7-59
inl# 83C152 HARDWARE DESCRIPTION

GO is the enablebit for the DMA Channel itself. The Note that setting the DMA bit does not itaelf~figure
DMA Channelis inactiveif GO = O. the DMA channels to seMee the GSC. That job must
be done by software writes to the DMA registers. The
PCON SMOD I ARE I REQ ] GAREN I XRCLK I GFIEN I PDN I IDL
DMA bit only seleots whether the GSCRV and
GSCTVinterrupts are flaggedby a FIFO needingserv-
ARB enables the DMA logicto detect ~ and gener- ice or by an “operationdone” signal.
ate HLDA. After it has activatedHLDA, the C152will
not begina new DMA to or from External Data Mem- The Receive and Transmit Error interrupt flags are
ory as long as ~ is seen to be active. This logicis generatedby the logicalOR of a numberof error condi-
disabledwhenARB = O,and enabledwhenARB = 1. tions, which are describedin Section3.6.5.
REQ enablesthe DMA logicto generate~ and de- Each interrupt is assigneda freed location in Program
tect HLDA before performinga DMA to or from Ex- Memory,and the interrupt causes the CPU to jump to
ternal Data Memory.After it has activated ~, the that location. All the interrupt fiags are sampled at
C152willnot beginthe DMA until= is seento be S5P2of everymachine CYCIG and then the samples are
active. This logicis disabledwhen REQ = O,and en- sequentiallypolled during the next machine cycle. If
abled when REQ = 1. more than one interrupt of the same priority is activq
the one that is highest in the polling sequenceis serv-
iced first. The interrupts and their fixed locations in
5.0 INTERRUPTSTRUCTURE Program Memoryare listedbelowin the order of their
pollingsequence.
The 8XC152 retains all fiveinterruptaof the 80C51BH.
Sixnewinterrupts are addedin the 8XC152,to support
its GSC and the DMA features. They are as listed be-
low,and the flagsthat generatethem are shownin Fig-
ure 5.1.

GSCRV — GSC ReceiveValid 270427-42

GSCRE — GSC ReceiveError
GSCTV — GSC TransmI“tValid

2EP--CRE
GSCTE — GSC Transmit Error
DMAO — DMA ChanmelO Done
DMA1 — DMA Channel 1 Done
270427-44
As shownin Figure5.1,the ReceiveValid interrupt ean
be signated either by the RFNE tlag (Receive FIFO 7FNF ‘1 DMA= ~
Not Empty), or by the RDN flag (Receive Done).
Which one of these flags causes tie interrupt depends
on the setting of the DMA bit in the SFR named $%+.s.
TSTAT. ~N d MA. 1

270427-45
DMA = O means the DMA hardware k not config-
ured to servicethe GSC, so the CPU will serviceit in
software in response to the Receive FIFO not being
empty-In that case,RFNE generatesthe ReceiveValid
IaED-’”m 270427-46
interrupt.
DMA = 1 meansthe DMA hardware is configuredto OONE
~OMAO
(OCONO.1)
service the GSC, in which case the CPU need not be 270427-47
interrupted till the receive is complete. In that case,
RDN generatesthe ReceiveValid interrupt. ‘NE ~DMAl
(OCON1.1)
270427-4S
Sknkrly the Transmit Valid interrupt ean be signaled
either by the TFNF flag (Transmit FIFO Not Full), or Figure 5.1. Six New Interrupts in the 8XC152
by the TDN flag (Transmit Done), depending on
whether the DMA bit is Oor 1.

7-60
 83C152 HARDWARE DESCRIPTION

The two Interrupt Priority registers in the 8XC152are

Interrupt Location Name as follows:
IEO OO03H ExternalInterruptO 76543 2 1 0
GSCRV O02BH GSC Receive Valid 1P: — — — Ps PT1 Pxl PTo Pxo
TFO OOOBH Timer OOverflow
GSCRE O033H GSC Receive Error
DMAO O03BH DMA ChannelO Done
Address of IP in SFR space = OB8H(bit-addressable)
IE1 O013H ExternalInterrupt1 76 5 4 3 2 1 0
GSCTV O043H GSCTrartsmitValid IPN1:
DMA1 O053H DMA Channel 1 Done
TF1 OOIBH Timer 1 Overflow
O04BH
Address of IPN1 in SFR space = OF8H(trit-sddress-
GSCTE GSC TransmitError
able)
TI+RI O023H UART Transmit/Receive
The bits in 1P are uncharuzedfrom the standard 8051
Note that the locationsof the basic 8051 interruut.sare 1P register. The bits in IP~l areas follows:
the same as in the reat of the MCS-51 Fsrnil~. And PGSTE = 1 GSC Transmit Error Interrupt Priority
relativeto each other they retsin their same positionsin to High
the pollingsequence. . o Priority to Low
PDMAI = 1 DMA Channel 1 Done Interrupt Priori-
The locationsof the new interrupts all followthe locs- ty to High
tion.sof the basic 8051interrupta in Program Memory, . o Priority to Low
but they are interleaved with them in the polling se- PGSTV = 1 GSC Transmit Valid Interrupt Priority
quence. to High
= o Priority to Low
To support the new interrupts a second Interrupt En- PDMAO= 1 DMA ChannelODone Interrupt Priori-
ableregister and a secondInterrupt Priority registerare ty to High
implementedin bit-addressableSFR space.The two In- . o Priority to Low
terrupt Enableregistersin the 8XC152are as follows: PGSRE = 1 GSCReceiveError Interrupt Priority to
7 6543 2 1 0 High
. o Priority to Low
IE: EA — — ES ETl EX1 ETo EXO PGSRV = 1 GSC ReeeiveValid Interrupt Priority to
High
. o Priority to Low
Address of IE in SFR space = OA8H(bit-addressable)
76 5 4 3 2 1 0 Note that these registers all have unimplementedbits
lENl:U4EGSTdEDMAllEGS~ EDMAo!EGSREtEGsRvi (“-”). If thesebits are r~ they willreturn unpredict-
able values. If they are written to, the value written
goes nowhere.
Address pF IEl in SFR space = OC8H(bit-address-
able) It is recommendedthat user software should never
write 1sto unimplementedbits in MCS-51devices.Fu-
The bits in IE are unchangedfrom the stsndsrd 8051 ture versionsof the devicemay have newbits instslled
IE register. The bits in IEN1 are as follows: in these loestiorta.If so, their reset valuewill be O.Old
EGSTE = 1 Enable GSC Transmit Error Interrupt softwarethat writes 1sto newlyimplementedbits may
= ODisable unexpectedlyinvokenew features
EDMA1 = 1 EnableDMA Channel 1 Done Interrupt
= O Disable The MCS-51 interrupt structure provides hardware
EGSTV = 1 EnableGSC Trsnsmit Valid Interrupt support for only two priority levels High and Low.
= ODisable With as many interrupt sources as the 8XC152has, it
EDMAO= 1 Emble DMA ChannelODone Interrupt may be helpful to know how to augmentthe priority
= ODisable structure in software.Anynumberof prioritylevelscan
EGSRE = 1 EnableGSC ReceiveError Interrupt be implementedin software by savingand redefining
= ODisable the interrupt enableregisterswithin the interrupt serv-
EGSRV = 1 EnableGSC ReceiveValid Interrupt iee routines. The techniqueis deacribedin the “MCS-
= ODisable 51” ArchitecturalOverview”chapter in this handbook.

7-61
intd. 83C152 HARDWARE DESCRIPTION

5.1 GSC Transmitter Error Conditions The TCDT bit can get set onlyif the GSCis eonfigured
to CSMA/CD mode. In that case, the GSC hardware
The GSC Transmitter seetion reports three kinds of sets TCDT when a collisionis detectedduring a trana-
error conditions: rnission,and the collisionwasdetectedafter TFIFO has
TCDT — Transmitter CollisionDetector baa accesed. Alao, the GSC hardware sets TCDT
whena detectedecdlisioncausesthe TCDCNT register
UR — Underrun in Transmit FIFO to overflow.
NOACK— No Acknowledge
The UR bit can get set only if the DMA bit in TSTAT
These bits reaidein the TSTATregister.User software is set. The DMA bit being set informsthe GSC hard-
ean read them, but onlythe GSChardwarecan write to ware that TFIFO is being seMeed by DMA. In that
them. The GSC hardware will set them in responseto caaGif the GSCgoeato fetch anotherbytefrom TFIFO
the variouserror conditionsthat they represent.When and finds it empty, and the byte count register of the
user softwaresets the TEN biL the GSChardware will DMA channel servicingTFfFO is not zero, it sets the
at that time clear these tlags. This is the onlyway these UR bit.
flags can be cleared.
If the DMA hardware is not being used to aerviee
The logicalOR of these three bits flagsthe GSCTrans- TFIFO, the UR bit cannot get set. If the DMA bit is O,
mit Error interrupt (GSCTE)and clears the TEN bit, then when the GSC finds TFIFO empty, it assumes
as shownin Figure 5.2.Thus any detectederror condi- that the transmissionof data is completeand the trans-
tion aborts the transmission.No CRCbits are transmit- missionof CRC bits can begin.
ted. In SDLC mode, no EOF tlag is generated. In
CSMA/CD mode, an EOF is generated by default, The NOACKbit is fictional only in CSMA/CD
since the GTXD pin is pulled to a logic 1 and held mode and onlywhenthe HABENbit in RSTAT is set.
there. The HABEN bit turns on the Hardware Baaed Ac-
knowledgefeature, as deacribedin Seetion3.2.6.If this
feature is not invoked,the NOACK bit will stay at O.

:E=ii 270427-49

Figure 5.2. Transmit Error Ffsgs (Logic for Clearing TEN, Setting TDN)

7-62
i~. 83C152 HARDWARE DESCRIPTION

CRCE+

1 set
EOF ‘RDN
RECEIVEO
270427-50
1
Figure 5.3. Reeeive Error Flag (Logic for Clearing GREN, setting RDN)

If the NOACK bit gets set, it meansthe GSC has com- The logicalOR of these four bits flagsthe GSCReceive
pleted a transmission, and was expectingto receive a Error interrupt (GSCRE)and clears the GREN bit, as
hardware based acknowledgefrom the receiver of the shownin Fimre 5.3. Note in this figurethat any error
message,but did not receive the acknowledge,or at conditionW prevent RDN from =g set.
leastdid not receiveit cleanly.Thereare three waysthe
NOACK bit can get set: A CRC Error means the CRC generatordid not come
1. The acknowledgesignal (an unattached preamble) to its correct value after calculating the CRC of the
was not receivedbefore the IFS was completed. message plus roxived CRC. An Alignment Error
means the number of bits received betweenthe BOF
2. A collisionwas detected during the IFS. and EOF was not a multipleof 8.
3. The line was active during the last bit-time of the
IFS. In SDLCmode,the CRCEbit gets set at the end of any
frame in which there is a CRC Error, and the AE bit
The first condition is an obviousreasonfor setting the gets set at the end of any frame in which there is an
NOACK bit, since that’s what the hardware based ac- AlignmentError.
knowledgeis for. The other two waysthe NOACK bit
~ get set are to guard against the possibilitythat the In CSMA/CD modejif there is no CRC Error, neither
transmittingstation might mistake an unrelated trans- CRCEnor AE will get set. If there is a CRC Error and
missionor transmission fmgment for an acknowledge no AlignmentError, the CRCE bit willget set, but not
signal. the AE bit. If there is both a CRC Error and an Align-
ment Error, the AE bit will get set, but not the CRCE
bit. Thus in CSMA/CD mode,the CRCE and AE bits
5.2 GSC ReceiverErrorConditions are mutuallyexclusive.
The GSC Reeeiver section reports four kinds of error The ReceiveAbort ilag, RCABT,gets set if an incom-
conditions: ing frame was interrupted after receiveddata had al-
CRCE — CRC Emor readypassedto the ReceiveFIFO. In SDLCmode,this
can happenif a line idle conditionis detectedbeforean
AE — AlignmentError EOF flag is. In CSMA/CD mod% it can happen if
RCABT— ReceiveAbort there is a collision.In either case, the CPU will haveto
OVR — Overrun in ReceiveFIFO re-initialize whatever pointers and counters it might
havebeen using.
These bits reaide in the RSTATregister.User software
can read them, but onlythe GSChardwarew write to The OverrunError flag, OVR, gets set if the GSC Re-
them. The GSC hardware will set them in responseto ceiveris ready to push a newly receivedbyte onto the
the variouserror conditionsthat they represent. When ReceiveFIFO, but the FIFOis full.
user software sets the GREN bit, the GSC hardware
willat that time clear these flags.This is the only way Up to 7 “dribble bits” can be receivedafter the EOF
these flagscan be cleared. withoutcausingan error condition.

7-63
ii@l. 83C152 HARDWARE DESCRIPTION

6.0 GLOSSARY DAS - DestinationAddress Space,see DCON.

ADR0,1,2,3 (95H, OA5H, OB5H,OC5H) - Address DCJ - D.C. Jam, see MYSLOT.
Match Registers 0,1,2,3- The contents of these SFRS
are comparedagainst the address bits from the serial DCGNO/1(092H,093H)
data on the GSC. If the address matchesthe SFR, then 7654321 0
the C152 accepts that frame. If in 8 bit addreaaing
mode,a match with artyof the four registerswilltrigger I DAS I IDA ! SAS I ISA I DM ! TM I DONE I Go I
acceptance.In 16 bit addressing mode, a match with
ADR1:ADROor ADR3:ADR2 will be accepted. Ad- The DCON registerscontrolthe operationof the DMA
dress lengthis determinedby GMOD (AL). chasmelsby determiningthe source of data to be trans-
ferred,the destinationofthe data to be transfer, and the
AE - AlignmentError, see RSTAT. variousmodeaof operation.
AL - AddressLength, see GMOD.
DCON.O(00) - EnableaDMA Transfer - When set it
AMSKO,l(OD5H,OE5H)- AddressMatch Mssk 0,1- enables a DMA channel. If block mode is set then
I&ntifies which bits in ADRO,l are “don’t care” bits. DMA transfer starts as soon as possibleunder CPU
Setting a bit to 1 in AMSKO,l identifies the corre- control. If demrmd mode is set then DMA transfer
spondingbit in ADDRO,I as not to be examinedwhen starts whena demandis asserted and recognized.
comparingaddresses.
DCON.1 (DONE) - DMA Transfer is Complete -
BAUD - (941-1)Contains the programmablevalue for When set the DMA transfer is complete.It is set when
the baudrate generatorfor the GSC.The baud rate will BCR equals O and is automatically reset when the
equal (fose)/((BAUD+ 1) X 8). DMA vectors to its interrupt routine. If DMA inter-
BCRLO,l(OE2H,OF2H)- Byte Count Register Low rupt is disabledand the user software executesa jump
0,1- Containsthe lower byte of the byte count. Used on the DONE bit then the user software must also
during DMA transfers to identify to the DMA chan- reset the done bit. If DONE is not set, then the DMA
nels whenthe transfer is complete. transfer is not complete.

BCRHO,l(OE3H,OF3H)- Byte Count Register High DCON.2 (TM) - Transfer Mode - When set, DMA
0,1- contains the upper byte of the byte count. burst transfers are used if the DMA channel is config-
ured in block mode or external interrupts are used to
BKOFF(OC4H)- BackoffTimer - The baokofftimer is initiate a transfer if in Demand Mode. When TM is
an eightbit count-downtimer with a clockperiodequal clear~ Alternate CycleTransfers are used if DMA is
to one slot time. The backoff time is used in the in the BlockMode,or LocalSerialcharmel/GSCinter-
CSMA/CDcollisionreardutionalgorithm. rupts are used to initiate a transfer ifin DemandMode.

BOF - Beginningof Frame flag - A term commonly DCON.3 (DW - DMA channel Mode - When set,
used when dealing with paoketized&ta. Signifiesthe Demand Mode is used and when cleared, BlockMode
beginningof a frame. is used.

CRC - CyclicRedundancyCheck - An error checking DCON.4 (ISA) - Increment Source Address - When
routinethat mathematicallymanipulatesa valuedepen- m the sourceaddressregistersare automaticallyincre-
dent on the incomingdata. The purpme is to identify mented during each transfer. When cleared, the source
whena frame haa been receivedin error. address registersare not incremented.

CRCE- CRCError, see RSTAT. DCON.5(SAS)- SourceAddressSpace- WhenW6the

source of data for the DMA transfers is internal data
CSMA/CD - Stands for Carrier sen% Multiple Ac- memoryifautoincrementis also set. Ifautoincrernentis
cess,with CollisionDetection. not set but SASis, then the source for data will be one
of the SpecialFunctionRegisters.WhenSASis cleared,
CT - CRC Type, see GMOD. the source for data is external data memory.

DARLO/1(OC2H,OD2H)- DestinationAddressReg- DCON.6 (IDA) - Increment Destination Address

ister Low0/1 - Containsthe lowerbyte of the destina- Space - When set, destinationaddress registemare in-
tions’addreaswhen performingDMA trsnsfers. cremented once after each byte is transferred. Where
cleared, the destinationaddress registers are not auto-
DARHO/1(OC3H,OD3H)- DestinationAddressReg- maticallyincremented.
ister Low0/1 - Containsthe upper byte of the destina-
tions’addrcaswhen performingDMA transfers.

7-64
in~. 83C152 HARDWARE DESCRIPTION

DCON.7 (DAS) - Destination Address Space - When GMOD (84H)

set, destinationof data to k-etransferred is internal data 7 6543210
memoryifautoincrementmodeis also set. If autoincre-
ment is not set the dcstinationwillbe one of the Special XTCLK Ml MO AL CT PL1 PLO PR
Function Registers.WhenDAS is cleared then the des-
tination is externaldata memory. The bits in this SFR,performmost of the configuration
on the type of &ta transfers to be used with the GSC.
DCR - DeterministicResolution,see MYSLOT. -mines the mode,address length, preamblelength
protocol select,and enablesthe external clockingof the
DEN - An akernate fiction of one of the pml 1 pins transmit data.
(P1.2). Its purpose is to enable external drivers when
the GSC is transmitting data. This function is always GMOD.O(PR) - Protocol-If set, SDLCprotocolswith
active when usingthe GSC and if PI.2 is programmed NRZI encoding,zero bit insertion, and SDLCflagsare
to a 1. used. If cleared,CSMA/CD link accesswith Manches-
ter encodingis used.
DM - DMA Mock see DCONO.
GMOD.1,2(PLO,l)- Preamblelength
DMA - Direct Memory Accessmodq see TSTAT.
PL1 PLOLENGTH (BITS)
DONE - DMA donebit, see DCONO. 000
018
DPH - Data Pointer High, sn SFR that contains the 1 0 32
high order byte of a generalpurpose pointer called the 1164
data pointer (DPTR).
The length includesthe two bit BeginOf frsme (BOF)
DPL - Data PointerLow,an SFR that containsthe low flag in CSMA/CDbut doesnot includethe SDLCflag.
order byte of the data pointer. In SDLCmode,the BOF is an SDLCtlag, otherwiseit
is two consecutiveones. Zero length is not compatible
EDMAO - Enable DMA Channel O interrupt, see in CSMA/CD mode.
IEN1.
GMOD.3(CT)- CRCType-If set, 32-bitAUTODIN-
EDMA1 - Enable DMA channel 1 interrupL see 11-32is used. If cleared, 16-bitCRC-CCITTis used.
IEN1.
GMOD.4 (AL) - Address Length - If set, 16-bit ad-
EGSRE - Enable GSC Receive Error interrupt, see &easingis used. If cleared, 8-bit addressingis used. In
IEN1. 8-bitmock a match with any of the 4 addressregistera
will allow that frame to be accepted (ADRO,ADR1,
EGSRV - Enable GSC Receive Valid interrupt, see ADR2, ADR3). “Don’t Care” bita may be masked in
IEN1. ADROand ADR1 with AMSKOand AMSK1.In 16-
bit mode, addresses are matched a-t
EGSTE - Enable GSC Transmit Error interrupGsee “ADR1:ADRO” or “ADR3:ADR2”. Again, “Don’t
IEN1. Care” bits in ADR1:ADROcan be maskedin AM-
SK1:AMSKO.A received address of all ones will al-
EGSTV - Enable GSC Transmit Valid interrupt, see ways be recognizedin any mode.
IEN1.
GMOD.5, 6 (MO,M1)- Mode Select- TWOtest modes.
EOF - A generalterm used in serial communications. an optional “alternate backotT’mode,or normal back-
EOF stands for End Of Frame and signitieswhen the off can be enabledwith these two bits.
ttedwhenusing
Isst bits ofdataaretransmi Packetized
data. Ml MO Mode
o 0 Normal
ES- EnableLSCSeMce interrupt, see IE. o 1 RswTransmit
1 0 RawReceive
ETO- EnableTimer Ointerrupt, see IE. 1 1 AlternateBackoff
ET1 - EnableTimer 1 interrupL see IE. GMOD.7 (XTCLK)- External Transmit Clock-If set
an external 1X clock is used for the transmitter. If
EXO- EnableExternal interrupt O,see IE. cleared the internal baud rate generator provides the
EXl - EnableExternal interrupt 1, see IE.

7-65
i@. 83C152 HARDWARE DESCRIPTION

transmit clock. The input clock is applied to P1.3 IE.2 (EM) - Enables the external interrupt INTI on
(T=). The user software ia responsiblefor setting or P3.3.
clearing this flag. Extemrd receiveclock is enabledby
setting PCON.3. IE.3 (ETl) - Enablesthe Timer 1 interrupt.

GO - DMA Go bi~ ace DCONO. 333.4(ES) - Enablesthe LocalSerialChannel intemrpt.

GRxD - GSCReceiveData input, an alternate function IE.7 (EA) - The global interrupt enable bit. This bit
of one of the port 1pins (PI.0). This pin is used as the must be set to a 1 for any other interrupt to be enabled.
receive input for the GSC. PLO must be programmed
to a 1 for this functionto operate. IEN1 - (OC8H)
76 5 4 3 2 1 0
GSC - GlobalSerialChannel - A high-level,multi-pro-
tccol, serial communicationcontroller added to the Ill EGSTE EDMA1 EGSTV EDMAOEGSRE EGSR
80C51BHcore to accomplish high-speedtransfers of
packetizedserialdata. Inten-upt enableregisterfor DMA and GSC interrupts.
A 1 in any bit positionenablesthat interrupt.
GTxD - GSCTransmitData output, an alternate func-
tion of one of the port 1 pins (P1.1).This pin is used as IEN1.O(EGSRV)- Enablesthe GSC valid receive in-
the transmit output for the GSC. P1.1 must be pro- terrupt.
_ed to a 1 for this functionto operate.
IEN1.1 (EGSRE) - Enablesthe GSC rweive error in-
HBAEN - Hardware Based AcknowledgeEnable see terrupt.
RSTAT.
IEN1.2 (EDMAO)- Enablesthe DMA done interrupt
HLDA - Hold Acknowledgean alternate function of for ChannelO.
one of the port 1 pins (P1.6). This pin is used to per-
form the “HOLD ACKNOWLEDGE” function for IEN1.3(EGSIT()- Enablesthe GSC valid transmit in-
DMA transfers. HLDA can bean input or an output, terrupt.
dependingon the configurationof the DMA channels.
P1.6 must be programmedto a 1 for this function to IEN1.4 (EDMA1) - Enablesthe DMA done interrupt
operate. for Chaunel 1.
HOLD - Hold, an alternate functionof one of the port lEN1.5 (BGSTE)- Enablesthe GSC transmit error in-
1 pins (P1.5).Thispin is used to perform the “HOLD” terrupt
functionfor DMA transfers. HOLD can bc an input or
an output, dependingon the configurationof the DMA IFS - (OA4H)Interframe Space,detcrmineathe number
channels. P1.5 must be programnred to a 1 for this of bit times separating transmr“ttedfi-atnesin Csw
function to operate. CD and SDLC.
IDA - IncrementDestinationAddress,see DCONO. 1P(OB8H)
IE (OA8H) 7 654 3 2 i o
7 654 3 2 1 0 Ps PTl Pxl PTO Pxo
EA I ES I ETl EX1 ETo I EXO I
Allows the user software two levels of prioritization to
be assignedto each of the interrupts in IE. A 1 assigns
Interrupt EnableSFR,usedto individuallyenable the the cmreapottdinginterrupt in IE a higher interrupt
Timer and Local Serial Channel interrupts. Also con- than an interrupt with a correspondingO.
tains the globalenablebit which muat be set to a 1 to
enable any interrupt to be automaticallyrecognizedby IP.O(PXO)- Assignsthe priority of external intermpL
the CPU. INTO.
IE.O (EXO)- Embles the external interrupt ~ on IP.1 (PTO)- Assignsthe priority of Timer Ointcrrup~
P3.2. To.
IE.1 (ETO)- Enablesthe Timer Ointerrupt.

7-66
i~. 83C152 HARDWARE DESCRIPTION

IP.2 (PXl) - Assignsthe priorityof externrdinterrupt, Determines which type of Jam is used, which backoff
INT1. algorithm is uaedj and the DCR slot address for the
GSC.
IP.3 (PT1) - Assignsthe priorityof Timer 1 interrupt,
T1. MYSLOT.0,1,2,3,4,5(SA0,1,2,3,4,5)- Thesebits deter-
mine which slot address is assignedto the C152when
IP.4 (I%) - Assignsthe priority of the LSC interrupt, using deterrninistic backoffduring CSMA/CD opera-
SBUF. tions on the GSC. Maximumslots available is 63. h
addreasof OOHpreventsthat stationfrom participating
IPN1 - (OF8~ in the backoffprocess.
76 5 4 3 2 1 0
I PGSTE I PDMA1 ] PGSTV I PDMAO I PG.SF4EI PGSRV ] MYSLOT.6(DCR) - Determineswhich collisionreso-
lution algorithmis used. If set to a 1, then the determi-
Allowsthe user software two lewelsof prioritization to nistic backoff is used. If cleared, then a random slot
be assignedto each of the interrupts in IEN1. A 1 as- assignmentis used.
signsthe correspondinginterrupt in IEN1 a higher in-
terrupt than an interrupt with a correspondingO. MYSLOT.7(DCJ) - Determinesthe type of Jam used
during CSMA/CD operationwhen a collisionoccurs.
IPN1.O(PGSRV)- Assignsthe priority of GSC receive If set to a 1 then a low D.C. level is used as the jam
valid interrupt. signal. If cleare& then CRC is used as the jam signal.
The jam is applied for a length of time equal to the
IPN1.1 (PGSRE) - Assignsthe priority of GSC error CRC length.
receiveinterrupt.
NOACK -No Acknowledgmenterror bit, seeTSTAT.
IPN1.2 (PDMAO)- Assignsthe priority of DMA done
interrupt for ChannelO. NRZI - Non-Return to Zero inverted, a type of data
encodingwhere a O is representedby a change in the
IPN1.3 (PGSTV)- Assignsthe priority of GSC trans- levelof the serial link. A 1is representedby no change.
mit valid interrupt.
OVR - @mrtlm error bit, see RSTAT.
IPN1.4 (PDMA1)- Assignsthe priority of DMA done
interrupt for Channel 1. PR - Protocolselectbit, seeGMOD.PCON (87H)
7654 3 2 10
IPN1.5 (PGSTE) - Assignsthe priority of GSC trans-
mit error interrupt. SMODIARBI REQIGARENIXRCLK GFIEN PD IDL[

ISA - Increment SourceAddr~ see DCONO. PCON.O(IDL) - Idle bit, used to place the C152into
the idle power savingmode.
LNI - Line Idle see TSTAT.
PCON.1 (PD) - Power Down bit, used to place the
LSC - Local Serial Channel- Tbe asynchronousaerial C152into the power downpowersavingmode.
port found on all MCS-51devices.Uses start/stop bits
and can transfer only 1 byte at a time. PCON.2 (GFIEN) - GSC Flag Idle Enable bit, when
set, enables idle flags (01111110)to be generated be-
MO- One of two GSC modebits, see TMOD. tween transmitted frames in SDLCmode.
Ml - One of two GSC modebits, see TMOD PCON.3 (XRCLK) - ExternalReceiveClockbit,used
to enablean externalclockto be usedfor onlythe re-
MYSLOT- (OF5H) ceiverportion of the GSC.
76543210 —
PCON.4 (GAREN) - GSC Auxiliary Receive Enable
DCJ I DCR SA5 SA4 SA3 SA2 SA1 SAO
bi~ used to enable the GSC to receive back-to-back
SDLC frames. This bit has no tied in CSMA/CD
mode.

7-67
i~. 83C152 HARDWARE DESCRIPTION

PCON.5 (REQ) - Requeatwmodebi~ set to a 1 when RI - LSC ReeeiveInterrupt bit, see SCON.
C152 is to be operated as the requester station during
DMA transfers. RFIFO - (F4H) RFIFO is a 3-byteFIFO that contains
the receivedata from the GSC.
PCON.6 (ARB) - Arbiter mode biL set to a 1 when
C152 is to be operated as the arbiter during DMA RSTAT(OE8H)- ReceiveStatusRegister
transfers. 7654321 0
PCON.7 (SMOD)- LSCmodebiL used to doublethe IOVRIRCABTIAEICRCEIRDNIRFNEIGRENIHABENI
baud rate on the LSC.
RSTAT.O(HBAEN) - Hardware BasedAcknowledge
PDMAO- Priority bit for DMA Channel Ointerrupt, Enable - If set, enables the hardware based acknowl-
see IPN1. edgefeature.
PDMA1 - Priority bit for DMA Channel 1 interrupt, RSTAT.1(GRIN) - Receiver Enable - When set, the
see IPN1. receiveris enabledto accept incomingthsnea. The user
must clear RFIFO with sotlware before enabling the
PGSRE - Priority bit for GSCReceiveError interrupt, receiver.RFIFO is cleared by readingthe contents of
see IPN1. RFIFO until RFNE = O.After each read of RFIFO, it
takes one machinecycle for the status of RFNE to be
PGSRV- Priority bit for GSCReceiveValidinterrupt, uxted. setting GREN dSO CkUS RDN, CRCE, AE,
see IPN1. and RCABT.GREN is cleared by hardwareat the end
of a receptionor if any receiveerrors are detected. The
PGSTE - Priority bit for GSC Transmit Error inter- status of GREN has no effect on whetherthe receiver
rupt, see IPN1. detects a collisionin CSMA/CD modeas the receiver
input circuitry alwaysmonitors the reeeivepin.
PGSTV - Priority bit for GSC Transmit Valid inter-
rupt, see IPN1. RSTAT.2(RFNE) - ReceiveFIFO Not Empty - If set,
indicatesthat the ree.eiveFIFO containsdata. The re-
PLO- One of two bits that determines the Preamble ceiveFIFO is a three byte buffer into whichthe receive
Length, see GMOD. data is loaded.A CPU read of the FIFO retrieves the
oldest data and automaticallyupdatesthe FIFO point-
PL1 - One of two bits that determhes the Preamble ers. SettingGREN to a one willclear the receiveFIFO.
Length, see GMOD. The status ofthis fig is ccmtrolledbythe GSC.This bit
is cleared if user softwareempties receiveFIFO.
PRBS- (OE4H)Pseudo-RandomBinary Sequence,gen-
erates the pseudo-random number to be used in RSTAT.3(RDN) - ReceiveDone -If set, indicatesthe
CSMA/CD backoffalgorithms. succeastidcompletionof a receiveroperation.Will not
be set if a CRC, alignment, abort, or FIFO overrun
PS - Priority bit for the LSCserviceinterrupt see 1P. error occurred.
PTO- Priority bit for Timer Ointerrupt, see 1P. RSTAT.4(CRCE)- CRC Error - Ifs@ indicatesthat a
properlyalignedframe was receivedwitha mismatched
PTl - Priority bit for Timer 1 interrupt, see 1P. CRC.
PXO- Priority bit for External interrupt O, see 1P. RSTAT.5 (AE) - Alignment Error - In CSMA/CD
mode,AE is set if the receivershift register(an internal
PX1 - Priority bit for Externatinterrupt 1, see 1P. serial-to-parallelconverter) is not full and the CRC is
bad whenan EOF is detected. In C?WfA/CDthe EOF
RCABT - GSC ReceiverAbort error bit, see RSTAT. is a line idle condition(see LNI) for two bit times. If
the CRC is correct while in CSMA/CD mode, AE is
RDN - GSC ReceiverDonebi~ see RSTAT. not set and any rnia-alignmentis assumedto be caused
by dribble bits as the line went idIe. In SDLC mode,
GREN - GSC ReceiverEnablebi~ see RSTAT. AE is set if a non-byte-alignedflag is received.CRCE
may also be set. The setting of this flagis controlledby
RFNE - GSC Receive FIFO Not Empty bit, see the GSC.
RSTAT.

7-68
i~e 83C152 HARDWARE DESCRIPTION

RSTAT.6(RCAB~ - ReceiverCollision/AbortDetect SCON.7(SM2)- LSC mode speciiier.

- IfseL indicatesthat a collisionwasdetectedafter data
had been 10wM into the receiveFIFO in CSMA/CD SDLC- Standsfor SynchronousData Link Cmmmni-
mode.In SDLCmodq RCABTindicatesthat 7 consec- cation and is a protocol developedby IBM.
utive oneswere detected prior to the end tlag but after
data has keen loaded into the receiveFIFO. AE may SLOTTM- (OB4H)Determines the length of the slot
also be set if RCABT is set. time in CSMA/CD.

RSTAT.7(OVR) - Overrun - If set, indicatesthat the SP (081H)- Stack Pointer, an eight bit pointer register
receiveFIFO was full and new shift register data was used duringa PUSN POP, CALL, RET, or RETL
written into it. It is cleared by user software, AE
and/or CRCE may also be set ifOVR is set. TCDCNT - (OD4H)Contains the numberof collisions
in the currcnt frame if using probabilisticCSMA/CD
SARHO(OA3H)- Source Addreas Register High O, and containsthe maximum number of slots in the de-
containsthe high byte of the source address for DMA terministicmode.
ChannelO.
TCDT - Transmit CollisionDetec~ see TSTAT.
SARHI (OB3H)- Source Address Register High 1,
containsthe high byte of the sourceaddress for DMA TCON (088H)
channel 1. 76543210
SARLO(OA2H)- SourceAddressRegisterLowO,con- TF1 TR1 TFo TRO IE1 IT1 IEO ITO
tains the low byte of the source address for DMA
ChannelO. TCON.O(ITO)- Interrupt Omode controlbit.
SARLI (OB2H)- SourceAddressRegisterLow 1,con- TCON.1(IEO)- External interrupt Oedgetlag.
tains the low byte of the source address for DMA
channel 1. TCON.2(ITl) - Interrupt 1 mode controlbit.
SAS- SourceAddress Spacebit, see DCONO. TCON.3(IEl) - External interrupt 1 edgeflag.
SBUF (099H) - Serial Buffer, both the receive and TCON.4(TRO)- Timer Orun control bit.
transmit SFR location for the LSC.
CON.5(TFO)- Timer Oovertlowflag.
SCON(098H)
7 6 5 4 3210 TCON.6(TR1) - Timer 1 run control bit.
SMO SM1 SM2 REN TB8 \ RB8 TI I RI
TCON.7(TF1) - Timer 1 over-tlowflag.

SCON.O(RI) - ReceiveInterrupt fiag. TDN - Transmit Done flag, w TSTAT.

SCON.1(TI) - Transmit Interrupt tlag. TEN - Transmit Enable bit, see TSTAT.

SCON.2(RB8) - ReceiveBit 8, containsthe ninth bit TFNF - Transmit FIFO Not Full tlag, see TSTAT.
that was receivedin Modes 2 and 3 or the stop bit in
Mode 1 if SM20.Not used in ModeO. TFIFO - (85H) TFIFO is a 3-byteFIFO that contains
the transmissiondata for the GSC.
SCON.3 (TB8) - Trrmsmit Bit 8, the ninth bit to be
transmitted in Modes 2 and 3. THO(08CH) - Timer O High byte contains the high
byte for timer/cmmter O.
SCON.4 (REm - Receiver Enable, enables reception
for the I-SC.

SCON.5(SM2)- Enablesthe multiprocessorcommuni-

cation feature in Modes 2 and 3 for the LSC.

SCON.6(SM1)- LSC mcde sptxirler.

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i~o 83C152 HARDWARE DESCRIPTION

THl (08DH) - Timer 1 High byte, containsthe high tera su ccesafd transmiasiottj a collision during the
byte for timer/counter 1. da~ CRC, or end tlag. Ifclmred during a transmission
the GSC transmit pin goesto a steady state high level.
TI - Transxm
“tInterrup~ see SCON. This is the method used to send an abort chamcter in
SDLC.Also ~ is forcedto a high level.The end of
TLO(08AH)- Timer OLowbyte, containsthe low byte transmissionowurs wheneverthe TFIFO is emptied.
for timer/counter O.
TSTAT.2(TFNF) - Transmit FIFO not Ml - When
TL1 (08BH)- Timer 1 Lowbyte, containsthe low byte se~ indicates that new data may be written into the
for timer/counter 1. transmit FIFO. The transmit FIFO is a three bytebuff-
er that loads the transmit shift register with data.
TM - Transfer Mod%see, DCONO.
TSTAT.3(TDN) - Tranamit Done - When set, indi-
TMOD (089H) catesthe successfulwmpletionof a frame transmission.
76543210 If HBAENis set, TDN will not be set until the end of
the IFS followingthe transmitted message,so that the
GATE c/7 Ml MO GATE c/T Ml MO acknowledgecan be checked.If an acknowledgeis ex-
pected and not rewiv~ TDN is not set. An acknowl-
TMOD.O(MO)- Mode selector bit for Timer O. edgeis not expectedfollowinga broadcast or multi-cast
packet.
TMOD.1 (Ml) - Mode selector bit for Timer O.
TSTAT.4(TCDT) - Transmit CollisionDetect -If set,
TMOD.2 (Cm - Timer/Counter s.dectorbit for indicatesthat the transmitter halted due to a collision.
Timer O. It is set ifa collisionoccurs during the data or CRC or
if there are more than eight wlliaions.
TMOD.3 (GATE) - Gating Modebit for Timer O.
T3TAT.5 (tJR) - Underrun - If set, indicates that in
TMOD.4 (MO)- Mode selector bit for Timer 1. DMA modethe last bit was SW out of the transmit
:~~w~ad t$~t=m byte count did not equrd
TMOD.5(Ml) - Mode selector bit for Timer 1. owurs, the transrm“tterhalts
without sendingthe CRC or the end flag.
TMOD.6 (Cfi) - Timer/Counter selectorbit for
Timer 1. T3TAT.6(NOACK) - No Ackllow]edge- If set, indi-
catesthat no acknowledgewasreceivedfor the previous
TMOD.7(GATE) - Gating Mode bit for Timer 1. frame. Will be set only if HBAEN is set and no ac-
knowledgeis received prior to the end of the IFS.
TSTAT(OD8)- Transmit StatusRegister NOACK is not set followinga broadcast or a madti-
cast packet.
76543210
LNI NOACK UR TCDT TDN TFNF TEN DMA TSTAT.7(I-M) - Line Idle - If seG indicates the re-
ceiveline is idle. In SDLCprotocolit is set if 15consec-
utive ones are received. In C3MA/CD protocol, line
TSTAT.O(DMA) - DMA Selwt - IfseL indicates that idleis set ifGRx D remainshigh for approximately1.6
DMA channelsare used to semioethe GSCFIFO’s and bit times. LNI is cleared after a transition on GRx D.
GSC interrupta occur on TDN and RDN, and also en-
ables UR to become set. If cleared, indicatesthat the TxC - External Clockinput for GSC transmitter.
GSC is operatingin it normal modeand interrupts oc-
cur on TFNE and RFNE.For more information on UR - Underrun flag, see TSTAT.
DMA servicing please refer to the DMA section on
DMA serial demand mode (4.2.2.3). XRCLK - External GSCReceiveClock Enablebi~ see
PCON.
TSTAT.1~N) - Transmit Enable - Whenset causes
TDN, w TCDT, and NOACK tlags to be reset and XTCLK - Extermd GSC Transmit Clock Enable bit,
the TFIFO cleared.l%e transmitter willclear TEN af- see GMOD.

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