Data Communication Lab
Data Communication Lab
Unipolar encoding is a line code. A positive voltage represents a binary 1, and zero
volts indicates a binary 0. It is the simplest line code, directly encoding the bit
stream, and is analogous to on-off keying in modulation.
Its drawbacks are that it is not self-clocking and it has a significant DC component,
which can be halved by using return-to-zero, where the signal returns to zero in the
middle of the bit period. With a 50% duty cycle each rectangular pulse is only at a
positive voltage for half of the bit period. This is ideal if one symbol is sent much
more often than the other and power considerations are necessary, and also makes
the signal self-clocking.
DIFFERENTIAL MANCHESTER
In Manchester Encoding scheme, two signal changes represent 0 and one signal
change repress. This encoding scheme is a combination of RZ and NRZ-I. It also
transit at the middle of the bit but changes phase only when 1 is encountered.
It changes the signal at the middle of the bit interval for synchronization, but the
presence or absence of the transition at the beginning of the interval determines the
bit. A transition means binary 0 and no transition means binary 1. There is still a
transition in the middle of each bit time, but there is only a transition at the start of a
bit time if the bit will be a logic high (binary one). There is no transition at the start of
the bit time if the bit will be a logic low (binary zero). It is the presence or absence of
a transition at the beginning of a bit time that signifies what logic state the bit
represents. Neither the direction of the transition nor the actual voltage level on the
line during the bit time have any significance in this respect. This means, effectively,
that if the signal gets inverted, it still represents the same bit pattern.
Matlab code for Differential Manchester
clc;
clear;
x=[0 1 0 1 0 0 0 1 1 0 1 1 0 0 0 1];
T=length(x);
n=100;
N=2*n*T;
dt=T/N;
pulse=-1;
t=0:dt:T;
y=zeros(1,length(t));
for i=0:(T-1);
if x(i+1)==1
if pulse==1
pulse=-1;
y(i*2*n+1 : (2*i+1)*n)=-1*pulse;
y((2*i+1)*n+1 : (2*i+2)*n)=pulse;
else
pulse=1;
y(i*2*n+1 : (2*i+1)*n)=-1*pulse;
y((2*i+1)*n+1 : (2*i+2)*n)=pulse;
end;
end;
end;
plot(t,y);
axis([0 t(end) -2 2]);
grid on;
title('differential Manchester');
Output of Differential Manchester
Because transitions only occur when a logic high is to be transmitted, MLT-3 has a
relatively low bandwidth requirement. The worst-case scenario from a bandwidth
perspective would be a long sequence of binary ones, which would cause the signal
to make one complete cycle (+0-0 or -0+0) in the space of four bits, as shown below.