Datasheet
Datasheet
Datasheet
U
FEATURES DESCRIPTIO
■ Generates Three Voltages: The LTC®3450 is a complete power converter solution for
5.1V at 10mA small thin film transistor (TFT) liquid crystal display (LCD)
– 5V, –10V, or –15V at 500µA panels. The device operates from a single Lithium-Ion cell,
10V or 15V at 500µA 2- to 3-cell alkaline input or any voltage source between
■ Better than 90% Efficiency 1.5V and 4.6V.
■ Low Output Ripple: Less than 5mVP-P The synchronous boost converter generates a low noise,
■ Complete 1mm Component Profile Solution high efficiency 5.1V, 10mA supply. Internal charge pumps
■ Controlled Power-Up Sequence: AVDD/VGL/VGH
are used to generate 10V, 15V, and –5V, –10V or –15V.
■ All Outputs Disconnected and Actively Discharged in
Output sequencing is controlled internally to insure proper
Shutdown
■
initialization of the LCD panel.
Low Noise Fixed Frequency Operation
■ Frequency Reduction Input for High Efficiency in A master shutdown input reduces quiescent current to
Blank Mode <2µA and quickly discharges each output for rapid turn off
■ Ultralow Quiescent Current: 75µA (Typ) in Scan Mode of the LCD panel. The LTC3450 is offered in a low profile
■ Available in a 3mm × 3mm 16-Pin QFN Package (0.75mm), 3mm × 3mm 16-pin QFN package, minimizing
the solution profile and footprint.
U , LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
5.1V, –10V, 15V Triple Output TFT-LCD Supply
VIN 47µH AVDD Efficiency vs VIN
AVDD
1.5V TO 5.1V/10mA
4.6V 8 7 100
2.2µF 2.2µF
SW VOUT 5mA LOAD
6 11
VIN C1 +
0.1µF 95
– 10
C1
100µH
4 12
BLANK SCAN MODE V2X 90
EFFICIENCY (%)
14 0.47µF 47µH
LTC3450 C2 +
5 13 0.1µF 85
OFF ON SHDN C2 –
15 VGH (3 × AVDD)
V3X 80
15V/500µA
9 16
GND VINV
VNEG C3 – C3 + 0.1µF 75
3 2 1
70
0.1µF 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.1µF
VIN (V)
VGL 3450 TA01b
–10V/500µA
3450 TA01
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LTC3450
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1) (Referred to GND)
TOP VIEW ORDER PART
VIN, SW.......................................................... – 0.3 to 7V NUMBER
VINV
V3X
C2+
C2–
SHDN, MODE ................................................. – 0.3 to 7V 16 15 14 13
VOUT .......................................................................... – 0.3 to 5.5V C3+ 1 12 V2X LTC3450EUD
– +
VNEG ........................................................................ –17V to 0.3V C3 2
17
11 C1
VNEG 3 10 C1–
Operating Temperature Range MODE 4 9 GND
LTC3450E (Note 4) ............................. – 40°C to 85°C 5 6 7 8
UD PART MARKING
Storage Temperature Range ................. – 65°C to 125°C
SHDN
VIN
VOUT
SW
LAAC
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
EXPOSED PAD IS VNEG (PIN 17)
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 68°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VOUT = 5.2V unless otherwise noted.
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LTC3450
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, VOUT = 5.2V unless otherwise noted.
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 3: Measured from point at which VNEG crosses –5V to point at which
of a device may be impaired. C2– starts switching.
Note 2: Specification is guaranteed by design and not 100% tested in Note 4: The LTC3450E is guaranteed to meet performance specifications
production. from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
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LTC3450
U W
TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C unless otherwise noted)
5mA
90
EFFICIENCY (%)
90
EFFICIENCY (%)
5mA
2mA
85 85
2mA
80 80
75 75
70 70
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VIN (V) VIN (V)
3450 G02 3450 G03
No Load VIN Current in Blank Mode No Load VIN Current in Scan Mode AVDD vs VIN and Load
100 800 5.16
90
700 5.14
80
600 0mA
70
VIN CURRENT (µA)
VIN CURRENT (µA)
5.12
2mA
60
AVDD (V)
500
50 5.10
400 5mA
40
5.08
30 300
10mA
20
200 5.06
10
0 100 5.04
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VIN (V) VIN (V) VIN (V)
3450 G04 3450 G05 3450 G06
AVDD vs Temperature
VGH vs Load VGL vs Load Figure 1 Circuit, 1mA Load
15.6 – 9.0 5.200
– 9.2 5.175
15.4
5.150
– 9.4
15.2
5.125
AVDD (V)
– 9.6
VGH (V)
VGL (V)
15.0 5.100
– 9.8
5.075
14.8
– 10.0
5.050
14.6 – 10.2 5.025
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LTC3450
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TYPICAL PERFOR A CE CHARACTERISTICS
AVDD Ripple Voltage
AVDD Load = 5mA AVDD Transient Response
AVDD
100mV/DIV
AVDD (AC)
5mV/DIV
(AC)
AVDD LOAD 5mA
5mA/DIV 1mA
3450 G10
VIN = 3.6V 1µs/DIV VIN = 3.6V 100µs/DIV 3450 G11
C2 = 2.2µF C2 = 2.2µF
INDUCTOR
VGH 0 CURRENT
10V/DIV 100mA/DIV
0
AVDD AVDD
5V/DIV 2V/DIV
0
VGL 0
5V/DIV
3450 G13
VIN = 3.6V 2ms/DIV 3450 G12
VIN = 3.6V 20µs/DIV
C2 = 2.2µF
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LTC3450
U U U
PI FU CTIO S
C3+ (Pin 1): Charge Pump Inverter Flying Capacitor Posi- SW (Pin 8): Switch Pin. Connect the inductor between SW
tive Node. The charge pump inverter flying capacitor is and VIN. Keep PCB trace lengths as short and wide as
connected between C3+ and C3 –. The voltage on C3+ will possible to reduce EMI and voltage overshoot. If the
alternate between GND and VINV at an approximate 50% inductor current falls to zero, the internal P-channel
duty cycle while the inverting charge pump is operating. MOSFET synchronous rectifier is turned off to prevent
Use a 10nF or larger X5R type ceramic capacitor for best reverse charging of the inductor and an internal switch
results. connects SW to VIN to reduce EMI.
C3 – (Pin 2): Charge Pump Inverter Flying Capacitor Nega- GND (Pin 9): Signal and Power Ground for the LTC3450.
tive Node. The charge pump inverter flying capacitor is Provide a short direct PCB path between GND and the
connected between C3+ and C3 –. The voltage on C3 – will output filter capacitor(s) on VOUT, V2X, V3X and VNEG.
alternate between GND and VNEG at an approximate 50% C1 – (Pin 10): Charge Pump Doubler Flying Capacitor
duty cycle while the inverting charge pump is operating.
Negative Node. The charge pump doubler flying capacitor
Use a 10nF or larger X5R type ceramic capacitor for best is connected between C1 + and C1 –. The voltage on C1– will
results.
alternate between GND and VOUT at an approximate 50%
VNEG (Pin 3): Charge Pump Inverter Output. VNEG can be duty cycle while the charge pump is operating. Use a 10nF
either – 5V or –10V depending on where VINV is con- or larger X5R type ceramic capacitor for best results.
nected. VNEG should be bypassed to GND with at 0.1µF or C1+ (Pin 11): Charge Pump Doubler Flying Capacitor
larger X5R type ceramic capacitor. VNEG can also be Positive Node. The charge pump doubler flying capacitor
configured for –15V with two external low current Schottky is connected between C1+ and C1–. The voltage on C1+ will
diodes (see Applications section).
alternate between VOUT and V2X at an approximate 50%
MODE (Pin 4): Drive MODE high to force the LTC3450 into duty cycle while the charge pump is operating. Use a 10nF
high power (scan) mode. Drive MODE low to force the or larger X5R type ceramic capacitor for best results.
LTC3450 into low power (blank) mode. The output volt-
V2X (Pin 12): Charge Pump Doubler Output. This output
ages remain active with the MODE pin driven low but with
is 10.2V (nom) at no load and is capable of delivering up
reduced output current capability. MODE must be pulled to 500µA to a load. V2X should be bypassed to GND with
up to VIN or higher on initial application of power in order
a 0.47µF X5R type ceramic capacitor.
for proper initialization to occur.
C2 – (Pin 13): Charge Pump Tripler Flying Capacitor Nega-
SHDN (Pin 5): Master Shutdown Input for the LTC3450. tive Node. The charge pump tripler flying capacitor is
Driving SHDN low disables all IC functions and reduces connected between C2 + and C2 –. The voltage on C2 – will
quiescent current from the battery to less than 2µA. Each alternate between GND and VOUT at an approximate 50%
generated output voltage is actively discharged to GND in duty cycle while the charge pump is operating. Use a 10nF
shutdown through internal pull down devices. An optional
or larger X5R type ceramic capacitor for best results.
RC network on SHDN provides a slower ramp up of the
boost converter inductor current during startup (soft-start). C2 + (Pin 14): Charge Pump Tripler Flying Capacitor Posi-
tive Node. The charge pump tripler flying capacitor is
VIN (Pin 6): Input Supply to the LTC3450. Connect VIN to
connected between C2 + and C2 –. The voltage on C2 + will
a voltage source between 1.5V and 4.6V. Bypass VIN to alternate between V2X and V3X at an approximate 50%
GND with a 2.2µF X5R ceramic capacitor. duty cycle while the charge pump is operating. Use a 10nF
VOUT (Pin 7): Main 5.1V Output of the Boost Regulator and or larger X5R type ceramic capacitor for best results.
Input to the Voltage Doubler Stage. Bypass VOUT with a low
ESR, ESL ceramic capacitor (X5R type) between 2.2µF and
10µF.
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LTC3450
U U U
PI FU CTIO S
V3X (Pin 15): Charge Pump Tripler Output. This output is Connecting VINV to 5V or 10V will generate –5V or –10V
15.3V (nom) at no load and is capable of delivering up to respectively on VNEG. See Applications section for –15V
500µA to a load. V3X should be bypassed to GND with a generation.
0.1µF X5R type ceramic capacitor. Exposed Pad (Pin 17): The exposed pad must be con-
VINV (Pin 16): Positive Voltage Input for the Charge Pump nected to VNEG (Pin 3) on the PCB. Do not connect the
Inverter. The charge pump inverter will generate a nega- exposed pad to GND.
tive voltage corresponding to the voltage applied to VINV.
W
BLOCK DIAGRA
L1
VIN 47µH
AVDD
1.5V TO 5.1V/10mA
4.6V SW VOUT C2
8 7
C1 2.2µF
2.2µF
VIN SYNCHRONOUS
SHUTDOWN
6 PWM BOOST C1+
CONVERTER CHARGE PUMP 11 CF1
DOUBLER C1– 0.1µF
IN 10
V2X
OUT 12 10V
C7
OSCILLATOR SHUTDOWN 1µF
550kHz
MODE
69kHz C2 +
BLANK SCAN 4 CHARGE PUMP 14 CF2
TRIPLER C2 – 0.1µF
IN 13
SHDN V3X VGH (3 × AVDD)
OFF ON 5 GLOBAL SHUTDOWN OUT 15
15V/500µA
C8
SHUTDOWN 0.47µF
VINV
16
C3 +
CHARGE PUMP 1 CF3
INVERTER C3 – 0.1µF
IN 2
VNEG VGL
OUT 3 –10V/500µA
C11
SHUTDOWN 0.47µF
3450 TA01
9
GND
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LTC3450
U
OPERATIO
The LTC3450 is a highly integrated power converter in- boost converter further reduces its quiescent current in
tended for small TFT-LCD display modules. A fixed fre- this mode, delivering both lower input (battery) current
quency, synchronous PWM boost regulator generates a drain and low noise operation.
low noise 5.1V, 10mA bias at greater than 90% efficiency
from an input voltage of 1.5V to 4.6V. Three charge pump Charge Pumps
converters use the 5.1V output to generate 10V, 15V and The LTC3450 includes three separate charge pump con-
–5V, –10V or –15V at load currents up to 500µA. Each verters which generate 10V, 15V and either –5V, –10V or
converter is frequency synchronized to the main 550kHz –15V. Each output can deliver a maximum of 500µA. The
(nominal) boost converter. The generated output voltages charge pumps feature fixed frequency, open-loop opera-
are internally sequenced to insure proper initialization of tion for high efficiency and lowest noise performance. The
the LCD panel. A digital shutdown input rapidly discharges charge pump converters operate at 1/8 the boost con-
each generated output voltage to provide a near instanta- verter frequency and include internal charge transfer
neous turn-off of the LCD display. switches. Thus, each charge pump requires only two small
external capacitors, one to transfer charge, and one for
Boost Converter
filtering. Similar to the boost converter, the charge pumps
The synchronous boost converter utilizes current mode operating frequency reduces to approximately 4kHz in
control and includes internally set control loop and slope blank mode, maintaining low noise operation but at re-
compensation for optimized performance and simple de- duced output current capability.
sign. Only three external components are required to
complete the design of the 5.1V, 10mA boost converter. Output Sequencing
The high operation frequency produces very low output Refer to the following text and Figure 1 for the LTC3450
ripple and allows the use of small low profile inductors and power-up sequence. When input power is applied, the
tiny external ceramic capacitors. The boost converter also boost converter initializes and charges its output towards
disconnects its output from VIN during shutdown to avoid the final value of 5.1V. When the boost converter output
loading the input power source. Softstart produces a reaches approximately 90% of its final value (4.5V), an
controlled ramp of the converter input current during internal 5V OK signal is asserted which allows the charge
startup, reducing the burden on the input power source. pump doubler to begin operation toward its final goal of
Very low operating quiescent current and synchronous 10V. Approximately 1ms later, the charge pump inverter
operation allow for greater than 90% conversion effi- begins operation toward its final goal of either
ciency. –5V or –10V depending on the connection of the VINV
The MODE input reduces the boost converter operating input. When the –5V or –10V output (VNEG) reaches
frequency by approximately 8x when driven high and approximately 50% of its final value, a 4ms (nominal)
reduces the output power capability of the boost con- timeout period begins. At the conclusion of the 4ms
verter. MODE is asserted when the polysilicon TFT-LCD timeout period, the charge pump tripler is allowed to
display is in its extremely low power blank condition. The begin operation, which will eventually charge V3X to 15V
(nominal).
V3X
15V V2X
10V VOUT
5V
VNEG
–10V 1ms
4ms
3450 F01
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LTC3450
U U W U
APPLICATIO S I FOR ATIO
Inductor Selection Soft-Start
Inductors in the range of 47µH to 100µH with saturation Soft-start operation provides a gradual increase in the
current (ISAT) ratings of at least 150mA are recommended current drawn from the input power source (usually a
for use with the LTC3450. Ferrite core materials are battery) during initial startup of the LTC3450, eliminating
strongly recommended for their superior high frequency the inrush current which is typical in most boost convert-
performance characteristics. A bobbin or toroid type core ers. This reduces stress on the input power source, boost
will reduce radiated noise. Inductors meeting these re- inductor and output capacitor, reduces voltage sag on the
quirements are listed in Table 1. battery and increases battery life. The rate at which the
Table 1. Recommended Inductors input current will increase is set by two external compo-
PART L MAX DCR HEIGHT nents (RSS and CSS) connected to SHDN (refer to Figure
NUMBER (µH) (Ω) (mm) VENDOR 2). Upon initial application of power or release of a pull
CLQ4D10-470 47 1.28 1.2 Sumida down switch on SHDN, the voltage on SHDN will increase
CLQ4D10-101 100 3.15 (847) 956-0666
CMD4D08-470 47 1.6 1.0 www.sumida.com
relative to the R • C time constant or RSS • CSS. After one
DO1606-473 47 1.1 2.0 Coilcraft
time constant SHDN will rise to approximately 63.2% of
DO1606-104 100 2.3 (847) 639-6400 the voltage on VIN. From 0V to approximately 0.77V on
DT1608-473 47 0.34 2.92 www.coilcraft.com SHDN, no switching will occur because the shutdown
DT1608-104 100 1.1
threshold is 0.77V (typ). From 0.77V to 1V the maximum
LQH43MN470J03 47 1.5 2.6 Murata switch pin current capability of the LTC3450 will gradually
LQH43MN101J03 100 2.5 www.murata.com
increase from near zero to the maximum current limit. An
DU6629-470M 47 0.64 2.92 Coev Magnetics
DU6629-101M 100 1.27 www.circuitprotection.com RSS in the range of 1MΩ to 10MΩ is recommended. If
SHDN is driven high with a logic signal, the input current
will gradually increase to its maximum value in approxi-
Capacitor Selection mately 50µs.
The boost converter requires two capacitors. The input
capacitor should be an X5R type of at least 1µF. The VOUT VIN
capacitor should also be an X5R type between 2.2µF and RSS
1M
10µF. A larger capacitor (10µF) should be used if lower 5%
output ripple is desired or the output load required is close 5 SHDN
CSS
to the 10mA maximum. 6.8nF
The charge pumps require flying capacitors of at least 1ms SOFT-START WITH 3.6V VIN
0.1µF to obtain specified performance. Ceramic X5R types 3450 F02
are strongly recommended for their low ESR and ESL and Figure 2. Soft-Start Component Configuration
capacitance versus bias voltage stability. The filter capaci-
tor on V2X should be at least 0.1µF. A 0.47µF or larger Printed Circuit Board Layout Guidelines
capacitor on V2X is recommended if VINV is connected to
V2X. The filter capacitors on V3X and VNEG should be High speed operation of the LTC3450 demands careful
0.1µF or larger. Please be certain that the capacitors used attention to PCB layout. You will not get advertised perfor-
are rated for the maximum voltage with adequate safety mance with careless layout. Figure 3 shows the recom-
margin. Refer to Table 2 for a listing of capacitor vendors. mended component placement for a single layer PCB. A
Table 2. Capacitor Vendor Information multilayer board with a separate ground plane is ideal but
Supplier Phone Website
not absolutely necessary.
AVX (803) 448-9411 www.avxcorp.com
Murata (714) 852-2001 www.murata.com
Taiyo Yuden (408) 573-4150 www.t-yuden.com
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LTC3450
U U W U
APPLICATIO S I FOR ATIO
V3X
JUMPER
VNEG
MODE
SHDN
VOUT
VIN GND
NOTE: QFN PACKAGE EXPOSED PAD
IS CONNECTED TO THE VNEG PIN.
DO NOT CONNECT EXPOSED PAD TO GROUND 3450 F03
U
TYPICAL APPLICATIO
5.1V, –15V, 15V Triple Output TFT-LCD Supply
L1
VIN 47µH
AVDD
1.5V TO 5.1V/10mA
4.6V C1 8 7 C2
2.2µF SW VOUT 2.2µF
6 11
VIN C1 + CF1
10 0.1µF
C1 –
4 12
BLANK SCAN MODE V2X
C4
14
LTC3450 C2 + CF2
0.47µF
5 13 0.1µF
OFF ON SHDN C2 – D1
15 VGH
V3X
15V/500µA
9 16
GND VINV C6
VNEG C3 – C3 + D2 0.1µF
3 2 1
0.1µF
C5
0.1µF
CF3
0.1µF
VGL
–15V/500µA 3450 TA02
D1, D2: DUAL SCHOTTKY DIODE, PANASONIC MA704WKCT
L1: SUMIDA CMD4D08-470
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LTC3450
U
PACKAGE DESCRIPTIO
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
R = 0.115
3.00 ± 0.10 0.75 ± 0.05 (4 SIDES)
TYP
(4 SIDES) 15 16
PIN 1 0.40 ± 0.10
TOP MARK
(NOTE 6) 1
1.45 ± 0.10 2
(4-SIDES)
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C5
0.1µF
CF3
0.1µF
L1: SUMIDA CMD4D08-470 VGL
–5V/500µA 3450 TA03
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