Features: Lt1375/Lt1376 1.5A, 500Khz Step-Down Switching Regulators

LT1375/LT1376
1.5A, 500kHz Step-Down

Switching Regulators
FEATURES
■ Constant 500kHz Switching Frequency is current mode for fast transient response and good loop
■ Easily Synchronizable stability. Both fixed output voltage and adjustable parts are
■ Uses All Surface Mount Components available.
■ Inductor Size Reduced to 5µH
A special high speed bipolar process and new design
■ Saturating Switch Design: 0.4Ω
techniques achieve high efficiency at high switching fre-
■ Effective Supply Current: 2.5mA
quency. Efficiency is maintained over a wide output cur-
■ Shutdown Current: 20µA
rent range by using the output to bias the circuitry and by
■ Cycle-by-Cycle Current Limiting
utilizing a supply boost capacitor to saturate the power
U switch. A shutdown signal will reduce supply current to
APPLICATIO S 20µA on both parts. The LT1375 can be externally syn-
chronized from 580kHz to 900kHz with logic level inputs.
■ Portable Computers
■ Battery-Powered Systems The LT1375/LT1376 fit into standard 8-pin PDIP and SO
■ Battery Charger packages, as well as a fused lead 16-pin SO with much
■ Distributed Power lower thermal resistance. Full cycle-by-cycle short-cir-
cuit protection and thermal shutdown are provided.
U Standard surface mount external parts are used, includ-
DESCRIPTIO ing the inductor and capacitors.
The LT ®1375/LT1376 are 500kHz monolithic buck mode
For low input voltage applications with 3.3V output, see
switching regulators. A 1.5A switch is included on the die
LT1507. This is a functionally identical part that can
along with all the necessary oscillator, control and logic
operate with input voltages between 4.5V and 12V.
circuitry. High switching frequency allows a considerable
reduction in the size of external components. The topology , LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATIO
5V Buck Converter Efficiency vs Load Current
D2 100
1N914
VOUT = 5V
VIN = 10V
C2 90 L = 10µH
0.1µF
INPUT BOOST OUTPUT**
EFFICIENCY (%)
VIN VSW
6V † TO 25V 5V, 1.25A 80
C3* + LT1376-5 BIAS
L1**
10µF TO 5µH
50µF DEFAULT SHDN FB 70
= ON GND VC C1
+ 100µF, 10V
D2
CC 1N5818 SOLID
3.3nF TANTALUM 60
* RIPPLE CURRENT ≥ IOUT/2 50

0 0.25 0.50 0.75 1.00 1.25
** INCREASE L1 TO 10µH FOR LOAD CURRENTS ABOVE 0.6A AND TO 20µH ABOVE 1A
† FOR INPUT VOLTAGE BELOW 7.5V, SOME RESTRICTIONS MAY APPLY. LOAD CURRENT (A)
SEE APPLICATIONS INFORMATION. 1375/76 TA01
1375/76 TA02
1
LT1375/LT1376
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ABSOLUTE MAXIMUM RATINGS (Note 1)
Input Voltage FB Pin Current (Adjustable Part) ............................ 1mA
LT1375/LT1376 .................................................. 25V Sense Voltage (Fixed 5V Part) .................................. 7V
LT1375HV/LT1376HV ........................................ 30V SYNC Pin Voltage ..................................................... 7V
BOOST Pin Voltage Operating Junction Temperature Range
LT1375/LT1376 .................................................. 35V LT1375C/LT1376C ............................... 0°C to 125° C
LT1375HV/LT1376HV ........................................ 40V LT1375I/LT1376I ............................. – 40°C to 125°C
SHDN Pin Voltage ..................................................... 7V Storage Temperature Range ................ – 65°C to 150°C
BIAS Pin Voltage ...................................................... 7V Lead Temperature (Soldering, 10 sec)................. 300°C
FB Pin Voltage (Adjustable Part) ............................ 3.5V
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PACKAGE/ORDER INFORMATION
TOP VIEW TOP VIEW TOP VIEW
BOOST 1 8 VC BOOST 1 8 VC GND 1 16 GND

VIN 2 7 FB/SENSE VIN 2 7 FB/SENSE NC 2 15 NC
VSW 3 6 GND VSW 3 6 GND BOOST 3 14 VC
SHDN 4 5 SYNC BIAS 4 5 SHDN VIN 4 13 FB/SENSE
VSW 5 12 GND
N8 PACKAGE S8 PACKAGE N8 PACKAGE S8 PACKAGE
8-LEAD PDIP 8-LEAD PLASTIC SO 8-LEAD PDIP 8-LEAD PLASTIC SO BIAS 6 11 SHDN
θJA = 100°C/ W (N8) θJA = 100°C/ W (N8) NC 7 10 NC
θJA = 120°C/ W TO 150°C/W DEPENDING ON θJA = 120°C/ W TO 150°C/W DEPENDING ON
PC BOARD LAYOUT (S8) PC BOARD LAYOUT (S8) GND 8 9 GND
S PACKAGE
ORDER PART NUMBER ORDER PART NUMBER 16-LEAD PLASTIC NARROW SO
θJA = 50°C/ W WITH FUSED CORNER PINS

LT1375CN8 LT1375IN8 LT1376CN8 LT1376IN8 CONNECTED TO GROUND PLANE OR LARGE
LT1375CN8-5 LT1375IN8-5 LT1376CN8-5 LT1376IN8-5 LANDS
LT1375CS8 LT1375IS8 LT1376CS8 LT1376IS8

LT1375CS8-5 LT1375IS8-5 LT1376CS8-5 LT1376IS8-5 ORDER PART NUMBER
LT1375HVCS8 LT1375HVIS8 LT1376HVCS8 LT1376HVIS8
LT1376CS
S8 PART MARKING S8 PART MARKING LT1376IS
LT1376HVCS
1375 1375I 1376 1376I LT1376HVIS
13755 1375I5 13765 1376I5
1375HV 375HVI 1376HV 376HVI
Consult factory for parts specified with wider operating temperature ranges.
2
LT1375/LT1376
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. TJ = 25°C, VIN = 15V, VC = 1.5V, boost open, switch open,
unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Voltage (Adjustable) 2.39 2.42 2.45 V
● 2.36 2.48 V
Sense Voltage (Fixed 5V) 4.94 5.0 5.06 V
● 4.90 5.10 V
Sense Pin Resistance 7 10 14 kΩ
Reference Voltage Line Regulation 5V ≤ VIN ≤ 25V 0.01 0.03 %/ V
5V ≤ VIN ≤ 30V (LT1375HV/LT1376HV) 0.01 0.03 %/V
Feedback Input Bias Current ● 0.5 1.5 µA
Error Amplifier Voltage Gain VSHDN = 1V (Notes 2, 8) 200 400
Error Amplifier Transconductance VSHDN = 1V, ∆I (VC) = ±10µA (Note 8) 1500 2000 2700 µMho
● 1100 3000 µMho
VC Pin to Switch Current Transconductance 2 A/ V
Error Amplifier Source Current VSHDN = 1V, VFB = 2.1V or VSENSE = 4.4V ● 150 225 320 µA
Error Amplifier Sink Current VSHDN = 1V, VFB = 2.7V or VSENSE = 5.6V 2 mA
VC Pin Switching Threshold Duty Cycle = 0 0.9 V
VC Pin High Clamp VSHDN = 1V 2.1 V
Switch Current Limit VC Open, VFB = 2.1V or VSENSE = 4.4V,
VBOOST = VIN + 5V DC ≤ 50% ● 1.50 2 3 A
DC = 80% ● 1.35 3 A
Switch On Resistance (Note 7) ISW = 1.5A, VBOOST = VIN + 5V 0.3 0.4 Ω
● 0.5 Ω
Maximum Switch Duty Cycle VFB = 2.1V or VSENSE = 4.4V ● 86 93 %
Switch Frequency VC Set to Give 50% Duty Cycle 460 500 540 kHz
0°C ≤ TJ ≤ 125°C 440 560 kHz
● 440 570 kHz
Switch Frequency Line Regulation 5V ≤ VIN ≤ 25V ● 0.05 0.15 %/ V
5V ≤ VIN ≤ 30V (LT1375HV/LT1376HV) ● 0.05 0.15 %/V
Frequency Shifting Threshold on FB Pin ∆f = 10kHz ● 0.8 1.0 1.3 V
Minimum Input Voltage (Note 3) ● 5.0 5.5 V
Minimum Boost Voltage (Note 4) ISW ≤ 1.5A ● 3 3.5 V
Boost Current (Note 5) VBOOST = VIN + 5V ISW = 500mA ● 12 22 mA
ISW = 1.5A ● 25 35 mA
Input Supply Current (Note 6) VBIAS = 5V ● 0.9 1.4 mA
Output Supply Current (Note 6) VBIAS = 5V ● 3.2 4.0 mA
Shutdown Supply Current VSHDN = 0V, VIN ≤ 25V, VSW = 0V, VC Open 15 50 µA
● 75 µA
VSHDN = 0V, VIN ≤ 30V, VSW = 0V, VC Open
(LT1375HV/LT1376HV) 20 75 µA
● 100 µA
Lockout Threshold VC Open ● 2.3 2.38 2.46 V
3
LT1375/LT1376
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. TJ = 25°C, VIN = 15V, VC = 1.5V, boost open, switch open,
unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Shutdown Thresholds VC Open Device Shutting Down ● 0.15 0.37 0.60 V
Device Starting Up ● 0.25 0.45 0.60 V
VC Open LT1375HV/LT1376HV Device Shutting Down ● 0.15 0.37 0.70 V
LT1375HV/LT1376HV Device Starting Up ● 0.25 0.45 0.70 V
Minimum Synchronizing Amplitude (LT1375 Only) VIN = 5V ● 1.5 2.2 V

Synchronizing Range (LT1375 Only) 580 900 kHz
SYNC Pin Input Resistance 40 kΩ
Note 1: Absolute Maximum Ratings are those values beyond which the life 5V. Total input referred supply current is calculated by summing input
of a device may be impaired. supply current (ISI) with a fraction of output supply current (ISO):
Note 2: Gain is measured with a VC swing equal to 200mV above the low ITOT = ISI + (ISO)(VOUT/VIN)(1.15)
clamp level to 200mV below the upper clamp level. With VIN = 15V, VOUT = 5V, ISI = 0.9mA, ISO = 3.6mA, ITOT = 2.28mA.
Note 3: Minimum input voltage is not measured directly, but is guaranteed For the LT1375, quiescent current is equal to:
by other tests. It is defined as the voltage where internal bias lines are still ITOT = ISI + ISO(1.15)
regulated so that the reference voltage and oscillator frequency remain
constant. Actual minimum input voltage to maintain a regulated output will because the BIAS pin is internally connected to VIN.
depend on output voltage and load current. See Applications Information. For LT1375 or BIAS open circuit, input supply current is the sum of input
Note 4: This is the minimum voltage across the boost capacitor needed to + output supply currents.
guarantee full saturation of the internal power switch. Note 7: Switch-on resistance is calculated by dividing VIN to VSW voltage
Note 5: Boost current is the current flowing into the BOOST pin with the by the forced current (1.5A). See Typical Performance Characteristics for
pin held 5V above input voltage. It flows only during switch-on time. the graph of switch voltage at other currents.
Note 6: Input supply current is the bias current drawn by the input pin Note 8: Transconductance and voltage gain refer to the internal amplifier
when the BIAS pin is held at 5V with switching disabled. Output supply exclusive of the voltage divider. To calculate gain and transconductance
current is the current drawn by the BIAS pin when the bias pin is held at refer to sense pin on fixed voltage parts. Divide values shown by the ratio
VOUT/2.42.
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TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Core Loss Switch Peak Current Limit Feedback Pin Voltage and Current
1.0 20 2.5 2.44 2.0
VOUT = 5V, VIN = 10V, IOUT = 1A 12
8 TYPICAL
2.0
CORE LOSS (% OF 5W LOAD)
SWITCH PEAK CURRENT (A)
TYPE 52 4 2.43 1.5

FEEDBACK VOLTAGE (V)
POWDERED IRON 2
0.1
CORE LOSS (W)
CURRENT (µA)
GUARANTEED MINIMUM
1.2 1.5
Kool Mµ® 0.8 VOLTAGE
2.42 1.0
0.4
PERMALLOY 1.0
0.01 µ = 125 0.2
CORE LOSS IS CURRENT
0.12 2.41 0.5
INDEPENDENT OF LOAD
0.08 0.5
CURRENT UNTIL LOAD CURRENT FALLS
LOW ENOUGH FOR CIRCUIT TO GO INTO 0.04
DISCONTINUOUS MODE
0.001 0.02 0 2.40 0
0 5 10 15 20 25 0 20 40 60 80 100 –50 –25 0 25 50 10075 125
INDUCTANCE (µH) DUTY CYCLE (%) JUNCTION TEMPERATURE (°C)
1375/76 G01 1375/76 G08 1375/76 G09
Kool Mµ is a registered trademark of Magnetics, Inc.
4
LT1375/LT1376
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Shutdown Pin Bias Current Standby and Shutdown Thresholds Shutdown Supply Current
500 2.40 30
CURRENT REQUIRED TO FORCE SHUTDOWN VSHUTDOWN = 0V
STANDBY
400 (FLOWS OUT OF PIN). AFTER SHUTDOWN, 25
INPUT SUPPLY CURRENT (µA)

SHUTDOWN PIN VOLTAGE (V)
CURRENT DROPS TO A FEW µA 2.36
300 20
CURRENT (µA)
2.32
200 15
0.8
8 10
AT 2.38V STANDBY THRESHOLD START-UP
(CURRENT FLOWS OUT OF PIN) 0.4
4 5
SHUTDOWN
0 0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0 5 10 15 20 25
TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) INPUT VOLTAGE (V)
1375/76 G04 1375/76 G05 1375/76 G06
Shutdown Supply Current Error Amplifier Transconductance Error Amplifier Transconductance

150 2500 3000 200
125 PHASE
TRANSCONDUCTANCE (µMho)
INPUT SUPPLY CURRENT (µA)
2000 2500 150
100 GAIN
GAIN (µMho)
PHASE (DEG)
VIN = 25V 1500 2000 100
75 VC
( )
1000 1500 ROUT COUT
VFB 2 • 10–3 50
200k 12pF
50 VIN = 10V
500 1000 ERROR AMPLIFIER EQUIVALENT CIRCUIT 0

25
RLOAD = 50Ω
0 0 500 –50
0 0.1 0.2 0.3 0.4 0.5 –50 –25 0 25 50 75 100 125 100 1k 10k 100k 1M 10M
SHUTDOWN VOLTAGE (V) JUNCTION TEMPERATURE (°C) FREQUENCY (Hz)
1375/76 G07 1375/76 G02 1375/76 G03
LT1376 Minimum Input Voltage

Frequency Foldback Switching Frequency with 5V Output
SWITCHING FREQUENCY (kHz) OR CURRENT (µA)
500 600 8.5

MINIMUM INPUT VOLTAGE CAN BE
8.0 REDUCED BY ADDING A SMALL EXTERNAL
400 PNP. SEE APPLICATIONS INFORMATION
SWITCHING 550
7.5
INPUT VOLTAGE (V)
FREQUENCY
FREQUENCY (kHz)
300 MINIMUM
7.0
500 VOLTAGE TO
START WITH
200 6.5
STANDARD
CIRCUIT
6.0
450
100 MINIMUM VOLTAGE
FEEDBACK PIN 5.5 TO RUN WITH
CURRENT
STANDARD CIRCUIT
0 400 5.0
0 0.5 1.0 1.5 2.0 2.5 –50 –25 0 25 50 75 100 125 0 10 100 1000
FEEDBACK PIN VOLTAGE (V) JUNCTION TEMPERATURE (°C) LOAD CURRENT (mA)
1375/76 G10 1375/76 G11 1375/76 G12
5
LT1375/LT1376
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Maximum Load Current Maximum Load Current Maximum Load Current
at VOUT = 10V at VOUT = 3.3V at VOUT = 5V
1.50 1.50 1.50
VOUT = 10V L = 20µH
L = 20µH L = 20µH
1.25 1.25 L = 10µH 1.25
L = 10µH
L = 10µH
1.00 1.00 1.00
L = 5µH
CURRENT (A)
CURRENT (A)
CURRENT (A)
L = 5µH
0.75 0.75 0.75
L = 5µH
0.50 0.50 0.50
0.25 0.25 0.25

VOUT = 3.3V VOUT = 5V
0 0 0
0 5 10 15 20 25 0 5 10 15 20 25 0 5 10 15 20 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
1375/76 G13 1375/76 G14 1375/76 G15
BOOST Pin Current VC Pin Shutdown Threshold Switch Voltage Drop

12 1.4 0.8
TJ = 25°C SHUTDOWN TJ = 25°C
10
1.2
BOOST PIN CURRENT (mA)
THRESHOLD VOLTAGE (V)
0.6
SWITCH VOLTAGE (V)

8
1.0
6 0.4
0.8
4
0.2
0.6
2
0 0.4 0
0 0.25 0.50 0.75 1.00 1.25 –50 –25 0 25 50 75
100 125 0 0.25 0.50 0.75 1.00 1.25 1.50
SWITCH CURRENT (A) JUNCTION TEMPERATURE (°C) SWITCH CURRENT (A)
1375/76 G16 1375/76 G11 1375/76 G18
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PIN FUNCTIONS
BOOST: The BOOST pin is used to provide a drive voltage, with the external catch diode. Maximum negative switch
higher than the input voltage, to the internal bipolar NPN voltage allowed is – 0.8V.
power switch. Without this added voltage, the typical
SHDN: The shutdown pin is used to turn off the regulator
switch voltage loss would be about 1.5V. The additional
and to reduce input drain current to a few microamperes.
boost voltage allows the switch to saturate and voltage Actually, this pin has two separate thresholds, one at
loss approximates that of a 0.3Ω FET structure, but with
2.38V to disable switching, and a second at 0.4V to force
much smaller die area. Efficiency improves from 75% for
complete micropower shutdown. The 2.38V threshold
conventional bipolar designs to > 87% for these new parts. functions as an accurate undervoltage lockout (UVLO).
VSW: The switch pin is the emitter of the on-chip power This is sometimes used to prevent the regulator from
NPN switch. It is driven up to the input pin voltage during operating until the input voltage has reached a predeter-
switch on time. Inductor current drives the switch pin mined level.
negative during switch off time. Negative voltage is clamped
6
LT1375/LT1376
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PIN FUNCTIONS
VIN: This is the collector of the on-chip power NPN switch. pin is used as a SENSE pin, connected directly to the 5V
This pin powers the internal circuitry and internal regulator output. Two additional functions are performed by the FB
when the BIAS pin is not present. At NPN switch on and off, pin. When the pin voltage drops below 1.7V, switch
high dl/dt edges occur on this pin. Keep the external current limit is reduced. Below 1V, switching frequency is
bypass and catch diode close to this pin. All trace induc- also reduced. See Feedback Pin Function section in Appli-
tance on this path will create a voltage spike at switch off, cations Information for details.
adding to the VCE voltage across the internal NPN. VC: The VC pin is the output of the error amplifier and the
BIAS (LT1376 Only): The BIAS pin is used to improve input of the peak switch current comparator. It is normally
efficiency when operating at higher input voltages and used for frequency compensation, but can do double duty
light load current. Connecting this pin to the regulated as a current clamp or control loop override. This pin sits
output voltage forces most of the internal circuitry to draw at about 1V for very light loads and 2V at maximum load.
its operating current from the output voltage rather than It can be driven to ground to shut off the regulator, but if
the input supply. This is a much more efficient way of driven high, current must be limited to 4mA.
doing business if the input voltage is much higher than the GND: The GND pin connection needs consideration for
output. Minimum output voltage setting for this mode of two reasons. First, it acts as the reference for the regulated
operation is 3.3V. Efficiency improvement at VIN = 20V, output, so load regulation will suffer if the “ground” end of
VOUT = 5V, and IOUT = 25mA is over 10%. the load is not at the same voltage as the GND pin of the
SYNC (LT1375 Only): The SYNC pin is used to synchro- IC. This condition will occur when load current or other
nize the internal oscillator to an external signal. It is directly currents flow through metal paths between the GND pin
logic compatible and can be driven with any signal be- and the load ground point. Keep the ground path short
tween 10% and 90% duty cycle. The synchronizing range between the GND pin and the load, and use a ground plane
is equal to initial operating frequency, up to 900kHz. See when possible. The second consideration is EMI caused
Synchronizing section in Applications Information for by GND pin current spikes. Internal capacitance between
details. the VSW pin and the GND pin creates very narrow (<10ns)
FB/SENSE: The feedback pin is used to set output voltage, current spikes in the GND pin. If the GND pin is connected
to system ground with a long metal trace, this trace may
using an external voltage divider that generates 2.42V at
the pin with the desired output voltage. The fixed voltage radiate excess EMI. Keep the path between the input
(-5) parts have the divider included on the chip, and the FB bypass and the GND pin short.
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BLOCK DIAGRAM
The LT1376 is a constant frequency, current mode buck amplifier commands current to be delivered to the output
converter. This means that there is an internal clock and rather than voltage. A voltage fed system will have low
two feedback loops that control the duty cycle of the power phase shift up to the resonant frequency of the inductor
switch. In addition to the normal error amplifier, there is a and output capacitor, then an abrupt 180° shift will occur.
current sense amplifier that monitors switch current on a The current fed system will have 90° phase shift at a much
cycle-by-cycle basis. A switch cycle starts with an oscilla- lower frequency, but will not have the additional 90° shift
tor pulse which sets the RS flip-flop to turn the switch on. until well beyond the LC resonant frequency. This makes
When switch current reaches a level set by the inverting it much easier to frequency compensate the feedback loop
input of the comparator, the flip-flop is reset and the and also gives much quicker transient response.
switch turns off. Output voltage control is obtained by
Most of the circuitry of the LT1376 operates from an
using the output of the error amplifier to set the switch
internal 2.9V bias line. The bias regulator normally draws
current trip point. This technique means that the error
power from the regulator input pin, but if the BIAS pin is
7
LT1375/LT1376
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BLOCK DIAGRAM
connected to an external voltage higher than 3V, bias than the input voltage, allowing switch to be saturated.
power will be drawn from the external source (typically the This boosted voltage is generated with an external capaci-
regulated output voltage). This will improve efficiency if tor and diode. Two comparators are connected to the
the BIAS pin voltage is lower than regulator input voltage. shutdown pin. One has a 2.38V threshold for undervoltage
lockout and the second has a 0.4V threshold for complete
High switch efficiency is attained by using the BOOST pin
shutdown.
to provide a voltage to the switch driver which is higher
0.1Ω
INPUT
+ –
CURRENT
2.9V BIAS INTERNAL SENSE
BIAS REGULATOR AMPLIFIER
VCC
VOLTAGE GAIN = 10
SLOPE COMP Σ BOOST
0.9V
500kHz
SYNC OSCILLATOR S Q1
RS DRIVER
POWER
FLIP-FLOP CIRCUITRY
SWITCH
+ R
SHUTDOWN
COMPARATOR
– VSW
+ – CURRENT
COMPARATOR
0.37V
FREQUENCY
SHDN SHIFT CIRCUIT
3.5µA
FOLDBACK Q2
CURRENT
+ LIMIT
CLAMP
–
FB
–
LOCKOUT +
COMPARATOR ERROR
2.38V AMPLIFIER
VC gm = 2000µMho 2.42V
GND
1375/76 BD
Figure 1. Block Diagram
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APPLICATIONS INFORMATION
FEEDBACK PIN FUNCTIONS resistors and the FB pin is renamed SENSE, connected
directly to the output.
The feedback (FB) pin on the LT1376 is used to set output
voltage and also to provide several overload protection The suggested value for the output divider resistor (see
features. The first part of this section deals with selecting Figure 2) from FB to ground (R2) is 5k or less, and a
resistors to set output voltage and the remaining part talks formula for R1 is shown below. The output voltage error
about foldback frequency and current limiting created by caused by ignoring the input bias current on the FB pin is
the FB pin. Please read both parts before committing to a less than 0.25% with R2 = 5k. A table of standard 1%
final design. The fixed 5V LT1376-5 has internal divider values is shown in Table 1 for common output voltages.
8
LT1375/LT1376
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LT1375/LT1376 TO FREQUENCY VSW
SHIFTING OUTPUT
5V
1.6V Q1
ERROR
AMPLIFIER
+ 2.4V
R1
R3 R4
FB
1k 1k +
R5
–
5k
Q2 R2
5k
VC GND
1375/76 F02
Figure 2. Frequency and Current Limit Foldback
Please read the following if divider resistors are increased equal to the short-circuit current limit of the switch (typi-
above the suggested values. cally 2A for the LT1376, folding back to less than 1A).
Minimum switch on time limitations would prevent the
R1 =
(
R2 VOUT − 2.42 ) switcher from attaining a sufficiently low duty cycle if
switching frequency were maintained at 500kHz, so fre-
2.42 quency is reduced by about 5:1 when the feedback pin
Table 1 voltage drops below 1V (see Frequency Foldback graph).
OUTPUT R1 % ERROR AT OUTPUT This does not affect operation with normal load condi-
VOLTAGE R2 (NEAREST 1%) DUE TO DISCREET 1% tions; one simply sees a gear shift in switching frequency
(V) (kΩ) (kΩ) RESISTOR STEPS
during start-up as the output voltage rises.
3 4.99 1.21 + 0.23
3.3 4.99 1.82 + 0.08 In addition to lower switching frequency, the LT1376 also
5 4.99 5.36 + 0.39 operates at lower switch current limit when the feedback
6 4.99 7.32 – 0.5 pin voltage drops below 1.7V. Q2 in Figure 2 performs this
8 4.99 11.5 – 0.04 function by clamping the VC pin to a voltage less than its
10 4.99 15.8 + 0.83 normal 2.3V upper clamp level. This foldback current limit
12 4.99 19.6 – 0.62 greatly reduces power dissipation in the IC, diode and
15 4.99 26.1 + 0.52 inductor during short-circuit conditions. Again, it is nearly
transparent to the user under normal load conditions. The
only loads which may be affected are current source loads
More Than Just Voltage Feedback which maintain full load current with output voltage less
The feedback (FB) pin is used for more than just output than 50% of final value. In these rare situations the
voltage sensing. It also reduces switching frequency and Feedback pin can be clamped above 1.5V with an external
current limit when output voltage is very low (see the diode to defeat foldback current limit. Caution: clamping
Frequency Foldback graph in Typical Performance Char- the feedback pin means that frequency shifting will also be
acteristics). This is done to control power dissipation in defeated, so a combination of high input voltage and dead
both the IC and in the external diode and inductor during shorted output may cause the LT1376 to lose control of
short-circuit conditions. A shorted output requires the current limit.
switching regulator to operate at very low duty cycles, and The internal circuitry which forces reduced switching
the average current through the diode and inductor is frequency also causes current to flow out of the feedback
9
LT1375/LT1376
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pin when output voltage is low. The equivalent circuitry is formula assumes continuous mode operation, implying
shown in Figure 2. Q1 is completely off during normal that the term on the right is less than one-half of IP.
operation. If the FB pin falls below 1V, Q1 begins to
conduct current and reduces frequency at the rate of
approximately 5kHz/µA. To ensure adequate frequency IOUT(MAX) =
IP −
(V )(V − V )
OUT IN OUT
foldback (under worst-case short-circuit conditions), the Continuous Mode 2(L)(f)(V ) IN
external divider Thevinin resistance must be low enough
to pull 150µA out of the FB pin with 0.6V on the pin (RDIV
≤ 4k). The net result is that reductions in frequency and For the conditions above and L = 10µH,
current limit are affected by output voltage divider imped-
ance. Although divider impedance is not critical, caution
IOUT (MAX ) = 1.44 −
(5)(8 − 5)
()
should be used if resistors are increased beyond the
suggested values and short-circuit conditions will occur 2 10 −5   500 • 10 3  8
with high input voltage. High frequency pickup will in-
crease and the protection accorded by frequency and = 1.44 − 0.19 = 1.25A
current foldback will decrease.
At VIN = 15V, duty cycle is 33%, so IP is just equal to a fixed
1.5A, and IOUT(MAX) is equal to:
MAXIMUM OUTPUT LOAD CURRENT
Maximum load current for a buck converter is limited by
1.5 −
(5)(15 − 5) = 1.5 − 0.33 = 1.17 A
( )
the maximum switch current rating (IP) of the LT1376.
This current rating is 1.5A up to 50% duty cycle (DC), 2 10 −5   500 • 10 3  15
decreasing to 1.35A at 80% duty cycle. This is shown
graphically in Typical Performance Characteristics and as Note that there is less load current available at the higher
shown in the formula below: input voltage because inductor ripple current increases.
IP = 1.5A for DC ≤ 50% This is not always the case. Certain combinations of
IP = 1.65A – 0.15 (DC) – 0.26 (DC)2 for 50% < DC < 90% inductor value and input voltage range may yield lower
available load current at the lowest input voltage due to
DC = Duty cycle = VOUT/VIN reduced peak switch current at high duty cycles. If load
Example: with VOUT = 5V, VIN = 8V; DC = 5/8 = 0.625, and; current is close to the maximum available, please check
maximum available current at both input voltage ex-
ISW(MAX) = 1.64 – 0.15 (0.625) – 0.26 (0.625)2 = 1.44A
tremes. To calculate actual peak switch current with a
Current rating decreases with duty cycle because the given set of conditions, use:
LT1376 has internal slope compensation to prevent cur-
rent mode subharmonic switching. For more details, read
Application Note 19. The LT1376 is a little unusual in this ISW(PEAK ) = IOUT +
(
VOUT VIN − VOUT )
regard because it has nonlinear slope compensation which 2(L)(f)(V ) IN
gives better compensation with less reduction in current
limit. For lighter loads where discontinuous operation can be
used, maximum load current is equal to:
Maximum load current would be equal to maximum
(I ) (f)(L)(V )
switch current for an infinitely large inductor, but with 2
finite inductor size, maximum load current is reduced by P OUT
IOUT(MAX) =
one-half peak-to-peak inductor current. The following
Discontinuous mode 2(V )(V − V )
OUT IN OUT
10
LT1375/LT1376
U U W U
Example: with L = 2µH, VOUT = 5V, and VIN(MAX) = 15V, must withstand continuous fault conditions. If maxi-
mum load current is 0.5A, for instance, a 0.5A inductor
( 1.5)  500 • 10   2 • 10  (15)
2 3 −6 may not survive a continuous 1.5A overload condition.
Dead shorts will actually be more gentle on the induc-
IOUT (MAX )= = 338mA
2(5)(15 − 5) tor because the LT1376 has foldback current limiting.
2. Calculate peak inductor current at full load current to
The main reason for using such a tiny inductor is that it is ensure that the inductor will not saturate. Peak current
physically very small, but keep in mind that peak-to-peak can be significantly higher than output current, espe-
inductor current will be very high. This will increase output cially with smaller inductors and lighter loads, so don’t
ripple voltage. If the output capacitor has to be made larger omit this step. Powdered iron cores are forgiving
to reduce ripple voltage, the overall circuit could actually because they saturate softly, whereas ferrite cores
wind up larger. saturate abruptly. Other core materials fall in between
somewhere. The following formula assumes continu-
CHOOSING THE INDUCTOR AND OUTPUT CAPACITOR ous mode of operation, but it errs only slightly on the
high side for discontinuous mode, so it can be used for
For most applications the output inductor will fall in the all conditions.
range of 3µH to 20µH. Lower values are chosen to reduce
physical size of the inductor. Higher values allow more
IPEAK = IOUT +
( )
VOUT VIN − VOUT
2(f)(L)(V )
output current because they reduce peak current seen by
the LT1376 switch, which has a 1.5A limit. Higher values IN
also reduce output ripple voltage, and reduce core loss.
VIN = Maximum input voltage
Graphs in the Typical Performance Characteristics section
f = Switching frequency, 500kHz
show maximum output load current versus inductor size
and input voltage. A second graph shows core loss versus 3. Decide if the design can tolerate an “open” core geom-
inductor size for various core materials. etry like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid
When choosing an inductor you might have to consider
to prevent EMI problems. One would not want an open
maximum load current, core and copper losses, allowable
core next to a magnetic storage media, for instance!
component height, output voltage ripple, EMI, fault cur-
This is a tough decision because the rods or barrels are
rent in the inductor, saturation, and of course, cost. The
temptingly cheap and small and there are no helpful
following procedure is suggested as a way of handling
guidelines to calculate when the magnetic field radia-
these somewhat complicated and conflicting requirements.
tion will be a problem.
1. Choose a value in microhenries from the graphs of
4. Start shopping for an inductor (see representative
maximum load current and core loss. Choosing a small
surface mount units in Table 2) which meets the re-
inductor with lighter loads may result in discontinuous
quirements of core shape, peak current (to avoid satu-
mode of operation, but the LT1376 is designed to work
ration), average current (to limit heating), and fault
well in either mode. Keep in mind that lower core loss
current (if the inductor gets too hot, wire insulation will
means higher cost, at least for closed core geometries
melt and cause turn-to-turn shorts). Keep in mind that
like toroids. The core loss graphs show both absolute
all good things like high efficiency, low profile, and high
loss and percent loss for a 5W output, so actual percent
temperature operation will increase cost, sometimes
losses must be calculated for each situation.
dramatically. Get a quote on the cheapest unit first to
Assume that the average inductor current is equal to calibrate yourself on price, then ask for what you really
load current and decide whether or not the inductor want.
11
LT1375/LT1376
U U W U
5. After making an initial choice, consider the secondary Tor = Toroid
SC = Semi-closed geometry
things like output voltage ripple, second sourcing, etc.
Fer = Ferrite core material
Use the experts in the Linear Technology’s applica- 52 = Type 52 powdered iron core material
tions department if you feel uncertain about the final KMµ = Kool Mµ
choice. They have experience with a wide range of
inductor types and can tell you about the latest devel- Output Capacitor
opments in low profile, surface mounting, etc. The output capacitor is normally chosen by its Effective
Series Resistance (ESR), because this is what determines
Table 2
output ripple voltage. At 500kHz, any polarized capacitor
SERIES CORE
is essentially resistive. To get low ESR takes volume, so
VENDOR/ VALUE DC CORE RESIS- MATER- HEIGHT physically smaller capacitors have high ESR. The ESR
PART NO. (µH) (Amps) TYPE TANCE(Ω) IAL (mm) range for typical LT1376 applications is 0.05Ω to 0.5Ω. A
Coiltronics typical output capacitor is an AVX type TPS, 100µF at 10V,
CTX5-1 5 2.3 Tor 0.027 KMµ 4.2 with a guaranteed ESR less than 0.1Ω. This is a “D” size
CTX10-1 10 1.9 Tor 0.039 KMµ 4.2 surface mount solid tantalum capacitor. TPS capacitors
CTX20-1 20 1.0 Tor 0.137 KMµ 4.2 are specially constructed and tested for low ESR, so they
CTX15-2 15 1.8 Tor 0.058 KMµ 6.0 give the lowest ESR for a given volume. The value in
CTX20-3 20 1.5 Tor 0.093 KMµ 4.7 microfarads is not particularly critical, and values from
CTX20-4 20 2.2 Tor 0.059 KMµ 6.4 22µF to greater than 500µF work well, but you cannot
CTX5-1P 5 1.8 Tor 0.021 52 4.2 cheat mother nature on ESR. If you find a tiny 22µF solid
CTX10-1P 10 1.6 Tor 0.030 52 4.2 tantalum capacitor, it will have high ESR, and output ripple
CTX15-1P 15 1.2 Tor 0.046 52 4.2 voltage will be terrible. Table 3 shows some typical solid
CTX20-1P 20 1.0 Tor 0.081 52 4.2 tantalum surface mount capacitors.
CTX20-2P 20 1.3 Tor 0.052 52 6.0 Table 3. Surface Mount Solid Tantalum Capacitor ESR
CTX20-4P 20 1.8 Tor 0.039 52 6.35 and Ripple Current
Sumida E Case Size ESR (Max., Ω ) Ripple Current (A)
CDRH64 10 1.7 SC 0.084 Fer 4.5 AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
CDRH74 22 1.2 SC 0.077 Fer 4.5 AVX TAJ 0.7 to 0.9 0.4
CDRH73 10 1.7 SC 0.055 Fer 3.4 D Case Size
CDRH73 22 1.1 SC 0.15 Fer 3.4 AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
CD73 10 1.4 Open 0.062 Fer 3.5 AVX TAJ 0.9 to 2.0 0.36 to 0.24
CD73 18 1.1 Open 0.085 Fer 3.5 C Case Size
CD104 10 2.4 Open 0.041 Fer 4.0 AVX TPS 0.2 (typ) 0.5 (typ)
CD104 18 1.7 Open 0.062 Fer 4.0 AVX TAJ 1.8 to 3.0 0.22 to 0.17
Gowanda B Case Size
SM20-102K 10 1.3 Open 0.038 Fer 7.0 AVX TAJ 2.5 to 10 0.16 to 0.08
SM20-152K 15 1.3 Open 0.049 Fer 7.0
SM20-222K 22 1.3 Open 0.059 Fer 7.0 Many engineers have heard that solid tantalum capacitors
Dale are prone to failure if they undergo high surge currents.
IHSM-4825 10 3.1 Open 0.071 Fer 5.6 This is historically true, and type TPS capacitors are
IHSM-4825 22 1.7 Open 0.152 Fer 5.6
specially tested for surge capability, but surge ruggedness
IHSM-5832 10 4.3 Open 0.053 Fer 7.1
is not a critical issue with the output capacitor. Solid
IHSM-5832 22 2.8 Open 0.12 Fer 7.1
tantalum capacitors fail during very high turn-on surges,
IHSM-7832 22 3.8 Open 0.054 Fer 7.1
which do not occur at the output of regulators. High
12
LT1375/LT1376
U U W U
discharge surges, such as when the regulator output is dI VIN
dead shorted, do not harm the capacitors. Σ =
dt L
Unlike the input capacitor, RMS ripple current in the
Peak-to-peak output ripple voltage is the sum of a triwave
output capacitor is normally low enough that ripple cur-
created by peak-to-peak ripple current times ESR, and a
rent rating is not an issue. The current waveform is
square wave created by parasitic inductance (ESL) and
triangular with a typical value of 200mARMS. The formula
ripple current slew rate. Capacitive reactance is assumed
to calculate this is:
to be small compared to ESR or ESL.
Output Capacitor Ripple Current (RMS):
IRIPPLE(RMS) =
( )(
0.29 VOUT VIN − VOUT ) ( )( ) ( )
VRIPPLE = IP-P ESR + ESL Σ
dI
dt
(L)(f)(V )
IN Example: with VIN =10V, VOUT = 5V, L = 10µH, ESR = 0.1Ω,
ESL = 10nH:
Ceramic Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. These are tempt- IP-P =
(5)(10 − 5) = 0.5A
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
( )
10  10 • 10 − 6  500 • 103 
loop stability problems. Solid tantalum capacitor’s ESR dI 10

Σ = = 10 6
generates a loop “zero” at 5kHz to 50kHz that is instrumen- dt 10 • 10 − 6
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually ( )( )
VRIPPLE = 0.5A 0.1 +  10 • 10 − 9   10 6 
resonate with their ESL before ESR becomes effective. = 0.05 + 0.01 = 60mVP-P
They are appropriate for input bypassing because of their
high ripple current ratings and tolerance of turn-on surges.
For further information on ceramic and other capacitor VOUT AT IOUT = 1A
types please refer to Design Note 95.
20mV/DIV
VOUT AT IOUT = 50mA

OUTPUT RIPPLE VOLTAGE
INDUCTOR CURRENT
Figure 3 shows a typical output ripple voltage waveform AT IOUT = 1A
for the LT1376. Ripple voltage is determined by the high 0.5A/DIV
frequency impedance of the output capacitor, and ripple INDUCTOR CURRENT
AT IOUT = 50mA
current through the inductor. Peak-to-peak ripple current 0.5µs/DIV 1375/76 F03
through the inductor into the output capacitor is:

Figure 3. LT1376 Ripple Voltage Waveform
IP-P =
(V )(V − V )
OUT IN OUT
(V )(L)(f)
IN
CATCH DIODE
The suggested catch diode (D1) is a 1N5818 Schottky, or
For high frequency switchers, the sum of ripple current its Motorola equivalent, MBR130. It is rated at 1A average
slew rates may also be relevant and can be calculated forward current and 30V reverse voltage. Typical forward
from: voltage is 0.42V at 1A. The diode conducts current only
during switch off time. Peak reverse voltage is equal to
13
LT1375/LT1376
U U W U
regulator input voltage. Average forward current in normal pin voltage is equal to input voltage plus output voltage,
operation can be calculated from: but when the boost diode is connected to the regulator
input, peak BOOST pin voltage is equal to twice the input
ID(AVG) =
(
IOUT VIN − VOUT ) voltage. Be sure that BOOST pin voltage does not exceed
its maximum rating.
VIN
For nearly all applications, a 0.1uF boost capacitor works
This formula will not yield values higher than 1A with just fine, but for the curious, more details are provided
maximum load current of 1.25A unless the ratio of input here. The size of the boost capacitor is determined by
to output voltage exceeds 5:1. The only reason to consider switch drive current requirements. During switch on time,
a larger diode is the worst-case condition of a high input drain current on the capacitor is approximately 10mA +
voltage and overloaded (not shorted) output. Under short- IOUT/ 75. At peak load current of 1.25A, this gives a total
circuit conditions, foldback current limit will reduce diode drain of 27mA. Capacitor ripple voltage is equal to the
current to less than 1A, but if the output is overloaded and product of on time and drain current divided by capacitor
does not fall to less than 1/3 of nominal output voltage, value; ∆V = tON • 27mA/C. To keep capacitor ripple voltage
foldback will not take effect. With the overloaded condi- to less than 0.5V (a slightly arbitrary number) at the worst-
tion, output current will increase to a typical value of 1.8A, case condition of tON = 1.8µs, the capacitor needs to be
determined by peak switch current limit of 2A. With 0.1µF. Boost capacitor ripple voltage is not a critical
VIN = 15V, VOUT = 4V (5V overloaded) and IOUT = 1.8A: parameter, but if the minimum voltage across the capaci-
tor drops to less than 3V, the power switch may not
ID(AVG) =
(
1.8 15 − 4 ) = 1.32A saturate fully and efficiency will drop. An approximate
formula for absolute minimum capacitor value is:
15
This is safe for short periods of time, but it would be
CMIN =
(10mA + I / 75)(V
OUT OUT / VIN)
prudent to check with the diode manufacturer if continu-
ous operation under these conditions must be tolerated.
(f)(V − 3V)
OUT
f = Switching frequency
BOOST␣ PIN␣ CONSIDERATIONS VOUT = Regulated output voltage
VIN = Minimum input voltage
For most applications, the boost components are a 0.1µF
capacitor and a 1N914 or 1N4148 diode. The anode is This formula can yield capacitor values substantially less
connected to the regulated output voltage and this gener- than 0.1µF, but it should be used with caution since it does
ates a voltage across the boost capacitor nearly identical not take into account secondary factors such as capacitor
to the regulated output. In certain applications, the anode series resistance, capacitance shift with temperature and
may instead be connected to the unregulated input volt- output overload.
age. This could be necessary if the regulated output
voltage is very low (< 3V) or if the input voltage is less than SHUTDOWN FUNCTION AND UNDERVOLTAGE
6V. Efficiency is not affected by the capacitor value, but the LOCKOUT
capacitor should have an ESR of less than 2Ω to ensure
that it can be recharged fully under the worst-case condi- Figure 4 shows how to add undervoltage lockout (UVLO)
tion of minimum input voltage. Almost any type of film or to the LT1376. Typically, UVLO is used in situations where
ceramic capacitor will work fine. the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
WARNING! Peak voltage on the BOOST pin is the sum of power from the source, so source current increases as
unregulated input voltage plus the voltage across the source voltage drops. This looks like a negative resistance
boost capacitor. This normally means that peak BOOST load to the source and can cause the source to current limit
14
LT1375/LT1376
U U W U
RFB
LT1375/LT1376
VSW OUTPUT
INPUT IN 2.38V +
STANDBY
RHI 3.5µA –
SHDN +
+
TOTAL
SHUTDOWN
C1 RLO 0.37V –
GND
1375/76 F04
Figure 4. Undervoltage Lockout
or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages RHI =
[ (
RLO VIN − 2.38 ∆V / VOUT + 1 + ∆V ) ]
where these problems might occur. 2.38 − R2 3.5µA( )
Threshold voltage for lockout is about 2.38V, slightly less
than the internal 2.42V reference voltage. A 3.5µA bias
( )(
RFB = RHI VOUT / ∆V )
current flows out of the pin at threshold. This internally 25k suggested for RLO
generated current is used to force a default high state on VIN = Input voltage at which switching stops as input
the shutdown pin if the pin is left open. When low shut- voltage descends to trip level
down current is not an issue, the error due to this current ∆V = Hysteresis in input voltage level
can be minimized by making RLO 10k or less. If shutdown
Example: output voltage is 5V, switching is to stop if input
current is an issue, RLO can be raised to 100k, but the error
voltage drops below 12V and should not restart unless
due to initial bias current and changes with temperature
input rises back to 13.5V. ∆V is therefore 1.5V and VIN =
should be considered.
12V. Let RLO = 25k.
(
RLO = 10k to 100k 25k suggested ) [ ( ) ]
25k 12 − 2.38 1.5 / 5 + 1 + 1.5
RHI =
(
RLO VIN − 2.38V ) RHI =
2.38 − 25k (3.5µA)
(
2.38V − RLO 3.5 µA ) 25k (10.41)
= = 114k
VIN = Minimum input voltage 2.29
Keep the connections from the resistors to the shutdown ( )
RFB = 114k 5 / 1.5 = 380k
pin short and make sure that interplane or surface capaci-
tance to the switching nodes are minimized. If high resis-
tor values are used, the shutdown pin should be bypassed SWITCH NODE CONSIDERATIONS
with a 1000pF capacitor to prevent coupling problems For maximum efficiency, switch rise and fall times are
from the switch node. If hysteresis is desired in the made as short as possible. To prevent radiation and high
undervoltage lockout point, a resistor RFB can be added to frequency resonance problems, proper layout of the com-
the output node. Resistor values can be calculated from: ponents connected to the switch node is essential. B field
15
LT1375/LT1376
U U W U
(magnetic) radiation is minimized by keeping catch diode, the only one containing nanosecond rise and fall times. If
switch pin, and input bypass capacitor leads as short as you follow this path on the PC layout, you will see that it is
possible. E field radiation is kept low by minimizing the irreducibly short. If you move the diode or input capacitor
length and area of all traces connected to the switch pin away from the LT1376, get your resumé in order. The
and BOOST pin. A ground plane should always be used other paths contain only some combination of DC and
under the switcher circuitry to prevent interplane cou- 500kHz triwave, so are much less critical.
pling. A suggested layout for the critical components is
SWITCH NODE
shown in Figure 5. Note that the feedback resistors and L1
compensation components are kept as far as possible 5V
from the switch node. Also note that the high current
HIGH
ground path of the catch diode and input capacitor are kept FREQUENCY
VIN LOAD
very short and separate from the analog ground line. CIRCULATING
PATH
The high speed switching current path is shown schemati-

cally in Figure 6. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path 1375/76 F06
including the switch, catch diode, and input capacitor is Figure 6. High Speed Switching Path
INPUT
MINIMIZE AREA OF D2
CONNECTIONS TO THE C2
SWITCH NODE AND
BOOST NODE CC MINIMIZE SIZE OF
BOOST VC FEEDBACK PIN
C3 CONNECTIONS TO
IN FB RC AVOID PICKUP
KEEP INPUT CAPACITOR
AND CATCH DIODE CLOSE SW GND
TO REGULATOR AND D1 R1 R2
TERMINATE THEM BIAS SHDN
TO SAME POINT
TERMINATE
FEEDBACK RESISTORS
AND COMPENSATION
L1 COMPONENTS
DIRECTLY TO SWITCHER
SHUTDOWN
C1 GROUND PIN
OUTPUT
GROUND RING NEED

NOT BE AS SHOWN.
(NORMALLY EXISTS AS
INTERNAL PLANE)
CONNECT OUTPUT CAPACITOR TAKE OUTPUT DIRECTLY FROM END OF OUTPUT 1375/76 F05
DIRECTLY TO HEAVY GROUND CAPACITOR TO AVOID PARASITIC RESISTANCE

AND INDUCTANCE (KELVIN CONNECTION)
Figure 5. Suggested Layout
16
LT1375/LT1376
U U W U
PARASITIC RESONANCE voltages over 1V lasting longer than 10ns should be
Resonance or “ringing” may sometimes be seen on the avoided. Note that 100MHz oscilloscopes are barely fast
enough to see the details of the falling edge overshoot in
switch node (see Figure 7). Very high frequency ringing
following switch rise time is caused by switch/diode/input Figure 7.
capacitor lead inductance and diode capacitance. Schot- A second, much lower frequency ringing is seen during
tky diodes have very high “Q” junction capacitance that switch off time if load current is low enough to allow the
can ring for many cycles when excited at high frequency. inductor current to fall to zero during part of the switch off
If total lead length for the input capacitor, diode and switch time (see Figure 8). Switch and diode capacitance reso-
path is 1 inch, the inductance will be approximately 25nH. nate with the inductor to form damped ringing at 1MHz to
Schottky diode capacitance of 100pF will create a reso- 10 MHz. Again, this ringing is not harmful to the regulator
nance at 100MHz. This ringing is not harmful to the and it has not been shown to contribute significantly to
LT1376 and can normally be ignored. EMI. Any attempt to damp it with a resistive snubber will
Overshoot or ringing following switch fall time is created degrade efficiency.
by switch capacitance rather than diode capacitance. This
ringing per se is not harmful, but the overshoot can cause INPUT BYPASSING AND VOLTAGE RANGE
problems if the amplitude becomes too high. The negative
voltage can forward bias parasitic junctions on the IC chip Input Bypass Capacitor
and cause erratic switching. The LT1376 has special Step-down converters draw current from the input supply
circuitry inside which mitigates this problem, but negative in pulses. The average height of these pulses is equal to
load current, and the duty cycle is equal to VOUT/ VIN. Rise
and fall time of the current is very fast. A local bypass
capacitor across the input supply is necessary to ensure
proper operation of the regulator and minimize the ripple
RISE AND FALL current fed back into the input supply. The capacitor also
WAVEFORMS ARE
5V/DIV SUPERIMPOSED forces switching current to flow in a tight local loop,
(PULSE WIDTH IS
NOT 120ns)
minimizing EMI.
Do not cheat on the ripple current rating of the Input
bypass capacitor, but also don’t get hung up on the value
in microfarads. The input capacitor is intended to absorb
20ns/DIV 1375/76 F07
all the switching current ripple, which can have an RMS
Figure 7. Switch Node Resonance value as high as one half of load current. Ripple current
ratings on the capacitor must be observed to ensure
reliable operation. The actual value of the capacitor in
microfarads is not particularly important because at
5V/DIV 500kHz, any value above 5µF is essentially resistive. RMS
SWITCH NODE
VOLTAGE
ripple current rating is the critical parameter. Actual RMS
current can be calculated from:
100mA/DIV INDUCTOR
CURRENT ( )
IRIPPLE(RMS) = IOUT VOUT VIN − VOUT / VIN
2
20ns/DIV 1375/76 F11

The term inside the radical has a maximum value of 0.5
0.5µs/DIV 1375/76 F08
when input voltage is twice output, and stays near 0.5 for
Figure 8. Discontinuous Mode Ringing a relatively wide range of input voltages. It is common
17
LT1375/LT1376
U U W U
practice therefore to simply use the worst-case value and below the minimum specification. Problems can also
assume that RMS ripple current is one half of load current. occur if the input-to-output voltage differential is near
At maximum output current of 1.5A for the LT1376, the minimum. The amplitude of these dips is normally a
input bypass capacitor should be rated at 0.75A ripple function of capacitor ESR and ESL because the capacitive
current. Note however, that there are many secondary reactance is small compared to these terms. ESR tends to
considerations in choosing the final ripple current rating. be the dominate term and is inversely related to physical
These include ambient temperature, average versus peak capacitor size within a given capacitor type.
load current, equipment operating schedule, and required
product lifetime. For more details, see Application Notes Minimum Input Voltage (After Start-Up)
19 and 46, and Design Note 95. Minimum input voltage to make the LT1376 “run” cor-
rectly is typically 5V, but to regulate the output, a buck
Input Capacitor Type
converter input voltage must always be higher than the
Some caution must be used when selecting the type of output voltage. To calculate minimum operating input
capacitor used at the input to regulators. Aluminum voltage, switch voltage loss and maximum duty cycle
electrolytics are lowest cost, but are physically large to must be taken into account. With the LT1376, there is the
achieve adequate ripple current rating, and size con- additional consideration of proper operation of the boost
straints (especially height), may preclude their use. Ce- circuit. The boost circuit allows the power switch to
ramic capacitors are now available in larger values, and saturate for high efficiency, but it also sometimes results
their high ripple current and voltage rating make them in a start-up or operating voltage that is several volts
ideal for input bypassing. Cost is fairly high and footprint higher than the standard running voltage, especially at
may also be somewhat large. Solid tantalum capacitors light loads. An approximate formula to calculate minimum
would be a good choice, except that they have a history of running voltage at load currents above 100mA is:
occasional spectacular failures when they are subjected to
large current surges during power-up. The capacitors can
short and then burn with a brilliant white light and lots of VIN(MIN) =
( )(
VOUT + IOUT 0.4Ω )
nasty smoke. This phenomenon occurs in only a small 0.88
percentage of units, but it has led some OEM companies
to forbid their use in high surge applications. The input Minimum Start-Up Voltage and Operation at
Light Loads
bypass capacitor of regulators can see these high surges
when a battery or high capacitance source is connected. The boost capacitor supplies current to the BOOST pin
Several manufacturers have developed a line of solid during switch on time. This capacitor is recharged only
tantalum capacitors specially tested for surge capability during switch off time. Under certain conditions of light
(AVX TPS series for instance, see Table 3), but even these load and low input voltage, the capacitor may not be
units may fail if the input voltage surge approaches the recharged fully during the relatively short off time. This
maximum voltage rating of the capacitor. AVX recom- causes the boost voltage to collapse and minimum input
mends derating capacitor voltage by 2:1 for high surge voltage is increased. Start-up voltage at light loads is
applications. The highest voltage rating is 50V, so 25V higher than normal running voltage for the same reasons.
may be a practical upper limit when using solid tantalum The graph in Figure 9 shows minimum input voltage for a
capacitors for input bypassing. 5V output, both for start-up and for normal operation.
Larger capacitors may be necessary when the input volt- The circuit in Figure 10 will allow operation at light load
age is very close to the minimum specified on the data with low input voltages. It uses a small PNP to charge the
sheet. Small voltage dips during switch on time are not boost capacitor C2, and an extra diode D3 to complete the
normally a problem, but at very low input voltage they may power path from VSW to the boost capacitor.
cause erratic operation because the input voltage drops
18
LT1375/LT1376
U U W U
8.0
(A) MINIMUM VOLTAGE
Compensation section for a discussion of an entirely
7.5
TO START WITH
STANDARD CIRCUIT
different cause of subharmonic switching before assum-
(A)
(B) (B) MINIMUM VOLTAGE ing that the cause is insufficient slope compensation.
INPUT VOLTAGE (V)
7.0 TO RUN WITH

STANDARD CIRCUIT
Application Note 19 has more details on the theory of slope
(C)
6.5 (C) MINIMUM VOLTAGE compensation.
TO START WITH
PNP There is a sync-supply sequence issue with the LT1375. If
6.0 (D) (D) MINIMUM VOLTAGE
TO RUN WITH power is supplied to the regulator after the external sync
5.5 PNP signal is supplied, the regulator may not start. This is
caused by the internal frequency foldback condition that
5.0
0.001 0.01 0.1 1 occurs when the FB pin is below 1V (see block diagram
LOAD CURRENT (A) 1375/76 F09
description in the data sheet). The oscillator tries to run at
100kHz when the FB pin is below 1V, and a high frequency
Figure 9. Minimum Input Voltage sync signal will then create an extremely low amplitude
D1
oscillator waveform. This amplitude may be so low that the
1N914 switch logic is not triggered to create switching. Under the
C2
normal regulated condition, the oscillator runs at much
0.1µF D3 higher amplitude with plenty of drive for the switch logic.
1N914
Note that for fixed voltage parts, the FB pin is replaced with
BOOST L1
INPUT VIN VSW OUTPUT a SENSE pin, and the voltage divider resistors are internal.
LT1376-5 Q1 In that case, the FB pin drops below 1V when the output
2N3905
+ SENSE voltage is less than 40% of its regulated value.
GND VC
+ There are no sequence problems if the power supply for
C1
CC
the sync signal comes from the output of the LT1375. If
this is not the case, and the sync signal could be present
1375/76 F10
when power is applied to the regulator, a gate should be
Figure 10. Reducing Minimum Input Voltage used to block sync signals as shown in Figure 11. Any
other technique which prevents sync signals when the
SYNCHRONIZING (Available on LT1375 Only) regulator output is low will work just as well. It does not
matter whether the sync signal is forced high or low; the
The LT1375 has the BIAS pin replaced with a SYNC pin, internal circuitry is edge triggered.
which is used to synchronize the internal oscillator to an
external signal. It is directly logic compatible and can be
VIN
driven with any signal between 10% and 90% duty cycle.
LT1375 VOUT
The synchronizing range is equal to initial operating fre- SYNC
quency up to 900kHz. This means that minimum practical
sync frequency is equal to the worst-case high self-
oscillating frequency (560kHz), not the typical operating 1375/76 F11
frequency of 500kHz. Caution should be used when syn- Figure 11. Gating the Sync Signal
chronizing above 700kHz because at higher sync frequen-
cies the amplitude of the internal slope compensation
FREQUENCY COMPENSATION
used to prevent subharmonic switching is reduced. This
type of subharmonic switching only occurs at input volt- Loop frequency compensation of switching regulators
ages less than twice output voltage. Higher inductor can be a rather complicated problem because the reactive
values will tend to eliminate problems. See Frequency components used to achieve high efficiency also
19
LT1375/LT1376
U U W U
introduce multiple poles into the feedback loop. The Error amplifier transconductance phase and gain are shown
inductor and output capacitor on a conventional step- in Figure 14. The error amplifier can be modeled as a
down converter actually form a resonant tank circuit that transconductance of 2000µMho, with an output imped-
can exhibit peaking and a rapid 180° phase shift at the ance of 200kΩ in parallel with 12pF. In all practical
resonant frequency. By contrast, the LT1376 uses a “cur- applications, the compensation network from VC pin to
rent mode” architecture to help alleviate phase shift cre- ground has a much lower impedance than the output
ated by the inductor. The basic connections are shown in impedance of the amplifier at frequencies above 500Hz.
Figure 12. Figure 13 shows a Bode plot of the phase and This means that the error amplifier characteristics them-
gain of the power section of the LT1376, measured from selves do not contribute excess phase shift to the loop, and
the VC pin to the output. Gain is set by the 2A/V transcon- the phase/gain characteristics of the error amplifier sec-
ductance of the LT1376 power section and the effective tion are completely controlled by the external compensa-
complex impedance from output to ground. Gain rolls off tion network.
smoothly above the 100Hz pole frequency set by the
In Figure 15, full loop phase/gain characteristics are
100µF output capacitor. Phase drop is limited to about
shown with a compensation capacitor of 0.0033µF, giving
85°. Phase recovers and gain levels off at the zero fre-
the error amplifier a pole at 240Hz, with phase rolling off
quency (≈16kHz) set by capacitor ESR (0.1Ω).
to 90° and staying there. The overall loop has a gain of
3000 200
LT1375
LT1376 CURRENT MODE VSW PHASE
POWER STAGE OUTPUT 2500 150
gm = 2A/V ERROR
AMPLIFIER R1 GAIN
GAIN (µMho)
PHASE (DEG)
– FB 2000 100
VC
( )
ESR ROUT COUT
+ 2.42V 1500 VFB 2 • 10–3 50
200k 12pF
+
GND VC C1
1000 ERROR AMPLIFIER EQUIVALENT CIRCUIT 0
R2 RLOAD = 50Ω
RC
CF 500 –50
100 1k 10k 100k 1M 10M
CC
FREQUENCY (Hz)
1375/76 F14
1375/76 F12
Figure 12. Model for Loop Response Figure 14. Error Amplifier Gain and Phase
40 40 80 200
VIN = 10V
VOUT = 5V GAIN
PHASE: VC PIN TO OUTPUT (DEG)
IOUT = 500mA
GAIN: VC PIN TO OUTPUT (dB)
60 150
20 0
LOOP PHASE (DEG)
LOOP GAIN (dB)
GAIN
40 100
0 –40
20 PHASE 50
PHASE
–20 –80 VIN = 10V

0 VOUT = 5V, IOUT = 500mA 0
COUT = 100µF, 10V, AVX TPS
CC = 3.3nF, RC = 0, L = 10µH
–40 –120 –20 –50
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
1375/76 F13 1375/76 F15
Figure 13. Response from VC Pin to Output Figure 15. Overall Loop Characteristics
20
LT1375/LT1376
U U W U
77dB at low frequency, rolling off to unity-gain at 20kHz. proper operation of the regulator. In the marginal case,
Phase shows a two-pole characteristic until the ESR of the subharmonic switching occurs, as evidenced by alternat-
output capacitor brings it back above 10kHz. Phase mar- ing pulse widths seen at the switch node. In more severe
gin is about 60° at unity-gain. cases, the regulator squeals or hisses audibly even though
Analog experts will note that around 1kHz, phase dips very the output voltage is still roughly correct. None of this will
show on a theoretical Bode plot because Bode is an
close to the zero phase margin line. This is typical of switch-
ing regulators, especially those that operate over a wide amplitude insensitive analysis. Tests have shown that if
range of loads. This region of low phase is not a problem ripple voltage on the VC is held to less than 100mVP-P, the
as long as it does not occur near unity-gain. In practice, the LT1376 will be well behaved. The formula below will give
an estimate of VC ripple voltage when RC is added to the
variability of output capacitor ESR tends to dominate all
loop, assuming that RC is large compared to the reactance
other effects with respect to loop response. Variations in
of CC at 500kHz.
ESR will cause unity-gain to move around, but at the same
(R )(G )(V − V )(ESR)(2.4)

time phase moves with it so that adequate phase margin
is maintained over a very wide range of ESR (≥ ±3:1). C MA IN OUT
VC(RIPPLE ) =
What About a Resistor in the Compensation Network? (V )(L)(f)
IN
It is common practice in switching regulator design to add GMA = Error amplifier transconductance (2000µMho)
a “zero” to the error amplifier compensation to increase If a computer simulation of the LT1376 showed that a
loop phase margin. This zero is created in the external series compensation resistor of 3k gave best overall loop
network in the form of a resistor (RC) in series with the response, with adequate gain margin, the resulting VC pin
compensation capacitor. Increasing the size of this resis- ripple voltage with VIN = 10V, VOUT = 5V, ESR = 0.1Ω,
tor generally creates better and better loop stability, but L = 10µH, would be:
there are two limitations on its value. First, the combina-
tion of output capacitor ESR and a large value for RC may
cause loop gain to stop rolling off altogether, creating a VC (RIPPLE
( 3k ) 2 • 10  (10 − 5)(0.1)(2.4)
−3
)= = 0.144V
gain margin problem. An approximate formula for RC
where gain margin falls to zero is:
( )
10  10 • 10   500 • 10 
−6

3

This ripple voltage is high enough to possibly create

(
R C Loop Gain = 1 =) (G )(G )(ESR)(2.42)
VOUT
subharmonic switching. In most situations a compromise
MP MA value (< 2k in this case) for the resistor gives acceptable
phase margin and no subharmonic problems. In other
GMP = Transconductance of power stage = 2A/V cases, the resistor may have to be larger to get acceptable
GMA = Error amplifier transconductance = 2 × 10–3 phase response, and some means must be used to control
ESR = Output capacitor ESR ripple voltage at the VC pin. The suggested way to do this
2.42 = Reference voltage is to add a capacitor (CF) in parallel with the RC /CC network
With VOUT = 5V and ESR = 0.1Ω, a value of 5.17k for RC on the VC pin. Pole frequency for this capacitor is typically
would yield zero gain margin, so this represents an upper set at one-fifth of switching frequency so that it provides
limit. There is a second limitation however which has significant attenuation of switching ripple, but does not
nothing to do with theoretical small signal dynamics. This add unacceptable phase shift at loop unity-gain frequency.
resistor sets high frequency gain of the error amplifier, With RC = 3k,
including the gain at the switching frequency. If switching
5 5
frequency gain is high enough, output ripple voltage will CF = = = 531pF
appear at the VC pin with enough amplitude to muck up (2π)(f)(R ) C ( )
2π  500 • 103  3k
21
LT1375/LT1376
U U W U
How Do I Test Loop Stability? of high frequency (500kHz) ripple. The ripple makes it
The “standard” compensation for LT1376 is a 3.3nF difficult to observe the small transient, so a two-pole,
100kHz filter has been added. This filter is not particularly
capacitor for CC, with RC = 0. While this compensation will
work for most applications, the “optimum” value for loop critical; even if it attenuated the transient signal slightly,
compensation components depends, to various extent, on this wouldn’t matter because amplitude is not critical.
parameters which are not well controlled. These include After verifying that the setup is working correctly, I start
inductor value (±30% due to production tolerance, load varying load current and input voltage to see if I can find
current and ripple current variations), output capacitance any combination that makes the transient response look
(±20% to ±50% due to production tolerance, tempera- suspiciously “ringy.” This procedure may lead to an ad-
ture, aging and changes at the load), output capacitor ESR justment for best loop stability or faster loop transient
(±200% due to production tolerance, temperature and response. Nearly always you will find that loop response
aging), and finally, DC input voltage and output load looks better if you add in several kΩ for RC. Do this only
current . This makes it important for the designer to check if necessary, because as explained before, RC above 1k
out the final design to ensure that it is “robust” and tolerant may require the addition of CF to control VC pin ripple. If
of all these variations. everything looks OK, I use a heat gun and cold spray on the
circuit (especially the output capacitor) to bring out any
I check switching regulator loop stability by pulse loading
temperature-dependent characteristics.
the regulator output while observing transient response at
the output, using the circuit shown in Figure 16. The
regulator loop is “hit” with a small transient AC load
current at a relatively low frequency, 50Hz to 1kHz. This VOUT AT IOUT =
500mA
causes the output to jump a few millivolts, then settle back BEFORE FILTER
to the original value, as shown in Figure 17. A well behaved VOUT AT IOUT =
10mV/DIV 500mA
loop will settle back cleanly, whereas a loop with poor AFTER FILTER
phase or gain margin will “ring” as it settles. The number VOUT AT IOUT = 50mA
AFTER FILTER
of rings indicates the degree of stability, and the frequency
of the ringing shows the approximate unity-gain fre- 5A/DIV
LOAD PULSE
THROUGH 50Ω
quency of the loop. Amplitude of the signal is not particu- f ≈ 780Hz
larly important, as long as the amplitude is not so high that 0.2ms/DIV 1375/76 F17
the loop behaves nonlinearly.

Figure 17. Loop Stability Check
The output of the regulator contains both the desired low
frequency transient information and a reasonable amount
RIPPLE FILTER
470Ω 4.7k TO X1
SWITCHING OSCILLOSCOPE
REGULATOR PROBE
+ 100µF TO 3300pF 330pF
1000µF
50Ω
ADJUSTABLE ADJUSTABLE
INPUT SUPPLY DC LOAD TO
OSCILLOSCOPE
SYNC
100Hz TO 1kHz
100mV TO 1VP-P
1375/76 F16
Figure 16. Loop Stability Test Circuit
22
LT1375/LT1376
U U W U
Keep in mind that this procedure does not take initial Quiescent current loss:
component tolerance into account. You should see fairly
clean response under all load and line conditions to ensure
 2
(
 VOUT  0.002 )
that component variations will not cause problems. One
note here: according to Murphy, the component most
( )
PQ = VIN 0.001 + VOUT ( )
0.005 +
 
VIN
likely to be changed in production is the output capacitor, RSW = Switch resistance (≈ 0.4)
because that is the component most likely to have manu- 16ns = Equivalent switch current/voltage overlap time
facturer variations (in ESR) large enough to cause prob- f = Switch frequency
lems. It would be a wise move to lock down the sources of Example: with VIN = 10V, VOUT = 5V and IOUT = 1A:
the output capacitor in production.
(0.4)(1) (5) +  16 • 10  (1)(10) 500 • 10

A possible exception to the “clean response” rule is at very 2
light loads, as evidenced in Figure 17 with ILOAD = 50mA. −9 3
PSW =    
Switching regulators tend to have dramatic shifts in loop 10
response at very light loads, mostly because the inductor = 0.2 + 0.08 = 0.28W
current becomes discontinuous. One common result is
(5) (0.008 + 1/ 75) = 0.053W
2
very slow but stable characteristics. A second possibility
is low phase margin, as evidenced by ringing at the output PBOOST =
10
with transients. The good news is that the low phase
(5) (0.002) = 0.04W
2
= 10(0.001) + 5(0.005) +
margin at light loads is not particularly sensitive to com-
ponent variation, so if it looks reasonable under a transient PQ
10
test, it will probably not be a problem in production. Note
that frequency of the light load ringing may vary with Total power dissipation is 0.28 + 0.053 + 0.04 = 0.37W.
component tolerance but phase margin generally hangs in
there. Thermal resistance for LT1376 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
THERMAL CALCULATIONS about 120°C/W. No plane will increase resistance to about
Power dissipation in the LT1376 chip comes from four 160°C/W. To calculate die temperature, use the proper
sources: switch DC loss, switch AC loss, boost circuit thermal resistance number for the desired package and
current, and input quiescent current. The following formu- add in worst-case ambient temperature:
las show how to calculate each of these losses. These TJ = TA + θJA (PTOT)
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load With the SO-8 package (θJA = 120°C/W), at an ambient
currents. temperature of 70°C,
Switch loss: TJ = 70 + 120 (0.37) = 114.4°C
Die temperature is highest at low input voltage, so use
( ) ( ) + 16ns(I )(V )(f)
2
RSW IOUT VOUT lowest continuous input operating voltage for thermal
PSW = OUT IN calculations.
V IN
Boost current loss:
PBOOST =
2
(
VOUT 0.008 + IOUT / 75 )
VIN
23
LT1375/LT1376
U U W U
POSITIVE-TO-NEGATIVE CONVERTER Maximum load current:
( )( ) ( )(
The circuit in Figure 18 is a classic positive-to-negative
 
)
topology using a grounded inductor. It differs from the VIN VOUT
IP −  VOUT VIN − 0.5
standard approach in the way the IC chip derives its
feedback signal, however, because the LT1376 accepts

=
( )( )( )
2 VOUT + VIN f L 

( )( )
IMAX
only positive feedback signals, the ground pin must be tied VOUT + VIN − 0.5 VOUT + VF
to the regulated negative output. A resistor divider to
ground or, in this case, the sense pin, then provides the IP = Maximum rated switch current
proper feedback voltage for the chip. VIN = Minimum input voltage
D1
VOUT = Output voltage
1N4148 VF = Catch diode forward voltage
C2
0.5 = Switch voltage drop at 1.5A
0.1µF L1*
INPUT
4.5V TO
BOOST
VSW
5µH Example: with VIN(MIN) = 4.7V, VOUT = 5V, L = 10µH, VF =
VIN
20V
LT1376-5
0.5V, IP = 1.5A: IMAX = 0.52A. Note that this equation does
C3 +
10µF TO SENSE
not take into account that maximum rated switch current
50µF GND VC (IP) on the LT1376 is reduced slightly for duty cycles
+ C1
CC D2 100µF above 50%. If duty cycle is expected to exceed 50% (input
1N5818 10V TANT
RC
voltage less than output voltage), use the actual IP value
OUTPUT** from the Electrical Characteristics table.
–5V, 0.5A
* INCREASE L1 TO 10µH OR 20µH FOR HIGHER CURRENT APPLICATIONS. Operating duty cycle:
SEE APPLICATIONS INFORMATION
VOUT + VF
** MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE
DC =
AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION 1375/76 F18
VIN − 0.3 + VOUT + VF

Figure 18. Positive-to-Negative Converter
(This formula uses an average value for switch loss, so it
may be several percent in error.)
Inverting regulators differ from buck regulators in the
basic switching network. Current is delivered to the output With the conditions above:
as square waves with a peak-to-peak amplitude much
5 + 0.5
greater than load current. This means that maximum load DC = = 56%
current will be significantly less than the LT1376’s 1.5A 4.7 − 0.3 + 5 + 0.5
maximum switch current, even with large inductor values. This duty cycle is close enough to 50% that IP can be
The buck converter in comparison, delivers current to the assumed to be 1.5A.
output as a triangular wave superimposed on a DC level
equal to load current, and load current can approach 1.5A
OUTPUT DIVIDER
with large inductors. Output ripple voltage for the positive-
to-negative converter will be much higher than a buck If the adjustable part is used, the resistor connected to
converter. Ripple current in the output capacitor will also VOUT (R2) should be set to approximately 5k. R1 is
be much higher. The following equations can be used to calculated from:
calculate operating conditions for the positive-to-negative
converter.
R1 =
(
R 2 VOUT − 2.42 )
2.42
24
LT1375/LT1376
U U W U
INDUCTOR VALUE Minimum inductor discontinuous mode:
( )( )
Unlike buck converters, positive-to-negative converters
cannot use large inductor values to reduce output ripple 2 VOUT IOUT
L MIN =
(f)(I )
voltage. At 500kHz, values larger than 25µH make almost 2
no change in output ripple. The graph in Figure 19 shows P
peak-to-peak output ripple voltage for a 5V to – 5V con-
verter versus inductor value. The criteria for choosing the Minimum inductor continuous mode:
inductor is therefore typically based on ensuring that peak
switch current rating is not exceeded. This gives the
lowest value of inductance that can be used, but in some L MIN =
(V )(V )
IN OUT
cases (lower output load currents) it may give a value that

( )(
2 f VIN + VOUT )
  V +V
I − I  1 + OUT F( )
creates unnecessarily high output ripple voltage. A com-  P OUT  
 VIN 
promise value is often chosen that reduces output ripple. 
As you can see from the graph, large inductors will not
give arbitrarily low ripple, but small inductors can give For the example above, with maximum load current of
high ripple. 0.25A:
150
(5) (1.5) = 0.37A

5V TO –5V CONVERTER
OUTPUT CAPACITOR
2 2
OUTPUT RIPPLE VOLTAGE (mVP-P)
120 ESR = 0.1Ω

ICONT =
4(5 + 5)(5 + 5 + 0.5)
90
ILOAD = 0.25A
60
This says that discontinuous mode can be used and the
ILOAD = 0.1A minimum inductor needed is found from:
( )( )
30
2 5 0.25
L MIN = = 2.2µH
( )
0
0 5 10 15 20 25
 500 • 10  1.5
3 2
INDUCTOR SIZE (µH)

1375/76 F19
Figure 19. Ripple Voltage on Positive-to-Negative Converter

In practice, the inductor should be increased by about
The difficulty in calculating the minimum inductor size 30% over the calculated minimum to handle losses and
needed is that you must first know whether the switcher variations in value. This suggests a minimum inductor of
will be in continuous or discontinuous mode at the critical 3µH for this application, but looking at the ripple voltage
point where switch current is 1.5A. The first step is to use chart shows that output ripple voltage could be reduced by
the following formula to calculate the load current where a factor of two by using a 15µH inductor. There is no rule
the switcher must use continuous mode. If your load of thumb here to make a final decision. If modest ripple is
current is less than this, use the discontinuous mode needed and the larger inductor does the trick, go for it. If
formula to calculate minimum inductor needed. If load ripple is noncritical use the smaller inductor. If ripple is
current is higher, use the continuous mode formula. extremely critical, a second filter may have to be added in
Output current where continuous mode is needed: any case, and the lower value of inductance can be used.
Keep in mind that the output capacitor is the other critical
factor in determining output ripple voltage. Ripple shown
(V ) (I )
2 2
IN P on the graph (Figure 19) is with a capacitor ESR of 0.1Ω.
ICONT =
4(V + V )(V + V ) This is reasonable for an AVX type TPS “D” or “E” size
IN OUT IN OUT + VF
25
LT1375/LT1376
U U W U
surface mount solid tantalum capacitor, but the final Peak diode current:
capacitor chosen must be looked at carefully for ESR
characteristics. Continuous Mode =
Ripple Current in the Input and Output Capacitors (V ) + (V )(V )

IN + VOUT IN OUT
2(L)(f)(V + V )
IOUT
Positive-to-negative converters have high ripple current in V IN IN OUT
2(I )(V )
both the input and output capacitors. For long capacitor
OUT OUT
lifetime, the RMS value of this current must be less than
(L)(f)
Discontinuous Mode =
the high frequency ripple current rating of the capacitor.
The following formula will give an approximate value for
RMS ripple current. This formula assumes continuous Keep in mind that during start-up and output overloads,
mode and large inductor value. Small inductors will give average diode current may be much higher than with
somewhat higher ripple current, especially in discontinu- normal loads. Care should be used if diodes rated less than
ous mode. The exact formulas are very complex and 1A are used, especially if continuous overload conditions
appear in Application Note 44, pages 30 and 31. For our must be tolerated.
purposes here I have simply added a fudge factor (ff). The
value for ff is about 1.2 for higher load currents and Dual Output SEPIC␣ Converter
L ≥10µH. It increases to about 2.0 for smaller inductors at The circuit in Figure 20 generates both positive and
lower load currents. negative 5V outputs with a single piece of magnetics. The
two inductors shown are actually just two windings on a
Capacitor IRMS = ff IOUT( )( ) VOUT
VIN
standard Coiltronics inductor. The topology for the 5V
output is a standard buck converter. The – 5V topology
ff = Fudge factor1 (1.2 to 2.0) would be a simple flyback winding coupled to the buck
converter if C4 were not present. C4 creates the SEPIC
Diode Current (Single-Ended Primary Inductance Converter) topology
which improves regulation and reduces ripple current in
Average diode current is equal to load current. Peak diode L1. For details on this circuit see Design Note 100.
current will be considerably higher.
D2
1N914
C2
0.1µF
INPUT BOOST OUTPUT
VIN VSW
6V TO 25V 5V
L1*
LT1376-5 BIAS 10µH
SHDN SENSE
GND VC
+ C3
+ C1**
100µF
22µF RC 10V TANT
35V TANT 470Ω D1
CC 1N5818
0.01µF
GND
* L1 IS A SINGLE CORE WITH TWO WINDINGS C4** + + C5**

COILTRONICS #CTX10-2P 100µF L1* D3 100µF
** AVX TPSD107M010 10V TANT 1N5818 10V TANT
† IF LOAD CAN GO TO ZERO, AN OPTIONAL OUTPUT
PRELOAD OF 1k TO 5k MAY BE USED TO –5V†
IMPROVE LOAD REGULATION 1375/76 F20
Figure 20. Dual Output SEPIC Converter

1Normally, Jamoca Almond
26
LT1375/LT1376
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
0.300 – 0.325 0.045 – 0.065 0.130 ± 0.005 MAX
(7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127)
8 7 6 5
0.065
0.255 ± 0.015*
(1.651)
TYP (6.477 ± 0.381)
0.009 – 0.015
(0.229 – 0.381) 0.125
(3.175) 0.020
+0.035 MIN (0.508) 1 2 3 4
0.325 –0.015
( )
MIN
+0.889 0.100 ± 0.010 0.018 ± 0.003 N8 1197
8.255 (2.540 ± 0.254) (0.457 ± 0.076)

–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45° 0.053 – 0.069 0.004 – 0.010 8 7 6 5
(0.254 – 0.508)
(1.346 – 1.752) (0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254) 0°– 8° TYP
0.228 – 0.244 0.150 – 0.157**

0.016 – 0.050 (5.791 – 6.197) (3.810 – 3.988)
0.014 – 0.019 0.050
0.406 – 1.270
(0.355 – 0.483) (1.270)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SO8 0996
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD 1 2 3 4
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
27
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1375/LT1376
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16 15 14 13 12 11 10 9
0.228 – 0.244 0.150 – 0.157**

(5.791 – 6.197) (3.810 – 3.988)
1 2 3 4 5 6 7 8
0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0° – 8° TYP (0.101 – 0.254)
(0.203 – 0.254)
0.014 – 0.019 0.050

0.016 – 0.050
(0.355 – 0.483) (1.270)
0.406 – 1.270 TYP S16 0695
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1370 High Efficiency DC/DC Converter 42V, 6A, 500kHz Switch
LT1371 High Efficiency DC/DC Converter 35V, 3A, 500kHz Switch
LT1372/LT1377 500kHz and 1MHz High Efficiency 1.5A Switching Regulators Boost Topology
LT1374 High Efficiency Step-Down Switching Regulator 25V, 4.5A, 500kHz Switch
LT1375/LT1376 1.5A Step-Down Switching Regulators 500kHz, Synchronizable in SO-8 Package
LT1507 1.5A Step-Down Switching Regulator 500kHz, 4V to 16V Input, SO-8 Package
LT1576 1.5A Step-Down Switching Regulator 200kHz, Reduced EMI Generation
LT1578 1.5A Step-Down Switching Regulator 200kHz, Reduced EMI Generation
LT1616 600mA Step-Down Switching Regulator 1.4MHz, 4V to 25V Input, SOT-23 Package
LT1676/LT1776 Wide Input Range Step-Down Switching Regulators 60V Input, 700mA Internal Switches
LTC1735 High Efficiency Synchronous Step-Down, N-Ch Drive Burst ModeTM Operation, 16-Pin Narrow SSOP
LTC1735-1 High Efficiency Step-Down Controller with Power Good Output Fault Protection, 16-Pin SSOP and SO-8
LT1767 1.5A, 1.4MHz Step-Down DC/DC Converter Higher Current, 8-Lead MSOP Package
LTC1772 Constant Frequency Step-Down Controller in SOT-23 Higher Current, High Effieciency: Up to 94%
LTC1779 0.25A Micropower Step-Down in SOT-23 Lower Current, 100% Duty Cycle
LTC1877 High Efficiency Monolithic Step-Down Regulator 550kHz, MS8, VIN Up to 10V, IQ =10µA, IOUT to 600mA at VIN = 5V
LTC1878 High Efficiency Monolithic Step-Down Regulator 550kHz, MS8, VIN Up to 6V, IQ = 10µA, IOUT to 600mA at VIN = 3.3V
LTC3404 1.4MHz High Efficiency, Monolithic Synchronous Step-Down Up to 95% Efficiency, 100% Duty Cycle, IQ = 10µA,
Regulator VIN = 2.65V to 6V
Burst Mode is a trademark of Linear Technology Corporation.
13756fc LT/TP 0401 REV C 2K • PRINTED IN USA

Linear Technology Corporation
28 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1995
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

Features: Lt1375/Lt1376 1.5A, 500Khz Step-Down Switching Regulators

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Features: Lt1375/Lt1376 1.5A, 500Khz Step-Down Switching Regulators

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LT1375/LT1376

1.5A, 500kHz Step-Down

* RIPPLE CURRENT ≥ IOUT/2 50

BOOST 1 8 VC BOOST 1 8 VC GND 1 16 GND

θJA = 50°C/ W WITH FUSED CORNER PINS

LT1375CS8 LT1375IS8 LT1376CS8 LT1376IS8

Minimum Synchronizing Amplitude (LT1375 Only) VIN = 5V ● 1.5 2.2 V

SWITCH PEAK CURRENT (A)

TYPE 52 4 2.43 1.5

Kool Mµ is a registered trademark of Magnetics, Inc.

INPUT SUPPLY CURRENT (µA)

Shutdown Supply Current Error Amplifier Transconductance Error Amplifier Transconductance

2000 2500 150

500 1000 ERROR AMPLIFIER EQUIVALENT CIRCUIT 0

LT1376 Minimum Input Voltage

500 600 8.5

0.50 0.50 0.50

0.25 0.25 0.25

BOOST Pin Current VC Pin Shutdown Threshold Switch Voltage Drop

THRESHOLD VOLTAGE (V)

SWITCH VOLTAGE (V)

SLOPE COMP Σ BOOST

Figure 1. Block Diagram

Figure 2. Frequency and Current Limit Foldback

loop stability problems. Solid tantalum capacitor’s ESR dI 10

VOUT AT IOUT = 50mA

through the inductor into the output capacitor is:

Figure 4. Undervoltage Lockout

or latch low under low source voltage conditions. UVLO

The high speed switching current path is shown schemati-

GROUND RING NEED

DIRECTLY TO HEAVY GROUND CAPACITOR TO AVOID PARASITIC RESISTANCE

Figure 5. Suggested Layout

20ns/DIV 1375/76 F11

7.0 TO RUN WITH

–20 –80 VIN = 10V

(R )(G )(V − V )(ESR)(2.4)

This ripple voltage is high enough to possibly create

the loop behaves nonlinearly.

Figure 16. Loop Stability Test Circuit

(0.4)(1) (5) +  16 • 10  (1)(10) 500 • 10

Boost current loss:

VIN − 0.3 + VOUT + VF

cases (lower output load currents) it may give a value that

(5) (1.5) = 0.37A

120 ESR = 0.1Ω

Figure 19. Ripple Voltage on Positive-to-Negative Converter

Ripple Current in the Input and Output Capacitors (V ) + (V )(V )

* L1 IS A SINGLE CORE WITH TWO WINDINGS C4** + + C5**

Figure 20. Dual Output SEPIC Converter

8.255 (2.540 ± 0.254) (0.457 ± 0.076)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

0.228 – 0.244 0.150 – 0.157**

0.228 – 0.244 0.150 – 0.157**

0.014 – 0.019 0.050

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

13756fc LT/TP 0401 REV C 2K • PRINTED IN USA

Datasheets for electronics components.

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* L1 IS A SINGLE CORE WITH TWO WINDINGS C4 + + C5