MicrocontrolJer (MSBTE) 1-2 Winter 2008

Microcontroller
the byte or character and also used to set the receiving mechanism to prepare for
Chapter 1 : Peripheral Devices [Total Marks - 4] the reception of the next character. A common kind of start-stop transmission is
ASCII over RS·232, for example for use in teletypewriter operation
Q. 1 I Describe synchronous and asynchronous data transfer techniques used

I •.:
in microprocessor. (4 Marks)
Mark -+j~~~~:-:=
!.~.I.a .. ~.~~~i-~~-1ldJe ~,6 o~7 da.~_~~~.

l nchronous communication:

With
themselves
synchronous commWlications,
to each other, and then continually
the two devices
send characters
initially
to stay in sync.
synchronize
Space
y:

Bit time
.

Synchronous communications allows faster data transfer rates than asynchronous

methods, because additional bits to mark the beginning and end of each data byte '- -----.,.--
Characlerframe
-'
are not required. In this communication dala bytes are transfa-red one after
another and so on up to end.
Before sending data bytes, special character called as synchronous Fig. 2 : Format of asynchronous serial communication

character is send by the transmitter to achieve the synchronization between

transmitter and receiver. Initially, the output line of the transmitter is high i.e. at Chapter 2: Programmable "0 Devices [Totar Marks ~36]
marking state. To start the transmission, first the synchronous character is
Q.1(b) Draw and label block diagram of Ie 8755. (4 Marks)
transmitted by the transmitter and then data bits. Once the data bits are started the
Ans. :
transmitter will go on sending data bits as shown in Fig. 1.
AS-Al0
READY 8755
PORT A
ro/M
ADO-AD7 :8'>-+- PAD-PAl

eE,
PROGfC'E"l
ALE
RESET
1m
Fig. 1 : Synchronous serial communications j(jJ1
lOW
eLK
Asynchronous communication:
Voo
Asynchronous serial communication describes an asynchronous Vcc
transmission protocol in which a start hit is sent prior to each byte or character GND
and a stop bit is sent after each data byte as shown in Fig. 2. The start bit is used
to synchronize transmitter and receiver. The stop signal is used to indicate end of Fig. 3
 1-3 Microcontroller (MSBTE) 1-4
Microcontroller (MSBTE) Winter 2008 Winter 2008

Q. 1 (c) Compare between microprocessor. microcontroller and microcomputer. Q.4(a) Draw complete interfacing diagram of Ie 8085 with IC 8155. Write a

Ans. : program to read dala from po~ of 8155 and out it ~rt B. (8 Marks)
(4 Marks)
Ans .
The 8155 has inbuilt de-mulliplexing circuitry to de-multiplexed
S,. Few instruction
InbuiltTimer
Inbuilt
I/O Ports
Separate
Many
Boolean
Inbuilt RAM
are or to
Microcontroller
available.
ROM
multifunction
serial
operation
memory
port i.e.
pins Ie.
read/write
Do
ill
to store
Many not
not
not
rend/write
external
possible
Boolean
Program
Less
011 same havehave
have
instruction
directly.
portsoperation
and
Microprocessor
I/O are inbuilt
inbuilt
memory
dnta data
not
multifunction toisTimer
inbuilt
from/to RAM
arc
not serial
or
stored
available,
pins on addrtss/data bus i.e. ADo-Ao, using ALE signal. Hmce, extanal circuitry for do-
nal bit8.is
idual 8155
like
ROM or
8250
requires
pon,
1. 8255
or 825extra
extra
requires I.device like
devices multiplexing of AD bus is not required; the ADo-AD7 lill(~ of 8085 can be

directly connected to ADo-AD7lines of8155, The control signals RD, WR and

101M
----
of 8085 can also be connected directly to the corrtsponding pins of8155,
so no need 10 generate control signal like lOW, lOR, MEMR and MEMW
using decoder. The RESET OUT of 8085 can be connected directly to RESET
--
related opcr~tions.
pin Of8155\ The 8155 requirts a CS signal to select cbip during 110 or memory

A"
\A" G2A 'WB 01

~of8155
A"~C 74~~~38

I \ _\"~12 B
A DecOder V 4

\ Fig. 4 : Chip select decoder logic for 8155

Hence il c~ be generated using address line AwAls and 3:8 decoder, the
Q. 2(d) Give the features of IC 8255. (4 Marks) chip select decoder Iflgic is shown in Fig. 4.The complete intcrfacing of8155
Ans. :

It has 24 Programmable I/O Pins organized as a three 8 bit pons. Fully

TTL Compatible. High Speed, No "Wait State" Operation with 5rvIHzand 8MHz
8086 IUld8088. Direct Bit SetlR~et Capability is available Pon C. Enhanced
Control Word Read Capability. Suppon tliree operating modes i.e. Mode 0 -
Simple 1/0, Mode I - HandshakeJStrobcd I/O, Mode 3 - Strobcd handshake
."' •• '"~oo •••• 00.,_,"",
bidirectionalI/O.
 Winter 2008 Microcontroller (MSBTE) 1-6 Winter 2008
MicrocontroUer (MSBTE) 1-5

TableB

A~5 III
0I0I0A4H
0IA2
A3H
A2H
Au
A13
l'A5H
IAOH
AIH
A"
Addr«:ss
Port
CWR
~PortA
TimcrLSB
TimerMSB
A;Port
PortB C Select Ports
ADD-AD? IIII Used
I ADD-AD?
1-
portAl~
10 generate CS signal
ALE ALE

lo/Kif IOIM
8 bit
lID
lID Port B I<::==:>
WR WR
8085
6 bit
Microprooessor
Port C I<::==:>
ResetOul Reset

Configure Port A as an Input, Port B as an Output aTld Port C as an

Output. Hence the amtro1 word of8155 is given below.
A"
Control Word:
A"
=ODH

A"
A"
A"

Fig_5 : Interfacing of 8155 with 8085 in I/O mappe{ I/O

0wi~~: f~*:bi:~~
,--
as ~~~: 8 memory locations ifd~njt care X are treated
Program

MVI A,DO H ; Write control word to initialize 8155

OUT CWR : PA"" Input, p.=Output, Pc••Output
1 I AOFFH IN Port_A ; Read data from Port A

OUT Port_B ; Write Data to Port B

Used to gtnarate CS signal I Not Used I Connected internally \0 8155 memory
HlT ; Stop
The address of the Port A, B, C and CVfR will be as shown in Table B
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Microcontroller (MSBTE) 1-7 Winter 2008 MicroconlroJler (MSBTE) 1-8 Winter 2008

Q.5(a) Draw the complete interfacing diagram of IC 8085 with DAC using 8255.
Write a program to generate staircase wave. (8 Marks) =80H
Ans. :
The complete interfacing of DAC 0808 with microprocessor using 8255
PPI in I/O mapped I/O is shown in Fig. 6.

Port C upper = Output

Fig. 7

Using DAC 0800, the different waves signal can be generated such as
square wave, triangular wave, saw-tooth wave, staircase tic.

LXI Sp, FFEF H ; initialize stack pointer

MVJ A, 80H

OUT CWR • ; initialize 8255 PPI

MYIA, 01 H

VEE __ 15V
OUTPort_B ; enable latch

UP, MVr B, FF H
UPl: OUT Port_A ; send data to DAC

OCR B ; increment cooot

Fig. 6 : Interfacing of DAC 0808 with 8085 using 8255 PPI MOV A,S
cpr 00 H ; compare with max cooot
Now, the DO-07 pins ofDAC 0800 are conneGted to port A pins Le. P~-
PA7• The DAC0800 has a current output on lOUT pin' s~ LF 351 should be used to JZUP
conven current into voltage signal as shown in Fig. A. The control word to CALL delay ; add delay
initialize 8255 is given below where Port A is configured as an output in mode O. JMPUPI ; continue same processes
The remaining ports Le. Port B and Port C are not used in interfacing of
Q.6(a) Interface a stepper motor to IC 8085 using 8255 and write a program to
DAC 0800 with 8085 microprocessor.
run motor in clockwise direction. (8 Marks)

Ans. : An ordinary DC motor will turn aroWld and aroWld as long as power is
supplied. No intelligent circuitry is required to drive such a motor, unless you

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Microcontroller (MSSTE) 1-9 Winter 2008
1-10 Winter 2008
\ Microcontroller (MSBTE)
want to slow it down or rev(.1'SC direction - jusl apply power and it spins. A
stepper mOlar is very different. If you just feed it power, it will slay where it is. In
order to make !.he motor Olove, you have to feed it a c111Ulging signal.

StlllPcr motor can be interfaced with 8085 cru using 8255 PPI as shown
in Fig. 8. Stepper motor has four windings i.e. A, B, C, D and connected to PAl,
PA", PAl ami p~ ofa Port A 01'8255. The speed of motor CWI be controlled by
adding delay in steps normally wrilh:11 as a subroutine and direction call be
controlled by loading bit pUIICIlI for steps in reverse or forward direction as
shown below:

Bits patlern to rotatc stcppa- motor in half stepping method arc givcn
Table B wherc one bit is changed at a time for 0.90
Table B

A 8CODE!
1010C
000
000
01 0D
01
102
010
09
05
OA011 H
08
06H
04H H
H
H

Fig. 8 : Interfacing of stepper motor with 8085 using 8255PPI

Control Word for 8255 PPI

=80H

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 Microcontroller (MSBTE) 1-11 Winter 2008 Microcontroller (MSBTE) 1-12 Winter 2008

Program
A,
CUPl 80
LXI
H
UP
CWR
Port_A
H,
C
Sp, C200
08 H to
HA, HH
FFEO M Rotate
;;.; If
Write
InitiaLize
decrement
InitiaLize
Initialize
Read
increment inPort
toadd
byte;bits clockwise
8255
Byte
byte
counter
memory
stack
pattern
memoryPPI
Acounter
deLay counter
between
0pointer
then
Le. direction
gobyfor
pointer
pointer
step to 1 UPl
steps
code
for lookusing
took up half
tabLestepping method
uptabLe Ans. :
Continuous rotation
T
LXI

After the execution of above program, stepper motor starts to rotate in

clockwise direction continuously.

Chapter 4 : 8051 Microcontroller [Total Marks· 28]

Q.1(d) Draw and label block diagram of Ie 8051. (4 Marks)

T
Fig, 9
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Microcontroller (MSBTE) 1w13 Winter 2008

14. SP - Stack pointer

Q. 2(a) Explain the function of EA pin in detail. (Chapter 4) (4 Marks) 15. peON -Power control register
Ans. :
16. DPTR - Data pointer register
EA must be strapped to Vss in order to enable the 8051 to fetch code from 17. TUHOIl - Timer registers
External Program Memory locations starting at OOOOH up to OFFFFH. Note, Q.2(c) Interface the external memory with IC 8051 and explain how data is
however, that if either of the U:JckBits is programmed, the logic level at EA is transferred .. (4 Marks)
Ans. : In case on-chip memory is not enough, it is possible to add two external
internally latched during reset for EPROM only. EA must be strapped to vee memory chips with capacity of 64Kb each.
for internal program execution.
VQ ports P2 and P3 are used for their addressing and data transmission as
Q. 2(b) What is a special function register? list all the SFR's in 8051 shown in following Fig. 10.
microcontroUer. (4 Marks)
Ans. :

SFRs are a kind of control table used for running and monitoring
microcontroller's operating.
Each of these registers, even each bit they include, has its name, address in
the scope of RAM and clearly defined purpose ( for example: timer control,
interrupt, serial connection etc.). Even though there are 128 free memory
locations intended for their storage, the basic core, shared by all types of 8051
controllers, has only 21 such registers
List of SfR is given below
I. A - accumulator
2. B-register
3. PSW - Program status word
4. IP - Interrupt priority register
5. P3 - port 3 register
6. IE - Interrupt enable
7. P2 - Port 2 register
8. SeON - Serial control register
9. PI - Port 1 register
10. TeON - Timer control register
II. SBUF - ~erial buffer
12. PO- Port 0 register F;g.10
13. TMOD - Timer mode register
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Microcontroller (MSBTE) 1-15 Winter 2006 Microcontroller (MSBTE) 1-16 Winter 2008

registers. Be;ides, the DPTR Register is usually used for storing data and
The 8051 microcontroller has two separate reading signals -!ill (P3.7) and intermediate results which have nothing to do with memory locations.
PSEN. The first one is aclivatoo byte from external data memory (RAM) should a 0 a a a a a a Value afttt' Re;et

~~e:~ (~~i~.~:~ .;~e st~~~;~~ci~~/~o~: ::(O~lt=l~ program

When the program during execution encounters the. instruction which
DPLI
bit7
I
bit6
I
bit5
I
bit4
I
bit3
I
bit2
I
bitl
I
bita
I Bit name

re;ides in external memory (ROM), the microcontroller will activate its control
output ALE and set the first 8 bits of addre;s (AO-A7) on PO. In this way, IC o 0 0 0 0 0 0 0 Value after Reset
ein.'llit 74HCT573 which "lets in" the first 8 bits to memory addre;s pins is DPHI I I I I I I I I Bit name
activated. bit? bit6 bitS bit4 bitJ bit2 bit1 bitO
A signal' on the pin ALE closes the IC circuit 74HCT573 immediately
after 8 higher bits ofaddre;s (A8-AI5) appear on the port. Fig. 11 , DPTR
In this way, a de;ired location in additional program memo;")' is Program Counter PC :
completely addressed. The only thing left over is to read its content. Pins on PO
The 16 bit program counter register is an engine which starts the program
are configured as inputs, the pin PSEN is activated and the microcontroller reads execution and indicates the address in memory from which next instruction is to
content from memory chip. The same connections are used both for data and be fetched. Immediately after its execution, the value of the program counter is
lower addre;s byte. Similar occurs when it is a needed to read some location from incremented by 1. For this automatic increment, the program executes one
external Data Memory. Now, addressing is performed in the same way, while instruction at a time as it is wrinen.
reading or writing is performed via signals which appear on the control outputs Howevcr... the program counter value could be changed at any moment, .
RDorWR. which will cause '~ump" to a new location in the program memory. This is how
subroutines or branch instructions are executed

(4 Marks)
SP Register (Stack Pointer, Address 81h) :
Q. 3(b) Describe the fUl1ction of DPTR. PC and Stack Poil")ter.
Ans. ; This is the stack pointer of the microcontrollcr. This SFR indicate; wha-e
the next value to be taken from the staCkwill be read from in Internal RAM. If
DPTR Registers (DPUDPH (Data Pointer Low/High, Addre;se; 82h183h)
you push a value onto the stack, the value will be written to the addre;s ofSP + 1.
The SFRs DPL and DPH work together to represent a 16-bit value called
That is to say, if SP holds the value 07h, a PUSH instruction will push the
the Data Pointer. The data pointer is used in operations regarding external RAM
value onto the stack at address 08h. This SFR is modified by all instructions
and some instructions involving code memory. Since it is an unsigned two-byte
which modif)' the stack, such as PUSH, POP, LCALL, RET, RETI, and wheneva-
integer value, it can represent values from oooaH to FFFFH (0 through 65,535
decimal). interrupts are provoked by the microcontrolleT.
A value of the Stack Pointer ensures that the Stack Pointer will point to
The;e registers are not true ones because they do not physically exist.
They consist of two separate registers: DPH (Data Pointer High) and (Data valid RAM and permits Stack availability. By starting each subprogram, the
value in the Stack Pointer is incremented by I. In the same manner, by ending
Pointer Low) as shown in Fig. Their 16 bits are used for external memory
addressing. They may be handled as a 16-bit register or as two independent 8-bit subprogram, this value is decremented by I. After any reset, the value 7 is written
to the Stack Pointer, which means that the lopaceof RAM reserved for the Stack
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Microcontroller (MSBTE) 1-17 Winter 2008
Microcontroller (MSBTE) 1-18 Winter 2008

starts from this location. Ifanother value is written to this register then the entire
Stack is moved to a new location in the memory.
(il) INC@Rp'
INC instruction increments the indicated byte variable by one. Alx>ve
o 0 0 0 0 I I J Value after Rcset
instruction increment tIle memory location addressed by the register Rp An
original value of OFFH overflows to OOH. No flags are affected. Rp varies £i:om
SP I I Bit name RO to R7 in bank 0 or I in internal RAM.
bit7 bit6 bitS bit4 bit3 bit2 bit! bitO
Q.1{t) List the different addressing modes of microcontroller 8051. (4 Marks)
Q.4(C) Give any two examples to prove the importance of Boolean processor. Ans. :

(8 Marks) (a) ]rnmc<Jiate addressing:

Ans. : The 8051 instruction set is optimized for the one-bit operations so often Immediate addressing is so-named because the value to be stored in
desired in real-world, real-time control applications. The Boolean processor
memory or register immediately follows the operation code ill memory.
provides direct support for bit manipulation. This leads to more efficient
For example MOV A, #20H; This instruction uses immediate addressing;
programs that need to deal with binary input and output conditions inherent in
because the accumulator will be loaded with the value; that immediately follows
digital-control problems. Bit addressing can be used for test pin monitoring or
in this case20H.
program control flags. For example, instructions for Boolean function are as
given below. (b) Direct addressing:
(a) ORL PO, #1 ; Set PO.O Direct addressing is so-named because the value to be stored in memory is
(b) XRL PO, #1 ; TogglePO.O obtained by directly retrieving it from another memory location.
(c) ANL C, PIA : AND the bit on PIA with carry. For example
(d) ANL C, l(PtA) ; AND inverted bit on PIA with carry MOV A, 30H : This instruction will fead the data from internal; RAM
The above instruction can be used monitor the status of any bit of Ports Le. address 30H and store it
in the Accumulator.

PI, P2, P3, PO which may be used in instrumentation.

(c) Indirect addressing (Register Indirect) :

Chapter 5 : MCS·51 Addressing Modes Indirect addressing is a very powerful addressing mode which in many
and Instructions [Total Marks· 24} cases provides an exceptional level of flexibility. In this addressing mode, vnly
register RO and Rl can be used as a pointer for the indirect operation. The register
Q. 1(e) Describe the function of following instruction of IC 8051. (4 Marks) points the memory location from which required data can be read or write.
(i) MOV A. @Rp (ii) INC@Rp For example
Ans. : MOV A, @RO : load tIle accumulator with the value from Internal
; RAM which is fOWId at the address indicated by RO.
OJ MOY A, @Rp ,
(d) Register addressing:
The byte variable addressed by the Registcr Rp is copied into A register.
The source byte is not affected. No otha-register or flag is affected. Rp varies In this addressing mode, all operand i.e. source and destination are located
from RO to R7 in bank 0 or 1 in internal RAM. in working registers i.e. RO to R7, DPTR, B and A afthe microcontroller. In this
addressing mode, instruction may have one or two operands.
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Microcontroller (MSBTE) 1-19 Winter 2008
Microcontroller (MSBTE) 1-20 Winter 2008

For example
MOV RJ, A : Copy the contents of Accumulator into R3 register memory. The instruction with 'C' in mnemonic is used to access internal and

MOV A, B : Copy the contents of B register to Accumulator external program memories. The mnemonic sj1Ilbol used for this addressing
mode is '@' sign. The length of this instruction always I byte.
Q.4{b) With the help of ANL instruction explain (8 Marks) For example:
(i) Direct addressing mode ANLA,@RO
This instruction will read the data out of Internal RAM whose address is
(ii) Indirect addressing mode
(iii) Register addressing mode stored in RO and perfonns the bitwise logical-AND operation with Accumulator,
store result in Accumulator. Register Addressing
(iv) Immediate addressing mode of 8051 Microcontroller
In this addressing mod<; all operand i.e. source and destination are located
Ans. :
in working registers i.e. RO to R7, DPTR, B and A of the microcontroller. Source
Direct addressing mode: and destination registers are specified by op-code itself. So, the length of
Direct addressing is so-named because the value to be stored in memory is instruction in this addressing mode is One byte. In this addressing mod<;
obtained by directly retrieving it from another memory location. However, the instruction may have one or m'o operands.
address of the opcnmd (data) memory location is specified by instruction itself. In For Example
this mode, the source and destination or both operands can be data memory ANLA, B
location .•
This instruction will performs the bitwise logical-AND operation
Hence the length of instruction is 2 byte for one memory operand and 3 between Accumulator and B register, store result in Accumulator.
byte Jor two memory operands. In this mode, the internal registers accept PC can
be used as dal3. memory location. This type of instruction can not be used to Immediate addressing:
.access external data memory. The address of the data memory is always g bit. Immediate addressing is so-named because the value to be stored in
The SFR's can be used as a data memory location.
memory or register immediately follows the operation code in memory. That is to
For example: say, the instnlction itself dictates what value will be stored in memory. The way,
ANLA,30H we identifY and use the immediate addressing method, is by using # sign.
This instruction will read the data out ofIntemal RAM address 30H and When any number (Operand) is preceded by tlJ.e /I sign then the addressing
performs the bitwise logical-AND operation with Accumulator, store result in of the instruction will be immediate addressing mode. This addressing mode can .
Accumulator. be used when number is to be place in a register or memory location.
Indirect Addressing (Register Indirect) : Hence the len.gth of the instruction is 2 byte for 8 bit operand and 3 byte
Indirect addressing is a very powerful addressing mode which in many for 16 bit operand.
cases provides an exceptional level Of flexibility. In this addressing mode, only For example
register RO and RI can be used a<; a pointer for the indirect operation. ANLA,#OFH
The register points the memory location from which required data can be This instruction will performs the bitwise logical-AND opcration between
read or write. Using this addressing mode, one can access data from internal and Accumulator and immediate data OFH, store rendt in Accumulator.
external data memories.
The instruction without 'X' in mnemonic is used to access internal data Q. 6(b) Write a program to add' two BCD numbers. Draw the flowchart also.
Store result in the data memory location. (8 Marks)
memory. The instruction with 'X' in mnemonic is used to access external data
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 MicrocontroUer (MSBTE) 1-21 Winter 2008
Microcontroller (MSBTE) 1-22 Winter 2008

Ans. : Suppose two BCD data bytes are stored in memory locations 3000H and
Program:
300lH. Write a program to add these two bytes from external memory locations
and store result in memory location 3002H of the external memory. MOV ,DPTR, 113000H ; Initialize memory pointer to external memory
Algorithm: MOVX A, @DPTR ; Read fitst number in Accumulator
Step 1 Initialize memory pointer using DPTR register with 3000H MOV RO,A ; Store in RO Register
Step 2 Load first BCD number from the memory location 3000H INC DPTR ; Increment memory pointer by I
Step 3 Increment memory pointer by 1 MOVX A, @DPTR ; Load second number- in Accumulator

Step 4 Load second BCD number from memory location 300lH ADD A,RO ; Add first number with second number
Step 5 Add both BCD numbers and Adjust the result to BCD DAA ; Adjust result to BCD
INC DPTR ; Increment memory pointer by I
Step 6 Store Result in memory location 3002H by incrementillg memory
Pointer MOVX @DPTR, A ; Store result to external memory

Step 7 Stop
LOOP, AJMP LOOP ; Stop

Chapter 6 : Assembly Language

Programming [Total Marks - 16]

Q.5(b) Describe DB, ORG, EQU END directive of Ie 8051 microcontroller.

(8 Marks)
Ans. :

DB Directive:

This directive is used for writing indicated value to program memory. If

several values are indicated one after another then they are separated by commas.
If ASCII array should be indicated it is enclosed with single quotation
marks. This directive can be used only if the segment CSEQ is active.
For example:
CSEG
DB 22,33, 'Alarm' ,44
When written before this directive, the label will point to the first value in
the array (in this example number 22).

ORG Directive:

This directive is used to define location in program memory where the

program following directive is to be placed.

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 Mlcrocontroller (MSBTE) 1-23 Winter 2008 Microconlroller (MSBTE) 1-24 Winter 2008

For example: Flowchart :

BEGINNING ORG 100

ORG 1000h
TABLE.

Program begins at location 100. The table with data will start at location
1024 (1000h).

EQ U Directive:

By means of this directive, a numeric value is replaced by a symboL

For example: Flowchart A
MAXIMUM EQU 99
Program:
After this directive, every appearance of the label "MAXIMU11" in the
program, the assembler will interprete as number 99 (MAXIMUM =:: 99). CLR P1.0 ;Clear Port I bits
It is only once possible to define symbols in this way so the EQU directive CLRPJ.4
is mostly used at tlle begilming of the program. CLRPL6,
END Directive: CLRP1.7
SETB PI.I ;Set Port I Bits
This directive must be at the end of every program. Once it encounters this
SETB P1.2
directive, the assemhler will stop interpreting program into machine code.
For example: SETB PT.3
SETB PIA

END ;End of program LOOP, AJMP LOOP ; Stop

Q.6(c) Write a program to set bit 1, 2, 3, 5 of Port 1 to 1 and reset the

remaining bits of Port 1 if IC 8051. (8 Marks) Chapter 7 : MCS~51 Timers/Counters, Interrupts
Ans. : and Serial Communication [Total Marks - 20J

Algorithm:
Q. 3(a) Explain the operating modes of IC 8051 timer. (4 Marks)
Step 1: Set Port 1 Bits 1,2,3,5. Ails.: Timcr- moderegistu sdxts mQoe of the timers TO and Tl.
Step 2: Res~ Port 1 Bits 0,4,6,7
St'-'t) 3: Stop

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 1-26 Wint.er 2008
Microcontroller (MSBTE) 1·25 Winter 2008 Microcontrolier (MSBTE)

chosen value (0- 255) saved in another register. The advantages of this way of
Table B
counting are described in the following example:
TnM1 Split
12TuMO
16·bittimer
310
8-bit Mode
.13-bittimer
auto-reload
Description
timer mode Suppose that for any reason it is continuously needed to count up 55
pulses at a time from the clock generator. When using mode I or mode 0, it is
needed to write number 200 to the timer registers and check constantly alterwards
wbether overflow occurred, i.e. whether the value 255 is reached by counting.
When it has occurred, it is needed to rewrite number 200 and repeat the
whole procedure. The microcontroller performs the same procedure in mode 2
automatically. Namely, in this mode it is only register TLOoperating as a timer
Mode 0 (13 Bit Timer) : (nonllally 8-bit), while the value from which counting should start is saved in the
THOregister.
This is onc of the rarities being kept only for compatibility with thl
previous versions of the microcontrollers. When using this mode, the higher b)tl Mode 3 (Split Timer Mode) :
THOll and only the first 5 bits of the lower byte TLO/I are in use. Beinl By configuring Timer 0 to operate in Mode 3, the 16-bit counter
configured in this way, the Timer 0 uses,only 13 of all 16 bits. With each nC\i,consisting of two registers THO and TLO is split into two independent 8-bit
pulse coming, the state of tile lower register (that one with 5 bits) is changed. timers. In addition, all control bits which belonged to the initial Timcr I
After 32 pulses received it becomes full and automatically is reset, whih (consisting of the registers THI and TLl), now control newly created Timer 1.
the higher byte THon is incremented by 1. This action will be repeated unti This means that even though the initial Timer I still can be configured to
registers count up 8192 pulses. After that, both registers are reset and countin! operate in any mode (mode I, 2 or 3), it is no longer able to stor, simply because
starts from O. there is no bit to do that. Therefore, in this mode, it will uninterruptedly "operate
in the background".
Mode 1 (16 Bit Timer) :

All bits from the registers THOand TLOare used in this mode. That is wh]
for this mc.deis being more commonly used. Counting is performed in the SaID(
way as in mode 0, with difference that the timer counts up to 65 536, i.e. as far al
the use of 16 bits allows

Mode 2 (Auto Re-Ioad Timer) :

What does auto·reload mean? Simply, it means that such timer uses ani)
one 8-hit register for COWlting,but it never counts from ° but from an arbitrar)easy solution
easy solution
 Microcontroller (MSBTE) 1·27 Winter 2008 Microcontroller (MSBTE) 1·28 Winter 2008

Mode 1 of UART :
Q. 3(c) Explain the operating modes of serial port of IC 8051 microcontroller.
(4 Marks) In Mode 1, ten hits are transmitted through TXD or received through RXD
Ans. : Serial port should be configured prior to being used. using SFR SCON in the following rnalUler :
Register as given below. (a) START bit (always 0), 4rst
Yalue after (b) Then 8 data bits (LSB fil'~t! (c) STOP bit (always J) last.
'oset
The START bit is not regis,ered in this pulse train. Its purpose d to start
SCON -I S-M-O-jS-M-l-'-S-M-2-I-REN--j-T-B-g-I-RB-g-I-T-l
-I-R-I-I Bit name
dala receiving ntecb lIlism. On receive the STOP bit is automatically written to
bit7 bit6 bitS bit4 bit3 bit2 bitt bitO
the RE8 bit in Dill SCON register.
Fig. 12: Format of SCON register Mode 2 ofu'\RT:
SMO and 8M! - bit seJects mode given in table A.
In mode 2, II bits are sent through TXD or received through RXD : a
SMO 8-bitUART
9-bitUART
8·bit Shift START bit (always 0), 8 data bits (lSB first), additional 9th data bit and a STOP
01SM!
Mode
302 Baud
1Description
1/32
frequency
JIl2 theRate
Determined
the quartz
quartz
by
Register
(1/64 the quartz the timer I
the timer I
frequency)
frequency bit (always I) last. On trallSlnit, the 9th data bit is actually the TB8 bit from the
UART
SeON rcgister. This bit commonly has the 'purpose of parity bit.
Upon transmission, the 9th data bit is copied to tlle RB8 bit in tlle same
register (SeON). The baud rate is eitllCf"1/32 or l/64 the quartz oscillator
frequency.

Mode 3 of UART :

Mode 3 is tllCsame as Mode 2 except the baud rate. In Mode 3, baud rate
is variable and Callbe selected using Timer I.

Q.3(d) Write the format of PCON register and explain. (4Marks)

Ans.: peON Register format is shown in Fig. 13.

Mode 0 of UART : o x x X 0 0 a a Value alter Reset

In mode 0, the data <U'etransferred through the RXD pin, while clock
PGON ISMOD~ijill1jl'iililliliiilll GFl I GFO I PO 1'0' I BUo,me
bit? bit6 bitS bit 4 bit 3 bit 2 bit 1 bitO
pulses appear on the TXD pin. The baud rat..:is fixed at 1/12 the quartz oscillator
frequency. On transmit/receive, the least significant bit (lSB bit) is being Fig. 13
sent/received first.
easy solution
easy solution
Microcon1ro!ler (MSBTE) 1-29 Winter 2008 1~"'1
Microcontroller (MSBTE) Winter 2008

The purpose of the Register peON bhs :

SMOD By setting tllis bit baud rate is doubled.
Aegistf:lf TCON
2. GFI General-purpose bit (available for use).
3. GFt General-purpose bit (available for use).

4. G~OGeneral-purpose bit (available for use).

5. PO By setting this bit the microcontrollcr is set into PO~1X:rDown mode.
6. lDL By setting this bit the microcontrcller is Sel into Idle mode

Q. 5(c) Explain the interrupts used in IC 8051 and how will you implement single oA
step operation in IC 8051. (8 Marks) R~rnterruPt
Ans. : w
z
There are five interrupt sources for the 8051 as shown in Fig. 14 which
~
means that they can recognize 5 ~ifferent events that can interrupt regular
program execution. Each interrupt can be enabled or disabled by setting bits in
the IE register. Also, as seen from the figure A, the whole interrupt system can be Fig. 14
disabled by clearing bit EA f!om the same register. Now, one detail should be Irtwo interrupts of equal priority requests arrive at the same time then the
explained which is not COmi)letelyobvious but refers to external interrupts- INTO interrupt to be serviced is selected according to the following priority list:
I. External interrupt INTO
and INTI.
2. Timer 0 illlerrupt
Namely, if the bits ITO and ITl stored in the TeON register are set, •
program interrupt will occur on changing logic state from I to 0, (only at the 3. Extcmallnterrupt INTI
moment). lfthese bits arc cleared, the same signal will generate interrupt request 4. Timer I interrupt
and it will be cOntinuouslyexecuted as far as the pins are held low. 5. Serial Comnnmicatioll Interrupt
The microcontrollers normally operate at very high speed. The use of 12
Ivfhzquartz crystal enable; 1.000.000 instructions per second to be executed! In
principle, there is no need for higher operating rate.
In case it is needed, it is easy to built~in crystal for high frequency. The
problem comes up when it is necessary to slow dowIl.

easy solution easy solution

Microcontroller (MSBTE) 1-31 Winter 2008
Microcontrolfer (MSBTE) 1·32 • Winter 2008
For example, when during testing in real operating awironment, several
inSlnlClions should be executoo step by step in ordcr to check for logic state of The second instruction is being executed until the push button is reJeasoo.

l/Opins. Immediately afta' tllat, the instruction RETl is executed and processor continues

executing the main program. Afta' each executed instruction, the intarupt INTO
Interrupt system applied on the 8051 micrOCOlltrollcrs prac~cally stops
is gen~ated and the whole procedure is repcalal ( push button is still pressoo).
operating and rnables instnlctions to be executed one at a time by pushing bunou.
Button Press::: One Instruction.
Two interrupt features enable that:
[J[J[J
Inlerlllpt request is ignored if an interrupt of the same priority level is
being ill progress.

Upon illltrrupt routine has been executed, a IH."W interrupt is not executed
until allC<1S1one instnlction from the main program is executed. In order to apply
this in practice, Ihe following steps should be done:

Exlernal intcmtpt sensitive to the signal level should be rnablo:l (for

example INTO).

2. Three following instlllctiolls should be enteral into the program (Slart

Irom "ddress 03hcx.):

~~~~~ J == ~::~:
___
;:::~
~:;:
~~::
:~:
::~
~~:~::~;~~::
::~
~:~:
:
Means: go back to the main program.

Fig. 15

Whal is going on? Once the pin P3.2 is sa 10 "0" (for example, by pushing
button), the microcontroller will interrupt program execution jump to the address I

0311cx, will be executed a mini-illl(.'rrupt rouline consisting of 3 instructions is

located al thai address. The first instnlclion is being cxecuted 1Ultil tIle push
button is pressed ( logic OIlC (I) on lhe pin P3.2).

easy solution
easy SOlution
 2-1 Summer 2009 MicrocontfolJer (MSBTE) 2-2 Summer 2009
Microcontroller (MSBTE)
A8-A10
READY 8355
I Summer 20091 IO/Fl
ADO-AD?

Chap_ter~_£!,_~_~Iphe~~evlces [Total Marks· 4] eE,

'O!',

Q.1(8) Compare between asynchronous and synchronous data transfer ALE

techniques. (4 Marks) RESET

Ans . Rll
IM
S" Used
Used
Two 10
fortransfer
data
Start separate
and bitolle
transR1'
stop clock
hardware al)d sofiw<1rc
Asynchronous
forinput
I
character
rate':::;
CilCh can
Data Transfer No
at used
aSynchronous
character
be
;::
is clock isand
transmitter
One
hardware.
20Kbits
character
Synchronization
Synchronous
Used to
implemented
Use::l
character.
at
high
character
I sec.
ausedreceivCl'.
time.
Data
for Iransferby
data for is
both
isTransfer
required
ausing
group
transfer
Slart and Stop bits are used.
and
of rate lOW
transmined along with group of t eLK
ence
5, I.
Vcc
GND
Fig. I

Q.2{d) Describe the function of fOllowing handshaking signals of 8255,

(I) IBF (ii) STB (iii) OBF (iv) ACK (4 Marks)

Ana. :

mF (Input Buffer Full) :

This is active high j;l.Ulput signal generated by 8255 to peripheral. A "high"
on this OUlput indicates that the data has been loaded into the input latch: in

essmce, and acknowledgment, so do nOI send next byte. IBF is set by STB input

being low and is reset by the rising edge of the RD input.

STB (Strobe Input) :

Chapter 2: Programmable I/O Devices {Total Marks· 28] This is an active low input signal to 8255. A "low" on this input loads data
into the input latch. This signal is generated by the peripheral to indicate data is
Q.1(b) Draw and label the block diagram of 8355. (4 Marks)
Ans. : available on input pon lines. The 8255 reads data hyte on receiving STB signal
and makes [BF signal high.
The 8355 contains 2K of ROM and 8755 contains 2K of EPROM. The
8355 has two 8 bit va pons. Each pon line is individually
input or output. An internal address latch to de-multiplexed
ALE signal
below.
and Can generate READY signal. Labeled
programmable

block diagram
as an
ADO-AD? by using
is shown
--
0iiF - (Output

The
OUI to the specified
easy SOlution
OBF
Buffer

output
Full) :

will go '1ow"
pon. This signal
to indicate
is generated
that the CPU has written
by 8255 for the
dala
output
Microcontroller (MSBTE) 2-3 Summer 2009
.. Microcontroller (MSBTE) 2-4 Summer 2009
peripheral to indicate data is available and latched on the port lme. Data IS
- Stepper motor can be interfaced with 8085 CPU using 8255 PPI as shown
guaranteed valid at the rising edge of OBF . The oaF Flip/flop will be set by in fig. 2. Stepper motor has four windings Le. A, B, C, D and connected,to PA],
. thedsing edge of the WR input and reset by ACK input being low. PA2, PAl and P~ ofa Port A of8255.

Control Word for 8255 PPI:

ACK - (Acknowledge Input) : 7 6 5 4 3
A "Jaw" on this inplll informs the 8255 that tlle data from Port A or Port B 1 I a I 0 I 0 I 0 =80H
is accepted by the output peripheral. In essence, the peripheral device generates
ACK signal indicating that data is accepted from tlle output port.

Q.4(a) Draw the interfacing diagram of stepper motor with microprocessor 8085
using Ie 8255. Write a program for rotating stepper motor by 1800 in
clockwise direction. (8 Marks)
Ans.: Interfacing of Stepper Motor with Microprocessor 8085 :
Now, suppose we want to rotate stqJper motor by 180° in clockwise
direction, then circular position of the rotor can be controlled by applying
appropriate numbers of steps.

In full stqJping, the angle of rotation is 1.8°for lOurstep sequence.

So, to rotate stepper motor by 180°, we need N number of steps which can
be calculated as given be1~.

NumberofSTEPSn = ReQuin::d~~~tionAnl!le = ll~~ = 100

The stqJ codes of the stepper motor are normally stored as an array in the
memory, so we can access these four step codes from the array in a turn. So, we
can find out how many turns are required to rota~e stepper motor by desired
angle, can be calculated as given below.

Numba-ofTurns = Number?fstepsN l~O =25

Fig. 2 : Interfacing of stepper motor with 8085 using 8255PPI .I

eaf>Y solution easy SOlution

 no Counter 8355 ~~ ".,,¥. ---- .-u
2-6 s' 2009
II Itroller
II,;'UvU"Can address
Not linesREADY
(MSBTE)
generate
generate no
8155
8755 Counter
8signal
II address
address
READY
Can
IOput
input
Programmable
Can or lines
lines READY
signal
or output.
generate 14-Bit
Microcontroller (MSBTE) 2-5 Summer 2009 M
No. Binary input or output.
Counter/Timer
Sr. signal
4.
6.
5.
Hence, the above program can be used to rotate stepper motor by 1800
with small additional changes.
I LXI
I
Sp, FFEO H ; Initialize stack pointer
MVI A, 80 H
OUT CWR ; Initialize 8255 PPI
MVI B,25H ; Initialize Turn counter to access array
UP: LXI H, C200 H ; Initialize memory pointer for look up table
MVI C. 04 H ; Initialize Byte counter
Q. 6(a) Draw and explain the interfacing of A 10 D Converter with 8085.
UPI: MOV A, M ; Read bits pattern i.e. step code (6 Marks)
OUT Port_A ; Write to Port A Ans. :
CALL delay ;adddelaybetweensteps Interfacing of ADC 0808/0809 with 8085 Microprocessor in I/O
INX H ; increment memory pointer for look up table Mapped 110
DCR C ; decrement byte counter by 1 The'. ADC0808/0809 can not be interfaced with microprocessor 8085
JNZ UPI ;:If byte counter 0 then go to UPl directly, hCJ;lce the 8255 PPI is required in betwcen 8085 and ADC 0808/0809 to
DCR B accommodate different control signals. Now, we can use any ports of tbc 8255
; Decrement Turn Counter by 1
PPI to interface ADC 0808/0809. The complete illwrfacing of ADC 0808/0809
JNZ UP ; If Turn Counter 0 then go to UP with microprocessor 8085 through 8255 PPI is shown in Fig.3.
HLT ; Stop
Hen; we will see the interfacing of diffen.'11t signals of ADC 080810809
After the executIon of the above program, the stepper motor rotates oy with 8255 PPI. Now, the Do-D7 i.e. 2-8 - 2"1 pins of ADC 0808 arc connected to
1800 in clockwise direction. pon A pins i.e. PAo-PA7. ThcALE and SOC are connected to PBo through which
we can issue Start of Conversion command and lv'llable internal address latch.
Q.5(c) Compare the features between 8755, 8155 and 8355. (6 Marks)
....
Ans - ..
.
The OE is connected. to PBI so that output from ADC 0808 after the
2KofROM
two
Each 8 port 8355
bit VOports
line is 8155
8755
2K
2KofEPROM
Each of
bit static
rolITammable
Each
two port
bit
individually VO
~ rollTammable
88port I/O as
is ports
line RAM
is an
ports ad
as an conversion can madc avail<lble on Port A lines by issuing Output Enable
Sr.
256X8
i. 6 bitorganized
memory
One I/O port as command. Theelld ofcOllVersion EOC signal can be read from Port C, hencctlle
Eoe pin is connected to PCo of the port C of8255 PPI. The input selection pin A,
B and C of ADC 0809 are grounded to select Oldy INo. All connections of the
ADC 0808 with 8255 PPI are shown in Fig. 3.

The control word to initialize 8255 is given where Port A is configured as

an input, Port B as an output, Port C lower as nn input ill mode O. Clock 10 the
ADC 0808 is connected to extemal clock gem.1·alor circuitry.

easy solution
",,'''''' ",,,Io,t;,,,,
 Microcontroller (MSBTE) 2-7 Summer 2009
~rocontroller (MSBTE) 2·8 Summer 2009

(i1) C.!§j:!,Complex Instruction Set Computer):

The term "clse" (complex instruction set computer or computing) refm
to computers designed with a full set of computer instructions that were intended
to provide needed capabilities in Ule most efficient way. Later, it was discovered
that, by reducing the filII set to only the most frequently used instructions; the
computer would get more work done in a shorter amount of time for most
applications.

(ill) Harvard Archilccture :

""
ADC
v.
The
inSlnlctions
~ architecture
and data, requiring
use)
dedicated
physically separate memories
buses for each of them as shown in t'1g.
for their

A. Instructions and op~ands can therefore be fetched simultaneously. Different

program and data btl6"\Vidths are possib)e, allowing program and data memory to
be 1x.1tcr optinhzcd to the 'architectural requircl;Iu ..>UIS. E.g.: If thc instruction
forlllat requires 14 bits thcn program bus 3l!d memory can be made 14·bit wide,
while the data bus and data memory r~l}.,ain' 8-bit ,\,ide.

Program 14-blls
Fig. 3 : Interfacing of ADC 0808/0809 with 8085 using 8255 PPI
Program
M~"",
Chapter 3: Introduction to Mlcrocontroller [Total Marks· 4]

Q.1(c) Give the meaning of following terms (4 Marks) The given blt8 widths al9 examplesontyl

(i) Rise (ii) else

(iii) Harward Architecture (iv) Von Neuman Arcitecture Fig. 4 : Hardware Architecture
Ans. :
(Iv) John Von Neumann's Architecture:
(I) RISC (Reduced In. ••trucdon Set Computer) :
, ---
The Yon Neumann Architecture is a computer design model that use) a
RISe (reduced instruction S<.1 computer) is a microprocessor that is processing unit and a single separate storage structure to hold both instructions
designed to perform a smaller number of types of computer instructions so that it and data. One shared memory for instructions (program) and data with one data
"all operate at a higher spero (perform more millions of instructions per second, bus and one address bus between processor and memory. Instructions and data
or MlPS). Since each instruction tJTle that a computer must perform requires have to be fetched in sequential order (known as the Yon Neumann BottImeck),
additional transistors and circuitry, a larger list or set of computer instructions limiting the opt:2'ation bandwidth. Its design is simpla than that of the Harvard
tends to make the microprocessor more complicated and slower in operation. architecture. It is mostly used to mterfhce to external memory as shown in Fig. 5.
easy solution 881)' solution
 Microcontroller (MSBTE) 2-9 Summer 2009
~rocontroller (MS8TE) 2-10 Summer 2009
Bit I : This bit is intcudaI tor the future versions of the microcontrollcrs, so it is
not supposed to be discussed ha-e.
Data 8-bits OV Overflow: Overnow occurs when the result of signed arithmctie operation is
to large, so that it emillot be stored in olle register. In that case, this flag bit will
cPt.! I Address 12..bi\s J Program be set (1). Ifthcrc is no overflow, this nag bit will be cleared (0).
'nO
Data RSO, RSl - Register bank selects bits: These two bils are usoo to select one of
Memory the four register banks in internal RAM as shoWll in Table A. By writing zeroes
and oncs to these bits, a group ofregistcrs ~-R, can be used out of four register
The given bits widths are examples. onlyl banks in intelllal RAM.
TabieA
Fig. 5 : John VOIl Neumann's Architecture
RSI 010RSO
1 Spaceln
BWlk3
Bankl
Bank2
BankO RAM
(08i~-OFH)
(I8H-! FH)
(IOH-17H)
(OOH-07H)
Chapter 4: 8051 Microcontroller llotal Marks ~54]
0 0!1
Q.1(d) Give PSW (Program Status Word) content of 8051 Microconlroller, Give
function of each flag. (4 Marks)
Ans. ;

rs\V Register (Pl""Ogram Status Word, Addresses DOH, Bit-Addressable) :

The Program Status Word is used to store 11 Ilumber of important bits that FO - Flag 0 : This is a general-purpose bit available to the user.

arc sel mid cleared by 805 I instructions. The PSW SFR contains ;he carry flag, AC - Auxiliary Carry Flag: It is llsed for BCD oper(ltjons only illld set when
the lluxiliary carry flag, the OVl..Tflow flag, and the parity flag, two register bank there is carry from Ol to D4 durillg ADD or SUB operation, otherwise it is
selcct bits, and user-definable Slatus flag. cleared.
Additionally, the PSW rcgistcr contains the register b,mk select flags
CY - Carry Flag: It is the ninth auxiliary bit used for all arithmetical operations
which arc llSCl:1to select which of tile "R" register banks arc currently selt:ctCl:1.
The Program Status Word (PSW) contains several status bits that reflect the and shift instnlCliolls. This flag is set whenever there is a CarryOllt lrom the D7 bit
currt1lt stllle of tile CPU. The ALU Ilutomatically changes sollie ofrcgistcr's bits, and alTcctoo by ADD and SUB operation. This flag can be set or IdiC! by using
which is uSlwlly IIsed in reguilltioll of the program performing. instructions like SETB C or CLR C.

(J 0 0 0 0 0 0 0 Value after Reset Q. 1{e) Describe two instructions each related with external data memory and
program memory of 8051 Microconlroller. (4 Marks)
PSW i Cy I AC I FO I RS I I RSO I OV I . I P IBU name Ans. :
bit? bit6 bit5 bit4 bit] bit2 bit! hi to 1. MOVX <destination-byte>,<aource-byte>
Fig. 6 Function : Move External

P - Pari!) bit: If a number of binary I's ii' ae<:umulator is even then thiS bit will
Description:
be UlllOJlllllically set (I), otherwise it will be cleared (0). It is Illninly used during The MOVX instructions transfer data bctwC61 the accumulator and a byte
data transmission and ru::civing via serial communicatioll. ofcxlemal data memory, which is why "X" is appendoo to MQV. Th~e are two
ea"y solution easy SOlution
Micfocontroller (MSBTE) 2-11 Summer 2009
Microcontroller (MSBTE) 2-12 Summer 2009
types of instructions, differing in whcther they provide an g-bit or 16-bit indirect --;- MOVe A, @A+ <base-register>
address to 1he extemal data RAM. In the firs1 type, the contents of RO or RI in
the current register bank provide an 8-bit address multiplexed with data on PO.
Function: Move Code byte
Eight bits nre sufficient for external lIO explU1Sioll decoding or for a Desenption :
relatively small RAM array. For somewhm larger arrays, lUly output pon pins can The MOve instnlctions load the uccumulator with a code byte or constant
be used to outl)Ut higher-order address bits. These pins are controlled by an from program memory. The address of the byte fetelled is the sum of the original
output instruction preceding the MOVX. In the second type of MOVX ulIsib>1l00 g-bit ~ccumlliator contents illHllhe contents of a l6-bit base registCl',
instntction, the Dnta Pointer generates a 16·bit address. which may be either the Data Pointt."l' or lhc PC.
P2 outputs the high-ordt:r eight address bits (the contents of OPH), while In the latla' case, lhe PC is incrementoo to the address of the following
PO multiplcxes the low-order eight bits (OPL) with data. The P2 Special FWlction instruction before being added with the Accumulator; otherwise the base register
Register retains its previous contents, while the P2 output buffers emit the is not altcred. Sixtccn·bit addition is performed so a carry-out from the low-order
CQIl1<'-'JltSof DPH. This fonn of MOVX is faster lUld more efficient when eight bits may propagate through higher-order bits. No nags are affected.
accessing very large data arrays (up to 64K bytes), since no lldditional
Example:
instructions are n<."C(ledto set up the output ports.
It is possible to use both MOVX types in some situmions. A large RAM Suppose a valuc bctwew 0 and 3 is in the accumulator. The following
arruy with its high-order address lines driven by P2 elUl be addressed via the Data instructions will trlUlslate the value ill the accumulator to one of four values
Pointer, or with code to output high-order address bits to P2, followed by a dcfinoo by the DB (defille bj1e) directive.
MOVX instruction using RO or RI. REL_PC, INC A
MOVC A,@A+PC
Example: RET
An cxternal 256 byte RAM using multiplexed address/data lines is DB 66H
connected to the 8051 Port O. Port 3 providcs controllincs for the external RAM. DB 77H
Ports I and 2 are usoo for norlllal I/O. Suppose. Registers 0 and I contain DB88H
12H lUld 34H. Location 34H of the cx!<'1Tlal RAM holds the value 56H. The DB 99H
instntetioll sequcnce, If the subroutine is calloo with the accumulator equal to OlH, it returns
MOVXA,@RI with 77H in the accumulator. The fNe A before the MOVe instruction is IlcOOed
MOVX@RO,A to "get aroWld" the RET instruction above the table. If s<.'Vcral b)1es of code

Copies the value 56H into both the Accumulator and external RAM separate the MOVC from the table, the corresponding number is addoo to the
location 12H. accumulator instead.

(I) MOVX A,@Ri (Where i may be 0 or 1) (I) MOVC A,@A+DPTR

Length in Bytes: I Lengtb in Bytes: 1
Operation, (A) ~ «Rill Operation, (A) ~ «A) + (DPTR))
(2) MOVX A,@DPTR (2) MOVC A,@A+PC
Length in Bytcs : I Length in Bytes: 1
Operation, (A) ~ «DPTR») Operation, (PC) ~ (PC) + I and (A) ~ «A) + (PC)

easy solution easy solutiOn

 Summar 2009
Microcontroller (MSBTE) 2-13 Summer 2009
~ocontroller (MSBTE) 2-14
Q.1(f) Explain Boolean Processor of 8051 microcontroller. (4 Marks) Mclllory 1118t use 16-bit address (MOVX @DPTR). III this applictllion It uses
Ans. : The 8051 instruction set is optimized for the one-bit operations so often strong internal pull ups when emitting Is.
desired in real-world, real-time control applications. The Boolean processor During accesses to external Data Memory Ihat use S-bit addresses (MOVX
provides direct support for bit manipulation. This leads to more efficient (gRi), Port 2 emits the contents of tile P~ Special FWlction Register. Port 2 also
programs that nccd to deal with binary input and output conditions inhtTCllt in receives some control signals and the lugh-ordcr address bits during EPROM
digital..wntrol problems. Bit addressing can be used for test pin monitoring or programming and program verification.
program control flags. For example, instructions for Boolean fWlCtion are as Port 3 (P3.0-P3.7):
given below.
Port 3 is an 8-bit bidircctionall/O port with intCTnal puH ups. Port 3 pins
(a) QRL PO, #1 Sc< PO.O
that have Is written 10 th(.'111arc pulled high by the internal pull ups, and in that
(b) XRL PO, #1 Togg]e PO.O state can be used as inputs.
(c) ANL C, P1.4 AND the bit on PI.4 with carry. Port 3 also serves Ihe functions of various special features "rlhe MCS 51
(d) ANL C, !(P1.4) AND inverted bit on P 1.4 with carry Illicrocontrollcr family, us listed Table A. Port 3 also receives some control

Q. 2(a) List the 110 ports of 8051 Microcontroller. Explain their alternative signals for EPROM programming ilnd prognml verificutioll.
Table A
functions. (4 Marks) External
Extcmal data
data memory
memoryI read write strobe
strobe
Pin Extcmal
Name
TXD
RXD
Alternate
Timer
Time,.
TO
TJ
Serial internl!'t
EXlemal
0Ioutput Function
cxtcmal
extemal interrupt 0
lineinput
Ans. : The microcontroller hus four VO ports as listed below. SL-,.ial input line
INTO iNTI
WR
RD
I. Port 0 2. Port 1 3. Pan 2 4. Port 3 P3.0
P3.1
P3.2
P3.6
P3.5 P3.3
P3.4
P3.7
The FtL'lction of I/O ports arc describe below:
Port 0 (PO.I/ADu-PO.7/AD,):
Port 0 is an 8-bit open dmin bidirectional I/O port. Altemative]y, Port 0 is
also the multiplexed with low-order address/data bus during accesses to cxtelllal
memory. Port 0 also receives the code bytes during EPROM programming, (Uld
outputs the code bytes during program verification.
Port 1 (PI.O - P1.7) :
Port I is an 8-bit bidirectional I/O l}Ort with inl(.Tnal pull ups. Port I pins
that have Is wrillen to them are pulled high by the intemal pull ups, and in that
state can be used as inputs. As inputs, Port I pins that are cxtt71lally being pulled
low will source current because of the internal pull ups. Port I also receives the
0.2(c) Interface external program memory with 8051 microcontrol1er explain
low-ordcr address bytes during EPROM programming and program verification.
how the data is transferred? (4 MarkS)
Port 2 (P2.0/ArP2.7/A1s): Ans. :
Port 2 is an 8-bit bidirectional I/O port with internal pull ups. Port 2 pins
that have Is written to them are pulled high by the internal pull ups, and in that Interlacing of external memory :
state can be used as inputs. Port 2 emits the high-ord(2" address byte during In case on-chip memory is 1101Cllough. it is possible to add two extcmal
fetches from external Program memory and during accesses to external Data memory ('11 ips with capacityof64Kh each. 110 ports P2 unci P3 (Ire used for their
addressing and data transmission (1'__sh_own_i_n_F_ig_.
7_. _

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 2-16 SlImmer 2009
Microcontroller (MSBTE) 2-15
Summer 2009 ~t;)ntroller (MSBTE)
Even though the additional memory is rarely used with the latest versions

of the microcontrollers, it will be described here in short what happens wLen

memory chips are C()nnocted according 10 the previous schematic.;..
When the program during execution enC()lInters the instruction which

resides in external memory (ROM), the microcontroller will activate its C()ntrol

output ALE and set the first 8 bits of address (, O-A7) on PO. In this way, Ie
circuit 74HCT573 which "lets in" tlle first 8 bit Iv memory address pins is
activated. A signal on tlle pin ALE closes the Ie circuit 74HCT573 immediately
afla' 8 higher bits ofaddrcss (A8-A 15) appear on the port. In this way. a desiral
location ill additional program memory is C()mpletely addressoo. The ollly thing
left over is to read its content.

Pins on PO are C()nfigured as inputs, the pin PSEN is activated and the

microcontrolk,.. reads C()ntent from memory chip. The same connections are used
both for data and lower address byte. Similar occurs when it is a needed to read
some location from extcmlll Data Memory. Now, addressing is perfonncd in the
same way, while reading or writing is performed via signals which appear on the

control outputs RD or WR.

Q.3(b) Explain the power saving operations of 8051 Mlcrocontroller. (4 Marks)

Ana. :
Fig. 7 : Additional external memories
Actunlly, there are two power~saving modes ofoper-alion : Idle and Po;wr
From the users' perspoctive, <.."Vcrything fWlctions quite simple ifproperly Doom as shown in Fig. 8.
connected because the most operations are performed by the microcolltrollcr

itself. The 8051 microcontroller has two separate rc.1ding signals RD (P3.7) and

PSEN. The first one is activated byte from external data memory (RAM) should
be read, while another olle is activaloo to read byte from external program
memory (ROM). These both signals are active at logical zero (0) level.
 Microcontroller (MSBTE) 2-17 Summer 20U9

~rocontroller (MSBTE) 2-18 Summer 2009

The controt of the on-chip RAM and all the Special Functions Registers
remain wlchanged during lhis mode. The Idle Mode call be terminated by any
atabled interrupt or by a hardware rc<let.
power Down Mode:
Wlll ..'Il the bit PO ill the register PCON is set frOIll within the program, the
microcontroller is set to Power down mode. It a d tums off its intemal oscillator
reducing drastically consumption in that wa) III power- down mode the
microcolltroller can operate using only 2V power supply while the 10tal power
consumption is less than 40uA.
The only way to get the microcontrolJer back to normal mode is reset.
During Power Down mode, the stale of all SFR registers and I/O pons remains
unchanged, and after Ihe microcontroller is put get into the normal mode, the
con1(.lIt of the SFR register is lost, but the conlent of intemal RAM is saved.
Reset signal must be long enough approximately 10mS in order 10 stabilize quartz
oscillator opG'l"ating.
In the Power Down mode the oscillator is stopped, and the instruction that
invokes Power Down is the last instmction executed. The on-chip RAM and
Special Function Registers retain their values wltil the Power Down mode is
terminated. The only exit from Power Down is a hardware rc<lct. Reset redefines
the SFRs but does not change the on-chip RAM.
The rcset should nOl be activated before vec is restored to ils normal
Fig.8: Power saving mode of 8051 operating level and must be held active long enough to allow the oscillator to
Idle Mode: restan and stabilize. The statuses of the exlernal pins during idle and power down
mode arc givro in Table A.
Immediately Ullon instmction which sets the bitlDL in the peON register,
the mi<.:rocontroll<.'f IU01S off the greatest power cOllsumer- epu IUlit while Table A : Status of the external pillS during Idle and Power down
Mode -- - PSEN --
p<'Tiphcral lUlit's such as serial port, timers and interrupt system conlinue 0Address
Float
Data
Float
1D Data
D
Dala
D
Data011 PORTO
ALE
PORTI
Data
PORT3
ata
ata
Internal
--ata
PORT2
Data
External
Program
Internal
External
Down
opcrating normally ~
Idle consuming
Power Memory6.5mA. In Idle mode,
I/O ports is remains unchanged. In ordcr to terminate
the state of nil registers and
Idle
the idle mode and make the
Power

rnicrocontrollcr opcrate normally, it is necessary to enable and execute any

illlGmlptorrese1.

Thro the IDL bit is autolllatically cleared and the program continues
exccuting from instmctioll following that instmction which has set the IDL bil.
They do llot perform any operation but ke<.1J the microcontroller from
undesired changes on the I/O ports. In Idle Mode, the CPU puts itself to sleep
while all the on-chip pcripherals remain active. The mode is invoked by software.
AA~V I'<nllllinn
 ~ler(MSBTE) 2-19 Summer 2009 Microcontroller (MSBTE) 2-20 Summer 2009

Q.3(d) Give the specifications of any two microcontrollers used for commercial
Q.3(c) Explain internal and external interrupt of 8051 Microcontrol!er. Explain applications. (4 Marks)
the function IP register. (4 Marks) Ans. :
Ans. :

Intel 1\1C8·51 • Introduced 1980 :

IP Register (Interrupt Priority) :
The MCS-5l Family includes 2 timers and 4 ports as well as 128bytes or
The IP register bits shown in Fig. 9 specifY the priority level of each
interrupt (high or low priority). more of on board RAM. The 51 is one of the most popular MCUs on the market.
II is now being made in speeds of up to 100MHz by SiLabs, while Intel continues

IP I x

bit7
I
X

hit6
0

I PT21
bitS
0

PS
bit4
0

bit3
0

I ITI I PXl I PTO I P~

bil2
0

bitl
0

hilO
Value after reset

Bit name
to make them up to 33MHz.

executing
The standard

54k of external
MCS-51 instruction

in a single cycle. They can support

memory space.
set has 111 instructions

up to 64k of external
with 64 of them

program, and

Fig. 9 : Interrupt priority register Intel MCS-48 - Introduced 1976 L :

PS - Serial Port Interrupt priority bit The Intel 8048 microcontroller, Intel's first I1C, was used in the.Magnavox
Priority 0
OdysseY video game console (as a 100 KHz 8021) and (in its 8042 variant) in
Priority 1 the original IBM PC keyboard. The 8048 is probably the most prominent memoo-

PTl - Timer I interrupt priority of Intel's MCS-48 family of microcontrollers. It was inspired by, and is

Priority 0 somewhat similar to, the Fairchild F8 microprocessor.

Priority 1 The MCS-48 has over 90 instructions with 90% of them being single byte.
The 8048 has a modified Harvard architecture, with internal or extemal program
PXl - External Interrupt INTI priority
ROM and 64---256 bytes of intemal (on-chip) RAM. The I/O is mapped into its
Priority 0
own address space, separate from programs and data.
Priority 1

PrO - Timer 0 Interrupt Priority

Priority 0

Priority I

PXO - External Interrupt INTO Priority

Priority 0

Priority 1

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Microcontroller (MSBTE) 2-21 Summer 2009 2·22 Summer 2009
~~nlroner (MSBTE)
Q. 4(b){l) Draw the architecture of 8051 microcontroller. (4 Marks)
Ans. :
An~. : Reset occurs when the RST pin is supplied with l\ positive pulse in
duration of at Ie-1St 2 machine cycles (24 clock cycles of crystal oscillator). After
that, the microcontr~lIer generates ~nterna1 rcset signal during which all SFRs,
excluding SBUF registers, Stack POllltcr and ports are rcsct (the state orthe first
tWO ports is indefinite while FF value is being wrillen to the ports cnnfib'Uring all
pins as inputs).
Dependillg on device purpose iUld environment it is in, on pOWcr~OIl reset
it is usually push button or circuit or both connocted to the RST pin. One of the
simplest circuits providing secure reset at the moment of turning powcr on is
shown in Fig. II.

8051

RST

aND

aND

Fig. II: Resetclrcuit

Upon the power is on, electrical cond1.11St'1"is being chargo:l lor several
Fig. 10
milliseconds through resistor connocted to the ground and during this proccss the
pm voltage sup?Iy is on. When the condenser is chargo:l, power supply voltage is
Q. 4(b)(ii) Draw and explain Power ON reset circuit of microcontroller 8051. Give
stable. and the pin keeps being connected to the ground providing normal
the content of PO·P3and SP register on reset. (4 Marks)
operatmg in that way. If later on, during the operation, nl<illual reset button is
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 2-24 Summer 2009
2-23 Summer 2009 Microcontroller (MSBTE)
Microcontroller (MSBTE)

pu: hcd, the condenser is being temporarily discharged and the microcontrolla is (III) DJNZ Rn, rndd :
bei 19 reset. Upon the button release, the whole process is repeated ... through the
Function: Decrcml.-'llt and Jump if Not Zero
pre ~ram- step by step.
Description: DJNZ decrl.-'111ents the location indicated by I, and branches to the
Q.• (c) Explain the following instruction of 8051 microcontroller. (8 Marks)
address indicated by the second operand if the resulting value is ~ zero. An
(i) ANl C,Io (ii) SWAPA
original value of OOH undcrflows to OFFH. No flags are affected. The branch
(iii) DJNZ Rn. radd (iv) RETI dtslination is computed by adding the signed relativo-displacement value in the
Ans. : last instruction byte to the PC, afttT incrcmentillg the PC to the first byte of the
following instmctioll. The location decremented may be a register or directly
(i) ,ANL C,/b :
addressed byte.
Function: Logical-AND for bit variables
Example:
Description: If the Boolean vlllue of the source bit is a logical 0, lh(.11 ANL C Internal RAM locations 40H, 50H, .md 60H contain the values OIH, 70H,
clears the carry flag; otherwise, this instruction leaves lhecarry flag in its current and 15H, respectively. The following instruction sequence,
state. A slash (/) preceding the operand in the assembly language indicates that DJNZ 40H,LABEL_1
the logical complement of the addressed bit is used as lhe source value, but the
DINZ 50H,LABEL_2
source hit itselfis not affected. No other flags are affected. Ouly din,;;t addressing
DJNZ 6OH,LABEL_3
is allowed for the source operand.
causes ajuOlp to the instnlction at label LABEL_2 with the values OOH, 6FH, and
Example: SClthecarry (Jag if, and only if, PI.O =: 1, ACC.7 z: I, and OV =: 0: 15H in the three RAM locations. The first jump was not taken because the result
was zero. This instruction provides a simple way to exocute a prot,'Tam loop a
MOVC,no ; LOAD CARRY WITH INPlIT pfN STATE
given number of times or for adding a moderate time delay (from 2' to 512
ANLC,ACC.? ;AND CARRY WITH ACCUM. BIT 7 machine cycles) with a single instmction. The following instruction sequence,
ANLC,IOV ;AND WITH INVERSE OF OVERFLOW FLAG MOV R2,# 8
(ii) SWAP A: TOGGLE: CPL Pl.?

DJNZ R2,TOGGLE
Function: Swap nibbles within the Accumulator
togglQl PI.7 cighttimes, causing four output pulses to appear at bit 7 of output
Description: SWAP A interchanges the low· and high-order nibbles (four-bit Pon I. Each pulse lasts three machine cycles; twO for DJNZ and one to alter the
fields) of the Accumui<:tor (bits 3 through 0 and bits 7 through 4). The operation pin.
can also be thought of as a 4~bil rolate instruction. No flags are affected.
(Iv) RETI:
Example:
Function: Return from interrupt
The Accumulator holds the value OC5H (I 1000101 B). The instruction,
Description: RETI pops the high- and low-order bytes of the PC successively
SWAP A leavc<; the Accumulator holding the value5CH (0101 IIOOB).
from the stack and restores the interrupt logic to accept additional interrupts ai the

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 2-26 Summer 2009
Microcontroller (MSBTE) 2-25 Summer 2009 Microcontroller (MSBTE)

same priority level as the one just processed. The Stack Pointer is left -;:;;: Compare two numbers

docreme:nto:! by two. ~o oth.cr rcgistcrs arc affected; th~ PS\\'. is not Step 6: rflllllllbcr > ncxtllumbet', then go to Sll>p 8
automatically restored to Its pre-mt('Tn1pt status. Program executlon contmucs at 7' Replace number with next number which is largest
'.he rcsulting address, which is gcncra!ly thc inSlruction immediately after the Step : Increment memory pointcr to reml next number in the array
point at which the int(.'1T\lpt request was detected. If a lower- or same-Icvel Step 8 .
intClTUpt was pending whCII the RETI instruction is exccuto:l, that onc instruction Step 9: Dccrcl11C11t byte counter by I
is exC(uted before the p<'llding interrupt is processed. Step 10: Ifbyte coWlter 1: 0 then go to step 5

Example: The Stack Pointcr originally contains the value OSH. An intCfnlpt was Step II: Store result
dt.1octoo during the instruction ending at location 0122H. Internal RAM locations Step 12: Stop
OAH and OSH contain the values 2JH and 01 H, respectively. The following .
instruction Program.

RETI > -~-C-lR--PS-W-.3----;-S'-I.-ct-:B-an-:k-:O--------'

ClR PSW.4
leaves the Stack Pointer cqullito 09H and retums program execution to location
0123H. MOV RI,OAH ; Initialize byte counter
MOV DPTR, #3000H ; Initialize memory pointer
Q. 61b) Write a program in 8051 microconlroller to find largest number from the DEC Rl ; Decrement byte counter by 1
array of ten numbers stored in external RAM memory. (6 Marks)
MOVX A, @DPTR ; Load number in Accumulator
Ans. :
MOV 40H, A ; Store number in memory location 60H
INCDPTR ; Increment memory pointer by 1
and l1lC~~;~~7~1~~~elaICd array always requires initialization Df byte counter lup:
MOVX A, @DPTR ; Read Next number
Now, we will see, how to write program to find largcst number from the
CJNE A, 40H, DN ; if number ~ next number. then go to ON
array often bytcs stor(X1 ill ~xtemaf memorv.
AJMP NEXT ; else go to NEXT
Program: ; If next number;> number then go to NEXT
ON: JC NEXT
Assume lIrray of the len bytes is stored in internal melliory of 8051 from MOV 40H, A ; Else replace next number with number
memory location JOOOH and Store largcstllumlx.-T in memory location JOOAH NEXT: DJNZ RI, UP ; Decrement byte counter by 1, if byte

Algorithm: counter ~ 0 then g~ to UP

INCDPTR ; Increment memory pointer by 1
Stell I : Initialize byte counter and memory pointl,. to read numbers from
MOV A,40H
array ; Store result to external memory location
MOVX @DPTR, A
StCJl2 : Read number frolllille array lOOP: AJMP lOOP ; Stop
Step 3: 111l.;rClilcnt memory pointer to read next number
Step 4: Decrement byte counter

e&5v.§Q!utLoo
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 2-28 Summer 2009

Microcontroller (MSBTE) 2-27 Summer 2009 ~troller (MSBTE)

For example:

Chapter 5 : MCS-S1 Addressing Modes CSEG

and Instructions [Total Marks· 4] DB 22~33, 'Alarm',44

When writtt11 before this directive, the label will point to the first value in

Q. 3(8) Explai'1 the function PSEN and ALE pins of microcontro!ler 8051 the array ( in this example number 22).
(4 Marks)
Ans. :
(i1) EQU,
By means of this directive, a numeric value is rcplac<x1 by a symbol.
For example:
PSEN (Program Store Ellable) :
MAXIMUM EQU 99
Program Store Enahle is the Read strobe to External Program Memory.
After this directive, every appearance of the label "MAXIMUM" in the

W11CTI the 8051 is executing C()de from Internal Program Memor)', ~ program, the asscmbler will interprctt: US number 99 (MAXIMUM = 99). It is
is inactive (high). When the device is executing code from Ext<.Tllal Program only once possible to define symbols ill this way so the EQU directive is mostly
used at the beginning of tile program.
Memory, PSEN is activated twice each machine cycle, except that two PSEN
activations are skipped during each access to Extemal Data Memory. (iii) ORG,
This directive is used to define location in program memory wherc the
ALE,
program following directivc is to be placed.
Address Latch Enable output signal for latching the low byte of the For example:
address during accesses 10 cxtt:mal memory. III normal opa-ation ALE is emitted BEGINNING ORG 100
at a C()IlS1anl rate of 1/6 the oscillator frequency, and may be llsed for external
liming or clocking purposes.
ORG lO00h
Chapter 6 : Assembly Language Programming
TABLE ...
[Total Marks ~6]

Q.5(b) Explain the function of following directives. (6 Marks) Program begins at iqcation 100. The table with data win start atlocatiol\
1024 (IOOOh).
(i) DB (ii) EQU (iii) ORG
(Iv) DATA'
(iv) DATA (v) END (vi) CODE By means of this dirt'ctive, an address within internlll RAM is designated
Ans. : as a symbol (address must be inlhe range of 0-255). In oth ••.
,. words, any selected
register may change its name or be assigned a new one.
(I) DB, For example:
This directive is used for writing indicated value to program mcmory. If TEMPI2 DATA 32 : Register at address 32 is named;as "TEMPI2"
scv(:ral values arc indicatcd one after another thcn they are separated byC()nunas. STATUS _R DATA DOb PSW register is assigned the name
If ASCI[ llrray should be indicated it is t11closed with single quotation marks.
;"STATUS_R"
This directive can be uso:l only if the segment CSEG is active.
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 MicrocoritroUer (MSBTE) 2-29 Summer 2009

(v) END,
Microcontroller (MSBTE) 2-30 Summer 2009

This directive must be at :.he end of every program. Once it encounters this
directive, the assembler will stop interpreting program into machine code.
Value after
For example: , Reset

TCON I TFI I TRI I TFO I TRO I lEI I IT! I IEO lITO I Bh ""me
END ; End of program bit? bit6 bit5 bit4 bit3 bit2 bit! bitO
(v;) CODE,
TFI (Timer 1 Overflow Flag) : This bit is automatically set with the
By means of this directive, an address in program memory is designated as Timer 1 overflow means when the timer changes from FFFF to 0000. It is cleared

a symbol. Since the maximal capacity of program memory is 64K, the address automatically when interrupt is vectored to location OOIBH. When this bit set, the
must be in the range of 0-65535. 8051 activates timer interrupt. This bit can be set through software.

For example; TRI (Timer Run Bit 1) : This bit turns the Timer 1 on

RESET CODE 0 : Memory location OOh called "RESET" 1 - Timer I is turnC\i on

TABLE CODE 1024: Memory location 1024h called ''TABLE'' 0- Timcr I is turned off

TFO (Timer 0 Overflow Flag) : This bit is automatically set with the
Chapter 7 : MCS-51 Timers/Counters, Interrupts
and Serial Communication [Total Marks -16] Timer 0 overflow means when the timer changes from FFFF to 0000. It is cleared
automatically when interrupt is vectored to location OOOBH. When this bit set, the
Q. 2(b) Draw the format of Timer Control (TCON) register and describe it.
8051 activates timer interrupt. This bit can be set through software.
(4 Marks)
Ans. : TRO (Timer Run Bit 0) : This bit turns tho timcr 0 on

Format of TCON Register (Timer Control, Addresses 88h, Bit- 1 - Timer 0 is turned on

Addressable) 0- Timer 0 is turned off

The Timer Control SFR is used to I configure and modify the way in IEO and lEI (External Interrupt Flag) : This bit indicates whether
which the 8051's two timers operate. This SFR controls whether each of the two external interrupt is activated or not. In edge triggered mode, it is set at the falling
timers is running or stopped and contains a flag to indicate that each timer has mode of the external interrupt signal. In level triggered mode, this bit set at the
overflowed. This is also one of the registers whose bits directly control timer low level of the external interrupt signal. Whro. this bit is set, it activate external
operating. Only 4 of all 8 bits this register has are used for timer control, while signal and cleared automatically when vectored to location 0013(IE1) and
remaining four are used for interrupt control. 0003(1£0). It can be set through software.

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