Application Report

SNVA866 – June 2019

How to design an Isolated Flyback using LM5155

Garrett Roecker

ABSTRACT
The LM5155 is a versatile non-synchronous low-side, N-FET controller for switching regulators. the
common configurations for the LM5155 include boost regulators, flyback regulators and SEPIC regulators.
This design guide focuses on how to configure and design the LM5155 as an isolated flyback regulator.
The procedure is generic and focuses on selecting the correct components for stable flyback operation.
The design example follows the application specifications of the LM5155EVM-FLY evaluation module, the
results are presented in the LM5155EVM-FLY User's Guide. For typical applications the LM5155 Flyback
Controller Quick Start Calculator can be used to efficiently complete the calculations described in this
report.

Contents
1 Introduction ................................................................................................................... 2
2 Example Application ......................................................................................................... 2
3 Calculations and Component Selection ................................................................................... 2
4 Component Selection Summary.......................................................................................... 12
5 Small Signal Frequency Analysis ........................................................................................ 17

List of Figures
1 LM5155 Current Sense Network .......................................................................................... 5
2 Isolated Feedback ........................................................................................................... 9
3 Application Circuit .......................................................................................................... 12
4 Efficiency vs ILOAD ........................................................................................................... 12
5 Control Loop Response VSUPPLY = 18V, ILOAD = 4A ...................................................................... 12
6 ................................................................................
Load Step: ILOAD 2A to 4A, VSUPPLY = 18V 13
7 ...............................................................................
Thermal Image: VSUPPLY = 18V, ILOAD = 4A 13
8 LM5155EVM-FLY Schematic ............................................................................................. 14

List of Tables
1 Design Parameters .......................................................................................................... 2
2 Selected Transformer Parameters ........................................................................................ 4
3 Selected Optocoupler parameters ....................................................................................... 10
4 List of Components ........................................................................................................ 15
5 Control Loop Equations ................................................................................................... 17
6 Compensation Modeling Equations ...................................................................................... 18

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1 Introduction
This design guide follows typical design procedures and calculations to implement an isolated
nonsynchronous flyback controller operating in continous conduction mode. The design example uses an
unregulated 24V rail (18V-36V) to produce a regulated 5V of up to 4A load current. A non-isolated
auxiliary winding of 10V is selected to power the LM5155, lowering power dissipation in the LM5155. The
switching frequency of 250kHz is selected to help minimize switching losses and conduction losses of the
switching MOSFET. Section 3 details the component selection based on the general design parameters
shown in Table 1.

2 Example Application
Table 1 indicates the design parameters for the example application.

Table 1. Design Parameters

Parameter
VSUPPLY 18V to 36V
VLOAD 5V
ILOAD 4A
VAUX 10V
IAUX 20mA
POUT_total 20.2W
fSW 250kHz

3 Calculations and Component Selection

This section covers the equations specific to the LM5155 to implement an isolated flyback controller that
operates in continuous conduction mode. Component selection is based on the example application
described in Table 1.

3.1 Switching Frequency

Selecting the switching frequency is the first step in the design process. Higher switching frequencies yield
a smaller total solution size. However, the small size comes at the cost of increased switching losses,
decreasing the efficiency of the regulator. Higher efficiency is achieved by selecting a relatively lower
switching frequency but requires physically larger components. Harmonics of the switching frequency
should be considered in designs that have strict EMC requirements. Equation 1 is used to set the
frequency of the internal oscillator of the LM5155. The example application is selected to have a switching
frequency of 250kHz.
2.21u 1010 2.21 u 1010
RT 955 955 87.44k:
fSW 250kHz (1)
A standard value of 86.6kΩ is chosen for RT.
Note that the internal oscillator of the LM5155 can be synchronized to an external clock as described in
the datasheet. The LM5155 has a maximum duty cycle limit that is frequency dependent. See the LM5155
datasheet for details on the maximum duty cycle limit.

3.2 Transformer Selection

In a flyback regulator, selecting the proper transformer for any application is a critical step. The first
decision is to select the correct switching type of operation for the application, discontinuous conduction
mode (DCM) or continuous conduction mode (CCM). CCM is selected for this design in order to minimize
the primary side RMS currents, maximize full load efficiency while minimizing load voltage ripple.

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3.2.1 Maximum Duty Cycle and Turns Ratio Selection

In CCM operation the duty cycle of the low side switch is calculated using Equation 2.
NP
˜ VLOAD
NS
D
NP
VSUPPLY ˜ VLOAD
NS

where
• NP is the number of turns on the primary side winding and assumed to be 1
• NS is the number of turns on the secondary side winding. (2)
The maximum duty cycle occurs when the supply voltage is at the minimum value. By selecting the
maximum duty cycle, the number of turns on the secondary winding is calculated. Selecting the duty cycle
to be less than 50% brings two main benefits. First, it reduces the need for slope compensation which is
required for stable operation when the duty cycle is greater than 50% in CCM operation. For some wide
input voltage designs limiting the duty cycle below 50% might not be possible. The LM5155 provides
programable slope compensation for such designs. Second, the right-half plane zero of the modulator is
pushed to high frequencies, helping to improve the load transient response and simplifying the control
loop compensation calculations. For this design the maximum duty cycle (DMAX) is selected to be 40%. The
number of turns on the secondary winding is calculated using Equation 3
VLOAD ˜ 1 DMAX ˜ NP 5V ˜ 1 0.4 ˜ 1
NS _ calc 0.417
VSUPPLY _ min ˜ DMAX 18V ˜ 0.4 (3)
NS is selected to be 0.5 turns. Selecting NS to be 0.5 turns the turns ratio to achieved in the fewest number
of full turns. In this example the minimum number of turns is 2 on the primary winding and 1 turn on the
secondary winding. With NS selected, Equation 4 is used to calculate the maximum duty cycle.
NP 1
˜ VLOAD ˜ 5V
NS 0.5
DMAX 0.357
NP 1
VSUPPLY _ min ˜ VLOAD 18V ˜ 5V
NS 0.5 (4)
DMAX is calculated to be approximately 35.7%, below the target maximum duty cycle of 40%. The number
of turns on the auxiliary winding is calculated using Equation 5
V 10V
NAUX _ calc NS ˜ AUX 0.5 ˜ 1
VLOAD 5V

where
• VAUX is the auxiliary winding voltage (5)

3.2.2 Primary Winding Inductance Selection

Three main parameters are considered when selecting the inductance value of primary winding: primary
winding current ripple ratio (ILRR), falling slope of the transformer current and the right half plane zero
frequency (ωZ_RHP) of the control loop. Finding a balance between these three parameters helps to simplify
the rest of the design process.
• The primary winding ripple current ripple ratio is selected to balance the copper loss and core loss of
the transformer. As the relative ripple current increases; the core losses increase and the copper
losses decrease.
• The falling slope of the transformer current should be small enough to prevent sub-harmonic oscillation
in applications with a duty cycle greater than 50%. A relatively larger inductance value of the primary
winding results in a smaller falling slope. The LM5155 provides fixed internal slope compensation as
well as programable slope compensation for these applications.
• The right half plane zero should be placed at high frequency, allowing for a higher crossover frequency
of the control loop. As the relative inductance value of the primary winding decreases the right half
plane zero frequency increases.

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A maximum ripple ratio between 30% and 70% results in a good balance of the total power loss of the
transformer, matching the down slope of the transformer current to the internal slope compensation and
the increasing the right half plane zero frequency. The maximum ripple ratio of the inductor current is set
to 60%. In CCM operation, the maximum primary winding ripple current occurs when the supply voltage is
at the maximum value. The primary winding inductance value for CCM operation is calculated using
Equation 6.
NP2 ˜ VSUPPLY _ max 2 ˜ VLOAD 2
LM _ calc 2
ILRR ˜ fSW ˜ POUT _ total ˜ NS ˜ VSUPPLY _ max NP ˜ VLOAD
12 ˜ 36V 2 ˜ 5V 2
LM_ calc 2
20.6PH
0.6 ˜ 250kHz ˜ 20.2W ˜ 0.5 ˜ 36V 1˜ 5V

where
• ILRR is the ripple ratio
• VSUPPLY_max is the maximum supply current
• POUT_total is the maximum power delivered by the flyback regulator (6)
The primary winding inductance is selected to be 21µH. The primary winding ripple current and primary
winding peak current are calculated using Equation 7 and Equation 8, respectively. The peak primary
winding current occurs at the minimum supply voltage.
VSUPPLY ˜ D 18V ˜ 0.357
'ILM 1.224A
LM ˜ fSW 21PH ˜ 250kHz (7)
POUT _ total 'ILM 20.2W 1.224A
ILPEAK 3.75A
VSUPPLY _ min ˜ D 2 18V ˜ 0.357 2 (8)
ILPEAK is used to properly size the current sense resistor. Table 2 summarizes the key parameters of
selected transformer.

Table 2. Selected Transformer Parameters

Parameter Value
Turns Ratio (NP:NS:NAUX) 1:0.5:1 (2:1:2)
Primary winding inductance (LM) 21µH
Primary winding saturation current (ISAT) 6A

3.3 Current Sense Resistor Calculations

Selection of the current sense network components is described in this section. Figure 1 shows the four
components that make up the current sense network of the LM5155. RS is the current sense resistor. This
resistor senses the switch current for the control loop, and sets the peak current limit value. RF and CF
form a low pass filter. This filter helps reduce the impact of any high frequency noise on the current sense
signal. RSL sets the external slope compensation and is optional. In some applications the internal slope
compensation of the LM5155 will not be sufficient and RSL will be required.

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ISWITCH

RF RSL
CS

CF

RS

Figure 1. LM5155 Current Sense Network

3.3.1 Current Sense Resistor and Slope Compensation Resistor Selection

The current sense resistor is selected to avoid triggering peak current limit protection when the minimum
supply voltage is present, VSUPPLY_min, and supplying the maximum output power, POUT_total. Due to
component tolerances and inefficiencies of the regulator, the peak current limit is set some margin above
the calculated peak current of the transformer primary winding. A margin of 20% to 30% (MI_LIMIT=0.2-0.3)
is a good starting point. Equation 9 is used to calculate the desired peak switch current limit value. In this
design example, MI_LIMIT is selected to be 30%.
ILPEAK _LIMIT _ SET 1 MI_LIMIT ˜ ILPEAK _MAX 1 0.3 ˜ 3.75A 4.88A (9)
Selecting the correct current sense resistor is an iterative process. The first step is calculating the
maximum current sense resistor value, assuming that no external slope compensation is required (RSL =
0Ω). The maximum current sense resistor value is selected using Equation 10.
V ˜L ˜ f 40mV ˜ 21PH ˜ 250kHz
RS _ MAX 1.66 SL M SW 1.66 34.9m:
NP 1
˜ VLOAD ˜ 5V
NS 0.5

where
• VSL is the internal fixed internal slope compensation of the LM5155 (10)
Assuming that no external slope compensation is required, the current sense resistor value is calculated
using Equation 11.
VCLTH 100mV
RS _ wo _ sl 20.48m:
ILPEAK _ LIMIT _ SET 4.88A

where
• VCLTH is the current limit threshold of the LM5155 (11)
If the calculated RS_wo_sl resistance value is less than the RS_MAX resistance value, then RS_wo_sl is selected
for the current sense resistor value (RS). If the calculated RS_wo_sl resistance value is greater than the
calculated RS_MAX resistance value, there are two approaches to take; decrease the current sense resistor
value or add external slope compensation.
• Decreasing the current sense resistor value increases the effectiveness of the internal slope
compensation. With no external slope compensation the peak inductor current limit will be constant
regardless of the duty cycle when using the LM5155. A lower current sense resistor value results in a
larger switch peak current limit value, which increases the required saturation current rating of the
primary winding.
• Adding external slope compensation. The peak inductor current limit varies with supply voltage when
external slope compensation is added to the current sense network.

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External slope compensation is added by setting RSL to a non-zero value, but less than 1kΩ. In
applications where external slope compensation is required, RS is calculated using Equation 12.
LM ˜ NS ˜ fsw ˜ VCLTH D ˜ VSLOPE
RS _ w _ sl
D ˜ 0.833 ˜ NP ˜ VLOAD ILPEAK _ LIMIT _ SET ˜ LM ˜ NS ˜ fSW
21PH ˜ 0.5 ˜ 250kHz ˜ 100mV 0.357 ˜ 40mV
RS _ w _ sl 20.97m:
0.357 ˜ 0.833 ˜ 1˜ 5V 4.88A ˜ 21PH ˜ 0.5 ˜ 250kHz (12)
RSL is calculated using Equation 13.
VCLTH ILPEAK _ LIMIT _ SET ˜ RS _ w _ sl 100mV 4.88A ˜ 20.06m:
RSL 223.4:
ISLOPE ˜ D 30PA ˜ 0.357

where
• ISLOPE is the slope compensation current source of the LM5155
• D is the duty cycle at the minimum supply voltage (13)
If the calculated RSL value is negative, the internal slope compensation is adequate and the additional
slope compensation is not required. If the calculated RSL value exceeds the maximum value of the 1kΩ,
the down slope of the sensed current needs to be reduce. To reduce the down slope of the primary
winding current, the primary winding inductance value of LM must be increased. If the primary winding
inductance value is changed the current sense resistor calculations must be redone.
Following the design procedure, a current sense resistor value is selected to be 20mΩ (RS), which is the
nearest standard resistor value to the calculated value in Equation 11. No external slope compensation is
required and RSL is selected to be 0Ω. The peak current limit of the transformer primary winding is
calculated using Equation 14.
VCLTH ISLOPE ˜ RSL ˜ D 100mV 30PA ˜ 0: ˜ 0.375
ILPEAK _LIMIT ILPEAK _LIMIT 5A
RS 20m:

where
• D is they duty cycle at the minimum supply voltage (14)
The peak current limit of the transformer primary winding is constant, regardless of the supply voltage,
because there is no added external slope compensation. The saturation current rating of the transformer
primary winding is 6A, and is adequate for the selected RS value of 20mΩ.

3.3.2 Current Sense Resistor Filter Selection

For all designs is it recommended to add a low pass filter to the current sense signal. RF and CF
implement this low pass filter as shown in Figure 1. The filter is added to help mitigate the impact of the
leading edge spike on the current sense signal. RF is selected to be between 10Ω and 200Ω. For this
design RF is selected to be 100Ω. CF must be less than the value specified in Equation 15 to ensure
proper operation.
1 D 1 0.357
CF 1.89nF
3 ˜ RF ˜ fSW 3 ˜ 100: ˜ 250kHz (15)
CF is selected to be 470pF.

3.4 MOSFET Selection

MOSFET selection for a flyback controller focuses on power dissipation and voltage rating. Power
dissipation of MOSFET is composed of two different parts, conduction losses and switching losses.
Conduction losses are dominated by the RDS(ON) resistance of the MOSFET. Switching losses occur during
the rise time and fall time of the switch node, when the N-channel MOSFET is turning on and turning off.
During the rise time and fall time, current through the MOSFET channel and a large voltage drop across
the drain to source are present, resulting in power dissipation. The longer the rise and fall time of the
switch node the higher the switching losses. Selecting a MOSFET with minimal parasitic capacitances
decreases the switching losses.

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The total gate charge (QG_total) must be small enough to keep the internal VCC regulator from entering
current limit. The QG_total for a given MOSFET can be found in the component datasheet. Equation 16
provides the maximum total gate charge of the MOSFET for the selected switching frequency. The QG_total
of the selected MOSFET is 35nC.
35mA
QG _ total
fSW (16)
The RMS current of the MOSFET is estimated using Equation 17. By estimating the switch RMS current, a
MOSFET with an adequately small RDS(ON) value is selected.
§§ P ·
2
'ILM2 ·¸ § § 20.2W ·2 1.2242 ·
IMOS _ RMS ¨
D˜ ¨ OUT _ total
¸ 0.357 ˜ ¨ ¨ ¸ 1.89A
¨ ©¨ VSUPPLY _ min ˜ D ¹¸ 12 ¸ ¨ © 18V ˜ 0.357 ¹¸ 12 ¹¸
© ¹ © (17)
The RDS(ON) of the selected MOSFET is 8.7mΩ.
The drain to source break down voltage rating on the MOSFET needs to be higher than the reflected
secondary side voltage plus the maximum input voltage as calculated in Equation 18.
§N · § 1 ·
VDS ! ¨ P VLOAD ¸ VSUPPLY _ max ¨ 0.5 ˜ 5V ¸ 36V 46V
N
© S ¹ © ¹ (18)
Due to the parasitic leakage inductance of the primary winding, the switch node voltage rings well above
the value calculated in Equation 18. To overcome the ringing on the switch node a voltage clamp can be
added. Designing this clamp is not described in this application report. For this design a MOSFET with a
voltage rating of 100V is selected.

3.5 Diode Selection

The diode on the secondary side must have a reverse voltage rating greater than the reflected voltage for
the primary transformer winding to the secondary winding plus the secondary load voltage. The reverse
voltage of the secondary diode is calculated in Equation 19.
§ NS · § 0.5 ·
VD _ r e verse ¨ ˜ VSUPPLY _ max ¸ VLOAD ¨ 1 ˜ 36V ¸ 5V 23V
© NP ¹ © ¹ (19)
Due to leakage inductance there will be a negative spike when the primary side switch is being turned off.
A snubber should be added across the diode to help minimize this voltage spike. Even if a snubber is
added, some voltage margin must be added to the value calculated in Equation 19. For this application, a
diode with a reverse voltage rating of 40V is selected.
The average current of the secondary side diode is estimated using Equation 20.
ID _ AVG ILOAD 5A (20)
The diode must be able to conduct the value calculated in Equation 20 with some margin. For the design,
the selected diode is capable of conducting 10A of average forward current.

3.6 Output Capacitor Selection

The output capacitor is required to smooth the load voltage ripple, provides an energy source during load
transients and provides energy to the load during the on-time of the MOSFET. A practical way to size the
output capacitor is based on the required load transient specification. The load transient specification is
related to the control loop crossover frequency. For this estimate it is expected that the control loop cross
over frequency is set to 1/5th the right half plane zero frequency. This right half plane zero frequency is
calculated using Equation 21.
VLOAD 2 2
52
2
˜ D' 2 ˜ 1 0.357
2
fZ _ RHP NP POUT _ total 1
fCROSS ˜ ˜ 20.2W 8.68kHz
5 NS 2 5 ˜ 2 ˜ S ˜ LM 0.52 5 ˜ 2 ˜ S ˜ 21PH (21)

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For this design example, the load transient specification indicates that the load voltage should not
overshoot or undershoot more than 100mV during a load transient from 50% load current (2A) to 100%
load current (4A) occurs. Equation 22 is used to calculate the estimated load capacitance to achieve the
specified load transient load voltage ripple requirements.
'ILOAD 2A
CLOAD _ min 366PF
2S ˜ fCROSS ˜ 'VLOAD 2S ˜ 8.6kHz ˜ 100mV

where
• ΔILOAD is the difference in the load current conditions (4A - 2A)
• ΔVLOAD is the specified overshoot voltage specification and undershoot voltage specification (22)
In this design CLOAD is selected to be 540µF.

3.7 Input Capacitor Selection

The input capacitors smooth the supply ripple voltage during operation. For this design, the input voltage
ripple is designed to be less than 50mV when the supply voltage is at the minimum value. Equation 23 is
used to estimate the required input capacitor based on the supply ripple voltage specification.
POUT _ total
˜ (1 D) 20.2W ˜ (1 0.357)
VSUPPLY _ min 18V
CIN _ min 57.7PF
'VSUPPLY ˜ fSW 50mV ˜ 250kHz (23)
The input capacitor is selected to be 100µF. Ceramic capacitors are added to help lower the ESR of the
input capacitor bank.

3.8 UVLO Resistor Selection

The external under voltage lockout (UVLO) resistors set the minimum operating supply voltage of the
regulator. Two levels must be specified; the voltage the LM5155 starts operation (VSUPPLY(ON)) and the
voltage the LM5155 enters stand-by mode (VSUPPLY(OFF)). In this example, VSUPPLY(ON) voltage is 17V and the
VSUPPLY(OFF) is 16V. Using Equation 24, the top UVLO resistor (RUVLOT) is calculated.
0.967 ˜ VSUPPLY(ON) VSUPPLY(OFF) 0.967 ˜ 17V 16V
RUVLOT 86.66k:
5PA 5PA (24)
RUVLOT is selected to be 100kΩ. RUVLOB is calculated using Equation 25.
1.5V ˜ RUVLOT 1.5V ˜ 100k:
RUVLOT 9.67k:
VSUPPLY(ON) 1.5V 17V 1.5V (25)
RUVLOB is selected to be 9.67kΩ.

3.9 Control Loop Compensation

In this section, a general technique is described to stabilize the control loop for a peak current mode
controlled flyback regulator in continuos conduction mode operation. Figure 2 shows circuit that
implements the isolated feedback path. To maintain the voltage isolation between the primary side and
secondary side an optocoupler is used. In Figure 2 the FB pin of the LM5155 is tied to ground. COPTO is
the parasitic capacitance of the optocoupler. This value is dependent upon the selected RPULLUP value and
can be estimated using the optocoupler datasheet. Assuming the CCOMP is much larger than COPTO, helps
to simplify the loop calculations. However, a pole is formed by RPULLUP and COPTO which should be
considered for accurate loop modeling. For a detailed model of the isolated feedback transfer function see
Table 6.
There are many different strategies to set the crossover frequency of the control loop, and correctly place
the poles and zeros of the feedback path to achieve stable operation. The loop compensation selection
process is broken down into a number of simplified steps described in the following sections.

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VPULLUP VLOAD

RLED
RPULLUP
KOPTO
VCOMP

COPTO

RFBT
CCOMP

CCOMP
RCOMP
RCOMP

VREF

RFBB
Figure 2. Isolated Feedback

3.9.1 Feedback Resistor Selection

To implement the circuit shown in Figure 2, a voltage reference must first be selected. The TLV431 is
selected due to the low reference voltage of 1.24V. For higher load voltage designs is it acceptable to use
the TL431, with a reference voltage of 2.5V. The load voltage of this designs is 5V, selecting a reference
voltage of 1.24V allows for more headroom to ensure the voltage reference is properly biased. The top
feedback resistor, RFBT, is selected to be 30kΩ in this design. Equation 26 is used to calculate the lower
feedback resistor, RFBB.
RFBT 30k:
RFBB 9.89k:
VLOAD 5V
1 1
VREF 1.24V (26)
RFBB is selected to be the standard value of 9.78kΩ.

3.9.2 RPULLUP Selection

A resistor between VPULLUP and VCOMP is suggested to implement the feedback circuit. This pull-up voltage
can vary depending on the auxiliary winding voltage or can be the VCC voltage of the LM5155. For this
design the VPULLUP rail is connected to the auxiliary winding of 10V. Equation 27 is used to calculate the
minimum RPULLUP value.
VPULLUP VCOMP _ max 10V 2.5V
RPULLUP ! 4.66k:
ICOMP _ clamp 1.6mA (27)
RPULLUP is selected to be 4.99kΩ.

3.9.3 Optocoupler Selection

When selecting a optocoupler a few major parameters need to be considered: current transfer ratio (CTR),
diode voltage drop on the secondary side, and the capacitance of the BJT on the primary side. In the
following equations CTR is synonymous with kOPTO, the diode drop with VD and the BJT capacitance with
COPTO in Figure 2.
• The CTR varies drastically based on the selected component. There can be as large as 600% variance
in the CTR value over operating conditions. Due to this large tolerance in CTR, the loop compensation
component selection needs to account for the minimum CTR value and maximum CTR value. In this
design the CTR of the selected optocoupler is 100% to 200%.
• The diode voltage drop impacts the selection of the RLED value. The diode drop need to be small
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enough to allow the voltage reference to be supplied with adequate voltage to ensure operation. The
diode drop of the selected optocoupler is 1.4V.
• The pull-up resistor (RPULLUP) and the parasitic capacitance (COPTO) form a pole, limiting the maximum
crossover frequency of the control loop. Once the pull-up resistor is selected the capacitance of the
optocoupler is calculated from the optocoupler datasheet. The selected optocoupler the capacitance is
calculated to be approximately 3.3nF. The cross over frequency should be less than the pole, which is
roughly 9.66kHz for this design.
Table 3 summarizes the key parameters of the selected optocoupler.

Table 3. Selected Optocoupler parameters

Parameter Value
kOPTO_min 100%
kOPTO_max 200%
VD 1.4V
COPTO 3.3nF
VCE(sat) 200mV

3.9.4 RLED Selection

The resistor in series with the optocoupler diode, RLED, directly affects the mid-band gain of control loop.
Equation 28 is used to calculated the maximum value of RLED ensuring that VCOMP voltage on the primary
side can be pulled to the saturation voltage of the optocoupler BJT, VCE(sat).
VLOAD VREF VD ˜ RPULLUP ˜ K OPTO _ min 5V 1.24V 1.4V ˜ 4.99k: ˜ 1
RLED 1.2k:
VPULLUP VCEsat 10V 200mV (28)
RLED is selected to be 1kΩ.

3.9.5 Crossover Frequency Selection

The crossover frequency of the loop is selected to be 1/5th the right half plane zero frequency, and less
than the pole set by the BJT capacitance and the pull-up resistor. Equation 29 details how to calculate the
1/5th the right half plane zero frequency.
VLOAD 2 2
52
˜ D' ˜ 1 0.357
2
fZ _ RHP NP 2 POUT _ total 12
20.2W
fCROSS ˜ ˜ 8.68kHz
5 NS 2 5 ˜ 2 ˜ S ˜ LM 0.52 5 ˜ 2 ˜ S ˜ 21PH (29)
The crossover frequency (fCROSS) is selected less than 1/5th the right half plane zero frequency. To allow for
component tolerances over temperature and process, a crossover frequency of 6kHz is selected.

3.9.6 Determine Required RCOMP

The RCOMP value directly affects the crossover frequency of the control loop. The higher the crossover
frequency, the faster the control loop reacts to transient conditions. Decreasing the RCOMP resistance value
lowers the crossover frequency but helps ensure the control loop remains stable over the specified supply
voltage range. Knowing the desired loop crossover frequency, 6kHz, RCOMP is calculate using Equation 30.
NS 2 ˜ S ˜ CLOAD ˜ RCS ˜ fCROSS ˜ RLED 0.5 2 ˜ S ˜ 540PF ˜ 20m: ˜ 6kHz ˜ 1k:
RCOMP ˜ ˜ 1.15k:
NP GCOMP ˜ KOPTO _ max ˜ (1 D) 1 0.142 ˜ 2 ˜ (1 0.357) (30)
RCOMP is selected to be 1kΩ.

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3.9.7 Determine Required CCOMP

The RCOMP resistor and CCOMP capacitor set a low frequency zero of the compensation network, providing a
phase boost. Placement of this zero frequency largely impacts the transient response of the control loop.
A good strategy to help ensure adequate phase margin is to place the zero at geometric mean of the
crossover frequency (fCROSS) and the low frequency pole of the modulator. Equation 31 places the low
frequency zero of error amplifier a the geometric mean of fCROSS and low frequency pole of the plant
(ωP_LF).
CLOAD ˜ VLOAD 2 540PF ˜ 5V 2
CCOMP 120nF
2 ˜ S ˜ RCOMP 2 ˜ fCROSS ˜ 1 D 2 ˜ S ˜ 1k: 2 ˜ 6kHz ˜ 1 0.217

where
• D is the duty cycle at the maximum supply voltage (0.217) (31)
For this design CCOMP is selected to be 220nF to help ensure extra phase margin.

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4 Component Selection Summary

VSUPPLY NP NS VLOAD

CIN CLOAD
NAUX
ISO_GND

VAUX

VCC
RUVLOT BIAS GATE

UVLO/SYNC CS
RUVLOB RS VAUX
LM51551
AGND PGND RPULLUP

FB RLED
PGOOD
RT COMP
SS RFBT
CCOMP CCOMP RCOMP
RT
RCOMP
VREF

Figure 3. Application Circuit

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Control Loop Response
Efficiency vs I LOAD VSUPPLY = 18V, ILOAD = 4A
60 180
100 Gain
Phase

40 120

20 60
90

Phase (deg)
Gain (dB)
0 0

80 -20 -60
Efficiency (%)

-40 -120

70 -60 -180
500 700 1000 2000 3000 5000 7000 10000 20000 30000 50000 100000 200000 300000 500000
Frequency (Hz) Loop

60

VIN = 36V
VIN = 24V
50 VIN = 18V

40
0 0.5 1 1.5 2 2.5 3 3.5 4
ILOAD (A) Effi

Figure 4. Efficiency vs ILOAD Figure 5. Control Loop Response VSUPPLY = 18V, ILOAD = 4A

D1 Q1

Figure 6. Load Step: ILOAD 2A to 4A, VSUPPLY = 18V Figure 7. Thermal Image: VSUPPLY = 18V, ILOAD = 4A

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Figure 8. LM5155EVM-FLY Schematic

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Table 4. List of Components

Item Qty Value Description Package Part Mfr
Ref Number
C1 1 680pF CAP, CERM, 680 pF, 100 V, +/- 10%, 0603 GRM188R72A681KA01D MuRata
X7R, 0603
C2 1 100uF CAP, Polymer Hybrid, 100 uF, 50 V, +/- 10x10 EEHZC1H101P Panasonic
20%, 28 ohm, 10x10 SMD
C3 1 0.1uF CAP, CERM, 0.1 uF, 50 V, +/- 20%, 0805 08055C104MAT2A AVX
X7R, 0805
C4, C5 2 1uF CAP, CERM, 1 uF, 50 V, +/- 10%, X7R, 0805 08055C105KAT2A AVX
0805
C6 1 4.7uF CAP, CERM, 4.7 uF, 50 V, +/- 10%, 1206 C3216X7R1H475K160AC TDK
X7R, 1206
C7, C8 2 270uF CAP, Aluminum Polymer, 270 uF, 25 V, D10xL12.7 PCV1E271MCL1GS Nichicon
+/- 20%, 0.027 ohm, D10xL12.7mm mm
SMD
C9, C10 2 10uF CAP, CERM, 10 uF, 25 V,+/- 10%, X7R, 1210 885012209028 Wurth
1210 Elektronik
C11, C13 2 0.1uF CAP, CERM, 0.1 uF, 25 V, +/- 10%, 0603 C1608X7R1E104K080AA TDK
X7R, 0603
C12 1 1000pF CAP, CERM, 1000 pF, 25 V, +/- 10%, 0603 GRM188R71E102KA01D MuRata
X7R, 0603
C14 1 0.01uF CAP, CERM, 0.01 uF, 50 V, +/- 10%, 0603 GCM188R71H103KA37D MuRata
X7R, AEC-Q200 Grade 1, 0603
C15 1 4.7uF CAP, CERM, 4.7 uF, 35 V, +/- 10%, 0603 GRM188R6YA475KE15D MuRata
X5R, 0603
C16 1 0.33uF CAP, CERM, 0.33 uF, 100 V, +/- 10%, C3216X7R2A334K130AA TDK
X7R,
C17 1 1uF CAP, CERM, 1 uF, 16 V, +/- 20%, X7R, 0603 GCM188R71C105MA64D MuRata
AEC-Q200 Grade 1, 0603
C18 1 0.1uF CAP, CERM, 0.1 uF, 50 V, +/- 10%, 0603 C1608X7R1H104K080AA TDK
X7R, 0603
C19 1 470pF CAP, CERM, 470 pF, 50 V, +/- 10%, 0603 GRM188R71H471KA01D MuRata
X7R, 0603
C20 1 4.7uF CAP, CERM, 4.7 µF, 25 V,+/- 10%, X6S, 0603 GRT188C81E475KE13D MuRata
AEC-Q200 Grade 2, 0603
C21 1 220pF CAP, CERM, 220 pF, 50 V, +/- 5%, 0603 C0603C221J5GACTU Kemet
C0G/NP0, 0603
C22 1 0.01uF CAP, CERM, 0.01 uF, 16 V, +/- 10%, 0603 GRM188R71C103KA01D MuRata
X7R, 0603
C24, C26 2 0.22uF CAP, CERM, 0.22 µF, 16 V,+/- 10%, 0603 CL10B224KO8VPNC Samsung
X7R, AEC-Q200 Grade 1, 0603
C28 1 1000pF CAP, CERM, 1000 pF, 2000 V, +/- 10%, 1812 1812GC102K1A AVX
X7R, 1812
D1 1 40V Diode, Schottky, 40 V, 10 A, AEC-Q101, TO-277A SS10P4-M3/87A Vishay-
TO-277A Semiconductor
D2 1 100V Diode, Switching, 100 V, 0.2 A, SOD- SOD-323 MMDL914-TP Micro
323 Commercial
Components
D3 1 150V Diode, Superfast Rectifier, 150 V, 1 A, SMA ES1C-13-F Diodes Inc.
SMA
D4 1 30V Diode, Schottky, 30 V, 0.2 A, SOT-323 SOT-323 BAT54SWT1G Fairchild
Semiconductor
H1, H2, 4 Bumpon, Cylindrical, 0.312 X 0.200, Black SJ61A1 3M
H3, H4 Black Bumpon

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Table 4. List of Components (continued)

J1, J2 2 Terminal Block, 5mm, 2-pole, TH TH, 2- ED350/2 On-Shore
Leads, Technology
Body
10x9mm,
Pin
Spacing
5mm
J3, TP9 2 TEST POINT SLOTTED .118", TH Test point, 1040 Keystone
TH Slot
Test point
J4 1 Header, 2.54mm, 5x1, Tin, TH Header, PEC05SAAN Sullins
2.54mm, Connector
5x1, TH Solutions
Q1 1 100V MOSFET, N-CH, 100 V, 13 A, DQJ0008A CSD19533Q5A Texas
DQJ0008A (VSONP-8) Instruments
R1 1 15.0 RES, 15.0, 1%, 0.5 W, 1210 1210 ERJ-14NF15R0U Panasonic
R2, R11 2 100 RES, 100, 1%, 0.1 W, AEC-Q200 Grade 0603 ERJ-3EKF1000V Panasonic
0, 0603
R3 1 0 RES, 0, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 RMCF0603ZT0R00 Stackpole
0603 Electronics Inc
R4 1 30.1k RES, 30.1 k, 1%, 1 W, AEC-Q200 2512 CRCW251230K1FKEG Vishay-Dale
Grade 0, 2512
R5, R8, 5 0 RES, 0, 5%, 0.1 W, AEC-Q200 Grade 0, 0603 ERJ-3GEY0R00V Panasonic
R10, R24, 0603
R26
R6, R9, 3 100k RES, 100 k, 1%, 0.1 W, AEC-Q200 0603 CRCW0603100KFKEA Vishay-Dale
R13 Grade 0, 0603
R7 1 10.0 RES, 10.0, 1%, 0.1 W, AEC-Q200 0603 CRCW060310R0FKEA Vishay-Dale
Grade 0, 0603
R12 1 0.02 RES, 0.02, 1%, 1 W, 0612 0612 PRL1632-R020-F-T1 Susumu Co Ltd
R14 1 1.00k RES, 1.00 k, 1%, 0.1 W, 0603 0603 ERJ-3EKF1001V Panasonic
R16, R22 2 9.76k RES, 9.76 k, 1%, 0.1 W, AEC-Q200 0603 CRCW06039K76FKEA Vishay-Dale
Grade 0, 0603
R17 1 86.6k RES, 86.6 k, 1%, 0.1 W, AEC-Q200 0603 CRCW060386K6FKEA Vishay-Dale
Grade 0, 0603
R18 1 4.99k RES, 4.99 k, 1%, 0.1 W, AEC-Q200 0603 CRCW06034K99FKEA Vishay-Dale
Grade 0, 0603
R19 1 30.0k RES, 30.0 k, 1%, 0.1 W, 0603 0603 RC0603FR-0730KL Yageo
R20, R21 2 1.00k RES, 1.00 k, 0.1%, 0.1 W, AEC-Q200 0603 ERA3AEB102V Panasonic
Grade 0, 0603
T1 1 21uH Transformer, 21 uH, SMT 13.97x18.2 750317933 Wurth
5mm Elektronik
TP1, TP2 2 Test Point, Miniature, Red, TH Red 5000 Keystone
Miniature
Testpoint
TP3, TP4, 3 Test Point, Miniature, Black, TH Black 5001 Keystone
TP8 Miniature
Testpoint
TP5 1 PC Test Point, SMT PC Test 5017 Keystone
Point, SMT
U1 1 2.2-MHz Wide Input Nonsynchronous DSS0012B LM5155DSST Texas
Boost, Sepic, Flyback Controller, Instruments
DSS0012B (WSON-12)
U2 1 Optocoupler, 2.5 kV, 100-200% CTR, PS2811-1 PS2811-1-M-A California
SMT Eastern
Laboratories
U3 1 Low-Voltage (1.24V) Adjustable DBZ0003A LMV431BIMF/NOPB Texas
Precision Shunt Regulators, 3-pin SOT- Instruments
23, Pb-Free

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www.ti.com Small Signal Frequency Analysis

5 Small Signal Frequency Analysis

This section provides detailed equations used to model the control loop when the LM5155 is configured as
an isolated flyback regulator. These equations are only valid when the regulator is operating in continuous
conduction mode. The simplified formulas allow for quick evaluation of the control loop, but loose accuracy
at high frequencies. The comprehensive formulas are more complex but provide better accuracy at high
frequencies.

5.1 Flyback Regulator Modulator Modeling

These equations model the plant of a peak current mode flyback regulator in continuous conduction mode.

Table 5. Control Loop Equations

Simplified Formula Comprehensive Formula
Modulator Equations

§ § s ·§ s ·
s ·§ s · š ¨¨ 1 ¸¸ ¨¨ 1 ¸¸
š ¨¨ 1 ¸¸ ¨¨ 1 ¸¸ Z Z
AM ©
Z Z v LOAD (s) Z _ ESR ¹ © Z _ RHP ¹
AM ©
Modulator Transfer v LOAD (s) Z _ ESR ¹ © Z _ RHP ¹
š
Function š § s ·§ s s2 ·
v COMP (s) § s · v COMP (s) ¨¨ 1 ¸¸ ¨ 1 ¸
¨¨ 1 ¸ ZP _ LF ¹ © Q ˜ Zn Zn2 ¹
© ZP _ LF ¸¹ (32)
©
(33)

NP VLOAD 2 1 D
Modulator DC Gain AM GCOMP ˜
NS POUT 1 D ACS ˜ RS (34)

NP 2 VLOAD 2 2
˜ 1 D
RHP Zero NS 2 POUT
ZZ _ RHP
LM ˜ D (35)
1
ESR Zero ZZ _ ESR
CLOAD ˜ RESR (36)
1 D
ZP _ LF 2
Low Frequency Pole V
CLOAD ˜ LOAD
POUT (37)
Sub-Harmonic Double
Pole Not Considered Zn S ˜ fsw (38)

1
Q
Quality Factor Not Considered ª § s · 1º
S «Dc ˜ ¨ 1 e ¸ »
¬ © sn ¹ 2¼ (39)
Slope Compensation Not Considered se VSLOPE ISLOPE ˜ RSL ˜ fsw (40)

Sensed Rising Inductor VSUPPLY ˜ 1 D ˜ RS ˜ A CS

Slope Not Considered sn
LM (41)

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5.2 Compensation Modeling

These equation model the isolate compensation network shown in Figure 2.

Table 6. Compensation Modeling Equations

Simplified Formula Comprehensive Formula
Feedback Equations

§ s ·§ s · § s ·§ s ·
š ¨¨ 1 ¸¸ ¨¨ 1 ¸¸ š ¨¨ 1 ¸¸ ¨¨ 1 ¸
Z Z ZZ1_ EA ¹ © ZZ2 _ EA ¸¹
AFB ©
Feedback Transfer v COMP (s) Z1_ EA ¹ © Z2 _ EA ¹ v COMP (s) ©
Function š AFB
v LOAD (s) § s · š
s ˜ k1 ˜ s 2 k 2 ˜ s 1
s ˜ ¨1 ¸ v LOAD (s)
¨ ¸
ZP _ EA ¹
© (42) (43)

K OPTO ˜ RPULLUP
Feedback DC Gain AFB
RLED ˜ RFBT ˜ CCOMP (44)
1
First Low Frequency Zero ZZ1_ EA
RCOMP RFBT ˜ CCOMP (45)

Second Low Frequency 1

Zero
ZZ2 _ EA
RCOMP ˜ CCOMP (46)
1
Low Frequency pole ZP _ EA N/A
RCOMP RPULLUP ˜ CHF (47)
K1 Not Considered k1 CCOMP ˜ COPTO ˜ RCOMP ˜ RPULLUP (48)
k2 CCOMP ˜ R COMP RPULLUP COPTO ˜ RPULLUP
K2 Not Considered
(49)

K OPTO ˜ RCOMP K OPTO ˜ RCOMP ˜ RFBT RCOMP

Mid-band Gain GMID GMID
RLED (50) RLED ˜ RFBT ˜ RCOMP RPULLUP (51)

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