USB Type-C Port Controller: General Description
USB Type-C Port Controller: General Description
USB Type-C Port Controller: General Description
General Description
EZ-PD™ CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4 provides
a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power adapters and docking stations. It
can also be used in dual role and downstream facing port applications. EZ-PD CCG4 uses Cypress’s proprietary M0S8 technology
with a 32-bit, 48-MHz Arm® Cortex®-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the
Type-C termination resistors RP and RD.
Notes
1. UFP refers to Power Sink.
2. DFP refers to Power Source.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-98440 Rev. *K Revised June 26, 2018
EZ-PD™ CCG4
4 x TCPWM 1 CC_PORT1 5
CORTEX-M0 4 x SCB2
2x V CONN
Flash 2 x Baseband MAC
FETs
(128KB) (PORT2)
2 x Baseband PHY
GPIOs6
Contents
Available Firmware and Software Tools ......................... 4 Packaging ........................................................................ 28
EZ-PD Configuration Utility ......................................... 4 Acronyms ........................................................................ 30
EZ-PD CCG4 Block Diagram ............................................ 4 Document Conventions ................................................. 31
Functional Overview ........................................................ 5 Units of Measure ....................................................... 31
CPU and Memory Subsystem ..................................... 5 References and Links to Applications Collaterals ...... 32
USB-PD Subsystem (SS) ............................................ 5 Knowledge Base Articles ........................................... 32
System Resources ...................................................... 6 Application Notes ...................................................... 32
Peripherals .................................................................. 7 Reference Designs .................................................... 32
GPIO ........................................................................... 7 Kits ............................................................................ 32
Pinouts .............................................................................. 8 Datasheets ................................................................ 32
Power ............................................................................... 16 Document History Page ................................................. 33
Application Diagrams ..................................................... 17 Sales, Solutions, and Legal Information ...................... 35
Electrical Specifications ................................................ 19 Worldwide Sales and Design Support ....................... 35
Absolute Maximum Ratings ....................................... 19 Products .................................................................... 35
Device-Level Specifications ...................................... 20 PSoC® Solutions ...................................................... 35
Digital Peripherals ..................................................... 23 Cypress Developer Community ................................. 35
Memory ..................................................................... 24 Technical Support ..................................................... 35
System Resources .................................................... 25
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
CPU Subsystem
CCG4
SWD/TC SPCIF
Cortex
32-bit FLASH SRAM ROM
M0
128 KB 8 KB 8 KB
48 MHz
AHB-Lite FAST MUL
Read Accelerator SRAM Controller ROM Controller
NVIC, IRQMX
System Resources
Lite
System Interconnect (Single Layer AHB)
Power
Sleep Control Peripherals
WIC
POR REF
PWRSYS
PCLK Peripheral Interconnect (MMIO)
Clock
Clock Control
WDT 2 x USB-PD 3.0
IMO ILO
4 x TCPWM
IOSS GPIO (5 x ports)
4 x SCB
Reset
Reset Control
XRES
2 X VCONN FET
2 x SAR ADC
CC BB PHY
Test
DFT Logic
DFT Analog
Pads, ESD
Power Modes High Speed I/O Matrix
Active/Sleep
Deep Sleep
27 x GPIOs, 2 OVTs
I/O Subsystem
From AMUX
TX Rp
CRC CC1
Rx_data RX RD1
to AHB Rx 4b5b SOP BMC
SRAM Decoder Detect Decoder CC2
Ref
Comp DB
Active Rd RD2
CC control Rd
CC detect
8kV IEC ESD
2 x Analog Baseband PHY
Deep Sleep Reference Enable Deep Sleep RD1 shorted to CC1 and RD2 shorted to CC2 for DRP applications using
Vref & Iref Gen vref, iref bondwire. For DFP applications, RD1 and RD2 not shorted to CC1 and CC2.
Dead Battery (DB) Rd termination removed after MCU boots up
Functional, Wakeup Interrupts
System Resources CCG4 can operate from three different power sources over the
Power System range of 2.7 to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
The power system is described in detail in the section Power on EZ-PD CCG4 provides Sleep and Deep Sleep low-power
page 16. It provides the assurance that voltage levels are as modes.
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are Clock System
as required for proper function or generate resets (brown-out The clock system for EZ-PD CCG4 consists of the internal main
detect (BOD)) or interrupts (low voltage detect (LVD)). EZ-PD oscillator (IMO) and the internal low-power oscillator (ILO).
Peripherals GPIO
Serial Communication Blocks (SCB) EZ-PD CCG4 has 30 GPIOs that includes the I2C and SWD pins,
EZ-PD CCG4 has four SCBs, which can be configured to which can also be used as GPIOs. The I2C pins from only
implement an I2C, SPI, or UART interface. The hardware I2C SCB 1 are overvoltage-tolerant. The number of available GPIOs
blocks implement full multi-master and slave interfaces capable vary with the part numbers. The GPIO block implements the
of multimaster arbitration. In the SPI mode, the SCB blocks can following:
be configured to act as a master or a slave. ■ Seven drive strength modes:
In the I2C mode, the SCB blocks are capable of operating at ❐ Input only
speeds up to 1 Mbps (Fast Mode Plus) and have flexible ❐ Weak pull-up with strong pull-down
buffering options to reduce interrupt overhead and latency for the ❐ Strong pull-up with weak pull-down
CPU. These blocks also support I2C that creates a mailbox ❐ Open drain with strong pull-down
address range in the memory of EZ-PD CCG4 and effectively ❐ Open drain with strong pull-up
reduce I2C communication to reading from and writing to an ❐ Strong pull-up with strong pull-down
array in memory. In addition, the blocks support 8-deep FIFOs
❐ Weak pull-up with weak pull-down
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock ■ Input threshold select (CMOS or LVTTL)
stretching caused by the CPU not having read data on time.
■ Individual control of input and output buffer enabling/disabling
The I2C peripherals are compatible with the I2C Standard-mode, in addition to the drive strength modes
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus ■ Hold mode for latching previous state (used for retaining I/O
I/Os are implemented with GPIO in open-drain modes. state in Deep Sleep mode)
The I2C port on SCB 2, SCB 3 and SCB 4 blocks of EZ-PD CCG4 ■ Selectable slew rates for dV/dt related noise control to improve
are not completely compliant with the I2C spec in the following: EMI
■ The GPIO cells for SCB 2 to SCB 4 I2C port are not During power-on and reset, the I/O pins are forced to the disable
overvoltage-tolerant and, therefore, cannot be hot-swapped or state so as not to crowbar any inputs and/or cause excess
powered up independently of the rest of the I2C system. turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of connect to an I/O pin.
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
■ Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
Pinouts
Table 1. Pinout for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT
Group Pin Name Pin Number Description
USB Type-C CC1_P1 9 USB PD connector detect/Configuration Channel 1
Port 1
CC2_P1 7 USB PD connector detect/Configuration Channel 2
USB Type-C CC1_P2 22 USB PD connector detect/Configuration Channel 1
Port 2
CC2_P2 24 USB PD connector detect/Configuration Channel 2
VBUS VBUS_P_CTRL_P1 11 Full rail control I/O for enabling/disabling Provider load FET of
Control USB Type-C port 1
VBUS_C_CTRL_P1 12 Full rail control I/O for enabling/disabling Consumer load FET of
USB Type-C port 1/SCB1 (see Table 3 on page 13 through
Table 6 on page 13)
VBUS_P_CTRL_P2 39 Full rail control I/O for enabling/disabling Provider load FET of
USB Type-C port 2
VBUS_C_CTRL_P2 38 Full rail control I/O for enabling/disabling Consumer load FET of
USB Type-C port 2
VBUS_DISCHARGE_P1 20 I/O used for discharging VBUS line during voltage change
VBUS_DISCHARGE_P2 40 I/O used for discharging VBUS line during voltage change
VCONN VCONN_MON_P1/GPIO 19 VCONN_MON_P1 (Monitor VCONN for UVP condition on port
Control 1)/GPIO
SCL_3/VCONN_MON_P2 25 SCB3 (see Table 3 on page 13 through Table 6 on page 13) or
VCONN_MON_P2(Monitor VCONN for UVP condition on port
2)
Overvoltage OVP_TRIP_P1 14 VBUS overvoltage output indicator for port 1 (active LOW)
Protection
(OVP) OVP_TRIP_P2 21 VBUS overvoltage output indicator for port 2 (active LOW)
Note
3. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable I/O buffers.
Figure 3. 40-pin QFN Pin Map (Top View) for CYPD4225-40LQXIT, CYPD4226-40LQXIT, and CYPD4236-40LQXIT
MUX_CTRL_3_P2/OCP_DET_P2
MUX_CTRL_1_P2/GPIO
MUX_CTRL_2_P2/GPIO
VBUS_DISCHARGE_P2
VBUS_MON_P2/GPIO
VBUS_C_CTRL_P2
VBUS_P_CTRL_P2
VDDIO
VCCD
VDDD
40
39
38
37
36
35
34
33
32
31
SWD_IO/AR_RST# 1 30 HPD_P2/GPIO
SWD_CLK/I2C_CFG_EC 2 29 SCL_4/MUX_CTRL_1_P1
I2C_SDA_SCB2_AR/VSEL_1_P1 3 28 SDA_4/MUX_CTRL_2_P1
I2C_SCL_SCB2_AR/VSEL_1_P2 4 27 VSEL_2_P2/GPIO
I2C_INT_AR_P1/OCP_DET_P1 5 26 SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
I2C_INT_AR_P2 6 25 SCL_3/VCONN_MON_P2
CC2_P1 7 24 CC2_P2
V5V_P1 8 23 V5V_P2
CC1_P1 9 22 CC1_P2
XRES 10 21 OVP_TRIP_P2
12
13
17
11
14
15
16
18
19
20
VCONN_MON_P1/GPIO
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
I2C_INT_EC
I2C_SDA_SCB1_EC
VBUS_MON_P1/GPIO
OVP_TRIP_P1
VBUS_DISCHARGE_P1
HPD_P1/GPIO
I2C_SCL_SCB1_EC
VBUS VBUS_P_CTRL_P1 11 Full rail control I/O for enabling/disabling. Provider load FET of
Control USB Type-C port 1.
VBUS_C_CTRL_P1 12 Full rail control I/O for enabling/disabling. Consumer load FET of
USB Type-C port 1/SCB1 (see Table 3 on page 13 through
Table 6 on page 13).
VBUS_DISCHARGE_P1 20 I/O used for discharging VBUS line during voltage change
VCONN VCONN_MON_P1/GPIO 19 VCONN_MON_P1 (Monitor VCONN for OVP condition on
Control port 1)/GPIO
Over OVP_TRIP_P1 14 VBUS overvoltage output indicator for port 1 (active LOW)
voltage
Protection
(OVP)
Note
4. This is firmware configurable GPIO. By default, this pin is floating. Firmware can add pull-up/pull-down and enable/disable IO buffers.
Figure 4. 40-pin QFN Pin Map (Top View) for CYPD4125-40LQXIT and CYPD4126-40LQXIT
OCP_DET_P2/GPIO
VDDIO
VCCD
VDDD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
40
39
38
37
36
35
34
33
32
31
SWD_IO/AR_RST# 1 30 GPIO
SWD_CLK/I2C_CFG_EC 2 29 SCL_4/MUX_CTRL_1_P1
I2C_SDA_SCB2_AR/VSEL_1_P1 3 28 SDA_4/MUX_CTRL_2_P1
I2C_SCL_SCB2_AR 4 27 GPIO
I2C_INT_AR_P1/OCP_DET_P1 5 26 SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
GPIO 6 25 SCL_3
CC2_P1 7 24 NC
V5V_P1 8 23 NC
CC1_P1 9 22 NC
XRES 10 21 GPIO
12
13
17
11
14
15
16
18
19
20
OVP_TRIP_P1
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
I2C_INT_EC
I2C_SDA_SCB1_EC
VBUS_MON_P1/GPIO
VBUS_DISCHARGE_P1
I2C_SCL_SCB1_EC
HPD_P1/GPIO
VCONN_MON_P1/GPIO
VDDD
GND
P1.1
P3.6
24
23
22
21
20
19
P1.2 1 18 P3.4
P1.3 2 17 P3.3
P1.5 3 16 P3.2
24-QFN
CC2 4 15 P3.1
V5V 5 14 P2.6
CC1 6 13 P3.0
10
11
12
7
8
9
P1.7
P0.0
P0.1
P2.3
P2.5
XRES
Power A separate I/O supply pin, VDDIO, allows the GPIOs to operate
at levels from 1.71 V to 5.5 V. The VDDIO pin can be equal to or
The following power system diagram shows the set of power less than the voltages connected to the V5V_P1 or V5V_P2 and
supply pins as implemented in EZ-PD CCG4. VDDD pins. The VDDIO supply should be less than or equal to
VDDD supply.
CCG4 will be able to operate from three possible external supply
sources: V5V_P1 for first Type-C port, V5V_P2 for second Type- The VCCD output of EZ-PD CCG4 must be bypassed to ground
C port and VDDD. via an external capacitor (in the range of 80 to 120 nF; X5R
CCG4 has the power supply input V5V_P1 and V5V_P2 pins for ceramic or better).
providing power to EMCA cables through integrated VCONN Bypass capacitors must be used from VDDD and V5V_P1 or
FETs. There are two VCONN FETs in CCG4 per Type-C port to V5V_P2 pins to ground; typical practice for systems in this
power either CC1 or CC2 pin. These FETs are capable of frequency range is to use a 0.1-µF capacitor on VDDD, V5V_P1
providing a minimum of 1W on the CC1 and CC2 pins for the and V5V_P2. Note that these are simply rules of thumb; for
EMCA cables. In USB-PD applications, the valid levels on critical applications, the PCB layout, lead inductance, and the
V5V_P1 and V5V_P2 supplies can range from 4.85 V to 5.5 V. bypass capacitor parasitic should be simulated to design and
The device’s internal operating power supply is derived from obtain optimal bypassing.
VDDD. In UFP mode, CCG4 operates in 2.7 V– 5.5V. In DFP and Figure 6 shows an example of the power supply bypass
DRP modes, it operates in the 3.0 V–5.5 V range. capacitors.
[6] [7]
CC1_P2 CC2_P2
[5]
V5V_P2
CC1_P1 CC2_P1
V5V_P1 VDDD
Core Regulator
(SRSS-Lite)
VDDIO VCCD
2 x CC
GPIOs Core
Tx/Rx
VSS
Note
5. V5V_P1 denoted power supply input for Type-C port 1
V5V_P2 denoted power supply input for Type-C port 2
6. CC1_1:USB PD connector detect/Configuration Channel 1 for Type-C port 1
CC1_2:USB PD connector detect/Configuration Channel 1 for Type-C port 2
7. CC2_1:USB PD connector detect/Configuration Channel 2 for Type-C port 1
CC2_2:USB PD connector detect/Configuration Channel 2 for Type-C port 2
Application Diagrams For the dual Type-C notebook application, these Type-C ports
can be power providers or power consumers simultaneously. In
Figure 7 and Figure 8 on page 18 show a dual Type-C port and addition, the CCG4 device controls the transfer of DisplayPort
a single Type-C port Notebook DRP application diagram using a signals over the Type-C interface using the display mux
CCG4 device. The Type-C port can be used as a power provider controllers.
or a power consumer. Optional FETs are provided for applications that need to provide
In each of these applications, CCG4 communicates with the power for accessories and cables using VCONN pin of the
Embedded Controller (EC), which manages the Battery Charger Type-C receptacle. VBUS FETs are also used for providing
Controller (BCC) to control the charging and discharging of power over VBUS and for consuming power over VBUS. A
internal battery. It also controls the Data Mux to route the VBUS_DISCHARGE FET controlled by CCG4 device is used to
HighSpeed signals either to the USB chipset (during normal quickly discharge VBUS after the Type-C connection is
mode) or the DisplayPort Chipset (during Alternate Mode).The detached.
SBU, SuperSpeed, and HighSpeed lines are routed directly from
the Display Mux of the notebook to the Type-C receptacle.
Figure 7. CCG4 in a Dual Port Notebook Application using CYPD4225-40LQXIT
HS 2
USB 3.0
SSTX/RX 4
HOST
TX 4
RX 4
MUX
ML_LANE_[0:3]N 4
SBU 2
ML_LANE_[0:3]P 4
DISPLAY PORT
CONTROLLER 1 AUX P/N 2
HPD_P1
I2C_SCL I2C_SDA
VBUS_SINK
49.9KO
4.7 uF 100 KO 4.7 uF
100 KO 2
VBUS_C_CTRL_P1 10 O
100 KO
2
SBU
DP/DM
SSTX/RX
DP/DM
VBUS_SOURCE
VBUS
VBUS_P_CTRL_P1 10 O
32
33
23
1
V5V_P1
V5V_P2
VDDIO
VDDD
VCCD
SWD_IO/AR_RST#
2
SWD_CLK/I2C_CFG_EC 200 O
TYPE-C
TO DISPLAY_PORT HPD_P1 18 VBUS_DISCHARGE_P1 10 O
CONTROLLER 1 HPD_P1/GPIO
VBUS RECEPTACLE 1
100 KO 100 KO
TO DISPLAY PORT HPD_P2 30
HPD_P2/GPIO 13 VBUS_MON_P1
CONTROLLER 2 VBUS_MON_P1/GPIO
19 VCONN_MON_P1/GPIO 10 KO 0.1µF
VSEL_2_P1
VSEL_1_P1
14 7 CC2
OVP_TRIP_P1 CC2_P1
VSEL_2_P2 27 9
VSEL_2_P2/GPIO CC1_P1 CC1
DC/DC
OR VDDIO VDDIO
11 VBUS_P_CTRL_P1
CHARGER AC-DC VBUS_P_CTRL_P1
330pF 330pF
SECONDARY 100 KO
10 VBUS_DISCHARGE_P1
XRES VBUS_DISCHARGE_P1 20 GND
(5-20V) 0.1µF
2.2 KO
21 12 VBUS_C_CTRL_P1
CCG4
VSEL_2_P2
OVP_TRIP_P2
VSEL_1_P2
2.2 KO VBUS_C_CTRL_P1
2.2 KO
EMBEDDED 15
I2C_INT_EC (CYPD4225-40LQXIT)
CONTROLLER 34
17 I2C_SCL_SCB1_EC
40-QFN MUX_CTRL_3_P2/GPIO GND
35
16 MUX_CTRL_2_P2/GPIO
I2C_SDA_SCB1_EC
VSEL_1_P2 4 36
I2C_SCL_SCB2_AR/VSEL_1_P2 MUX_CTRL_1_P2/GPIO
VSEL_1_P1 3 38 VBUS_C_CTRL_P2
I2C_SDA_SCB2_AR/VSEL_1_P1 VBUS_C_CTRL_P2/
5 VBUS_P_CTRL_P2
I2C_INT_AR_P1 VBUS_P_CTRL_P2 39
6
I2C_INT_AR_P2 VBUS_DISCHARGE_P2
VBUS_DISCHARGE_P2 40
VDDIO
25
SCL_3/VCONN_MON_P2/GPIO 24
CC2_P2 CC2
2.2 KO 2.2 KO VSEL_2_P1 26
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1
I2C MASTER I2C_SCL 29 22
CC1_P2 CC1
SCL_4/MUX_CTRL_1_P1/GPIO
FOR ALT VBUS
MODE MUX I2C_SDA 28 330pF 330pF TYPE-C
SDA_4/MUX_CTRL_2_P1/GPIO 100 KO
CONTROL RECEPTACLE 2
EPAD 37 VBUS_MON_P2
CONNECTED VSS
VBUS_MON_P2
TO TYPE-C 10 KO 0.1µF
PORT1 or
PORT2
VBUS_SINK
SSTX/RX
DP/DM
DP/DM
VBUS
SBU
49.9KO
100 KO 2
4.7 uF 4.7 uF
2
VBUS_P_CTRL_P2 10 O
100 KO
VBUS (5-20V)
VBUS_SOURCE
49.9KO
100 KO
4.7 uF
VBUS_P_CTRL_P2 10 O
100 KO
200 O
VBUS_DISCHARGE_P2 10 O
100 KO
HS 2
USB 3.0
SSTX/RX 4
HOST
TX 4
RX 4
MUX
ML_LANE_[0:3]N 4
SBU 2
ML_LANE_[0:3]P 4
DISPLAY PORT
CONTROLLER 2 AUX P/N 2
HPD_P2
I2C_SCL I2C_SDA
USB 3.0
SSTX/RX 4 TX 4
HOST
RX 4
MUX SBU 2
ML_LANE_[0:3]N 4
ML_LANE_[0:3]P 4
DISPLAY PORT
CONTROLLER 1 AUX P/N 2
HPD_P1
VBUS_SINK
I2C_SCL I2C_SDA CHARGER
49.9KO 2
4.7 uF 100 KO
100 KO
VBUS_C_CTRL_P1 10 O
100 KO
2
VSEL_2_P1
DC/DC VBUS (5-20V)
SBU
DP/DM
SSTX/RX
DP/DM
OR VBUS_SOURCE
VSEL_1_P1 AC-DC VBUS
SECONDARY
OPTIONAL VDDIO SUPPLY. CAN SHORT
(5-20V) TO VDDD IN SINGLE SUPPLY SYSTEMS. 49.9KO
4.7 uF 100 KO 4.7 uF
5.0V 5.0V 3.3V VDDIO 100 KO
VBUS_P_CTRL_P1 10 O
31
32
33
23
8
1 200O
V5V_P1
V5V_P2
VDDD
VDDIO
VCCD
SWD_IO/AR_RST#
VBUS_DISCHARGE_P1 10 O
2
SWD_CLK/I2C_CFG_EC
TO DISPLAY_PORT 100 KO TYPE-C
CONTROLLER 1 HPD_P1 18
HPD_P1/GPIO
VBUS RECEPTACLE 1
100 KO
13 VBUS_MON_P1
VBUS_MON_P1/GPIO
19 VCONN_MON__P1/GPIO 10 KO 0.1µF
14 7
OVP_TRIP_P1 CC2_P1 CC2
9
CC1_P1 CC1
VDDIO VDDIO
11 VBUS_P_CTRL_P1 330pF 330pF
VBUS_P_CTRL_P1
100 KO 10 VBUS_DISCHARGE_P1
XRES VBUS_DISCHARGE_P1 20 GND
2.2 KO 0.1µF
21 12 VBUS_C_CTRL_P1
2.2 KO GPIO CCG4 VBUS_C_CTRL_P1
2.2 KO
EMBEDDED 15
I2C_INT_EC
(CYPD4125-40LQXIT)
CONTROLLER 40-QFN GPIO
27
17
I2C_SCL_SCB1_EC
30
16 GPIO
I2C_SDA_SCB1_EC
4 34
I2C_SCL_SCB2_AR GPIO
VSEL_1_P1 3 35
I2C_SDA_SCB2_AR/VSEL_1_P1 GPIO
VDDIO 5
I2C_INT_AR_P1 GPIO 36
6
GPIO
GPIO 37
25 38
2.2 KO SCL_3 GPIO
2.2 KO VSEL_2_P1 26
SDA_3/MUX_CTRL_3_P1/VSEL_2_P1 39
I2C_SCL GPIO
I2C MASTER FOR ALT MODE 29
SCL_4/MUX_CTRL_1_P1 40
MUX CONTROL CONNECTED TO I2C_SDA GPIO
28
TYPE-C PORT1 SDA_4/MUX_CTRL_2_P1 24
NC
EPAD
VSS 22
NC
Electrical Specifications
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings[8]
Parameter Description Min Typ Max Units Details/Conditions
VDDD_MAX Digital supply relative to VSS –0.5 – 6 V Absolute max
V5V_P1 Max supply voltage relative to VSS – – 6 V Absolute max
V5V_P2 Max supply voltage relative to VSS – – 6 V Absolute max
VDDIO_MAX Max supply voltage relative to VSS – – 6 V Absolute max
VGPIO_ABS GPIO voltage –0.5 – VDDIO + 0.5 V Absolute max
IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute max
IGPIO_injection GPIO injection current, Max for VIH –0.5 – 0.5 mA Absolute max, current
> VDDD, and Min for VIL < VSS injected per pin
ESD_HBM Electrostatic discharge human 2200 – – V –
body model
ESD_CDM Electrostatic discharge charged 500 – – V –
device model
LU Pin current for latch-up –200 – 200 mA –
ESD_IEC_CON Electrostatic discharge 8000 – – V Contact discharge on CC1
IEC61000-4-2 and CC2 pins
ESD_IEC_AIR Electrostatic discharge 15000 – – V Air discharge for pins CC1
IEC61000-4-2 and CC2
Note
8. Usage above the absolute maximum conditions listed in Table 8 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,
except where noted.
Table 9. DC Specifications
I/O
Table 11. I/O DC Specifications
XRES
Table 13. XRES DC Specifications
Note
9. VIH must not exceed VDDIO + 0.2 V.
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Pulse Width Modulation (PWM) for GPIO Pins
Table 14. PWM AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.TCPWM.3 TCPWMFREQ Operating frequency – Fc – MHz Fc max = CLK_SYS. Maximum = 48 MHz
SID.TCPWM.4 TPWMENEXT Input trigger pulse width – 2/Fc – ns For all trigger events
SID.TCPWM.5 TPWMEXT Output trigger pulse width – 2/Fc – ns Minimum possible width of Overflow,
Underflow, and CC (Counter equals
Compare value) outputs
SID.TCPWM.5A TCRES Resolution of counter – 1/Fc – ns Minimum time between successive
counts
SID.TCPWM.5B PWMRES PWM resolution – 1/Fc – ns Minimum pulse width of PWM output
SID.TCPWM.5C QRES Quadrature inputs resolution – 1/Fc – ns Minimum pulse width between
quadrature-phase inputs
I2C
Table 15. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID153 FI2C1 Bit rate – – 1 Mbps –
UART
Table 16. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID162 FUART Bit rate – – 1 Mbps –
SPI
Table 17. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID166 FSPI SPI operating frequency – – 8 MHz –
(Master; 6X oversampling)
Memory
Table 20. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.MEM#4 TROWWRITE[10] Row (block) write time (erase and – – 20 ms –
program)
SID.MEM#3 TROWERASE[10] Row erase time – – 13 ms –
SID.MEM#8 TROWPROGRAM [10] Row program time after erase – – 7 ms –
SID178 TBULKERASE[10] Bulk erase time (128 KB) – – 35 ms –
SID180 TDEVPROG[10] Total device program time – – 25 seconds Guaranteed by
characterization
SID.MEM#6 FEND Flash endurance 100K – – cycles Guaranteed by
characterization
SID182 FRET1 Flash retention. TA 55 °C, 100 K 20 – – years Guaranteed by
P/E cycles characterization
SID182A FRET2 Flash retention. TA 85 °C, 10 K 10 – – years Guaranteed by
P/E cycles characterization
Note
10. It can take as much as 20 milliseconds to write to flash. During this time the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
System Resources
Power-on-Reset (POR) with Brown Out
Table 21. Imprecise Power On Reset (PRES)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID185 VRISEIPOR Rising trip voltage 0.80 – 1.50 V Guaranteed by
characterization
SID186 VFALLIPOR Falling trip voltage 0.75 – 1.4 V Guaranteed by
characterization
Table 22. Precise Power On Reset (POR)
SWD Interface
Table 23. SWD Interface Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.SWD#1 F_SWDCLK1 3.3 V VDDIO 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock
frequency
SID.SWD#2 F_SWDCLK2 1.8 V VDDIO 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock
frequency
SID.SWD#3 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns Guaranteed by
characterization
SID.SWD#4 T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns Guaranteed by
characterization
SID.SWD#5 T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns Guaranteed by
characterization
SID.SWD#6 T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns Guaranteed by
characterization
Power Down
Table 26. PD DC Specifications
Ordering Information
The EZ-PD CCG4 part numbers and features are listed in Table 29.
Table 29. EZ-PD CCG4 Ordering Information
Type-C PD Dead Battery Termination
Part Number Application TCPWM Role Package
Ports Spec# Termination Resistor
CYPD4125-40LQXIT Notebooks, desktops 1 4 PD2.0 Yes RP[11], RD[12], RD-DB[12] DRP 40-pin QFN
CYPD4225-40LQXIT Notebooks, desktops 2 4 PD2.0 Yes RP[11], RD[12], RD-DB[12] DRP 40-pin QFN
[11] [12] [12]
CYPD4126-40LQXIT Notebooks, desktops 1 2 PD3.0 Yes RP , RD , RD-DB DRP 40-pin QFN
CYPD4226-40LQXIT Notebooks, desktops 2 2 PD3.0 Yes RP[11], RD[12], RD-DB[12] DRP 40-pin QFN
CYPD4236-40LQXIT Docking station 2 2 PD3.0 No RP[11], RD[12] DRP 40-pin QFN
[11] [12] [12]
CYPD4126-24LQXIT Notebooks, desktops 1 2 PD3.0 Yes RP , RD , RD-DB DRP 24-pin QFN
CYPD4136-24LQXIT Docking station 1 2 PD3.0 No RP[11], RD[12] DRP 24-pin QFN
Notes
11. Termination resistor denoting a downstream facing port.
12. Termination resistor denoting an accessory or upstream facing port.
Packaging
Figure 9. 40-Pin QFN (6 × 6 × 0.6 mm), LR40A/LQ40A 4.6 × 4.6 E-PAD (Sawn) Package Outline, 001-80659
001-80659 *A
NOTES
DIMENSIONS
SYMBOL 1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN. NOM. MAX. 2. DIE THICKNESS ALLOWABLE IS 0.305 mm MAXIMUM(.012 INCHES MAXIMUM)
3. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. -1994.
A 0.60
4. THE PIN #1 IDENTIFIER MUST BE PLACED ON THE TOP SURFACE OF THE
A1 0.00 0.05
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF
A2 0.40 0.425
PACKAGE BODY.
A3 0.152 REF 5. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
D 4.00 BSC 7. APPLIED FOR EXPOSED PAD AND TERMINALS. EXCLUDE EMBEDDING PART
OF EXPOSED PAD FROM MEASURING.
D2 2.65 2.75 2.85
8. APPLIED ONLY TO TERMINALS.
E 4.00 BSC
9. JEDEC SPECIFICATION NO. REF: N.A.
E2 2.65 2.75 2.85
e 0.50 BSC
R 0.09
002-16934 *A
References and Links to Applications ■ AN95599 - Hardware Design Guidelines for EZ-PD™ CCG2
Collaterals ■ AN210403 - Hardware Design Guidelines for Dual Role Port
Applications Using EZ-PD™ USB Type-C Controllers
Knowledge Base Articles
■ AN210771 - Getting Started with EZ-PD™ CCG4
■ Key Differences Among EZ-PD™ CCG1, CCG2, CCG3 and
CCG4 - KBA210740 Reference Designs
■ Programming EZ-PD™ CCG2, EZ-PD™ CCG3 and EZ-PD™ ■ EZ-PD™ CCG2 Electronically Marked Cable Assembly
CCG4 Using PSoC® Programmer and MiniProg3 - KBA96477 (EMCA) Paddle Card Reference Design
■ CCGX Frequently Asked Questions (FAQs) - KBA97244 ■ EZ-PD™ CCG2 USB Type-C to DisplayPort Cable Solution
■ Handling Precautions for CY4501 CCG1 DVK - KBA210560 ■ CCG1 USB Type-C to DisplayPort Cable Solution
■ Cypress EZ-PD™ CCGx Hardware - KBA204102 ■ CCG1 USB Type-C to HDMI/DVI/VGA Adapter Solution
■ Difference between USB Type-C and USB-PD - KBA204033 ■ EZ-PD™ CCG2 USB Type-C to HDMI Adapter Solution
■ CCGx Programming Methods - KBA97271
■ CCG1 Electronically Marked Cable Assembly (EMCA) Paddle
■ Getting started with Cypress USB Type-C Products - Card Reference Design
KBA04071
■ CCG1 USB Type-C to Legacy USB Device Cable Paddle Card
■ Type-C to DisplayPort Cable Electrical Requirements Reference Schematics
■ Dead Battery Charging Implementation in USB Type-C ■ EZ-USB GX3 USB Type-C to Gigabit Ethernet Dongle
Solutions - KBA97273
■ EZ-PD™ CCG2 USB Type-C Monitor/Dock Solution
■ Termination Resistors Required for the USB Type-C Connector
– KBA97180 ■ CCG2 20W Power Adapter Reference Design
■ VBUS Bypass Capacitor Recommendation for Type-C Cable ■ CCG2 18W Power Adapter Reference Design
and Type-C to Legacy Cable/Adapter Assemblies – KBA97270
■ EZ-USB GX3 USB Type-A to Gigabit Ethernet Reference
■ Need for Regulator and Auxiliary Switch in Type-C to Design Kit
DisplayPort (DP) Cable Solution - KBA97274
Kits
■ Need for a USB Billboard Device in Type-C Solutions –
KBA97146 ■ CY4501 CCG1 Development Kit
■ CCG1 Devices in Type-C to Legacy Cable/Adapter Assemblies ■ CY4502 EZ-PD™ CCG2 Development Kit
– KBA97145
■ CY4531 EZ-PD CCG3 Evaluation Kit
■ Cypress USB Type-C Controller Supported Solutions –
KBA97179 ■ CY4541 EZ-PD™ CCG4 Evaluation Kit
■ Termination Resistors for Type-C to Legacy Ports – KBA97272 Datasheets
■ Handling Instructions for CY4502 CCG2 Development Kit – ■ CCG1 Datasheet: USB Type-C Port Controller with Power
KBA97916 Delivery
■ Thunderbolt™ Cable Application Using CCG3 Devices -
■ CYPD1120 Datasheet: USB Power Delivery Alternate Mode
KBA210976
Controller on Type-C
■ Power Adapter Application Using CCG3 Devices - KBA210975
■ CCG2: USB Type-C Port Controller Datasheet
■ Methods to Upgrade Firmware on CCG3 Devices - KBA210974
■ CCG3: USB Type-C Controller Datasheet
■ Device Flash Memory Size and Advantages - KBA210973
■ Applications of EZ-PD™ CCG4 - KBA210739
Application Notes
■ AN96527 - Designing USB Type-C Products Using Cypress’s
CCG1 Controllers
■ AN95615 - Designing USB 3.1 Type-C Cables Using EZ-PD™
CCG2
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