Switching Fets and Dead Time: Driver Ic Circuit

Switching FETs and Dead Time
I was looking though some old notes this week and stumbled on the day I learned about dead time. No this is not
that fatal moment we all trying to ignore but is a critical period of time when switching FETs on and off in a Half or Full
bridge.
I was looking through some old notes this week and stumbled upon the day I learned about dead time. No, this is
not that fatal moment we all try to ignore; it’s a period of time where switching FETs on and off in either a Half or Full
bridge is critical. So what is it, and why is the switching of FETs so important? When digital meets analogue circuits, there
is always some fun getting the results you want and Half and Full bridges are no exception. Although I’ll be looking at these
particular circuits, it’s fair to say the same ideas will also be useful for switching any device, such as turning a FET on and
off, with accurate timing and control.
Below I have set out the basics of one side of a bridge, but with some components removed so we can look at the
key features alone.
Driver IC Circuit
The circuit works by generating a square wave from the HI and LO outputs in the operate phase. This, in theory
means that only one device is on at a time and that point ‘A’ will go between 0 volts and +V. You will see that there are
two resistors connected to the gates of the FETs. These are specified by the datasheet as required. They limit the current
that flows between the driver IC and the FETs gate. The gate in these devices contains a small capacitor that is just part of
the function of the FET. So when the gate voltage ( Vgs ) swings between 0 and, say 15 volts, this capacitor needs to charge
up. Then it needs to discharge when the gate goes back to 0 volts. The driver ICs can switch rather high instantaneous
currents, but the resistor is there to limit this. I’ve also added zenor diodes, which is good practice as this protects the gate
voltage from going over the switching level (in this case 15 volts) or generating a negative voltage below -0.5. Lastly, I have
added an inductor (I) which is not really a fitted device, but will represent the PCB inductance between the bottom FET and
the 0 volt reference of the driver IC (in this example the driver side is connected separately to the bottom of the FET, but is
not always available in ICs of this type).
So what we should see if nothing is connected at ‘A’ is only a transition of voltage and no current passing from top
to bottom. However, we have two RC circuits formed by the capacitor in the FETs and the series resistors that are affecting
the gates of the FETs. What we see is one device slowly switching on as the other slowly switches off. At a mid point the
FETs are both partly switched on and current will flow. In the circuit I was testing at the time, I had 400Vdc across the
bridge and was getting 30 amps through the FETs for around 1nS—not good. This causes more issues than simply a large
current surge and EMC. The large current in the PCB and my invisible inductor causes a voltage to appear at the source of
the bottom FET. This lifts the COM connection, and in this device has the effect of starting to switch the FET off again (Vgs
reduces). You will also notice ringing noise in the circuit as the inductance starts to resonate.
New FET gate circuit
The old way of fixing this is to generate some dead time when the devices are both switched off enough,
preventing large current surges. This was done by changing the circuit that feeds the FET. First, we want to slow down the
charging of the FET when switching it on by increasing the resistance—in this case from 4R7 to 22R. Then to get a really
quick switch off time I use a bypass diode that allows the driver IC to quickly ground the gate of the FET. In some cases you
may still want a small resistor, for example 1R in series with this diode if the gate currents are large, but the diode alone
will normally do the job. In my circuit this reduced the current to less than 1 amp at the crossover and was acceptable at
the time.
Dead Time
This period of time as I said is called the “dead time” and allows for the reduction of this short circuit effect that
happens in circuits like this. However, times have evolved and dead time control is now built into driver ICs and even
microcontrollers. It would not be too hard to see that in the above circuit if the HI and LO signals have a short pause
between transitions allowing control of the timing of the gates and the switching of the FETs. Dead time is not
symmetrical, and this can be seen in modern dead time control devices. The circuit above will have different current
surges when going from high to low and low to high. So the new devices use a pre and post-timer that can be separately
configured. Below you can see a typical timing arrangement for this taken from a Microchip controller.
Pre and Post Timing
Here it’s easy to see the original signal (PWM Generator) that feeds the dead time control circuit. With a time set
to zero, the high and low sides switch together. Then adjusting these pre and post-times allows for asymmetric dead
times. This allows for more efficient control and will allow you to reduce losses in circuit designs. You are also reducing
noise that can affect your EMC results. Dead time and controlling FET gate switching can make significant improvements
and modern devices are allowing increasingly better control.

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Switching FETs and Dead Time

New FET gate circuit

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